1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "qemu-common.h" 25 #if !defined(CONFIG_USER_ONLY) 26 #include "hw/loader.h" 27 #endif 28 #include "hw/arm/arm.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "kvm_arm.h" 32 #include "qapi/visitor.h" 33 34 static inline void set_feature(CPUARMState *env, int feature) 35 { 36 env->features |= 1ULL << feature; 37 } 38 39 static inline void unset_feature(CPUARMState *env, int feature) 40 { 41 env->features &= ~(1ULL << feature); 42 } 43 44 #ifndef CONFIG_USER_ONLY 45 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 46 { 47 ARMCPU *cpu = arm_env_get_cpu(env); 48 49 /* Number of cores is in [25:24]; otherwise we RAZ */ 50 return (cpu->core_count - 1) << 24; 51 } 52 #endif 53 54 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { 55 #ifndef CONFIG_USER_ONLY 56 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, 57 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, 58 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 59 .writefn = arm_cp_write_ignore }, 60 { .name = "L2CTLR", 61 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, 62 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 63 .writefn = arm_cp_write_ignore }, 64 #endif 65 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, 66 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, 67 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 68 { .name = "L2ECTLR", 69 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, 70 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 71 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, 72 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, 73 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 74 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 75 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, 76 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 77 { .name = "CPUACTLR", 78 .cp = 15, .opc1 = 0, .crm = 15, 79 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 80 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 81 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, 82 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 83 { .name = "CPUECTLR", 84 .cp = 15, .opc1 = 1, .crm = 15, 85 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 86 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, 87 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, 88 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 89 { .name = "CPUMERRSR", 90 .cp = 15, .opc1 = 2, .crm = 15, 91 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 92 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, 93 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, 94 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 95 { .name = "L2MERRSR", 96 .cp = 15, .opc1 = 3, .crm = 15, 97 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 98 REGINFO_SENTINEL 99 }; 100 101 static void aarch64_a57_initfn(Object *obj) 102 { 103 ARMCPU *cpu = ARM_CPU(obj); 104 105 cpu->dtb_compatible = "arm,cortex-a57"; 106 set_feature(&cpu->env, ARM_FEATURE_V8); 107 set_feature(&cpu->env, ARM_FEATURE_VFP4); 108 set_feature(&cpu->env, ARM_FEATURE_NEON); 109 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 110 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 111 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 112 set_feature(&cpu->env, ARM_FEATURE_EL2); 113 set_feature(&cpu->env, ARM_FEATURE_EL3); 114 set_feature(&cpu->env, ARM_FEATURE_PMU); 115 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 116 cpu->midr = 0x411fd070; 117 cpu->revidr = 0x00000000; 118 cpu->reset_fpsid = 0x41034070; 119 cpu->isar.mvfr0 = 0x10110222; 120 cpu->isar.mvfr1 = 0x12111111; 121 cpu->isar.mvfr2 = 0x00000043; 122 cpu->ctr = 0x8444c004; 123 cpu->reset_sctlr = 0x00c50838; 124 cpu->id_pfr0 = 0x00000131; 125 cpu->id_pfr1 = 0x00011011; 126 cpu->id_dfr0 = 0x03010066; 127 cpu->id_afr0 = 0x00000000; 128 cpu->id_mmfr0 = 0x10101105; 129 cpu->id_mmfr1 = 0x40000000; 130 cpu->id_mmfr2 = 0x01260000; 131 cpu->id_mmfr3 = 0x02102211; 132 cpu->isar.id_isar0 = 0x02101110; 133 cpu->isar.id_isar1 = 0x13112111; 134 cpu->isar.id_isar2 = 0x21232042; 135 cpu->isar.id_isar3 = 0x01112131; 136 cpu->isar.id_isar4 = 0x00011142; 137 cpu->isar.id_isar5 = 0x00011121; 138 cpu->isar.id_isar6 = 0; 139 cpu->isar.id_aa64pfr0 = 0x00002222; 140 cpu->id_aa64dfr0 = 0x10305106; 141 cpu->isar.id_aa64isar0 = 0x00011120; 142 cpu->isar.id_aa64mmfr0 = 0x00001124; 143 cpu->dbgdidr = 0x3516d000; 144 cpu->clidr = 0x0a200023; 145 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 146 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 147 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 148 cpu->dcz_blocksize = 4; /* 64 bytes */ 149 cpu->gic_num_lrs = 4; 150 cpu->gic_vpribits = 5; 151 cpu->gic_vprebits = 5; 152 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 153 } 154 155 static void aarch64_a53_initfn(Object *obj) 156 { 157 ARMCPU *cpu = ARM_CPU(obj); 158 159 cpu->dtb_compatible = "arm,cortex-a53"; 160 set_feature(&cpu->env, ARM_FEATURE_V8); 161 set_feature(&cpu->env, ARM_FEATURE_VFP4); 162 set_feature(&cpu->env, ARM_FEATURE_NEON); 163 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 164 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 165 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 166 set_feature(&cpu->env, ARM_FEATURE_EL2); 167 set_feature(&cpu->env, ARM_FEATURE_EL3); 168 set_feature(&cpu->env, ARM_FEATURE_PMU); 169 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 170 cpu->midr = 0x410fd034; 171 cpu->revidr = 0x00000000; 172 cpu->reset_fpsid = 0x41034070; 173 cpu->isar.mvfr0 = 0x10110222; 174 cpu->isar.mvfr1 = 0x12111111; 175 cpu->isar.mvfr2 = 0x00000043; 176 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 177 cpu->reset_sctlr = 0x00c50838; 178 cpu->id_pfr0 = 0x00000131; 179 cpu->id_pfr1 = 0x00011011; 180 cpu->id_dfr0 = 0x03010066; 181 cpu->id_afr0 = 0x00000000; 182 cpu->id_mmfr0 = 0x10101105; 183 cpu->id_mmfr1 = 0x40000000; 184 cpu->id_mmfr2 = 0x01260000; 185 cpu->id_mmfr3 = 0x02102211; 186 cpu->isar.id_isar0 = 0x02101110; 187 cpu->isar.id_isar1 = 0x13112111; 188 cpu->isar.id_isar2 = 0x21232042; 189 cpu->isar.id_isar3 = 0x01112131; 190 cpu->isar.id_isar4 = 0x00011142; 191 cpu->isar.id_isar5 = 0x00011121; 192 cpu->isar.id_isar6 = 0; 193 cpu->isar.id_aa64pfr0 = 0x00002222; 194 cpu->id_aa64dfr0 = 0x10305106; 195 cpu->isar.id_aa64isar0 = 0x00011120; 196 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 197 cpu->dbgdidr = 0x3516d000; 198 cpu->clidr = 0x0a200023; 199 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 200 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 201 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 202 cpu->dcz_blocksize = 4; /* 64 bytes */ 203 cpu->gic_num_lrs = 4; 204 cpu->gic_vpribits = 5; 205 cpu->gic_vprebits = 5; 206 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 207 } 208 209 static void aarch64_a72_initfn(Object *obj) 210 { 211 ARMCPU *cpu = ARM_CPU(obj); 212 213 cpu->dtb_compatible = "arm,cortex-a72"; 214 set_feature(&cpu->env, ARM_FEATURE_V8); 215 set_feature(&cpu->env, ARM_FEATURE_VFP4); 216 set_feature(&cpu->env, ARM_FEATURE_NEON); 217 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 218 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 219 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 220 set_feature(&cpu->env, ARM_FEATURE_EL2); 221 set_feature(&cpu->env, ARM_FEATURE_EL3); 222 set_feature(&cpu->env, ARM_FEATURE_PMU); 223 cpu->midr = 0x410fd083; 224 cpu->revidr = 0x00000000; 225 cpu->reset_fpsid = 0x41034080; 226 cpu->isar.mvfr0 = 0x10110222; 227 cpu->isar.mvfr1 = 0x12111111; 228 cpu->isar.mvfr2 = 0x00000043; 229 cpu->ctr = 0x8444c004; 230 cpu->reset_sctlr = 0x00c50838; 231 cpu->id_pfr0 = 0x00000131; 232 cpu->id_pfr1 = 0x00011011; 233 cpu->id_dfr0 = 0x03010066; 234 cpu->id_afr0 = 0x00000000; 235 cpu->id_mmfr0 = 0x10201105; 236 cpu->id_mmfr1 = 0x40000000; 237 cpu->id_mmfr2 = 0x01260000; 238 cpu->id_mmfr3 = 0x02102211; 239 cpu->isar.id_isar0 = 0x02101110; 240 cpu->isar.id_isar1 = 0x13112111; 241 cpu->isar.id_isar2 = 0x21232042; 242 cpu->isar.id_isar3 = 0x01112131; 243 cpu->isar.id_isar4 = 0x00011142; 244 cpu->isar.id_isar5 = 0x00011121; 245 cpu->isar.id_aa64pfr0 = 0x00002222; 246 cpu->id_aa64dfr0 = 0x10305106; 247 cpu->isar.id_aa64isar0 = 0x00011120; 248 cpu->isar.id_aa64mmfr0 = 0x00001124; 249 cpu->dbgdidr = 0x3516d000; 250 cpu->clidr = 0x0a200023; 251 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 252 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 253 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ 254 cpu->dcz_blocksize = 4; /* 64 bytes */ 255 cpu->gic_num_lrs = 4; 256 cpu->gic_vpribits = 5; 257 cpu->gic_vprebits = 5; 258 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 259 } 260 261 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, 262 void *opaque, Error **errp) 263 { 264 ARMCPU *cpu = ARM_CPU(obj); 265 visit_type_uint32(v, name, &cpu->sve_max_vq, errp); 266 } 267 268 static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, 269 void *opaque, Error **errp) 270 { 271 ARMCPU *cpu = ARM_CPU(obj); 272 Error *err = NULL; 273 274 visit_type_uint32(v, name, &cpu->sve_max_vq, &err); 275 276 if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) { 277 error_setg(&err, "unsupported SVE vector length"); 278 error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n", 279 ARM_MAX_VQ); 280 } 281 error_propagate(errp, err); 282 } 283 284 #ifdef CONFIG_USER_ONLY 285 static void cpu_max_get_packey(Object *obj, Visitor *v, const char *name, 286 void *opaque, Error **errp) 287 { 288 ARMCPU *cpu = ARM_CPU(obj); 289 const uint64_t *bit = opaque; 290 bool enabled = (cpu->env.cp15.sctlr_el[1] & *bit) != 0; 291 292 visit_type_bool(v, name, &enabled, errp); 293 } 294 295 static void cpu_max_set_packey(Object *obj, Visitor *v, const char *name, 296 void *opaque, Error **errp) 297 { 298 ARMCPU *cpu = ARM_CPU(obj); 299 Error *err = NULL; 300 const uint64_t *bit = opaque; 301 bool enabled; 302 303 visit_type_bool(v, name, &enabled, errp); 304 305 if (!err) { 306 if (enabled) { 307 cpu->env.cp15.sctlr_el[1] |= *bit; 308 } else { 309 cpu->env.cp15.sctlr_el[1] &= ~*bit; 310 } 311 } 312 error_propagate(errp, err); 313 } 314 #endif 315 316 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 317 * otherwise, a CPU with as many features enabled as our emulation supports. 318 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; 319 * this only needs to handle 64 bits. 320 */ 321 static void aarch64_max_initfn(Object *obj) 322 { 323 ARMCPU *cpu = ARM_CPU(obj); 324 325 if (kvm_enabled()) { 326 kvm_arm_set_cpu_features_from_host(cpu); 327 } else { 328 uint64_t t; 329 uint32_t u; 330 aarch64_a57_initfn(obj); 331 332 t = cpu->isar.id_aa64isar0; 333 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ 334 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); 335 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ 336 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); 337 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); 338 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); 339 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); 340 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); 341 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); 342 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); 343 cpu->isar.id_aa64isar0 = t; 344 345 t = cpu->isar.id_aa64isar1; 346 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); 347 t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ 348 t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); 349 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); 350 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); 351 cpu->isar.id_aa64isar1 = t; 352 353 t = cpu->isar.id_aa64pfr0; 354 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); 355 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); 356 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); 357 cpu->isar.id_aa64pfr0 = t; 358 359 t = cpu->isar.id_aa64mmfr1; 360 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ 361 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); 362 cpu->isar.id_aa64mmfr1 = t; 363 364 /* Replicate the same data to the 32-bit id registers. */ 365 u = cpu->isar.id_isar5; 366 u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ 367 u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); 368 u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); 369 u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); 370 u = FIELD_DP32(u, ID_ISAR5, RDM, 1); 371 u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); 372 cpu->isar.id_isar5 = u; 373 374 u = cpu->isar.id_isar6; 375 u = FIELD_DP32(u, ID_ISAR6, DP, 1); 376 cpu->isar.id_isar6 = u; 377 378 /* 379 * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, 380 * so do not set MVFR1.FPHP. Strictly speaking this is not legal, 381 * but it is also not legal to enable SVE without support for FP16, 382 * and enabling SVE in system mode is more useful in the short term. 383 */ 384 385 #ifdef CONFIG_USER_ONLY 386 /* For usermode -cpu max we can use a larger and more efficient DCZ 387 * blocksize since we don't have to follow what the hardware does. 388 */ 389 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 390 cpu->dcz_blocksize = 7; /* 512 bytes */ 391 392 /* 393 * Note that Linux will enable enable all of the keys at once. 394 * But doing it this way will allow experimentation beyond that. 395 */ 396 { 397 static const uint64_t apia_bit = SCTLR_EnIA; 398 static const uint64_t apib_bit = SCTLR_EnIB; 399 static const uint64_t apda_bit = SCTLR_EnDA; 400 static const uint64_t apdb_bit = SCTLR_EnDB; 401 402 object_property_add(obj, "apia", "bool", cpu_max_get_packey, 403 cpu_max_set_packey, NULL, 404 (void *)&apia_bit, &error_fatal); 405 object_property_add(obj, "apib", "bool", cpu_max_get_packey, 406 cpu_max_set_packey, NULL, 407 (void *)&apib_bit, &error_fatal); 408 object_property_add(obj, "apda", "bool", cpu_max_get_packey, 409 cpu_max_set_packey, NULL, 410 (void *)&apda_bit, &error_fatal); 411 object_property_add(obj, "apdb", "bool", cpu_max_get_packey, 412 cpu_max_set_packey, NULL, 413 (void *)&apdb_bit, &error_fatal); 414 415 /* Enable all PAC keys by default. */ 416 cpu->env.cp15.sctlr_el[1] |= SCTLR_EnIA | SCTLR_EnIB; 417 cpu->env.cp15.sctlr_el[1] |= SCTLR_EnDA | SCTLR_EnDB; 418 } 419 #endif 420 421 cpu->sve_max_vq = ARM_MAX_VQ; 422 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq, 423 cpu_max_set_sve_vq, NULL, NULL, &error_fatal); 424 } 425 } 426 427 struct ARMCPUInfo { 428 const char *name; 429 void (*initfn)(Object *obj); 430 void (*class_init)(ObjectClass *oc, void *data); 431 }; 432 433 static const ARMCPUInfo aarch64_cpus[] = { 434 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 435 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 436 { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, 437 { .name = "max", .initfn = aarch64_max_initfn }, 438 { .name = NULL } 439 }; 440 441 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 442 { 443 ARMCPU *cpu = ARM_CPU(obj); 444 445 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 446 } 447 448 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 449 { 450 ARMCPU *cpu = ARM_CPU(obj); 451 452 /* At this time, this property is only allowed if KVM is enabled. This 453 * restriction allows us to avoid fixing up functionality that assumes a 454 * uniform execution state like do_interrupt. 455 */ 456 if (!kvm_enabled()) { 457 error_setg(errp, "'aarch64' feature cannot be disabled " 458 "unless KVM is enabled"); 459 return; 460 } 461 462 if (value == false) { 463 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 464 } else { 465 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 466 } 467 } 468 469 static void aarch64_cpu_initfn(Object *obj) 470 { 471 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, 472 aarch64_cpu_set_aarch64, NULL); 473 object_property_set_description(obj, "aarch64", 474 "Set on/off to enable/disable aarch64 " 475 "execution state ", 476 NULL); 477 } 478 479 static void aarch64_cpu_finalizefn(Object *obj) 480 { 481 } 482 483 static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) 484 { 485 ARMCPU *cpu = ARM_CPU(cs); 486 /* It's OK to look at env for the current mode here, because it's 487 * never possible for an AArch64 TB to chain to an AArch32 TB. 488 * (Otherwise we would need to use synchronize_from_tb instead.) 489 */ 490 if (is_a64(&cpu->env)) { 491 cpu->env.pc = value; 492 } else { 493 cpu->env.regs[15] = value; 494 } 495 } 496 497 static gchar *aarch64_gdb_arch_name(CPUState *cs) 498 { 499 return g_strdup("aarch64"); 500 } 501 502 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 503 { 504 CPUClass *cc = CPU_CLASS(oc); 505 506 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 507 cc->set_pc = aarch64_cpu_set_pc; 508 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 509 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 510 cc->gdb_num_core_regs = 34; 511 cc->gdb_core_xml_file = "aarch64-core.xml"; 512 cc->gdb_arch_name = aarch64_gdb_arch_name; 513 } 514 515 static void aarch64_cpu_instance_init(Object *obj) 516 { 517 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 518 519 acc->info->initfn(obj); 520 arm_cpu_post_init(obj); 521 } 522 523 static void cpu_register_class_init(ObjectClass *oc, void *data) 524 { 525 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 526 527 acc->info = data; 528 } 529 530 static void aarch64_cpu_register(const ARMCPUInfo *info) 531 { 532 TypeInfo type_info = { 533 .parent = TYPE_AARCH64_CPU, 534 .instance_size = sizeof(ARMCPU), 535 .instance_init = aarch64_cpu_instance_init, 536 .class_size = sizeof(ARMCPUClass), 537 .class_init = info->class_init ?: cpu_register_class_init, 538 .class_data = (void *)info, 539 }; 540 541 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 542 type_register(&type_info); 543 g_free((void *)type_info.name); 544 } 545 546 static const TypeInfo aarch64_cpu_type_info = { 547 .name = TYPE_AARCH64_CPU, 548 .parent = TYPE_ARM_CPU, 549 .instance_size = sizeof(ARMCPU), 550 .instance_init = aarch64_cpu_initfn, 551 .instance_finalize = aarch64_cpu_finalizefn, 552 .abstract = true, 553 .class_size = sizeof(AArch64CPUClass), 554 .class_init = aarch64_cpu_class_init, 555 }; 556 557 static void aarch64_cpu_register_types(void) 558 { 559 const ARMCPUInfo *info = aarch64_cpus; 560 561 type_register_static(&aarch64_cpu_type_info); 562 563 while (info->name) { 564 aarch64_cpu_register(info); 565 info++; 566 } 567 } 568 569 type_init(aarch64_cpu_register_types) 570