1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #ifdef CONFIG_TCG 25 #include "hw/core/tcg-cpu-ops.h" 26 #endif /* CONFIG_TCG */ 27 #include "qemu/module.h" 28 #if !defined(CONFIG_USER_ONLY) 29 #include "hw/loader.h" 30 #endif 31 #include "sysemu/kvm.h" 32 #include "sysemu/hvf.h" 33 #include "kvm_arm.h" 34 #include "hvf_arm.h" 35 #include "qapi/visitor.h" 36 #include "hw/qdev-properties.h" 37 #include "internals.h" 38 39 static void aarch64_a35_initfn(Object *obj) 40 { 41 ARMCPU *cpu = ARM_CPU(obj); 42 43 cpu->dtb_compatible = "arm,cortex-a35"; 44 set_feature(&cpu->env, ARM_FEATURE_V8); 45 set_feature(&cpu->env, ARM_FEATURE_NEON); 46 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 47 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 48 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 49 set_feature(&cpu->env, ARM_FEATURE_EL2); 50 set_feature(&cpu->env, ARM_FEATURE_EL3); 51 set_feature(&cpu->env, ARM_FEATURE_PMU); 52 53 /* From B2.2 AArch64 identification registers. */ 54 cpu->midr = 0x411fd040; 55 cpu->revidr = 0; 56 cpu->ctr = 0x84448004; 57 cpu->isar.id_pfr0 = 0x00000131; 58 cpu->isar.id_pfr1 = 0x00011011; 59 cpu->isar.id_dfr0 = 0x03010066; 60 cpu->id_afr0 = 0; 61 cpu->isar.id_mmfr0 = 0x10201105; 62 cpu->isar.id_mmfr1 = 0x40000000; 63 cpu->isar.id_mmfr2 = 0x01260000; 64 cpu->isar.id_mmfr3 = 0x02102211; 65 cpu->isar.id_isar0 = 0x02101110; 66 cpu->isar.id_isar1 = 0x13112111; 67 cpu->isar.id_isar2 = 0x21232042; 68 cpu->isar.id_isar3 = 0x01112131; 69 cpu->isar.id_isar4 = 0x00011142; 70 cpu->isar.id_isar5 = 0x00011121; 71 cpu->isar.id_aa64pfr0 = 0x00002222; 72 cpu->isar.id_aa64pfr1 = 0; 73 cpu->isar.id_aa64dfr0 = 0x10305106; 74 cpu->isar.id_aa64dfr1 = 0; 75 cpu->isar.id_aa64isar0 = 0x00011120; 76 cpu->isar.id_aa64isar1 = 0; 77 cpu->isar.id_aa64mmfr0 = 0x00101122; 78 cpu->isar.id_aa64mmfr1 = 0; 79 cpu->clidr = 0x0a200023; 80 cpu->dcz_blocksize = 4; 81 82 /* From B2.4 AArch64 Virtual Memory control registers */ 83 cpu->reset_sctlr = 0x00c50838; 84 85 /* From B2.10 AArch64 performance monitor registers */ 86 cpu->isar.reset_pmcr_el0 = 0x410a3000; 87 88 /* From B2.29 Cache ID registers */ 89 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 90 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 91 cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */ 92 93 /* From B3.5 VGIC Type register */ 94 cpu->gic_num_lrs = 4; 95 cpu->gic_vpribits = 5; 96 cpu->gic_vprebits = 5; 97 cpu->gic_pribits = 5; 98 99 /* From C6.4 Debug ID Register */ 100 cpu->isar.dbgdidr = 0x3516d000; 101 /* From C6.5 Debug Device ID Register */ 102 cpu->isar.dbgdevid = 0x00110f13; 103 /* From C6.6 Debug Device ID Register 1 */ 104 cpu->isar.dbgdevid1 = 0x2; 105 106 /* From Cortex-A35 SIMD and Floating-point Support r1p0 */ 107 /* From 3.2 AArch32 register summary */ 108 cpu->reset_fpsid = 0x41034043; 109 110 /* From 2.2 AArch64 register summary */ 111 cpu->isar.mvfr0 = 0x10110222; 112 cpu->isar.mvfr1 = 0x12111111; 113 cpu->isar.mvfr2 = 0x00000043; 114 115 /* These values are the same with A53/A57/A72. */ 116 define_cortex_a72_a57_a53_cp_reginfo(cpu); 117 } 118 119 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) 120 { 121 /* 122 * If any vector lengths are explicitly enabled with sve<N> properties, 123 * then all other lengths are implicitly disabled. If sve-max-vq is 124 * specified then it is the same as explicitly enabling all lengths 125 * up to and including the specified maximum, which means all larger 126 * lengths will be implicitly disabled. If no sve<N> properties 127 * are enabled and sve-max-vq is not specified, then all lengths not 128 * explicitly disabled will be enabled. Additionally, all power-of-two 129 * vector lengths less than the maximum enabled length will be 130 * automatically enabled and all vector lengths larger than the largest 131 * disabled power-of-two vector length will be automatically disabled. 132 * Errors are generated if the user provided input that interferes with 133 * any of the above. Finally, if SVE is not disabled, then at least one 134 * vector length must be enabled. 135 */ 136 uint32_t vq_map = cpu->sve_vq.map; 137 uint32_t vq_init = cpu->sve_vq.init; 138 uint32_t vq_supported; 139 uint32_t vq_mask = 0; 140 uint32_t tmp, vq, max_vq = 0; 141 142 /* 143 * CPU models specify a set of supported vector lengths which are 144 * enabled by default. Attempting to enable any vector length not set 145 * in the supported bitmap results in an error. When KVM is enabled we 146 * fetch the supported bitmap from the host. 147 */ 148 if (kvm_enabled()) { 149 if (kvm_arm_sve_supported()) { 150 cpu->sve_vq.supported = kvm_arm_sve_get_vls(CPU(cpu)); 151 vq_supported = cpu->sve_vq.supported; 152 } else { 153 assert(!cpu_isar_feature(aa64_sve, cpu)); 154 vq_supported = 0; 155 } 156 } else { 157 vq_supported = cpu->sve_vq.supported; 158 } 159 160 /* 161 * Process explicit sve<N> properties. 162 * From the properties, sve_vq_map<N> implies sve_vq_init<N>. 163 * Check first for any sve<N> enabled. 164 */ 165 if (vq_map != 0) { 166 max_vq = 32 - clz32(vq_map); 167 vq_mask = MAKE_64BIT_MASK(0, max_vq); 168 169 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { 170 error_setg(errp, "cannot enable sve%d", max_vq * 128); 171 error_append_hint(errp, "sve%d is larger than the maximum vector " 172 "length, sve-max-vq=%d (%d bits)\n", 173 max_vq * 128, cpu->sve_max_vq, 174 cpu->sve_max_vq * 128); 175 return; 176 } 177 178 if (kvm_enabled()) { 179 /* 180 * For KVM we have to automatically enable all supported unitialized 181 * lengths, even when the smaller lengths are not all powers-of-two. 182 */ 183 vq_map |= vq_supported & ~vq_init & vq_mask; 184 } else { 185 /* Propagate enabled bits down through required powers-of-two. */ 186 vq_map |= SVE_VQ_POW2_MAP & ~vq_init & vq_mask; 187 } 188 } else if (cpu->sve_max_vq == 0) { 189 /* 190 * No explicit bits enabled, and no implicit bits from sve-max-vq. 191 */ 192 if (!cpu_isar_feature(aa64_sve, cpu)) { 193 /* SVE is disabled and so are all vector lengths. Good. */ 194 return; 195 } 196 197 if (kvm_enabled()) { 198 /* Disabling a supported length disables all larger lengths. */ 199 tmp = vq_init & vq_supported; 200 } else { 201 /* Disabling a power-of-two disables all larger lengths. */ 202 tmp = vq_init & SVE_VQ_POW2_MAP; 203 } 204 vq = ctz32(tmp) + 1; 205 206 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 207 vq_mask = MAKE_64BIT_MASK(0, max_vq); 208 vq_map = vq_supported & ~vq_init & vq_mask; 209 210 if (max_vq == 0 || vq_map == 0) { 211 error_setg(errp, "cannot disable sve%d", vq * 128); 212 error_append_hint(errp, "Disabling sve%d results in all " 213 "vector lengths being disabled.\n", 214 vq * 128); 215 error_append_hint(errp, "With SVE enabled, at least one " 216 "vector length must be enabled.\n"); 217 return; 218 } 219 220 max_vq = 32 - clz32(vq_map); 221 vq_mask = MAKE_64BIT_MASK(0, max_vq); 222 } 223 224 /* 225 * Process the sve-max-vq property. 226 * Note that we know from the above that no bit above 227 * sve-max-vq is currently set. 228 */ 229 if (cpu->sve_max_vq != 0) { 230 max_vq = cpu->sve_max_vq; 231 vq_mask = MAKE_64BIT_MASK(0, max_vq); 232 233 if (vq_init & ~vq_map & (1 << (max_vq - 1))) { 234 error_setg(errp, "cannot disable sve%d", max_vq * 128); 235 error_append_hint(errp, "The maximum vector length must be " 236 "enabled, sve-max-vq=%d (%d bits)\n", 237 max_vq, max_vq * 128); 238 return; 239 } 240 241 /* Set all bits not explicitly set within sve-max-vq. */ 242 vq_map |= ~vq_init & vq_mask; 243 } 244 245 /* 246 * We should know what max-vq is now. Also, as we're done 247 * manipulating sve-vq-map, we ensure any bits above max-vq 248 * are clear, just in case anybody looks. 249 */ 250 assert(max_vq != 0); 251 assert(vq_mask != 0); 252 vq_map &= vq_mask; 253 254 /* Ensure the set of lengths matches what is supported. */ 255 tmp = vq_map ^ (vq_supported & vq_mask); 256 if (tmp) { 257 vq = 32 - clz32(tmp); 258 if (vq_map & (1 << (vq - 1))) { 259 if (cpu->sve_max_vq) { 260 error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq); 261 error_append_hint(errp, "This CPU does not support " 262 "the vector length %d-bits.\n", vq * 128); 263 error_append_hint(errp, "It may not be possible to use " 264 "sve-max-vq with this CPU. Try " 265 "using only sve<N> properties.\n"); 266 } else { 267 error_setg(errp, "cannot enable sve%d", vq * 128); 268 if (vq_supported) { 269 error_append_hint(errp, "This CPU does not support " 270 "the vector length %d-bits.\n", vq * 128); 271 } else { 272 error_append_hint(errp, "SVE not supported by KVM " 273 "on this host\n"); 274 } 275 } 276 return; 277 } else { 278 if (kvm_enabled()) { 279 error_setg(errp, "cannot disable sve%d", vq * 128); 280 error_append_hint(errp, "The KVM host requires all " 281 "supported vector lengths smaller " 282 "than %d bits to also be enabled.\n", 283 max_vq * 128); 284 return; 285 } else { 286 /* Ensure all required powers-of-two are enabled. */ 287 tmp = SVE_VQ_POW2_MAP & vq_mask & ~vq_map; 288 if (tmp) { 289 vq = 32 - clz32(tmp); 290 error_setg(errp, "cannot disable sve%d", vq * 128); 291 error_append_hint(errp, "sve%d is required as it " 292 "is a power-of-two length smaller " 293 "than the maximum, sve%d\n", 294 vq * 128, max_vq * 128); 295 return; 296 } 297 } 298 } 299 } 300 301 /* 302 * Now that we validated all our vector lengths, the only question 303 * left to answer is if we even want SVE at all. 304 */ 305 if (!cpu_isar_feature(aa64_sve, cpu)) { 306 error_setg(errp, "cannot enable sve%d", max_vq * 128); 307 error_append_hint(errp, "SVE must be enabled to enable vector " 308 "lengths.\n"); 309 error_append_hint(errp, "Add sve=on to the CPU property list.\n"); 310 return; 311 } 312 313 /* From now on sve_max_vq is the actual maximum supported length. */ 314 cpu->sve_max_vq = max_vq; 315 cpu->sve_vq.map = vq_map; 316 } 317 318 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, 319 void *opaque, Error **errp) 320 { 321 ARMCPU *cpu = ARM_CPU(obj); 322 uint32_t value; 323 324 /* All vector lengths are disabled when SVE is off. */ 325 if (!cpu_isar_feature(aa64_sve, cpu)) { 326 value = 0; 327 } else { 328 value = cpu->sve_max_vq; 329 } 330 visit_type_uint32(v, name, &value, errp); 331 } 332 333 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, 334 void *opaque, Error **errp) 335 { 336 ARMCPU *cpu = ARM_CPU(obj); 337 uint32_t max_vq; 338 339 if (!visit_type_uint32(v, name, &max_vq, errp)) { 340 return; 341 } 342 343 if (kvm_enabled() && !kvm_arm_sve_supported()) { 344 error_setg(errp, "cannot set sve-max-vq"); 345 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 346 return; 347 } 348 349 if (max_vq == 0 || max_vq > ARM_MAX_VQ) { 350 error_setg(errp, "unsupported SVE vector length"); 351 error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", 352 ARM_MAX_VQ); 353 return; 354 } 355 356 cpu->sve_max_vq = max_vq; 357 } 358 359 /* 360 * Note that cpu_arm_{get,set}_vq cannot use the simpler 361 * object_property_add_bool interface because they make use of the 362 * contents of "name" to determine which bit on which to operate. 363 */ 364 static void cpu_arm_get_vq(Object *obj, Visitor *v, const char *name, 365 void *opaque, Error **errp) 366 { 367 ARMCPU *cpu = ARM_CPU(obj); 368 ARMVQMap *vq_map = opaque; 369 uint32_t vq = atoi(&name[3]) / 128; 370 bool sve = vq_map == &cpu->sve_vq; 371 bool value; 372 373 /* All vector lengths are disabled when feature is off. */ 374 if (sve 375 ? !cpu_isar_feature(aa64_sve, cpu) 376 : !cpu_isar_feature(aa64_sme, cpu)) { 377 value = false; 378 } else { 379 value = extract32(vq_map->map, vq - 1, 1); 380 } 381 visit_type_bool(v, name, &value, errp); 382 } 383 384 static void cpu_arm_set_vq(Object *obj, Visitor *v, const char *name, 385 void *opaque, Error **errp) 386 { 387 ARMVQMap *vq_map = opaque; 388 uint32_t vq = atoi(&name[3]) / 128; 389 bool value; 390 391 if (!visit_type_bool(v, name, &value, errp)) { 392 return; 393 } 394 395 vq_map->map = deposit32(vq_map->map, vq - 1, 1, value); 396 vq_map->init |= 1 << (vq - 1); 397 } 398 399 static bool cpu_arm_get_sve(Object *obj, Error **errp) 400 { 401 ARMCPU *cpu = ARM_CPU(obj); 402 return cpu_isar_feature(aa64_sve, cpu); 403 } 404 405 static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) 406 { 407 ARMCPU *cpu = ARM_CPU(obj); 408 uint64_t t; 409 410 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 411 error_setg(errp, "'sve' feature not supported by KVM on this host"); 412 return; 413 } 414 415 t = cpu->isar.id_aa64pfr0; 416 t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); 417 cpu->isar.id_aa64pfr0 = t; 418 } 419 420 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) 421 { 422 uint32_t vq_map = cpu->sme_vq.map; 423 uint32_t vq_init = cpu->sme_vq.init; 424 uint32_t vq_supported = cpu->sme_vq.supported; 425 uint32_t vq; 426 427 if (vq_map == 0) { 428 if (!cpu_isar_feature(aa64_sme, cpu)) { 429 cpu->isar.id_aa64smfr0 = 0; 430 return; 431 } 432 433 /* TODO: KVM will require limitations via SMCR_EL2. */ 434 vq_map = vq_supported & ~vq_init; 435 436 if (vq_map == 0) { 437 vq = ctz32(vq_supported) + 1; 438 error_setg(errp, "cannot disable sme%d", vq * 128); 439 error_append_hint(errp, "All SME vector lengths are disabled.\n"); 440 error_append_hint(errp, "With SME enabled, at least one " 441 "vector length must be enabled.\n"); 442 return; 443 } 444 } else { 445 if (!cpu_isar_feature(aa64_sme, cpu)) { 446 vq = 32 - clz32(vq_map); 447 error_setg(errp, "cannot enable sme%d", vq * 128); 448 error_append_hint(errp, "SME must be enabled to enable " 449 "vector lengths.\n"); 450 error_append_hint(errp, "Add sme=on to the CPU property list.\n"); 451 return; 452 } 453 /* TODO: KVM will require limitations via SMCR_EL2. */ 454 } 455 456 cpu->sme_vq.map = vq_map; 457 } 458 459 static bool cpu_arm_get_sme(Object *obj, Error **errp) 460 { 461 ARMCPU *cpu = ARM_CPU(obj); 462 return cpu_isar_feature(aa64_sme, cpu); 463 } 464 465 static void cpu_arm_set_sme(Object *obj, bool value, Error **errp) 466 { 467 ARMCPU *cpu = ARM_CPU(obj); 468 uint64_t t; 469 470 t = cpu->isar.id_aa64pfr1; 471 t = FIELD_DP64(t, ID_AA64PFR1, SME, value); 472 cpu->isar.id_aa64pfr1 = t; 473 } 474 475 static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp) 476 { 477 ARMCPU *cpu = ARM_CPU(obj); 478 return cpu_isar_feature(aa64_sme, cpu) && 479 cpu_isar_feature(aa64_sme_fa64, cpu); 480 } 481 482 static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp) 483 { 484 ARMCPU *cpu = ARM_CPU(obj); 485 uint64_t t; 486 487 t = cpu->isar.id_aa64smfr0; 488 t = FIELD_DP64(t, ID_AA64SMFR0, FA64, value); 489 cpu->isar.id_aa64smfr0 = t; 490 } 491 492 #ifdef CONFIG_USER_ONLY 493 /* Mirror linux /proc/sys/abi/{sve,sme}_default_vector_length. */ 494 static void cpu_arm_set_default_vec_len(Object *obj, Visitor *v, 495 const char *name, void *opaque, 496 Error **errp) 497 { 498 uint32_t *ptr_default_vq = opaque; 499 int32_t default_len, default_vq, remainder; 500 501 if (!visit_type_int32(v, name, &default_len, errp)) { 502 return; 503 } 504 505 /* Undocumented, but the kernel allows -1 to indicate "maximum". */ 506 if (default_len == -1) { 507 *ptr_default_vq = ARM_MAX_VQ; 508 return; 509 } 510 511 default_vq = default_len / 16; 512 remainder = default_len % 16; 513 514 /* 515 * Note that the 512 max comes from include/uapi/asm/sve_context.h 516 * and is the maximum architectural width of ZCR_ELx.LEN. 517 */ 518 if (remainder || default_vq < 1 || default_vq > 512) { 519 ARMCPU *cpu = ARM_CPU(obj); 520 const char *which = 521 (ptr_default_vq == &cpu->sve_default_vq ? "sve" : "sme"); 522 523 error_setg(errp, "cannot set %s-default-vector-length", which); 524 if (remainder) { 525 error_append_hint(errp, "Vector length not a multiple of 16\n"); 526 } else if (default_vq < 1) { 527 error_append_hint(errp, "Vector length smaller than 16\n"); 528 } else { 529 error_append_hint(errp, "Vector length larger than %d\n", 530 512 * 16); 531 } 532 return; 533 } 534 535 *ptr_default_vq = default_vq; 536 } 537 538 static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v, 539 const char *name, void *opaque, 540 Error **errp) 541 { 542 uint32_t *ptr_default_vq = opaque; 543 int32_t value = *ptr_default_vq * 16; 544 545 visit_type_int32(v, name, &value, errp); 546 } 547 #endif 548 549 static void aarch64_add_sve_properties(Object *obj) 550 { 551 ARMCPU *cpu = ARM_CPU(obj); 552 uint32_t vq; 553 554 object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); 555 556 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 557 char name[8]; 558 sprintf(name, "sve%d", vq * 128); 559 object_property_add(obj, name, "bool", cpu_arm_get_vq, 560 cpu_arm_set_vq, NULL, &cpu->sve_vq); 561 } 562 563 #ifdef CONFIG_USER_ONLY 564 /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ 565 object_property_add(obj, "sve-default-vector-length", "int32", 566 cpu_arm_get_default_vec_len, 567 cpu_arm_set_default_vec_len, NULL, 568 &cpu->sve_default_vq); 569 #endif 570 } 571 572 static void aarch64_add_sme_properties(Object *obj) 573 { 574 ARMCPU *cpu = ARM_CPU(obj); 575 uint32_t vq; 576 577 object_property_add_bool(obj, "sme", cpu_arm_get_sme, cpu_arm_set_sme); 578 object_property_add_bool(obj, "sme_fa64", cpu_arm_get_sme_fa64, 579 cpu_arm_set_sme_fa64); 580 581 for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) { 582 char name[8]; 583 sprintf(name, "sme%d", vq * 128); 584 object_property_add(obj, name, "bool", cpu_arm_get_vq, 585 cpu_arm_set_vq, NULL, &cpu->sme_vq); 586 } 587 588 #ifdef CONFIG_USER_ONLY 589 /* Mirror linux /proc/sys/abi/sme_default_vector_length. */ 590 object_property_add(obj, "sme-default-vector-length", "int32", 591 cpu_arm_get_default_vec_len, 592 cpu_arm_set_default_vec_len, NULL, 593 &cpu->sme_default_vq); 594 #endif 595 } 596 597 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) 598 { 599 int arch_val = 0, impdef_val = 0; 600 uint64_t t; 601 602 /* Exit early if PAuth is enabled, and fall through to disable it */ 603 if ((kvm_enabled() || hvf_enabled()) && cpu->prop_pauth) { 604 if (!cpu_isar_feature(aa64_pauth, cpu)) { 605 error_setg(errp, "'pauth' feature not supported by %s on this host", 606 kvm_enabled() ? "KVM" : "hvf"); 607 } 608 609 return; 610 } 611 612 /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ 613 if (cpu->prop_pauth) { 614 if (cpu->prop_pauth_impdef) { 615 impdef_val = 1; 616 } else { 617 arch_val = 1; 618 } 619 } else if (cpu->prop_pauth_impdef) { 620 error_setg(errp, "cannot enable pauth-impdef without pauth"); 621 error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); 622 } 623 624 t = cpu->isar.id_aa64isar1; 625 t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); 626 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); 627 t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); 628 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); 629 cpu->isar.id_aa64isar1 = t; 630 } 631 632 static Property arm_cpu_pauth_property = 633 DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); 634 static Property arm_cpu_pauth_impdef_property = 635 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); 636 637 static void aarch64_add_pauth_properties(Object *obj) 638 { 639 ARMCPU *cpu = ARM_CPU(obj); 640 641 /* Default to PAUTH on, with the architected algorithm on TCG. */ 642 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); 643 if (kvm_enabled() || hvf_enabled()) { 644 /* 645 * Mirror PAuth support from the probed sysregs back into the 646 * property for KVM or hvf. Is it just a bit backward? Yes it is! 647 * Note that prop_pauth is true whether the host CPU supports the 648 * architected QARMA5 algorithm or the IMPDEF one. We don't 649 * provide the separate pauth-impdef property for KVM or hvf, 650 * only for TCG. 651 */ 652 cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); 653 } else { 654 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); 655 } 656 } 657 658 static Property arm_cpu_lpa2_property = 659 DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); 660 661 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) 662 { 663 uint64_t t; 664 665 /* 666 * We only install the property for tcg -cpu max; this is the 667 * only situation in which the cpu field can be true. 668 */ 669 if (!cpu->prop_lpa2) { 670 return; 671 } 672 673 t = cpu->isar.id_aa64mmfr0; 674 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */ 675 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */ 676 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */ 677 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */ 678 cpu->isar.id_aa64mmfr0 = t; 679 } 680 681 static void aarch64_a57_initfn(Object *obj) 682 { 683 ARMCPU *cpu = ARM_CPU(obj); 684 685 cpu->dtb_compatible = "arm,cortex-a57"; 686 set_feature(&cpu->env, ARM_FEATURE_V8); 687 set_feature(&cpu->env, ARM_FEATURE_NEON); 688 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 689 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 690 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 691 set_feature(&cpu->env, ARM_FEATURE_EL2); 692 set_feature(&cpu->env, ARM_FEATURE_EL3); 693 set_feature(&cpu->env, ARM_FEATURE_PMU); 694 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 695 cpu->midr = 0x411fd070; 696 cpu->revidr = 0x00000000; 697 cpu->reset_fpsid = 0x41034070; 698 cpu->isar.mvfr0 = 0x10110222; 699 cpu->isar.mvfr1 = 0x12111111; 700 cpu->isar.mvfr2 = 0x00000043; 701 cpu->ctr = 0x8444c004; 702 cpu->reset_sctlr = 0x00c50838; 703 cpu->isar.id_pfr0 = 0x00000131; 704 cpu->isar.id_pfr1 = 0x00011011; 705 cpu->isar.id_dfr0 = 0x03010066; 706 cpu->id_afr0 = 0x00000000; 707 cpu->isar.id_mmfr0 = 0x10101105; 708 cpu->isar.id_mmfr1 = 0x40000000; 709 cpu->isar.id_mmfr2 = 0x01260000; 710 cpu->isar.id_mmfr3 = 0x02102211; 711 cpu->isar.id_isar0 = 0x02101110; 712 cpu->isar.id_isar1 = 0x13112111; 713 cpu->isar.id_isar2 = 0x21232042; 714 cpu->isar.id_isar3 = 0x01112131; 715 cpu->isar.id_isar4 = 0x00011142; 716 cpu->isar.id_isar5 = 0x00011121; 717 cpu->isar.id_isar6 = 0; 718 cpu->isar.id_aa64pfr0 = 0x00002222; 719 cpu->isar.id_aa64dfr0 = 0x10305106; 720 cpu->isar.id_aa64isar0 = 0x00011120; 721 cpu->isar.id_aa64mmfr0 = 0x00001124; 722 cpu->isar.dbgdidr = 0x3516d000; 723 cpu->isar.dbgdevid = 0x01110f13; 724 cpu->isar.dbgdevid1 = 0x2; 725 cpu->isar.reset_pmcr_el0 = 0x41013000; 726 cpu->clidr = 0x0a200023; 727 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 728 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 729 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 730 cpu->dcz_blocksize = 4; /* 64 bytes */ 731 cpu->gic_num_lrs = 4; 732 cpu->gic_vpribits = 5; 733 cpu->gic_vprebits = 5; 734 cpu->gic_pribits = 5; 735 define_cortex_a72_a57_a53_cp_reginfo(cpu); 736 } 737 738 static void aarch64_a53_initfn(Object *obj) 739 { 740 ARMCPU *cpu = ARM_CPU(obj); 741 742 cpu->dtb_compatible = "arm,cortex-a53"; 743 set_feature(&cpu->env, ARM_FEATURE_V8); 744 set_feature(&cpu->env, ARM_FEATURE_NEON); 745 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 746 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 747 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 748 set_feature(&cpu->env, ARM_FEATURE_EL2); 749 set_feature(&cpu->env, ARM_FEATURE_EL3); 750 set_feature(&cpu->env, ARM_FEATURE_PMU); 751 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 752 cpu->midr = 0x410fd034; 753 cpu->revidr = 0x00000000; 754 cpu->reset_fpsid = 0x41034070; 755 cpu->isar.mvfr0 = 0x10110222; 756 cpu->isar.mvfr1 = 0x12111111; 757 cpu->isar.mvfr2 = 0x00000043; 758 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 759 cpu->reset_sctlr = 0x00c50838; 760 cpu->isar.id_pfr0 = 0x00000131; 761 cpu->isar.id_pfr1 = 0x00011011; 762 cpu->isar.id_dfr0 = 0x03010066; 763 cpu->id_afr0 = 0x00000000; 764 cpu->isar.id_mmfr0 = 0x10101105; 765 cpu->isar.id_mmfr1 = 0x40000000; 766 cpu->isar.id_mmfr2 = 0x01260000; 767 cpu->isar.id_mmfr3 = 0x02102211; 768 cpu->isar.id_isar0 = 0x02101110; 769 cpu->isar.id_isar1 = 0x13112111; 770 cpu->isar.id_isar2 = 0x21232042; 771 cpu->isar.id_isar3 = 0x01112131; 772 cpu->isar.id_isar4 = 0x00011142; 773 cpu->isar.id_isar5 = 0x00011121; 774 cpu->isar.id_isar6 = 0; 775 cpu->isar.id_aa64pfr0 = 0x00002222; 776 cpu->isar.id_aa64dfr0 = 0x10305106; 777 cpu->isar.id_aa64isar0 = 0x00011120; 778 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 779 cpu->isar.dbgdidr = 0x3516d000; 780 cpu->isar.dbgdevid = 0x00110f13; 781 cpu->isar.dbgdevid1 = 0x1; 782 cpu->isar.reset_pmcr_el0 = 0x41033000; 783 cpu->clidr = 0x0a200023; 784 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 785 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 786 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 787 cpu->dcz_blocksize = 4; /* 64 bytes */ 788 cpu->gic_num_lrs = 4; 789 cpu->gic_vpribits = 5; 790 cpu->gic_vprebits = 5; 791 cpu->gic_pribits = 5; 792 define_cortex_a72_a57_a53_cp_reginfo(cpu); 793 } 794 795 static void aarch64_a55_initfn(Object *obj) 796 { 797 ARMCPU *cpu = ARM_CPU(obj); 798 799 cpu->dtb_compatible = "arm,cortex-a55"; 800 set_feature(&cpu->env, ARM_FEATURE_V8); 801 set_feature(&cpu->env, ARM_FEATURE_NEON); 802 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 803 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 804 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 805 set_feature(&cpu->env, ARM_FEATURE_EL2); 806 set_feature(&cpu->env, ARM_FEATURE_EL3); 807 set_feature(&cpu->env, ARM_FEATURE_PMU); 808 809 /* Ordered by B2.4 AArch64 registers by functional group */ 810 cpu->clidr = 0x82000023; 811 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 812 cpu->dcz_blocksize = 4; /* 64 bytes */ 813 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; 814 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 815 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 816 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; 817 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 818 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 819 cpu->isar.id_aa64pfr0 = 0x0000000010112222ull; 820 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; 821 cpu->id_afr0 = 0x00000000; 822 cpu->isar.id_dfr0 = 0x04010088; 823 cpu->isar.id_isar0 = 0x02101110; 824 cpu->isar.id_isar1 = 0x13112111; 825 cpu->isar.id_isar2 = 0x21232042; 826 cpu->isar.id_isar3 = 0x01112131; 827 cpu->isar.id_isar4 = 0x00011142; 828 cpu->isar.id_isar5 = 0x01011121; 829 cpu->isar.id_isar6 = 0x00000010; 830 cpu->isar.id_mmfr0 = 0x10201105; 831 cpu->isar.id_mmfr1 = 0x40000000; 832 cpu->isar.id_mmfr2 = 0x01260000; 833 cpu->isar.id_mmfr3 = 0x02122211; 834 cpu->isar.id_mmfr4 = 0x00021110; 835 cpu->isar.id_pfr0 = 0x10010131; 836 cpu->isar.id_pfr1 = 0x00011011; 837 cpu->isar.id_pfr2 = 0x00000011; 838 cpu->midr = 0x412FD050; /* r2p0 */ 839 cpu->revidr = 0; 840 841 /* From B2.23 CCSIDR_EL1 */ 842 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 843 cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */ 844 cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */ 845 846 /* From B2.96 SCTLR_EL3 */ 847 cpu->reset_sctlr = 0x30c50838; 848 849 /* From B4.45 ICH_VTR_EL2 */ 850 cpu->gic_num_lrs = 4; 851 cpu->gic_vpribits = 5; 852 cpu->gic_vprebits = 5; 853 cpu->gic_pribits = 5; 854 855 cpu->isar.mvfr0 = 0x10110222; 856 cpu->isar.mvfr1 = 0x13211111; 857 cpu->isar.mvfr2 = 0x00000043; 858 859 /* From D5.4 AArch64 PMU register summary */ 860 cpu->isar.reset_pmcr_el0 = 0x410b3000; 861 } 862 863 static void aarch64_a72_initfn(Object *obj) 864 { 865 ARMCPU *cpu = ARM_CPU(obj); 866 867 cpu->dtb_compatible = "arm,cortex-a72"; 868 set_feature(&cpu->env, ARM_FEATURE_V8); 869 set_feature(&cpu->env, ARM_FEATURE_NEON); 870 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 871 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 872 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 873 set_feature(&cpu->env, ARM_FEATURE_EL2); 874 set_feature(&cpu->env, ARM_FEATURE_EL3); 875 set_feature(&cpu->env, ARM_FEATURE_PMU); 876 cpu->midr = 0x410fd083; 877 cpu->revidr = 0x00000000; 878 cpu->reset_fpsid = 0x41034080; 879 cpu->isar.mvfr0 = 0x10110222; 880 cpu->isar.mvfr1 = 0x12111111; 881 cpu->isar.mvfr2 = 0x00000043; 882 cpu->ctr = 0x8444c004; 883 cpu->reset_sctlr = 0x00c50838; 884 cpu->isar.id_pfr0 = 0x00000131; 885 cpu->isar.id_pfr1 = 0x00011011; 886 cpu->isar.id_dfr0 = 0x03010066; 887 cpu->id_afr0 = 0x00000000; 888 cpu->isar.id_mmfr0 = 0x10201105; 889 cpu->isar.id_mmfr1 = 0x40000000; 890 cpu->isar.id_mmfr2 = 0x01260000; 891 cpu->isar.id_mmfr3 = 0x02102211; 892 cpu->isar.id_isar0 = 0x02101110; 893 cpu->isar.id_isar1 = 0x13112111; 894 cpu->isar.id_isar2 = 0x21232042; 895 cpu->isar.id_isar3 = 0x01112131; 896 cpu->isar.id_isar4 = 0x00011142; 897 cpu->isar.id_isar5 = 0x00011121; 898 cpu->isar.id_aa64pfr0 = 0x00002222; 899 cpu->isar.id_aa64dfr0 = 0x10305106; 900 cpu->isar.id_aa64isar0 = 0x00011120; 901 cpu->isar.id_aa64mmfr0 = 0x00001124; 902 cpu->isar.dbgdidr = 0x3516d000; 903 cpu->isar.dbgdevid = 0x01110f13; 904 cpu->isar.dbgdevid1 = 0x2; 905 cpu->isar.reset_pmcr_el0 = 0x41023000; 906 cpu->clidr = 0x0a200023; 907 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 908 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 909 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ 910 cpu->dcz_blocksize = 4; /* 64 bytes */ 911 cpu->gic_num_lrs = 4; 912 cpu->gic_vpribits = 5; 913 cpu->gic_vprebits = 5; 914 cpu->gic_pribits = 5; 915 define_cortex_a72_a57_a53_cp_reginfo(cpu); 916 } 917 918 static void aarch64_a76_initfn(Object *obj) 919 { 920 ARMCPU *cpu = ARM_CPU(obj); 921 922 cpu->dtb_compatible = "arm,cortex-a76"; 923 set_feature(&cpu->env, ARM_FEATURE_V8); 924 set_feature(&cpu->env, ARM_FEATURE_NEON); 925 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 926 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 927 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 928 set_feature(&cpu->env, ARM_FEATURE_EL2); 929 set_feature(&cpu->env, ARM_FEATURE_EL3); 930 set_feature(&cpu->env, ARM_FEATURE_PMU); 931 932 /* Ordered by B2.4 AArch64 registers by functional group */ 933 cpu->clidr = 0x82000023; 934 cpu->ctr = 0x8444C004; 935 cpu->dcz_blocksize = 4; 936 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; 937 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 938 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 939 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; 940 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 941 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 942 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 943 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; 944 cpu->id_afr0 = 0x00000000; 945 cpu->isar.id_dfr0 = 0x04010088; 946 cpu->isar.id_isar0 = 0x02101110; 947 cpu->isar.id_isar1 = 0x13112111; 948 cpu->isar.id_isar2 = 0x21232042; 949 cpu->isar.id_isar3 = 0x01112131; 950 cpu->isar.id_isar4 = 0x00010142; 951 cpu->isar.id_isar5 = 0x01011121; 952 cpu->isar.id_isar6 = 0x00000010; 953 cpu->isar.id_mmfr0 = 0x10201105; 954 cpu->isar.id_mmfr1 = 0x40000000; 955 cpu->isar.id_mmfr2 = 0x01260000; 956 cpu->isar.id_mmfr3 = 0x02122211; 957 cpu->isar.id_mmfr4 = 0x00021110; 958 cpu->isar.id_pfr0 = 0x10010131; 959 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 960 cpu->isar.id_pfr2 = 0x00000011; 961 cpu->midr = 0x414fd0b1; /* r4p1 */ 962 cpu->revidr = 0; 963 964 /* From B2.18 CCSIDR_EL1 */ 965 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 966 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 967 cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ 968 969 /* From B2.93 SCTLR_EL3 */ 970 cpu->reset_sctlr = 0x30c50838; 971 972 /* From B4.23 ICH_VTR_EL2 */ 973 cpu->gic_num_lrs = 4; 974 cpu->gic_vpribits = 5; 975 cpu->gic_vprebits = 5; 976 cpu->gic_pribits = 5; 977 978 /* From B5.1 AdvSIMD AArch64 register summary */ 979 cpu->isar.mvfr0 = 0x10110222; 980 cpu->isar.mvfr1 = 0x13211111; 981 cpu->isar.mvfr2 = 0x00000043; 982 983 /* From D5.1 AArch64 PMU register summary */ 984 cpu->isar.reset_pmcr_el0 = 0x410b3000; 985 } 986 987 static void aarch64_a64fx_initfn(Object *obj) 988 { 989 ARMCPU *cpu = ARM_CPU(obj); 990 991 cpu->dtb_compatible = "arm,a64fx"; 992 set_feature(&cpu->env, ARM_FEATURE_V8); 993 set_feature(&cpu->env, ARM_FEATURE_NEON); 994 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 995 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 996 set_feature(&cpu->env, ARM_FEATURE_EL2); 997 set_feature(&cpu->env, ARM_FEATURE_EL3); 998 set_feature(&cpu->env, ARM_FEATURE_PMU); 999 cpu->midr = 0x461f0010; 1000 cpu->revidr = 0x00000000; 1001 cpu->ctr = 0x86668006; 1002 cpu->reset_sctlr = 0x30000180; 1003 cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */ 1004 cpu->isar.id_aa64pfr1 = 0x0000000000000000; 1005 cpu->isar.id_aa64dfr0 = 0x0000000010305408; 1006 cpu->isar.id_aa64dfr1 = 0x0000000000000000; 1007 cpu->id_aa64afr0 = 0x0000000000000000; 1008 cpu->id_aa64afr1 = 0x0000000000000000; 1009 cpu->isar.id_aa64mmfr0 = 0x0000000000001122; 1010 cpu->isar.id_aa64mmfr1 = 0x0000000011212100; 1011 cpu->isar.id_aa64mmfr2 = 0x0000000000001011; 1012 cpu->isar.id_aa64isar0 = 0x0000000010211120; 1013 cpu->isar.id_aa64isar1 = 0x0000000000010001; 1014 cpu->isar.id_aa64zfr0 = 0x0000000000000000; 1015 cpu->clidr = 0x0000000080000023; 1016 cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */ 1017 cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */ 1018 cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */ 1019 cpu->dcz_blocksize = 6; /* 256 bytes */ 1020 cpu->gic_num_lrs = 4; 1021 cpu->gic_vpribits = 5; 1022 cpu->gic_vprebits = 5; 1023 cpu->gic_pribits = 5; 1024 1025 /* The A64FX supports only 128, 256 and 512 bit vector lengths */ 1026 aarch64_add_sve_properties(obj); 1027 cpu->sve_vq.supported = (1 << 0) /* 128bit */ 1028 | (1 << 1) /* 256bit */ 1029 | (1 << 3); /* 512bit */ 1030 1031 cpu->isar.reset_pmcr_el0 = 0x46014040; 1032 1033 /* TODO: Add A64FX specific HPC extension registers */ 1034 } 1035 1036 static void aarch64_neoverse_n1_initfn(Object *obj) 1037 { 1038 ARMCPU *cpu = ARM_CPU(obj); 1039 1040 cpu->dtb_compatible = "arm,neoverse-n1"; 1041 set_feature(&cpu->env, ARM_FEATURE_V8); 1042 set_feature(&cpu->env, ARM_FEATURE_NEON); 1043 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1044 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 1045 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1046 set_feature(&cpu->env, ARM_FEATURE_EL2); 1047 set_feature(&cpu->env, ARM_FEATURE_EL3); 1048 set_feature(&cpu->env, ARM_FEATURE_PMU); 1049 1050 /* Ordered by B2.4 AArch64 registers by functional group */ 1051 cpu->clidr = 0x82000023; 1052 cpu->ctr = 0x8444c004; 1053 cpu->dcz_blocksize = 4; 1054 cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; 1055 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 1056 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 1057 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; 1058 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 1059 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 1060 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 1061 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; 1062 cpu->id_afr0 = 0x00000000; 1063 cpu->isar.id_dfr0 = 0x04010088; 1064 cpu->isar.id_isar0 = 0x02101110; 1065 cpu->isar.id_isar1 = 0x13112111; 1066 cpu->isar.id_isar2 = 0x21232042; 1067 cpu->isar.id_isar3 = 0x01112131; 1068 cpu->isar.id_isar4 = 0x00010142; 1069 cpu->isar.id_isar5 = 0x01011121; 1070 cpu->isar.id_isar6 = 0x00000010; 1071 cpu->isar.id_mmfr0 = 0x10201105; 1072 cpu->isar.id_mmfr1 = 0x40000000; 1073 cpu->isar.id_mmfr2 = 0x01260000; 1074 cpu->isar.id_mmfr3 = 0x02122211; 1075 cpu->isar.id_mmfr4 = 0x00021110; 1076 cpu->isar.id_pfr0 = 0x10010131; 1077 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 1078 cpu->isar.id_pfr2 = 0x00000011; 1079 cpu->midr = 0x414fd0c1; /* r4p1 */ 1080 cpu->revidr = 0; 1081 1082 /* From B2.23 CCSIDR_EL1 */ 1083 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 1084 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 1085 cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ 1086 1087 /* From B2.98 SCTLR_EL3 */ 1088 cpu->reset_sctlr = 0x30c50838; 1089 1090 /* From B4.23 ICH_VTR_EL2 */ 1091 cpu->gic_num_lrs = 4; 1092 cpu->gic_vpribits = 5; 1093 cpu->gic_vprebits = 5; 1094 cpu->gic_pribits = 5; 1095 1096 /* From B5.1 AdvSIMD AArch64 register summary */ 1097 cpu->isar.mvfr0 = 0x10110222; 1098 cpu->isar.mvfr1 = 0x13211111; 1099 cpu->isar.mvfr2 = 0x00000043; 1100 1101 /* From D5.1 AArch64 PMU register summary */ 1102 cpu->isar.reset_pmcr_el0 = 0x410c3000; 1103 } 1104 1105 static void aarch64_host_initfn(Object *obj) 1106 { 1107 #if defined(CONFIG_KVM) 1108 ARMCPU *cpu = ARM_CPU(obj); 1109 kvm_arm_set_cpu_features_from_host(cpu); 1110 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1111 aarch64_add_sve_properties(obj); 1112 aarch64_add_pauth_properties(obj); 1113 } 1114 #elif defined(CONFIG_HVF) 1115 ARMCPU *cpu = ARM_CPU(obj); 1116 hvf_arm_set_cpu_features_from_host(cpu); 1117 aarch64_add_pauth_properties(obj); 1118 #else 1119 g_assert_not_reached(); 1120 #endif 1121 } 1122 1123 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 1124 * otherwise, a CPU with as many features enabled as our emulation supports. 1125 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; 1126 * this only needs to handle 64 bits. 1127 */ 1128 static void aarch64_max_initfn(Object *obj) 1129 { 1130 ARMCPU *cpu = ARM_CPU(obj); 1131 uint64_t t; 1132 uint32_t u; 1133 1134 if (kvm_enabled() || hvf_enabled()) { 1135 /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ 1136 aarch64_host_initfn(obj); 1137 return; 1138 } 1139 1140 /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */ 1141 1142 aarch64_a57_initfn(obj); 1143 1144 /* 1145 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real 1146 * one and try to apply errata workarounds or use impdef features we 1147 * don't provide. 1148 * An IMPLEMENTER field of 0 means "reserved for software use"; 1149 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers 1150 * to see which features are present"; 1151 * the VARIANT, PARTNUM and REVISION fields are all implementation 1152 * defined and we choose to define PARTNUM just in case guest 1153 * code needs to distinguish this QEMU CPU from other software 1154 * implementations, though this shouldn't be needed. 1155 */ 1156 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); 1157 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); 1158 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); 1159 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); 1160 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); 1161 cpu->midr = t; 1162 1163 /* 1164 * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS} 1165 * are zero. 1166 */ 1167 u = cpu->clidr; 1168 u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); 1169 u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0); 1170 cpu->clidr = u; 1171 1172 t = cpu->isar.id_aa64isar0; 1173 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ 1174 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ 1175 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ 1176 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); 1177 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ 1178 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ 1179 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ 1180 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ 1181 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ 1182 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ 1183 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ 1184 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ 1185 t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ 1186 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ 1187 cpu->isar.id_aa64isar0 = t; 1188 1189 t = cpu->isar.id_aa64isar1; 1190 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ 1191 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ 1192 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ 1193 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ 1194 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ 1195 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ 1196 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ 1197 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ 1198 t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ 1199 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ 1200 cpu->isar.id_aa64isar1 = t; 1201 1202 t = cpu->isar.id_aa64pfr0; 1203 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ 1204 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ 1205 t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */ 1206 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); 1207 t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ 1208 t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ 1209 t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ 1210 t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ 1211 cpu->isar.id_aa64pfr0 = t; 1212 1213 t = cpu->isar.id_aa64pfr1; 1214 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ 1215 t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ 1216 /* 1217 * Begin with full support for MTE. This will be downgraded to MTE=0 1218 * during realize if the board provides no tag memory, much like 1219 * we do for EL2 with the virtualization=on property. 1220 */ 1221 t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ 1222 t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ 1223 t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ 1224 t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ 1225 cpu->isar.id_aa64pfr1 = t; 1226 1227 t = cpu->isar.id_aa64mmfr0; 1228 t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ 1229 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ 1230 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ 1231 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ 1232 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ 1233 cpu->isar.id_aa64mmfr0 = t; 1234 1235 t = cpu->isar.id_aa64mmfr1; 1236 t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ 1237 t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ 1238 t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ 1239 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ 1240 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ 1241 t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ 1242 t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ 1243 t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ 1244 t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ 1245 cpu->isar.id_aa64mmfr1 = t; 1246 1247 t = cpu->isar.id_aa64mmfr2; 1248 t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ 1249 t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ 1250 t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ 1251 t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ 1252 t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ 1253 t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ 1254 t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ 1255 t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ 1256 t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ 1257 t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ 1258 t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ 1259 cpu->isar.id_aa64mmfr2 = t; 1260 1261 t = cpu->isar.id_aa64zfr0; 1262 t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); 1263 t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ 1264 t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ 1265 t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ 1266 t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ 1267 t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ 1268 t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ 1269 t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ 1270 t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ 1271 cpu->isar.id_aa64zfr0 = t; 1272 1273 t = cpu->isar.id_aa64dfr0; 1274 t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ 1275 t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ 1276 cpu->isar.id_aa64dfr0 = t; 1277 1278 t = cpu->isar.id_aa64smfr0; 1279 t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ 1280 t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ 1281 t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ 1282 t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ 1283 t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ 1284 t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ 1285 t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ 1286 cpu->isar.id_aa64smfr0 = t; 1287 1288 /* Replicate the same data to the 32-bit id registers. */ 1289 aa32_max_features(cpu); 1290 1291 #ifdef CONFIG_USER_ONLY 1292 /* 1293 * For usermode -cpu max we can use a larger and more efficient DCZ 1294 * blocksize since we don't have to follow what the hardware does. 1295 */ 1296 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 1297 cpu->dcz_blocksize = 7; /* 512 bytes */ 1298 #endif 1299 1300 cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); 1301 cpu->sme_vq.supported = SVE_VQ_POW2_MAP; 1302 1303 aarch64_add_pauth_properties(obj); 1304 aarch64_add_sve_properties(obj); 1305 aarch64_add_sme_properties(obj); 1306 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, 1307 cpu_max_set_sve_max_vq, NULL, NULL); 1308 qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); 1309 } 1310 1311 static const ARMCPUInfo aarch64_cpus[] = { 1312 { .name = "cortex-a35", .initfn = aarch64_a35_initfn }, 1313 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 1314 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 1315 { .name = "cortex-a55", .initfn = aarch64_a55_initfn }, 1316 { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, 1317 { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, 1318 { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, 1319 { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, 1320 { .name = "max", .initfn = aarch64_max_initfn }, 1321 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1322 { .name = "host", .initfn = aarch64_host_initfn }, 1323 #endif 1324 }; 1325 1326 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 1327 { 1328 ARMCPU *cpu = ARM_CPU(obj); 1329 1330 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 1331 } 1332 1333 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 1334 { 1335 ARMCPU *cpu = ARM_CPU(obj); 1336 1337 /* At this time, this property is only allowed if KVM is enabled. This 1338 * restriction allows us to avoid fixing up functionality that assumes a 1339 * uniform execution state like do_interrupt. 1340 */ 1341 if (value == false) { 1342 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 1343 error_setg(errp, "'aarch64' feature cannot be disabled " 1344 "unless KVM is enabled and 32-bit EL1 " 1345 "is supported"); 1346 return; 1347 } 1348 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 1349 } else { 1350 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 1351 } 1352 } 1353 1354 static void aarch64_cpu_finalizefn(Object *obj) 1355 { 1356 } 1357 1358 static gchar *aarch64_gdb_arch_name(CPUState *cs) 1359 { 1360 return g_strdup("aarch64"); 1361 } 1362 1363 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 1364 { 1365 CPUClass *cc = CPU_CLASS(oc); 1366 1367 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 1368 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 1369 cc->gdb_num_core_regs = 34; 1370 cc->gdb_core_xml_file = "aarch64-core.xml"; 1371 cc->gdb_arch_name = aarch64_gdb_arch_name; 1372 1373 object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, 1374 aarch64_cpu_set_aarch64); 1375 object_class_property_set_description(oc, "aarch64", 1376 "Set on/off to enable/disable aarch64 " 1377 "execution state "); 1378 } 1379 1380 static void aarch64_cpu_instance_init(Object *obj) 1381 { 1382 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 1383 1384 acc->info->initfn(obj); 1385 arm_cpu_post_init(obj); 1386 } 1387 1388 static void cpu_register_class_init(ObjectClass *oc, void *data) 1389 { 1390 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1391 1392 acc->info = data; 1393 } 1394 1395 void aarch64_cpu_register(const ARMCPUInfo *info) 1396 { 1397 TypeInfo type_info = { 1398 .parent = TYPE_AARCH64_CPU, 1399 .instance_size = sizeof(ARMCPU), 1400 .instance_init = aarch64_cpu_instance_init, 1401 .class_size = sizeof(ARMCPUClass), 1402 .class_init = info->class_init ?: cpu_register_class_init, 1403 .class_data = (void *)info, 1404 }; 1405 1406 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1407 type_register(&type_info); 1408 g_free((void *)type_info.name); 1409 } 1410 1411 static const TypeInfo aarch64_cpu_type_info = { 1412 .name = TYPE_AARCH64_CPU, 1413 .parent = TYPE_ARM_CPU, 1414 .instance_size = sizeof(ARMCPU), 1415 .instance_finalize = aarch64_cpu_finalizefn, 1416 .abstract = true, 1417 .class_size = sizeof(AArch64CPUClass), 1418 .class_init = aarch64_cpu_class_init, 1419 }; 1420 1421 static void aarch64_cpu_register_types(void) 1422 { 1423 size_t i; 1424 1425 type_register_static(&aarch64_cpu_type_info); 1426 1427 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { 1428 aarch64_cpu_register(&aarch64_cpus[i]); 1429 } 1430 } 1431 1432 type_init(aarch64_cpu_register_types) 1433