1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "qemu/module.h" 25 #if !defined(CONFIG_USER_ONLY) 26 #include "hw/loader.h" 27 #endif 28 #include "sysemu/kvm.h" 29 #include "kvm_arm.h" 30 #include "qapi/visitor.h" 31 32 static inline void set_feature(CPUARMState *env, int feature) 33 { 34 env->features |= 1ULL << feature; 35 } 36 37 static inline void unset_feature(CPUARMState *env, int feature) 38 { 39 env->features &= ~(1ULL << feature); 40 } 41 42 #ifndef CONFIG_USER_ONLY 43 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 44 { 45 ARMCPU *cpu = env_archcpu(env); 46 47 /* Number of cores is in [25:24]; otherwise we RAZ */ 48 return (cpu->core_count - 1) << 24; 49 } 50 #endif 51 52 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { 53 #ifndef CONFIG_USER_ONLY 54 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, 55 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, 56 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 57 .writefn = arm_cp_write_ignore }, 58 { .name = "L2CTLR", 59 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, 60 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 61 .writefn = arm_cp_write_ignore }, 62 #endif 63 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, 64 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, 65 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 66 { .name = "L2ECTLR", 67 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, 68 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 69 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, 70 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, 71 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 72 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 73 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, 74 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 75 { .name = "CPUACTLR", 76 .cp = 15, .opc1 = 0, .crm = 15, 77 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 78 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 79 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, 80 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 81 { .name = "CPUECTLR", 82 .cp = 15, .opc1 = 1, .crm = 15, 83 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 84 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, 85 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, 86 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 87 { .name = "CPUMERRSR", 88 .cp = 15, .opc1 = 2, .crm = 15, 89 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 90 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, 91 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, 92 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 93 { .name = "L2MERRSR", 94 .cp = 15, .opc1 = 3, .crm = 15, 95 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 96 REGINFO_SENTINEL 97 }; 98 99 static void aarch64_a57_initfn(Object *obj) 100 { 101 ARMCPU *cpu = ARM_CPU(obj); 102 103 cpu->dtb_compatible = "arm,cortex-a57"; 104 set_feature(&cpu->env, ARM_FEATURE_V8); 105 set_feature(&cpu->env, ARM_FEATURE_VFP4); 106 set_feature(&cpu->env, ARM_FEATURE_NEON); 107 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 108 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 109 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 110 set_feature(&cpu->env, ARM_FEATURE_EL2); 111 set_feature(&cpu->env, ARM_FEATURE_EL3); 112 set_feature(&cpu->env, ARM_FEATURE_PMU); 113 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 114 cpu->midr = 0x411fd070; 115 cpu->revidr = 0x00000000; 116 cpu->reset_fpsid = 0x41034070; 117 cpu->isar.mvfr0 = 0x10110222; 118 cpu->isar.mvfr1 = 0x12111111; 119 cpu->isar.mvfr2 = 0x00000043; 120 cpu->ctr = 0x8444c004; 121 cpu->reset_sctlr = 0x00c50838; 122 cpu->id_pfr0 = 0x00000131; 123 cpu->id_pfr1 = 0x00011011; 124 cpu->id_dfr0 = 0x03010066; 125 cpu->id_afr0 = 0x00000000; 126 cpu->id_mmfr0 = 0x10101105; 127 cpu->id_mmfr1 = 0x40000000; 128 cpu->id_mmfr2 = 0x01260000; 129 cpu->id_mmfr3 = 0x02102211; 130 cpu->isar.id_isar0 = 0x02101110; 131 cpu->isar.id_isar1 = 0x13112111; 132 cpu->isar.id_isar2 = 0x21232042; 133 cpu->isar.id_isar3 = 0x01112131; 134 cpu->isar.id_isar4 = 0x00011142; 135 cpu->isar.id_isar5 = 0x00011121; 136 cpu->isar.id_isar6 = 0; 137 cpu->isar.id_aa64pfr0 = 0x00002222; 138 cpu->id_aa64dfr0 = 0x10305106; 139 cpu->isar.id_aa64isar0 = 0x00011120; 140 cpu->isar.id_aa64mmfr0 = 0x00001124; 141 cpu->dbgdidr = 0x3516d000; 142 cpu->clidr = 0x0a200023; 143 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 144 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 145 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 146 cpu->dcz_blocksize = 4; /* 64 bytes */ 147 cpu->gic_num_lrs = 4; 148 cpu->gic_vpribits = 5; 149 cpu->gic_vprebits = 5; 150 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 151 } 152 153 static void aarch64_a53_initfn(Object *obj) 154 { 155 ARMCPU *cpu = ARM_CPU(obj); 156 157 cpu->dtb_compatible = "arm,cortex-a53"; 158 set_feature(&cpu->env, ARM_FEATURE_V8); 159 set_feature(&cpu->env, ARM_FEATURE_VFP4); 160 set_feature(&cpu->env, ARM_FEATURE_NEON); 161 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 162 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 163 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 164 set_feature(&cpu->env, ARM_FEATURE_EL2); 165 set_feature(&cpu->env, ARM_FEATURE_EL3); 166 set_feature(&cpu->env, ARM_FEATURE_PMU); 167 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 168 cpu->midr = 0x410fd034; 169 cpu->revidr = 0x00000000; 170 cpu->reset_fpsid = 0x41034070; 171 cpu->isar.mvfr0 = 0x10110222; 172 cpu->isar.mvfr1 = 0x12111111; 173 cpu->isar.mvfr2 = 0x00000043; 174 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 175 cpu->reset_sctlr = 0x00c50838; 176 cpu->id_pfr0 = 0x00000131; 177 cpu->id_pfr1 = 0x00011011; 178 cpu->id_dfr0 = 0x03010066; 179 cpu->id_afr0 = 0x00000000; 180 cpu->id_mmfr0 = 0x10101105; 181 cpu->id_mmfr1 = 0x40000000; 182 cpu->id_mmfr2 = 0x01260000; 183 cpu->id_mmfr3 = 0x02102211; 184 cpu->isar.id_isar0 = 0x02101110; 185 cpu->isar.id_isar1 = 0x13112111; 186 cpu->isar.id_isar2 = 0x21232042; 187 cpu->isar.id_isar3 = 0x01112131; 188 cpu->isar.id_isar4 = 0x00011142; 189 cpu->isar.id_isar5 = 0x00011121; 190 cpu->isar.id_isar6 = 0; 191 cpu->isar.id_aa64pfr0 = 0x00002222; 192 cpu->id_aa64dfr0 = 0x10305106; 193 cpu->isar.id_aa64isar0 = 0x00011120; 194 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 195 cpu->dbgdidr = 0x3516d000; 196 cpu->clidr = 0x0a200023; 197 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 198 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 199 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 200 cpu->dcz_blocksize = 4; /* 64 bytes */ 201 cpu->gic_num_lrs = 4; 202 cpu->gic_vpribits = 5; 203 cpu->gic_vprebits = 5; 204 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 205 } 206 207 static void aarch64_a72_initfn(Object *obj) 208 { 209 ARMCPU *cpu = ARM_CPU(obj); 210 211 cpu->dtb_compatible = "arm,cortex-a72"; 212 set_feature(&cpu->env, ARM_FEATURE_V8); 213 set_feature(&cpu->env, ARM_FEATURE_VFP4); 214 set_feature(&cpu->env, ARM_FEATURE_NEON); 215 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 216 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 217 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 218 set_feature(&cpu->env, ARM_FEATURE_EL2); 219 set_feature(&cpu->env, ARM_FEATURE_EL3); 220 set_feature(&cpu->env, ARM_FEATURE_PMU); 221 cpu->midr = 0x410fd083; 222 cpu->revidr = 0x00000000; 223 cpu->reset_fpsid = 0x41034080; 224 cpu->isar.mvfr0 = 0x10110222; 225 cpu->isar.mvfr1 = 0x12111111; 226 cpu->isar.mvfr2 = 0x00000043; 227 cpu->ctr = 0x8444c004; 228 cpu->reset_sctlr = 0x00c50838; 229 cpu->id_pfr0 = 0x00000131; 230 cpu->id_pfr1 = 0x00011011; 231 cpu->id_dfr0 = 0x03010066; 232 cpu->id_afr0 = 0x00000000; 233 cpu->id_mmfr0 = 0x10201105; 234 cpu->id_mmfr1 = 0x40000000; 235 cpu->id_mmfr2 = 0x01260000; 236 cpu->id_mmfr3 = 0x02102211; 237 cpu->isar.id_isar0 = 0x02101110; 238 cpu->isar.id_isar1 = 0x13112111; 239 cpu->isar.id_isar2 = 0x21232042; 240 cpu->isar.id_isar3 = 0x01112131; 241 cpu->isar.id_isar4 = 0x00011142; 242 cpu->isar.id_isar5 = 0x00011121; 243 cpu->isar.id_aa64pfr0 = 0x00002222; 244 cpu->id_aa64dfr0 = 0x10305106; 245 cpu->isar.id_aa64isar0 = 0x00011120; 246 cpu->isar.id_aa64mmfr0 = 0x00001124; 247 cpu->dbgdidr = 0x3516d000; 248 cpu->clidr = 0x0a200023; 249 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 250 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 251 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ 252 cpu->dcz_blocksize = 4; /* 64 bytes */ 253 cpu->gic_num_lrs = 4; 254 cpu->gic_vpribits = 5; 255 cpu->gic_vprebits = 5; 256 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 257 } 258 259 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, 260 void *opaque, Error **errp) 261 { 262 ARMCPU *cpu = ARM_CPU(obj); 263 visit_type_uint32(v, name, &cpu->sve_max_vq, errp); 264 } 265 266 static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, 267 void *opaque, Error **errp) 268 { 269 ARMCPU *cpu = ARM_CPU(obj); 270 Error *err = NULL; 271 272 visit_type_uint32(v, name, &cpu->sve_max_vq, &err); 273 274 if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) { 275 error_setg(&err, "unsupported SVE vector length"); 276 error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n", 277 ARM_MAX_VQ); 278 } 279 error_propagate(errp, err); 280 } 281 282 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 283 * otherwise, a CPU with as many features enabled as our emulation supports. 284 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; 285 * this only needs to handle 64 bits. 286 */ 287 static void aarch64_max_initfn(Object *obj) 288 { 289 ARMCPU *cpu = ARM_CPU(obj); 290 291 if (kvm_enabled()) { 292 kvm_arm_set_cpu_features_from_host(cpu); 293 } else { 294 uint64_t t; 295 uint32_t u; 296 aarch64_a57_initfn(obj); 297 298 /* 299 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real 300 * one and try to apply errata workarounds or use impdef features we 301 * don't provide. 302 * An IMPLEMENTER field of 0 means "reserved for software use"; 303 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers 304 * to see which features are present"; 305 * the VARIANT, PARTNUM and REVISION fields are all implementation 306 * defined and we choose to define PARTNUM just in case guest 307 * code needs to distinguish this QEMU CPU from other software 308 * implementations, though this shouldn't be needed. 309 */ 310 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); 311 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); 312 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); 313 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); 314 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); 315 cpu->midr = t; 316 317 t = cpu->isar.id_aa64isar0; 318 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ 319 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); 320 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ 321 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); 322 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); 323 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); 324 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); 325 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); 326 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); 327 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); 328 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); 329 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ 330 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); 331 cpu->isar.id_aa64isar0 = t; 332 333 t = cpu->isar.id_aa64isar1; 334 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); 335 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); 336 t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ 337 t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); 338 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); 339 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); 340 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); 341 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); 342 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); 343 cpu->isar.id_aa64isar1 = t; 344 345 t = cpu->isar.id_aa64pfr0; 346 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); 347 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); 348 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); 349 cpu->isar.id_aa64pfr0 = t; 350 351 t = cpu->isar.id_aa64pfr1; 352 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); 353 cpu->isar.id_aa64pfr1 = t; 354 355 t = cpu->isar.id_aa64mmfr1; 356 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ 357 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); 358 cpu->isar.id_aa64mmfr1 = t; 359 360 /* Replicate the same data to the 32-bit id registers. */ 361 u = cpu->isar.id_isar5; 362 u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ 363 u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); 364 u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); 365 u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); 366 u = FIELD_DP32(u, ID_ISAR5, RDM, 1); 367 u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); 368 cpu->isar.id_isar5 = u; 369 370 u = cpu->isar.id_isar6; 371 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); 372 u = FIELD_DP32(u, ID_ISAR6, DP, 1); 373 u = FIELD_DP32(u, ID_ISAR6, FHM, 1); 374 u = FIELD_DP32(u, ID_ISAR6, SB, 1); 375 u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); 376 cpu->isar.id_isar6 = u; 377 378 /* 379 * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, 380 * so do not set MVFR1.FPHP. Strictly speaking this is not legal, 381 * but it is also not legal to enable SVE without support for FP16, 382 * and enabling SVE in system mode is more useful in the short term. 383 */ 384 385 #ifdef CONFIG_USER_ONLY 386 /* For usermode -cpu max we can use a larger and more efficient DCZ 387 * blocksize since we don't have to follow what the hardware does. 388 */ 389 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 390 cpu->dcz_blocksize = 7; /* 512 bytes */ 391 #endif 392 393 cpu->sve_max_vq = ARM_MAX_VQ; 394 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq, 395 cpu_max_set_sve_vq, NULL, NULL, &error_fatal); 396 } 397 } 398 399 struct ARMCPUInfo { 400 const char *name; 401 void (*initfn)(Object *obj); 402 void (*class_init)(ObjectClass *oc, void *data); 403 }; 404 405 static const ARMCPUInfo aarch64_cpus[] = { 406 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 407 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 408 { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, 409 { .name = "max", .initfn = aarch64_max_initfn }, 410 { .name = NULL } 411 }; 412 413 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 414 { 415 ARMCPU *cpu = ARM_CPU(obj); 416 417 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 418 } 419 420 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 421 { 422 ARMCPU *cpu = ARM_CPU(obj); 423 424 /* At this time, this property is only allowed if KVM is enabled. This 425 * restriction allows us to avoid fixing up functionality that assumes a 426 * uniform execution state like do_interrupt. 427 */ 428 if (value == false) { 429 if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) { 430 error_setg(errp, "'aarch64' feature cannot be disabled " 431 "unless KVM is enabled and 32-bit EL1 " 432 "is supported"); 433 return; 434 } 435 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 436 } else { 437 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 438 } 439 } 440 441 static void aarch64_cpu_initfn(Object *obj) 442 { 443 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, 444 aarch64_cpu_set_aarch64, NULL); 445 object_property_set_description(obj, "aarch64", 446 "Set on/off to enable/disable aarch64 " 447 "execution state ", 448 NULL); 449 } 450 451 static void aarch64_cpu_finalizefn(Object *obj) 452 { 453 } 454 455 static gchar *aarch64_gdb_arch_name(CPUState *cs) 456 { 457 return g_strdup("aarch64"); 458 } 459 460 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 461 { 462 CPUClass *cc = CPU_CLASS(oc); 463 464 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 465 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 466 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 467 cc->gdb_num_core_regs = 34; 468 cc->gdb_core_xml_file = "aarch64-core.xml"; 469 cc->gdb_arch_name = aarch64_gdb_arch_name; 470 } 471 472 static void aarch64_cpu_instance_init(Object *obj) 473 { 474 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 475 476 acc->info->initfn(obj); 477 arm_cpu_post_init(obj); 478 } 479 480 static void cpu_register_class_init(ObjectClass *oc, void *data) 481 { 482 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 483 484 acc->info = data; 485 } 486 487 static void aarch64_cpu_register(const ARMCPUInfo *info) 488 { 489 TypeInfo type_info = { 490 .parent = TYPE_AARCH64_CPU, 491 .instance_size = sizeof(ARMCPU), 492 .instance_init = aarch64_cpu_instance_init, 493 .class_size = sizeof(ARMCPUClass), 494 .class_init = info->class_init ?: cpu_register_class_init, 495 .class_data = (void *)info, 496 }; 497 498 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 499 type_register(&type_info); 500 g_free((void *)type_info.name); 501 } 502 503 static const TypeInfo aarch64_cpu_type_info = { 504 .name = TYPE_AARCH64_CPU, 505 .parent = TYPE_ARM_CPU, 506 .instance_size = sizeof(ARMCPU), 507 .instance_init = aarch64_cpu_initfn, 508 .instance_finalize = aarch64_cpu_finalizefn, 509 .abstract = true, 510 .class_size = sizeof(AArch64CPUClass), 511 .class_init = aarch64_cpu_class_init, 512 }; 513 514 static void aarch64_cpu_register_types(void) 515 { 516 const ARMCPUInfo *info = aarch64_cpus; 517 518 type_register_static(&aarch64_cpu_type_info); 519 520 while (info->name) { 521 aarch64_cpu_register(info); 522 info++; 523 } 524 } 525 526 type_init(aarch64_cpu_register_types) 527