1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #ifdef CONFIG_TCG 25 #include "hw/core/tcg-cpu-ops.h" 26 #endif /* CONFIG_TCG */ 27 #include "qemu/module.h" 28 #if !defined(CONFIG_USER_ONLY) 29 #include "hw/loader.h" 30 #endif 31 #include "sysemu/kvm.h" 32 #include "sysemu/hvf.h" 33 #include "kvm_arm.h" 34 #include "hvf_arm.h" 35 #include "qapi/visitor.h" 36 #include "hw/qdev-properties.h" 37 #include "internals.h" 38 39 40 static void aarch64_a57_initfn(Object *obj) 41 { 42 ARMCPU *cpu = ARM_CPU(obj); 43 44 cpu->dtb_compatible = "arm,cortex-a57"; 45 set_feature(&cpu->env, ARM_FEATURE_V8); 46 set_feature(&cpu->env, ARM_FEATURE_NEON); 47 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 48 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 49 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 50 set_feature(&cpu->env, ARM_FEATURE_EL2); 51 set_feature(&cpu->env, ARM_FEATURE_EL3); 52 set_feature(&cpu->env, ARM_FEATURE_PMU); 53 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 54 cpu->midr = 0x411fd070; 55 cpu->revidr = 0x00000000; 56 cpu->reset_fpsid = 0x41034070; 57 cpu->isar.mvfr0 = 0x10110222; 58 cpu->isar.mvfr1 = 0x12111111; 59 cpu->isar.mvfr2 = 0x00000043; 60 cpu->ctr = 0x8444c004; 61 cpu->reset_sctlr = 0x00c50838; 62 cpu->isar.id_pfr0 = 0x00000131; 63 cpu->isar.id_pfr1 = 0x00011011; 64 cpu->isar.id_dfr0 = 0x03010066; 65 cpu->id_afr0 = 0x00000000; 66 cpu->isar.id_mmfr0 = 0x10101105; 67 cpu->isar.id_mmfr1 = 0x40000000; 68 cpu->isar.id_mmfr2 = 0x01260000; 69 cpu->isar.id_mmfr3 = 0x02102211; 70 cpu->isar.id_isar0 = 0x02101110; 71 cpu->isar.id_isar1 = 0x13112111; 72 cpu->isar.id_isar2 = 0x21232042; 73 cpu->isar.id_isar3 = 0x01112131; 74 cpu->isar.id_isar4 = 0x00011142; 75 cpu->isar.id_isar5 = 0x00011121; 76 cpu->isar.id_isar6 = 0; 77 cpu->isar.id_aa64pfr0 = 0x00002222; 78 cpu->isar.id_aa64dfr0 = 0x10305106; 79 cpu->isar.id_aa64isar0 = 0x00011120; 80 cpu->isar.id_aa64mmfr0 = 0x00001124; 81 cpu->isar.dbgdidr = 0x3516d000; 82 cpu->isar.reset_pmcr_el0 = 0x41013000; 83 cpu->clidr = 0x0a200023; 84 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 85 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 86 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 87 cpu->dcz_blocksize = 4; /* 64 bytes */ 88 cpu->gic_num_lrs = 4; 89 cpu->gic_vpribits = 5; 90 cpu->gic_vprebits = 5; 91 cpu->gic_pribits = 5; 92 define_cortex_a72_a57_a53_cp_reginfo(cpu); 93 } 94 95 static void aarch64_a53_initfn(Object *obj) 96 { 97 ARMCPU *cpu = ARM_CPU(obj); 98 99 cpu->dtb_compatible = "arm,cortex-a53"; 100 set_feature(&cpu->env, ARM_FEATURE_V8); 101 set_feature(&cpu->env, ARM_FEATURE_NEON); 102 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 103 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 104 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 105 set_feature(&cpu->env, ARM_FEATURE_EL2); 106 set_feature(&cpu->env, ARM_FEATURE_EL3); 107 set_feature(&cpu->env, ARM_FEATURE_PMU); 108 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 109 cpu->midr = 0x410fd034; 110 cpu->revidr = 0x00000000; 111 cpu->reset_fpsid = 0x41034070; 112 cpu->isar.mvfr0 = 0x10110222; 113 cpu->isar.mvfr1 = 0x12111111; 114 cpu->isar.mvfr2 = 0x00000043; 115 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 116 cpu->reset_sctlr = 0x00c50838; 117 cpu->isar.id_pfr0 = 0x00000131; 118 cpu->isar.id_pfr1 = 0x00011011; 119 cpu->isar.id_dfr0 = 0x03010066; 120 cpu->id_afr0 = 0x00000000; 121 cpu->isar.id_mmfr0 = 0x10101105; 122 cpu->isar.id_mmfr1 = 0x40000000; 123 cpu->isar.id_mmfr2 = 0x01260000; 124 cpu->isar.id_mmfr3 = 0x02102211; 125 cpu->isar.id_isar0 = 0x02101110; 126 cpu->isar.id_isar1 = 0x13112111; 127 cpu->isar.id_isar2 = 0x21232042; 128 cpu->isar.id_isar3 = 0x01112131; 129 cpu->isar.id_isar4 = 0x00011142; 130 cpu->isar.id_isar5 = 0x00011121; 131 cpu->isar.id_isar6 = 0; 132 cpu->isar.id_aa64pfr0 = 0x00002222; 133 cpu->isar.id_aa64dfr0 = 0x10305106; 134 cpu->isar.id_aa64isar0 = 0x00011120; 135 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 136 cpu->isar.dbgdidr = 0x3516d000; 137 cpu->isar.reset_pmcr_el0 = 0x41033000; 138 cpu->clidr = 0x0a200023; 139 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 140 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 141 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 142 cpu->dcz_blocksize = 4; /* 64 bytes */ 143 cpu->gic_num_lrs = 4; 144 cpu->gic_vpribits = 5; 145 cpu->gic_vprebits = 5; 146 cpu->gic_pribits = 5; 147 define_cortex_a72_a57_a53_cp_reginfo(cpu); 148 } 149 150 static void aarch64_a72_initfn(Object *obj) 151 { 152 ARMCPU *cpu = ARM_CPU(obj); 153 154 cpu->dtb_compatible = "arm,cortex-a72"; 155 set_feature(&cpu->env, ARM_FEATURE_V8); 156 set_feature(&cpu->env, ARM_FEATURE_NEON); 157 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 158 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 159 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 160 set_feature(&cpu->env, ARM_FEATURE_EL2); 161 set_feature(&cpu->env, ARM_FEATURE_EL3); 162 set_feature(&cpu->env, ARM_FEATURE_PMU); 163 cpu->midr = 0x410fd083; 164 cpu->revidr = 0x00000000; 165 cpu->reset_fpsid = 0x41034080; 166 cpu->isar.mvfr0 = 0x10110222; 167 cpu->isar.mvfr1 = 0x12111111; 168 cpu->isar.mvfr2 = 0x00000043; 169 cpu->ctr = 0x8444c004; 170 cpu->reset_sctlr = 0x00c50838; 171 cpu->isar.id_pfr0 = 0x00000131; 172 cpu->isar.id_pfr1 = 0x00011011; 173 cpu->isar.id_dfr0 = 0x03010066; 174 cpu->id_afr0 = 0x00000000; 175 cpu->isar.id_mmfr0 = 0x10201105; 176 cpu->isar.id_mmfr1 = 0x40000000; 177 cpu->isar.id_mmfr2 = 0x01260000; 178 cpu->isar.id_mmfr3 = 0x02102211; 179 cpu->isar.id_isar0 = 0x02101110; 180 cpu->isar.id_isar1 = 0x13112111; 181 cpu->isar.id_isar2 = 0x21232042; 182 cpu->isar.id_isar3 = 0x01112131; 183 cpu->isar.id_isar4 = 0x00011142; 184 cpu->isar.id_isar5 = 0x00011121; 185 cpu->isar.id_aa64pfr0 = 0x00002222; 186 cpu->isar.id_aa64dfr0 = 0x10305106; 187 cpu->isar.id_aa64isar0 = 0x00011120; 188 cpu->isar.id_aa64mmfr0 = 0x00001124; 189 cpu->isar.dbgdidr = 0x3516d000; 190 cpu->isar.reset_pmcr_el0 = 0x41023000; 191 cpu->clidr = 0x0a200023; 192 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 193 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 194 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ 195 cpu->dcz_blocksize = 4; /* 64 bytes */ 196 cpu->gic_num_lrs = 4; 197 cpu->gic_vpribits = 5; 198 cpu->gic_vprebits = 5; 199 cpu->gic_pribits = 5; 200 define_cortex_a72_a57_a53_cp_reginfo(cpu); 201 } 202 203 static void aarch64_a76_initfn(Object *obj) 204 { 205 ARMCPU *cpu = ARM_CPU(obj); 206 207 cpu->dtb_compatible = "arm,cortex-a76"; 208 set_feature(&cpu->env, ARM_FEATURE_V8); 209 set_feature(&cpu->env, ARM_FEATURE_NEON); 210 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 211 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 212 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 213 set_feature(&cpu->env, ARM_FEATURE_EL2); 214 set_feature(&cpu->env, ARM_FEATURE_EL3); 215 set_feature(&cpu->env, ARM_FEATURE_PMU); 216 217 /* Ordered by B2.4 AArch64 registers by functional group */ 218 cpu->clidr = 0x82000023; 219 cpu->ctr = 0x8444C004; 220 cpu->dcz_blocksize = 4; 221 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; 222 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 223 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 224 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; 225 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 226 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 227 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 228 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; 229 cpu->id_afr0 = 0x00000000; 230 cpu->isar.id_dfr0 = 0x04010088; 231 cpu->isar.id_isar0 = 0x02101110; 232 cpu->isar.id_isar1 = 0x13112111; 233 cpu->isar.id_isar2 = 0x21232042; 234 cpu->isar.id_isar3 = 0x01112131; 235 cpu->isar.id_isar4 = 0x00010142; 236 cpu->isar.id_isar5 = 0x01011121; 237 cpu->isar.id_isar6 = 0x00000010; 238 cpu->isar.id_mmfr0 = 0x10201105; 239 cpu->isar.id_mmfr1 = 0x40000000; 240 cpu->isar.id_mmfr2 = 0x01260000; 241 cpu->isar.id_mmfr3 = 0x02122211; 242 cpu->isar.id_mmfr4 = 0x00021110; 243 cpu->isar.id_pfr0 = 0x10010131; 244 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 245 cpu->isar.id_pfr2 = 0x00000011; 246 cpu->midr = 0x414fd0b1; /* r4p1 */ 247 cpu->revidr = 0; 248 249 /* From B2.18 CCSIDR_EL1 */ 250 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 251 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 252 cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ 253 254 /* From B2.93 SCTLR_EL3 */ 255 cpu->reset_sctlr = 0x30c50838; 256 257 /* From B4.23 ICH_VTR_EL2 */ 258 cpu->gic_num_lrs = 4; 259 cpu->gic_vpribits = 5; 260 cpu->gic_vprebits = 5; 261 cpu->gic_pribits = 5; 262 263 /* From B5.1 AdvSIMD AArch64 register summary */ 264 cpu->isar.mvfr0 = 0x10110222; 265 cpu->isar.mvfr1 = 0x13211111; 266 cpu->isar.mvfr2 = 0x00000043; 267 268 /* From D5.1 AArch64 PMU register summary */ 269 cpu->isar.reset_pmcr_el0 = 0x410b3000; 270 } 271 272 static void aarch64_neoverse_n1_initfn(Object *obj) 273 { 274 ARMCPU *cpu = ARM_CPU(obj); 275 276 cpu->dtb_compatible = "arm,neoverse-n1"; 277 set_feature(&cpu->env, ARM_FEATURE_V8); 278 set_feature(&cpu->env, ARM_FEATURE_NEON); 279 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 280 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 281 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 282 set_feature(&cpu->env, ARM_FEATURE_EL2); 283 set_feature(&cpu->env, ARM_FEATURE_EL3); 284 set_feature(&cpu->env, ARM_FEATURE_PMU); 285 286 /* Ordered by B2.4 AArch64 registers by functional group */ 287 cpu->clidr = 0x82000023; 288 cpu->ctr = 0x8444c004; 289 cpu->dcz_blocksize = 4; 290 cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; 291 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 292 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 293 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; 294 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 295 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 296 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 297 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; 298 cpu->id_afr0 = 0x00000000; 299 cpu->isar.id_dfr0 = 0x04010088; 300 cpu->isar.id_isar0 = 0x02101110; 301 cpu->isar.id_isar1 = 0x13112111; 302 cpu->isar.id_isar2 = 0x21232042; 303 cpu->isar.id_isar3 = 0x01112131; 304 cpu->isar.id_isar4 = 0x00010142; 305 cpu->isar.id_isar5 = 0x01011121; 306 cpu->isar.id_isar6 = 0x00000010; 307 cpu->isar.id_mmfr0 = 0x10201105; 308 cpu->isar.id_mmfr1 = 0x40000000; 309 cpu->isar.id_mmfr2 = 0x01260000; 310 cpu->isar.id_mmfr3 = 0x02122211; 311 cpu->isar.id_mmfr4 = 0x00021110; 312 cpu->isar.id_pfr0 = 0x10010131; 313 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 314 cpu->isar.id_pfr2 = 0x00000011; 315 cpu->midr = 0x414fd0c1; /* r4p1 */ 316 cpu->revidr = 0; 317 318 /* From B2.23 CCSIDR_EL1 */ 319 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 320 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 321 cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ 322 323 /* From B2.98 SCTLR_EL3 */ 324 cpu->reset_sctlr = 0x30c50838; 325 326 /* From B4.23 ICH_VTR_EL2 */ 327 cpu->gic_num_lrs = 4; 328 cpu->gic_vpribits = 5; 329 cpu->gic_vprebits = 5; 330 cpu->gic_pribits = 5; 331 332 /* From B5.1 AdvSIMD AArch64 register summary */ 333 cpu->isar.mvfr0 = 0x10110222; 334 cpu->isar.mvfr1 = 0x13211111; 335 cpu->isar.mvfr2 = 0x00000043; 336 337 /* From D5.1 AArch64 PMU register summary */ 338 cpu->isar.reset_pmcr_el0 = 0x410c3000; 339 } 340 341 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) 342 { 343 /* 344 * If any vector lengths are explicitly enabled with sve<N> properties, 345 * then all other lengths are implicitly disabled. If sve-max-vq is 346 * specified then it is the same as explicitly enabling all lengths 347 * up to and including the specified maximum, which means all larger 348 * lengths will be implicitly disabled. If no sve<N> properties 349 * are enabled and sve-max-vq is not specified, then all lengths not 350 * explicitly disabled will be enabled. Additionally, all power-of-two 351 * vector lengths less than the maximum enabled length will be 352 * automatically enabled and all vector lengths larger than the largest 353 * disabled power-of-two vector length will be automatically disabled. 354 * Errors are generated if the user provided input that interferes with 355 * any of the above. Finally, if SVE is not disabled, then at least one 356 * vector length must be enabled. 357 */ 358 uint32_t vq_map = cpu->sve_vq.map; 359 uint32_t vq_init = cpu->sve_vq.init; 360 uint32_t vq_supported; 361 uint32_t vq_mask = 0; 362 uint32_t tmp, vq, max_vq = 0; 363 364 /* 365 * CPU models specify a set of supported vector lengths which are 366 * enabled by default. Attempting to enable any vector length not set 367 * in the supported bitmap results in an error. When KVM is enabled we 368 * fetch the supported bitmap from the host. 369 */ 370 if (kvm_enabled()) { 371 if (kvm_arm_sve_supported()) { 372 cpu->sve_vq.supported = kvm_arm_sve_get_vls(CPU(cpu)); 373 vq_supported = cpu->sve_vq.supported; 374 } else { 375 assert(!cpu_isar_feature(aa64_sve, cpu)); 376 vq_supported = 0; 377 } 378 } else { 379 vq_supported = cpu->sve_vq.supported; 380 } 381 382 /* 383 * Process explicit sve<N> properties. 384 * From the properties, sve_vq_map<N> implies sve_vq_init<N>. 385 * Check first for any sve<N> enabled. 386 */ 387 if (vq_map != 0) { 388 max_vq = 32 - clz32(vq_map); 389 vq_mask = MAKE_64BIT_MASK(0, max_vq); 390 391 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { 392 error_setg(errp, "cannot enable sve%d", max_vq * 128); 393 error_append_hint(errp, "sve%d is larger than the maximum vector " 394 "length, sve-max-vq=%d (%d bits)\n", 395 max_vq * 128, cpu->sve_max_vq, 396 cpu->sve_max_vq * 128); 397 return; 398 } 399 400 if (kvm_enabled()) { 401 /* 402 * For KVM we have to automatically enable all supported unitialized 403 * lengths, even when the smaller lengths are not all powers-of-two. 404 */ 405 vq_map |= vq_supported & ~vq_init & vq_mask; 406 } else { 407 /* Propagate enabled bits down through required powers-of-two. */ 408 vq_map |= SVE_VQ_POW2_MAP & ~vq_init & vq_mask; 409 } 410 } else if (cpu->sve_max_vq == 0) { 411 /* 412 * No explicit bits enabled, and no implicit bits from sve-max-vq. 413 */ 414 if (!cpu_isar_feature(aa64_sve, cpu)) { 415 /* SVE is disabled and so are all vector lengths. Good. */ 416 return; 417 } 418 419 if (kvm_enabled()) { 420 /* Disabling a supported length disables all larger lengths. */ 421 tmp = vq_init & vq_supported; 422 } else { 423 /* Disabling a power-of-two disables all larger lengths. */ 424 tmp = vq_init & SVE_VQ_POW2_MAP; 425 } 426 vq = ctz32(tmp) + 1; 427 428 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 429 vq_mask = MAKE_64BIT_MASK(0, max_vq); 430 vq_map = vq_supported & ~vq_init & vq_mask; 431 432 if (max_vq == 0 || vq_map == 0) { 433 error_setg(errp, "cannot disable sve%d", vq * 128); 434 error_append_hint(errp, "Disabling sve%d results in all " 435 "vector lengths being disabled.\n", 436 vq * 128); 437 error_append_hint(errp, "With SVE enabled, at least one " 438 "vector length must be enabled.\n"); 439 return; 440 } 441 442 max_vq = 32 - clz32(vq_map); 443 vq_mask = MAKE_64BIT_MASK(0, max_vq); 444 } 445 446 /* 447 * Process the sve-max-vq property. 448 * Note that we know from the above that no bit above 449 * sve-max-vq is currently set. 450 */ 451 if (cpu->sve_max_vq != 0) { 452 max_vq = cpu->sve_max_vq; 453 vq_mask = MAKE_64BIT_MASK(0, max_vq); 454 455 if (vq_init & ~vq_map & (1 << (max_vq - 1))) { 456 error_setg(errp, "cannot disable sve%d", max_vq * 128); 457 error_append_hint(errp, "The maximum vector length must be " 458 "enabled, sve-max-vq=%d (%d bits)\n", 459 max_vq, max_vq * 128); 460 return; 461 } 462 463 /* Set all bits not explicitly set within sve-max-vq. */ 464 vq_map |= ~vq_init & vq_mask; 465 } 466 467 /* 468 * We should know what max-vq is now. Also, as we're done 469 * manipulating sve-vq-map, we ensure any bits above max-vq 470 * are clear, just in case anybody looks. 471 */ 472 assert(max_vq != 0); 473 assert(vq_mask != 0); 474 vq_map &= vq_mask; 475 476 /* Ensure the set of lengths matches what is supported. */ 477 tmp = vq_map ^ (vq_supported & vq_mask); 478 if (tmp) { 479 vq = 32 - clz32(tmp); 480 if (vq_map & (1 << (vq - 1))) { 481 if (cpu->sve_max_vq) { 482 error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq); 483 error_append_hint(errp, "This CPU does not support " 484 "the vector length %d-bits.\n", vq * 128); 485 error_append_hint(errp, "It may not be possible to use " 486 "sve-max-vq with this CPU. Try " 487 "using only sve<N> properties.\n"); 488 } else { 489 error_setg(errp, "cannot enable sve%d", vq * 128); 490 if (vq_supported) { 491 error_append_hint(errp, "This CPU does not support " 492 "the vector length %d-bits.\n", vq * 128); 493 } else { 494 error_append_hint(errp, "SVE not supported by KVM " 495 "on this host\n"); 496 } 497 } 498 return; 499 } else { 500 if (kvm_enabled()) { 501 error_setg(errp, "cannot disable sve%d", vq * 128); 502 error_append_hint(errp, "The KVM host requires all " 503 "supported vector lengths smaller " 504 "than %d bits to also be enabled.\n", 505 max_vq * 128); 506 return; 507 } else { 508 /* Ensure all required powers-of-two are enabled. */ 509 tmp = SVE_VQ_POW2_MAP & vq_mask & ~vq_map; 510 if (tmp) { 511 vq = 32 - clz32(tmp); 512 error_setg(errp, "cannot disable sve%d", vq * 128); 513 error_append_hint(errp, "sve%d is required as it " 514 "is a power-of-two length smaller " 515 "than the maximum, sve%d\n", 516 vq * 128, max_vq * 128); 517 return; 518 } 519 } 520 } 521 } 522 523 /* 524 * Now that we validated all our vector lengths, the only question 525 * left to answer is if we even want SVE at all. 526 */ 527 if (!cpu_isar_feature(aa64_sve, cpu)) { 528 error_setg(errp, "cannot enable sve%d", max_vq * 128); 529 error_append_hint(errp, "SVE must be enabled to enable vector " 530 "lengths.\n"); 531 error_append_hint(errp, "Add sve=on to the CPU property list.\n"); 532 return; 533 } 534 535 /* From now on sve_max_vq is the actual maximum supported length. */ 536 cpu->sve_max_vq = max_vq; 537 cpu->sve_vq.map = vq_map; 538 } 539 540 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, 541 void *opaque, Error **errp) 542 { 543 ARMCPU *cpu = ARM_CPU(obj); 544 uint32_t value; 545 546 /* All vector lengths are disabled when SVE is off. */ 547 if (!cpu_isar_feature(aa64_sve, cpu)) { 548 value = 0; 549 } else { 550 value = cpu->sve_max_vq; 551 } 552 visit_type_uint32(v, name, &value, errp); 553 } 554 555 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, 556 void *opaque, Error **errp) 557 { 558 ARMCPU *cpu = ARM_CPU(obj); 559 uint32_t max_vq; 560 561 if (!visit_type_uint32(v, name, &max_vq, errp)) { 562 return; 563 } 564 565 if (kvm_enabled() && !kvm_arm_sve_supported()) { 566 error_setg(errp, "cannot set sve-max-vq"); 567 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 568 return; 569 } 570 571 if (max_vq == 0 || max_vq > ARM_MAX_VQ) { 572 error_setg(errp, "unsupported SVE vector length"); 573 error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", 574 ARM_MAX_VQ); 575 return; 576 } 577 578 cpu->sve_max_vq = max_vq; 579 } 580 581 /* 582 * Note that cpu_arm_{get,set}_vq cannot use the simpler 583 * object_property_add_bool interface because they make use of the 584 * contents of "name" to determine which bit on which to operate. 585 */ 586 static void cpu_arm_get_vq(Object *obj, Visitor *v, const char *name, 587 void *opaque, Error **errp) 588 { 589 ARMCPU *cpu = ARM_CPU(obj); 590 ARMVQMap *vq_map = opaque; 591 uint32_t vq = atoi(&name[3]) / 128; 592 bool sve = vq_map == &cpu->sve_vq; 593 bool value; 594 595 /* All vector lengths are disabled when feature is off. */ 596 if (sve 597 ? !cpu_isar_feature(aa64_sve, cpu) 598 : !cpu_isar_feature(aa64_sme, cpu)) { 599 value = false; 600 } else { 601 value = extract32(vq_map->map, vq - 1, 1); 602 } 603 visit_type_bool(v, name, &value, errp); 604 } 605 606 static void cpu_arm_set_vq(Object *obj, Visitor *v, const char *name, 607 void *opaque, Error **errp) 608 { 609 ARMVQMap *vq_map = opaque; 610 uint32_t vq = atoi(&name[3]) / 128; 611 bool value; 612 613 if (!visit_type_bool(v, name, &value, errp)) { 614 return; 615 } 616 617 vq_map->map = deposit32(vq_map->map, vq - 1, 1, value); 618 vq_map->init |= 1 << (vq - 1); 619 } 620 621 static bool cpu_arm_get_sve(Object *obj, Error **errp) 622 { 623 ARMCPU *cpu = ARM_CPU(obj); 624 return cpu_isar_feature(aa64_sve, cpu); 625 } 626 627 static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) 628 { 629 ARMCPU *cpu = ARM_CPU(obj); 630 uint64_t t; 631 632 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 633 error_setg(errp, "'sve' feature not supported by KVM on this host"); 634 return; 635 } 636 637 t = cpu->isar.id_aa64pfr0; 638 t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); 639 cpu->isar.id_aa64pfr0 = t; 640 } 641 642 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) 643 { 644 uint32_t vq_map = cpu->sme_vq.map; 645 uint32_t vq_init = cpu->sme_vq.init; 646 uint32_t vq_supported = cpu->sme_vq.supported; 647 uint32_t vq; 648 649 if (vq_map == 0) { 650 if (!cpu_isar_feature(aa64_sme, cpu)) { 651 cpu->isar.id_aa64smfr0 = 0; 652 return; 653 } 654 655 /* TODO: KVM will require limitations via SMCR_EL2. */ 656 vq_map = vq_supported & ~vq_init; 657 658 if (vq_map == 0) { 659 vq = ctz32(vq_supported) + 1; 660 error_setg(errp, "cannot disable sme%d", vq * 128); 661 error_append_hint(errp, "All SME vector lengths are disabled.\n"); 662 error_append_hint(errp, "With SME enabled, at least one " 663 "vector length must be enabled.\n"); 664 return; 665 } 666 } else { 667 if (!cpu_isar_feature(aa64_sme, cpu)) { 668 vq = 32 - clz32(vq_map); 669 error_setg(errp, "cannot enable sme%d", vq * 128); 670 error_append_hint(errp, "SME must be enabled to enable " 671 "vector lengths.\n"); 672 error_append_hint(errp, "Add sme=on to the CPU property list.\n"); 673 return; 674 } 675 /* TODO: KVM will require limitations via SMCR_EL2. */ 676 } 677 678 cpu->sme_vq.map = vq_map; 679 } 680 681 static bool cpu_arm_get_sme(Object *obj, Error **errp) 682 { 683 ARMCPU *cpu = ARM_CPU(obj); 684 return cpu_isar_feature(aa64_sme, cpu); 685 } 686 687 static void cpu_arm_set_sme(Object *obj, bool value, Error **errp) 688 { 689 ARMCPU *cpu = ARM_CPU(obj); 690 uint64_t t; 691 692 t = cpu->isar.id_aa64pfr1; 693 t = FIELD_DP64(t, ID_AA64PFR1, SME, value); 694 cpu->isar.id_aa64pfr1 = t; 695 } 696 697 static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp) 698 { 699 ARMCPU *cpu = ARM_CPU(obj); 700 return cpu_isar_feature(aa64_sme, cpu) && 701 cpu_isar_feature(aa64_sme_fa64, cpu); 702 } 703 704 static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp) 705 { 706 ARMCPU *cpu = ARM_CPU(obj); 707 uint64_t t; 708 709 t = cpu->isar.id_aa64smfr0; 710 t = FIELD_DP64(t, ID_AA64SMFR0, FA64, value); 711 cpu->isar.id_aa64smfr0 = t; 712 } 713 714 #ifdef CONFIG_USER_ONLY 715 /* Mirror linux /proc/sys/abi/{sve,sme}_default_vector_length. */ 716 static void cpu_arm_set_default_vec_len(Object *obj, Visitor *v, 717 const char *name, void *opaque, 718 Error **errp) 719 { 720 uint32_t *ptr_default_vq = opaque; 721 int32_t default_len, default_vq, remainder; 722 723 if (!visit_type_int32(v, name, &default_len, errp)) { 724 return; 725 } 726 727 /* Undocumented, but the kernel allows -1 to indicate "maximum". */ 728 if (default_len == -1) { 729 *ptr_default_vq = ARM_MAX_VQ; 730 return; 731 } 732 733 default_vq = default_len / 16; 734 remainder = default_len % 16; 735 736 /* 737 * Note that the 512 max comes from include/uapi/asm/sve_context.h 738 * and is the maximum architectural width of ZCR_ELx.LEN. 739 */ 740 if (remainder || default_vq < 1 || default_vq > 512) { 741 ARMCPU *cpu = ARM_CPU(obj); 742 const char *which = 743 (ptr_default_vq == &cpu->sve_default_vq ? "sve" : "sme"); 744 745 error_setg(errp, "cannot set %s-default-vector-length", which); 746 if (remainder) { 747 error_append_hint(errp, "Vector length not a multiple of 16\n"); 748 } else if (default_vq < 1) { 749 error_append_hint(errp, "Vector length smaller than 16\n"); 750 } else { 751 error_append_hint(errp, "Vector length larger than %d\n", 752 512 * 16); 753 } 754 return; 755 } 756 757 *ptr_default_vq = default_vq; 758 } 759 760 static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v, 761 const char *name, void *opaque, 762 Error **errp) 763 { 764 uint32_t *ptr_default_vq = opaque; 765 int32_t value = *ptr_default_vq * 16; 766 767 visit_type_int32(v, name, &value, errp); 768 } 769 #endif 770 771 static void aarch64_add_sve_properties(Object *obj) 772 { 773 ARMCPU *cpu = ARM_CPU(obj); 774 uint32_t vq; 775 776 object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); 777 778 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 779 char name[8]; 780 sprintf(name, "sve%d", vq * 128); 781 object_property_add(obj, name, "bool", cpu_arm_get_vq, 782 cpu_arm_set_vq, NULL, &cpu->sve_vq); 783 } 784 785 #ifdef CONFIG_USER_ONLY 786 /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ 787 object_property_add(obj, "sve-default-vector-length", "int32", 788 cpu_arm_get_default_vec_len, 789 cpu_arm_set_default_vec_len, NULL, 790 &cpu->sve_default_vq); 791 #endif 792 } 793 794 static void aarch64_add_sme_properties(Object *obj) 795 { 796 ARMCPU *cpu = ARM_CPU(obj); 797 uint32_t vq; 798 799 object_property_add_bool(obj, "sme", cpu_arm_get_sme, cpu_arm_set_sme); 800 object_property_add_bool(obj, "sme_fa64", cpu_arm_get_sme_fa64, 801 cpu_arm_set_sme_fa64); 802 803 for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) { 804 char name[8]; 805 sprintf(name, "sme%d", vq * 128); 806 object_property_add(obj, name, "bool", cpu_arm_get_vq, 807 cpu_arm_set_vq, NULL, &cpu->sme_vq); 808 } 809 810 #ifdef CONFIG_USER_ONLY 811 /* Mirror linux /proc/sys/abi/sme_default_vector_length. */ 812 object_property_add(obj, "sme-default-vector-length", "int32", 813 cpu_arm_get_default_vec_len, 814 cpu_arm_set_default_vec_len, NULL, 815 &cpu->sme_default_vq); 816 #endif 817 } 818 819 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) 820 { 821 int arch_val = 0, impdef_val = 0; 822 uint64_t t; 823 824 /* Exit early if PAuth is enabled, and fall through to disable it */ 825 if ((kvm_enabled() || hvf_enabled()) && cpu->prop_pauth) { 826 if (!cpu_isar_feature(aa64_pauth, cpu)) { 827 error_setg(errp, "'pauth' feature not supported by %s on this host", 828 kvm_enabled() ? "KVM" : "hvf"); 829 } 830 831 return; 832 } 833 834 /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ 835 if (cpu->prop_pauth) { 836 if (cpu->prop_pauth_impdef) { 837 impdef_val = 1; 838 } else { 839 arch_val = 1; 840 } 841 } else if (cpu->prop_pauth_impdef) { 842 error_setg(errp, "cannot enable pauth-impdef without pauth"); 843 error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); 844 } 845 846 t = cpu->isar.id_aa64isar1; 847 t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); 848 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); 849 t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); 850 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); 851 cpu->isar.id_aa64isar1 = t; 852 } 853 854 static Property arm_cpu_pauth_property = 855 DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); 856 static Property arm_cpu_pauth_impdef_property = 857 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); 858 859 static void aarch64_add_pauth_properties(Object *obj) 860 { 861 ARMCPU *cpu = ARM_CPU(obj); 862 863 /* Default to PAUTH on, with the architected algorithm on TCG. */ 864 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); 865 if (kvm_enabled() || hvf_enabled()) { 866 /* 867 * Mirror PAuth support from the probed sysregs back into the 868 * property for KVM or hvf. Is it just a bit backward? Yes it is! 869 * Note that prop_pauth is true whether the host CPU supports the 870 * architected QARMA5 algorithm or the IMPDEF one. We don't 871 * provide the separate pauth-impdef property for KVM or hvf, 872 * only for TCG. 873 */ 874 cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); 875 } else { 876 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); 877 } 878 } 879 880 static Property arm_cpu_lpa2_property = 881 DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); 882 883 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) 884 { 885 uint64_t t; 886 887 /* 888 * We only install the property for tcg -cpu max; this is the 889 * only situation in which the cpu field can be true. 890 */ 891 if (!cpu->prop_lpa2) { 892 return; 893 } 894 895 t = cpu->isar.id_aa64mmfr0; 896 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */ 897 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */ 898 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */ 899 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */ 900 cpu->isar.id_aa64mmfr0 = t; 901 } 902 903 static void aarch64_host_initfn(Object *obj) 904 { 905 #if defined(CONFIG_KVM) 906 ARMCPU *cpu = ARM_CPU(obj); 907 kvm_arm_set_cpu_features_from_host(cpu); 908 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 909 aarch64_add_sve_properties(obj); 910 aarch64_add_pauth_properties(obj); 911 } 912 #elif defined(CONFIG_HVF) 913 ARMCPU *cpu = ARM_CPU(obj); 914 hvf_arm_set_cpu_features_from_host(cpu); 915 aarch64_add_pauth_properties(obj); 916 #else 917 g_assert_not_reached(); 918 #endif 919 } 920 921 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 922 * otherwise, a CPU with as many features enabled as our emulation supports. 923 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; 924 * this only needs to handle 64 bits. 925 */ 926 static void aarch64_max_initfn(Object *obj) 927 { 928 ARMCPU *cpu = ARM_CPU(obj); 929 uint64_t t; 930 uint32_t u; 931 932 if (kvm_enabled() || hvf_enabled()) { 933 /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ 934 aarch64_host_initfn(obj); 935 return; 936 } 937 938 /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */ 939 940 aarch64_a57_initfn(obj); 941 942 /* 943 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real 944 * one and try to apply errata workarounds or use impdef features we 945 * don't provide. 946 * An IMPLEMENTER field of 0 means "reserved for software use"; 947 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers 948 * to see which features are present"; 949 * the VARIANT, PARTNUM and REVISION fields are all implementation 950 * defined and we choose to define PARTNUM just in case guest 951 * code needs to distinguish this QEMU CPU from other software 952 * implementations, though this shouldn't be needed. 953 */ 954 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); 955 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); 956 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); 957 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); 958 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); 959 cpu->midr = t; 960 961 /* 962 * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS} 963 * are zero. 964 */ 965 u = cpu->clidr; 966 u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); 967 u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0); 968 cpu->clidr = u; 969 970 t = cpu->isar.id_aa64isar0; 971 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ 972 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ 973 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ 974 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); 975 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ 976 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ 977 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ 978 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ 979 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ 980 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ 981 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ 982 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ 983 t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ 984 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ 985 cpu->isar.id_aa64isar0 = t; 986 987 t = cpu->isar.id_aa64isar1; 988 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ 989 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ 990 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ 991 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ 992 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ 993 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ 994 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ 995 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ 996 t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ 997 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ 998 cpu->isar.id_aa64isar1 = t; 999 1000 t = cpu->isar.id_aa64pfr0; 1001 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ 1002 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ 1003 t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */ 1004 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); 1005 t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ 1006 t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ 1007 t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ 1008 t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ 1009 cpu->isar.id_aa64pfr0 = t; 1010 1011 t = cpu->isar.id_aa64pfr1; 1012 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ 1013 t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ 1014 /* 1015 * Begin with full support for MTE. This will be downgraded to MTE=0 1016 * during realize if the board provides no tag memory, much like 1017 * we do for EL2 with the virtualization=on property. 1018 */ 1019 t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ 1020 t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ 1021 t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ 1022 cpu->isar.id_aa64pfr1 = t; 1023 1024 t = cpu->isar.id_aa64mmfr0; 1025 t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ 1026 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ 1027 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ 1028 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ 1029 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ 1030 cpu->isar.id_aa64mmfr0 = t; 1031 1032 t = cpu->isar.id_aa64mmfr1; 1033 t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ 1034 t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ 1035 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ 1036 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ 1037 t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ 1038 t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ 1039 t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ 1040 cpu->isar.id_aa64mmfr1 = t; 1041 1042 t = cpu->isar.id_aa64mmfr2; 1043 t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ 1044 t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ 1045 t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ 1046 t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ 1047 t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ 1048 t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ 1049 t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ 1050 t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ 1051 t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ 1052 cpu->isar.id_aa64mmfr2 = t; 1053 1054 t = cpu->isar.id_aa64zfr0; 1055 t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); 1056 t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ 1057 t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ 1058 t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ 1059 t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ 1060 t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ 1061 t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ 1062 t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ 1063 t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ 1064 cpu->isar.id_aa64zfr0 = t; 1065 1066 t = cpu->isar.id_aa64dfr0; 1067 t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ 1068 t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ 1069 cpu->isar.id_aa64dfr0 = t; 1070 1071 /* Replicate the same data to the 32-bit id registers. */ 1072 aa32_max_features(cpu); 1073 1074 #ifdef CONFIG_USER_ONLY 1075 /* 1076 * For usermode -cpu max we can use a larger and more efficient DCZ 1077 * blocksize since we don't have to follow what the hardware does. 1078 */ 1079 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 1080 cpu->dcz_blocksize = 7; /* 512 bytes */ 1081 #endif 1082 1083 cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); 1084 cpu->sme_vq.supported = SVE_VQ_POW2_MAP; 1085 1086 aarch64_add_pauth_properties(obj); 1087 aarch64_add_sve_properties(obj); 1088 aarch64_add_sme_properties(obj); 1089 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, 1090 cpu_max_set_sve_max_vq, NULL, NULL); 1091 qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); 1092 } 1093 1094 static void aarch64_a64fx_initfn(Object *obj) 1095 { 1096 ARMCPU *cpu = ARM_CPU(obj); 1097 1098 cpu->dtb_compatible = "arm,a64fx"; 1099 set_feature(&cpu->env, ARM_FEATURE_V8); 1100 set_feature(&cpu->env, ARM_FEATURE_NEON); 1101 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1102 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 1103 set_feature(&cpu->env, ARM_FEATURE_EL2); 1104 set_feature(&cpu->env, ARM_FEATURE_EL3); 1105 set_feature(&cpu->env, ARM_FEATURE_PMU); 1106 cpu->midr = 0x461f0010; 1107 cpu->revidr = 0x00000000; 1108 cpu->ctr = 0x86668006; 1109 cpu->reset_sctlr = 0x30000180; 1110 cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */ 1111 cpu->isar.id_aa64pfr1 = 0x0000000000000000; 1112 cpu->isar.id_aa64dfr0 = 0x0000000010305408; 1113 cpu->isar.id_aa64dfr1 = 0x0000000000000000; 1114 cpu->id_aa64afr0 = 0x0000000000000000; 1115 cpu->id_aa64afr1 = 0x0000000000000000; 1116 cpu->isar.id_aa64mmfr0 = 0x0000000000001122; 1117 cpu->isar.id_aa64mmfr1 = 0x0000000011212100; 1118 cpu->isar.id_aa64mmfr2 = 0x0000000000001011; 1119 cpu->isar.id_aa64isar0 = 0x0000000010211120; 1120 cpu->isar.id_aa64isar1 = 0x0000000000010001; 1121 cpu->isar.id_aa64zfr0 = 0x0000000000000000; 1122 cpu->clidr = 0x0000000080000023; 1123 cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */ 1124 cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */ 1125 cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */ 1126 cpu->dcz_blocksize = 6; /* 256 bytes */ 1127 cpu->gic_num_lrs = 4; 1128 cpu->gic_vpribits = 5; 1129 cpu->gic_vprebits = 5; 1130 cpu->gic_pribits = 5; 1131 1132 /* The A64FX supports only 128, 256 and 512 bit vector lengths */ 1133 aarch64_add_sve_properties(obj); 1134 cpu->sve_vq.supported = (1 << 0) /* 128bit */ 1135 | (1 << 1) /* 256bit */ 1136 | (1 << 3); /* 512bit */ 1137 1138 cpu->isar.reset_pmcr_el0 = 0x46014040; 1139 1140 /* TODO: Add A64FX specific HPC extension registers */ 1141 } 1142 1143 static const ARMCPUInfo aarch64_cpus[] = { 1144 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 1145 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 1146 { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, 1147 { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, 1148 { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, 1149 { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, 1150 { .name = "max", .initfn = aarch64_max_initfn }, 1151 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1152 { .name = "host", .initfn = aarch64_host_initfn }, 1153 #endif 1154 }; 1155 1156 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 1157 { 1158 ARMCPU *cpu = ARM_CPU(obj); 1159 1160 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 1161 } 1162 1163 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 1164 { 1165 ARMCPU *cpu = ARM_CPU(obj); 1166 1167 /* At this time, this property is only allowed if KVM is enabled. This 1168 * restriction allows us to avoid fixing up functionality that assumes a 1169 * uniform execution state like do_interrupt. 1170 */ 1171 if (value == false) { 1172 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 1173 error_setg(errp, "'aarch64' feature cannot be disabled " 1174 "unless KVM is enabled and 32-bit EL1 " 1175 "is supported"); 1176 return; 1177 } 1178 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 1179 } else { 1180 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 1181 } 1182 } 1183 1184 static void aarch64_cpu_finalizefn(Object *obj) 1185 { 1186 } 1187 1188 static gchar *aarch64_gdb_arch_name(CPUState *cs) 1189 { 1190 return g_strdup("aarch64"); 1191 } 1192 1193 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 1194 { 1195 CPUClass *cc = CPU_CLASS(oc); 1196 1197 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 1198 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 1199 cc->gdb_num_core_regs = 34; 1200 cc->gdb_core_xml_file = "aarch64-core.xml"; 1201 cc->gdb_arch_name = aarch64_gdb_arch_name; 1202 1203 object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, 1204 aarch64_cpu_set_aarch64); 1205 object_class_property_set_description(oc, "aarch64", 1206 "Set on/off to enable/disable aarch64 " 1207 "execution state "); 1208 } 1209 1210 static void aarch64_cpu_instance_init(Object *obj) 1211 { 1212 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 1213 1214 acc->info->initfn(obj); 1215 arm_cpu_post_init(obj); 1216 } 1217 1218 static void cpu_register_class_init(ObjectClass *oc, void *data) 1219 { 1220 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1221 1222 acc->info = data; 1223 } 1224 1225 void aarch64_cpu_register(const ARMCPUInfo *info) 1226 { 1227 TypeInfo type_info = { 1228 .parent = TYPE_AARCH64_CPU, 1229 .instance_size = sizeof(ARMCPU), 1230 .instance_init = aarch64_cpu_instance_init, 1231 .class_size = sizeof(ARMCPUClass), 1232 .class_init = info->class_init ?: cpu_register_class_init, 1233 .class_data = (void *)info, 1234 }; 1235 1236 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1237 type_register(&type_info); 1238 g_free((void *)type_info.name); 1239 } 1240 1241 static const TypeInfo aarch64_cpu_type_info = { 1242 .name = TYPE_AARCH64_CPU, 1243 .parent = TYPE_ARM_CPU, 1244 .instance_size = sizeof(ARMCPU), 1245 .instance_finalize = aarch64_cpu_finalizefn, 1246 .abstract = true, 1247 .class_size = sizeof(AArch64CPUClass), 1248 .class_init = aarch64_cpu_class_init, 1249 }; 1250 1251 static void aarch64_cpu_register_types(void) 1252 { 1253 size_t i; 1254 1255 type_register_static(&aarch64_cpu_type_info); 1256 1257 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { 1258 aarch64_cpu_register(&aarch64_cpus[i]); 1259 } 1260 } 1261 1262 type_init(aarch64_cpu_register_types) 1263