1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "qemu/module.h" 25 #if !defined(CONFIG_USER_ONLY) 26 #include "hw/loader.h" 27 #endif 28 #include "sysemu/kvm.h" 29 #include "kvm_arm.h" 30 #include "qapi/visitor.h" 31 #include "hw/qdev-properties.h" 32 33 34 #ifndef CONFIG_USER_ONLY 35 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 36 { 37 ARMCPU *cpu = env_archcpu(env); 38 39 /* Number of cores is in [25:24]; otherwise we RAZ */ 40 return (cpu->core_count - 1) << 24; 41 } 42 #endif 43 44 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { 45 #ifndef CONFIG_USER_ONLY 46 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, 47 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, 48 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 49 .writefn = arm_cp_write_ignore }, 50 { .name = "L2CTLR", 51 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, 52 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 53 .writefn = arm_cp_write_ignore }, 54 #endif 55 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, 56 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, 57 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 58 { .name = "L2ECTLR", 59 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, 60 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 61 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, 62 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, 63 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 64 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 65 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, 66 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 67 { .name = "CPUACTLR", 68 .cp = 15, .opc1 = 0, .crm = 15, 69 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 70 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 71 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, 72 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 73 { .name = "CPUECTLR", 74 .cp = 15, .opc1 = 1, .crm = 15, 75 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 76 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, 77 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, 78 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 79 { .name = "CPUMERRSR", 80 .cp = 15, .opc1 = 2, .crm = 15, 81 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 82 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, 83 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, 84 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 85 { .name = "L2MERRSR", 86 .cp = 15, .opc1 = 3, .crm = 15, 87 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 88 REGINFO_SENTINEL 89 }; 90 91 static void aarch64_a57_initfn(Object *obj) 92 { 93 ARMCPU *cpu = ARM_CPU(obj); 94 95 cpu->dtb_compatible = "arm,cortex-a57"; 96 set_feature(&cpu->env, ARM_FEATURE_V8); 97 set_feature(&cpu->env, ARM_FEATURE_NEON); 98 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 99 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 100 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 101 set_feature(&cpu->env, ARM_FEATURE_EL2); 102 set_feature(&cpu->env, ARM_FEATURE_EL3); 103 set_feature(&cpu->env, ARM_FEATURE_PMU); 104 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 105 cpu->midr = 0x411fd070; 106 cpu->revidr = 0x00000000; 107 cpu->reset_fpsid = 0x41034070; 108 cpu->isar.mvfr0 = 0x10110222; 109 cpu->isar.mvfr1 = 0x12111111; 110 cpu->isar.mvfr2 = 0x00000043; 111 cpu->ctr = 0x8444c004; 112 cpu->reset_sctlr = 0x00c50838; 113 cpu->isar.id_pfr0 = 0x00000131; 114 cpu->isar.id_pfr1 = 0x00011011; 115 cpu->isar.id_dfr0 = 0x03010066; 116 cpu->id_afr0 = 0x00000000; 117 cpu->isar.id_mmfr0 = 0x10101105; 118 cpu->isar.id_mmfr1 = 0x40000000; 119 cpu->isar.id_mmfr2 = 0x01260000; 120 cpu->isar.id_mmfr3 = 0x02102211; 121 cpu->isar.id_isar0 = 0x02101110; 122 cpu->isar.id_isar1 = 0x13112111; 123 cpu->isar.id_isar2 = 0x21232042; 124 cpu->isar.id_isar3 = 0x01112131; 125 cpu->isar.id_isar4 = 0x00011142; 126 cpu->isar.id_isar5 = 0x00011121; 127 cpu->isar.id_isar6 = 0; 128 cpu->isar.id_aa64pfr0 = 0x00002222; 129 cpu->isar.id_aa64dfr0 = 0x10305106; 130 cpu->isar.id_aa64isar0 = 0x00011120; 131 cpu->isar.id_aa64mmfr0 = 0x00001124; 132 cpu->isar.dbgdidr = 0x3516d000; 133 cpu->clidr = 0x0a200023; 134 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 135 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 136 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 137 cpu->dcz_blocksize = 4; /* 64 bytes */ 138 cpu->gic_num_lrs = 4; 139 cpu->gic_vpribits = 5; 140 cpu->gic_vprebits = 5; 141 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 142 } 143 144 static void aarch64_a53_initfn(Object *obj) 145 { 146 ARMCPU *cpu = ARM_CPU(obj); 147 148 cpu->dtb_compatible = "arm,cortex-a53"; 149 set_feature(&cpu->env, ARM_FEATURE_V8); 150 set_feature(&cpu->env, ARM_FEATURE_NEON); 151 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 152 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 153 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 154 set_feature(&cpu->env, ARM_FEATURE_EL2); 155 set_feature(&cpu->env, ARM_FEATURE_EL3); 156 set_feature(&cpu->env, ARM_FEATURE_PMU); 157 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 158 cpu->midr = 0x410fd034; 159 cpu->revidr = 0x00000000; 160 cpu->reset_fpsid = 0x41034070; 161 cpu->isar.mvfr0 = 0x10110222; 162 cpu->isar.mvfr1 = 0x12111111; 163 cpu->isar.mvfr2 = 0x00000043; 164 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 165 cpu->reset_sctlr = 0x00c50838; 166 cpu->isar.id_pfr0 = 0x00000131; 167 cpu->isar.id_pfr1 = 0x00011011; 168 cpu->isar.id_dfr0 = 0x03010066; 169 cpu->id_afr0 = 0x00000000; 170 cpu->isar.id_mmfr0 = 0x10101105; 171 cpu->isar.id_mmfr1 = 0x40000000; 172 cpu->isar.id_mmfr2 = 0x01260000; 173 cpu->isar.id_mmfr3 = 0x02102211; 174 cpu->isar.id_isar0 = 0x02101110; 175 cpu->isar.id_isar1 = 0x13112111; 176 cpu->isar.id_isar2 = 0x21232042; 177 cpu->isar.id_isar3 = 0x01112131; 178 cpu->isar.id_isar4 = 0x00011142; 179 cpu->isar.id_isar5 = 0x00011121; 180 cpu->isar.id_isar6 = 0; 181 cpu->isar.id_aa64pfr0 = 0x00002222; 182 cpu->isar.id_aa64dfr0 = 0x10305106; 183 cpu->isar.id_aa64isar0 = 0x00011120; 184 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 185 cpu->isar.dbgdidr = 0x3516d000; 186 cpu->clidr = 0x0a200023; 187 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 188 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 189 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 190 cpu->dcz_blocksize = 4; /* 64 bytes */ 191 cpu->gic_num_lrs = 4; 192 cpu->gic_vpribits = 5; 193 cpu->gic_vprebits = 5; 194 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 195 } 196 197 static void aarch64_a72_initfn(Object *obj) 198 { 199 ARMCPU *cpu = ARM_CPU(obj); 200 201 cpu->dtb_compatible = "arm,cortex-a72"; 202 set_feature(&cpu->env, ARM_FEATURE_V8); 203 set_feature(&cpu->env, ARM_FEATURE_NEON); 204 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 205 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 206 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 207 set_feature(&cpu->env, ARM_FEATURE_EL2); 208 set_feature(&cpu->env, ARM_FEATURE_EL3); 209 set_feature(&cpu->env, ARM_FEATURE_PMU); 210 cpu->midr = 0x410fd083; 211 cpu->revidr = 0x00000000; 212 cpu->reset_fpsid = 0x41034080; 213 cpu->isar.mvfr0 = 0x10110222; 214 cpu->isar.mvfr1 = 0x12111111; 215 cpu->isar.mvfr2 = 0x00000043; 216 cpu->ctr = 0x8444c004; 217 cpu->reset_sctlr = 0x00c50838; 218 cpu->isar.id_pfr0 = 0x00000131; 219 cpu->isar.id_pfr1 = 0x00011011; 220 cpu->isar.id_dfr0 = 0x03010066; 221 cpu->id_afr0 = 0x00000000; 222 cpu->isar.id_mmfr0 = 0x10201105; 223 cpu->isar.id_mmfr1 = 0x40000000; 224 cpu->isar.id_mmfr2 = 0x01260000; 225 cpu->isar.id_mmfr3 = 0x02102211; 226 cpu->isar.id_isar0 = 0x02101110; 227 cpu->isar.id_isar1 = 0x13112111; 228 cpu->isar.id_isar2 = 0x21232042; 229 cpu->isar.id_isar3 = 0x01112131; 230 cpu->isar.id_isar4 = 0x00011142; 231 cpu->isar.id_isar5 = 0x00011121; 232 cpu->isar.id_aa64pfr0 = 0x00002222; 233 cpu->isar.id_aa64dfr0 = 0x10305106; 234 cpu->isar.id_aa64isar0 = 0x00011120; 235 cpu->isar.id_aa64mmfr0 = 0x00001124; 236 cpu->isar.dbgdidr = 0x3516d000; 237 cpu->clidr = 0x0a200023; 238 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 239 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 240 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ 241 cpu->dcz_blocksize = 4; /* 64 bytes */ 242 cpu->gic_num_lrs = 4; 243 cpu->gic_vpribits = 5; 244 cpu->gic_vprebits = 5; 245 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 246 } 247 248 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) 249 { 250 /* 251 * If any vector lengths are explicitly enabled with sve<N> properties, 252 * then all other lengths are implicitly disabled. If sve-max-vq is 253 * specified then it is the same as explicitly enabling all lengths 254 * up to and including the specified maximum, which means all larger 255 * lengths will be implicitly disabled. If no sve<N> properties 256 * are enabled and sve-max-vq is not specified, then all lengths not 257 * explicitly disabled will be enabled. Additionally, all power-of-two 258 * vector lengths less than the maximum enabled length will be 259 * automatically enabled and all vector lengths larger than the largest 260 * disabled power-of-two vector length will be automatically disabled. 261 * Errors are generated if the user provided input that interferes with 262 * any of the above. Finally, if SVE is not disabled, then at least one 263 * vector length must be enabled. 264 */ 265 DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ); 266 DECLARE_BITMAP(tmp, ARM_MAX_VQ); 267 uint32_t vq, max_vq = 0; 268 269 /* Collect the set of vector lengths supported by KVM. */ 270 bitmap_zero(kvm_supported, ARM_MAX_VQ); 271 if (kvm_enabled() && kvm_arm_sve_supported()) { 272 kvm_arm_sve_get_vls(CPU(cpu), kvm_supported); 273 } else if (kvm_enabled()) { 274 assert(!cpu_isar_feature(aa64_sve, cpu)); 275 } 276 277 /* 278 * Process explicit sve<N> properties. 279 * From the properties, sve_vq_map<N> implies sve_vq_init<N>. 280 * Check first for any sve<N> enabled. 281 */ 282 if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) { 283 max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; 284 285 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { 286 error_setg(errp, "cannot enable sve%d", max_vq * 128); 287 error_append_hint(errp, "sve%d is larger than the maximum vector " 288 "length, sve-max-vq=%d (%d bits)\n", 289 max_vq * 128, cpu->sve_max_vq, 290 cpu->sve_max_vq * 128); 291 return; 292 } 293 294 if (kvm_enabled()) { 295 /* 296 * For KVM we have to automatically enable all supported unitialized 297 * lengths, even when the smaller lengths are not all powers-of-two. 298 */ 299 bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq); 300 bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); 301 } else { 302 /* Propagate enabled bits down through required powers-of-two. */ 303 for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { 304 if (!test_bit(vq - 1, cpu->sve_vq_init)) { 305 set_bit(vq - 1, cpu->sve_vq_map); 306 } 307 } 308 } 309 } else if (cpu->sve_max_vq == 0) { 310 /* 311 * No explicit bits enabled, and no implicit bits from sve-max-vq. 312 */ 313 if (!cpu_isar_feature(aa64_sve, cpu)) { 314 /* SVE is disabled and so are all vector lengths. Good. */ 315 return; 316 } 317 318 if (kvm_enabled()) { 319 /* Disabling a supported length disables all larger lengths. */ 320 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 321 if (test_bit(vq - 1, cpu->sve_vq_init) && 322 test_bit(vq - 1, kvm_supported)) { 323 break; 324 } 325 } 326 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 327 bitmap_andnot(cpu->sve_vq_map, kvm_supported, 328 cpu->sve_vq_init, max_vq); 329 if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) { 330 error_setg(errp, "cannot disable sve%d", vq * 128); 331 error_append_hint(errp, "Disabling sve%d results in all " 332 "vector lengths being disabled.\n", 333 vq * 128); 334 error_append_hint(errp, "With SVE enabled, at least one " 335 "vector length must be enabled.\n"); 336 return; 337 } 338 } else { 339 /* Disabling a power-of-two disables all larger lengths. */ 340 if (test_bit(0, cpu->sve_vq_init)) { 341 error_setg(errp, "cannot disable sve128"); 342 error_append_hint(errp, "Disabling sve128 results in all " 343 "vector lengths being disabled.\n"); 344 error_append_hint(errp, "With SVE enabled, at least one " 345 "vector length must be enabled.\n"); 346 return; 347 } 348 for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) { 349 if (test_bit(vq - 1, cpu->sve_vq_init)) { 350 break; 351 } 352 } 353 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 354 bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq); 355 } 356 357 max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1; 358 } 359 360 /* 361 * Process the sve-max-vq property. 362 * Note that we know from the above that no bit above 363 * sve-max-vq is currently set. 364 */ 365 if (cpu->sve_max_vq != 0) { 366 max_vq = cpu->sve_max_vq; 367 368 if (!test_bit(max_vq - 1, cpu->sve_vq_map) && 369 test_bit(max_vq - 1, cpu->sve_vq_init)) { 370 error_setg(errp, "cannot disable sve%d", max_vq * 128); 371 error_append_hint(errp, "The maximum vector length must be " 372 "enabled, sve-max-vq=%d (%d bits)\n", 373 max_vq, max_vq * 128); 374 return; 375 } 376 377 /* Set all bits not explicitly set within sve-max-vq. */ 378 bitmap_complement(tmp, cpu->sve_vq_init, max_vq); 379 bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); 380 } 381 382 /* 383 * We should know what max-vq is now. Also, as we're done 384 * manipulating sve-vq-map, we ensure any bits above max-vq 385 * are clear, just in case anybody looks. 386 */ 387 assert(max_vq != 0); 388 bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq); 389 390 if (kvm_enabled()) { 391 /* Ensure the set of lengths matches what KVM supports. */ 392 bitmap_xor(tmp, cpu->sve_vq_map, kvm_supported, max_vq); 393 if (!bitmap_empty(tmp, max_vq)) { 394 vq = find_last_bit(tmp, max_vq) + 1; 395 if (test_bit(vq - 1, cpu->sve_vq_map)) { 396 if (cpu->sve_max_vq) { 397 error_setg(errp, "cannot set sve-max-vq=%d", 398 cpu->sve_max_vq); 399 error_append_hint(errp, "This KVM host does not support " 400 "the vector length %d-bits.\n", 401 vq * 128); 402 error_append_hint(errp, "It may not be possible to use " 403 "sve-max-vq with this KVM host. Try " 404 "using only sve<N> properties.\n"); 405 } else { 406 error_setg(errp, "cannot enable sve%d", vq * 128); 407 error_append_hint(errp, "This KVM host does not support " 408 "the vector length %d-bits.\n", 409 vq * 128); 410 } 411 } else { 412 error_setg(errp, "cannot disable sve%d", vq * 128); 413 error_append_hint(errp, "The KVM host requires all " 414 "supported vector lengths smaller " 415 "than %d bits to also be enabled.\n", 416 max_vq * 128); 417 } 418 return; 419 } 420 } else { 421 /* Ensure all required powers-of-two are enabled. */ 422 for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { 423 if (!test_bit(vq - 1, cpu->sve_vq_map)) { 424 error_setg(errp, "cannot disable sve%d", vq * 128); 425 error_append_hint(errp, "sve%d is required as it " 426 "is a power-of-two length smaller than " 427 "the maximum, sve%d\n", 428 vq * 128, max_vq * 128); 429 return; 430 } 431 } 432 } 433 434 /* 435 * Now that we validated all our vector lengths, the only question 436 * left to answer is if we even want SVE at all. 437 */ 438 if (!cpu_isar_feature(aa64_sve, cpu)) { 439 error_setg(errp, "cannot enable sve%d", max_vq * 128); 440 error_append_hint(errp, "SVE must be enabled to enable vector " 441 "lengths.\n"); 442 error_append_hint(errp, "Add sve=on to the CPU property list.\n"); 443 return; 444 } 445 446 /* From now on sve_max_vq is the actual maximum supported length. */ 447 cpu->sve_max_vq = max_vq; 448 } 449 450 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, 451 void *opaque, Error **errp) 452 { 453 ARMCPU *cpu = ARM_CPU(obj); 454 uint32_t value; 455 456 /* All vector lengths are disabled when SVE is off. */ 457 if (!cpu_isar_feature(aa64_sve, cpu)) { 458 value = 0; 459 } else { 460 value = cpu->sve_max_vq; 461 } 462 visit_type_uint32(v, name, &value, errp); 463 } 464 465 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, 466 void *opaque, Error **errp) 467 { 468 ARMCPU *cpu = ARM_CPU(obj); 469 uint32_t max_vq; 470 471 if (!visit_type_uint32(v, name, &max_vq, errp)) { 472 return; 473 } 474 475 if (kvm_enabled() && !kvm_arm_sve_supported()) { 476 error_setg(errp, "cannot set sve-max-vq"); 477 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 478 return; 479 } 480 481 if (max_vq == 0 || max_vq > ARM_MAX_VQ) { 482 error_setg(errp, "unsupported SVE vector length"); 483 error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", 484 ARM_MAX_VQ); 485 return; 486 } 487 488 cpu->sve_max_vq = max_vq; 489 } 490 491 /* 492 * Note that cpu_arm_get/set_sve_vq cannot use the simpler 493 * object_property_add_bool interface because they make use 494 * of the contents of "name" to determine which bit on which 495 * to operate. 496 */ 497 static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, 498 void *opaque, Error **errp) 499 { 500 ARMCPU *cpu = ARM_CPU(obj); 501 uint32_t vq = atoi(&name[3]) / 128; 502 bool value; 503 504 /* All vector lengths are disabled when SVE is off. */ 505 if (!cpu_isar_feature(aa64_sve, cpu)) { 506 value = false; 507 } else { 508 value = test_bit(vq - 1, cpu->sve_vq_map); 509 } 510 visit_type_bool(v, name, &value, errp); 511 } 512 513 static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, 514 void *opaque, Error **errp) 515 { 516 ARMCPU *cpu = ARM_CPU(obj); 517 uint32_t vq = atoi(&name[3]) / 128; 518 bool value; 519 520 if (!visit_type_bool(v, name, &value, errp)) { 521 return; 522 } 523 524 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 525 error_setg(errp, "cannot enable %s", name); 526 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 527 return; 528 } 529 530 if (value) { 531 set_bit(vq - 1, cpu->sve_vq_map); 532 } else { 533 clear_bit(vq - 1, cpu->sve_vq_map); 534 } 535 set_bit(vq - 1, cpu->sve_vq_init); 536 } 537 538 static bool cpu_arm_get_sve(Object *obj, Error **errp) 539 { 540 ARMCPU *cpu = ARM_CPU(obj); 541 return cpu_isar_feature(aa64_sve, cpu); 542 } 543 544 static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) 545 { 546 ARMCPU *cpu = ARM_CPU(obj); 547 uint64_t t; 548 549 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 550 error_setg(errp, "'sve' feature not supported by KVM on this host"); 551 return; 552 } 553 554 t = cpu->isar.id_aa64pfr0; 555 t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); 556 cpu->isar.id_aa64pfr0 = t; 557 } 558 559 void aarch64_add_sve_properties(Object *obj) 560 { 561 uint32_t vq; 562 563 object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); 564 565 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 566 char name[8]; 567 sprintf(name, "sve%d", vq * 128); 568 object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, 569 cpu_arm_set_sve_vq, NULL, NULL); 570 } 571 } 572 573 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) 574 { 575 int arch_val = 0, impdef_val = 0; 576 uint64_t t; 577 578 /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ 579 if (cpu->prop_pauth) { 580 if (cpu->prop_pauth_impdef) { 581 impdef_val = 1; 582 } else { 583 arch_val = 1; 584 } 585 } else if (cpu->prop_pauth_impdef) { 586 error_setg(errp, "cannot enable pauth-impdef without pauth"); 587 error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); 588 } 589 590 t = cpu->isar.id_aa64isar1; 591 t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); 592 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); 593 t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); 594 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); 595 cpu->isar.id_aa64isar1 = t; 596 } 597 598 static Property arm_cpu_pauth_property = 599 DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); 600 static Property arm_cpu_pauth_impdef_property = 601 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); 602 603 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 604 * otherwise, a CPU with as many features enabled as our emulation supports. 605 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; 606 * this only needs to handle 64 bits. 607 */ 608 static void aarch64_max_initfn(Object *obj) 609 { 610 ARMCPU *cpu = ARM_CPU(obj); 611 612 if (kvm_enabled()) { 613 kvm_arm_set_cpu_features_from_host(cpu); 614 } else { 615 uint64_t t; 616 uint32_t u; 617 aarch64_a57_initfn(obj); 618 619 /* 620 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real 621 * one and try to apply errata workarounds or use impdef features we 622 * don't provide. 623 * An IMPLEMENTER field of 0 means "reserved for software use"; 624 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers 625 * to see which features are present"; 626 * the VARIANT, PARTNUM and REVISION fields are all implementation 627 * defined and we choose to define PARTNUM just in case guest 628 * code needs to distinguish this QEMU CPU from other software 629 * implementations, though this shouldn't be needed. 630 */ 631 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); 632 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); 633 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); 634 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); 635 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); 636 cpu->midr = t; 637 638 t = cpu->isar.id_aa64isar0; 639 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ 640 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); 641 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ 642 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); 643 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); 644 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); 645 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); 646 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); 647 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); 648 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); 649 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); 650 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ 651 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); 652 cpu->isar.id_aa64isar0 = t; 653 654 t = cpu->isar.id_aa64isar1; 655 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); 656 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); 657 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); 658 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); 659 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); 660 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); 661 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ 662 cpu->isar.id_aa64isar1 = t; 663 664 t = cpu->isar.id_aa64pfr0; 665 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); 666 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); 667 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); 668 t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); 669 cpu->isar.id_aa64pfr0 = t; 670 671 t = cpu->isar.id_aa64pfr1; 672 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); 673 /* 674 * Begin with full support for MTE. This will be downgraded to MTE=0 675 * during realize if the board provides no tag memory, much like 676 * we do for EL2 with the virtualization=on property. 677 */ 678 t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); 679 cpu->isar.id_aa64pfr1 = t; 680 681 t = cpu->isar.id_aa64mmfr0; 682 t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ 683 cpu->isar.id_aa64mmfr0 = t; 684 685 t = cpu->isar.id_aa64mmfr1; 686 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ 687 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); 688 t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); 689 t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ 690 t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ 691 t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ 692 cpu->isar.id_aa64mmfr1 = t; 693 694 t = cpu->isar.id_aa64mmfr2; 695 t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); 696 t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ 697 t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ 698 cpu->isar.id_aa64mmfr2 = t; 699 700 /* Replicate the same data to the 32-bit id registers. */ 701 u = cpu->isar.id_isar5; 702 u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ 703 u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); 704 u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); 705 u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); 706 u = FIELD_DP32(u, ID_ISAR5, RDM, 1); 707 u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); 708 cpu->isar.id_isar5 = u; 709 710 u = cpu->isar.id_isar6; 711 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); 712 u = FIELD_DP32(u, ID_ISAR6, DP, 1); 713 u = FIELD_DP32(u, ID_ISAR6, FHM, 1); 714 u = FIELD_DP32(u, ID_ISAR6, SB, 1); 715 u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); 716 cpu->isar.id_isar6 = u; 717 718 u = cpu->isar.id_mmfr3; 719 u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ 720 cpu->isar.id_mmfr3 = u; 721 722 u = cpu->isar.id_mmfr4; 723 u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ 724 u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 725 u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ 726 u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ 727 cpu->isar.id_mmfr4 = u; 728 729 t = cpu->isar.id_aa64dfr0; 730 t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ 731 cpu->isar.id_aa64dfr0 = t; 732 733 u = cpu->isar.id_dfr0; 734 u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ 735 cpu->isar.id_dfr0 = u; 736 737 u = cpu->isar.mvfr1; 738 u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ 739 u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ 740 cpu->isar.mvfr1 = u; 741 742 #ifdef CONFIG_USER_ONLY 743 /* For usermode -cpu max we can use a larger and more efficient DCZ 744 * blocksize since we don't have to follow what the hardware does. 745 */ 746 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 747 cpu->dcz_blocksize = 7; /* 512 bytes */ 748 #endif 749 750 /* Default to PAUTH on, with the architected algorithm. */ 751 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); 752 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); 753 } 754 755 aarch64_add_sve_properties(obj); 756 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, 757 cpu_max_set_sve_max_vq, NULL, NULL); 758 } 759 760 static const ARMCPUInfo aarch64_cpus[] = { 761 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 762 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 763 { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, 764 { .name = "max", .initfn = aarch64_max_initfn }, 765 }; 766 767 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 768 { 769 ARMCPU *cpu = ARM_CPU(obj); 770 771 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 772 } 773 774 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 775 { 776 ARMCPU *cpu = ARM_CPU(obj); 777 778 /* At this time, this property is only allowed if KVM is enabled. This 779 * restriction allows us to avoid fixing up functionality that assumes a 780 * uniform execution state like do_interrupt. 781 */ 782 if (value == false) { 783 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 784 error_setg(errp, "'aarch64' feature cannot be disabled " 785 "unless KVM is enabled and 32-bit EL1 " 786 "is supported"); 787 return; 788 } 789 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 790 } else { 791 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 792 } 793 } 794 795 static void aarch64_cpu_finalizefn(Object *obj) 796 { 797 } 798 799 static gchar *aarch64_gdb_arch_name(CPUState *cs) 800 { 801 return g_strdup("aarch64"); 802 } 803 804 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 805 { 806 CPUClass *cc = CPU_CLASS(oc); 807 808 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 809 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 810 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 811 cc->gdb_num_core_regs = 34; 812 cc->gdb_core_xml_file = "aarch64-core.xml"; 813 cc->gdb_arch_name = aarch64_gdb_arch_name; 814 815 object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, 816 aarch64_cpu_set_aarch64); 817 object_class_property_set_description(oc, "aarch64", 818 "Set on/off to enable/disable aarch64 " 819 "execution state "); 820 } 821 822 static void aarch64_cpu_instance_init(Object *obj) 823 { 824 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 825 826 acc->info->initfn(obj); 827 arm_cpu_post_init(obj); 828 } 829 830 static void cpu_register_class_init(ObjectClass *oc, void *data) 831 { 832 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 833 834 acc->info = data; 835 } 836 837 void aarch64_cpu_register(const ARMCPUInfo *info) 838 { 839 TypeInfo type_info = { 840 .parent = TYPE_AARCH64_CPU, 841 .instance_size = sizeof(ARMCPU), 842 .instance_init = aarch64_cpu_instance_init, 843 .class_size = sizeof(ARMCPUClass), 844 .class_init = info->class_init ?: cpu_register_class_init, 845 .class_data = (void *)info, 846 }; 847 848 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 849 type_register(&type_info); 850 g_free((void *)type_info.name); 851 } 852 853 static const TypeInfo aarch64_cpu_type_info = { 854 .name = TYPE_AARCH64_CPU, 855 .parent = TYPE_ARM_CPU, 856 .instance_size = sizeof(ARMCPU), 857 .instance_finalize = aarch64_cpu_finalizefn, 858 .abstract = true, 859 .class_size = sizeof(AArch64CPUClass), 860 .class_init = aarch64_cpu_class_init, 861 }; 862 863 static void aarch64_cpu_register_types(void) 864 { 865 size_t i; 866 867 type_register_static(&aarch64_cpu_type_info); 868 869 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { 870 aarch64_cpu_register(&aarch64_cpus[i]); 871 } 872 } 873 874 type_init(aarch64_cpu_register_types) 875