1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #ifdef CONFIG_TCG 25 #include "hw/core/tcg-cpu-ops.h" 26 #endif /* CONFIG_TCG */ 27 #include "qemu/module.h" 28 #if !defined(CONFIG_USER_ONLY) 29 #include "hw/loader.h" 30 #endif 31 #include "sysemu/kvm.h" 32 #include "sysemu/hvf.h" 33 #include "kvm_arm.h" 34 #include "hvf_arm.h" 35 #include "qapi/visitor.h" 36 #include "hw/qdev-properties.h" 37 #include "internals.h" 38 39 40 static void aarch64_a57_initfn(Object *obj) 41 { 42 ARMCPU *cpu = ARM_CPU(obj); 43 44 cpu->dtb_compatible = "arm,cortex-a57"; 45 set_feature(&cpu->env, ARM_FEATURE_V8); 46 set_feature(&cpu->env, ARM_FEATURE_NEON); 47 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 48 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 49 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 50 set_feature(&cpu->env, ARM_FEATURE_EL2); 51 set_feature(&cpu->env, ARM_FEATURE_EL3); 52 set_feature(&cpu->env, ARM_FEATURE_PMU); 53 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 54 cpu->midr = 0x411fd070; 55 cpu->revidr = 0x00000000; 56 cpu->reset_fpsid = 0x41034070; 57 cpu->isar.mvfr0 = 0x10110222; 58 cpu->isar.mvfr1 = 0x12111111; 59 cpu->isar.mvfr2 = 0x00000043; 60 cpu->ctr = 0x8444c004; 61 cpu->reset_sctlr = 0x00c50838; 62 cpu->isar.id_pfr0 = 0x00000131; 63 cpu->isar.id_pfr1 = 0x00011011; 64 cpu->isar.id_dfr0 = 0x03010066; 65 cpu->id_afr0 = 0x00000000; 66 cpu->isar.id_mmfr0 = 0x10101105; 67 cpu->isar.id_mmfr1 = 0x40000000; 68 cpu->isar.id_mmfr2 = 0x01260000; 69 cpu->isar.id_mmfr3 = 0x02102211; 70 cpu->isar.id_isar0 = 0x02101110; 71 cpu->isar.id_isar1 = 0x13112111; 72 cpu->isar.id_isar2 = 0x21232042; 73 cpu->isar.id_isar3 = 0x01112131; 74 cpu->isar.id_isar4 = 0x00011142; 75 cpu->isar.id_isar5 = 0x00011121; 76 cpu->isar.id_isar6 = 0; 77 cpu->isar.id_aa64pfr0 = 0x00002222; 78 cpu->isar.id_aa64dfr0 = 0x10305106; 79 cpu->isar.id_aa64isar0 = 0x00011120; 80 cpu->isar.id_aa64mmfr0 = 0x00001124; 81 cpu->isar.dbgdidr = 0x3516d000; 82 cpu->isar.reset_pmcr_el0 = 0x41013000; 83 cpu->clidr = 0x0a200023; 84 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 85 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 86 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 87 cpu->dcz_blocksize = 4; /* 64 bytes */ 88 cpu->gic_num_lrs = 4; 89 cpu->gic_vpribits = 5; 90 cpu->gic_vprebits = 5; 91 cpu->gic_pribits = 5; 92 define_cortex_a72_a57_a53_cp_reginfo(cpu); 93 } 94 95 static void aarch64_a53_initfn(Object *obj) 96 { 97 ARMCPU *cpu = ARM_CPU(obj); 98 99 cpu->dtb_compatible = "arm,cortex-a53"; 100 set_feature(&cpu->env, ARM_FEATURE_V8); 101 set_feature(&cpu->env, ARM_FEATURE_NEON); 102 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 103 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 104 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 105 set_feature(&cpu->env, ARM_FEATURE_EL2); 106 set_feature(&cpu->env, ARM_FEATURE_EL3); 107 set_feature(&cpu->env, ARM_FEATURE_PMU); 108 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 109 cpu->midr = 0x410fd034; 110 cpu->revidr = 0x00000000; 111 cpu->reset_fpsid = 0x41034070; 112 cpu->isar.mvfr0 = 0x10110222; 113 cpu->isar.mvfr1 = 0x12111111; 114 cpu->isar.mvfr2 = 0x00000043; 115 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 116 cpu->reset_sctlr = 0x00c50838; 117 cpu->isar.id_pfr0 = 0x00000131; 118 cpu->isar.id_pfr1 = 0x00011011; 119 cpu->isar.id_dfr0 = 0x03010066; 120 cpu->id_afr0 = 0x00000000; 121 cpu->isar.id_mmfr0 = 0x10101105; 122 cpu->isar.id_mmfr1 = 0x40000000; 123 cpu->isar.id_mmfr2 = 0x01260000; 124 cpu->isar.id_mmfr3 = 0x02102211; 125 cpu->isar.id_isar0 = 0x02101110; 126 cpu->isar.id_isar1 = 0x13112111; 127 cpu->isar.id_isar2 = 0x21232042; 128 cpu->isar.id_isar3 = 0x01112131; 129 cpu->isar.id_isar4 = 0x00011142; 130 cpu->isar.id_isar5 = 0x00011121; 131 cpu->isar.id_isar6 = 0; 132 cpu->isar.id_aa64pfr0 = 0x00002222; 133 cpu->isar.id_aa64dfr0 = 0x10305106; 134 cpu->isar.id_aa64isar0 = 0x00011120; 135 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 136 cpu->isar.dbgdidr = 0x3516d000; 137 cpu->isar.reset_pmcr_el0 = 0x41033000; 138 cpu->clidr = 0x0a200023; 139 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 140 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 141 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 142 cpu->dcz_blocksize = 4; /* 64 bytes */ 143 cpu->gic_num_lrs = 4; 144 cpu->gic_vpribits = 5; 145 cpu->gic_vprebits = 5; 146 cpu->gic_pribits = 5; 147 define_cortex_a72_a57_a53_cp_reginfo(cpu); 148 } 149 150 static void aarch64_a72_initfn(Object *obj) 151 { 152 ARMCPU *cpu = ARM_CPU(obj); 153 154 cpu->dtb_compatible = "arm,cortex-a72"; 155 set_feature(&cpu->env, ARM_FEATURE_V8); 156 set_feature(&cpu->env, ARM_FEATURE_NEON); 157 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 158 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 159 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 160 set_feature(&cpu->env, ARM_FEATURE_EL2); 161 set_feature(&cpu->env, ARM_FEATURE_EL3); 162 set_feature(&cpu->env, ARM_FEATURE_PMU); 163 cpu->midr = 0x410fd083; 164 cpu->revidr = 0x00000000; 165 cpu->reset_fpsid = 0x41034080; 166 cpu->isar.mvfr0 = 0x10110222; 167 cpu->isar.mvfr1 = 0x12111111; 168 cpu->isar.mvfr2 = 0x00000043; 169 cpu->ctr = 0x8444c004; 170 cpu->reset_sctlr = 0x00c50838; 171 cpu->isar.id_pfr0 = 0x00000131; 172 cpu->isar.id_pfr1 = 0x00011011; 173 cpu->isar.id_dfr0 = 0x03010066; 174 cpu->id_afr0 = 0x00000000; 175 cpu->isar.id_mmfr0 = 0x10201105; 176 cpu->isar.id_mmfr1 = 0x40000000; 177 cpu->isar.id_mmfr2 = 0x01260000; 178 cpu->isar.id_mmfr3 = 0x02102211; 179 cpu->isar.id_isar0 = 0x02101110; 180 cpu->isar.id_isar1 = 0x13112111; 181 cpu->isar.id_isar2 = 0x21232042; 182 cpu->isar.id_isar3 = 0x01112131; 183 cpu->isar.id_isar4 = 0x00011142; 184 cpu->isar.id_isar5 = 0x00011121; 185 cpu->isar.id_aa64pfr0 = 0x00002222; 186 cpu->isar.id_aa64dfr0 = 0x10305106; 187 cpu->isar.id_aa64isar0 = 0x00011120; 188 cpu->isar.id_aa64mmfr0 = 0x00001124; 189 cpu->isar.dbgdidr = 0x3516d000; 190 cpu->isar.reset_pmcr_el0 = 0x41023000; 191 cpu->clidr = 0x0a200023; 192 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 193 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 194 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ 195 cpu->dcz_blocksize = 4; /* 64 bytes */ 196 cpu->gic_num_lrs = 4; 197 cpu->gic_vpribits = 5; 198 cpu->gic_vprebits = 5; 199 cpu->gic_pribits = 5; 200 define_cortex_a72_a57_a53_cp_reginfo(cpu); 201 } 202 203 static void aarch64_a76_initfn(Object *obj) 204 { 205 ARMCPU *cpu = ARM_CPU(obj); 206 207 cpu->dtb_compatible = "arm,cortex-a76"; 208 set_feature(&cpu->env, ARM_FEATURE_V8); 209 set_feature(&cpu->env, ARM_FEATURE_NEON); 210 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 211 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 212 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 213 set_feature(&cpu->env, ARM_FEATURE_EL2); 214 set_feature(&cpu->env, ARM_FEATURE_EL3); 215 set_feature(&cpu->env, ARM_FEATURE_PMU); 216 217 /* Ordered by B2.4 AArch64 registers by functional group */ 218 cpu->clidr = 0x82000023; 219 cpu->ctr = 0x8444C004; 220 cpu->dcz_blocksize = 4; 221 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; 222 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 223 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 224 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; 225 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 226 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 227 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 228 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; 229 cpu->id_afr0 = 0x00000000; 230 cpu->isar.id_dfr0 = 0x04010088; 231 cpu->isar.id_isar0 = 0x02101110; 232 cpu->isar.id_isar1 = 0x13112111; 233 cpu->isar.id_isar2 = 0x21232042; 234 cpu->isar.id_isar3 = 0x01112131; 235 cpu->isar.id_isar4 = 0x00010142; 236 cpu->isar.id_isar5 = 0x01011121; 237 cpu->isar.id_isar6 = 0x00000010; 238 cpu->isar.id_mmfr0 = 0x10201105; 239 cpu->isar.id_mmfr1 = 0x40000000; 240 cpu->isar.id_mmfr2 = 0x01260000; 241 cpu->isar.id_mmfr3 = 0x02122211; 242 cpu->isar.id_mmfr4 = 0x00021110; 243 cpu->isar.id_pfr0 = 0x10010131; 244 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 245 cpu->isar.id_pfr2 = 0x00000011; 246 cpu->midr = 0x414fd0b1; /* r4p1 */ 247 cpu->revidr = 0; 248 249 /* From B2.18 CCSIDR_EL1 */ 250 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 251 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 252 cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ 253 254 /* From B2.93 SCTLR_EL3 */ 255 cpu->reset_sctlr = 0x30c50838; 256 257 /* From B4.23 ICH_VTR_EL2 */ 258 cpu->gic_num_lrs = 4; 259 cpu->gic_vpribits = 5; 260 cpu->gic_vprebits = 5; 261 cpu->gic_pribits = 5; 262 263 /* From B5.1 AdvSIMD AArch64 register summary */ 264 cpu->isar.mvfr0 = 0x10110222; 265 cpu->isar.mvfr1 = 0x13211111; 266 cpu->isar.mvfr2 = 0x00000043; 267 268 /* From D5.1 AArch64 PMU register summary */ 269 cpu->isar.reset_pmcr_el0 = 0x410b3000; 270 } 271 272 static void aarch64_neoverse_n1_initfn(Object *obj) 273 { 274 ARMCPU *cpu = ARM_CPU(obj); 275 276 cpu->dtb_compatible = "arm,neoverse-n1"; 277 set_feature(&cpu->env, ARM_FEATURE_V8); 278 set_feature(&cpu->env, ARM_FEATURE_NEON); 279 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 280 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 281 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 282 set_feature(&cpu->env, ARM_FEATURE_EL2); 283 set_feature(&cpu->env, ARM_FEATURE_EL3); 284 set_feature(&cpu->env, ARM_FEATURE_PMU); 285 286 /* Ordered by B2.4 AArch64 registers by functional group */ 287 cpu->clidr = 0x82000023; 288 cpu->ctr = 0x8444c004; 289 cpu->dcz_blocksize = 4; 290 cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; 291 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 292 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 293 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; 294 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 295 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 296 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 297 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; 298 cpu->id_afr0 = 0x00000000; 299 cpu->isar.id_dfr0 = 0x04010088; 300 cpu->isar.id_isar0 = 0x02101110; 301 cpu->isar.id_isar1 = 0x13112111; 302 cpu->isar.id_isar2 = 0x21232042; 303 cpu->isar.id_isar3 = 0x01112131; 304 cpu->isar.id_isar4 = 0x00010142; 305 cpu->isar.id_isar5 = 0x01011121; 306 cpu->isar.id_isar6 = 0x00000010; 307 cpu->isar.id_mmfr0 = 0x10201105; 308 cpu->isar.id_mmfr1 = 0x40000000; 309 cpu->isar.id_mmfr2 = 0x01260000; 310 cpu->isar.id_mmfr3 = 0x02122211; 311 cpu->isar.id_mmfr4 = 0x00021110; 312 cpu->isar.id_pfr0 = 0x10010131; 313 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 314 cpu->isar.id_pfr2 = 0x00000011; 315 cpu->midr = 0x414fd0c1; /* r4p1 */ 316 cpu->revidr = 0; 317 318 /* From B2.23 CCSIDR_EL1 */ 319 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 320 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 321 cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ 322 323 /* From B2.98 SCTLR_EL3 */ 324 cpu->reset_sctlr = 0x30c50838; 325 326 /* From B4.23 ICH_VTR_EL2 */ 327 cpu->gic_num_lrs = 4; 328 cpu->gic_vpribits = 5; 329 cpu->gic_vprebits = 5; 330 cpu->gic_pribits = 5; 331 332 /* From B5.1 AdvSIMD AArch64 register summary */ 333 cpu->isar.mvfr0 = 0x10110222; 334 cpu->isar.mvfr1 = 0x13211111; 335 cpu->isar.mvfr2 = 0x00000043; 336 337 /* From D5.1 AArch64 PMU register summary */ 338 cpu->isar.reset_pmcr_el0 = 0x410c3000; 339 } 340 341 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) 342 { 343 /* 344 * If any vector lengths are explicitly enabled with sve<N> properties, 345 * then all other lengths are implicitly disabled. If sve-max-vq is 346 * specified then it is the same as explicitly enabling all lengths 347 * up to and including the specified maximum, which means all larger 348 * lengths will be implicitly disabled. If no sve<N> properties 349 * are enabled and sve-max-vq is not specified, then all lengths not 350 * explicitly disabled will be enabled. Additionally, all power-of-two 351 * vector lengths less than the maximum enabled length will be 352 * automatically enabled and all vector lengths larger than the largest 353 * disabled power-of-two vector length will be automatically disabled. 354 * Errors are generated if the user provided input that interferes with 355 * any of the above. Finally, if SVE is not disabled, then at least one 356 * vector length must be enabled. 357 */ 358 DECLARE_BITMAP(tmp, ARM_MAX_VQ); 359 uint32_t vq, max_vq = 0; 360 361 /* 362 * CPU models specify a set of supported vector lengths which are 363 * enabled by default. Attempting to enable any vector length not set 364 * in the supported bitmap results in an error. When KVM is enabled we 365 * fetch the supported bitmap from the host. 366 */ 367 if (kvm_enabled() && kvm_arm_sve_supported()) { 368 kvm_arm_sve_get_vls(CPU(cpu), cpu->sve_vq_supported); 369 } else if (kvm_enabled()) { 370 assert(!cpu_isar_feature(aa64_sve, cpu)); 371 } 372 373 /* 374 * Process explicit sve<N> properties. 375 * From the properties, sve_vq_map<N> implies sve_vq_init<N>. 376 * Check first for any sve<N> enabled. 377 */ 378 if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) { 379 max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; 380 381 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { 382 error_setg(errp, "cannot enable sve%d", max_vq * 128); 383 error_append_hint(errp, "sve%d is larger than the maximum vector " 384 "length, sve-max-vq=%d (%d bits)\n", 385 max_vq * 128, cpu->sve_max_vq, 386 cpu->sve_max_vq * 128); 387 return; 388 } 389 390 if (kvm_enabled()) { 391 /* 392 * For KVM we have to automatically enable all supported unitialized 393 * lengths, even when the smaller lengths are not all powers-of-two. 394 */ 395 bitmap_andnot(tmp, cpu->sve_vq_supported, cpu->sve_vq_init, max_vq); 396 bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); 397 } else { 398 /* Propagate enabled bits down through required powers-of-two. */ 399 for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { 400 if (!test_bit(vq - 1, cpu->sve_vq_init)) { 401 set_bit(vq - 1, cpu->sve_vq_map); 402 } 403 } 404 } 405 } else if (cpu->sve_max_vq == 0) { 406 /* 407 * No explicit bits enabled, and no implicit bits from sve-max-vq. 408 */ 409 if (!cpu_isar_feature(aa64_sve, cpu)) { 410 /* SVE is disabled and so are all vector lengths. Good. */ 411 return; 412 } 413 414 if (kvm_enabled()) { 415 /* Disabling a supported length disables all larger lengths. */ 416 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 417 if (test_bit(vq - 1, cpu->sve_vq_init) && 418 test_bit(vq - 1, cpu->sve_vq_supported)) { 419 break; 420 } 421 } 422 } else { 423 /* Disabling a power-of-two disables all larger lengths. */ 424 for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) { 425 if (test_bit(vq - 1, cpu->sve_vq_init)) { 426 break; 427 } 428 } 429 } 430 431 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 432 bitmap_andnot(cpu->sve_vq_map, cpu->sve_vq_supported, 433 cpu->sve_vq_init, max_vq); 434 if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) { 435 error_setg(errp, "cannot disable sve%d", vq * 128); 436 error_append_hint(errp, "Disabling sve%d results in all " 437 "vector lengths being disabled.\n", 438 vq * 128); 439 error_append_hint(errp, "With SVE enabled, at least one " 440 "vector length must be enabled.\n"); 441 return; 442 } 443 444 max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1; 445 } 446 447 /* 448 * Process the sve-max-vq property. 449 * Note that we know from the above that no bit above 450 * sve-max-vq is currently set. 451 */ 452 if (cpu->sve_max_vq != 0) { 453 max_vq = cpu->sve_max_vq; 454 455 if (!test_bit(max_vq - 1, cpu->sve_vq_map) && 456 test_bit(max_vq - 1, cpu->sve_vq_init)) { 457 error_setg(errp, "cannot disable sve%d", max_vq * 128); 458 error_append_hint(errp, "The maximum vector length must be " 459 "enabled, sve-max-vq=%d (%d bits)\n", 460 max_vq, max_vq * 128); 461 return; 462 } 463 464 /* Set all bits not explicitly set within sve-max-vq. */ 465 bitmap_complement(tmp, cpu->sve_vq_init, max_vq); 466 bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); 467 } 468 469 /* 470 * We should know what max-vq is now. Also, as we're done 471 * manipulating sve-vq-map, we ensure any bits above max-vq 472 * are clear, just in case anybody looks. 473 */ 474 assert(max_vq != 0); 475 bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq); 476 477 /* Ensure the set of lengths matches what is supported. */ 478 bitmap_xor(tmp, cpu->sve_vq_map, cpu->sve_vq_supported, max_vq); 479 if (!bitmap_empty(tmp, max_vq)) { 480 vq = find_last_bit(tmp, max_vq) + 1; 481 if (test_bit(vq - 1, cpu->sve_vq_map)) { 482 if (cpu->sve_max_vq) { 483 error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq); 484 error_append_hint(errp, "This CPU does not support " 485 "the vector length %d-bits.\n", vq * 128); 486 error_append_hint(errp, "It may not be possible to use " 487 "sve-max-vq with this CPU. Try " 488 "using only sve<N> properties.\n"); 489 } else { 490 error_setg(errp, "cannot enable sve%d", vq * 128); 491 error_append_hint(errp, "This CPU does not support " 492 "the vector length %d-bits.\n", vq * 128); 493 } 494 return; 495 } else { 496 if (kvm_enabled()) { 497 error_setg(errp, "cannot disable sve%d", vq * 128); 498 error_append_hint(errp, "The KVM host requires all " 499 "supported vector lengths smaller " 500 "than %d bits to also be enabled.\n", 501 max_vq * 128); 502 return; 503 } else { 504 /* Ensure all required powers-of-two are enabled. */ 505 for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { 506 if (!test_bit(vq - 1, cpu->sve_vq_map)) { 507 error_setg(errp, "cannot disable sve%d", vq * 128); 508 error_append_hint(errp, "sve%d is required as it " 509 "is a power-of-two length smaller " 510 "than the maximum, sve%d\n", 511 vq * 128, max_vq * 128); 512 return; 513 } 514 } 515 } 516 } 517 } 518 519 /* 520 * Now that we validated all our vector lengths, the only question 521 * left to answer is if we even want SVE at all. 522 */ 523 if (!cpu_isar_feature(aa64_sve, cpu)) { 524 error_setg(errp, "cannot enable sve%d", max_vq * 128); 525 error_append_hint(errp, "SVE must be enabled to enable vector " 526 "lengths.\n"); 527 error_append_hint(errp, "Add sve=on to the CPU property list.\n"); 528 return; 529 } 530 531 /* From now on sve_max_vq is the actual maximum supported length. */ 532 cpu->sve_max_vq = max_vq; 533 } 534 535 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, 536 void *opaque, Error **errp) 537 { 538 ARMCPU *cpu = ARM_CPU(obj); 539 uint32_t value; 540 541 /* All vector lengths are disabled when SVE is off. */ 542 if (!cpu_isar_feature(aa64_sve, cpu)) { 543 value = 0; 544 } else { 545 value = cpu->sve_max_vq; 546 } 547 visit_type_uint32(v, name, &value, errp); 548 } 549 550 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, 551 void *opaque, Error **errp) 552 { 553 ARMCPU *cpu = ARM_CPU(obj); 554 uint32_t max_vq; 555 556 if (!visit_type_uint32(v, name, &max_vq, errp)) { 557 return; 558 } 559 560 if (kvm_enabled() && !kvm_arm_sve_supported()) { 561 error_setg(errp, "cannot set sve-max-vq"); 562 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 563 return; 564 } 565 566 if (max_vq == 0 || max_vq > ARM_MAX_VQ) { 567 error_setg(errp, "unsupported SVE vector length"); 568 error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", 569 ARM_MAX_VQ); 570 return; 571 } 572 573 cpu->sve_max_vq = max_vq; 574 } 575 576 /* 577 * Note that cpu_arm_get/set_sve_vq cannot use the simpler 578 * object_property_add_bool interface because they make use 579 * of the contents of "name" to determine which bit on which 580 * to operate. 581 */ 582 static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, 583 void *opaque, Error **errp) 584 { 585 ARMCPU *cpu = ARM_CPU(obj); 586 uint32_t vq = atoi(&name[3]) / 128; 587 bool value; 588 589 /* All vector lengths are disabled when SVE is off. */ 590 if (!cpu_isar_feature(aa64_sve, cpu)) { 591 value = false; 592 } else { 593 value = test_bit(vq - 1, cpu->sve_vq_map); 594 } 595 visit_type_bool(v, name, &value, errp); 596 } 597 598 static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, 599 void *opaque, Error **errp) 600 { 601 ARMCPU *cpu = ARM_CPU(obj); 602 uint32_t vq = atoi(&name[3]) / 128; 603 bool value; 604 605 if (!visit_type_bool(v, name, &value, errp)) { 606 return; 607 } 608 609 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 610 error_setg(errp, "cannot enable %s", name); 611 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 612 return; 613 } 614 615 if (value) { 616 set_bit(vq - 1, cpu->sve_vq_map); 617 } else { 618 clear_bit(vq - 1, cpu->sve_vq_map); 619 } 620 set_bit(vq - 1, cpu->sve_vq_init); 621 } 622 623 static bool cpu_arm_get_sve(Object *obj, Error **errp) 624 { 625 ARMCPU *cpu = ARM_CPU(obj); 626 return cpu_isar_feature(aa64_sve, cpu); 627 } 628 629 static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) 630 { 631 ARMCPU *cpu = ARM_CPU(obj); 632 uint64_t t; 633 634 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 635 error_setg(errp, "'sve' feature not supported by KVM on this host"); 636 return; 637 } 638 639 t = cpu->isar.id_aa64pfr0; 640 t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); 641 cpu->isar.id_aa64pfr0 = t; 642 } 643 644 #ifdef CONFIG_USER_ONLY 645 /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ 646 static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v, 647 const char *name, void *opaque, 648 Error **errp) 649 { 650 ARMCPU *cpu = ARM_CPU(obj); 651 int32_t default_len, default_vq, remainder; 652 653 if (!visit_type_int32(v, name, &default_len, errp)) { 654 return; 655 } 656 657 /* Undocumented, but the kernel allows -1 to indicate "maximum". */ 658 if (default_len == -1) { 659 cpu->sve_default_vq = ARM_MAX_VQ; 660 return; 661 } 662 663 default_vq = default_len / 16; 664 remainder = default_len % 16; 665 666 /* 667 * Note that the 512 max comes from include/uapi/asm/sve_context.h 668 * and is the maximum architectural width of ZCR_ELx.LEN. 669 */ 670 if (remainder || default_vq < 1 || default_vq > 512) { 671 error_setg(errp, "cannot set sve-default-vector-length"); 672 if (remainder) { 673 error_append_hint(errp, "Vector length not a multiple of 16\n"); 674 } else if (default_vq < 1) { 675 error_append_hint(errp, "Vector length smaller than 16\n"); 676 } else { 677 error_append_hint(errp, "Vector length larger than %d\n", 678 512 * 16); 679 } 680 return; 681 } 682 683 cpu->sve_default_vq = default_vq; 684 } 685 686 static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v, 687 const char *name, void *opaque, 688 Error **errp) 689 { 690 ARMCPU *cpu = ARM_CPU(obj); 691 int32_t value = cpu->sve_default_vq * 16; 692 693 visit_type_int32(v, name, &value, errp); 694 } 695 #endif 696 697 void aarch64_add_sve_properties(Object *obj) 698 { 699 uint32_t vq; 700 701 object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); 702 703 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 704 char name[8]; 705 sprintf(name, "sve%d", vq * 128); 706 object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, 707 cpu_arm_set_sve_vq, NULL, NULL); 708 } 709 710 #ifdef CONFIG_USER_ONLY 711 /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ 712 object_property_add(obj, "sve-default-vector-length", "int32", 713 cpu_arm_get_sve_default_vec_len, 714 cpu_arm_set_sve_default_vec_len, NULL, NULL); 715 #endif 716 } 717 718 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) 719 { 720 int arch_val = 0, impdef_val = 0; 721 uint64_t t; 722 723 /* Exit early if PAuth is enabled, and fall through to disable it */ 724 if ((kvm_enabled() || hvf_enabled()) && cpu->prop_pauth) { 725 if (!cpu_isar_feature(aa64_pauth, cpu)) { 726 error_setg(errp, "'pauth' feature not supported by %s on this host", 727 kvm_enabled() ? "KVM" : "hvf"); 728 } 729 730 return; 731 } 732 733 /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ 734 if (cpu->prop_pauth) { 735 if (cpu->prop_pauth_impdef) { 736 impdef_val = 1; 737 } else { 738 arch_val = 1; 739 } 740 } else if (cpu->prop_pauth_impdef) { 741 error_setg(errp, "cannot enable pauth-impdef without pauth"); 742 error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); 743 } 744 745 t = cpu->isar.id_aa64isar1; 746 t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); 747 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); 748 t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); 749 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); 750 cpu->isar.id_aa64isar1 = t; 751 } 752 753 static Property arm_cpu_pauth_property = 754 DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); 755 static Property arm_cpu_pauth_impdef_property = 756 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); 757 758 void aarch64_add_pauth_properties(Object *obj) 759 { 760 ARMCPU *cpu = ARM_CPU(obj); 761 762 /* Default to PAUTH on, with the architected algorithm on TCG. */ 763 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); 764 if (kvm_enabled() || hvf_enabled()) { 765 /* 766 * Mirror PAuth support from the probed sysregs back into the 767 * property for KVM or hvf. Is it just a bit backward? Yes it is! 768 * Note that prop_pauth is true whether the host CPU supports the 769 * architected QARMA5 algorithm or the IMPDEF one. We don't 770 * provide the separate pauth-impdef property for KVM or hvf, 771 * only for TCG. 772 */ 773 cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); 774 } else { 775 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); 776 } 777 } 778 779 static Property arm_cpu_lpa2_property = 780 DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); 781 782 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) 783 { 784 uint64_t t; 785 786 /* 787 * We only install the property for tcg -cpu max; this is the 788 * only situation in which the cpu field can be true. 789 */ 790 if (!cpu->prop_lpa2) { 791 return; 792 } 793 794 t = cpu->isar.id_aa64mmfr0; 795 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */ 796 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */ 797 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */ 798 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */ 799 cpu->isar.id_aa64mmfr0 = t; 800 } 801 802 static void aarch64_host_initfn(Object *obj) 803 { 804 #if defined(CONFIG_KVM) 805 ARMCPU *cpu = ARM_CPU(obj); 806 kvm_arm_set_cpu_features_from_host(cpu); 807 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 808 aarch64_add_sve_properties(obj); 809 aarch64_add_pauth_properties(obj); 810 } 811 #elif defined(CONFIG_HVF) 812 ARMCPU *cpu = ARM_CPU(obj); 813 hvf_arm_set_cpu_features_from_host(cpu); 814 aarch64_add_pauth_properties(obj); 815 #else 816 g_assert_not_reached(); 817 #endif 818 } 819 820 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 821 * otherwise, a CPU with as many features enabled as our emulation supports. 822 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; 823 * this only needs to handle 64 bits. 824 */ 825 static void aarch64_max_initfn(Object *obj) 826 { 827 ARMCPU *cpu = ARM_CPU(obj); 828 uint64_t t; 829 uint32_t u; 830 831 if (kvm_enabled() || hvf_enabled()) { 832 /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ 833 aarch64_host_initfn(obj); 834 return; 835 } 836 837 /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */ 838 839 aarch64_a57_initfn(obj); 840 841 /* 842 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real 843 * one and try to apply errata workarounds or use impdef features we 844 * don't provide. 845 * An IMPLEMENTER field of 0 means "reserved for software use"; 846 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers 847 * to see which features are present"; 848 * the VARIANT, PARTNUM and REVISION fields are all implementation 849 * defined and we choose to define PARTNUM just in case guest 850 * code needs to distinguish this QEMU CPU from other software 851 * implementations, though this shouldn't be needed. 852 */ 853 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); 854 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); 855 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); 856 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); 857 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); 858 cpu->midr = t; 859 860 /* 861 * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS} 862 * are zero. 863 */ 864 u = cpu->clidr; 865 u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); 866 u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0); 867 cpu->clidr = u; 868 869 t = cpu->isar.id_aa64isar0; 870 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ 871 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ 872 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ 873 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); 874 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ 875 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ 876 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ 877 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ 878 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ 879 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ 880 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ 881 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ 882 t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ 883 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ 884 cpu->isar.id_aa64isar0 = t; 885 886 t = cpu->isar.id_aa64isar1; 887 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ 888 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ 889 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ 890 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ 891 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ 892 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ 893 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ 894 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ 895 t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ 896 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ 897 cpu->isar.id_aa64isar1 = t; 898 899 t = cpu->isar.id_aa64pfr0; 900 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ 901 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ 902 t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ 903 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); 904 t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ 905 t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ 906 t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ 907 t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ 908 cpu->isar.id_aa64pfr0 = t; 909 910 t = cpu->isar.id_aa64pfr1; 911 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ 912 t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ 913 /* 914 * Begin with full support for MTE. This will be downgraded to MTE=0 915 * during realize if the board provides no tag memory, much like 916 * we do for EL2 with the virtualization=on property. 917 */ 918 t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ 919 t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ 920 cpu->isar.id_aa64pfr1 = t; 921 922 t = cpu->isar.id_aa64mmfr0; 923 t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ 924 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ 925 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ 926 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ 927 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ 928 cpu->isar.id_aa64mmfr0 = t; 929 930 t = cpu->isar.id_aa64mmfr1; 931 t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ 932 t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ 933 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ 934 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ 935 t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ 936 t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ 937 t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ 938 cpu->isar.id_aa64mmfr1 = t; 939 940 t = cpu->isar.id_aa64mmfr2; 941 t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ 942 t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ 943 t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ 944 t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ 945 t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ 946 t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ 947 t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ 948 t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ 949 t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ 950 cpu->isar.id_aa64mmfr2 = t; 951 952 t = cpu->isar.id_aa64zfr0; 953 t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); 954 t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ 955 t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ 956 t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ 957 t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ 958 t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ 959 t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ 960 t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ 961 t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ 962 cpu->isar.id_aa64zfr0 = t; 963 964 t = cpu->isar.id_aa64dfr0; 965 t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ 966 t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ 967 cpu->isar.id_aa64dfr0 = t; 968 969 /* Replicate the same data to the 32-bit id registers. */ 970 aa32_max_features(cpu); 971 972 #ifdef CONFIG_USER_ONLY 973 /* 974 * For usermode -cpu max we can use a larger and more efficient DCZ 975 * blocksize since we don't have to follow what the hardware does. 976 */ 977 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 978 cpu->dcz_blocksize = 7; /* 512 bytes */ 979 #endif 980 981 bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ); 982 983 aarch64_add_pauth_properties(obj); 984 aarch64_add_sve_properties(obj); 985 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, 986 cpu_max_set_sve_max_vq, NULL, NULL); 987 qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); 988 } 989 990 static void aarch64_a64fx_initfn(Object *obj) 991 { 992 ARMCPU *cpu = ARM_CPU(obj); 993 994 cpu->dtb_compatible = "arm,a64fx"; 995 set_feature(&cpu->env, ARM_FEATURE_V8); 996 set_feature(&cpu->env, ARM_FEATURE_NEON); 997 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 998 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 999 set_feature(&cpu->env, ARM_FEATURE_EL2); 1000 set_feature(&cpu->env, ARM_FEATURE_EL3); 1001 set_feature(&cpu->env, ARM_FEATURE_PMU); 1002 cpu->midr = 0x461f0010; 1003 cpu->revidr = 0x00000000; 1004 cpu->ctr = 0x86668006; 1005 cpu->reset_sctlr = 0x30000180; 1006 cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */ 1007 cpu->isar.id_aa64pfr1 = 0x0000000000000000; 1008 cpu->isar.id_aa64dfr0 = 0x0000000010305408; 1009 cpu->isar.id_aa64dfr1 = 0x0000000000000000; 1010 cpu->id_aa64afr0 = 0x0000000000000000; 1011 cpu->id_aa64afr1 = 0x0000000000000000; 1012 cpu->isar.id_aa64mmfr0 = 0x0000000000001122; 1013 cpu->isar.id_aa64mmfr1 = 0x0000000011212100; 1014 cpu->isar.id_aa64mmfr2 = 0x0000000000001011; 1015 cpu->isar.id_aa64isar0 = 0x0000000010211120; 1016 cpu->isar.id_aa64isar1 = 0x0000000000010001; 1017 cpu->isar.id_aa64zfr0 = 0x0000000000000000; 1018 cpu->clidr = 0x0000000080000023; 1019 cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */ 1020 cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */ 1021 cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */ 1022 cpu->dcz_blocksize = 6; /* 256 bytes */ 1023 cpu->gic_num_lrs = 4; 1024 cpu->gic_vpribits = 5; 1025 cpu->gic_vprebits = 5; 1026 cpu->gic_pribits = 5; 1027 1028 /* Suppport of A64FX's vector length are 128,256 and 512bit only */ 1029 aarch64_add_sve_properties(obj); 1030 bitmap_zero(cpu->sve_vq_supported, ARM_MAX_VQ); 1031 set_bit(0, cpu->sve_vq_supported); /* 128bit */ 1032 set_bit(1, cpu->sve_vq_supported); /* 256bit */ 1033 set_bit(3, cpu->sve_vq_supported); /* 512bit */ 1034 1035 cpu->isar.reset_pmcr_el0 = 0x46014040; 1036 1037 /* TODO: Add A64FX specific HPC extension registers */ 1038 } 1039 1040 static const ARMCPUInfo aarch64_cpus[] = { 1041 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 1042 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 1043 { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, 1044 { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, 1045 { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, 1046 { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, 1047 { .name = "max", .initfn = aarch64_max_initfn }, 1048 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1049 { .name = "host", .initfn = aarch64_host_initfn }, 1050 #endif 1051 }; 1052 1053 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 1054 { 1055 ARMCPU *cpu = ARM_CPU(obj); 1056 1057 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 1058 } 1059 1060 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 1061 { 1062 ARMCPU *cpu = ARM_CPU(obj); 1063 1064 /* At this time, this property is only allowed if KVM is enabled. This 1065 * restriction allows us to avoid fixing up functionality that assumes a 1066 * uniform execution state like do_interrupt. 1067 */ 1068 if (value == false) { 1069 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 1070 error_setg(errp, "'aarch64' feature cannot be disabled " 1071 "unless KVM is enabled and 32-bit EL1 " 1072 "is supported"); 1073 return; 1074 } 1075 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 1076 } else { 1077 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 1078 } 1079 } 1080 1081 static void aarch64_cpu_finalizefn(Object *obj) 1082 { 1083 } 1084 1085 static gchar *aarch64_gdb_arch_name(CPUState *cs) 1086 { 1087 return g_strdup("aarch64"); 1088 } 1089 1090 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 1091 { 1092 CPUClass *cc = CPU_CLASS(oc); 1093 1094 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 1095 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 1096 cc->gdb_num_core_regs = 34; 1097 cc->gdb_core_xml_file = "aarch64-core.xml"; 1098 cc->gdb_arch_name = aarch64_gdb_arch_name; 1099 1100 object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, 1101 aarch64_cpu_set_aarch64); 1102 object_class_property_set_description(oc, "aarch64", 1103 "Set on/off to enable/disable aarch64 " 1104 "execution state "); 1105 } 1106 1107 static void aarch64_cpu_instance_init(Object *obj) 1108 { 1109 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 1110 1111 acc->info->initfn(obj); 1112 arm_cpu_post_init(obj); 1113 } 1114 1115 static void cpu_register_class_init(ObjectClass *oc, void *data) 1116 { 1117 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1118 1119 acc->info = data; 1120 } 1121 1122 void aarch64_cpu_register(const ARMCPUInfo *info) 1123 { 1124 TypeInfo type_info = { 1125 .parent = TYPE_AARCH64_CPU, 1126 .instance_size = sizeof(ARMCPU), 1127 .instance_init = aarch64_cpu_instance_init, 1128 .class_size = sizeof(ARMCPUClass), 1129 .class_init = info->class_init ?: cpu_register_class_init, 1130 .class_data = (void *)info, 1131 }; 1132 1133 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1134 type_register(&type_info); 1135 g_free((void *)type_info.name); 1136 } 1137 1138 static const TypeInfo aarch64_cpu_type_info = { 1139 .name = TYPE_AARCH64_CPU, 1140 .parent = TYPE_ARM_CPU, 1141 .instance_size = sizeof(ARMCPU), 1142 .instance_finalize = aarch64_cpu_finalizefn, 1143 .abstract = true, 1144 .class_size = sizeof(AArch64CPUClass), 1145 .class_init = aarch64_cpu_class_init, 1146 }; 1147 1148 static void aarch64_cpu_register_types(void) 1149 { 1150 size_t i; 1151 1152 type_register_static(&aarch64_cpu_type_info); 1153 1154 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { 1155 aarch64_cpu_register(&aarch64_cpus[i]); 1156 } 1157 } 1158 1159 type_init(aarch64_cpu_register_types) 1160