1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #ifdef CONFIG_TCG 25 #include "hw/core/tcg-cpu-ops.h" 26 #endif /* CONFIG_TCG */ 27 #include "qemu/module.h" 28 #if !defined(CONFIG_USER_ONLY) 29 #include "hw/loader.h" 30 #endif 31 #include "sysemu/kvm.h" 32 #include "sysemu/hvf.h" 33 #include "kvm_arm.h" 34 #include "hvf_arm.h" 35 #include "qapi/visitor.h" 36 #include "hw/qdev-properties.h" 37 38 39 #ifndef CONFIG_USER_ONLY 40 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 41 { 42 ARMCPU *cpu = env_archcpu(env); 43 44 /* Number of cores is in [25:24]; otherwise we RAZ */ 45 return (cpu->core_count - 1) << 24; 46 } 47 #endif 48 49 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { 50 #ifndef CONFIG_USER_ONLY 51 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, 52 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, 53 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 54 .writefn = arm_cp_write_ignore }, 55 { .name = "L2CTLR", 56 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, 57 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 58 .writefn = arm_cp_write_ignore }, 59 #endif 60 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, 61 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, 62 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 63 { .name = "L2ECTLR", 64 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, 65 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 66 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, 67 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, 68 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 69 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 70 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, 71 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 72 { .name = "CPUACTLR", 73 .cp = 15, .opc1 = 0, .crm = 15, 74 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 75 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 76 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, 77 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 78 { .name = "CPUECTLR", 79 .cp = 15, .opc1 = 1, .crm = 15, 80 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 81 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, 82 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, 83 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 84 { .name = "CPUMERRSR", 85 .cp = 15, .opc1 = 2, .crm = 15, 86 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 87 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, 88 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, 89 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 90 { .name = "L2MERRSR", 91 .cp = 15, .opc1 = 3, .crm = 15, 92 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 93 REGINFO_SENTINEL 94 }; 95 96 static void aarch64_a57_initfn(Object *obj) 97 { 98 ARMCPU *cpu = ARM_CPU(obj); 99 100 cpu->dtb_compatible = "arm,cortex-a57"; 101 set_feature(&cpu->env, ARM_FEATURE_V8); 102 set_feature(&cpu->env, ARM_FEATURE_NEON); 103 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 104 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 105 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 106 set_feature(&cpu->env, ARM_FEATURE_EL2); 107 set_feature(&cpu->env, ARM_FEATURE_EL3); 108 set_feature(&cpu->env, ARM_FEATURE_PMU); 109 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 110 cpu->midr = 0x411fd070; 111 cpu->revidr = 0x00000000; 112 cpu->reset_fpsid = 0x41034070; 113 cpu->isar.mvfr0 = 0x10110222; 114 cpu->isar.mvfr1 = 0x12111111; 115 cpu->isar.mvfr2 = 0x00000043; 116 cpu->ctr = 0x8444c004; 117 cpu->reset_sctlr = 0x00c50838; 118 cpu->isar.id_pfr0 = 0x00000131; 119 cpu->isar.id_pfr1 = 0x00011011; 120 cpu->isar.id_dfr0 = 0x03010066; 121 cpu->id_afr0 = 0x00000000; 122 cpu->isar.id_mmfr0 = 0x10101105; 123 cpu->isar.id_mmfr1 = 0x40000000; 124 cpu->isar.id_mmfr2 = 0x01260000; 125 cpu->isar.id_mmfr3 = 0x02102211; 126 cpu->isar.id_isar0 = 0x02101110; 127 cpu->isar.id_isar1 = 0x13112111; 128 cpu->isar.id_isar2 = 0x21232042; 129 cpu->isar.id_isar3 = 0x01112131; 130 cpu->isar.id_isar4 = 0x00011142; 131 cpu->isar.id_isar5 = 0x00011121; 132 cpu->isar.id_isar6 = 0; 133 cpu->isar.id_aa64pfr0 = 0x00002222; 134 cpu->isar.id_aa64dfr0 = 0x10305106; 135 cpu->isar.id_aa64isar0 = 0x00011120; 136 cpu->isar.id_aa64mmfr0 = 0x00001124; 137 cpu->isar.dbgdidr = 0x3516d000; 138 cpu->clidr = 0x0a200023; 139 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 140 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 141 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 142 cpu->dcz_blocksize = 4; /* 64 bytes */ 143 cpu->gic_num_lrs = 4; 144 cpu->gic_vpribits = 5; 145 cpu->gic_vprebits = 5; 146 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 147 } 148 149 static void aarch64_a53_initfn(Object *obj) 150 { 151 ARMCPU *cpu = ARM_CPU(obj); 152 153 cpu->dtb_compatible = "arm,cortex-a53"; 154 set_feature(&cpu->env, ARM_FEATURE_V8); 155 set_feature(&cpu->env, ARM_FEATURE_NEON); 156 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 157 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 158 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 159 set_feature(&cpu->env, ARM_FEATURE_EL2); 160 set_feature(&cpu->env, ARM_FEATURE_EL3); 161 set_feature(&cpu->env, ARM_FEATURE_PMU); 162 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 163 cpu->midr = 0x410fd034; 164 cpu->revidr = 0x00000000; 165 cpu->reset_fpsid = 0x41034070; 166 cpu->isar.mvfr0 = 0x10110222; 167 cpu->isar.mvfr1 = 0x12111111; 168 cpu->isar.mvfr2 = 0x00000043; 169 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 170 cpu->reset_sctlr = 0x00c50838; 171 cpu->isar.id_pfr0 = 0x00000131; 172 cpu->isar.id_pfr1 = 0x00011011; 173 cpu->isar.id_dfr0 = 0x03010066; 174 cpu->id_afr0 = 0x00000000; 175 cpu->isar.id_mmfr0 = 0x10101105; 176 cpu->isar.id_mmfr1 = 0x40000000; 177 cpu->isar.id_mmfr2 = 0x01260000; 178 cpu->isar.id_mmfr3 = 0x02102211; 179 cpu->isar.id_isar0 = 0x02101110; 180 cpu->isar.id_isar1 = 0x13112111; 181 cpu->isar.id_isar2 = 0x21232042; 182 cpu->isar.id_isar3 = 0x01112131; 183 cpu->isar.id_isar4 = 0x00011142; 184 cpu->isar.id_isar5 = 0x00011121; 185 cpu->isar.id_isar6 = 0; 186 cpu->isar.id_aa64pfr0 = 0x00002222; 187 cpu->isar.id_aa64dfr0 = 0x10305106; 188 cpu->isar.id_aa64isar0 = 0x00011120; 189 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 190 cpu->isar.dbgdidr = 0x3516d000; 191 cpu->clidr = 0x0a200023; 192 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 193 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 194 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 195 cpu->dcz_blocksize = 4; /* 64 bytes */ 196 cpu->gic_num_lrs = 4; 197 cpu->gic_vpribits = 5; 198 cpu->gic_vprebits = 5; 199 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 200 } 201 202 static void aarch64_a72_initfn(Object *obj) 203 { 204 ARMCPU *cpu = ARM_CPU(obj); 205 206 cpu->dtb_compatible = "arm,cortex-a72"; 207 set_feature(&cpu->env, ARM_FEATURE_V8); 208 set_feature(&cpu->env, ARM_FEATURE_NEON); 209 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 210 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 211 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 212 set_feature(&cpu->env, ARM_FEATURE_EL2); 213 set_feature(&cpu->env, ARM_FEATURE_EL3); 214 set_feature(&cpu->env, ARM_FEATURE_PMU); 215 cpu->midr = 0x410fd083; 216 cpu->revidr = 0x00000000; 217 cpu->reset_fpsid = 0x41034080; 218 cpu->isar.mvfr0 = 0x10110222; 219 cpu->isar.mvfr1 = 0x12111111; 220 cpu->isar.mvfr2 = 0x00000043; 221 cpu->ctr = 0x8444c004; 222 cpu->reset_sctlr = 0x00c50838; 223 cpu->isar.id_pfr0 = 0x00000131; 224 cpu->isar.id_pfr1 = 0x00011011; 225 cpu->isar.id_dfr0 = 0x03010066; 226 cpu->id_afr0 = 0x00000000; 227 cpu->isar.id_mmfr0 = 0x10201105; 228 cpu->isar.id_mmfr1 = 0x40000000; 229 cpu->isar.id_mmfr2 = 0x01260000; 230 cpu->isar.id_mmfr3 = 0x02102211; 231 cpu->isar.id_isar0 = 0x02101110; 232 cpu->isar.id_isar1 = 0x13112111; 233 cpu->isar.id_isar2 = 0x21232042; 234 cpu->isar.id_isar3 = 0x01112131; 235 cpu->isar.id_isar4 = 0x00011142; 236 cpu->isar.id_isar5 = 0x00011121; 237 cpu->isar.id_aa64pfr0 = 0x00002222; 238 cpu->isar.id_aa64dfr0 = 0x10305106; 239 cpu->isar.id_aa64isar0 = 0x00011120; 240 cpu->isar.id_aa64mmfr0 = 0x00001124; 241 cpu->isar.dbgdidr = 0x3516d000; 242 cpu->clidr = 0x0a200023; 243 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 244 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 245 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ 246 cpu->dcz_blocksize = 4; /* 64 bytes */ 247 cpu->gic_num_lrs = 4; 248 cpu->gic_vpribits = 5; 249 cpu->gic_vprebits = 5; 250 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 251 } 252 253 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) 254 { 255 /* 256 * If any vector lengths are explicitly enabled with sve<N> properties, 257 * then all other lengths are implicitly disabled. If sve-max-vq is 258 * specified then it is the same as explicitly enabling all lengths 259 * up to and including the specified maximum, which means all larger 260 * lengths will be implicitly disabled. If no sve<N> properties 261 * are enabled and sve-max-vq is not specified, then all lengths not 262 * explicitly disabled will be enabled. Additionally, all power-of-two 263 * vector lengths less than the maximum enabled length will be 264 * automatically enabled and all vector lengths larger than the largest 265 * disabled power-of-two vector length will be automatically disabled. 266 * Errors are generated if the user provided input that interferes with 267 * any of the above. Finally, if SVE is not disabled, then at least one 268 * vector length must be enabled. 269 */ 270 DECLARE_BITMAP(tmp, ARM_MAX_VQ); 271 uint32_t vq, max_vq = 0; 272 273 /* 274 * CPU models specify a set of supported vector lengths which are 275 * enabled by default. Attempting to enable any vector length not set 276 * in the supported bitmap results in an error. When KVM is enabled we 277 * fetch the supported bitmap from the host. 278 */ 279 if (kvm_enabled() && kvm_arm_sve_supported()) { 280 kvm_arm_sve_get_vls(CPU(cpu), cpu->sve_vq_supported); 281 } else if (kvm_enabled()) { 282 assert(!cpu_isar_feature(aa64_sve, cpu)); 283 } 284 285 /* 286 * Process explicit sve<N> properties. 287 * From the properties, sve_vq_map<N> implies sve_vq_init<N>. 288 * Check first for any sve<N> enabled. 289 */ 290 if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) { 291 max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; 292 293 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { 294 error_setg(errp, "cannot enable sve%d", max_vq * 128); 295 error_append_hint(errp, "sve%d is larger than the maximum vector " 296 "length, sve-max-vq=%d (%d bits)\n", 297 max_vq * 128, cpu->sve_max_vq, 298 cpu->sve_max_vq * 128); 299 return; 300 } 301 302 if (kvm_enabled()) { 303 /* 304 * For KVM we have to automatically enable all supported unitialized 305 * lengths, even when the smaller lengths are not all powers-of-two. 306 */ 307 bitmap_andnot(tmp, cpu->sve_vq_supported, cpu->sve_vq_init, max_vq); 308 bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); 309 } else { 310 /* Propagate enabled bits down through required powers-of-two. */ 311 for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { 312 if (!test_bit(vq - 1, cpu->sve_vq_init)) { 313 set_bit(vq - 1, cpu->sve_vq_map); 314 } 315 } 316 } 317 } else if (cpu->sve_max_vq == 0) { 318 /* 319 * No explicit bits enabled, and no implicit bits from sve-max-vq. 320 */ 321 if (!cpu_isar_feature(aa64_sve, cpu)) { 322 /* SVE is disabled and so are all vector lengths. Good. */ 323 return; 324 } 325 326 if (kvm_enabled()) { 327 /* Disabling a supported length disables all larger lengths. */ 328 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 329 if (test_bit(vq - 1, cpu->sve_vq_init) && 330 test_bit(vq - 1, cpu->sve_vq_supported)) { 331 break; 332 } 333 } 334 } else { 335 /* Disabling a power-of-two disables all larger lengths. */ 336 for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) { 337 if (test_bit(vq - 1, cpu->sve_vq_init)) { 338 break; 339 } 340 } 341 } 342 343 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 344 bitmap_andnot(cpu->sve_vq_map, cpu->sve_vq_supported, 345 cpu->sve_vq_init, max_vq); 346 if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) { 347 error_setg(errp, "cannot disable sve%d", vq * 128); 348 error_append_hint(errp, "Disabling sve%d results in all " 349 "vector lengths being disabled.\n", 350 vq * 128); 351 error_append_hint(errp, "With SVE enabled, at least one " 352 "vector length must be enabled.\n"); 353 return; 354 } 355 356 max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1; 357 } 358 359 /* 360 * Process the sve-max-vq property. 361 * Note that we know from the above that no bit above 362 * sve-max-vq is currently set. 363 */ 364 if (cpu->sve_max_vq != 0) { 365 max_vq = cpu->sve_max_vq; 366 367 if (!test_bit(max_vq - 1, cpu->sve_vq_map) && 368 test_bit(max_vq - 1, cpu->sve_vq_init)) { 369 error_setg(errp, "cannot disable sve%d", max_vq * 128); 370 error_append_hint(errp, "The maximum vector length must be " 371 "enabled, sve-max-vq=%d (%d bits)\n", 372 max_vq, max_vq * 128); 373 return; 374 } 375 376 /* Set all bits not explicitly set within sve-max-vq. */ 377 bitmap_complement(tmp, cpu->sve_vq_init, max_vq); 378 bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); 379 } 380 381 /* 382 * We should know what max-vq is now. Also, as we're done 383 * manipulating sve-vq-map, we ensure any bits above max-vq 384 * are clear, just in case anybody looks. 385 */ 386 assert(max_vq != 0); 387 bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq); 388 389 /* Ensure the set of lengths matches what is supported. */ 390 bitmap_xor(tmp, cpu->sve_vq_map, cpu->sve_vq_supported, max_vq); 391 if (!bitmap_empty(tmp, max_vq)) { 392 vq = find_last_bit(tmp, max_vq) + 1; 393 if (test_bit(vq - 1, cpu->sve_vq_map)) { 394 if (cpu->sve_max_vq) { 395 error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq); 396 error_append_hint(errp, "This CPU does not support " 397 "the vector length %d-bits.\n", vq * 128); 398 error_append_hint(errp, "It may not be possible to use " 399 "sve-max-vq with this CPU. Try " 400 "using only sve<N> properties.\n"); 401 } else { 402 error_setg(errp, "cannot enable sve%d", vq * 128); 403 error_append_hint(errp, "This CPU does not support " 404 "the vector length %d-bits.\n", vq * 128); 405 } 406 return; 407 } else { 408 if (kvm_enabled()) { 409 error_setg(errp, "cannot disable sve%d", vq * 128); 410 error_append_hint(errp, "The KVM host requires all " 411 "supported vector lengths smaller " 412 "than %d bits to also be enabled.\n", 413 max_vq * 128); 414 return; 415 } else { 416 /* Ensure all required powers-of-two are enabled. */ 417 for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { 418 if (!test_bit(vq - 1, cpu->sve_vq_map)) { 419 error_setg(errp, "cannot disable sve%d", vq * 128); 420 error_append_hint(errp, "sve%d is required as it " 421 "is a power-of-two length smaller " 422 "than the maximum, sve%d\n", 423 vq * 128, max_vq * 128); 424 return; 425 } 426 } 427 } 428 } 429 } 430 431 /* 432 * Now that we validated all our vector lengths, the only question 433 * left to answer is if we even want SVE at all. 434 */ 435 if (!cpu_isar_feature(aa64_sve, cpu)) { 436 error_setg(errp, "cannot enable sve%d", max_vq * 128); 437 error_append_hint(errp, "SVE must be enabled to enable vector " 438 "lengths.\n"); 439 error_append_hint(errp, "Add sve=on to the CPU property list.\n"); 440 return; 441 } 442 443 /* From now on sve_max_vq is the actual maximum supported length. */ 444 cpu->sve_max_vq = max_vq; 445 } 446 447 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, 448 void *opaque, Error **errp) 449 { 450 ARMCPU *cpu = ARM_CPU(obj); 451 uint32_t value; 452 453 /* All vector lengths are disabled when SVE is off. */ 454 if (!cpu_isar_feature(aa64_sve, cpu)) { 455 value = 0; 456 } else { 457 value = cpu->sve_max_vq; 458 } 459 visit_type_uint32(v, name, &value, errp); 460 } 461 462 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, 463 void *opaque, Error **errp) 464 { 465 ARMCPU *cpu = ARM_CPU(obj); 466 uint32_t max_vq; 467 468 if (!visit_type_uint32(v, name, &max_vq, errp)) { 469 return; 470 } 471 472 if (kvm_enabled() && !kvm_arm_sve_supported()) { 473 error_setg(errp, "cannot set sve-max-vq"); 474 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 475 return; 476 } 477 478 if (max_vq == 0 || max_vq > ARM_MAX_VQ) { 479 error_setg(errp, "unsupported SVE vector length"); 480 error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", 481 ARM_MAX_VQ); 482 return; 483 } 484 485 cpu->sve_max_vq = max_vq; 486 } 487 488 /* 489 * Note that cpu_arm_get/set_sve_vq cannot use the simpler 490 * object_property_add_bool interface because they make use 491 * of the contents of "name" to determine which bit on which 492 * to operate. 493 */ 494 static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, 495 void *opaque, Error **errp) 496 { 497 ARMCPU *cpu = ARM_CPU(obj); 498 uint32_t vq = atoi(&name[3]) / 128; 499 bool value; 500 501 /* All vector lengths are disabled when SVE is off. */ 502 if (!cpu_isar_feature(aa64_sve, cpu)) { 503 value = false; 504 } else { 505 value = test_bit(vq - 1, cpu->sve_vq_map); 506 } 507 visit_type_bool(v, name, &value, errp); 508 } 509 510 static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, 511 void *opaque, Error **errp) 512 { 513 ARMCPU *cpu = ARM_CPU(obj); 514 uint32_t vq = atoi(&name[3]) / 128; 515 bool value; 516 517 if (!visit_type_bool(v, name, &value, errp)) { 518 return; 519 } 520 521 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 522 error_setg(errp, "cannot enable %s", name); 523 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 524 return; 525 } 526 527 if (value) { 528 set_bit(vq - 1, cpu->sve_vq_map); 529 } else { 530 clear_bit(vq - 1, cpu->sve_vq_map); 531 } 532 set_bit(vq - 1, cpu->sve_vq_init); 533 } 534 535 static bool cpu_arm_get_sve(Object *obj, Error **errp) 536 { 537 ARMCPU *cpu = ARM_CPU(obj); 538 return cpu_isar_feature(aa64_sve, cpu); 539 } 540 541 static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) 542 { 543 ARMCPU *cpu = ARM_CPU(obj); 544 uint64_t t; 545 546 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 547 error_setg(errp, "'sve' feature not supported by KVM on this host"); 548 return; 549 } 550 551 t = cpu->isar.id_aa64pfr0; 552 t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); 553 cpu->isar.id_aa64pfr0 = t; 554 } 555 556 #ifdef CONFIG_USER_ONLY 557 /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ 558 static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v, 559 const char *name, void *opaque, 560 Error **errp) 561 { 562 ARMCPU *cpu = ARM_CPU(obj); 563 int32_t default_len, default_vq, remainder; 564 565 if (!visit_type_int32(v, name, &default_len, errp)) { 566 return; 567 } 568 569 /* Undocumented, but the kernel allows -1 to indicate "maximum". */ 570 if (default_len == -1) { 571 cpu->sve_default_vq = ARM_MAX_VQ; 572 return; 573 } 574 575 default_vq = default_len / 16; 576 remainder = default_len % 16; 577 578 /* 579 * Note that the 512 max comes from include/uapi/asm/sve_context.h 580 * and is the maximum architectural width of ZCR_ELx.LEN. 581 */ 582 if (remainder || default_vq < 1 || default_vq > 512) { 583 error_setg(errp, "cannot set sve-default-vector-length"); 584 if (remainder) { 585 error_append_hint(errp, "Vector length not a multiple of 16\n"); 586 } else if (default_vq < 1) { 587 error_append_hint(errp, "Vector length smaller than 16\n"); 588 } else { 589 error_append_hint(errp, "Vector length larger than %d\n", 590 512 * 16); 591 } 592 return; 593 } 594 595 cpu->sve_default_vq = default_vq; 596 } 597 598 static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v, 599 const char *name, void *opaque, 600 Error **errp) 601 { 602 ARMCPU *cpu = ARM_CPU(obj); 603 int32_t value = cpu->sve_default_vq * 16; 604 605 visit_type_int32(v, name, &value, errp); 606 } 607 #endif 608 609 void aarch64_add_sve_properties(Object *obj) 610 { 611 uint32_t vq; 612 613 object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); 614 615 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 616 char name[8]; 617 sprintf(name, "sve%d", vq * 128); 618 object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, 619 cpu_arm_set_sve_vq, NULL, NULL); 620 } 621 622 #ifdef CONFIG_USER_ONLY 623 /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ 624 object_property_add(obj, "sve-default-vector-length", "int32", 625 cpu_arm_get_sve_default_vec_len, 626 cpu_arm_set_sve_default_vec_len, NULL, NULL); 627 #endif 628 } 629 630 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) 631 { 632 int arch_val = 0, impdef_val = 0; 633 uint64_t t; 634 635 /* Exit early if PAuth is enabled, and fall through to disable it */ 636 if ((kvm_enabled() || hvf_enabled()) && cpu->prop_pauth) { 637 if (!cpu_isar_feature(aa64_pauth, cpu)) { 638 error_setg(errp, "'pauth' feature not supported by %s on this host", 639 kvm_enabled() ? "KVM" : "hvf"); 640 } 641 642 return; 643 } 644 645 /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ 646 if (cpu->prop_pauth) { 647 if (cpu->prop_pauth_impdef) { 648 impdef_val = 1; 649 } else { 650 arch_val = 1; 651 } 652 } else if (cpu->prop_pauth_impdef) { 653 error_setg(errp, "cannot enable pauth-impdef without pauth"); 654 error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); 655 } 656 657 t = cpu->isar.id_aa64isar1; 658 t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); 659 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); 660 t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); 661 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); 662 cpu->isar.id_aa64isar1 = t; 663 } 664 665 static Property arm_cpu_pauth_property = 666 DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); 667 static Property arm_cpu_pauth_impdef_property = 668 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); 669 670 void aarch64_add_pauth_properties(Object *obj) 671 { 672 ARMCPU *cpu = ARM_CPU(obj); 673 674 /* Default to PAUTH on, with the architected algorithm on TCG. */ 675 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); 676 if (kvm_enabled() || hvf_enabled()) { 677 /* 678 * Mirror PAuth support from the probed sysregs back into the 679 * property for KVM or hvf. Is it just a bit backward? Yes it is! 680 * Note that prop_pauth is true whether the host CPU supports the 681 * architected QARMA5 algorithm or the IMPDEF one. We don't 682 * provide the separate pauth-impdef property for KVM or hvf, 683 * only for TCG. 684 */ 685 cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); 686 } else { 687 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); 688 } 689 } 690 691 static Property arm_cpu_lpa2_property = 692 DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); 693 694 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) 695 { 696 uint64_t t; 697 698 /* 699 * We only install the property for tcg -cpu max; this is the 700 * only situation in which the cpu field can be true. 701 */ 702 if (!cpu->prop_lpa2) { 703 return; 704 } 705 706 t = cpu->isar.id_aa64mmfr0; 707 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */ 708 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */ 709 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */ 710 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */ 711 cpu->isar.id_aa64mmfr0 = t; 712 } 713 714 static void aarch64_host_initfn(Object *obj) 715 { 716 #if defined(CONFIG_KVM) 717 ARMCPU *cpu = ARM_CPU(obj); 718 kvm_arm_set_cpu_features_from_host(cpu); 719 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 720 aarch64_add_sve_properties(obj); 721 aarch64_add_pauth_properties(obj); 722 } 723 #elif defined(CONFIG_HVF) 724 ARMCPU *cpu = ARM_CPU(obj); 725 hvf_arm_set_cpu_features_from_host(cpu); 726 aarch64_add_pauth_properties(obj); 727 #else 728 g_assert_not_reached(); 729 #endif 730 } 731 732 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 733 * otherwise, a CPU with as many features enabled as our emulation supports. 734 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; 735 * this only needs to handle 64 bits. 736 */ 737 static void aarch64_max_initfn(Object *obj) 738 { 739 ARMCPU *cpu = ARM_CPU(obj); 740 uint64_t t; 741 uint32_t u; 742 743 if (kvm_enabled() || hvf_enabled()) { 744 /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ 745 aarch64_host_initfn(obj); 746 return; 747 } 748 749 /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */ 750 751 aarch64_a57_initfn(obj); 752 753 /* 754 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real 755 * one and try to apply errata workarounds or use impdef features we 756 * don't provide. 757 * An IMPLEMENTER field of 0 means "reserved for software use"; 758 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers 759 * to see which features are present"; 760 * the VARIANT, PARTNUM and REVISION fields are all implementation 761 * defined and we choose to define PARTNUM just in case guest 762 * code needs to distinguish this QEMU CPU from other software 763 * implementations, though this shouldn't be needed. 764 */ 765 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); 766 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); 767 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); 768 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); 769 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); 770 cpu->midr = t; 771 772 t = cpu->isar.id_aa64isar0; 773 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ 774 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); 775 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ 776 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); 777 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); 778 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); 779 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); 780 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); 781 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); 782 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); 783 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); 784 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ 785 t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ 786 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); 787 cpu->isar.id_aa64isar0 = t; 788 789 t = cpu->isar.id_aa64isar1; 790 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); 791 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); 792 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); 793 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); 794 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); 795 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); 796 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); 797 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ 798 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); 799 cpu->isar.id_aa64isar1 = t; 800 801 t = cpu->isar.id_aa64pfr0; 802 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); 803 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); 804 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); 805 t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); 806 t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); 807 cpu->isar.id_aa64pfr0 = t; 808 809 t = cpu->isar.id_aa64pfr1; 810 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); 811 t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); 812 /* 813 * Begin with full support for MTE. This will be downgraded to MTE=0 814 * during realize if the board provides no tag memory, much like 815 * we do for EL2 with the virtualization=on property. 816 */ 817 t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); 818 cpu->isar.id_aa64pfr1 = t; 819 820 t = cpu->isar.id_aa64mmfr0; 821 t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ 822 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ 823 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ 824 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ 825 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ 826 cpu->isar.id_aa64mmfr0 = t; 827 828 t = cpu->isar.id_aa64mmfr1; 829 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ 830 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); 831 t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); 832 t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ 833 t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ 834 t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ 835 cpu->isar.id_aa64mmfr1 = t; 836 837 t = cpu->isar.id_aa64mmfr2; 838 t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); 839 t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ 840 t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ 841 t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ 842 cpu->isar.id_aa64mmfr2 = t; 843 844 t = cpu->isar.id_aa64zfr0; 845 t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); 846 t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ 847 t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); 848 t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); 849 t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); 850 t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); 851 t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); 852 t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); 853 t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); 854 cpu->isar.id_aa64zfr0 = t; 855 856 /* Replicate the same data to the 32-bit id registers. */ 857 u = cpu->isar.id_isar5; 858 u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ 859 u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); 860 u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); 861 u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); 862 u = FIELD_DP32(u, ID_ISAR5, RDM, 1); 863 u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); 864 cpu->isar.id_isar5 = u; 865 866 u = cpu->isar.id_isar6; 867 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); 868 u = FIELD_DP32(u, ID_ISAR6, DP, 1); 869 u = FIELD_DP32(u, ID_ISAR6, FHM, 1); 870 u = FIELD_DP32(u, ID_ISAR6, SB, 1); 871 u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); 872 u = FIELD_DP32(u, ID_ISAR6, BF16, 1); 873 u = FIELD_DP32(u, ID_ISAR6, I8MM, 1); 874 cpu->isar.id_isar6 = u; 875 876 u = cpu->isar.id_pfr0; 877 u = FIELD_DP32(u, ID_PFR0, DIT, 1); 878 cpu->isar.id_pfr0 = u; 879 880 u = cpu->isar.id_pfr2; 881 u = FIELD_DP32(u, ID_PFR2, SSBS, 1); 882 cpu->isar.id_pfr2 = u; 883 884 u = cpu->isar.id_mmfr3; 885 u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ 886 cpu->isar.id_mmfr3 = u; 887 888 u = cpu->isar.id_mmfr4; 889 u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ 890 u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 891 u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ 892 u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ 893 cpu->isar.id_mmfr4 = u; 894 895 t = cpu->isar.id_aa64dfr0; 896 t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ 897 cpu->isar.id_aa64dfr0 = t; 898 899 u = cpu->isar.id_dfr0; 900 u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ 901 cpu->isar.id_dfr0 = u; 902 903 u = cpu->isar.mvfr1; 904 u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ 905 u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ 906 cpu->isar.mvfr1 = u; 907 908 #ifdef CONFIG_USER_ONLY 909 /* 910 * For usermode -cpu max we can use a larger and more efficient DCZ 911 * blocksize since we don't have to follow what the hardware does. 912 */ 913 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 914 cpu->dcz_blocksize = 7; /* 512 bytes */ 915 #endif 916 917 bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ); 918 919 aarch64_add_pauth_properties(obj); 920 aarch64_add_sve_properties(obj); 921 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, 922 cpu_max_set_sve_max_vq, NULL, NULL); 923 qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); 924 } 925 926 static void aarch64_a64fx_initfn(Object *obj) 927 { 928 ARMCPU *cpu = ARM_CPU(obj); 929 930 cpu->dtb_compatible = "arm,a64fx"; 931 set_feature(&cpu->env, ARM_FEATURE_V8); 932 set_feature(&cpu->env, ARM_FEATURE_NEON); 933 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 934 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 935 set_feature(&cpu->env, ARM_FEATURE_EL2); 936 set_feature(&cpu->env, ARM_FEATURE_EL3); 937 set_feature(&cpu->env, ARM_FEATURE_PMU); 938 cpu->midr = 0x461f0010; 939 cpu->revidr = 0x00000000; 940 cpu->ctr = 0x86668006; 941 cpu->reset_sctlr = 0x30000180; 942 cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */ 943 cpu->isar.id_aa64pfr1 = 0x0000000000000000; 944 cpu->isar.id_aa64dfr0 = 0x0000000010305408; 945 cpu->isar.id_aa64dfr1 = 0x0000000000000000; 946 cpu->id_aa64afr0 = 0x0000000000000000; 947 cpu->id_aa64afr1 = 0x0000000000000000; 948 cpu->isar.id_aa64mmfr0 = 0x0000000000001122; 949 cpu->isar.id_aa64mmfr1 = 0x0000000011212100; 950 cpu->isar.id_aa64mmfr2 = 0x0000000000001011; 951 cpu->isar.id_aa64isar0 = 0x0000000010211120; 952 cpu->isar.id_aa64isar1 = 0x0000000000010001; 953 cpu->isar.id_aa64zfr0 = 0x0000000000000000; 954 cpu->clidr = 0x0000000080000023; 955 cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */ 956 cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */ 957 cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */ 958 cpu->dcz_blocksize = 6; /* 256 bytes */ 959 cpu->gic_num_lrs = 4; 960 cpu->gic_vpribits = 5; 961 cpu->gic_vprebits = 5; 962 963 /* Suppport of A64FX's vector length are 128,256 and 512bit only */ 964 aarch64_add_sve_properties(obj); 965 bitmap_zero(cpu->sve_vq_supported, ARM_MAX_VQ); 966 set_bit(0, cpu->sve_vq_supported); /* 128bit */ 967 set_bit(1, cpu->sve_vq_supported); /* 256bit */ 968 set_bit(3, cpu->sve_vq_supported); /* 512bit */ 969 970 /* TODO: Add A64FX specific HPC extension registers */ 971 } 972 973 static const ARMCPUInfo aarch64_cpus[] = { 974 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 975 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 976 { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, 977 { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, 978 { .name = "max", .initfn = aarch64_max_initfn }, 979 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 980 { .name = "host", .initfn = aarch64_host_initfn }, 981 #endif 982 }; 983 984 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 985 { 986 ARMCPU *cpu = ARM_CPU(obj); 987 988 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 989 } 990 991 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 992 { 993 ARMCPU *cpu = ARM_CPU(obj); 994 995 /* At this time, this property is only allowed if KVM is enabled. This 996 * restriction allows us to avoid fixing up functionality that assumes a 997 * uniform execution state like do_interrupt. 998 */ 999 if (value == false) { 1000 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 1001 error_setg(errp, "'aarch64' feature cannot be disabled " 1002 "unless KVM is enabled and 32-bit EL1 " 1003 "is supported"); 1004 return; 1005 } 1006 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 1007 } else { 1008 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 1009 } 1010 } 1011 1012 static void aarch64_cpu_finalizefn(Object *obj) 1013 { 1014 } 1015 1016 static gchar *aarch64_gdb_arch_name(CPUState *cs) 1017 { 1018 return g_strdup("aarch64"); 1019 } 1020 1021 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 1022 { 1023 CPUClass *cc = CPU_CLASS(oc); 1024 1025 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 1026 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 1027 cc->gdb_num_core_regs = 34; 1028 cc->gdb_core_xml_file = "aarch64-core.xml"; 1029 cc->gdb_arch_name = aarch64_gdb_arch_name; 1030 1031 object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, 1032 aarch64_cpu_set_aarch64); 1033 object_class_property_set_description(oc, "aarch64", 1034 "Set on/off to enable/disable aarch64 " 1035 "execution state "); 1036 } 1037 1038 static void aarch64_cpu_instance_init(Object *obj) 1039 { 1040 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 1041 1042 acc->info->initfn(obj); 1043 arm_cpu_post_init(obj); 1044 } 1045 1046 static void cpu_register_class_init(ObjectClass *oc, void *data) 1047 { 1048 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1049 1050 acc->info = data; 1051 } 1052 1053 void aarch64_cpu_register(const ARMCPUInfo *info) 1054 { 1055 TypeInfo type_info = { 1056 .parent = TYPE_AARCH64_CPU, 1057 .instance_size = sizeof(ARMCPU), 1058 .instance_init = aarch64_cpu_instance_init, 1059 .class_size = sizeof(ARMCPUClass), 1060 .class_init = info->class_init ?: cpu_register_class_init, 1061 .class_data = (void *)info, 1062 }; 1063 1064 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1065 type_register(&type_info); 1066 g_free((void *)type_info.name); 1067 } 1068 1069 static const TypeInfo aarch64_cpu_type_info = { 1070 .name = TYPE_AARCH64_CPU, 1071 .parent = TYPE_ARM_CPU, 1072 .instance_size = sizeof(ARMCPU), 1073 .instance_finalize = aarch64_cpu_finalizefn, 1074 .abstract = true, 1075 .class_size = sizeof(AArch64CPUClass), 1076 .class_init = aarch64_cpu_class_init, 1077 }; 1078 1079 static void aarch64_cpu_register_types(void) 1080 { 1081 size_t i; 1082 1083 type_register_static(&aarch64_cpu_type_info); 1084 1085 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { 1086 aarch64_cpu_register(&aarch64_cpus[i]); 1087 } 1088 } 1089 1090 type_init(aarch64_cpu_register_types) 1091