1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "qemu-common.h" 25 #if !defined(CONFIG_USER_ONLY) 26 #include "hw/loader.h" 27 #endif 28 #include "hw/arm/arm.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 32 static inline void set_feature(CPUARMState *env, int feature) 33 { 34 env->features |= 1ULL << feature; 35 } 36 37 static inline void unset_feature(CPUARMState *env, int feature) 38 { 39 env->features &= ~(1ULL << feature); 40 } 41 42 #ifndef CONFIG_USER_ONLY 43 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 44 { 45 /* Number of processors is in [25:24]; otherwise we RAZ */ 46 return (smp_cpus - 1) << 24; 47 } 48 #endif 49 50 static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = { 51 #ifndef CONFIG_USER_ONLY 52 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, 53 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, 54 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 55 .writefn = arm_cp_write_ignore }, 56 { .name = "L2CTLR", 57 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, 58 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 59 .writefn = arm_cp_write_ignore }, 60 #endif 61 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, 62 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, 63 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 64 { .name = "L2ECTLR", 65 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, 66 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 67 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, 68 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, 69 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 70 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 71 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, 72 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 73 { .name = "CPUACTLR", 74 .cp = 15, .opc1 = 0, .crm = 15, 75 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 76 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 77 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, 78 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 79 { .name = "CPUECTLR", 80 .cp = 15, .opc1 = 1, .crm = 15, 81 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 82 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, 83 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, 84 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 85 { .name = "CPUMERRSR", 86 .cp = 15, .opc1 = 2, .crm = 15, 87 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 88 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, 89 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, 90 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 91 { .name = "L2MERRSR", 92 .cp = 15, .opc1 = 3, .crm = 15, 93 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 94 REGINFO_SENTINEL 95 }; 96 97 static void aarch64_a57_initfn(Object *obj) 98 { 99 ARMCPU *cpu = ARM_CPU(obj); 100 101 cpu->dtb_compatible = "arm,cortex-a57"; 102 set_feature(&cpu->env, ARM_FEATURE_V8); 103 set_feature(&cpu->env, ARM_FEATURE_VFP4); 104 set_feature(&cpu->env, ARM_FEATURE_NEON); 105 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 106 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 107 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 108 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 109 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 110 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 111 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 112 set_feature(&cpu->env, ARM_FEATURE_CRC); 113 set_feature(&cpu->env, ARM_FEATURE_EL2); 114 set_feature(&cpu->env, ARM_FEATURE_EL3); 115 set_feature(&cpu->env, ARM_FEATURE_PMU); 116 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 117 cpu->midr = 0x411fd070; 118 cpu->revidr = 0x00000000; 119 cpu->reset_fpsid = 0x41034070; 120 cpu->mvfr0 = 0x10110222; 121 cpu->mvfr1 = 0x12111111; 122 cpu->mvfr2 = 0x00000043; 123 cpu->ctr = 0x8444c004; 124 cpu->reset_sctlr = 0x00c50838; 125 cpu->id_pfr0 = 0x00000131; 126 cpu->id_pfr1 = 0x00011011; 127 cpu->id_dfr0 = 0x03010066; 128 cpu->id_afr0 = 0x00000000; 129 cpu->id_mmfr0 = 0x10101105; 130 cpu->id_mmfr1 = 0x40000000; 131 cpu->id_mmfr2 = 0x01260000; 132 cpu->id_mmfr3 = 0x02102211; 133 cpu->id_isar0 = 0x02101110; 134 cpu->id_isar1 = 0x13112111; 135 cpu->id_isar2 = 0x21232042; 136 cpu->id_isar3 = 0x01112131; 137 cpu->id_isar4 = 0x00011142; 138 cpu->id_isar5 = 0x00011121; 139 cpu->id_aa64pfr0 = 0x00002222; 140 cpu->id_aa64dfr0 = 0x10305106; 141 cpu->pmceid0 = 0x00000000; 142 cpu->pmceid1 = 0x00000000; 143 cpu->id_aa64isar0 = 0x00011120; 144 cpu->id_aa64mmfr0 = 0x00001124; 145 cpu->dbgdidr = 0x3516d000; 146 cpu->clidr = 0x0a200023; 147 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 148 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 149 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 150 cpu->dcz_blocksize = 4; /* 64 bytes */ 151 cpu->gic_num_lrs = 4; 152 cpu->gic_vpribits = 5; 153 cpu->gic_vprebits = 5; 154 define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); 155 } 156 157 static void aarch64_a53_initfn(Object *obj) 158 { 159 ARMCPU *cpu = ARM_CPU(obj); 160 161 cpu->dtb_compatible = "arm,cortex-a53"; 162 set_feature(&cpu->env, ARM_FEATURE_V8); 163 set_feature(&cpu->env, ARM_FEATURE_VFP4); 164 set_feature(&cpu->env, ARM_FEATURE_NEON); 165 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 166 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 167 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 168 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 169 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 170 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 171 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 172 set_feature(&cpu->env, ARM_FEATURE_CRC); 173 set_feature(&cpu->env, ARM_FEATURE_EL2); 174 set_feature(&cpu->env, ARM_FEATURE_EL3); 175 set_feature(&cpu->env, ARM_FEATURE_PMU); 176 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 177 cpu->midr = 0x410fd034; 178 cpu->revidr = 0x00000000; 179 cpu->reset_fpsid = 0x41034070; 180 cpu->mvfr0 = 0x10110222; 181 cpu->mvfr1 = 0x12111111; 182 cpu->mvfr2 = 0x00000043; 183 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 184 cpu->reset_sctlr = 0x00c50838; 185 cpu->id_pfr0 = 0x00000131; 186 cpu->id_pfr1 = 0x00011011; 187 cpu->id_dfr0 = 0x03010066; 188 cpu->id_afr0 = 0x00000000; 189 cpu->id_mmfr0 = 0x10101105; 190 cpu->id_mmfr1 = 0x40000000; 191 cpu->id_mmfr2 = 0x01260000; 192 cpu->id_mmfr3 = 0x02102211; 193 cpu->id_isar0 = 0x02101110; 194 cpu->id_isar1 = 0x13112111; 195 cpu->id_isar2 = 0x21232042; 196 cpu->id_isar3 = 0x01112131; 197 cpu->id_isar4 = 0x00011142; 198 cpu->id_isar5 = 0x00011121; 199 cpu->id_aa64pfr0 = 0x00002222; 200 cpu->id_aa64dfr0 = 0x10305106; 201 cpu->id_aa64isar0 = 0x00011120; 202 cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 203 cpu->dbgdidr = 0x3516d000; 204 cpu->clidr = 0x0a200023; 205 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 206 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 207 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 208 cpu->dcz_blocksize = 4; /* 64 bytes */ 209 cpu->gic_num_lrs = 4; 210 cpu->gic_vpribits = 5; 211 cpu->gic_vprebits = 5; 212 define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); 213 } 214 215 #ifdef CONFIG_USER_ONLY 216 static void aarch64_any_initfn(Object *obj) 217 { 218 ARMCPU *cpu = ARM_CPU(obj); 219 220 set_feature(&cpu->env, ARM_FEATURE_V8); 221 set_feature(&cpu->env, ARM_FEATURE_VFP4); 222 set_feature(&cpu->env, ARM_FEATURE_NEON); 223 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 224 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 225 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 226 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 227 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 228 set_feature(&cpu->env, ARM_FEATURE_CRC); 229 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 230 cpu->dcz_blocksize = 7; /* 512 bytes */ 231 } 232 #endif 233 234 typedef struct ARMCPUInfo { 235 const char *name; 236 void (*initfn)(Object *obj); 237 void (*class_init)(ObjectClass *oc, void *data); 238 } ARMCPUInfo; 239 240 static const ARMCPUInfo aarch64_cpus[] = { 241 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 242 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 243 #ifdef CONFIG_USER_ONLY 244 { .name = "any", .initfn = aarch64_any_initfn }, 245 #endif 246 { .name = NULL } 247 }; 248 249 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 250 { 251 ARMCPU *cpu = ARM_CPU(obj); 252 253 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 254 } 255 256 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 257 { 258 ARMCPU *cpu = ARM_CPU(obj); 259 260 /* At this time, this property is only allowed if KVM is enabled. This 261 * restriction allows us to avoid fixing up functionality that assumes a 262 * uniform execution state like do_interrupt. 263 */ 264 if (!kvm_enabled()) { 265 error_setg(errp, "'aarch64' feature cannot be disabled " 266 "unless KVM is enabled"); 267 return; 268 } 269 270 if (value == false) { 271 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 272 } else { 273 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 274 } 275 } 276 277 static void aarch64_cpu_initfn(Object *obj) 278 { 279 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, 280 aarch64_cpu_set_aarch64, NULL); 281 object_property_set_description(obj, "aarch64", 282 "Set on/off to enable/disable aarch64 " 283 "execution state ", 284 NULL); 285 } 286 287 static void aarch64_cpu_finalizefn(Object *obj) 288 { 289 } 290 291 static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) 292 { 293 ARMCPU *cpu = ARM_CPU(cs); 294 /* It's OK to look at env for the current mode here, because it's 295 * never possible for an AArch64 TB to chain to an AArch32 TB. 296 * (Otherwise we would need to use synchronize_from_tb instead.) 297 */ 298 if (is_a64(&cpu->env)) { 299 cpu->env.pc = value; 300 } else { 301 cpu->env.regs[15] = value; 302 } 303 } 304 305 static gchar *aarch64_gdb_arch_name(CPUState *cs) 306 { 307 return g_strdup("aarch64"); 308 } 309 310 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 311 { 312 CPUClass *cc = CPU_CLASS(oc); 313 314 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 315 cc->set_pc = aarch64_cpu_set_pc; 316 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 317 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 318 cc->gdb_num_core_regs = 34; 319 cc->gdb_core_xml_file = "aarch64-core.xml"; 320 cc->gdb_arch_name = aarch64_gdb_arch_name; 321 } 322 323 static void aarch64_cpu_register(const ARMCPUInfo *info) 324 { 325 TypeInfo type_info = { 326 .parent = TYPE_AARCH64_CPU, 327 .instance_size = sizeof(ARMCPU), 328 .instance_init = info->initfn, 329 .class_size = sizeof(ARMCPUClass), 330 .class_init = info->class_init, 331 }; 332 333 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 334 type_register(&type_info); 335 g_free((void *)type_info.name); 336 } 337 338 static const TypeInfo aarch64_cpu_type_info = { 339 .name = TYPE_AARCH64_CPU, 340 .parent = TYPE_ARM_CPU, 341 .instance_size = sizeof(ARMCPU), 342 .instance_init = aarch64_cpu_initfn, 343 .instance_finalize = aarch64_cpu_finalizefn, 344 .abstract = true, 345 .class_size = sizeof(AArch64CPUClass), 346 .class_init = aarch64_cpu_class_init, 347 }; 348 349 static void aarch64_cpu_register_types(void) 350 { 351 const ARMCPUInfo *info = aarch64_cpus; 352 353 type_register_static(&aarch64_cpu_type_info); 354 355 while (info->name) { 356 aarch64_cpu_register(info); 357 info++; 358 } 359 } 360 361 type_init(aarch64_cpu_register_types) 362