1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "qemu/module.h" 25 #if !defined(CONFIG_USER_ONLY) 26 #include "hw/loader.h" 27 #endif 28 #include "sysemu/kvm.h" 29 #include "kvm_arm.h" 30 #include "qapi/visitor.h" 31 32 #ifndef CONFIG_USER_ONLY 33 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 34 { 35 ARMCPU *cpu = env_archcpu(env); 36 37 /* Number of cores is in [25:24]; otherwise we RAZ */ 38 return (cpu->core_count - 1) << 24; 39 } 40 #endif 41 42 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { 43 #ifndef CONFIG_USER_ONLY 44 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, 45 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, 46 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 47 .writefn = arm_cp_write_ignore }, 48 { .name = "L2CTLR", 49 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, 50 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 51 .writefn = arm_cp_write_ignore }, 52 #endif 53 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, 54 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, 55 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 56 { .name = "L2ECTLR", 57 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, 58 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 59 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, 60 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, 61 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 62 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 63 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, 64 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 65 { .name = "CPUACTLR", 66 .cp = 15, .opc1 = 0, .crm = 15, 67 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 68 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 69 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, 70 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 71 { .name = "CPUECTLR", 72 .cp = 15, .opc1 = 1, .crm = 15, 73 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 74 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, 75 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, 76 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 77 { .name = "CPUMERRSR", 78 .cp = 15, .opc1 = 2, .crm = 15, 79 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 80 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, 81 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, 82 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 83 { .name = "L2MERRSR", 84 .cp = 15, .opc1 = 3, .crm = 15, 85 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 86 REGINFO_SENTINEL 87 }; 88 89 static void aarch64_a57_initfn(Object *obj) 90 { 91 ARMCPU *cpu = ARM_CPU(obj); 92 93 cpu->dtb_compatible = "arm,cortex-a57"; 94 set_feature(&cpu->env, ARM_FEATURE_V8); 95 set_feature(&cpu->env, ARM_FEATURE_NEON); 96 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 97 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 98 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 99 set_feature(&cpu->env, ARM_FEATURE_EL2); 100 set_feature(&cpu->env, ARM_FEATURE_EL3); 101 set_feature(&cpu->env, ARM_FEATURE_PMU); 102 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 103 cpu->midr = 0x411fd070; 104 cpu->revidr = 0x00000000; 105 cpu->reset_fpsid = 0x41034070; 106 cpu->isar.mvfr0 = 0x10110222; 107 cpu->isar.mvfr1 = 0x12111111; 108 cpu->isar.mvfr2 = 0x00000043; 109 cpu->ctr = 0x8444c004; 110 cpu->reset_sctlr = 0x00c50838; 111 cpu->isar.id_pfr0 = 0x00000131; 112 cpu->isar.id_pfr1 = 0x00011011; 113 cpu->isar.id_dfr0 = 0x03010066; 114 cpu->id_afr0 = 0x00000000; 115 cpu->isar.id_mmfr0 = 0x10101105; 116 cpu->isar.id_mmfr1 = 0x40000000; 117 cpu->isar.id_mmfr2 = 0x01260000; 118 cpu->isar.id_mmfr3 = 0x02102211; 119 cpu->isar.id_isar0 = 0x02101110; 120 cpu->isar.id_isar1 = 0x13112111; 121 cpu->isar.id_isar2 = 0x21232042; 122 cpu->isar.id_isar3 = 0x01112131; 123 cpu->isar.id_isar4 = 0x00011142; 124 cpu->isar.id_isar5 = 0x00011121; 125 cpu->isar.id_isar6 = 0; 126 cpu->isar.id_aa64pfr0 = 0x00002222; 127 cpu->isar.id_aa64dfr0 = 0x10305106; 128 cpu->isar.id_aa64isar0 = 0x00011120; 129 cpu->isar.id_aa64mmfr0 = 0x00001124; 130 cpu->isar.dbgdidr = 0x3516d000; 131 cpu->clidr = 0x0a200023; 132 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 133 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 134 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 135 cpu->dcz_blocksize = 4; /* 64 bytes */ 136 cpu->gic_num_lrs = 4; 137 cpu->gic_vpribits = 5; 138 cpu->gic_vprebits = 5; 139 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 140 } 141 142 static void aarch64_a53_initfn(Object *obj) 143 { 144 ARMCPU *cpu = ARM_CPU(obj); 145 146 cpu->dtb_compatible = "arm,cortex-a53"; 147 set_feature(&cpu->env, ARM_FEATURE_V8); 148 set_feature(&cpu->env, ARM_FEATURE_NEON); 149 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 150 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 151 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 152 set_feature(&cpu->env, ARM_FEATURE_EL2); 153 set_feature(&cpu->env, ARM_FEATURE_EL3); 154 set_feature(&cpu->env, ARM_FEATURE_PMU); 155 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 156 cpu->midr = 0x410fd034; 157 cpu->revidr = 0x00000000; 158 cpu->reset_fpsid = 0x41034070; 159 cpu->isar.mvfr0 = 0x10110222; 160 cpu->isar.mvfr1 = 0x12111111; 161 cpu->isar.mvfr2 = 0x00000043; 162 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 163 cpu->reset_sctlr = 0x00c50838; 164 cpu->isar.id_pfr0 = 0x00000131; 165 cpu->isar.id_pfr1 = 0x00011011; 166 cpu->isar.id_dfr0 = 0x03010066; 167 cpu->id_afr0 = 0x00000000; 168 cpu->isar.id_mmfr0 = 0x10101105; 169 cpu->isar.id_mmfr1 = 0x40000000; 170 cpu->isar.id_mmfr2 = 0x01260000; 171 cpu->isar.id_mmfr3 = 0x02102211; 172 cpu->isar.id_isar0 = 0x02101110; 173 cpu->isar.id_isar1 = 0x13112111; 174 cpu->isar.id_isar2 = 0x21232042; 175 cpu->isar.id_isar3 = 0x01112131; 176 cpu->isar.id_isar4 = 0x00011142; 177 cpu->isar.id_isar5 = 0x00011121; 178 cpu->isar.id_isar6 = 0; 179 cpu->isar.id_aa64pfr0 = 0x00002222; 180 cpu->isar.id_aa64dfr0 = 0x10305106; 181 cpu->isar.id_aa64isar0 = 0x00011120; 182 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 183 cpu->isar.dbgdidr = 0x3516d000; 184 cpu->clidr = 0x0a200023; 185 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 186 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 187 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 188 cpu->dcz_blocksize = 4; /* 64 bytes */ 189 cpu->gic_num_lrs = 4; 190 cpu->gic_vpribits = 5; 191 cpu->gic_vprebits = 5; 192 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 193 } 194 195 static void aarch64_a72_initfn(Object *obj) 196 { 197 ARMCPU *cpu = ARM_CPU(obj); 198 199 cpu->dtb_compatible = "arm,cortex-a72"; 200 set_feature(&cpu->env, ARM_FEATURE_V8); 201 set_feature(&cpu->env, ARM_FEATURE_NEON); 202 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 203 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 204 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 205 set_feature(&cpu->env, ARM_FEATURE_EL2); 206 set_feature(&cpu->env, ARM_FEATURE_EL3); 207 set_feature(&cpu->env, ARM_FEATURE_PMU); 208 cpu->midr = 0x410fd083; 209 cpu->revidr = 0x00000000; 210 cpu->reset_fpsid = 0x41034080; 211 cpu->isar.mvfr0 = 0x10110222; 212 cpu->isar.mvfr1 = 0x12111111; 213 cpu->isar.mvfr2 = 0x00000043; 214 cpu->ctr = 0x8444c004; 215 cpu->reset_sctlr = 0x00c50838; 216 cpu->isar.id_pfr0 = 0x00000131; 217 cpu->isar.id_pfr1 = 0x00011011; 218 cpu->isar.id_dfr0 = 0x03010066; 219 cpu->id_afr0 = 0x00000000; 220 cpu->isar.id_mmfr0 = 0x10201105; 221 cpu->isar.id_mmfr1 = 0x40000000; 222 cpu->isar.id_mmfr2 = 0x01260000; 223 cpu->isar.id_mmfr3 = 0x02102211; 224 cpu->isar.id_isar0 = 0x02101110; 225 cpu->isar.id_isar1 = 0x13112111; 226 cpu->isar.id_isar2 = 0x21232042; 227 cpu->isar.id_isar3 = 0x01112131; 228 cpu->isar.id_isar4 = 0x00011142; 229 cpu->isar.id_isar5 = 0x00011121; 230 cpu->isar.id_aa64pfr0 = 0x00002222; 231 cpu->isar.id_aa64dfr0 = 0x10305106; 232 cpu->isar.id_aa64isar0 = 0x00011120; 233 cpu->isar.id_aa64mmfr0 = 0x00001124; 234 cpu->isar.dbgdidr = 0x3516d000; 235 cpu->clidr = 0x0a200023; 236 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 237 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 238 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ 239 cpu->dcz_blocksize = 4; /* 64 bytes */ 240 cpu->gic_num_lrs = 4; 241 cpu->gic_vpribits = 5; 242 cpu->gic_vprebits = 5; 243 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 244 } 245 246 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) 247 { 248 /* 249 * If any vector lengths are explicitly enabled with sve<N> properties, 250 * then all other lengths are implicitly disabled. If sve-max-vq is 251 * specified then it is the same as explicitly enabling all lengths 252 * up to and including the specified maximum, which means all larger 253 * lengths will be implicitly disabled. If no sve<N> properties 254 * are enabled and sve-max-vq is not specified, then all lengths not 255 * explicitly disabled will be enabled. Additionally, all power-of-two 256 * vector lengths less than the maximum enabled length will be 257 * automatically enabled and all vector lengths larger than the largest 258 * disabled power-of-two vector length will be automatically disabled. 259 * Errors are generated if the user provided input that interferes with 260 * any of the above. Finally, if SVE is not disabled, then at least one 261 * vector length must be enabled. 262 */ 263 DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ); 264 DECLARE_BITMAP(tmp, ARM_MAX_VQ); 265 uint32_t vq, max_vq = 0; 266 267 /* Collect the set of vector lengths supported by KVM. */ 268 bitmap_zero(kvm_supported, ARM_MAX_VQ); 269 if (kvm_enabled() && kvm_arm_sve_supported()) { 270 kvm_arm_sve_get_vls(CPU(cpu), kvm_supported); 271 } else if (kvm_enabled()) { 272 assert(!cpu_isar_feature(aa64_sve, cpu)); 273 } 274 275 /* 276 * Process explicit sve<N> properties. 277 * From the properties, sve_vq_map<N> implies sve_vq_init<N>. 278 * Check first for any sve<N> enabled. 279 */ 280 if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) { 281 max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; 282 283 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { 284 error_setg(errp, "cannot enable sve%d", max_vq * 128); 285 error_append_hint(errp, "sve%d is larger than the maximum vector " 286 "length, sve-max-vq=%d (%d bits)\n", 287 max_vq * 128, cpu->sve_max_vq, 288 cpu->sve_max_vq * 128); 289 return; 290 } 291 292 if (kvm_enabled()) { 293 /* 294 * For KVM we have to automatically enable all supported unitialized 295 * lengths, even when the smaller lengths are not all powers-of-two. 296 */ 297 bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq); 298 bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); 299 } else { 300 /* Propagate enabled bits down through required powers-of-two. */ 301 for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { 302 if (!test_bit(vq - 1, cpu->sve_vq_init)) { 303 set_bit(vq - 1, cpu->sve_vq_map); 304 } 305 } 306 } 307 } else if (cpu->sve_max_vq == 0) { 308 /* 309 * No explicit bits enabled, and no implicit bits from sve-max-vq. 310 */ 311 if (!cpu_isar_feature(aa64_sve, cpu)) { 312 /* SVE is disabled and so are all vector lengths. Good. */ 313 return; 314 } 315 316 if (kvm_enabled()) { 317 /* Disabling a supported length disables all larger lengths. */ 318 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 319 if (test_bit(vq - 1, cpu->sve_vq_init) && 320 test_bit(vq - 1, kvm_supported)) { 321 break; 322 } 323 } 324 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 325 bitmap_andnot(cpu->sve_vq_map, kvm_supported, 326 cpu->sve_vq_init, max_vq); 327 if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) { 328 error_setg(errp, "cannot disable sve%d", vq * 128); 329 error_append_hint(errp, "Disabling sve%d results in all " 330 "vector lengths being disabled.\n", 331 vq * 128); 332 error_append_hint(errp, "With SVE enabled, at least one " 333 "vector length must be enabled.\n"); 334 return; 335 } 336 } else { 337 /* Disabling a power-of-two disables all larger lengths. */ 338 if (test_bit(0, cpu->sve_vq_init)) { 339 error_setg(errp, "cannot disable sve128"); 340 error_append_hint(errp, "Disabling sve128 results in all " 341 "vector lengths being disabled.\n"); 342 error_append_hint(errp, "With SVE enabled, at least one " 343 "vector length must be enabled.\n"); 344 return; 345 } 346 for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) { 347 if (test_bit(vq - 1, cpu->sve_vq_init)) { 348 break; 349 } 350 } 351 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 352 bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq); 353 } 354 355 max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1; 356 } 357 358 /* 359 * Process the sve-max-vq property. 360 * Note that we know from the above that no bit above 361 * sve-max-vq is currently set. 362 */ 363 if (cpu->sve_max_vq != 0) { 364 max_vq = cpu->sve_max_vq; 365 366 if (!test_bit(max_vq - 1, cpu->sve_vq_map) && 367 test_bit(max_vq - 1, cpu->sve_vq_init)) { 368 error_setg(errp, "cannot disable sve%d", max_vq * 128); 369 error_append_hint(errp, "The maximum vector length must be " 370 "enabled, sve-max-vq=%d (%d bits)\n", 371 max_vq, max_vq * 128); 372 return; 373 } 374 375 /* Set all bits not explicitly set within sve-max-vq. */ 376 bitmap_complement(tmp, cpu->sve_vq_init, max_vq); 377 bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); 378 } 379 380 /* 381 * We should know what max-vq is now. Also, as we're done 382 * manipulating sve-vq-map, we ensure any bits above max-vq 383 * are clear, just in case anybody looks. 384 */ 385 assert(max_vq != 0); 386 bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq); 387 388 if (kvm_enabled()) { 389 /* Ensure the set of lengths matches what KVM supports. */ 390 bitmap_xor(tmp, cpu->sve_vq_map, kvm_supported, max_vq); 391 if (!bitmap_empty(tmp, max_vq)) { 392 vq = find_last_bit(tmp, max_vq) + 1; 393 if (test_bit(vq - 1, cpu->sve_vq_map)) { 394 if (cpu->sve_max_vq) { 395 error_setg(errp, "cannot set sve-max-vq=%d", 396 cpu->sve_max_vq); 397 error_append_hint(errp, "This KVM host does not support " 398 "the vector length %d-bits.\n", 399 vq * 128); 400 error_append_hint(errp, "It may not be possible to use " 401 "sve-max-vq with this KVM host. Try " 402 "using only sve<N> properties.\n"); 403 } else { 404 error_setg(errp, "cannot enable sve%d", vq * 128); 405 error_append_hint(errp, "This KVM host does not support " 406 "the vector length %d-bits.\n", 407 vq * 128); 408 } 409 } else { 410 error_setg(errp, "cannot disable sve%d", vq * 128); 411 error_append_hint(errp, "The KVM host requires all " 412 "supported vector lengths smaller " 413 "than %d bits to also be enabled.\n", 414 max_vq * 128); 415 } 416 return; 417 } 418 } else { 419 /* Ensure all required powers-of-two are enabled. */ 420 for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { 421 if (!test_bit(vq - 1, cpu->sve_vq_map)) { 422 error_setg(errp, "cannot disable sve%d", vq * 128); 423 error_append_hint(errp, "sve%d is required as it " 424 "is a power-of-two length smaller than " 425 "the maximum, sve%d\n", 426 vq * 128, max_vq * 128); 427 return; 428 } 429 } 430 } 431 432 /* 433 * Now that we validated all our vector lengths, the only question 434 * left to answer is if we even want SVE at all. 435 */ 436 if (!cpu_isar_feature(aa64_sve, cpu)) { 437 error_setg(errp, "cannot enable sve%d", max_vq * 128); 438 error_append_hint(errp, "SVE must be enabled to enable vector " 439 "lengths.\n"); 440 error_append_hint(errp, "Add sve=on to the CPU property list.\n"); 441 return; 442 } 443 444 /* From now on sve_max_vq is the actual maximum supported length. */ 445 cpu->sve_max_vq = max_vq; 446 } 447 448 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, 449 void *opaque, Error **errp) 450 { 451 ARMCPU *cpu = ARM_CPU(obj); 452 uint32_t value; 453 454 /* All vector lengths are disabled when SVE is off. */ 455 if (!cpu_isar_feature(aa64_sve, cpu)) { 456 value = 0; 457 } else { 458 value = cpu->sve_max_vq; 459 } 460 visit_type_uint32(v, name, &value, errp); 461 } 462 463 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, 464 void *opaque, Error **errp) 465 { 466 ARMCPU *cpu = ARM_CPU(obj); 467 uint32_t max_vq; 468 469 if (!visit_type_uint32(v, name, &max_vq, errp)) { 470 return; 471 } 472 473 if (kvm_enabled() && !kvm_arm_sve_supported()) { 474 error_setg(errp, "cannot set sve-max-vq"); 475 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 476 return; 477 } 478 479 if (max_vq == 0 || max_vq > ARM_MAX_VQ) { 480 error_setg(errp, "unsupported SVE vector length"); 481 error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", 482 ARM_MAX_VQ); 483 return; 484 } 485 486 cpu->sve_max_vq = max_vq; 487 } 488 489 static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, 490 void *opaque, Error **errp) 491 { 492 ARMCPU *cpu = ARM_CPU(obj); 493 uint32_t vq = atoi(&name[3]) / 128; 494 bool value; 495 496 /* All vector lengths are disabled when SVE is off. */ 497 if (!cpu_isar_feature(aa64_sve, cpu)) { 498 value = false; 499 } else { 500 value = test_bit(vq - 1, cpu->sve_vq_map); 501 } 502 visit_type_bool(v, name, &value, errp); 503 } 504 505 static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, 506 void *opaque, Error **errp) 507 { 508 ARMCPU *cpu = ARM_CPU(obj); 509 uint32_t vq = atoi(&name[3]) / 128; 510 bool value; 511 512 if (!visit_type_bool(v, name, &value, errp)) { 513 return; 514 } 515 516 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 517 error_setg(errp, "cannot enable %s", name); 518 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 519 return; 520 } 521 522 if (value) { 523 set_bit(vq - 1, cpu->sve_vq_map); 524 } else { 525 clear_bit(vq - 1, cpu->sve_vq_map); 526 } 527 set_bit(vq - 1, cpu->sve_vq_init); 528 } 529 530 static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name, 531 void *opaque, Error **errp) 532 { 533 ARMCPU *cpu = ARM_CPU(obj); 534 bool value = cpu_isar_feature(aa64_sve, cpu); 535 536 visit_type_bool(v, name, &value, errp); 537 } 538 539 static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name, 540 void *opaque, Error **errp) 541 { 542 ARMCPU *cpu = ARM_CPU(obj); 543 bool value; 544 uint64_t t; 545 546 if (!visit_type_bool(v, name, &value, errp)) { 547 return; 548 } 549 550 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 551 error_setg(errp, "'sve' feature not supported by KVM on this host"); 552 return; 553 } 554 555 t = cpu->isar.id_aa64pfr0; 556 t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); 557 cpu->isar.id_aa64pfr0 = t; 558 } 559 560 void aarch64_add_sve_properties(Object *obj) 561 { 562 uint32_t vq; 563 564 object_property_add(obj, "sve", "bool", cpu_arm_get_sve, 565 cpu_arm_set_sve, NULL, NULL); 566 567 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 568 char name[8]; 569 sprintf(name, "sve%d", vq * 128); 570 object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, 571 cpu_arm_set_sve_vq, NULL, NULL); 572 } 573 } 574 575 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 576 * otherwise, a CPU with as many features enabled as our emulation supports. 577 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; 578 * this only needs to handle 64 bits. 579 */ 580 static void aarch64_max_initfn(Object *obj) 581 { 582 ARMCPU *cpu = ARM_CPU(obj); 583 584 if (kvm_enabled()) { 585 kvm_arm_set_cpu_features_from_host(cpu); 586 } else { 587 uint64_t t; 588 uint32_t u; 589 aarch64_a57_initfn(obj); 590 591 /* 592 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real 593 * one and try to apply errata workarounds or use impdef features we 594 * don't provide. 595 * An IMPLEMENTER field of 0 means "reserved for software use"; 596 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers 597 * to see which features are present"; 598 * the VARIANT, PARTNUM and REVISION fields are all implementation 599 * defined and we choose to define PARTNUM just in case guest 600 * code needs to distinguish this QEMU CPU from other software 601 * implementations, though this shouldn't be needed. 602 */ 603 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); 604 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); 605 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); 606 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); 607 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); 608 cpu->midr = t; 609 610 t = cpu->isar.id_aa64isar0; 611 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ 612 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); 613 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ 614 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); 615 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); 616 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); 617 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); 618 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); 619 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); 620 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); 621 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); 622 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ 623 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); 624 cpu->isar.id_aa64isar0 = t; 625 626 t = cpu->isar.id_aa64isar1; 627 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); 628 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); 629 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); 630 t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ 631 t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); 632 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); 633 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); 634 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); 635 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); 636 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); 637 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ 638 cpu->isar.id_aa64isar1 = t; 639 640 t = cpu->isar.id_aa64pfr0; 641 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); 642 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); 643 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); 644 cpu->isar.id_aa64pfr0 = t; 645 646 t = cpu->isar.id_aa64pfr1; 647 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); 648 /* 649 * Begin with full support for MTE. This will be downgraded to MTE=0 650 * during realize if the board provides no tag memory, much like 651 * we do for EL2 with the virtualization=on property. 652 */ 653 t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); 654 cpu->isar.id_aa64pfr1 = t; 655 656 t = cpu->isar.id_aa64mmfr0; 657 t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ 658 cpu->isar.id_aa64mmfr0 = t; 659 660 t = cpu->isar.id_aa64mmfr1; 661 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ 662 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); 663 t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); 664 t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ 665 t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ 666 t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ 667 cpu->isar.id_aa64mmfr1 = t; 668 669 t = cpu->isar.id_aa64mmfr2; 670 t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); 671 t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ 672 cpu->isar.id_aa64mmfr2 = t; 673 674 /* Replicate the same data to the 32-bit id registers. */ 675 u = cpu->isar.id_isar5; 676 u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ 677 u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); 678 u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); 679 u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); 680 u = FIELD_DP32(u, ID_ISAR5, RDM, 1); 681 u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); 682 cpu->isar.id_isar5 = u; 683 684 u = cpu->isar.id_isar6; 685 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); 686 u = FIELD_DP32(u, ID_ISAR6, DP, 1); 687 u = FIELD_DP32(u, ID_ISAR6, FHM, 1); 688 u = FIELD_DP32(u, ID_ISAR6, SB, 1); 689 u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); 690 cpu->isar.id_isar6 = u; 691 692 u = cpu->isar.id_mmfr3; 693 u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ 694 cpu->isar.id_mmfr3 = u; 695 696 u = cpu->isar.id_mmfr4; 697 u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ 698 u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 699 u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ 700 u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ 701 cpu->isar.id_mmfr4 = u; 702 703 t = cpu->isar.id_aa64dfr0; 704 t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ 705 cpu->isar.id_aa64dfr0 = t; 706 707 u = cpu->isar.id_dfr0; 708 u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ 709 cpu->isar.id_dfr0 = u; 710 711 u = cpu->isar.mvfr1; 712 u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ 713 u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ 714 cpu->isar.mvfr1 = u; 715 716 #ifdef CONFIG_USER_ONLY 717 /* For usermode -cpu max we can use a larger and more efficient DCZ 718 * blocksize since we don't have to follow what the hardware does. 719 */ 720 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 721 cpu->dcz_blocksize = 7; /* 512 bytes */ 722 #endif 723 } 724 725 aarch64_add_sve_properties(obj); 726 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, 727 cpu_max_set_sve_max_vq, NULL, NULL); 728 } 729 730 static const ARMCPUInfo aarch64_cpus[] = { 731 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 732 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 733 { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, 734 { .name = "max", .initfn = aarch64_max_initfn }, 735 }; 736 737 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 738 { 739 ARMCPU *cpu = ARM_CPU(obj); 740 741 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 742 } 743 744 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 745 { 746 ARMCPU *cpu = ARM_CPU(obj); 747 748 /* At this time, this property is only allowed if KVM is enabled. This 749 * restriction allows us to avoid fixing up functionality that assumes a 750 * uniform execution state like do_interrupt. 751 */ 752 if (value == false) { 753 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 754 error_setg(errp, "'aarch64' feature cannot be disabled " 755 "unless KVM is enabled and 32-bit EL1 " 756 "is supported"); 757 return; 758 } 759 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 760 } else { 761 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 762 } 763 } 764 765 static void aarch64_cpu_initfn(Object *obj) 766 { 767 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, 768 aarch64_cpu_set_aarch64); 769 object_property_set_description(obj, "aarch64", 770 "Set on/off to enable/disable aarch64 " 771 "execution state "); 772 } 773 774 static void aarch64_cpu_finalizefn(Object *obj) 775 { 776 } 777 778 static gchar *aarch64_gdb_arch_name(CPUState *cs) 779 { 780 return g_strdup("aarch64"); 781 } 782 783 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 784 { 785 CPUClass *cc = CPU_CLASS(oc); 786 787 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 788 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 789 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 790 cc->gdb_num_core_regs = 34; 791 cc->gdb_core_xml_file = "aarch64-core.xml"; 792 cc->gdb_arch_name = aarch64_gdb_arch_name; 793 } 794 795 static void aarch64_cpu_instance_init(Object *obj) 796 { 797 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 798 799 acc->info->initfn(obj); 800 arm_cpu_post_init(obj); 801 } 802 803 static void cpu_register_class_init(ObjectClass *oc, void *data) 804 { 805 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 806 807 acc->info = data; 808 } 809 810 void aarch64_cpu_register(const ARMCPUInfo *info) 811 { 812 TypeInfo type_info = { 813 .parent = TYPE_AARCH64_CPU, 814 .instance_size = sizeof(ARMCPU), 815 .instance_init = aarch64_cpu_instance_init, 816 .class_size = sizeof(ARMCPUClass), 817 .class_init = info->class_init ?: cpu_register_class_init, 818 .class_data = (void *)info, 819 }; 820 821 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 822 type_register(&type_info); 823 g_free((void *)type_info.name); 824 } 825 826 static const TypeInfo aarch64_cpu_type_info = { 827 .name = TYPE_AARCH64_CPU, 828 .parent = TYPE_ARM_CPU, 829 .instance_size = sizeof(ARMCPU), 830 .instance_init = aarch64_cpu_initfn, 831 .instance_finalize = aarch64_cpu_finalizefn, 832 .abstract = true, 833 .class_size = sizeof(AArch64CPUClass), 834 .class_init = aarch64_cpu_class_init, 835 }; 836 837 static void aarch64_cpu_register_types(void) 838 { 839 size_t i; 840 841 type_register_static(&aarch64_cpu_type_info); 842 843 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { 844 aarch64_cpu_register(&aarch64_cpus[i]); 845 } 846 } 847 848 type_init(aarch64_cpu_register_types) 849