1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #ifdef CONFIG_TCG 25 #include "hw/core/tcg-cpu-ops.h" 26 #endif /* CONFIG_TCG */ 27 #include "qemu/module.h" 28 #if !defined(CONFIG_USER_ONLY) 29 #include "hw/loader.h" 30 #endif 31 #include "sysemu/kvm.h" 32 #include "sysemu/hvf.h" 33 #include "kvm_arm.h" 34 #include "hvf_arm.h" 35 #include "qapi/visitor.h" 36 #include "hw/qdev-properties.h" 37 #include "internals.h" 38 39 static void aarch64_a35_initfn(Object *obj) 40 { 41 ARMCPU *cpu = ARM_CPU(obj); 42 43 cpu->dtb_compatible = "arm,cortex-a35"; 44 set_feature(&cpu->env, ARM_FEATURE_V8); 45 set_feature(&cpu->env, ARM_FEATURE_NEON); 46 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 47 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 48 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 49 set_feature(&cpu->env, ARM_FEATURE_EL2); 50 set_feature(&cpu->env, ARM_FEATURE_EL3); 51 set_feature(&cpu->env, ARM_FEATURE_PMU); 52 53 /* From B2.2 AArch64 identification registers. */ 54 cpu->midr = 0x411fd040; 55 cpu->revidr = 0; 56 cpu->ctr = 0x84448004; 57 cpu->isar.id_pfr0 = 0x00000131; 58 cpu->isar.id_pfr1 = 0x00011011; 59 cpu->isar.id_dfr0 = 0x03010066; 60 cpu->id_afr0 = 0; 61 cpu->isar.id_mmfr0 = 0x10201105; 62 cpu->isar.id_mmfr1 = 0x40000000; 63 cpu->isar.id_mmfr2 = 0x01260000; 64 cpu->isar.id_mmfr3 = 0x02102211; 65 cpu->isar.id_isar0 = 0x02101110; 66 cpu->isar.id_isar1 = 0x13112111; 67 cpu->isar.id_isar2 = 0x21232042; 68 cpu->isar.id_isar3 = 0x01112131; 69 cpu->isar.id_isar4 = 0x00011142; 70 cpu->isar.id_isar5 = 0x00011121; 71 cpu->isar.id_aa64pfr0 = 0x00002222; 72 cpu->isar.id_aa64pfr1 = 0; 73 cpu->isar.id_aa64dfr0 = 0x10305106; 74 cpu->isar.id_aa64dfr1 = 0; 75 cpu->isar.id_aa64isar0 = 0x00011120; 76 cpu->isar.id_aa64isar1 = 0; 77 cpu->isar.id_aa64mmfr0 = 0x00101122; 78 cpu->isar.id_aa64mmfr1 = 0; 79 cpu->clidr = 0x0a200023; 80 cpu->dcz_blocksize = 4; 81 82 /* From B2.4 AArch64 Virtual Memory control registers */ 83 cpu->reset_sctlr = 0x00c50838; 84 85 /* From B2.10 AArch64 performance monitor registers */ 86 cpu->isar.reset_pmcr_el0 = 0x410a3000; 87 88 /* From B2.29 Cache ID registers */ 89 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 90 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 91 cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */ 92 93 /* From B3.5 VGIC Type register */ 94 cpu->gic_num_lrs = 4; 95 cpu->gic_vpribits = 5; 96 cpu->gic_vprebits = 5; 97 cpu->gic_pribits = 5; 98 99 /* From C6.4 Debug ID Register */ 100 cpu->isar.dbgdidr = 0x3516d000; 101 /* From C6.5 Debug Device ID Register */ 102 cpu->isar.dbgdevid = 0x00110f13; 103 /* From C6.6 Debug Device ID Register 1 */ 104 cpu->isar.dbgdevid1 = 0x2; 105 106 /* From Cortex-A35 SIMD and Floating-point Support r1p0 */ 107 /* From 3.2 AArch32 register summary */ 108 cpu->reset_fpsid = 0x41034043; 109 110 /* From 2.2 AArch64 register summary */ 111 cpu->isar.mvfr0 = 0x10110222; 112 cpu->isar.mvfr1 = 0x12111111; 113 cpu->isar.mvfr2 = 0x00000043; 114 115 /* These values are the same with A53/A57/A72. */ 116 define_cortex_a72_a57_a53_cp_reginfo(cpu); 117 } 118 119 static void aarch64_a57_initfn(Object *obj) 120 { 121 ARMCPU *cpu = ARM_CPU(obj); 122 123 cpu->dtb_compatible = "arm,cortex-a57"; 124 set_feature(&cpu->env, ARM_FEATURE_V8); 125 set_feature(&cpu->env, ARM_FEATURE_NEON); 126 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 127 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 128 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 129 set_feature(&cpu->env, ARM_FEATURE_EL2); 130 set_feature(&cpu->env, ARM_FEATURE_EL3); 131 set_feature(&cpu->env, ARM_FEATURE_PMU); 132 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 133 cpu->midr = 0x411fd070; 134 cpu->revidr = 0x00000000; 135 cpu->reset_fpsid = 0x41034070; 136 cpu->isar.mvfr0 = 0x10110222; 137 cpu->isar.mvfr1 = 0x12111111; 138 cpu->isar.mvfr2 = 0x00000043; 139 cpu->ctr = 0x8444c004; 140 cpu->reset_sctlr = 0x00c50838; 141 cpu->isar.id_pfr0 = 0x00000131; 142 cpu->isar.id_pfr1 = 0x00011011; 143 cpu->isar.id_dfr0 = 0x03010066; 144 cpu->id_afr0 = 0x00000000; 145 cpu->isar.id_mmfr0 = 0x10101105; 146 cpu->isar.id_mmfr1 = 0x40000000; 147 cpu->isar.id_mmfr2 = 0x01260000; 148 cpu->isar.id_mmfr3 = 0x02102211; 149 cpu->isar.id_isar0 = 0x02101110; 150 cpu->isar.id_isar1 = 0x13112111; 151 cpu->isar.id_isar2 = 0x21232042; 152 cpu->isar.id_isar3 = 0x01112131; 153 cpu->isar.id_isar4 = 0x00011142; 154 cpu->isar.id_isar5 = 0x00011121; 155 cpu->isar.id_isar6 = 0; 156 cpu->isar.id_aa64pfr0 = 0x00002222; 157 cpu->isar.id_aa64dfr0 = 0x10305106; 158 cpu->isar.id_aa64isar0 = 0x00011120; 159 cpu->isar.id_aa64mmfr0 = 0x00001124; 160 cpu->isar.dbgdidr = 0x3516d000; 161 cpu->isar.dbgdevid = 0x01110f13; 162 cpu->isar.dbgdevid1 = 0x2; 163 cpu->isar.reset_pmcr_el0 = 0x41013000; 164 cpu->clidr = 0x0a200023; 165 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 166 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 167 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 168 cpu->dcz_blocksize = 4; /* 64 bytes */ 169 cpu->gic_num_lrs = 4; 170 cpu->gic_vpribits = 5; 171 cpu->gic_vprebits = 5; 172 cpu->gic_pribits = 5; 173 define_cortex_a72_a57_a53_cp_reginfo(cpu); 174 } 175 176 static void aarch64_a53_initfn(Object *obj) 177 { 178 ARMCPU *cpu = ARM_CPU(obj); 179 180 cpu->dtb_compatible = "arm,cortex-a53"; 181 set_feature(&cpu->env, ARM_FEATURE_V8); 182 set_feature(&cpu->env, ARM_FEATURE_NEON); 183 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 184 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 185 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 186 set_feature(&cpu->env, ARM_FEATURE_EL2); 187 set_feature(&cpu->env, ARM_FEATURE_EL3); 188 set_feature(&cpu->env, ARM_FEATURE_PMU); 189 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 190 cpu->midr = 0x410fd034; 191 cpu->revidr = 0x00000000; 192 cpu->reset_fpsid = 0x41034070; 193 cpu->isar.mvfr0 = 0x10110222; 194 cpu->isar.mvfr1 = 0x12111111; 195 cpu->isar.mvfr2 = 0x00000043; 196 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 197 cpu->reset_sctlr = 0x00c50838; 198 cpu->isar.id_pfr0 = 0x00000131; 199 cpu->isar.id_pfr1 = 0x00011011; 200 cpu->isar.id_dfr0 = 0x03010066; 201 cpu->id_afr0 = 0x00000000; 202 cpu->isar.id_mmfr0 = 0x10101105; 203 cpu->isar.id_mmfr1 = 0x40000000; 204 cpu->isar.id_mmfr2 = 0x01260000; 205 cpu->isar.id_mmfr3 = 0x02102211; 206 cpu->isar.id_isar0 = 0x02101110; 207 cpu->isar.id_isar1 = 0x13112111; 208 cpu->isar.id_isar2 = 0x21232042; 209 cpu->isar.id_isar3 = 0x01112131; 210 cpu->isar.id_isar4 = 0x00011142; 211 cpu->isar.id_isar5 = 0x00011121; 212 cpu->isar.id_isar6 = 0; 213 cpu->isar.id_aa64pfr0 = 0x00002222; 214 cpu->isar.id_aa64dfr0 = 0x10305106; 215 cpu->isar.id_aa64isar0 = 0x00011120; 216 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 217 cpu->isar.dbgdidr = 0x3516d000; 218 cpu->isar.dbgdevid = 0x00110f13; 219 cpu->isar.dbgdevid1 = 0x1; 220 cpu->isar.reset_pmcr_el0 = 0x41033000; 221 cpu->clidr = 0x0a200023; 222 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 223 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 224 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 225 cpu->dcz_blocksize = 4; /* 64 bytes */ 226 cpu->gic_num_lrs = 4; 227 cpu->gic_vpribits = 5; 228 cpu->gic_vprebits = 5; 229 cpu->gic_pribits = 5; 230 define_cortex_a72_a57_a53_cp_reginfo(cpu); 231 } 232 233 static void aarch64_a72_initfn(Object *obj) 234 { 235 ARMCPU *cpu = ARM_CPU(obj); 236 237 cpu->dtb_compatible = "arm,cortex-a72"; 238 set_feature(&cpu->env, ARM_FEATURE_V8); 239 set_feature(&cpu->env, ARM_FEATURE_NEON); 240 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 241 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 242 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 243 set_feature(&cpu->env, ARM_FEATURE_EL2); 244 set_feature(&cpu->env, ARM_FEATURE_EL3); 245 set_feature(&cpu->env, ARM_FEATURE_PMU); 246 cpu->midr = 0x410fd083; 247 cpu->revidr = 0x00000000; 248 cpu->reset_fpsid = 0x41034080; 249 cpu->isar.mvfr0 = 0x10110222; 250 cpu->isar.mvfr1 = 0x12111111; 251 cpu->isar.mvfr2 = 0x00000043; 252 cpu->ctr = 0x8444c004; 253 cpu->reset_sctlr = 0x00c50838; 254 cpu->isar.id_pfr0 = 0x00000131; 255 cpu->isar.id_pfr1 = 0x00011011; 256 cpu->isar.id_dfr0 = 0x03010066; 257 cpu->id_afr0 = 0x00000000; 258 cpu->isar.id_mmfr0 = 0x10201105; 259 cpu->isar.id_mmfr1 = 0x40000000; 260 cpu->isar.id_mmfr2 = 0x01260000; 261 cpu->isar.id_mmfr3 = 0x02102211; 262 cpu->isar.id_isar0 = 0x02101110; 263 cpu->isar.id_isar1 = 0x13112111; 264 cpu->isar.id_isar2 = 0x21232042; 265 cpu->isar.id_isar3 = 0x01112131; 266 cpu->isar.id_isar4 = 0x00011142; 267 cpu->isar.id_isar5 = 0x00011121; 268 cpu->isar.id_aa64pfr0 = 0x00002222; 269 cpu->isar.id_aa64dfr0 = 0x10305106; 270 cpu->isar.id_aa64isar0 = 0x00011120; 271 cpu->isar.id_aa64mmfr0 = 0x00001124; 272 cpu->isar.dbgdidr = 0x3516d000; 273 cpu->isar.dbgdevid = 0x01110f13; 274 cpu->isar.dbgdevid1 = 0x2; 275 cpu->isar.reset_pmcr_el0 = 0x41023000; 276 cpu->clidr = 0x0a200023; 277 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 278 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 279 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ 280 cpu->dcz_blocksize = 4; /* 64 bytes */ 281 cpu->gic_num_lrs = 4; 282 cpu->gic_vpribits = 5; 283 cpu->gic_vprebits = 5; 284 cpu->gic_pribits = 5; 285 define_cortex_a72_a57_a53_cp_reginfo(cpu); 286 } 287 288 static void aarch64_a76_initfn(Object *obj) 289 { 290 ARMCPU *cpu = ARM_CPU(obj); 291 292 cpu->dtb_compatible = "arm,cortex-a76"; 293 set_feature(&cpu->env, ARM_FEATURE_V8); 294 set_feature(&cpu->env, ARM_FEATURE_NEON); 295 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 296 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 297 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 298 set_feature(&cpu->env, ARM_FEATURE_EL2); 299 set_feature(&cpu->env, ARM_FEATURE_EL3); 300 set_feature(&cpu->env, ARM_FEATURE_PMU); 301 302 /* Ordered by B2.4 AArch64 registers by functional group */ 303 cpu->clidr = 0x82000023; 304 cpu->ctr = 0x8444C004; 305 cpu->dcz_blocksize = 4; 306 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; 307 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 308 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 309 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; 310 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 311 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 312 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 313 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; 314 cpu->id_afr0 = 0x00000000; 315 cpu->isar.id_dfr0 = 0x04010088; 316 cpu->isar.id_isar0 = 0x02101110; 317 cpu->isar.id_isar1 = 0x13112111; 318 cpu->isar.id_isar2 = 0x21232042; 319 cpu->isar.id_isar3 = 0x01112131; 320 cpu->isar.id_isar4 = 0x00010142; 321 cpu->isar.id_isar5 = 0x01011121; 322 cpu->isar.id_isar6 = 0x00000010; 323 cpu->isar.id_mmfr0 = 0x10201105; 324 cpu->isar.id_mmfr1 = 0x40000000; 325 cpu->isar.id_mmfr2 = 0x01260000; 326 cpu->isar.id_mmfr3 = 0x02122211; 327 cpu->isar.id_mmfr4 = 0x00021110; 328 cpu->isar.id_pfr0 = 0x10010131; 329 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 330 cpu->isar.id_pfr2 = 0x00000011; 331 cpu->midr = 0x414fd0b1; /* r4p1 */ 332 cpu->revidr = 0; 333 334 /* From B2.18 CCSIDR_EL1 */ 335 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 336 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 337 cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ 338 339 /* From B2.93 SCTLR_EL3 */ 340 cpu->reset_sctlr = 0x30c50838; 341 342 /* From B4.23 ICH_VTR_EL2 */ 343 cpu->gic_num_lrs = 4; 344 cpu->gic_vpribits = 5; 345 cpu->gic_vprebits = 5; 346 cpu->gic_pribits = 5; 347 348 /* From B5.1 AdvSIMD AArch64 register summary */ 349 cpu->isar.mvfr0 = 0x10110222; 350 cpu->isar.mvfr1 = 0x13211111; 351 cpu->isar.mvfr2 = 0x00000043; 352 353 /* From D5.1 AArch64 PMU register summary */ 354 cpu->isar.reset_pmcr_el0 = 0x410b3000; 355 } 356 357 static void aarch64_neoverse_n1_initfn(Object *obj) 358 { 359 ARMCPU *cpu = ARM_CPU(obj); 360 361 cpu->dtb_compatible = "arm,neoverse-n1"; 362 set_feature(&cpu->env, ARM_FEATURE_V8); 363 set_feature(&cpu->env, ARM_FEATURE_NEON); 364 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 365 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 366 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 367 set_feature(&cpu->env, ARM_FEATURE_EL2); 368 set_feature(&cpu->env, ARM_FEATURE_EL3); 369 set_feature(&cpu->env, ARM_FEATURE_PMU); 370 371 /* Ordered by B2.4 AArch64 registers by functional group */ 372 cpu->clidr = 0x82000023; 373 cpu->ctr = 0x8444c004; 374 cpu->dcz_blocksize = 4; 375 cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; 376 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 377 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 378 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; 379 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 380 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 381 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 382 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; 383 cpu->id_afr0 = 0x00000000; 384 cpu->isar.id_dfr0 = 0x04010088; 385 cpu->isar.id_isar0 = 0x02101110; 386 cpu->isar.id_isar1 = 0x13112111; 387 cpu->isar.id_isar2 = 0x21232042; 388 cpu->isar.id_isar3 = 0x01112131; 389 cpu->isar.id_isar4 = 0x00010142; 390 cpu->isar.id_isar5 = 0x01011121; 391 cpu->isar.id_isar6 = 0x00000010; 392 cpu->isar.id_mmfr0 = 0x10201105; 393 cpu->isar.id_mmfr1 = 0x40000000; 394 cpu->isar.id_mmfr2 = 0x01260000; 395 cpu->isar.id_mmfr3 = 0x02122211; 396 cpu->isar.id_mmfr4 = 0x00021110; 397 cpu->isar.id_pfr0 = 0x10010131; 398 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 399 cpu->isar.id_pfr2 = 0x00000011; 400 cpu->midr = 0x414fd0c1; /* r4p1 */ 401 cpu->revidr = 0; 402 403 /* From B2.23 CCSIDR_EL1 */ 404 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 405 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 406 cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ 407 408 /* From B2.98 SCTLR_EL3 */ 409 cpu->reset_sctlr = 0x30c50838; 410 411 /* From B4.23 ICH_VTR_EL2 */ 412 cpu->gic_num_lrs = 4; 413 cpu->gic_vpribits = 5; 414 cpu->gic_vprebits = 5; 415 cpu->gic_pribits = 5; 416 417 /* From B5.1 AdvSIMD AArch64 register summary */ 418 cpu->isar.mvfr0 = 0x10110222; 419 cpu->isar.mvfr1 = 0x13211111; 420 cpu->isar.mvfr2 = 0x00000043; 421 422 /* From D5.1 AArch64 PMU register summary */ 423 cpu->isar.reset_pmcr_el0 = 0x410c3000; 424 } 425 426 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) 427 { 428 /* 429 * If any vector lengths are explicitly enabled with sve<N> properties, 430 * then all other lengths are implicitly disabled. If sve-max-vq is 431 * specified then it is the same as explicitly enabling all lengths 432 * up to and including the specified maximum, which means all larger 433 * lengths will be implicitly disabled. If no sve<N> properties 434 * are enabled and sve-max-vq is not specified, then all lengths not 435 * explicitly disabled will be enabled. Additionally, all power-of-two 436 * vector lengths less than the maximum enabled length will be 437 * automatically enabled and all vector lengths larger than the largest 438 * disabled power-of-two vector length will be automatically disabled. 439 * Errors are generated if the user provided input that interferes with 440 * any of the above. Finally, if SVE is not disabled, then at least one 441 * vector length must be enabled. 442 */ 443 uint32_t vq_map = cpu->sve_vq.map; 444 uint32_t vq_init = cpu->sve_vq.init; 445 uint32_t vq_supported; 446 uint32_t vq_mask = 0; 447 uint32_t tmp, vq, max_vq = 0; 448 449 /* 450 * CPU models specify a set of supported vector lengths which are 451 * enabled by default. Attempting to enable any vector length not set 452 * in the supported bitmap results in an error. When KVM is enabled we 453 * fetch the supported bitmap from the host. 454 */ 455 if (kvm_enabled()) { 456 if (kvm_arm_sve_supported()) { 457 cpu->sve_vq.supported = kvm_arm_sve_get_vls(CPU(cpu)); 458 vq_supported = cpu->sve_vq.supported; 459 } else { 460 assert(!cpu_isar_feature(aa64_sve, cpu)); 461 vq_supported = 0; 462 } 463 } else { 464 vq_supported = cpu->sve_vq.supported; 465 } 466 467 /* 468 * Process explicit sve<N> properties. 469 * From the properties, sve_vq_map<N> implies sve_vq_init<N>. 470 * Check first for any sve<N> enabled. 471 */ 472 if (vq_map != 0) { 473 max_vq = 32 - clz32(vq_map); 474 vq_mask = MAKE_64BIT_MASK(0, max_vq); 475 476 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { 477 error_setg(errp, "cannot enable sve%d", max_vq * 128); 478 error_append_hint(errp, "sve%d is larger than the maximum vector " 479 "length, sve-max-vq=%d (%d bits)\n", 480 max_vq * 128, cpu->sve_max_vq, 481 cpu->sve_max_vq * 128); 482 return; 483 } 484 485 if (kvm_enabled()) { 486 /* 487 * For KVM we have to automatically enable all supported unitialized 488 * lengths, even when the smaller lengths are not all powers-of-two. 489 */ 490 vq_map |= vq_supported & ~vq_init & vq_mask; 491 } else { 492 /* Propagate enabled bits down through required powers-of-two. */ 493 vq_map |= SVE_VQ_POW2_MAP & ~vq_init & vq_mask; 494 } 495 } else if (cpu->sve_max_vq == 0) { 496 /* 497 * No explicit bits enabled, and no implicit bits from sve-max-vq. 498 */ 499 if (!cpu_isar_feature(aa64_sve, cpu)) { 500 /* SVE is disabled and so are all vector lengths. Good. */ 501 return; 502 } 503 504 if (kvm_enabled()) { 505 /* Disabling a supported length disables all larger lengths. */ 506 tmp = vq_init & vq_supported; 507 } else { 508 /* Disabling a power-of-two disables all larger lengths. */ 509 tmp = vq_init & SVE_VQ_POW2_MAP; 510 } 511 vq = ctz32(tmp) + 1; 512 513 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 514 vq_mask = MAKE_64BIT_MASK(0, max_vq); 515 vq_map = vq_supported & ~vq_init & vq_mask; 516 517 if (max_vq == 0 || vq_map == 0) { 518 error_setg(errp, "cannot disable sve%d", vq * 128); 519 error_append_hint(errp, "Disabling sve%d results in all " 520 "vector lengths being disabled.\n", 521 vq * 128); 522 error_append_hint(errp, "With SVE enabled, at least one " 523 "vector length must be enabled.\n"); 524 return; 525 } 526 527 max_vq = 32 - clz32(vq_map); 528 vq_mask = MAKE_64BIT_MASK(0, max_vq); 529 } 530 531 /* 532 * Process the sve-max-vq property. 533 * Note that we know from the above that no bit above 534 * sve-max-vq is currently set. 535 */ 536 if (cpu->sve_max_vq != 0) { 537 max_vq = cpu->sve_max_vq; 538 vq_mask = MAKE_64BIT_MASK(0, max_vq); 539 540 if (vq_init & ~vq_map & (1 << (max_vq - 1))) { 541 error_setg(errp, "cannot disable sve%d", max_vq * 128); 542 error_append_hint(errp, "The maximum vector length must be " 543 "enabled, sve-max-vq=%d (%d bits)\n", 544 max_vq, max_vq * 128); 545 return; 546 } 547 548 /* Set all bits not explicitly set within sve-max-vq. */ 549 vq_map |= ~vq_init & vq_mask; 550 } 551 552 /* 553 * We should know what max-vq is now. Also, as we're done 554 * manipulating sve-vq-map, we ensure any bits above max-vq 555 * are clear, just in case anybody looks. 556 */ 557 assert(max_vq != 0); 558 assert(vq_mask != 0); 559 vq_map &= vq_mask; 560 561 /* Ensure the set of lengths matches what is supported. */ 562 tmp = vq_map ^ (vq_supported & vq_mask); 563 if (tmp) { 564 vq = 32 - clz32(tmp); 565 if (vq_map & (1 << (vq - 1))) { 566 if (cpu->sve_max_vq) { 567 error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq); 568 error_append_hint(errp, "This CPU does not support " 569 "the vector length %d-bits.\n", vq * 128); 570 error_append_hint(errp, "It may not be possible to use " 571 "sve-max-vq with this CPU. Try " 572 "using only sve<N> properties.\n"); 573 } else { 574 error_setg(errp, "cannot enable sve%d", vq * 128); 575 if (vq_supported) { 576 error_append_hint(errp, "This CPU does not support " 577 "the vector length %d-bits.\n", vq * 128); 578 } else { 579 error_append_hint(errp, "SVE not supported by KVM " 580 "on this host\n"); 581 } 582 } 583 return; 584 } else { 585 if (kvm_enabled()) { 586 error_setg(errp, "cannot disable sve%d", vq * 128); 587 error_append_hint(errp, "The KVM host requires all " 588 "supported vector lengths smaller " 589 "than %d bits to also be enabled.\n", 590 max_vq * 128); 591 return; 592 } else { 593 /* Ensure all required powers-of-two are enabled. */ 594 tmp = SVE_VQ_POW2_MAP & vq_mask & ~vq_map; 595 if (tmp) { 596 vq = 32 - clz32(tmp); 597 error_setg(errp, "cannot disable sve%d", vq * 128); 598 error_append_hint(errp, "sve%d is required as it " 599 "is a power-of-two length smaller " 600 "than the maximum, sve%d\n", 601 vq * 128, max_vq * 128); 602 return; 603 } 604 } 605 } 606 } 607 608 /* 609 * Now that we validated all our vector lengths, the only question 610 * left to answer is if we even want SVE at all. 611 */ 612 if (!cpu_isar_feature(aa64_sve, cpu)) { 613 error_setg(errp, "cannot enable sve%d", max_vq * 128); 614 error_append_hint(errp, "SVE must be enabled to enable vector " 615 "lengths.\n"); 616 error_append_hint(errp, "Add sve=on to the CPU property list.\n"); 617 return; 618 } 619 620 /* From now on sve_max_vq is the actual maximum supported length. */ 621 cpu->sve_max_vq = max_vq; 622 cpu->sve_vq.map = vq_map; 623 } 624 625 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, 626 void *opaque, Error **errp) 627 { 628 ARMCPU *cpu = ARM_CPU(obj); 629 uint32_t value; 630 631 /* All vector lengths are disabled when SVE is off. */ 632 if (!cpu_isar_feature(aa64_sve, cpu)) { 633 value = 0; 634 } else { 635 value = cpu->sve_max_vq; 636 } 637 visit_type_uint32(v, name, &value, errp); 638 } 639 640 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, 641 void *opaque, Error **errp) 642 { 643 ARMCPU *cpu = ARM_CPU(obj); 644 uint32_t max_vq; 645 646 if (!visit_type_uint32(v, name, &max_vq, errp)) { 647 return; 648 } 649 650 if (kvm_enabled() && !kvm_arm_sve_supported()) { 651 error_setg(errp, "cannot set sve-max-vq"); 652 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 653 return; 654 } 655 656 if (max_vq == 0 || max_vq > ARM_MAX_VQ) { 657 error_setg(errp, "unsupported SVE vector length"); 658 error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", 659 ARM_MAX_VQ); 660 return; 661 } 662 663 cpu->sve_max_vq = max_vq; 664 } 665 666 /* 667 * Note that cpu_arm_{get,set}_vq cannot use the simpler 668 * object_property_add_bool interface because they make use of the 669 * contents of "name" to determine which bit on which to operate. 670 */ 671 static void cpu_arm_get_vq(Object *obj, Visitor *v, const char *name, 672 void *opaque, Error **errp) 673 { 674 ARMCPU *cpu = ARM_CPU(obj); 675 ARMVQMap *vq_map = opaque; 676 uint32_t vq = atoi(&name[3]) / 128; 677 bool sve = vq_map == &cpu->sve_vq; 678 bool value; 679 680 /* All vector lengths are disabled when feature is off. */ 681 if (sve 682 ? !cpu_isar_feature(aa64_sve, cpu) 683 : !cpu_isar_feature(aa64_sme, cpu)) { 684 value = false; 685 } else { 686 value = extract32(vq_map->map, vq - 1, 1); 687 } 688 visit_type_bool(v, name, &value, errp); 689 } 690 691 static void cpu_arm_set_vq(Object *obj, Visitor *v, const char *name, 692 void *opaque, Error **errp) 693 { 694 ARMVQMap *vq_map = opaque; 695 uint32_t vq = atoi(&name[3]) / 128; 696 bool value; 697 698 if (!visit_type_bool(v, name, &value, errp)) { 699 return; 700 } 701 702 vq_map->map = deposit32(vq_map->map, vq - 1, 1, value); 703 vq_map->init |= 1 << (vq - 1); 704 } 705 706 static bool cpu_arm_get_sve(Object *obj, Error **errp) 707 { 708 ARMCPU *cpu = ARM_CPU(obj); 709 return cpu_isar_feature(aa64_sve, cpu); 710 } 711 712 static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) 713 { 714 ARMCPU *cpu = ARM_CPU(obj); 715 uint64_t t; 716 717 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 718 error_setg(errp, "'sve' feature not supported by KVM on this host"); 719 return; 720 } 721 722 t = cpu->isar.id_aa64pfr0; 723 t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); 724 cpu->isar.id_aa64pfr0 = t; 725 } 726 727 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) 728 { 729 uint32_t vq_map = cpu->sme_vq.map; 730 uint32_t vq_init = cpu->sme_vq.init; 731 uint32_t vq_supported = cpu->sme_vq.supported; 732 uint32_t vq; 733 734 if (vq_map == 0) { 735 if (!cpu_isar_feature(aa64_sme, cpu)) { 736 cpu->isar.id_aa64smfr0 = 0; 737 return; 738 } 739 740 /* TODO: KVM will require limitations via SMCR_EL2. */ 741 vq_map = vq_supported & ~vq_init; 742 743 if (vq_map == 0) { 744 vq = ctz32(vq_supported) + 1; 745 error_setg(errp, "cannot disable sme%d", vq * 128); 746 error_append_hint(errp, "All SME vector lengths are disabled.\n"); 747 error_append_hint(errp, "With SME enabled, at least one " 748 "vector length must be enabled.\n"); 749 return; 750 } 751 } else { 752 if (!cpu_isar_feature(aa64_sme, cpu)) { 753 vq = 32 - clz32(vq_map); 754 error_setg(errp, "cannot enable sme%d", vq * 128); 755 error_append_hint(errp, "SME must be enabled to enable " 756 "vector lengths.\n"); 757 error_append_hint(errp, "Add sme=on to the CPU property list.\n"); 758 return; 759 } 760 /* TODO: KVM will require limitations via SMCR_EL2. */ 761 } 762 763 cpu->sme_vq.map = vq_map; 764 } 765 766 static bool cpu_arm_get_sme(Object *obj, Error **errp) 767 { 768 ARMCPU *cpu = ARM_CPU(obj); 769 return cpu_isar_feature(aa64_sme, cpu); 770 } 771 772 static void cpu_arm_set_sme(Object *obj, bool value, Error **errp) 773 { 774 ARMCPU *cpu = ARM_CPU(obj); 775 uint64_t t; 776 777 t = cpu->isar.id_aa64pfr1; 778 t = FIELD_DP64(t, ID_AA64PFR1, SME, value); 779 cpu->isar.id_aa64pfr1 = t; 780 } 781 782 static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp) 783 { 784 ARMCPU *cpu = ARM_CPU(obj); 785 return cpu_isar_feature(aa64_sme, cpu) && 786 cpu_isar_feature(aa64_sme_fa64, cpu); 787 } 788 789 static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp) 790 { 791 ARMCPU *cpu = ARM_CPU(obj); 792 uint64_t t; 793 794 t = cpu->isar.id_aa64smfr0; 795 t = FIELD_DP64(t, ID_AA64SMFR0, FA64, value); 796 cpu->isar.id_aa64smfr0 = t; 797 } 798 799 #ifdef CONFIG_USER_ONLY 800 /* Mirror linux /proc/sys/abi/{sve,sme}_default_vector_length. */ 801 static void cpu_arm_set_default_vec_len(Object *obj, Visitor *v, 802 const char *name, void *opaque, 803 Error **errp) 804 { 805 uint32_t *ptr_default_vq = opaque; 806 int32_t default_len, default_vq, remainder; 807 808 if (!visit_type_int32(v, name, &default_len, errp)) { 809 return; 810 } 811 812 /* Undocumented, but the kernel allows -1 to indicate "maximum". */ 813 if (default_len == -1) { 814 *ptr_default_vq = ARM_MAX_VQ; 815 return; 816 } 817 818 default_vq = default_len / 16; 819 remainder = default_len % 16; 820 821 /* 822 * Note that the 512 max comes from include/uapi/asm/sve_context.h 823 * and is the maximum architectural width of ZCR_ELx.LEN. 824 */ 825 if (remainder || default_vq < 1 || default_vq > 512) { 826 ARMCPU *cpu = ARM_CPU(obj); 827 const char *which = 828 (ptr_default_vq == &cpu->sve_default_vq ? "sve" : "sme"); 829 830 error_setg(errp, "cannot set %s-default-vector-length", which); 831 if (remainder) { 832 error_append_hint(errp, "Vector length not a multiple of 16\n"); 833 } else if (default_vq < 1) { 834 error_append_hint(errp, "Vector length smaller than 16\n"); 835 } else { 836 error_append_hint(errp, "Vector length larger than %d\n", 837 512 * 16); 838 } 839 return; 840 } 841 842 *ptr_default_vq = default_vq; 843 } 844 845 static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v, 846 const char *name, void *opaque, 847 Error **errp) 848 { 849 uint32_t *ptr_default_vq = opaque; 850 int32_t value = *ptr_default_vq * 16; 851 852 visit_type_int32(v, name, &value, errp); 853 } 854 #endif 855 856 static void aarch64_add_sve_properties(Object *obj) 857 { 858 ARMCPU *cpu = ARM_CPU(obj); 859 uint32_t vq; 860 861 object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); 862 863 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 864 char name[8]; 865 sprintf(name, "sve%d", vq * 128); 866 object_property_add(obj, name, "bool", cpu_arm_get_vq, 867 cpu_arm_set_vq, NULL, &cpu->sve_vq); 868 } 869 870 #ifdef CONFIG_USER_ONLY 871 /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ 872 object_property_add(obj, "sve-default-vector-length", "int32", 873 cpu_arm_get_default_vec_len, 874 cpu_arm_set_default_vec_len, NULL, 875 &cpu->sve_default_vq); 876 #endif 877 } 878 879 static void aarch64_add_sme_properties(Object *obj) 880 { 881 ARMCPU *cpu = ARM_CPU(obj); 882 uint32_t vq; 883 884 object_property_add_bool(obj, "sme", cpu_arm_get_sme, cpu_arm_set_sme); 885 object_property_add_bool(obj, "sme_fa64", cpu_arm_get_sme_fa64, 886 cpu_arm_set_sme_fa64); 887 888 for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) { 889 char name[8]; 890 sprintf(name, "sme%d", vq * 128); 891 object_property_add(obj, name, "bool", cpu_arm_get_vq, 892 cpu_arm_set_vq, NULL, &cpu->sme_vq); 893 } 894 895 #ifdef CONFIG_USER_ONLY 896 /* Mirror linux /proc/sys/abi/sme_default_vector_length. */ 897 object_property_add(obj, "sme-default-vector-length", "int32", 898 cpu_arm_get_default_vec_len, 899 cpu_arm_set_default_vec_len, NULL, 900 &cpu->sme_default_vq); 901 #endif 902 } 903 904 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) 905 { 906 int arch_val = 0, impdef_val = 0; 907 uint64_t t; 908 909 /* Exit early if PAuth is enabled, and fall through to disable it */ 910 if ((kvm_enabled() || hvf_enabled()) && cpu->prop_pauth) { 911 if (!cpu_isar_feature(aa64_pauth, cpu)) { 912 error_setg(errp, "'pauth' feature not supported by %s on this host", 913 kvm_enabled() ? "KVM" : "hvf"); 914 } 915 916 return; 917 } 918 919 /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ 920 if (cpu->prop_pauth) { 921 if (cpu->prop_pauth_impdef) { 922 impdef_val = 1; 923 } else { 924 arch_val = 1; 925 } 926 } else if (cpu->prop_pauth_impdef) { 927 error_setg(errp, "cannot enable pauth-impdef without pauth"); 928 error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); 929 } 930 931 t = cpu->isar.id_aa64isar1; 932 t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); 933 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); 934 t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); 935 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); 936 cpu->isar.id_aa64isar1 = t; 937 } 938 939 static Property arm_cpu_pauth_property = 940 DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); 941 static Property arm_cpu_pauth_impdef_property = 942 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); 943 944 static void aarch64_add_pauth_properties(Object *obj) 945 { 946 ARMCPU *cpu = ARM_CPU(obj); 947 948 /* Default to PAUTH on, with the architected algorithm on TCG. */ 949 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); 950 if (kvm_enabled() || hvf_enabled()) { 951 /* 952 * Mirror PAuth support from the probed sysregs back into the 953 * property for KVM or hvf. Is it just a bit backward? Yes it is! 954 * Note that prop_pauth is true whether the host CPU supports the 955 * architected QARMA5 algorithm or the IMPDEF one. We don't 956 * provide the separate pauth-impdef property for KVM or hvf, 957 * only for TCG. 958 */ 959 cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); 960 } else { 961 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); 962 } 963 } 964 965 static Property arm_cpu_lpa2_property = 966 DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); 967 968 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) 969 { 970 uint64_t t; 971 972 /* 973 * We only install the property for tcg -cpu max; this is the 974 * only situation in which the cpu field can be true. 975 */ 976 if (!cpu->prop_lpa2) { 977 return; 978 } 979 980 t = cpu->isar.id_aa64mmfr0; 981 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */ 982 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */ 983 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */ 984 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */ 985 cpu->isar.id_aa64mmfr0 = t; 986 } 987 988 static void aarch64_host_initfn(Object *obj) 989 { 990 #if defined(CONFIG_KVM) 991 ARMCPU *cpu = ARM_CPU(obj); 992 kvm_arm_set_cpu_features_from_host(cpu); 993 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 994 aarch64_add_sve_properties(obj); 995 aarch64_add_pauth_properties(obj); 996 } 997 #elif defined(CONFIG_HVF) 998 ARMCPU *cpu = ARM_CPU(obj); 999 hvf_arm_set_cpu_features_from_host(cpu); 1000 aarch64_add_pauth_properties(obj); 1001 #else 1002 g_assert_not_reached(); 1003 #endif 1004 } 1005 1006 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 1007 * otherwise, a CPU with as many features enabled as our emulation supports. 1008 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; 1009 * this only needs to handle 64 bits. 1010 */ 1011 static void aarch64_max_initfn(Object *obj) 1012 { 1013 ARMCPU *cpu = ARM_CPU(obj); 1014 uint64_t t; 1015 uint32_t u; 1016 1017 if (kvm_enabled() || hvf_enabled()) { 1018 /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ 1019 aarch64_host_initfn(obj); 1020 return; 1021 } 1022 1023 /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */ 1024 1025 aarch64_a57_initfn(obj); 1026 1027 /* 1028 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real 1029 * one and try to apply errata workarounds or use impdef features we 1030 * don't provide. 1031 * An IMPLEMENTER field of 0 means "reserved for software use"; 1032 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers 1033 * to see which features are present"; 1034 * the VARIANT, PARTNUM and REVISION fields are all implementation 1035 * defined and we choose to define PARTNUM just in case guest 1036 * code needs to distinguish this QEMU CPU from other software 1037 * implementations, though this shouldn't be needed. 1038 */ 1039 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); 1040 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); 1041 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); 1042 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); 1043 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); 1044 cpu->midr = t; 1045 1046 /* 1047 * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS} 1048 * are zero. 1049 */ 1050 u = cpu->clidr; 1051 u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); 1052 u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0); 1053 cpu->clidr = u; 1054 1055 t = cpu->isar.id_aa64isar0; 1056 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ 1057 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ 1058 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ 1059 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); 1060 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ 1061 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ 1062 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ 1063 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ 1064 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ 1065 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ 1066 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ 1067 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ 1068 t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ 1069 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ 1070 cpu->isar.id_aa64isar0 = t; 1071 1072 t = cpu->isar.id_aa64isar1; 1073 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ 1074 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ 1075 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ 1076 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ 1077 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ 1078 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ 1079 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ 1080 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ 1081 t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ 1082 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ 1083 cpu->isar.id_aa64isar1 = t; 1084 1085 t = cpu->isar.id_aa64pfr0; 1086 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ 1087 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ 1088 t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */ 1089 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); 1090 t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ 1091 t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ 1092 t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ 1093 t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ 1094 cpu->isar.id_aa64pfr0 = t; 1095 1096 t = cpu->isar.id_aa64pfr1; 1097 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ 1098 t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ 1099 /* 1100 * Begin with full support for MTE. This will be downgraded to MTE=0 1101 * during realize if the board provides no tag memory, much like 1102 * we do for EL2 with the virtualization=on property. 1103 */ 1104 t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ 1105 t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ 1106 t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ 1107 t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ 1108 cpu->isar.id_aa64pfr1 = t; 1109 1110 t = cpu->isar.id_aa64mmfr0; 1111 t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ 1112 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ 1113 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ 1114 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ 1115 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ 1116 cpu->isar.id_aa64mmfr0 = t; 1117 1118 t = cpu->isar.id_aa64mmfr1; 1119 t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ 1120 t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ 1121 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ 1122 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ 1123 t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ 1124 t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ 1125 t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ 1126 t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ 1127 cpu->isar.id_aa64mmfr1 = t; 1128 1129 t = cpu->isar.id_aa64mmfr2; 1130 t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ 1131 t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ 1132 t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ 1133 t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ 1134 t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ 1135 t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ 1136 t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ 1137 t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ 1138 t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ 1139 cpu->isar.id_aa64mmfr2 = t; 1140 1141 t = cpu->isar.id_aa64zfr0; 1142 t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); 1143 t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ 1144 t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ 1145 t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ 1146 t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ 1147 t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ 1148 t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ 1149 t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ 1150 t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ 1151 cpu->isar.id_aa64zfr0 = t; 1152 1153 t = cpu->isar.id_aa64dfr0; 1154 t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ 1155 t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ 1156 cpu->isar.id_aa64dfr0 = t; 1157 1158 t = cpu->isar.id_aa64smfr0; 1159 t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ 1160 t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ 1161 t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ 1162 t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ 1163 t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ 1164 t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ 1165 t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ 1166 cpu->isar.id_aa64smfr0 = t; 1167 1168 /* Replicate the same data to the 32-bit id registers. */ 1169 aa32_max_features(cpu); 1170 1171 #ifdef CONFIG_USER_ONLY 1172 /* 1173 * For usermode -cpu max we can use a larger and more efficient DCZ 1174 * blocksize since we don't have to follow what the hardware does. 1175 */ 1176 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 1177 cpu->dcz_blocksize = 7; /* 512 bytes */ 1178 #endif 1179 1180 cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); 1181 cpu->sme_vq.supported = SVE_VQ_POW2_MAP; 1182 1183 aarch64_add_pauth_properties(obj); 1184 aarch64_add_sve_properties(obj); 1185 aarch64_add_sme_properties(obj); 1186 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, 1187 cpu_max_set_sve_max_vq, NULL, NULL); 1188 qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); 1189 } 1190 1191 static void aarch64_a64fx_initfn(Object *obj) 1192 { 1193 ARMCPU *cpu = ARM_CPU(obj); 1194 1195 cpu->dtb_compatible = "arm,a64fx"; 1196 set_feature(&cpu->env, ARM_FEATURE_V8); 1197 set_feature(&cpu->env, ARM_FEATURE_NEON); 1198 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1199 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 1200 set_feature(&cpu->env, ARM_FEATURE_EL2); 1201 set_feature(&cpu->env, ARM_FEATURE_EL3); 1202 set_feature(&cpu->env, ARM_FEATURE_PMU); 1203 cpu->midr = 0x461f0010; 1204 cpu->revidr = 0x00000000; 1205 cpu->ctr = 0x86668006; 1206 cpu->reset_sctlr = 0x30000180; 1207 cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */ 1208 cpu->isar.id_aa64pfr1 = 0x0000000000000000; 1209 cpu->isar.id_aa64dfr0 = 0x0000000010305408; 1210 cpu->isar.id_aa64dfr1 = 0x0000000000000000; 1211 cpu->id_aa64afr0 = 0x0000000000000000; 1212 cpu->id_aa64afr1 = 0x0000000000000000; 1213 cpu->isar.id_aa64mmfr0 = 0x0000000000001122; 1214 cpu->isar.id_aa64mmfr1 = 0x0000000011212100; 1215 cpu->isar.id_aa64mmfr2 = 0x0000000000001011; 1216 cpu->isar.id_aa64isar0 = 0x0000000010211120; 1217 cpu->isar.id_aa64isar1 = 0x0000000000010001; 1218 cpu->isar.id_aa64zfr0 = 0x0000000000000000; 1219 cpu->clidr = 0x0000000080000023; 1220 cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */ 1221 cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */ 1222 cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */ 1223 cpu->dcz_blocksize = 6; /* 256 bytes */ 1224 cpu->gic_num_lrs = 4; 1225 cpu->gic_vpribits = 5; 1226 cpu->gic_vprebits = 5; 1227 cpu->gic_pribits = 5; 1228 1229 /* The A64FX supports only 128, 256 and 512 bit vector lengths */ 1230 aarch64_add_sve_properties(obj); 1231 cpu->sve_vq.supported = (1 << 0) /* 128bit */ 1232 | (1 << 1) /* 256bit */ 1233 | (1 << 3); /* 512bit */ 1234 1235 cpu->isar.reset_pmcr_el0 = 0x46014040; 1236 1237 /* TODO: Add A64FX specific HPC extension registers */ 1238 } 1239 1240 static const ARMCPUInfo aarch64_cpus[] = { 1241 { .name = "cortex-a35", .initfn = aarch64_a35_initfn }, 1242 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 1243 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 1244 { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, 1245 { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, 1246 { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, 1247 { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, 1248 { .name = "max", .initfn = aarch64_max_initfn }, 1249 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1250 { .name = "host", .initfn = aarch64_host_initfn }, 1251 #endif 1252 }; 1253 1254 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 1255 { 1256 ARMCPU *cpu = ARM_CPU(obj); 1257 1258 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 1259 } 1260 1261 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 1262 { 1263 ARMCPU *cpu = ARM_CPU(obj); 1264 1265 /* At this time, this property is only allowed if KVM is enabled. This 1266 * restriction allows us to avoid fixing up functionality that assumes a 1267 * uniform execution state like do_interrupt. 1268 */ 1269 if (value == false) { 1270 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 1271 error_setg(errp, "'aarch64' feature cannot be disabled " 1272 "unless KVM is enabled and 32-bit EL1 " 1273 "is supported"); 1274 return; 1275 } 1276 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 1277 } else { 1278 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 1279 } 1280 } 1281 1282 static void aarch64_cpu_finalizefn(Object *obj) 1283 { 1284 } 1285 1286 static gchar *aarch64_gdb_arch_name(CPUState *cs) 1287 { 1288 return g_strdup("aarch64"); 1289 } 1290 1291 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 1292 { 1293 CPUClass *cc = CPU_CLASS(oc); 1294 1295 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 1296 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 1297 cc->gdb_num_core_regs = 34; 1298 cc->gdb_core_xml_file = "aarch64-core.xml"; 1299 cc->gdb_arch_name = aarch64_gdb_arch_name; 1300 1301 object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, 1302 aarch64_cpu_set_aarch64); 1303 object_class_property_set_description(oc, "aarch64", 1304 "Set on/off to enable/disable aarch64 " 1305 "execution state "); 1306 } 1307 1308 static void aarch64_cpu_instance_init(Object *obj) 1309 { 1310 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 1311 1312 acc->info->initfn(obj); 1313 arm_cpu_post_init(obj); 1314 } 1315 1316 static void cpu_register_class_init(ObjectClass *oc, void *data) 1317 { 1318 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1319 1320 acc->info = data; 1321 } 1322 1323 void aarch64_cpu_register(const ARMCPUInfo *info) 1324 { 1325 TypeInfo type_info = { 1326 .parent = TYPE_AARCH64_CPU, 1327 .instance_size = sizeof(ARMCPU), 1328 .instance_init = aarch64_cpu_instance_init, 1329 .class_size = sizeof(ARMCPUClass), 1330 .class_init = info->class_init ?: cpu_register_class_init, 1331 .class_data = (void *)info, 1332 }; 1333 1334 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1335 type_register(&type_info); 1336 g_free((void *)type_info.name); 1337 } 1338 1339 static const TypeInfo aarch64_cpu_type_info = { 1340 .name = TYPE_AARCH64_CPU, 1341 .parent = TYPE_ARM_CPU, 1342 .instance_size = sizeof(ARMCPU), 1343 .instance_finalize = aarch64_cpu_finalizefn, 1344 .abstract = true, 1345 .class_size = sizeof(AArch64CPUClass), 1346 .class_init = aarch64_cpu_class_init, 1347 }; 1348 1349 static void aarch64_cpu_register_types(void) 1350 { 1351 size_t i; 1352 1353 type_register_static(&aarch64_cpu_type_info); 1354 1355 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { 1356 aarch64_cpu_register(&aarch64_cpus[i]); 1357 } 1358 } 1359 1360 type_init(aarch64_cpu_register_types) 1361