1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "qemu-common.h" 25 #if !defined(CONFIG_USER_ONLY) 26 #include "hw/loader.h" 27 #endif 28 #include "hw/arm/arm.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 32 static inline void set_feature(CPUARMState *env, int feature) 33 { 34 env->features |= 1ULL << feature; 35 } 36 37 static inline void unset_feature(CPUARMState *env, int feature) 38 { 39 env->features &= ~(1ULL << feature); 40 } 41 42 #ifndef CONFIG_USER_ONLY 43 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 44 { 45 /* Number of processors is in [25:24]; otherwise we RAZ */ 46 return (smp_cpus - 1) << 24; 47 } 48 #endif 49 50 static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = { 51 #ifndef CONFIG_USER_ONLY 52 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, 53 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, 54 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 55 .writefn = arm_cp_write_ignore }, 56 { .name = "L2CTLR", 57 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, 58 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 59 .writefn = arm_cp_write_ignore }, 60 #endif 61 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, 62 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, 63 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 64 { .name = "L2ECTLR", 65 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, 66 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 67 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, 68 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, 69 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 70 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 71 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, 72 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 73 { .name = "CPUACTLR", 74 .cp = 15, .opc1 = 0, .crm = 15, 75 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 76 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 77 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, 78 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 79 { .name = "CPUECTLR", 80 .cp = 15, .opc1 = 1, .crm = 15, 81 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 82 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, 83 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, 84 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 85 { .name = "CPUMERRSR", 86 .cp = 15, .opc1 = 2, .crm = 15, 87 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 88 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, 89 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, 90 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 91 { .name = "L2MERRSR", 92 .cp = 15, .opc1 = 3, .crm = 15, 93 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 94 REGINFO_SENTINEL 95 }; 96 97 static void aarch64_a57_initfn(Object *obj) 98 { 99 ARMCPU *cpu = ARM_CPU(obj); 100 101 cpu->dtb_compatible = "arm,cortex-a57"; 102 set_feature(&cpu->env, ARM_FEATURE_V8); 103 set_feature(&cpu->env, ARM_FEATURE_VFP4); 104 set_feature(&cpu->env, ARM_FEATURE_NEON); 105 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 106 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 107 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 108 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 109 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 110 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 111 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 112 set_feature(&cpu->env, ARM_FEATURE_CRC); 113 set_feature(&cpu->env, ARM_FEATURE_EL3); 114 set_feature(&cpu->env, ARM_FEATURE_PMU); 115 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 116 cpu->midr = 0x411fd070; 117 cpu->revidr = 0x00000000; 118 cpu->reset_fpsid = 0x41034070; 119 cpu->mvfr0 = 0x10110222; 120 cpu->mvfr1 = 0x12111111; 121 cpu->mvfr2 = 0x00000043; 122 cpu->ctr = 0x8444c004; 123 cpu->reset_sctlr = 0x00c50838; 124 cpu->id_pfr0 = 0x00000131; 125 cpu->id_pfr1 = 0x00011011; 126 cpu->id_dfr0 = 0x03010066; 127 cpu->id_afr0 = 0x00000000; 128 cpu->id_mmfr0 = 0x10101105; 129 cpu->id_mmfr1 = 0x40000000; 130 cpu->id_mmfr2 = 0x01260000; 131 cpu->id_mmfr3 = 0x02102211; 132 cpu->id_isar0 = 0x02101110; 133 cpu->id_isar1 = 0x13112111; 134 cpu->id_isar2 = 0x21232042; 135 cpu->id_isar3 = 0x01112131; 136 cpu->id_isar4 = 0x00011142; 137 cpu->id_isar5 = 0x00011121; 138 cpu->id_aa64pfr0 = 0x00002222; 139 cpu->id_aa64dfr0 = 0x10305106; 140 cpu->pmceid0 = 0x00000000; 141 cpu->pmceid1 = 0x00000000; 142 cpu->id_aa64isar0 = 0x00011120; 143 cpu->id_aa64mmfr0 = 0x00001124; 144 cpu->dbgdidr = 0x3516d000; 145 cpu->clidr = 0x0a200023; 146 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 147 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 148 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 149 cpu->dcz_blocksize = 4; /* 64 bytes */ 150 cpu->gic_num_lrs = 4; 151 cpu->gic_vpribits = 5; 152 cpu->gic_vprebits = 5; 153 define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); 154 } 155 156 static void aarch64_a53_initfn(Object *obj) 157 { 158 ARMCPU *cpu = ARM_CPU(obj); 159 160 cpu->dtb_compatible = "arm,cortex-a53"; 161 set_feature(&cpu->env, ARM_FEATURE_V8); 162 set_feature(&cpu->env, ARM_FEATURE_VFP4); 163 set_feature(&cpu->env, ARM_FEATURE_NEON); 164 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 165 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 166 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 167 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 168 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 169 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 170 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 171 set_feature(&cpu->env, ARM_FEATURE_CRC); 172 set_feature(&cpu->env, ARM_FEATURE_EL3); 173 set_feature(&cpu->env, ARM_FEATURE_PMU); 174 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 175 cpu->midr = 0x410fd034; 176 cpu->revidr = 0x00000000; 177 cpu->reset_fpsid = 0x41034070; 178 cpu->mvfr0 = 0x10110222; 179 cpu->mvfr1 = 0x12111111; 180 cpu->mvfr2 = 0x00000043; 181 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 182 cpu->reset_sctlr = 0x00c50838; 183 cpu->id_pfr0 = 0x00000131; 184 cpu->id_pfr1 = 0x00011011; 185 cpu->id_dfr0 = 0x03010066; 186 cpu->id_afr0 = 0x00000000; 187 cpu->id_mmfr0 = 0x10101105; 188 cpu->id_mmfr1 = 0x40000000; 189 cpu->id_mmfr2 = 0x01260000; 190 cpu->id_mmfr3 = 0x02102211; 191 cpu->id_isar0 = 0x02101110; 192 cpu->id_isar1 = 0x13112111; 193 cpu->id_isar2 = 0x21232042; 194 cpu->id_isar3 = 0x01112131; 195 cpu->id_isar4 = 0x00011142; 196 cpu->id_isar5 = 0x00011121; 197 cpu->id_aa64pfr0 = 0x00002222; 198 cpu->id_aa64dfr0 = 0x10305106; 199 cpu->id_aa64isar0 = 0x00011120; 200 cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 201 cpu->dbgdidr = 0x3516d000; 202 cpu->clidr = 0x0a200023; 203 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 204 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 205 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 206 cpu->dcz_blocksize = 4; /* 64 bytes */ 207 cpu->gic_num_lrs = 4; 208 cpu->gic_vpribits = 5; 209 cpu->gic_vprebits = 5; 210 define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); 211 } 212 213 #ifdef CONFIG_USER_ONLY 214 static void aarch64_any_initfn(Object *obj) 215 { 216 ARMCPU *cpu = ARM_CPU(obj); 217 218 set_feature(&cpu->env, ARM_FEATURE_V8); 219 set_feature(&cpu->env, ARM_FEATURE_VFP4); 220 set_feature(&cpu->env, ARM_FEATURE_NEON); 221 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 222 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 223 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 224 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 225 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 226 set_feature(&cpu->env, ARM_FEATURE_CRC); 227 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 228 cpu->dcz_blocksize = 7; /* 512 bytes */ 229 } 230 #endif 231 232 typedef struct ARMCPUInfo { 233 const char *name; 234 void (*initfn)(Object *obj); 235 void (*class_init)(ObjectClass *oc, void *data); 236 } ARMCPUInfo; 237 238 static const ARMCPUInfo aarch64_cpus[] = { 239 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 240 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 241 #ifdef CONFIG_USER_ONLY 242 { .name = "any", .initfn = aarch64_any_initfn }, 243 #endif 244 { .name = NULL } 245 }; 246 247 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 248 { 249 ARMCPU *cpu = ARM_CPU(obj); 250 251 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 252 } 253 254 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 255 { 256 ARMCPU *cpu = ARM_CPU(obj); 257 258 /* At this time, this property is only allowed if KVM is enabled. This 259 * restriction allows us to avoid fixing up functionality that assumes a 260 * uniform execution state like do_interrupt. 261 */ 262 if (!kvm_enabled()) { 263 error_setg(errp, "'aarch64' feature cannot be disabled " 264 "unless KVM is enabled"); 265 return; 266 } 267 268 if (value == false) { 269 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 270 } else { 271 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 272 } 273 } 274 275 static void aarch64_cpu_initfn(Object *obj) 276 { 277 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, 278 aarch64_cpu_set_aarch64, NULL); 279 object_property_set_description(obj, "aarch64", 280 "Set on/off to enable/disable aarch64 " 281 "execution state ", 282 NULL); 283 } 284 285 static void aarch64_cpu_finalizefn(Object *obj) 286 { 287 } 288 289 static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) 290 { 291 ARMCPU *cpu = ARM_CPU(cs); 292 /* It's OK to look at env for the current mode here, because it's 293 * never possible for an AArch64 TB to chain to an AArch32 TB. 294 * (Otherwise we would need to use synchronize_from_tb instead.) 295 */ 296 if (is_a64(&cpu->env)) { 297 cpu->env.pc = value; 298 } else { 299 cpu->env.regs[15] = value; 300 } 301 } 302 303 static gchar *aarch64_gdb_arch_name(CPUState *cs) 304 { 305 return g_strdup("aarch64"); 306 } 307 308 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 309 { 310 CPUClass *cc = CPU_CLASS(oc); 311 312 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 313 cc->set_pc = aarch64_cpu_set_pc; 314 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 315 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 316 cc->gdb_num_core_regs = 34; 317 cc->gdb_core_xml_file = "aarch64-core.xml"; 318 cc->gdb_arch_name = aarch64_gdb_arch_name; 319 } 320 321 static void aarch64_cpu_register(const ARMCPUInfo *info) 322 { 323 TypeInfo type_info = { 324 .parent = TYPE_AARCH64_CPU, 325 .instance_size = sizeof(ARMCPU), 326 .instance_init = info->initfn, 327 .class_size = sizeof(ARMCPUClass), 328 .class_init = info->class_init, 329 }; 330 331 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 332 type_register(&type_info); 333 g_free((void *)type_info.name); 334 } 335 336 static const TypeInfo aarch64_cpu_type_info = { 337 .name = TYPE_AARCH64_CPU, 338 .parent = TYPE_ARM_CPU, 339 .instance_size = sizeof(ARMCPU), 340 .instance_init = aarch64_cpu_initfn, 341 .instance_finalize = aarch64_cpu_finalizefn, 342 .abstract = true, 343 .class_size = sizeof(AArch64CPUClass), 344 .class_init = aarch64_cpu_class_init, 345 }; 346 347 static void aarch64_cpu_register_types(void) 348 { 349 const ARMCPUInfo *info = aarch64_cpus; 350 351 type_register_static(&aarch64_cpu_type_info); 352 353 while (info->name) { 354 aarch64_cpu_register(info); 355 info++; 356 } 357 } 358 359 type_init(aarch64_cpu_register_types) 360