1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #ifdef CONFIG_TCG 25 #include "hw/core/tcg-cpu-ops.h" 26 #endif /* CONFIG_TCG */ 27 #include "qemu/module.h" 28 #if !defined(CONFIG_USER_ONLY) 29 #include "hw/loader.h" 30 #endif 31 #include "sysemu/kvm.h" 32 #include "kvm_arm.h" 33 #include "qapi/visitor.h" 34 #include "hw/qdev-properties.h" 35 36 37 #ifndef CONFIG_USER_ONLY 38 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 39 { 40 ARMCPU *cpu = env_archcpu(env); 41 42 /* Number of cores is in [25:24]; otherwise we RAZ */ 43 return (cpu->core_count - 1) << 24; 44 } 45 #endif 46 47 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { 48 #ifndef CONFIG_USER_ONLY 49 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, 50 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, 51 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 52 .writefn = arm_cp_write_ignore }, 53 { .name = "L2CTLR", 54 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, 55 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 56 .writefn = arm_cp_write_ignore }, 57 #endif 58 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, 59 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, 60 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 61 { .name = "L2ECTLR", 62 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, 63 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 64 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, 65 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, 66 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 67 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 68 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, 69 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 70 { .name = "CPUACTLR", 71 .cp = 15, .opc1 = 0, .crm = 15, 72 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 73 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 74 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, 75 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 76 { .name = "CPUECTLR", 77 .cp = 15, .opc1 = 1, .crm = 15, 78 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 79 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, 80 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, 81 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 82 { .name = "CPUMERRSR", 83 .cp = 15, .opc1 = 2, .crm = 15, 84 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 85 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, 86 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, 87 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 88 { .name = "L2MERRSR", 89 .cp = 15, .opc1 = 3, .crm = 15, 90 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 91 REGINFO_SENTINEL 92 }; 93 94 static void aarch64_a57_initfn(Object *obj) 95 { 96 ARMCPU *cpu = ARM_CPU(obj); 97 98 cpu->dtb_compatible = "arm,cortex-a57"; 99 set_feature(&cpu->env, ARM_FEATURE_V8); 100 set_feature(&cpu->env, ARM_FEATURE_NEON); 101 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 102 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 103 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 104 set_feature(&cpu->env, ARM_FEATURE_EL2); 105 set_feature(&cpu->env, ARM_FEATURE_EL3); 106 set_feature(&cpu->env, ARM_FEATURE_PMU); 107 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 108 cpu->midr = 0x411fd070; 109 cpu->revidr = 0x00000000; 110 cpu->reset_fpsid = 0x41034070; 111 cpu->isar.mvfr0 = 0x10110222; 112 cpu->isar.mvfr1 = 0x12111111; 113 cpu->isar.mvfr2 = 0x00000043; 114 cpu->ctr = 0x8444c004; 115 cpu->reset_sctlr = 0x00c50838; 116 cpu->isar.id_pfr0 = 0x00000131; 117 cpu->isar.id_pfr1 = 0x00011011; 118 cpu->isar.id_dfr0 = 0x03010066; 119 cpu->id_afr0 = 0x00000000; 120 cpu->isar.id_mmfr0 = 0x10101105; 121 cpu->isar.id_mmfr1 = 0x40000000; 122 cpu->isar.id_mmfr2 = 0x01260000; 123 cpu->isar.id_mmfr3 = 0x02102211; 124 cpu->isar.id_isar0 = 0x02101110; 125 cpu->isar.id_isar1 = 0x13112111; 126 cpu->isar.id_isar2 = 0x21232042; 127 cpu->isar.id_isar3 = 0x01112131; 128 cpu->isar.id_isar4 = 0x00011142; 129 cpu->isar.id_isar5 = 0x00011121; 130 cpu->isar.id_isar6 = 0; 131 cpu->isar.id_aa64pfr0 = 0x00002222; 132 cpu->isar.id_aa64dfr0 = 0x10305106; 133 cpu->isar.id_aa64isar0 = 0x00011120; 134 cpu->isar.id_aa64mmfr0 = 0x00001124; 135 cpu->isar.dbgdidr = 0x3516d000; 136 cpu->clidr = 0x0a200023; 137 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 138 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 139 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 140 cpu->dcz_blocksize = 4; /* 64 bytes */ 141 cpu->gic_num_lrs = 4; 142 cpu->gic_vpribits = 5; 143 cpu->gic_vprebits = 5; 144 cpu->isar.reset_pmcr_el0 = 0x41013000; 145 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 146 } 147 148 static void aarch64_a53_initfn(Object *obj) 149 { 150 ARMCPU *cpu = ARM_CPU(obj); 151 152 cpu->dtb_compatible = "arm,cortex-a53"; 153 set_feature(&cpu->env, ARM_FEATURE_V8); 154 set_feature(&cpu->env, ARM_FEATURE_NEON); 155 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 156 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 157 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 158 set_feature(&cpu->env, ARM_FEATURE_EL2); 159 set_feature(&cpu->env, ARM_FEATURE_EL3); 160 set_feature(&cpu->env, ARM_FEATURE_PMU); 161 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 162 cpu->midr = 0x410fd034; 163 cpu->revidr = 0x00000000; 164 cpu->reset_fpsid = 0x41034070; 165 cpu->isar.mvfr0 = 0x10110222; 166 cpu->isar.mvfr1 = 0x12111111; 167 cpu->isar.mvfr2 = 0x00000043; 168 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 169 cpu->reset_sctlr = 0x00c50838; 170 cpu->isar.id_pfr0 = 0x00000131; 171 cpu->isar.id_pfr1 = 0x00011011; 172 cpu->isar.id_dfr0 = 0x03010066; 173 cpu->id_afr0 = 0x00000000; 174 cpu->isar.id_mmfr0 = 0x10101105; 175 cpu->isar.id_mmfr1 = 0x40000000; 176 cpu->isar.id_mmfr2 = 0x01260000; 177 cpu->isar.id_mmfr3 = 0x02102211; 178 cpu->isar.id_isar0 = 0x02101110; 179 cpu->isar.id_isar1 = 0x13112111; 180 cpu->isar.id_isar2 = 0x21232042; 181 cpu->isar.id_isar3 = 0x01112131; 182 cpu->isar.id_isar4 = 0x00011142; 183 cpu->isar.id_isar5 = 0x00011121; 184 cpu->isar.id_isar6 = 0; 185 cpu->isar.id_aa64pfr0 = 0x00002222; 186 cpu->isar.id_aa64dfr0 = 0x10305106; 187 cpu->isar.id_aa64isar0 = 0x00011120; 188 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 189 cpu->isar.dbgdidr = 0x3516d000; 190 cpu->clidr = 0x0a200023; 191 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 192 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 193 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 194 cpu->dcz_blocksize = 4; /* 64 bytes */ 195 cpu->gic_num_lrs = 4; 196 cpu->gic_vpribits = 5; 197 cpu->gic_vprebits = 5; 198 cpu->isar.reset_pmcr_el0 = 0x41033000; 199 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 200 } 201 202 static void aarch64_a72_initfn(Object *obj) 203 { 204 ARMCPU *cpu = ARM_CPU(obj); 205 206 cpu->dtb_compatible = "arm,cortex-a72"; 207 set_feature(&cpu->env, ARM_FEATURE_V8); 208 set_feature(&cpu->env, ARM_FEATURE_NEON); 209 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 210 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 211 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 212 set_feature(&cpu->env, ARM_FEATURE_EL2); 213 set_feature(&cpu->env, ARM_FEATURE_EL3); 214 set_feature(&cpu->env, ARM_FEATURE_PMU); 215 cpu->midr = 0x410fd083; 216 cpu->revidr = 0x00000000; 217 cpu->reset_fpsid = 0x41034080; 218 cpu->isar.mvfr0 = 0x10110222; 219 cpu->isar.mvfr1 = 0x12111111; 220 cpu->isar.mvfr2 = 0x00000043; 221 cpu->ctr = 0x8444c004; 222 cpu->reset_sctlr = 0x00c50838; 223 cpu->isar.id_pfr0 = 0x00000131; 224 cpu->isar.id_pfr1 = 0x00011011; 225 cpu->isar.id_dfr0 = 0x03010066; 226 cpu->id_afr0 = 0x00000000; 227 cpu->isar.id_mmfr0 = 0x10201105; 228 cpu->isar.id_mmfr1 = 0x40000000; 229 cpu->isar.id_mmfr2 = 0x01260000; 230 cpu->isar.id_mmfr3 = 0x02102211; 231 cpu->isar.id_isar0 = 0x02101110; 232 cpu->isar.id_isar1 = 0x13112111; 233 cpu->isar.id_isar2 = 0x21232042; 234 cpu->isar.id_isar3 = 0x01112131; 235 cpu->isar.id_isar4 = 0x00011142; 236 cpu->isar.id_isar5 = 0x00011121; 237 cpu->isar.id_aa64pfr0 = 0x00002222; 238 cpu->isar.id_aa64dfr0 = 0x10305106; 239 cpu->isar.id_aa64isar0 = 0x00011120; 240 cpu->isar.id_aa64mmfr0 = 0x00001124; 241 cpu->isar.dbgdidr = 0x3516d000; 242 cpu->clidr = 0x0a200023; 243 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 244 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 245 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ 246 cpu->dcz_blocksize = 4; /* 64 bytes */ 247 cpu->gic_num_lrs = 4; 248 cpu->gic_vpribits = 5; 249 cpu->gic_vprebits = 5; 250 cpu->isar.reset_pmcr_el0 = 0x41023000; 251 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 252 } 253 254 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) 255 { 256 /* 257 * If any vector lengths are explicitly enabled with sve<N> properties, 258 * then all other lengths are implicitly disabled. If sve-max-vq is 259 * specified then it is the same as explicitly enabling all lengths 260 * up to and including the specified maximum, which means all larger 261 * lengths will be implicitly disabled. If no sve<N> properties 262 * are enabled and sve-max-vq is not specified, then all lengths not 263 * explicitly disabled will be enabled. Additionally, all power-of-two 264 * vector lengths less than the maximum enabled length will be 265 * automatically enabled and all vector lengths larger than the largest 266 * disabled power-of-two vector length will be automatically disabled. 267 * Errors are generated if the user provided input that interferes with 268 * any of the above. Finally, if SVE is not disabled, then at least one 269 * vector length must be enabled. 270 */ 271 DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ); 272 DECLARE_BITMAP(tmp, ARM_MAX_VQ); 273 uint32_t vq, max_vq = 0; 274 275 /* Collect the set of vector lengths supported by KVM. */ 276 bitmap_zero(kvm_supported, ARM_MAX_VQ); 277 if (kvm_enabled() && kvm_arm_sve_supported()) { 278 kvm_arm_sve_get_vls(CPU(cpu), kvm_supported); 279 } else if (kvm_enabled()) { 280 assert(!cpu_isar_feature(aa64_sve, cpu)); 281 } 282 283 /* 284 * Process explicit sve<N> properties. 285 * From the properties, sve_vq_map<N> implies sve_vq_init<N>. 286 * Check first for any sve<N> enabled. 287 */ 288 if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) { 289 max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; 290 291 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { 292 error_setg(errp, "cannot enable sve%d", max_vq * 128); 293 error_append_hint(errp, "sve%d is larger than the maximum vector " 294 "length, sve-max-vq=%d (%d bits)\n", 295 max_vq * 128, cpu->sve_max_vq, 296 cpu->sve_max_vq * 128); 297 return; 298 } 299 300 if (kvm_enabled()) { 301 /* 302 * For KVM we have to automatically enable all supported unitialized 303 * lengths, even when the smaller lengths are not all powers-of-two. 304 */ 305 bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq); 306 bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); 307 } else { 308 /* Propagate enabled bits down through required powers-of-two. */ 309 for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { 310 if (!test_bit(vq - 1, cpu->sve_vq_init)) { 311 set_bit(vq - 1, cpu->sve_vq_map); 312 } 313 } 314 } 315 } else if (cpu->sve_max_vq == 0) { 316 /* 317 * No explicit bits enabled, and no implicit bits from sve-max-vq. 318 */ 319 if (!cpu_isar_feature(aa64_sve, cpu)) { 320 /* SVE is disabled and so are all vector lengths. Good. */ 321 return; 322 } 323 324 if (kvm_enabled()) { 325 /* Disabling a supported length disables all larger lengths. */ 326 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 327 if (test_bit(vq - 1, cpu->sve_vq_init) && 328 test_bit(vq - 1, kvm_supported)) { 329 break; 330 } 331 } 332 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 333 bitmap_andnot(cpu->sve_vq_map, kvm_supported, 334 cpu->sve_vq_init, max_vq); 335 if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) { 336 error_setg(errp, "cannot disable sve%d", vq * 128); 337 error_append_hint(errp, "Disabling sve%d results in all " 338 "vector lengths being disabled.\n", 339 vq * 128); 340 error_append_hint(errp, "With SVE enabled, at least one " 341 "vector length must be enabled.\n"); 342 return; 343 } 344 } else { 345 /* Disabling a power-of-two disables all larger lengths. */ 346 if (test_bit(0, cpu->sve_vq_init)) { 347 error_setg(errp, "cannot disable sve128"); 348 error_append_hint(errp, "Disabling sve128 results in all " 349 "vector lengths being disabled.\n"); 350 error_append_hint(errp, "With SVE enabled, at least one " 351 "vector length must be enabled.\n"); 352 return; 353 } 354 for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) { 355 if (test_bit(vq - 1, cpu->sve_vq_init)) { 356 break; 357 } 358 } 359 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 360 bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq); 361 } 362 363 max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1; 364 } 365 366 /* 367 * Process the sve-max-vq property. 368 * Note that we know from the above that no bit above 369 * sve-max-vq is currently set. 370 */ 371 if (cpu->sve_max_vq != 0) { 372 max_vq = cpu->sve_max_vq; 373 374 if (!test_bit(max_vq - 1, cpu->sve_vq_map) && 375 test_bit(max_vq - 1, cpu->sve_vq_init)) { 376 error_setg(errp, "cannot disable sve%d", max_vq * 128); 377 error_append_hint(errp, "The maximum vector length must be " 378 "enabled, sve-max-vq=%d (%d bits)\n", 379 max_vq, max_vq * 128); 380 return; 381 } 382 383 /* Set all bits not explicitly set within sve-max-vq. */ 384 bitmap_complement(tmp, cpu->sve_vq_init, max_vq); 385 bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); 386 } 387 388 /* 389 * We should know what max-vq is now. Also, as we're done 390 * manipulating sve-vq-map, we ensure any bits above max-vq 391 * are clear, just in case anybody looks. 392 */ 393 assert(max_vq != 0); 394 bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq); 395 396 if (kvm_enabled()) { 397 /* Ensure the set of lengths matches what KVM supports. */ 398 bitmap_xor(tmp, cpu->sve_vq_map, kvm_supported, max_vq); 399 if (!bitmap_empty(tmp, max_vq)) { 400 vq = find_last_bit(tmp, max_vq) + 1; 401 if (test_bit(vq - 1, cpu->sve_vq_map)) { 402 if (cpu->sve_max_vq) { 403 error_setg(errp, "cannot set sve-max-vq=%d", 404 cpu->sve_max_vq); 405 error_append_hint(errp, "This KVM host does not support " 406 "the vector length %d-bits.\n", 407 vq * 128); 408 error_append_hint(errp, "It may not be possible to use " 409 "sve-max-vq with this KVM host. Try " 410 "using only sve<N> properties.\n"); 411 } else { 412 error_setg(errp, "cannot enable sve%d", vq * 128); 413 error_append_hint(errp, "This KVM host does not support " 414 "the vector length %d-bits.\n", 415 vq * 128); 416 } 417 } else { 418 error_setg(errp, "cannot disable sve%d", vq * 128); 419 error_append_hint(errp, "The KVM host requires all " 420 "supported vector lengths smaller " 421 "than %d bits to also be enabled.\n", 422 max_vq * 128); 423 } 424 return; 425 } 426 } else { 427 /* Ensure all required powers-of-two are enabled. */ 428 for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { 429 if (!test_bit(vq - 1, cpu->sve_vq_map)) { 430 error_setg(errp, "cannot disable sve%d", vq * 128); 431 error_append_hint(errp, "sve%d is required as it " 432 "is a power-of-two length smaller than " 433 "the maximum, sve%d\n", 434 vq * 128, max_vq * 128); 435 return; 436 } 437 } 438 } 439 440 /* 441 * Now that we validated all our vector lengths, the only question 442 * left to answer is if we even want SVE at all. 443 */ 444 if (!cpu_isar_feature(aa64_sve, cpu)) { 445 error_setg(errp, "cannot enable sve%d", max_vq * 128); 446 error_append_hint(errp, "SVE must be enabled to enable vector " 447 "lengths.\n"); 448 error_append_hint(errp, "Add sve=on to the CPU property list.\n"); 449 return; 450 } 451 452 /* From now on sve_max_vq is the actual maximum supported length. */ 453 cpu->sve_max_vq = max_vq; 454 } 455 456 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, 457 void *opaque, Error **errp) 458 { 459 ARMCPU *cpu = ARM_CPU(obj); 460 uint32_t value; 461 462 /* All vector lengths are disabled when SVE is off. */ 463 if (!cpu_isar_feature(aa64_sve, cpu)) { 464 value = 0; 465 } else { 466 value = cpu->sve_max_vq; 467 } 468 visit_type_uint32(v, name, &value, errp); 469 } 470 471 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, 472 void *opaque, Error **errp) 473 { 474 ARMCPU *cpu = ARM_CPU(obj); 475 uint32_t max_vq; 476 477 if (!visit_type_uint32(v, name, &max_vq, errp)) { 478 return; 479 } 480 481 if (kvm_enabled() && !kvm_arm_sve_supported()) { 482 error_setg(errp, "cannot set sve-max-vq"); 483 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 484 return; 485 } 486 487 if (max_vq == 0 || max_vq > ARM_MAX_VQ) { 488 error_setg(errp, "unsupported SVE vector length"); 489 error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", 490 ARM_MAX_VQ); 491 return; 492 } 493 494 cpu->sve_max_vq = max_vq; 495 } 496 497 /* 498 * Note that cpu_arm_get/set_sve_vq cannot use the simpler 499 * object_property_add_bool interface because they make use 500 * of the contents of "name" to determine which bit on which 501 * to operate. 502 */ 503 static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, 504 void *opaque, Error **errp) 505 { 506 ARMCPU *cpu = ARM_CPU(obj); 507 uint32_t vq = atoi(&name[3]) / 128; 508 bool value; 509 510 /* All vector lengths are disabled when SVE is off. */ 511 if (!cpu_isar_feature(aa64_sve, cpu)) { 512 value = false; 513 } else { 514 value = test_bit(vq - 1, cpu->sve_vq_map); 515 } 516 visit_type_bool(v, name, &value, errp); 517 } 518 519 static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, 520 void *opaque, Error **errp) 521 { 522 ARMCPU *cpu = ARM_CPU(obj); 523 uint32_t vq = atoi(&name[3]) / 128; 524 bool value; 525 526 if (!visit_type_bool(v, name, &value, errp)) { 527 return; 528 } 529 530 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 531 error_setg(errp, "cannot enable %s", name); 532 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 533 return; 534 } 535 536 if (value) { 537 set_bit(vq - 1, cpu->sve_vq_map); 538 } else { 539 clear_bit(vq - 1, cpu->sve_vq_map); 540 } 541 set_bit(vq - 1, cpu->sve_vq_init); 542 } 543 544 static bool cpu_arm_get_sve(Object *obj, Error **errp) 545 { 546 ARMCPU *cpu = ARM_CPU(obj); 547 return cpu_isar_feature(aa64_sve, cpu); 548 } 549 550 static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) 551 { 552 ARMCPU *cpu = ARM_CPU(obj); 553 uint64_t t; 554 555 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 556 error_setg(errp, "'sve' feature not supported by KVM on this host"); 557 return; 558 } 559 560 t = cpu->isar.id_aa64pfr0; 561 t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); 562 cpu->isar.id_aa64pfr0 = t; 563 } 564 565 void aarch64_add_sve_properties(Object *obj) 566 { 567 uint32_t vq; 568 569 object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); 570 571 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 572 char name[8]; 573 sprintf(name, "sve%d", vq * 128); 574 object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, 575 cpu_arm_set_sve_vq, NULL, NULL); 576 } 577 } 578 579 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) 580 { 581 int arch_val = 0, impdef_val = 0; 582 uint64_t t; 583 584 /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ 585 if (cpu->prop_pauth) { 586 if (cpu->prop_pauth_impdef) { 587 impdef_val = 1; 588 } else { 589 arch_val = 1; 590 } 591 } else if (cpu->prop_pauth_impdef) { 592 error_setg(errp, "cannot enable pauth-impdef without pauth"); 593 error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); 594 } 595 596 t = cpu->isar.id_aa64isar1; 597 t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); 598 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); 599 t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); 600 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); 601 cpu->isar.id_aa64isar1 = t; 602 } 603 604 static Property arm_cpu_pauth_property = 605 DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); 606 static Property arm_cpu_pauth_impdef_property = 607 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); 608 609 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 610 * otherwise, a CPU with as many features enabled as our emulation supports. 611 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; 612 * this only needs to handle 64 bits. 613 */ 614 static void aarch64_max_initfn(Object *obj) 615 { 616 ARMCPU *cpu = ARM_CPU(obj); 617 618 if (kvm_enabled()) { 619 kvm_arm_set_cpu_features_from_host(cpu); 620 } else { 621 uint64_t t; 622 uint32_t u; 623 aarch64_a57_initfn(obj); 624 625 /* 626 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real 627 * one and try to apply errata workarounds or use impdef features we 628 * don't provide. 629 * An IMPLEMENTER field of 0 means "reserved for software use"; 630 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers 631 * to see which features are present"; 632 * the VARIANT, PARTNUM and REVISION fields are all implementation 633 * defined and we choose to define PARTNUM just in case guest 634 * code needs to distinguish this QEMU CPU from other software 635 * implementations, though this shouldn't be needed. 636 */ 637 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); 638 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); 639 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); 640 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); 641 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); 642 cpu->midr = t; 643 644 t = cpu->isar.id_aa64isar0; 645 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ 646 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); 647 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ 648 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); 649 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); 650 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); 651 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); 652 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); 653 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); 654 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); 655 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); 656 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ 657 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); 658 cpu->isar.id_aa64isar0 = t; 659 660 t = cpu->isar.id_aa64isar1; 661 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); 662 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); 663 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); 664 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); 665 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); 666 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); 667 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ 668 cpu->isar.id_aa64isar1 = t; 669 670 t = cpu->isar.id_aa64pfr0; 671 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); 672 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); 673 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); 674 t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); 675 t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); 676 cpu->isar.id_aa64pfr0 = t; 677 678 t = cpu->isar.id_aa64pfr1; 679 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); 680 t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); 681 /* 682 * Begin with full support for MTE. This will be downgraded to MTE=0 683 * during realize if the board provides no tag memory, much like 684 * we do for EL2 with the virtualization=on property. 685 */ 686 t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); 687 cpu->isar.id_aa64pfr1 = t; 688 689 t = cpu->isar.id_aa64mmfr0; 690 t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ 691 cpu->isar.id_aa64mmfr0 = t; 692 693 t = cpu->isar.id_aa64mmfr1; 694 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ 695 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); 696 t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); 697 t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ 698 t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ 699 t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ 700 cpu->isar.id_aa64mmfr1 = t; 701 702 t = cpu->isar.id_aa64mmfr2; 703 t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); 704 t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ 705 t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ 706 cpu->isar.id_aa64mmfr2 = t; 707 708 /* Replicate the same data to the 32-bit id registers. */ 709 u = cpu->isar.id_isar5; 710 u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ 711 u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); 712 u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); 713 u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); 714 u = FIELD_DP32(u, ID_ISAR5, RDM, 1); 715 u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); 716 cpu->isar.id_isar5 = u; 717 718 u = cpu->isar.id_isar6; 719 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); 720 u = FIELD_DP32(u, ID_ISAR6, DP, 1); 721 u = FIELD_DP32(u, ID_ISAR6, FHM, 1); 722 u = FIELD_DP32(u, ID_ISAR6, SB, 1); 723 u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); 724 cpu->isar.id_isar6 = u; 725 726 u = cpu->isar.id_pfr0; 727 u = FIELD_DP32(u, ID_PFR0, DIT, 1); 728 cpu->isar.id_pfr0 = u; 729 730 u = cpu->isar.id_pfr2; 731 u = FIELD_DP32(u, ID_PFR2, SSBS, 1); 732 cpu->isar.id_pfr2 = u; 733 734 u = cpu->isar.id_mmfr3; 735 u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ 736 cpu->isar.id_mmfr3 = u; 737 738 u = cpu->isar.id_mmfr4; 739 u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ 740 u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 741 u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ 742 u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ 743 cpu->isar.id_mmfr4 = u; 744 745 t = cpu->isar.id_aa64dfr0; 746 t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ 747 cpu->isar.id_aa64dfr0 = t; 748 749 u = cpu->isar.id_dfr0; 750 u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ 751 cpu->isar.id_dfr0 = u; 752 753 u = cpu->isar.mvfr1; 754 u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ 755 u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ 756 cpu->isar.mvfr1 = u; 757 758 #ifdef CONFIG_USER_ONLY 759 /* For usermode -cpu max we can use a larger and more efficient DCZ 760 * blocksize since we don't have to follow what the hardware does. 761 */ 762 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 763 cpu->dcz_blocksize = 7; /* 512 bytes */ 764 #endif 765 766 /* Default to PAUTH on, with the architected algorithm. */ 767 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); 768 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); 769 } 770 771 aarch64_add_sve_properties(obj); 772 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, 773 cpu_max_set_sve_max_vq, NULL, NULL); 774 } 775 776 static const ARMCPUInfo aarch64_cpus[] = { 777 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 778 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 779 { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, 780 { .name = "max", .initfn = aarch64_max_initfn }, 781 }; 782 783 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 784 { 785 ARMCPU *cpu = ARM_CPU(obj); 786 787 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 788 } 789 790 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 791 { 792 ARMCPU *cpu = ARM_CPU(obj); 793 794 /* At this time, this property is only allowed if KVM is enabled. This 795 * restriction allows us to avoid fixing up functionality that assumes a 796 * uniform execution state like do_interrupt. 797 */ 798 if (value == false) { 799 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 800 error_setg(errp, "'aarch64' feature cannot be disabled " 801 "unless KVM is enabled and 32-bit EL1 " 802 "is supported"); 803 return; 804 } 805 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 806 } else { 807 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 808 } 809 } 810 811 static void aarch64_cpu_finalizefn(Object *obj) 812 { 813 } 814 815 static gchar *aarch64_gdb_arch_name(CPUState *cs) 816 { 817 return g_strdup("aarch64"); 818 } 819 820 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 821 { 822 CPUClass *cc = CPU_CLASS(oc); 823 824 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 825 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 826 cc->gdb_num_core_regs = 34; 827 cc->gdb_core_xml_file = "aarch64-core.xml"; 828 cc->gdb_arch_name = aarch64_gdb_arch_name; 829 830 object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, 831 aarch64_cpu_set_aarch64); 832 object_class_property_set_description(oc, "aarch64", 833 "Set on/off to enable/disable aarch64 " 834 "execution state "); 835 } 836 837 static void aarch64_cpu_instance_init(Object *obj) 838 { 839 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 840 841 acc->info->initfn(obj); 842 arm_cpu_post_init(obj); 843 } 844 845 static void cpu_register_class_init(ObjectClass *oc, void *data) 846 { 847 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 848 849 acc->info = data; 850 } 851 852 void aarch64_cpu_register(const ARMCPUInfo *info) 853 { 854 TypeInfo type_info = { 855 .parent = TYPE_AARCH64_CPU, 856 .instance_size = sizeof(ARMCPU), 857 .instance_init = aarch64_cpu_instance_init, 858 .class_size = sizeof(ARMCPUClass), 859 .class_init = info->class_init ?: cpu_register_class_init, 860 .class_data = (void *)info, 861 }; 862 863 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 864 type_register(&type_info); 865 g_free((void *)type_info.name); 866 } 867 868 static const TypeInfo aarch64_cpu_type_info = { 869 .name = TYPE_AARCH64_CPU, 870 .parent = TYPE_ARM_CPU, 871 .instance_size = sizeof(ARMCPU), 872 .instance_finalize = aarch64_cpu_finalizefn, 873 .abstract = true, 874 .class_size = sizeof(AArch64CPUClass), 875 .class_init = aarch64_cpu_class_init, 876 }; 877 878 static void aarch64_cpu_register_types(void) 879 { 880 size_t i; 881 882 type_register_static(&aarch64_cpu_type_info); 883 884 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { 885 aarch64_cpu_register(&aarch64_cpus[i]); 886 } 887 } 888 889 type_init(aarch64_cpu_register_types) 890