1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "qemu-common.h" 25 #if !defined(CONFIG_USER_ONLY) 26 #include "hw/loader.h" 27 #endif 28 #include "hw/arm/arm.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "kvm_arm.h" 32 33 static inline void set_feature(CPUARMState *env, int feature) 34 { 35 env->features |= 1ULL << feature; 36 } 37 38 static inline void unset_feature(CPUARMState *env, int feature) 39 { 40 env->features &= ~(1ULL << feature); 41 } 42 43 #ifndef CONFIG_USER_ONLY 44 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 45 { 46 ARMCPU *cpu = arm_env_get_cpu(env); 47 48 /* Number of cores is in [25:24]; otherwise we RAZ */ 49 return (cpu->core_count - 1) << 24; 50 } 51 #endif 52 53 static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = { 54 #ifndef CONFIG_USER_ONLY 55 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, 56 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, 57 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 58 .writefn = arm_cp_write_ignore }, 59 { .name = "L2CTLR", 60 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, 61 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, 62 .writefn = arm_cp_write_ignore }, 63 #endif 64 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, 65 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, 66 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 67 { .name = "L2ECTLR", 68 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, 69 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 70 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, 71 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, 72 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 73 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 74 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, 75 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 76 { .name = "CPUACTLR", 77 .cp = 15, .opc1 = 0, .crm = 15, 78 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 79 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 80 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, 81 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 82 { .name = "CPUECTLR", 83 .cp = 15, .opc1 = 1, .crm = 15, 84 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 85 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, 86 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, 87 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 88 { .name = "CPUMERRSR", 89 .cp = 15, .opc1 = 2, .crm = 15, 90 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 91 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, 92 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, 93 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 94 { .name = "L2MERRSR", 95 .cp = 15, .opc1 = 3, .crm = 15, 96 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 97 REGINFO_SENTINEL 98 }; 99 100 static void aarch64_a57_initfn(Object *obj) 101 { 102 ARMCPU *cpu = ARM_CPU(obj); 103 104 cpu->dtb_compatible = "arm,cortex-a57"; 105 set_feature(&cpu->env, ARM_FEATURE_V8); 106 set_feature(&cpu->env, ARM_FEATURE_VFP4); 107 set_feature(&cpu->env, ARM_FEATURE_NEON); 108 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 109 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 110 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 111 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 112 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 113 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 114 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 115 set_feature(&cpu->env, ARM_FEATURE_CRC); 116 set_feature(&cpu->env, ARM_FEATURE_EL2); 117 set_feature(&cpu->env, ARM_FEATURE_EL3); 118 set_feature(&cpu->env, ARM_FEATURE_PMU); 119 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 120 cpu->midr = 0x411fd070; 121 cpu->revidr = 0x00000000; 122 cpu->reset_fpsid = 0x41034070; 123 cpu->mvfr0 = 0x10110222; 124 cpu->mvfr1 = 0x12111111; 125 cpu->mvfr2 = 0x00000043; 126 cpu->ctr = 0x8444c004; 127 cpu->reset_sctlr = 0x00c50838; 128 cpu->id_pfr0 = 0x00000131; 129 cpu->id_pfr1 = 0x00011011; 130 cpu->id_dfr0 = 0x03010066; 131 cpu->id_afr0 = 0x00000000; 132 cpu->id_mmfr0 = 0x10101105; 133 cpu->id_mmfr1 = 0x40000000; 134 cpu->id_mmfr2 = 0x01260000; 135 cpu->id_mmfr3 = 0x02102211; 136 cpu->id_isar0 = 0x02101110; 137 cpu->id_isar1 = 0x13112111; 138 cpu->id_isar2 = 0x21232042; 139 cpu->id_isar3 = 0x01112131; 140 cpu->id_isar4 = 0x00011142; 141 cpu->id_isar5 = 0x00011121; 142 cpu->id_aa64pfr0 = 0x00002222; 143 cpu->id_aa64dfr0 = 0x10305106; 144 cpu->pmceid0 = 0x00000000; 145 cpu->pmceid1 = 0x00000000; 146 cpu->id_aa64isar0 = 0x00011120; 147 cpu->id_aa64mmfr0 = 0x00001124; 148 cpu->dbgdidr = 0x3516d000; 149 cpu->clidr = 0x0a200023; 150 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 151 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 152 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 153 cpu->dcz_blocksize = 4; /* 64 bytes */ 154 cpu->gic_num_lrs = 4; 155 cpu->gic_vpribits = 5; 156 cpu->gic_vprebits = 5; 157 define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); 158 } 159 160 static void aarch64_a53_initfn(Object *obj) 161 { 162 ARMCPU *cpu = ARM_CPU(obj); 163 164 cpu->dtb_compatible = "arm,cortex-a53"; 165 set_feature(&cpu->env, ARM_FEATURE_V8); 166 set_feature(&cpu->env, ARM_FEATURE_VFP4); 167 set_feature(&cpu->env, ARM_FEATURE_NEON); 168 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 169 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 170 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 171 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 172 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 173 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 174 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 175 set_feature(&cpu->env, ARM_FEATURE_CRC); 176 set_feature(&cpu->env, ARM_FEATURE_EL2); 177 set_feature(&cpu->env, ARM_FEATURE_EL3); 178 set_feature(&cpu->env, ARM_FEATURE_PMU); 179 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 180 cpu->midr = 0x410fd034; 181 cpu->revidr = 0x00000000; 182 cpu->reset_fpsid = 0x41034070; 183 cpu->mvfr0 = 0x10110222; 184 cpu->mvfr1 = 0x12111111; 185 cpu->mvfr2 = 0x00000043; 186 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 187 cpu->reset_sctlr = 0x00c50838; 188 cpu->id_pfr0 = 0x00000131; 189 cpu->id_pfr1 = 0x00011011; 190 cpu->id_dfr0 = 0x03010066; 191 cpu->id_afr0 = 0x00000000; 192 cpu->id_mmfr0 = 0x10101105; 193 cpu->id_mmfr1 = 0x40000000; 194 cpu->id_mmfr2 = 0x01260000; 195 cpu->id_mmfr3 = 0x02102211; 196 cpu->id_isar0 = 0x02101110; 197 cpu->id_isar1 = 0x13112111; 198 cpu->id_isar2 = 0x21232042; 199 cpu->id_isar3 = 0x01112131; 200 cpu->id_isar4 = 0x00011142; 201 cpu->id_isar5 = 0x00011121; 202 cpu->id_aa64pfr0 = 0x00002222; 203 cpu->id_aa64dfr0 = 0x10305106; 204 cpu->id_aa64isar0 = 0x00011120; 205 cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 206 cpu->dbgdidr = 0x3516d000; 207 cpu->clidr = 0x0a200023; 208 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 209 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 210 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 211 cpu->dcz_blocksize = 4; /* 64 bytes */ 212 cpu->gic_num_lrs = 4; 213 cpu->gic_vpribits = 5; 214 cpu->gic_vprebits = 5; 215 define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); 216 } 217 218 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 219 * otherwise, a CPU with as many features enabled as our emulation supports. 220 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; 221 * this only needs to handle 64 bits. 222 */ 223 static void aarch64_max_initfn(Object *obj) 224 { 225 ARMCPU *cpu = ARM_CPU(obj); 226 227 if (kvm_enabled()) { 228 kvm_arm_set_cpu_features_from_host(cpu); 229 } else { 230 aarch64_a57_initfn(obj); 231 #ifdef CONFIG_USER_ONLY 232 /* We don't set these in system emulation mode for the moment, 233 * since we don't correctly set the ID registers to advertise them, 234 * and in some cases they're only available in AArch64 and not AArch32, 235 * whereas the architecture requires them to be present in both if 236 * present in either. 237 */ 238 set_feature(&cpu->env, ARM_FEATURE_V8); 239 set_feature(&cpu->env, ARM_FEATURE_VFP4); 240 set_feature(&cpu->env, ARM_FEATURE_NEON); 241 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 242 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 243 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 244 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 245 set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); 246 set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); 247 set_feature(&cpu->env, ARM_FEATURE_V8_SM3); 248 set_feature(&cpu->env, ARM_FEATURE_V8_SM4); 249 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 250 set_feature(&cpu->env, ARM_FEATURE_CRC); 251 set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS); 252 set_feature(&cpu->env, ARM_FEATURE_V8_RDM); 253 set_feature(&cpu->env, ARM_FEATURE_V8_FP16); 254 set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); 255 /* For usermode -cpu max we can use a larger and more efficient DCZ 256 * blocksize since we don't have to follow what the hardware does. 257 */ 258 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 259 cpu->dcz_blocksize = 7; /* 512 bytes */ 260 #endif 261 } 262 } 263 264 typedef struct ARMCPUInfo { 265 const char *name; 266 void (*initfn)(Object *obj); 267 void (*class_init)(ObjectClass *oc, void *data); 268 } ARMCPUInfo; 269 270 static const ARMCPUInfo aarch64_cpus[] = { 271 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 272 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 273 { .name = "max", .initfn = aarch64_max_initfn }, 274 { .name = NULL } 275 }; 276 277 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 278 { 279 ARMCPU *cpu = ARM_CPU(obj); 280 281 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 282 } 283 284 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 285 { 286 ARMCPU *cpu = ARM_CPU(obj); 287 288 /* At this time, this property is only allowed if KVM is enabled. This 289 * restriction allows us to avoid fixing up functionality that assumes a 290 * uniform execution state like do_interrupt. 291 */ 292 if (!kvm_enabled()) { 293 error_setg(errp, "'aarch64' feature cannot be disabled " 294 "unless KVM is enabled"); 295 return; 296 } 297 298 if (value == false) { 299 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 300 } else { 301 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 302 } 303 } 304 305 static void aarch64_cpu_initfn(Object *obj) 306 { 307 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, 308 aarch64_cpu_set_aarch64, NULL); 309 object_property_set_description(obj, "aarch64", 310 "Set on/off to enable/disable aarch64 " 311 "execution state ", 312 NULL); 313 } 314 315 static void aarch64_cpu_finalizefn(Object *obj) 316 { 317 } 318 319 static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) 320 { 321 ARMCPU *cpu = ARM_CPU(cs); 322 /* It's OK to look at env for the current mode here, because it's 323 * never possible for an AArch64 TB to chain to an AArch32 TB. 324 * (Otherwise we would need to use synchronize_from_tb instead.) 325 */ 326 if (is_a64(&cpu->env)) { 327 cpu->env.pc = value; 328 } else { 329 cpu->env.regs[15] = value; 330 } 331 } 332 333 static gchar *aarch64_gdb_arch_name(CPUState *cs) 334 { 335 return g_strdup("aarch64"); 336 } 337 338 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 339 { 340 CPUClass *cc = CPU_CLASS(oc); 341 342 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 343 cc->set_pc = aarch64_cpu_set_pc; 344 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 345 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 346 cc->gdb_num_core_regs = 34; 347 cc->gdb_core_xml_file = "aarch64-core.xml"; 348 cc->gdb_arch_name = aarch64_gdb_arch_name; 349 } 350 351 static void aarch64_cpu_register(const ARMCPUInfo *info) 352 { 353 TypeInfo type_info = { 354 .parent = TYPE_AARCH64_CPU, 355 .instance_size = sizeof(ARMCPU), 356 .instance_init = info->initfn, 357 .class_size = sizeof(ARMCPUClass), 358 .class_init = info->class_init, 359 }; 360 361 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 362 type_register(&type_info); 363 g_free((void *)type_info.name); 364 } 365 366 static const TypeInfo aarch64_cpu_type_info = { 367 .name = TYPE_AARCH64_CPU, 368 .parent = TYPE_ARM_CPU, 369 .instance_size = sizeof(ARMCPU), 370 .instance_init = aarch64_cpu_initfn, 371 .instance_finalize = aarch64_cpu_finalizefn, 372 .abstract = true, 373 .class_size = sizeof(AArch64CPUClass), 374 .class_init = aarch64_cpu_class_init, 375 }; 376 377 static void aarch64_cpu_register_types(void) 378 { 379 const ARMCPUInfo *info = aarch64_cpus; 380 381 type_register_static(&aarch64_cpu_type_info); 382 383 while (info->name) { 384 aarch64_cpu_register(info); 385 info++; 386 } 387 } 388 389 type_init(aarch64_cpu_register_types) 390 391 /* The manual says that when SVE is enabled and VQ is widened the 392 * implementation is allowed to zero the previously inaccessible 393 * portion of the registers. The corollary to that is that when 394 * SVE is enabled and VQ is narrowed we are also allowed to zero 395 * the now inaccessible portion of the registers. 396 * 397 * The intent of this is that no predicate bit beyond VQ is ever set. 398 * Which means that some operations on predicate registers themselves 399 * may operate on full uint64_t or even unrolled across the maximum 400 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally 401 * may well be cheaper than conditionals to restrict the operation 402 * to the relevant portion of a uint16_t[16]. 403 * 404 * TODO: Need to call this for changes to the real system registers 405 * and EL state changes. 406 */ 407 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) 408 { 409 int i, j; 410 uint64_t pmask; 411 412 assert(vq >= 1 && vq <= ARM_MAX_VQ); 413 414 /* Zap the high bits of the zregs. */ 415 for (i = 0; i < 32; i++) { 416 memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); 417 } 418 419 /* Zap the high bits of the pregs and ffr. */ 420 pmask = 0; 421 if (vq & 3) { 422 pmask = ~(-1ULL << (16 * (vq & 3))); 423 } 424 for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { 425 for (i = 0; i < 17; ++i) { 426 env->vfp.pregs[i].p[j] &= pmask; 427 } 428 pmask = 0; 429 } 430 } 431