1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "cpregs.h" 25 #include "qemu/module.h" 26 #include "qemu/units.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/hvf.h" 29 #include "sysemu/qtest.h" 30 #include "sysemu/tcg.h" 31 #include "kvm_arm.h" 32 #include "hvf_arm.h" 33 #include "qapi/visitor.h" 34 #include "hw/qdev-properties.h" 35 #include "internals.h" 36 #include "cpu-features.h" 37 #include "cpregs.h" 38 39 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) 40 { 41 /* 42 * If any vector lengths are explicitly enabled with sve<N> properties, 43 * then all other lengths are implicitly disabled. If sve-max-vq is 44 * specified then it is the same as explicitly enabling all lengths 45 * up to and including the specified maximum, which means all larger 46 * lengths will be implicitly disabled. If no sve<N> properties 47 * are enabled and sve-max-vq is not specified, then all lengths not 48 * explicitly disabled will be enabled. Additionally, all power-of-two 49 * vector lengths less than the maximum enabled length will be 50 * automatically enabled and all vector lengths larger than the largest 51 * disabled power-of-two vector length will be automatically disabled. 52 * Errors are generated if the user provided input that interferes with 53 * any of the above. Finally, if SVE is not disabled, then at least one 54 * vector length must be enabled. 55 */ 56 uint32_t vq_map = cpu->sve_vq.map; 57 uint32_t vq_init = cpu->sve_vq.init; 58 uint32_t vq_supported; 59 uint32_t vq_mask = 0; 60 uint32_t tmp, vq, max_vq = 0; 61 62 /* 63 * CPU models specify a set of supported vector lengths which are 64 * enabled by default. Attempting to enable any vector length not set 65 * in the supported bitmap results in an error. When KVM is enabled we 66 * fetch the supported bitmap from the host. 67 */ 68 if (kvm_enabled()) { 69 if (kvm_arm_sve_supported()) { 70 cpu->sve_vq.supported = kvm_arm_sve_get_vls(cpu); 71 vq_supported = cpu->sve_vq.supported; 72 } else { 73 assert(!cpu_isar_feature(aa64_sve, cpu)); 74 vq_supported = 0; 75 } 76 } else { 77 vq_supported = cpu->sve_vq.supported; 78 } 79 80 /* 81 * Process explicit sve<N> properties. 82 * From the properties, sve_vq_map<N> implies sve_vq_init<N>. 83 * Check first for any sve<N> enabled. 84 */ 85 if (vq_map != 0) { 86 max_vq = 32 - clz32(vq_map); 87 vq_mask = MAKE_64BIT_MASK(0, max_vq); 88 89 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { 90 error_setg(errp, "cannot enable sve%d", max_vq * 128); 91 error_append_hint(errp, "sve%d is larger than the maximum vector " 92 "length, sve-max-vq=%d (%d bits)\n", 93 max_vq * 128, cpu->sve_max_vq, 94 cpu->sve_max_vq * 128); 95 return; 96 } 97 98 if (kvm_enabled()) { 99 /* 100 * For KVM we have to automatically enable all supported uninitialized 101 * lengths, even when the smaller lengths are not all powers-of-two. 102 */ 103 vq_map |= vq_supported & ~vq_init & vq_mask; 104 } else { 105 /* Propagate enabled bits down through required powers-of-two. */ 106 vq_map |= SVE_VQ_POW2_MAP & ~vq_init & vq_mask; 107 } 108 } else if (cpu->sve_max_vq == 0) { 109 /* 110 * No explicit bits enabled, and no implicit bits from sve-max-vq. 111 */ 112 if (!cpu_isar_feature(aa64_sve, cpu)) { 113 /* 114 * SVE is disabled and so are all vector lengths. Good. 115 * Disable all SVE extensions as well. 116 */ 117 cpu->isar.id_aa64zfr0 = 0; 118 return; 119 } 120 121 if (kvm_enabled()) { 122 /* Disabling a supported length disables all larger lengths. */ 123 tmp = vq_init & vq_supported; 124 } else { 125 /* Disabling a power-of-two disables all larger lengths. */ 126 tmp = vq_init & SVE_VQ_POW2_MAP; 127 } 128 vq = ctz32(tmp) + 1; 129 130 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 131 vq_mask = max_vq > 0 ? MAKE_64BIT_MASK(0, max_vq) : 0; 132 vq_map = vq_supported & ~vq_init & vq_mask; 133 134 if (vq_map == 0) { 135 error_setg(errp, "cannot disable sve%d", vq * 128); 136 error_append_hint(errp, "Disabling sve%d results in all " 137 "vector lengths being disabled.\n", 138 vq * 128); 139 error_append_hint(errp, "With SVE enabled, at least one " 140 "vector length must be enabled.\n"); 141 return; 142 } 143 144 max_vq = 32 - clz32(vq_map); 145 vq_mask = MAKE_64BIT_MASK(0, max_vq); 146 } 147 148 /* 149 * Process the sve-max-vq property. 150 * Note that we know from the above that no bit above 151 * sve-max-vq is currently set. 152 */ 153 if (cpu->sve_max_vq != 0) { 154 max_vq = cpu->sve_max_vq; 155 vq_mask = MAKE_64BIT_MASK(0, max_vq); 156 157 if (vq_init & ~vq_map & (1 << (max_vq - 1))) { 158 error_setg(errp, "cannot disable sve%d", max_vq * 128); 159 error_append_hint(errp, "The maximum vector length must be " 160 "enabled, sve-max-vq=%d (%d bits)\n", 161 max_vq, max_vq * 128); 162 return; 163 } 164 165 /* Set all bits not explicitly set within sve-max-vq. */ 166 vq_map |= ~vq_init & vq_mask; 167 } 168 169 /* 170 * We should know what max-vq is now. Also, as we're done 171 * manipulating sve-vq-map, we ensure any bits above max-vq 172 * are clear, just in case anybody looks. 173 */ 174 assert(max_vq != 0); 175 assert(vq_mask != 0); 176 vq_map &= vq_mask; 177 178 /* Ensure the set of lengths matches what is supported. */ 179 tmp = vq_map ^ (vq_supported & vq_mask); 180 if (tmp) { 181 vq = 32 - clz32(tmp); 182 if (vq_map & (1 << (vq - 1))) { 183 if (cpu->sve_max_vq) { 184 error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq); 185 error_append_hint(errp, "This CPU does not support " 186 "the vector length %d-bits.\n", vq * 128); 187 error_append_hint(errp, "It may not be possible to use " 188 "sve-max-vq with this CPU. Try " 189 "using only sve<N> properties.\n"); 190 } else { 191 error_setg(errp, "cannot enable sve%d", vq * 128); 192 if (vq_supported) { 193 error_append_hint(errp, "This CPU does not support " 194 "the vector length %d-bits.\n", vq * 128); 195 } else { 196 error_append_hint(errp, "SVE not supported by KVM " 197 "on this host\n"); 198 } 199 } 200 return; 201 } else { 202 if (kvm_enabled()) { 203 error_setg(errp, "cannot disable sve%d", vq * 128); 204 error_append_hint(errp, "The KVM host requires all " 205 "supported vector lengths smaller " 206 "than %d bits to also be enabled.\n", 207 max_vq * 128); 208 return; 209 } else { 210 /* Ensure all required powers-of-two are enabled. */ 211 tmp = SVE_VQ_POW2_MAP & vq_mask & ~vq_map; 212 if (tmp) { 213 vq = 32 - clz32(tmp); 214 error_setg(errp, "cannot disable sve%d", vq * 128); 215 error_append_hint(errp, "sve%d is required as it " 216 "is a power-of-two length smaller " 217 "than the maximum, sve%d\n", 218 vq * 128, max_vq * 128); 219 return; 220 } 221 } 222 } 223 } 224 225 /* 226 * Now that we validated all our vector lengths, the only question 227 * left to answer is if we even want SVE at all. 228 */ 229 if (!cpu_isar_feature(aa64_sve, cpu)) { 230 error_setg(errp, "cannot enable sve%d", max_vq * 128); 231 error_append_hint(errp, "SVE must be enabled to enable vector " 232 "lengths.\n"); 233 error_append_hint(errp, "Add sve=on to the CPU property list.\n"); 234 return; 235 } 236 237 /* From now on sve_max_vq is the actual maximum supported length. */ 238 cpu->sve_max_vq = max_vq; 239 cpu->sve_vq.map = vq_map; 240 } 241 242 /* 243 * Note that cpu_arm_{get,set}_vq cannot use the simpler 244 * object_property_add_bool interface because they make use of the 245 * contents of "name" to determine which bit on which to operate. 246 */ 247 static void cpu_arm_get_vq(Object *obj, Visitor *v, const char *name, 248 void *opaque, Error **errp) 249 { 250 ARMCPU *cpu = ARM_CPU(obj); 251 ARMVQMap *vq_map = opaque; 252 uint32_t vq = atoi(&name[3]) / 128; 253 bool sve = vq_map == &cpu->sve_vq; 254 bool value; 255 256 /* All vector lengths are disabled when feature is off. */ 257 if (sve 258 ? !cpu_isar_feature(aa64_sve, cpu) 259 : !cpu_isar_feature(aa64_sme, cpu)) { 260 value = false; 261 } else { 262 value = extract32(vq_map->map, vq - 1, 1); 263 } 264 visit_type_bool(v, name, &value, errp); 265 } 266 267 static void cpu_arm_set_vq(Object *obj, Visitor *v, const char *name, 268 void *opaque, Error **errp) 269 { 270 ARMVQMap *vq_map = opaque; 271 uint32_t vq = atoi(&name[3]) / 128; 272 bool value; 273 274 if (!visit_type_bool(v, name, &value, errp)) { 275 return; 276 } 277 278 vq_map->map = deposit32(vq_map->map, vq - 1, 1, value); 279 vq_map->init |= 1 << (vq - 1); 280 } 281 282 static bool cpu_arm_get_sve(Object *obj, Error **errp) 283 { 284 ARMCPU *cpu = ARM_CPU(obj); 285 return cpu_isar_feature(aa64_sve, cpu); 286 } 287 288 static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) 289 { 290 ARMCPU *cpu = ARM_CPU(obj); 291 uint64_t t; 292 293 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 294 error_setg(errp, "'sve' feature not supported by KVM on this host"); 295 return; 296 } 297 298 t = cpu->isar.id_aa64pfr0; 299 t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); 300 cpu->isar.id_aa64pfr0 = t; 301 } 302 303 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) 304 { 305 uint32_t vq_map = cpu->sme_vq.map; 306 uint32_t vq_init = cpu->sme_vq.init; 307 uint32_t vq_supported = cpu->sme_vq.supported; 308 uint32_t vq; 309 310 if (vq_map == 0) { 311 if (!cpu_isar_feature(aa64_sme, cpu)) { 312 cpu->isar.id_aa64smfr0 = 0; 313 return; 314 } 315 316 /* TODO: KVM will require limitations via SMCR_EL2. */ 317 vq_map = vq_supported & ~vq_init; 318 319 if (vq_map == 0) { 320 vq = ctz32(vq_supported) + 1; 321 error_setg(errp, "cannot disable sme%d", vq * 128); 322 error_append_hint(errp, "All SME vector lengths are disabled.\n"); 323 error_append_hint(errp, "With SME enabled, at least one " 324 "vector length must be enabled.\n"); 325 return; 326 } 327 } else { 328 if (!cpu_isar_feature(aa64_sme, cpu)) { 329 vq = 32 - clz32(vq_map); 330 error_setg(errp, "cannot enable sme%d", vq * 128); 331 error_append_hint(errp, "SME must be enabled to enable " 332 "vector lengths.\n"); 333 error_append_hint(errp, "Add sme=on to the CPU property list.\n"); 334 return; 335 } 336 /* TODO: KVM will require limitations via SMCR_EL2. */ 337 } 338 339 cpu->sme_vq.map = vq_map; 340 } 341 342 static bool cpu_arm_get_sme(Object *obj, Error **errp) 343 { 344 ARMCPU *cpu = ARM_CPU(obj); 345 return cpu_isar_feature(aa64_sme, cpu); 346 } 347 348 static void cpu_arm_set_sme(Object *obj, bool value, Error **errp) 349 { 350 ARMCPU *cpu = ARM_CPU(obj); 351 uint64_t t; 352 353 t = cpu->isar.id_aa64pfr1; 354 t = FIELD_DP64(t, ID_AA64PFR1, SME, value); 355 cpu->isar.id_aa64pfr1 = t; 356 } 357 358 static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp) 359 { 360 ARMCPU *cpu = ARM_CPU(obj); 361 return cpu_isar_feature(aa64_sme, cpu) && 362 cpu_isar_feature(aa64_sme_fa64, cpu); 363 } 364 365 static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp) 366 { 367 ARMCPU *cpu = ARM_CPU(obj); 368 uint64_t t; 369 370 t = cpu->isar.id_aa64smfr0; 371 t = FIELD_DP64(t, ID_AA64SMFR0, FA64, value); 372 cpu->isar.id_aa64smfr0 = t; 373 } 374 375 #ifdef CONFIG_USER_ONLY 376 /* Mirror linux /proc/sys/abi/{sve,sme}_default_vector_length. */ 377 static void cpu_arm_set_default_vec_len(Object *obj, Visitor *v, 378 const char *name, void *opaque, 379 Error **errp) 380 { 381 uint32_t *ptr_default_vq = opaque; 382 int32_t default_len, default_vq, remainder; 383 384 if (!visit_type_int32(v, name, &default_len, errp)) { 385 return; 386 } 387 388 /* Undocumented, but the kernel allows -1 to indicate "maximum". */ 389 if (default_len == -1) { 390 *ptr_default_vq = ARM_MAX_VQ; 391 return; 392 } 393 394 default_vq = default_len / 16; 395 remainder = default_len % 16; 396 397 /* 398 * Note that the 512 max comes from include/uapi/asm/sve_context.h 399 * and is the maximum architectural width of ZCR_ELx.LEN. 400 */ 401 if (remainder || default_vq < 1 || default_vq > 512) { 402 ARMCPU *cpu = ARM_CPU(obj); 403 const char *which = 404 (ptr_default_vq == &cpu->sve_default_vq ? "sve" : "sme"); 405 406 error_setg(errp, "cannot set %s-default-vector-length", which); 407 if (remainder) { 408 error_append_hint(errp, "Vector length not a multiple of 16\n"); 409 } else if (default_vq < 1) { 410 error_append_hint(errp, "Vector length smaller than 16\n"); 411 } else { 412 error_append_hint(errp, "Vector length larger than %d\n", 413 512 * 16); 414 } 415 return; 416 } 417 418 *ptr_default_vq = default_vq; 419 } 420 421 static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v, 422 const char *name, void *opaque, 423 Error **errp) 424 { 425 uint32_t *ptr_default_vq = opaque; 426 int32_t value = *ptr_default_vq * 16; 427 428 visit_type_int32(v, name, &value, errp); 429 } 430 #endif 431 432 void aarch64_add_sve_properties(Object *obj) 433 { 434 ARMCPU *cpu = ARM_CPU(obj); 435 uint32_t vq; 436 437 object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); 438 439 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 440 char name[8]; 441 snprintf(name, sizeof(name), "sve%d", vq * 128); 442 object_property_add(obj, name, "bool", cpu_arm_get_vq, 443 cpu_arm_set_vq, NULL, &cpu->sve_vq); 444 } 445 446 #ifdef CONFIG_USER_ONLY 447 /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ 448 object_property_add(obj, "sve-default-vector-length", "int32", 449 cpu_arm_get_default_vec_len, 450 cpu_arm_set_default_vec_len, NULL, 451 &cpu->sve_default_vq); 452 #endif 453 } 454 455 void aarch64_add_sme_properties(Object *obj) 456 { 457 ARMCPU *cpu = ARM_CPU(obj); 458 uint32_t vq; 459 460 object_property_add_bool(obj, "sme", cpu_arm_get_sme, cpu_arm_set_sme); 461 object_property_add_bool(obj, "sme_fa64", cpu_arm_get_sme_fa64, 462 cpu_arm_set_sme_fa64); 463 464 for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) { 465 char name[8]; 466 snprintf(name, sizeof(name), "sme%d", vq * 128); 467 object_property_add(obj, name, "bool", cpu_arm_get_vq, 468 cpu_arm_set_vq, NULL, &cpu->sme_vq); 469 } 470 471 #ifdef CONFIG_USER_ONLY 472 /* Mirror linux /proc/sys/abi/sme_default_vector_length. */ 473 object_property_add(obj, "sme-default-vector-length", "int32", 474 cpu_arm_get_default_vec_len, 475 cpu_arm_set_default_vec_len, NULL, 476 &cpu->sme_default_vq); 477 #endif 478 } 479 480 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) 481 { 482 ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu); 483 uint64_t isar1, isar2; 484 485 /* 486 * These properties enable or disable Pauth as a whole, or change 487 * the pauth algorithm, but do not change the set of features that 488 * are present. We have saved a copy of those features above and 489 * will now place it into the field that chooses the algorithm. 490 * 491 * Begin by disabling all fields. 492 */ 493 isar1 = cpu->isar.id_aa64isar1; 494 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, 0); 495 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 0); 496 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, 0); 497 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0); 498 499 isar2 = cpu->isar.id_aa64isar2; 500 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0); 501 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0); 502 503 if (kvm_enabled() || hvf_enabled()) { 504 /* 505 * Exit early if PAuth is enabled and fall through to disable it. 506 * The algorithm selection properties are not present. 507 */ 508 if (cpu->prop_pauth) { 509 if (features == 0) { 510 error_setg(errp, "'pauth' feature not supported by " 511 "%s on this host", current_accel_name()); 512 } 513 return; 514 } 515 } else { 516 /* Pauth properties are only present when the model supports it. */ 517 if (features == 0) { 518 assert(!cpu->prop_pauth); 519 return; 520 } 521 522 if (cpu->prop_pauth) { 523 if (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) { 524 error_setg(errp, 525 "cannot enable both pauth-impdef and pauth-qarma3"); 526 return; 527 } 528 529 if (cpu->prop_pauth_impdef) { 530 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features); 531 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1); 532 } else if (cpu->prop_pauth_qarma3) { 533 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features); 534 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1); 535 } else { 536 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); 537 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); 538 } 539 } else if (cpu->prop_pauth_impdef || cpu->prop_pauth_qarma3) { 540 error_setg(errp, "cannot enable pauth-impdef or " 541 "pauth-qarma3 without pauth"); 542 error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); 543 } 544 } 545 546 cpu->isar.id_aa64isar1 = isar1; 547 cpu->isar.id_aa64isar2 = isar2; 548 } 549 550 static Property arm_cpu_pauth_property = 551 DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); 552 static Property arm_cpu_pauth_impdef_property = 553 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); 554 static Property arm_cpu_pauth_qarma3_property = 555 DEFINE_PROP_BOOL("pauth-qarma3", ARMCPU, prop_pauth_qarma3, false); 556 557 void aarch64_add_pauth_properties(Object *obj) 558 { 559 ARMCPU *cpu = ARM_CPU(obj); 560 561 /* Default to PAUTH on, with the architected algorithm on TCG. */ 562 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); 563 if (kvm_enabled() || hvf_enabled()) { 564 /* 565 * Mirror PAuth support from the probed sysregs back into the 566 * property for KVM or hvf. Is it just a bit backward? Yes it is! 567 * Note that prop_pauth is true whether the host CPU supports the 568 * architected QARMA5 algorithm or the IMPDEF one. We don't 569 * provide the separate pauth-impdef property for KVM or hvf, 570 * only for TCG. 571 */ 572 cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); 573 } else { 574 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); 575 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma3_property); 576 } 577 } 578 579 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) 580 { 581 uint64_t t; 582 583 /* 584 * We only install the property for tcg -cpu max; this is the 585 * only situation in which the cpu field can be true. 586 */ 587 if (!cpu->prop_lpa2) { 588 return; 589 } 590 591 t = cpu->isar.id_aa64mmfr0; 592 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */ 593 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */ 594 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */ 595 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */ 596 cpu->isar.id_aa64mmfr0 = t; 597 } 598 599 static void aarch64_a57_initfn(Object *obj) 600 { 601 ARMCPU *cpu = ARM_CPU(obj); 602 603 cpu->dtb_compatible = "arm,cortex-a57"; 604 set_feature(&cpu->env, ARM_FEATURE_V8); 605 set_feature(&cpu->env, ARM_FEATURE_NEON); 606 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 607 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 608 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 609 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 610 set_feature(&cpu->env, ARM_FEATURE_EL2); 611 set_feature(&cpu->env, ARM_FEATURE_EL3); 612 set_feature(&cpu->env, ARM_FEATURE_PMU); 613 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 614 cpu->midr = 0x411fd070; 615 cpu->revidr = 0x00000000; 616 cpu->reset_fpsid = 0x41034070; 617 cpu->isar.mvfr0 = 0x10110222; 618 cpu->isar.mvfr1 = 0x12111111; 619 cpu->isar.mvfr2 = 0x00000043; 620 cpu->ctr = 0x8444c004; 621 cpu->reset_sctlr = 0x00c50838; 622 cpu->isar.id_pfr0 = 0x00000131; 623 cpu->isar.id_pfr1 = 0x00011011; 624 cpu->isar.id_dfr0 = 0x03010066; 625 cpu->id_afr0 = 0x00000000; 626 cpu->isar.id_mmfr0 = 0x10101105; 627 cpu->isar.id_mmfr1 = 0x40000000; 628 cpu->isar.id_mmfr2 = 0x01260000; 629 cpu->isar.id_mmfr3 = 0x02102211; 630 cpu->isar.id_isar0 = 0x02101110; 631 cpu->isar.id_isar1 = 0x13112111; 632 cpu->isar.id_isar2 = 0x21232042; 633 cpu->isar.id_isar3 = 0x01112131; 634 cpu->isar.id_isar4 = 0x00011142; 635 cpu->isar.id_isar5 = 0x00011121; 636 cpu->isar.id_isar6 = 0; 637 cpu->isar.id_aa64pfr0 = 0x00002222; 638 cpu->isar.id_aa64dfr0 = 0x10305106; 639 cpu->isar.id_aa64isar0 = 0x00011120; 640 cpu->isar.id_aa64mmfr0 = 0x00001124; 641 cpu->isar.dbgdidr = 0x3516d000; 642 cpu->isar.dbgdevid = 0x01110f13; 643 cpu->isar.dbgdevid1 = 0x2; 644 cpu->isar.reset_pmcr_el0 = 0x41013000; 645 cpu->clidr = 0x0a200023; 646 /* 32KB L1 dcache */ 647 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); 648 /* 48KB L1 icache */ 649 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2); 650 /* 2048KB L2 cache */ 651 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7); 652 cpu->dcz_blocksize = 4; /* 64 bytes */ 653 cpu->gic_num_lrs = 4; 654 cpu->gic_vpribits = 5; 655 cpu->gic_vprebits = 5; 656 cpu->gic_pribits = 5; 657 define_cortex_a72_a57_a53_cp_reginfo(cpu); 658 } 659 660 static void aarch64_a53_initfn(Object *obj) 661 { 662 ARMCPU *cpu = ARM_CPU(obj); 663 664 cpu->dtb_compatible = "arm,cortex-a53"; 665 set_feature(&cpu->env, ARM_FEATURE_V8); 666 set_feature(&cpu->env, ARM_FEATURE_NEON); 667 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 668 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 669 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 670 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 671 set_feature(&cpu->env, ARM_FEATURE_EL2); 672 set_feature(&cpu->env, ARM_FEATURE_EL3); 673 set_feature(&cpu->env, ARM_FEATURE_PMU); 674 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 675 cpu->midr = 0x410fd034; 676 cpu->revidr = 0x00000100; 677 cpu->reset_fpsid = 0x41034070; 678 cpu->isar.mvfr0 = 0x10110222; 679 cpu->isar.mvfr1 = 0x12111111; 680 cpu->isar.mvfr2 = 0x00000043; 681 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 682 cpu->reset_sctlr = 0x00c50838; 683 cpu->isar.id_pfr0 = 0x00000131; 684 cpu->isar.id_pfr1 = 0x00011011; 685 cpu->isar.id_dfr0 = 0x03010066; 686 cpu->id_afr0 = 0x00000000; 687 cpu->isar.id_mmfr0 = 0x10101105; 688 cpu->isar.id_mmfr1 = 0x40000000; 689 cpu->isar.id_mmfr2 = 0x01260000; 690 cpu->isar.id_mmfr3 = 0x02102211; 691 cpu->isar.id_isar0 = 0x02101110; 692 cpu->isar.id_isar1 = 0x13112111; 693 cpu->isar.id_isar2 = 0x21232042; 694 cpu->isar.id_isar3 = 0x01112131; 695 cpu->isar.id_isar4 = 0x00011142; 696 cpu->isar.id_isar5 = 0x00011121; 697 cpu->isar.id_isar6 = 0; 698 cpu->isar.id_aa64pfr0 = 0x00002222; 699 cpu->isar.id_aa64dfr0 = 0x10305106; 700 cpu->isar.id_aa64isar0 = 0x00011120; 701 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 702 cpu->isar.dbgdidr = 0x3516d000; 703 cpu->isar.dbgdevid = 0x00110f13; 704 cpu->isar.dbgdevid1 = 0x1; 705 cpu->isar.reset_pmcr_el0 = 0x41033000; 706 cpu->clidr = 0x0a200023; 707 /* 32KB L1 dcache */ 708 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); 709 /* 32KB L1 icache */ 710 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, 2); 711 /* 1024KB L2 cache */ 712 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7); 713 cpu->dcz_blocksize = 4; /* 64 bytes */ 714 cpu->gic_num_lrs = 4; 715 cpu->gic_vpribits = 5; 716 cpu->gic_vprebits = 5; 717 cpu->gic_pribits = 5; 718 define_cortex_a72_a57_a53_cp_reginfo(cpu); 719 } 720 721 static void aarch64_host_initfn(Object *obj) 722 { 723 #if defined(CONFIG_KVM) 724 ARMCPU *cpu = ARM_CPU(obj); 725 kvm_arm_set_cpu_features_from_host(cpu); 726 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 727 aarch64_add_sve_properties(obj); 728 aarch64_add_pauth_properties(obj); 729 } 730 #elif defined(CONFIG_HVF) 731 ARMCPU *cpu = ARM_CPU(obj); 732 hvf_arm_set_cpu_features_from_host(cpu); 733 aarch64_add_pauth_properties(obj); 734 #else 735 g_assert_not_reached(); 736 #endif 737 } 738 739 static void aarch64_max_initfn(Object *obj) 740 { 741 if (kvm_enabled() || hvf_enabled()) { 742 /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ 743 aarch64_host_initfn(obj); 744 return; 745 } 746 747 if (tcg_enabled() || qtest_enabled()) { 748 aarch64_a57_initfn(obj); 749 } 750 751 /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */ 752 if (tcg_enabled()) { 753 aarch64_max_tcg_initfn(obj); 754 } 755 } 756 757 static const ARMCPUInfo aarch64_cpus[] = { 758 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 759 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 760 { .name = "max", .initfn = aarch64_max_initfn }, 761 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 762 { .name = "host", .initfn = aarch64_host_initfn }, 763 #endif 764 }; 765 766 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 767 { 768 ARMCPU *cpu = ARM_CPU(obj); 769 770 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 771 } 772 773 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 774 { 775 ARMCPU *cpu = ARM_CPU(obj); 776 777 /* At this time, this property is only allowed if KVM is enabled. This 778 * restriction allows us to avoid fixing up functionality that assumes a 779 * uniform execution state like do_interrupt. 780 */ 781 if (value == false) { 782 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 783 error_setg(errp, "'aarch64' feature cannot be disabled " 784 "unless KVM is enabled and 32-bit EL1 " 785 "is supported"); 786 return; 787 } 788 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 789 } else { 790 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 791 } 792 } 793 794 static void aarch64_cpu_finalizefn(Object *obj) 795 { 796 } 797 798 static const gchar *aarch64_gdb_arch_name(CPUState *cs) 799 { 800 return "aarch64"; 801 } 802 803 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 804 { 805 CPUClass *cc = CPU_CLASS(oc); 806 807 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 808 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 809 cc->gdb_core_xml_file = "aarch64-core.xml"; 810 cc->gdb_arch_name = aarch64_gdb_arch_name; 811 812 object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, 813 aarch64_cpu_set_aarch64); 814 object_class_property_set_description(oc, "aarch64", 815 "Set on/off to enable/disable aarch64 " 816 "execution state "); 817 } 818 819 static void aarch64_cpu_instance_init(Object *obj) 820 { 821 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 822 823 acc->info->initfn(obj); 824 arm_cpu_post_init(obj); 825 } 826 827 static void cpu_register_class_init(ObjectClass *oc, void *data) 828 { 829 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 830 831 acc->info = data; 832 } 833 834 void aarch64_cpu_register(const ARMCPUInfo *info) 835 { 836 TypeInfo type_info = { 837 .parent = TYPE_AARCH64_CPU, 838 .instance_init = aarch64_cpu_instance_init, 839 .class_init = info->class_init ?: cpu_register_class_init, 840 .class_data = (void *)info, 841 }; 842 843 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 844 type_register(&type_info); 845 g_free((void *)type_info.name); 846 } 847 848 static const TypeInfo aarch64_cpu_type_info = { 849 .name = TYPE_AARCH64_CPU, 850 .parent = TYPE_ARM_CPU, 851 .instance_finalize = aarch64_cpu_finalizefn, 852 .abstract = true, 853 .class_init = aarch64_cpu_class_init, 854 }; 855 856 static void aarch64_cpu_register_types(void) 857 { 858 size_t i; 859 860 type_register_static(&aarch64_cpu_type_info); 861 862 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { 863 aarch64_cpu_register(&aarch64_cpus[i]); 864 } 865 } 866 867 type_init(aarch64_cpu_register_types) 868