1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #ifdef CONFIG_TCG 25 #include "hw/core/tcg-cpu-ops.h" 26 #endif /* CONFIG_TCG */ 27 #include "qemu/module.h" 28 #if !defined(CONFIG_USER_ONLY) 29 #include "hw/loader.h" 30 #endif 31 #include "sysemu/kvm.h" 32 #include "sysemu/hvf.h" 33 #include "kvm_arm.h" 34 #include "hvf_arm.h" 35 #include "qapi/visitor.h" 36 #include "hw/qdev-properties.h" 37 #include "internals.h" 38 39 40 static void aarch64_a57_initfn(Object *obj) 41 { 42 ARMCPU *cpu = ARM_CPU(obj); 43 44 cpu->dtb_compatible = "arm,cortex-a57"; 45 set_feature(&cpu->env, ARM_FEATURE_V8); 46 set_feature(&cpu->env, ARM_FEATURE_NEON); 47 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 48 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 49 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 50 set_feature(&cpu->env, ARM_FEATURE_EL2); 51 set_feature(&cpu->env, ARM_FEATURE_EL3); 52 set_feature(&cpu->env, ARM_FEATURE_PMU); 53 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 54 cpu->midr = 0x411fd070; 55 cpu->revidr = 0x00000000; 56 cpu->reset_fpsid = 0x41034070; 57 cpu->isar.mvfr0 = 0x10110222; 58 cpu->isar.mvfr1 = 0x12111111; 59 cpu->isar.mvfr2 = 0x00000043; 60 cpu->ctr = 0x8444c004; 61 cpu->reset_sctlr = 0x00c50838; 62 cpu->isar.id_pfr0 = 0x00000131; 63 cpu->isar.id_pfr1 = 0x00011011; 64 cpu->isar.id_dfr0 = 0x03010066; 65 cpu->id_afr0 = 0x00000000; 66 cpu->isar.id_mmfr0 = 0x10101105; 67 cpu->isar.id_mmfr1 = 0x40000000; 68 cpu->isar.id_mmfr2 = 0x01260000; 69 cpu->isar.id_mmfr3 = 0x02102211; 70 cpu->isar.id_isar0 = 0x02101110; 71 cpu->isar.id_isar1 = 0x13112111; 72 cpu->isar.id_isar2 = 0x21232042; 73 cpu->isar.id_isar3 = 0x01112131; 74 cpu->isar.id_isar4 = 0x00011142; 75 cpu->isar.id_isar5 = 0x00011121; 76 cpu->isar.id_isar6 = 0; 77 cpu->isar.id_aa64pfr0 = 0x00002222; 78 cpu->isar.id_aa64dfr0 = 0x10305106; 79 cpu->isar.id_aa64isar0 = 0x00011120; 80 cpu->isar.id_aa64mmfr0 = 0x00001124; 81 cpu->isar.dbgdidr = 0x3516d000; 82 cpu->clidr = 0x0a200023; 83 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 84 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 85 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 86 cpu->dcz_blocksize = 4; /* 64 bytes */ 87 cpu->gic_num_lrs = 4; 88 cpu->gic_vpribits = 5; 89 cpu->gic_vprebits = 5; 90 define_cortex_a72_a57_a53_cp_reginfo(cpu); 91 } 92 93 static void aarch64_a53_initfn(Object *obj) 94 { 95 ARMCPU *cpu = ARM_CPU(obj); 96 97 cpu->dtb_compatible = "arm,cortex-a53"; 98 set_feature(&cpu->env, ARM_FEATURE_V8); 99 set_feature(&cpu->env, ARM_FEATURE_NEON); 100 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 101 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 102 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 103 set_feature(&cpu->env, ARM_FEATURE_EL2); 104 set_feature(&cpu->env, ARM_FEATURE_EL3); 105 set_feature(&cpu->env, ARM_FEATURE_PMU); 106 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 107 cpu->midr = 0x410fd034; 108 cpu->revidr = 0x00000000; 109 cpu->reset_fpsid = 0x41034070; 110 cpu->isar.mvfr0 = 0x10110222; 111 cpu->isar.mvfr1 = 0x12111111; 112 cpu->isar.mvfr2 = 0x00000043; 113 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 114 cpu->reset_sctlr = 0x00c50838; 115 cpu->isar.id_pfr0 = 0x00000131; 116 cpu->isar.id_pfr1 = 0x00011011; 117 cpu->isar.id_dfr0 = 0x03010066; 118 cpu->id_afr0 = 0x00000000; 119 cpu->isar.id_mmfr0 = 0x10101105; 120 cpu->isar.id_mmfr1 = 0x40000000; 121 cpu->isar.id_mmfr2 = 0x01260000; 122 cpu->isar.id_mmfr3 = 0x02102211; 123 cpu->isar.id_isar0 = 0x02101110; 124 cpu->isar.id_isar1 = 0x13112111; 125 cpu->isar.id_isar2 = 0x21232042; 126 cpu->isar.id_isar3 = 0x01112131; 127 cpu->isar.id_isar4 = 0x00011142; 128 cpu->isar.id_isar5 = 0x00011121; 129 cpu->isar.id_isar6 = 0; 130 cpu->isar.id_aa64pfr0 = 0x00002222; 131 cpu->isar.id_aa64dfr0 = 0x10305106; 132 cpu->isar.id_aa64isar0 = 0x00011120; 133 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 134 cpu->isar.dbgdidr = 0x3516d000; 135 cpu->clidr = 0x0a200023; 136 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 137 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 138 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 139 cpu->dcz_blocksize = 4; /* 64 bytes */ 140 cpu->gic_num_lrs = 4; 141 cpu->gic_vpribits = 5; 142 cpu->gic_vprebits = 5; 143 define_cortex_a72_a57_a53_cp_reginfo(cpu); 144 } 145 146 static void aarch64_a72_initfn(Object *obj) 147 { 148 ARMCPU *cpu = ARM_CPU(obj); 149 150 cpu->dtb_compatible = "arm,cortex-a72"; 151 set_feature(&cpu->env, ARM_FEATURE_V8); 152 set_feature(&cpu->env, ARM_FEATURE_NEON); 153 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 154 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 155 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 156 set_feature(&cpu->env, ARM_FEATURE_EL2); 157 set_feature(&cpu->env, ARM_FEATURE_EL3); 158 set_feature(&cpu->env, ARM_FEATURE_PMU); 159 cpu->midr = 0x410fd083; 160 cpu->revidr = 0x00000000; 161 cpu->reset_fpsid = 0x41034080; 162 cpu->isar.mvfr0 = 0x10110222; 163 cpu->isar.mvfr1 = 0x12111111; 164 cpu->isar.mvfr2 = 0x00000043; 165 cpu->ctr = 0x8444c004; 166 cpu->reset_sctlr = 0x00c50838; 167 cpu->isar.id_pfr0 = 0x00000131; 168 cpu->isar.id_pfr1 = 0x00011011; 169 cpu->isar.id_dfr0 = 0x03010066; 170 cpu->id_afr0 = 0x00000000; 171 cpu->isar.id_mmfr0 = 0x10201105; 172 cpu->isar.id_mmfr1 = 0x40000000; 173 cpu->isar.id_mmfr2 = 0x01260000; 174 cpu->isar.id_mmfr3 = 0x02102211; 175 cpu->isar.id_isar0 = 0x02101110; 176 cpu->isar.id_isar1 = 0x13112111; 177 cpu->isar.id_isar2 = 0x21232042; 178 cpu->isar.id_isar3 = 0x01112131; 179 cpu->isar.id_isar4 = 0x00011142; 180 cpu->isar.id_isar5 = 0x00011121; 181 cpu->isar.id_aa64pfr0 = 0x00002222; 182 cpu->isar.id_aa64dfr0 = 0x10305106; 183 cpu->isar.id_aa64isar0 = 0x00011120; 184 cpu->isar.id_aa64mmfr0 = 0x00001124; 185 cpu->isar.dbgdidr = 0x3516d000; 186 cpu->clidr = 0x0a200023; 187 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 188 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 189 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ 190 cpu->dcz_blocksize = 4; /* 64 bytes */ 191 cpu->gic_num_lrs = 4; 192 cpu->gic_vpribits = 5; 193 cpu->gic_vprebits = 5; 194 define_cortex_a72_a57_a53_cp_reginfo(cpu); 195 } 196 197 static void aarch64_a76_initfn(Object *obj) 198 { 199 ARMCPU *cpu = ARM_CPU(obj); 200 201 cpu->dtb_compatible = "arm,cortex-a76"; 202 set_feature(&cpu->env, ARM_FEATURE_V8); 203 set_feature(&cpu->env, ARM_FEATURE_NEON); 204 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 205 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 206 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 207 set_feature(&cpu->env, ARM_FEATURE_EL2); 208 set_feature(&cpu->env, ARM_FEATURE_EL3); 209 set_feature(&cpu->env, ARM_FEATURE_PMU); 210 211 /* Ordered by B2.4 AArch64 registers by functional group */ 212 cpu->clidr = 0x82000023; 213 cpu->ctr = 0x8444C004; 214 cpu->dcz_blocksize = 4; 215 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; 216 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 217 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 218 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; 219 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 220 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 221 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 222 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; 223 cpu->id_afr0 = 0x00000000; 224 cpu->isar.id_dfr0 = 0x04010088; 225 cpu->isar.id_isar0 = 0x02101110; 226 cpu->isar.id_isar1 = 0x13112111; 227 cpu->isar.id_isar2 = 0x21232042; 228 cpu->isar.id_isar3 = 0x01112131; 229 cpu->isar.id_isar4 = 0x00010142; 230 cpu->isar.id_isar5 = 0x01011121; 231 cpu->isar.id_isar6 = 0x00000010; 232 cpu->isar.id_mmfr0 = 0x10201105; 233 cpu->isar.id_mmfr1 = 0x40000000; 234 cpu->isar.id_mmfr2 = 0x01260000; 235 cpu->isar.id_mmfr3 = 0x02122211; 236 cpu->isar.id_mmfr4 = 0x00021110; 237 cpu->isar.id_pfr0 = 0x10010131; 238 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 239 cpu->isar.id_pfr2 = 0x00000011; 240 cpu->midr = 0x414fd0b1; /* r4p1 */ 241 cpu->revidr = 0; 242 243 /* From B2.18 CCSIDR_EL1 */ 244 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 245 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 246 cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ 247 248 /* From B2.93 SCTLR_EL3 */ 249 cpu->reset_sctlr = 0x30c50838; 250 251 /* From B4.23 ICH_VTR_EL2 */ 252 cpu->gic_num_lrs = 4; 253 cpu->gic_vpribits = 5; 254 cpu->gic_vprebits = 5; 255 256 /* From B5.1 AdvSIMD AArch64 register summary */ 257 cpu->isar.mvfr0 = 0x10110222; 258 cpu->isar.mvfr1 = 0x13211111; 259 cpu->isar.mvfr2 = 0x00000043; 260 } 261 262 static void aarch64_neoverse_n1_initfn(Object *obj) 263 { 264 ARMCPU *cpu = ARM_CPU(obj); 265 266 cpu->dtb_compatible = "arm,neoverse-n1"; 267 set_feature(&cpu->env, ARM_FEATURE_V8); 268 set_feature(&cpu->env, ARM_FEATURE_NEON); 269 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 270 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 271 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 272 set_feature(&cpu->env, ARM_FEATURE_EL2); 273 set_feature(&cpu->env, ARM_FEATURE_EL3); 274 set_feature(&cpu->env, ARM_FEATURE_PMU); 275 276 /* Ordered by B2.4 AArch64 registers by functional group */ 277 cpu->clidr = 0x82000023; 278 cpu->ctr = 0x8444c004; 279 cpu->dcz_blocksize = 4; 280 cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; 281 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 282 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 283 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; 284 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 285 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 286 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 287 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; 288 cpu->id_afr0 = 0x00000000; 289 cpu->isar.id_dfr0 = 0x04010088; 290 cpu->isar.id_isar0 = 0x02101110; 291 cpu->isar.id_isar1 = 0x13112111; 292 cpu->isar.id_isar2 = 0x21232042; 293 cpu->isar.id_isar3 = 0x01112131; 294 cpu->isar.id_isar4 = 0x00010142; 295 cpu->isar.id_isar5 = 0x01011121; 296 cpu->isar.id_isar6 = 0x00000010; 297 cpu->isar.id_mmfr0 = 0x10201105; 298 cpu->isar.id_mmfr1 = 0x40000000; 299 cpu->isar.id_mmfr2 = 0x01260000; 300 cpu->isar.id_mmfr3 = 0x02122211; 301 cpu->isar.id_mmfr4 = 0x00021110; 302 cpu->isar.id_pfr0 = 0x10010131; 303 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 304 cpu->isar.id_pfr2 = 0x00000011; 305 cpu->midr = 0x414fd0c1; /* r4p1 */ 306 cpu->revidr = 0; 307 308 /* From B2.23 CCSIDR_EL1 */ 309 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 310 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 311 cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ 312 313 /* From B2.98 SCTLR_EL3 */ 314 cpu->reset_sctlr = 0x30c50838; 315 316 /* From B4.23 ICH_VTR_EL2 */ 317 cpu->gic_num_lrs = 4; 318 cpu->gic_vpribits = 5; 319 cpu->gic_vprebits = 5; 320 321 /* From B5.1 AdvSIMD AArch64 register summary */ 322 cpu->isar.mvfr0 = 0x10110222; 323 cpu->isar.mvfr1 = 0x13211111; 324 cpu->isar.mvfr2 = 0x00000043; 325 } 326 327 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) 328 { 329 /* 330 * If any vector lengths are explicitly enabled with sve<N> properties, 331 * then all other lengths are implicitly disabled. If sve-max-vq is 332 * specified then it is the same as explicitly enabling all lengths 333 * up to and including the specified maximum, which means all larger 334 * lengths will be implicitly disabled. If no sve<N> properties 335 * are enabled and sve-max-vq is not specified, then all lengths not 336 * explicitly disabled will be enabled. Additionally, all power-of-two 337 * vector lengths less than the maximum enabled length will be 338 * automatically enabled and all vector lengths larger than the largest 339 * disabled power-of-two vector length will be automatically disabled. 340 * Errors are generated if the user provided input that interferes with 341 * any of the above. Finally, if SVE is not disabled, then at least one 342 * vector length must be enabled. 343 */ 344 DECLARE_BITMAP(tmp, ARM_MAX_VQ); 345 uint32_t vq, max_vq = 0; 346 347 /* 348 * CPU models specify a set of supported vector lengths which are 349 * enabled by default. Attempting to enable any vector length not set 350 * in the supported bitmap results in an error. When KVM is enabled we 351 * fetch the supported bitmap from the host. 352 */ 353 if (kvm_enabled() && kvm_arm_sve_supported()) { 354 kvm_arm_sve_get_vls(CPU(cpu), cpu->sve_vq_supported); 355 } else if (kvm_enabled()) { 356 assert(!cpu_isar_feature(aa64_sve, cpu)); 357 } 358 359 /* 360 * Process explicit sve<N> properties. 361 * From the properties, sve_vq_map<N> implies sve_vq_init<N>. 362 * Check first for any sve<N> enabled. 363 */ 364 if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) { 365 max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; 366 367 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { 368 error_setg(errp, "cannot enable sve%d", max_vq * 128); 369 error_append_hint(errp, "sve%d is larger than the maximum vector " 370 "length, sve-max-vq=%d (%d bits)\n", 371 max_vq * 128, cpu->sve_max_vq, 372 cpu->sve_max_vq * 128); 373 return; 374 } 375 376 if (kvm_enabled()) { 377 /* 378 * For KVM we have to automatically enable all supported unitialized 379 * lengths, even when the smaller lengths are not all powers-of-two. 380 */ 381 bitmap_andnot(tmp, cpu->sve_vq_supported, cpu->sve_vq_init, max_vq); 382 bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); 383 } else { 384 /* Propagate enabled bits down through required powers-of-two. */ 385 for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { 386 if (!test_bit(vq - 1, cpu->sve_vq_init)) { 387 set_bit(vq - 1, cpu->sve_vq_map); 388 } 389 } 390 } 391 } else if (cpu->sve_max_vq == 0) { 392 /* 393 * No explicit bits enabled, and no implicit bits from sve-max-vq. 394 */ 395 if (!cpu_isar_feature(aa64_sve, cpu)) { 396 /* SVE is disabled and so are all vector lengths. Good. */ 397 return; 398 } 399 400 if (kvm_enabled()) { 401 /* Disabling a supported length disables all larger lengths. */ 402 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 403 if (test_bit(vq - 1, cpu->sve_vq_init) && 404 test_bit(vq - 1, cpu->sve_vq_supported)) { 405 break; 406 } 407 } 408 } else { 409 /* Disabling a power-of-two disables all larger lengths. */ 410 for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) { 411 if (test_bit(vq - 1, cpu->sve_vq_init)) { 412 break; 413 } 414 } 415 } 416 417 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 418 bitmap_andnot(cpu->sve_vq_map, cpu->sve_vq_supported, 419 cpu->sve_vq_init, max_vq); 420 if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) { 421 error_setg(errp, "cannot disable sve%d", vq * 128); 422 error_append_hint(errp, "Disabling sve%d results in all " 423 "vector lengths being disabled.\n", 424 vq * 128); 425 error_append_hint(errp, "With SVE enabled, at least one " 426 "vector length must be enabled.\n"); 427 return; 428 } 429 430 max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1; 431 } 432 433 /* 434 * Process the sve-max-vq property. 435 * Note that we know from the above that no bit above 436 * sve-max-vq is currently set. 437 */ 438 if (cpu->sve_max_vq != 0) { 439 max_vq = cpu->sve_max_vq; 440 441 if (!test_bit(max_vq - 1, cpu->sve_vq_map) && 442 test_bit(max_vq - 1, cpu->sve_vq_init)) { 443 error_setg(errp, "cannot disable sve%d", max_vq * 128); 444 error_append_hint(errp, "The maximum vector length must be " 445 "enabled, sve-max-vq=%d (%d bits)\n", 446 max_vq, max_vq * 128); 447 return; 448 } 449 450 /* Set all bits not explicitly set within sve-max-vq. */ 451 bitmap_complement(tmp, cpu->sve_vq_init, max_vq); 452 bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); 453 } 454 455 /* 456 * We should know what max-vq is now. Also, as we're done 457 * manipulating sve-vq-map, we ensure any bits above max-vq 458 * are clear, just in case anybody looks. 459 */ 460 assert(max_vq != 0); 461 bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq); 462 463 /* Ensure the set of lengths matches what is supported. */ 464 bitmap_xor(tmp, cpu->sve_vq_map, cpu->sve_vq_supported, max_vq); 465 if (!bitmap_empty(tmp, max_vq)) { 466 vq = find_last_bit(tmp, max_vq) + 1; 467 if (test_bit(vq - 1, cpu->sve_vq_map)) { 468 if (cpu->sve_max_vq) { 469 error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq); 470 error_append_hint(errp, "This CPU does not support " 471 "the vector length %d-bits.\n", vq * 128); 472 error_append_hint(errp, "It may not be possible to use " 473 "sve-max-vq with this CPU. Try " 474 "using only sve<N> properties.\n"); 475 } else { 476 error_setg(errp, "cannot enable sve%d", vq * 128); 477 error_append_hint(errp, "This CPU does not support " 478 "the vector length %d-bits.\n", vq * 128); 479 } 480 return; 481 } else { 482 if (kvm_enabled()) { 483 error_setg(errp, "cannot disable sve%d", vq * 128); 484 error_append_hint(errp, "The KVM host requires all " 485 "supported vector lengths smaller " 486 "than %d bits to also be enabled.\n", 487 max_vq * 128); 488 return; 489 } else { 490 /* Ensure all required powers-of-two are enabled. */ 491 for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { 492 if (!test_bit(vq - 1, cpu->sve_vq_map)) { 493 error_setg(errp, "cannot disable sve%d", vq * 128); 494 error_append_hint(errp, "sve%d is required as it " 495 "is a power-of-two length smaller " 496 "than the maximum, sve%d\n", 497 vq * 128, max_vq * 128); 498 return; 499 } 500 } 501 } 502 } 503 } 504 505 /* 506 * Now that we validated all our vector lengths, the only question 507 * left to answer is if we even want SVE at all. 508 */ 509 if (!cpu_isar_feature(aa64_sve, cpu)) { 510 error_setg(errp, "cannot enable sve%d", max_vq * 128); 511 error_append_hint(errp, "SVE must be enabled to enable vector " 512 "lengths.\n"); 513 error_append_hint(errp, "Add sve=on to the CPU property list.\n"); 514 return; 515 } 516 517 /* From now on sve_max_vq is the actual maximum supported length. */ 518 cpu->sve_max_vq = max_vq; 519 } 520 521 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, 522 void *opaque, Error **errp) 523 { 524 ARMCPU *cpu = ARM_CPU(obj); 525 uint32_t value; 526 527 /* All vector lengths are disabled when SVE is off. */ 528 if (!cpu_isar_feature(aa64_sve, cpu)) { 529 value = 0; 530 } else { 531 value = cpu->sve_max_vq; 532 } 533 visit_type_uint32(v, name, &value, errp); 534 } 535 536 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, 537 void *opaque, Error **errp) 538 { 539 ARMCPU *cpu = ARM_CPU(obj); 540 uint32_t max_vq; 541 542 if (!visit_type_uint32(v, name, &max_vq, errp)) { 543 return; 544 } 545 546 if (kvm_enabled() && !kvm_arm_sve_supported()) { 547 error_setg(errp, "cannot set sve-max-vq"); 548 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 549 return; 550 } 551 552 if (max_vq == 0 || max_vq > ARM_MAX_VQ) { 553 error_setg(errp, "unsupported SVE vector length"); 554 error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", 555 ARM_MAX_VQ); 556 return; 557 } 558 559 cpu->sve_max_vq = max_vq; 560 } 561 562 /* 563 * Note that cpu_arm_get/set_sve_vq cannot use the simpler 564 * object_property_add_bool interface because they make use 565 * of the contents of "name" to determine which bit on which 566 * to operate. 567 */ 568 static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, 569 void *opaque, Error **errp) 570 { 571 ARMCPU *cpu = ARM_CPU(obj); 572 uint32_t vq = atoi(&name[3]) / 128; 573 bool value; 574 575 /* All vector lengths are disabled when SVE is off. */ 576 if (!cpu_isar_feature(aa64_sve, cpu)) { 577 value = false; 578 } else { 579 value = test_bit(vq - 1, cpu->sve_vq_map); 580 } 581 visit_type_bool(v, name, &value, errp); 582 } 583 584 static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, 585 void *opaque, Error **errp) 586 { 587 ARMCPU *cpu = ARM_CPU(obj); 588 uint32_t vq = atoi(&name[3]) / 128; 589 bool value; 590 591 if (!visit_type_bool(v, name, &value, errp)) { 592 return; 593 } 594 595 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 596 error_setg(errp, "cannot enable %s", name); 597 error_append_hint(errp, "SVE not supported by KVM on this host\n"); 598 return; 599 } 600 601 if (value) { 602 set_bit(vq - 1, cpu->sve_vq_map); 603 } else { 604 clear_bit(vq - 1, cpu->sve_vq_map); 605 } 606 set_bit(vq - 1, cpu->sve_vq_init); 607 } 608 609 static bool cpu_arm_get_sve(Object *obj, Error **errp) 610 { 611 ARMCPU *cpu = ARM_CPU(obj); 612 return cpu_isar_feature(aa64_sve, cpu); 613 } 614 615 static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) 616 { 617 ARMCPU *cpu = ARM_CPU(obj); 618 uint64_t t; 619 620 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 621 error_setg(errp, "'sve' feature not supported by KVM on this host"); 622 return; 623 } 624 625 t = cpu->isar.id_aa64pfr0; 626 t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); 627 cpu->isar.id_aa64pfr0 = t; 628 } 629 630 #ifdef CONFIG_USER_ONLY 631 /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ 632 static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v, 633 const char *name, void *opaque, 634 Error **errp) 635 { 636 ARMCPU *cpu = ARM_CPU(obj); 637 int32_t default_len, default_vq, remainder; 638 639 if (!visit_type_int32(v, name, &default_len, errp)) { 640 return; 641 } 642 643 /* Undocumented, but the kernel allows -1 to indicate "maximum". */ 644 if (default_len == -1) { 645 cpu->sve_default_vq = ARM_MAX_VQ; 646 return; 647 } 648 649 default_vq = default_len / 16; 650 remainder = default_len % 16; 651 652 /* 653 * Note that the 512 max comes from include/uapi/asm/sve_context.h 654 * and is the maximum architectural width of ZCR_ELx.LEN. 655 */ 656 if (remainder || default_vq < 1 || default_vq > 512) { 657 error_setg(errp, "cannot set sve-default-vector-length"); 658 if (remainder) { 659 error_append_hint(errp, "Vector length not a multiple of 16\n"); 660 } else if (default_vq < 1) { 661 error_append_hint(errp, "Vector length smaller than 16\n"); 662 } else { 663 error_append_hint(errp, "Vector length larger than %d\n", 664 512 * 16); 665 } 666 return; 667 } 668 669 cpu->sve_default_vq = default_vq; 670 } 671 672 static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v, 673 const char *name, void *opaque, 674 Error **errp) 675 { 676 ARMCPU *cpu = ARM_CPU(obj); 677 int32_t value = cpu->sve_default_vq * 16; 678 679 visit_type_int32(v, name, &value, errp); 680 } 681 #endif 682 683 void aarch64_add_sve_properties(Object *obj) 684 { 685 uint32_t vq; 686 687 object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); 688 689 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 690 char name[8]; 691 sprintf(name, "sve%d", vq * 128); 692 object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, 693 cpu_arm_set_sve_vq, NULL, NULL); 694 } 695 696 #ifdef CONFIG_USER_ONLY 697 /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ 698 object_property_add(obj, "sve-default-vector-length", "int32", 699 cpu_arm_get_sve_default_vec_len, 700 cpu_arm_set_sve_default_vec_len, NULL, NULL); 701 #endif 702 } 703 704 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) 705 { 706 int arch_val = 0, impdef_val = 0; 707 uint64_t t; 708 709 /* Exit early if PAuth is enabled, and fall through to disable it */ 710 if ((kvm_enabled() || hvf_enabled()) && cpu->prop_pauth) { 711 if (!cpu_isar_feature(aa64_pauth, cpu)) { 712 error_setg(errp, "'pauth' feature not supported by %s on this host", 713 kvm_enabled() ? "KVM" : "hvf"); 714 } 715 716 return; 717 } 718 719 /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ 720 if (cpu->prop_pauth) { 721 if (cpu->prop_pauth_impdef) { 722 impdef_val = 1; 723 } else { 724 arch_val = 1; 725 } 726 } else if (cpu->prop_pauth_impdef) { 727 error_setg(errp, "cannot enable pauth-impdef without pauth"); 728 error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); 729 } 730 731 t = cpu->isar.id_aa64isar1; 732 t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); 733 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); 734 t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); 735 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); 736 cpu->isar.id_aa64isar1 = t; 737 } 738 739 static Property arm_cpu_pauth_property = 740 DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); 741 static Property arm_cpu_pauth_impdef_property = 742 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); 743 744 void aarch64_add_pauth_properties(Object *obj) 745 { 746 ARMCPU *cpu = ARM_CPU(obj); 747 748 /* Default to PAUTH on, with the architected algorithm on TCG. */ 749 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); 750 if (kvm_enabled() || hvf_enabled()) { 751 /* 752 * Mirror PAuth support from the probed sysregs back into the 753 * property for KVM or hvf. Is it just a bit backward? Yes it is! 754 * Note that prop_pauth is true whether the host CPU supports the 755 * architected QARMA5 algorithm or the IMPDEF one. We don't 756 * provide the separate pauth-impdef property for KVM or hvf, 757 * only for TCG. 758 */ 759 cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); 760 } else { 761 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); 762 } 763 } 764 765 static Property arm_cpu_lpa2_property = 766 DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); 767 768 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) 769 { 770 uint64_t t; 771 772 /* 773 * We only install the property for tcg -cpu max; this is the 774 * only situation in which the cpu field can be true. 775 */ 776 if (!cpu->prop_lpa2) { 777 return; 778 } 779 780 t = cpu->isar.id_aa64mmfr0; 781 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */ 782 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */ 783 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */ 784 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */ 785 cpu->isar.id_aa64mmfr0 = t; 786 } 787 788 static void aarch64_host_initfn(Object *obj) 789 { 790 #if defined(CONFIG_KVM) 791 ARMCPU *cpu = ARM_CPU(obj); 792 kvm_arm_set_cpu_features_from_host(cpu); 793 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 794 aarch64_add_sve_properties(obj); 795 aarch64_add_pauth_properties(obj); 796 } 797 #elif defined(CONFIG_HVF) 798 ARMCPU *cpu = ARM_CPU(obj); 799 hvf_arm_set_cpu_features_from_host(cpu); 800 aarch64_add_pauth_properties(obj); 801 #else 802 g_assert_not_reached(); 803 #endif 804 } 805 806 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 807 * otherwise, a CPU with as many features enabled as our emulation supports. 808 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; 809 * this only needs to handle 64 bits. 810 */ 811 static void aarch64_max_initfn(Object *obj) 812 { 813 ARMCPU *cpu = ARM_CPU(obj); 814 uint64_t t; 815 uint32_t u; 816 817 if (kvm_enabled() || hvf_enabled()) { 818 /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ 819 aarch64_host_initfn(obj); 820 return; 821 } 822 823 /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */ 824 825 aarch64_a57_initfn(obj); 826 827 /* 828 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real 829 * one and try to apply errata workarounds or use impdef features we 830 * don't provide. 831 * An IMPLEMENTER field of 0 means "reserved for software use"; 832 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers 833 * to see which features are present"; 834 * the VARIANT, PARTNUM and REVISION fields are all implementation 835 * defined and we choose to define PARTNUM just in case guest 836 * code needs to distinguish this QEMU CPU from other software 837 * implementations, though this shouldn't be needed. 838 */ 839 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); 840 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); 841 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); 842 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); 843 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); 844 cpu->midr = t; 845 846 /* 847 * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS} 848 * are zero. 849 */ 850 u = cpu->clidr; 851 u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); 852 u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0); 853 cpu->clidr = u; 854 855 t = cpu->isar.id_aa64isar0; 856 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ 857 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ 858 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ 859 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); 860 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ 861 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ 862 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ 863 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ 864 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ 865 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ 866 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ 867 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ 868 t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ 869 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ 870 cpu->isar.id_aa64isar0 = t; 871 872 t = cpu->isar.id_aa64isar1; 873 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ 874 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ 875 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ 876 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ 877 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ 878 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ 879 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ 880 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ 881 t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ 882 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ 883 cpu->isar.id_aa64isar1 = t; 884 885 t = cpu->isar.id_aa64pfr0; 886 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ 887 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ 888 t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ 889 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); 890 t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ 891 t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ 892 t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ 893 t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ 894 cpu->isar.id_aa64pfr0 = t; 895 896 t = cpu->isar.id_aa64pfr1; 897 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ 898 t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ 899 /* 900 * Begin with full support for MTE. This will be downgraded to MTE=0 901 * during realize if the board provides no tag memory, much like 902 * we do for EL2 with the virtualization=on property. 903 */ 904 t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ 905 t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ 906 cpu->isar.id_aa64pfr1 = t; 907 908 t = cpu->isar.id_aa64mmfr0; 909 t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ 910 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ 911 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ 912 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ 913 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ 914 cpu->isar.id_aa64mmfr0 = t; 915 916 t = cpu->isar.id_aa64mmfr1; 917 t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ 918 t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ 919 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ 920 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ 921 t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ 922 t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ 923 cpu->isar.id_aa64mmfr1 = t; 924 925 t = cpu->isar.id_aa64mmfr2; 926 t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ 927 t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ 928 t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ 929 t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ 930 t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ 931 t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ 932 t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ 933 t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ 934 t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ 935 cpu->isar.id_aa64mmfr2 = t; 936 937 t = cpu->isar.id_aa64zfr0; 938 t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); 939 t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ 940 t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ 941 t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ 942 t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ 943 t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ 944 t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ 945 t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ 946 t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ 947 cpu->isar.id_aa64zfr0 = t; 948 949 t = cpu->isar.id_aa64dfr0; 950 t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ 951 t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ 952 cpu->isar.id_aa64dfr0 = t; 953 954 /* Replicate the same data to the 32-bit id registers. */ 955 aa32_max_features(cpu); 956 957 #ifdef CONFIG_USER_ONLY 958 /* 959 * For usermode -cpu max we can use a larger and more efficient DCZ 960 * blocksize since we don't have to follow what the hardware does. 961 */ 962 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 963 cpu->dcz_blocksize = 7; /* 512 bytes */ 964 #endif 965 966 bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ); 967 968 aarch64_add_pauth_properties(obj); 969 aarch64_add_sve_properties(obj); 970 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, 971 cpu_max_set_sve_max_vq, NULL, NULL); 972 qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); 973 } 974 975 static void aarch64_a64fx_initfn(Object *obj) 976 { 977 ARMCPU *cpu = ARM_CPU(obj); 978 979 cpu->dtb_compatible = "arm,a64fx"; 980 set_feature(&cpu->env, ARM_FEATURE_V8); 981 set_feature(&cpu->env, ARM_FEATURE_NEON); 982 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 983 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 984 set_feature(&cpu->env, ARM_FEATURE_EL2); 985 set_feature(&cpu->env, ARM_FEATURE_EL3); 986 set_feature(&cpu->env, ARM_FEATURE_PMU); 987 cpu->midr = 0x461f0010; 988 cpu->revidr = 0x00000000; 989 cpu->ctr = 0x86668006; 990 cpu->reset_sctlr = 0x30000180; 991 cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */ 992 cpu->isar.id_aa64pfr1 = 0x0000000000000000; 993 cpu->isar.id_aa64dfr0 = 0x0000000010305408; 994 cpu->isar.id_aa64dfr1 = 0x0000000000000000; 995 cpu->id_aa64afr0 = 0x0000000000000000; 996 cpu->id_aa64afr1 = 0x0000000000000000; 997 cpu->isar.id_aa64mmfr0 = 0x0000000000001122; 998 cpu->isar.id_aa64mmfr1 = 0x0000000011212100; 999 cpu->isar.id_aa64mmfr2 = 0x0000000000001011; 1000 cpu->isar.id_aa64isar0 = 0x0000000010211120; 1001 cpu->isar.id_aa64isar1 = 0x0000000000010001; 1002 cpu->isar.id_aa64zfr0 = 0x0000000000000000; 1003 cpu->clidr = 0x0000000080000023; 1004 cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */ 1005 cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */ 1006 cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */ 1007 cpu->dcz_blocksize = 6; /* 256 bytes */ 1008 cpu->gic_num_lrs = 4; 1009 cpu->gic_vpribits = 5; 1010 cpu->gic_vprebits = 5; 1011 1012 /* Suppport of A64FX's vector length are 128,256 and 512bit only */ 1013 aarch64_add_sve_properties(obj); 1014 bitmap_zero(cpu->sve_vq_supported, ARM_MAX_VQ); 1015 set_bit(0, cpu->sve_vq_supported); /* 128bit */ 1016 set_bit(1, cpu->sve_vq_supported); /* 256bit */ 1017 set_bit(3, cpu->sve_vq_supported); /* 512bit */ 1018 1019 /* TODO: Add A64FX specific HPC extension registers */ 1020 } 1021 1022 static const ARMCPUInfo aarch64_cpus[] = { 1023 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 1024 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 1025 { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, 1026 { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, 1027 { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, 1028 { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, 1029 { .name = "max", .initfn = aarch64_max_initfn }, 1030 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1031 { .name = "host", .initfn = aarch64_host_initfn }, 1032 #endif 1033 }; 1034 1035 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 1036 { 1037 ARMCPU *cpu = ARM_CPU(obj); 1038 1039 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 1040 } 1041 1042 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 1043 { 1044 ARMCPU *cpu = ARM_CPU(obj); 1045 1046 /* At this time, this property is only allowed if KVM is enabled. This 1047 * restriction allows us to avoid fixing up functionality that assumes a 1048 * uniform execution state like do_interrupt. 1049 */ 1050 if (value == false) { 1051 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 1052 error_setg(errp, "'aarch64' feature cannot be disabled " 1053 "unless KVM is enabled and 32-bit EL1 " 1054 "is supported"); 1055 return; 1056 } 1057 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 1058 } else { 1059 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 1060 } 1061 } 1062 1063 static void aarch64_cpu_finalizefn(Object *obj) 1064 { 1065 } 1066 1067 static gchar *aarch64_gdb_arch_name(CPUState *cs) 1068 { 1069 return g_strdup("aarch64"); 1070 } 1071 1072 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 1073 { 1074 CPUClass *cc = CPU_CLASS(oc); 1075 1076 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 1077 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 1078 cc->gdb_num_core_regs = 34; 1079 cc->gdb_core_xml_file = "aarch64-core.xml"; 1080 cc->gdb_arch_name = aarch64_gdb_arch_name; 1081 1082 object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, 1083 aarch64_cpu_set_aarch64); 1084 object_class_property_set_description(oc, "aarch64", 1085 "Set on/off to enable/disable aarch64 " 1086 "execution state "); 1087 } 1088 1089 static void aarch64_cpu_instance_init(Object *obj) 1090 { 1091 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 1092 1093 acc->info->initfn(obj); 1094 arm_cpu_post_init(obj); 1095 } 1096 1097 static void cpu_register_class_init(ObjectClass *oc, void *data) 1098 { 1099 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1100 1101 acc->info = data; 1102 } 1103 1104 void aarch64_cpu_register(const ARMCPUInfo *info) 1105 { 1106 TypeInfo type_info = { 1107 .parent = TYPE_AARCH64_CPU, 1108 .instance_size = sizeof(ARMCPU), 1109 .instance_init = aarch64_cpu_instance_init, 1110 .class_size = sizeof(ARMCPUClass), 1111 .class_init = info->class_init ?: cpu_register_class_init, 1112 .class_data = (void *)info, 1113 }; 1114 1115 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1116 type_register(&type_info); 1117 g_free((void *)type_info.name); 1118 } 1119 1120 static const TypeInfo aarch64_cpu_type_info = { 1121 .name = TYPE_AARCH64_CPU, 1122 .parent = TYPE_ARM_CPU, 1123 .instance_size = sizeof(ARMCPU), 1124 .instance_finalize = aarch64_cpu_finalizefn, 1125 .abstract = true, 1126 .class_size = sizeof(AArch64CPUClass), 1127 .class_init = aarch64_cpu_class_init, 1128 }; 1129 1130 static void aarch64_cpu_register_types(void) 1131 { 1132 size_t i; 1133 1134 type_register_static(&aarch64_cpu_type_info); 1135 1136 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { 1137 aarch64_cpu_register(&aarch64_cpus[i]); 1138 } 1139 } 1140 1141 type_init(aarch64_cpu_register_types) 1142