1 /* 2 * QEMU AArch64 CPU 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "cpregs.h" 25 #include "qemu/module.h" 26 #include "sysemu/kvm.h" 27 #include "sysemu/hvf.h" 28 #include "sysemu/qtest.h" 29 #include "sysemu/tcg.h" 30 #include "kvm_arm.h" 31 #include "hvf_arm.h" 32 #include "qapi/visitor.h" 33 #include "hw/qdev-properties.h" 34 #include "internals.h" 35 #include "cpu-features.h" 36 #include "cpregs.h" 37 38 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) 39 { 40 /* 41 * If any vector lengths are explicitly enabled with sve<N> properties, 42 * then all other lengths are implicitly disabled. If sve-max-vq is 43 * specified then it is the same as explicitly enabling all lengths 44 * up to and including the specified maximum, which means all larger 45 * lengths will be implicitly disabled. If no sve<N> properties 46 * are enabled and sve-max-vq is not specified, then all lengths not 47 * explicitly disabled will be enabled. Additionally, all power-of-two 48 * vector lengths less than the maximum enabled length will be 49 * automatically enabled and all vector lengths larger than the largest 50 * disabled power-of-two vector length will be automatically disabled. 51 * Errors are generated if the user provided input that interferes with 52 * any of the above. Finally, if SVE is not disabled, then at least one 53 * vector length must be enabled. 54 */ 55 uint32_t vq_map = cpu->sve_vq.map; 56 uint32_t vq_init = cpu->sve_vq.init; 57 uint32_t vq_supported; 58 uint32_t vq_mask = 0; 59 uint32_t tmp, vq, max_vq = 0; 60 61 /* 62 * CPU models specify a set of supported vector lengths which are 63 * enabled by default. Attempting to enable any vector length not set 64 * in the supported bitmap results in an error. When KVM is enabled we 65 * fetch the supported bitmap from the host. 66 */ 67 if (kvm_enabled()) { 68 if (kvm_arm_sve_supported()) { 69 cpu->sve_vq.supported = kvm_arm_sve_get_vls(cpu); 70 vq_supported = cpu->sve_vq.supported; 71 } else { 72 assert(!cpu_isar_feature(aa64_sve, cpu)); 73 vq_supported = 0; 74 } 75 } else { 76 vq_supported = cpu->sve_vq.supported; 77 } 78 79 /* 80 * Process explicit sve<N> properties. 81 * From the properties, sve_vq_map<N> implies sve_vq_init<N>. 82 * Check first for any sve<N> enabled. 83 */ 84 if (vq_map != 0) { 85 max_vq = 32 - clz32(vq_map); 86 vq_mask = MAKE_64BIT_MASK(0, max_vq); 87 88 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { 89 error_setg(errp, "cannot enable sve%d", max_vq * 128); 90 error_append_hint(errp, "sve%d is larger than the maximum vector " 91 "length, sve-max-vq=%d (%d bits)\n", 92 max_vq * 128, cpu->sve_max_vq, 93 cpu->sve_max_vq * 128); 94 return; 95 } 96 97 if (kvm_enabled()) { 98 /* 99 * For KVM we have to automatically enable all supported uninitialized 100 * lengths, even when the smaller lengths are not all powers-of-two. 101 */ 102 vq_map |= vq_supported & ~vq_init & vq_mask; 103 } else { 104 /* Propagate enabled bits down through required powers-of-two. */ 105 vq_map |= SVE_VQ_POW2_MAP & ~vq_init & vq_mask; 106 } 107 } else if (cpu->sve_max_vq == 0) { 108 /* 109 * No explicit bits enabled, and no implicit bits from sve-max-vq. 110 */ 111 if (!cpu_isar_feature(aa64_sve, cpu)) { 112 /* 113 * SVE is disabled and so are all vector lengths. Good. 114 * Disable all SVE extensions as well. 115 */ 116 cpu->isar.id_aa64zfr0 = 0; 117 return; 118 } 119 120 if (kvm_enabled()) { 121 /* Disabling a supported length disables all larger lengths. */ 122 tmp = vq_init & vq_supported; 123 } else { 124 /* Disabling a power-of-two disables all larger lengths. */ 125 tmp = vq_init & SVE_VQ_POW2_MAP; 126 } 127 vq = ctz32(tmp) + 1; 128 129 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; 130 vq_mask = max_vq > 0 ? MAKE_64BIT_MASK(0, max_vq) : 0; 131 vq_map = vq_supported & ~vq_init & vq_mask; 132 133 if (vq_map == 0) { 134 error_setg(errp, "cannot disable sve%d", vq * 128); 135 error_append_hint(errp, "Disabling sve%d results in all " 136 "vector lengths being disabled.\n", 137 vq * 128); 138 error_append_hint(errp, "With SVE enabled, at least one " 139 "vector length must be enabled.\n"); 140 return; 141 } 142 143 max_vq = 32 - clz32(vq_map); 144 vq_mask = MAKE_64BIT_MASK(0, max_vq); 145 } 146 147 /* 148 * Process the sve-max-vq property. 149 * Note that we know from the above that no bit above 150 * sve-max-vq is currently set. 151 */ 152 if (cpu->sve_max_vq != 0) { 153 max_vq = cpu->sve_max_vq; 154 vq_mask = MAKE_64BIT_MASK(0, max_vq); 155 156 if (vq_init & ~vq_map & (1 << (max_vq - 1))) { 157 error_setg(errp, "cannot disable sve%d", max_vq * 128); 158 error_append_hint(errp, "The maximum vector length must be " 159 "enabled, sve-max-vq=%d (%d bits)\n", 160 max_vq, max_vq * 128); 161 return; 162 } 163 164 /* Set all bits not explicitly set within sve-max-vq. */ 165 vq_map |= ~vq_init & vq_mask; 166 } 167 168 /* 169 * We should know what max-vq is now. Also, as we're done 170 * manipulating sve-vq-map, we ensure any bits above max-vq 171 * are clear, just in case anybody looks. 172 */ 173 assert(max_vq != 0); 174 assert(vq_mask != 0); 175 vq_map &= vq_mask; 176 177 /* Ensure the set of lengths matches what is supported. */ 178 tmp = vq_map ^ (vq_supported & vq_mask); 179 if (tmp) { 180 vq = 32 - clz32(tmp); 181 if (vq_map & (1 << (vq - 1))) { 182 if (cpu->sve_max_vq) { 183 error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq); 184 error_append_hint(errp, "This CPU does not support " 185 "the vector length %d-bits.\n", vq * 128); 186 error_append_hint(errp, "It may not be possible to use " 187 "sve-max-vq with this CPU. Try " 188 "using only sve<N> properties.\n"); 189 } else { 190 error_setg(errp, "cannot enable sve%d", vq * 128); 191 if (vq_supported) { 192 error_append_hint(errp, "This CPU does not support " 193 "the vector length %d-bits.\n", vq * 128); 194 } else { 195 error_append_hint(errp, "SVE not supported by KVM " 196 "on this host\n"); 197 } 198 } 199 return; 200 } else { 201 if (kvm_enabled()) { 202 error_setg(errp, "cannot disable sve%d", vq * 128); 203 error_append_hint(errp, "The KVM host requires all " 204 "supported vector lengths smaller " 205 "than %d bits to also be enabled.\n", 206 max_vq * 128); 207 return; 208 } else { 209 /* Ensure all required powers-of-two are enabled. */ 210 tmp = SVE_VQ_POW2_MAP & vq_mask & ~vq_map; 211 if (tmp) { 212 vq = 32 - clz32(tmp); 213 error_setg(errp, "cannot disable sve%d", vq * 128); 214 error_append_hint(errp, "sve%d is required as it " 215 "is a power-of-two length smaller " 216 "than the maximum, sve%d\n", 217 vq * 128, max_vq * 128); 218 return; 219 } 220 } 221 } 222 } 223 224 /* 225 * Now that we validated all our vector lengths, the only question 226 * left to answer is if we even want SVE at all. 227 */ 228 if (!cpu_isar_feature(aa64_sve, cpu)) { 229 error_setg(errp, "cannot enable sve%d", max_vq * 128); 230 error_append_hint(errp, "SVE must be enabled to enable vector " 231 "lengths.\n"); 232 error_append_hint(errp, "Add sve=on to the CPU property list.\n"); 233 return; 234 } 235 236 /* From now on sve_max_vq is the actual maximum supported length. */ 237 cpu->sve_max_vq = max_vq; 238 cpu->sve_vq.map = vq_map; 239 } 240 241 /* 242 * Note that cpu_arm_{get,set}_vq cannot use the simpler 243 * object_property_add_bool interface because they make use of the 244 * contents of "name" to determine which bit on which to operate. 245 */ 246 static void cpu_arm_get_vq(Object *obj, Visitor *v, const char *name, 247 void *opaque, Error **errp) 248 { 249 ARMCPU *cpu = ARM_CPU(obj); 250 ARMVQMap *vq_map = opaque; 251 uint32_t vq = atoi(&name[3]) / 128; 252 bool sve = vq_map == &cpu->sve_vq; 253 bool value; 254 255 /* All vector lengths are disabled when feature is off. */ 256 if (sve 257 ? !cpu_isar_feature(aa64_sve, cpu) 258 : !cpu_isar_feature(aa64_sme, cpu)) { 259 value = false; 260 } else { 261 value = extract32(vq_map->map, vq - 1, 1); 262 } 263 visit_type_bool(v, name, &value, errp); 264 } 265 266 static void cpu_arm_set_vq(Object *obj, Visitor *v, const char *name, 267 void *opaque, Error **errp) 268 { 269 ARMVQMap *vq_map = opaque; 270 uint32_t vq = atoi(&name[3]) / 128; 271 bool value; 272 273 if (!visit_type_bool(v, name, &value, errp)) { 274 return; 275 } 276 277 vq_map->map = deposit32(vq_map->map, vq - 1, 1, value); 278 vq_map->init |= 1 << (vq - 1); 279 } 280 281 static bool cpu_arm_get_sve(Object *obj, Error **errp) 282 { 283 ARMCPU *cpu = ARM_CPU(obj); 284 return cpu_isar_feature(aa64_sve, cpu); 285 } 286 287 static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) 288 { 289 ARMCPU *cpu = ARM_CPU(obj); 290 uint64_t t; 291 292 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { 293 error_setg(errp, "'sve' feature not supported by KVM on this host"); 294 return; 295 } 296 297 t = cpu->isar.id_aa64pfr0; 298 t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); 299 cpu->isar.id_aa64pfr0 = t; 300 } 301 302 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) 303 { 304 uint32_t vq_map = cpu->sme_vq.map; 305 uint32_t vq_init = cpu->sme_vq.init; 306 uint32_t vq_supported = cpu->sme_vq.supported; 307 uint32_t vq; 308 309 if (vq_map == 0) { 310 if (!cpu_isar_feature(aa64_sme, cpu)) { 311 cpu->isar.id_aa64smfr0 = 0; 312 return; 313 } 314 315 /* TODO: KVM will require limitations via SMCR_EL2. */ 316 vq_map = vq_supported & ~vq_init; 317 318 if (vq_map == 0) { 319 vq = ctz32(vq_supported) + 1; 320 error_setg(errp, "cannot disable sme%d", vq * 128); 321 error_append_hint(errp, "All SME vector lengths are disabled.\n"); 322 error_append_hint(errp, "With SME enabled, at least one " 323 "vector length must be enabled.\n"); 324 return; 325 } 326 } else { 327 if (!cpu_isar_feature(aa64_sme, cpu)) { 328 vq = 32 - clz32(vq_map); 329 error_setg(errp, "cannot enable sme%d", vq * 128); 330 error_append_hint(errp, "SME must be enabled to enable " 331 "vector lengths.\n"); 332 error_append_hint(errp, "Add sme=on to the CPU property list.\n"); 333 return; 334 } 335 /* TODO: KVM will require limitations via SMCR_EL2. */ 336 } 337 338 cpu->sme_vq.map = vq_map; 339 } 340 341 static bool cpu_arm_get_sme(Object *obj, Error **errp) 342 { 343 ARMCPU *cpu = ARM_CPU(obj); 344 return cpu_isar_feature(aa64_sme, cpu); 345 } 346 347 static void cpu_arm_set_sme(Object *obj, bool value, Error **errp) 348 { 349 ARMCPU *cpu = ARM_CPU(obj); 350 uint64_t t; 351 352 t = cpu->isar.id_aa64pfr1; 353 t = FIELD_DP64(t, ID_AA64PFR1, SME, value); 354 cpu->isar.id_aa64pfr1 = t; 355 } 356 357 static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp) 358 { 359 ARMCPU *cpu = ARM_CPU(obj); 360 return cpu_isar_feature(aa64_sme, cpu) && 361 cpu_isar_feature(aa64_sme_fa64, cpu); 362 } 363 364 static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp) 365 { 366 ARMCPU *cpu = ARM_CPU(obj); 367 uint64_t t; 368 369 t = cpu->isar.id_aa64smfr0; 370 t = FIELD_DP64(t, ID_AA64SMFR0, FA64, value); 371 cpu->isar.id_aa64smfr0 = t; 372 } 373 374 #ifdef CONFIG_USER_ONLY 375 /* Mirror linux /proc/sys/abi/{sve,sme}_default_vector_length. */ 376 static void cpu_arm_set_default_vec_len(Object *obj, Visitor *v, 377 const char *name, void *opaque, 378 Error **errp) 379 { 380 uint32_t *ptr_default_vq = opaque; 381 int32_t default_len, default_vq, remainder; 382 383 if (!visit_type_int32(v, name, &default_len, errp)) { 384 return; 385 } 386 387 /* Undocumented, but the kernel allows -1 to indicate "maximum". */ 388 if (default_len == -1) { 389 *ptr_default_vq = ARM_MAX_VQ; 390 return; 391 } 392 393 default_vq = default_len / 16; 394 remainder = default_len % 16; 395 396 /* 397 * Note that the 512 max comes from include/uapi/asm/sve_context.h 398 * and is the maximum architectural width of ZCR_ELx.LEN. 399 */ 400 if (remainder || default_vq < 1 || default_vq > 512) { 401 ARMCPU *cpu = ARM_CPU(obj); 402 const char *which = 403 (ptr_default_vq == &cpu->sve_default_vq ? "sve" : "sme"); 404 405 error_setg(errp, "cannot set %s-default-vector-length", which); 406 if (remainder) { 407 error_append_hint(errp, "Vector length not a multiple of 16\n"); 408 } else if (default_vq < 1) { 409 error_append_hint(errp, "Vector length smaller than 16\n"); 410 } else { 411 error_append_hint(errp, "Vector length larger than %d\n", 412 512 * 16); 413 } 414 return; 415 } 416 417 *ptr_default_vq = default_vq; 418 } 419 420 static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v, 421 const char *name, void *opaque, 422 Error **errp) 423 { 424 uint32_t *ptr_default_vq = opaque; 425 int32_t value = *ptr_default_vq * 16; 426 427 visit_type_int32(v, name, &value, errp); 428 } 429 #endif 430 431 void aarch64_add_sve_properties(Object *obj) 432 { 433 ARMCPU *cpu = ARM_CPU(obj); 434 uint32_t vq; 435 436 object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); 437 438 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { 439 char name[8]; 440 snprintf(name, sizeof(name), "sve%d", vq * 128); 441 object_property_add(obj, name, "bool", cpu_arm_get_vq, 442 cpu_arm_set_vq, NULL, &cpu->sve_vq); 443 } 444 445 #ifdef CONFIG_USER_ONLY 446 /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ 447 object_property_add(obj, "sve-default-vector-length", "int32", 448 cpu_arm_get_default_vec_len, 449 cpu_arm_set_default_vec_len, NULL, 450 &cpu->sve_default_vq); 451 #endif 452 } 453 454 void aarch64_add_sme_properties(Object *obj) 455 { 456 ARMCPU *cpu = ARM_CPU(obj); 457 uint32_t vq; 458 459 object_property_add_bool(obj, "sme", cpu_arm_get_sme, cpu_arm_set_sme); 460 object_property_add_bool(obj, "sme_fa64", cpu_arm_get_sme_fa64, 461 cpu_arm_set_sme_fa64); 462 463 for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) { 464 char name[8]; 465 snprintf(name, sizeof(name), "sme%d", vq * 128); 466 object_property_add(obj, name, "bool", cpu_arm_get_vq, 467 cpu_arm_set_vq, NULL, &cpu->sme_vq); 468 } 469 470 #ifdef CONFIG_USER_ONLY 471 /* Mirror linux /proc/sys/abi/sme_default_vector_length. */ 472 object_property_add(obj, "sme-default-vector-length", "int32", 473 cpu_arm_get_default_vec_len, 474 cpu_arm_set_default_vec_len, NULL, 475 &cpu->sme_default_vq); 476 #endif 477 } 478 479 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) 480 { 481 ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu); 482 uint64_t isar1, isar2; 483 484 /* 485 * These properties enable or disable Pauth as a whole, or change 486 * the pauth algorithm, but do not change the set of features that 487 * are present. We have saved a copy of those features above and 488 * will now place it into the field that chooses the algorithm. 489 * 490 * Begin by disabling all fields. 491 */ 492 isar1 = cpu->isar.id_aa64isar1; 493 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, 0); 494 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 0); 495 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, 0); 496 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0); 497 498 isar2 = cpu->isar.id_aa64isar2; 499 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0); 500 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0); 501 502 if (kvm_enabled() || hvf_enabled()) { 503 /* 504 * Exit early if PAuth is enabled and fall through to disable it. 505 * The algorithm selection properties are not present. 506 */ 507 if (cpu->prop_pauth) { 508 if (features == 0) { 509 error_setg(errp, "'pauth' feature not supported by " 510 "%s on this host", current_accel_name()); 511 } 512 return; 513 } 514 } else { 515 /* Pauth properties are only present when the model supports it. */ 516 if (features == 0) { 517 assert(!cpu->prop_pauth); 518 return; 519 } 520 521 if (cpu->prop_pauth) { 522 if (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) { 523 error_setg(errp, 524 "cannot enable both pauth-impdef and pauth-qarma3"); 525 return; 526 } 527 528 if (cpu->prop_pauth_impdef) { 529 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features); 530 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1); 531 } else if (cpu->prop_pauth_qarma3) { 532 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features); 533 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1); 534 } else { 535 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); 536 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); 537 } 538 } else if (cpu->prop_pauth_impdef || cpu->prop_pauth_qarma3) { 539 error_setg(errp, "cannot enable pauth-impdef or " 540 "pauth-qarma3 without pauth"); 541 error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); 542 } 543 } 544 545 cpu->isar.id_aa64isar1 = isar1; 546 cpu->isar.id_aa64isar2 = isar2; 547 } 548 549 static Property arm_cpu_pauth_property = 550 DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); 551 static Property arm_cpu_pauth_impdef_property = 552 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); 553 static Property arm_cpu_pauth_qarma3_property = 554 DEFINE_PROP_BOOL("pauth-qarma3", ARMCPU, prop_pauth_qarma3, false); 555 556 void aarch64_add_pauth_properties(Object *obj) 557 { 558 ARMCPU *cpu = ARM_CPU(obj); 559 560 /* Default to PAUTH on, with the architected algorithm on TCG. */ 561 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); 562 if (kvm_enabled() || hvf_enabled()) { 563 /* 564 * Mirror PAuth support from the probed sysregs back into the 565 * property for KVM or hvf. Is it just a bit backward? Yes it is! 566 * Note that prop_pauth is true whether the host CPU supports the 567 * architected QARMA5 algorithm or the IMPDEF one. We don't 568 * provide the separate pauth-impdef property for KVM or hvf, 569 * only for TCG. 570 */ 571 cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); 572 } else { 573 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); 574 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma3_property); 575 } 576 } 577 578 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) 579 { 580 uint64_t t; 581 582 /* 583 * We only install the property for tcg -cpu max; this is the 584 * only situation in which the cpu field can be true. 585 */ 586 if (!cpu->prop_lpa2) { 587 return; 588 } 589 590 t = cpu->isar.id_aa64mmfr0; 591 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */ 592 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */ 593 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */ 594 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */ 595 cpu->isar.id_aa64mmfr0 = t; 596 } 597 598 static void aarch64_a57_initfn(Object *obj) 599 { 600 ARMCPU *cpu = ARM_CPU(obj); 601 602 cpu->dtb_compatible = "arm,cortex-a57"; 603 set_feature(&cpu->env, ARM_FEATURE_V8); 604 set_feature(&cpu->env, ARM_FEATURE_NEON); 605 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 606 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 607 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 608 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 609 set_feature(&cpu->env, ARM_FEATURE_EL2); 610 set_feature(&cpu->env, ARM_FEATURE_EL3); 611 set_feature(&cpu->env, ARM_FEATURE_PMU); 612 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; 613 cpu->midr = 0x411fd070; 614 cpu->revidr = 0x00000000; 615 cpu->reset_fpsid = 0x41034070; 616 cpu->isar.mvfr0 = 0x10110222; 617 cpu->isar.mvfr1 = 0x12111111; 618 cpu->isar.mvfr2 = 0x00000043; 619 cpu->ctr = 0x8444c004; 620 cpu->reset_sctlr = 0x00c50838; 621 cpu->isar.id_pfr0 = 0x00000131; 622 cpu->isar.id_pfr1 = 0x00011011; 623 cpu->isar.id_dfr0 = 0x03010066; 624 cpu->id_afr0 = 0x00000000; 625 cpu->isar.id_mmfr0 = 0x10101105; 626 cpu->isar.id_mmfr1 = 0x40000000; 627 cpu->isar.id_mmfr2 = 0x01260000; 628 cpu->isar.id_mmfr3 = 0x02102211; 629 cpu->isar.id_isar0 = 0x02101110; 630 cpu->isar.id_isar1 = 0x13112111; 631 cpu->isar.id_isar2 = 0x21232042; 632 cpu->isar.id_isar3 = 0x01112131; 633 cpu->isar.id_isar4 = 0x00011142; 634 cpu->isar.id_isar5 = 0x00011121; 635 cpu->isar.id_isar6 = 0; 636 cpu->isar.id_aa64pfr0 = 0x00002222; 637 cpu->isar.id_aa64dfr0 = 0x10305106; 638 cpu->isar.id_aa64isar0 = 0x00011120; 639 cpu->isar.id_aa64mmfr0 = 0x00001124; 640 cpu->isar.dbgdidr = 0x3516d000; 641 cpu->isar.dbgdevid = 0x01110f13; 642 cpu->isar.dbgdevid1 = 0x2; 643 cpu->isar.reset_pmcr_el0 = 0x41013000; 644 cpu->clidr = 0x0a200023; 645 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 646 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 647 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 648 cpu->dcz_blocksize = 4; /* 64 bytes */ 649 cpu->gic_num_lrs = 4; 650 cpu->gic_vpribits = 5; 651 cpu->gic_vprebits = 5; 652 cpu->gic_pribits = 5; 653 define_cortex_a72_a57_a53_cp_reginfo(cpu); 654 } 655 656 static void aarch64_a53_initfn(Object *obj) 657 { 658 ARMCPU *cpu = ARM_CPU(obj); 659 660 cpu->dtb_compatible = "arm,cortex-a53"; 661 set_feature(&cpu->env, ARM_FEATURE_V8); 662 set_feature(&cpu->env, ARM_FEATURE_NEON); 663 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 664 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 665 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 666 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 667 set_feature(&cpu->env, ARM_FEATURE_EL2); 668 set_feature(&cpu->env, ARM_FEATURE_EL3); 669 set_feature(&cpu->env, ARM_FEATURE_PMU); 670 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; 671 cpu->midr = 0x410fd034; 672 cpu->revidr = 0x00000100; 673 cpu->reset_fpsid = 0x41034070; 674 cpu->isar.mvfr0 = 0x10110222; 675 cpu->isar.mvfr1 = 0x12111111; 676 cpu->isar.mvfr2 = 0x00000043; 677 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 678 cpu->reset_sctlr = 0x00c50838; 679 cpu->isar.id_pfr0 = 0x00000131; 680 cpu->isar.id_pfr1 = 0x00011011; 681 cpu->isar.id_dfr0 = 0x03010066; 682 cpu->id_afr0 = 0x00000000; 683 cpu->isar.id_mmfr0 = 0x10101105; 684 cpu->isar.id_mmfr1 = 0x40000000; 685 cpu->isar.id_mmfr2 = 0x01260000; 686 cpu->isar.id_mmfr3 = 0x02102211; 687 cpu->isar.id_isar0 = 0x02101110; 688 cpu->isar.id_isar1 = 0x13112111; 689 cpu->isar.id_isar2 = 0x21232042; 690 cpu->isar.id_isar3 = 0x01112131; 691 cpu->isar.id_isar4 = 0x00011142; 692 cpu->isar.id_isar5 = 0x00011121; 693 cpu->isar.id_isar6 = 0; 694 cpu->isar.id_aa64pfr0 = 0x00002222; 695 cpu->isar.id_aa64dfr0 = 0x10305106; 696 cpu->isar.id_aa64isar0 = 0x00011120; 697 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ 698 cpu->isar.dbgdidr = 0x3516d000; 699 cpu->isar.dbgdevid = 0x00110f13; 700 cpu->isar.dbgdevid1 = 0x1; 701 cpu->isar.reset_pmcr_el0 = 0x41033000; 702 cpu->clidr = 0x0a200023; 703 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 704 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 705 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ 706 cpu->dcz_blocksize = 4; /* 64 bytes */ 707 cpu->gic_num_lrs = 4; 708 cpu->gic_vpribits = 5; 709 cpu->gic_vprebits = 5; 710 cpu->gic_pribits = 5; 711 define_cortex_a72_a57_a53_cp_reginfo(cpu); 712 } 713 714 static void aarch64_host_initfn(Object *obj) 715 { 716 #if defined(CONFIG_KVM) 717 ARMCPU *cpu = ARM_CPU(obj); 718 kvm_arm_set_cpu_features_from_host(cpu); 719 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 720 aarch64_add_sve_properties(obj); 721 aarch64_add_pauth_properties(obj); 722 } 723 #elif defined(CONFIG_HVF) 724 ARMCPU *cpu = ARM_CPU(obj); 725 hvf_arm_set_cpu_features_from_host(cpu); 726 aarch64_add_pauth_properties(obj); 727 #else 728 g_assert_not_reached(); 729 #endif 730 } 731 732 static void aarch64_max_initfn(Object *obj) 733 { 734 if (kvm_enabled() || hvf_enabled()) { 735 /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ 736 aarch64_host_initfn(obj); 737 return; 738 } 739 740 if (tcg_enabled() || qtest_enabled()) { 741 aarch64_a57_initfn(obj); 742 } 743 744 /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */ 745 if (tcg_enabled()) { 746 aarch64_max_tcg_initfn(obj); 747 } 748 } 749 750 static const ARMCPUInfo aarch64_cpus[] = { 751 { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, 752 { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, 753 { .name = "max", .initfn = aarch64_max_initfn }, 754 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 755 { .name = "host", .initfn = aarch64_host_initfn }, 756 #endif 757 }; 758 759 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 760 { 761 ARMCPU *cpu = ARM_CPU(obj); 762 763 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 764 } 765 766 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 767 { 768 ARMCPU *cpu = ARM_CPU(obj); 769 770 /* At this time, this property is only allowed if KVM is enabled. This 771 * restriction allows us to avoid fixing up functionality that assumes a 772 * uniform execution state like do_interrupt. 773 */ 774 if (value == false) { 775 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 776 error_setg(errp, "'aarch64' feature cannot be disabled " 777 "unless KVM is enabled and 32-bit EL1 " 778 "is supported"); 779 return; 780 } 781 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 782 } else { 783 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 784 } 785 } 786 787 static void aarch64_cpu_finalizefn(Object *obj) 788 { 789 } 790 791 static const gchar *aarch64_gdb_arch_name(CPUState *cs) 792 { 793 return "aarch64"; 794 } 795 796 static void aarch64_cpu_class_init(ObjectClass *oc, void *data) 797 { 798 CPUClass *cc = CPU_CLASS(oc); 799 800 cc->gdb_read_register = aarch64_cpu_gdb_read_register; 801 cc->gdb_write_register = aarch64_cpu_gdb_write_register; 802 cc->gdb_core_xml_file = "aarch64-core.xml"; 803 cc->gdb_arch_name = aarch64_gdb_arch_name; 804 805 object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, 806 aarch64_cpu_set_aarch64); 807 object_class_property_set_description(oc, "aarch64", 808 "Set on/off to enable/disable aarch64 " 809 "execution state "); 810 } 811 812 static void aarch64_cpu_instance_init(Object *obj) 813 { 814 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 815 816 acc->info->initfn(obj); 817 arm_cpu_post_init(obj); 818 } 819 820 static void cpu_register_class_init(ObjectClass *oc, void *data) 821 { 822 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 823 824 acc->info = data; 825 } 826 827 void aarch64_cpu_register(const ARMCPUInfo *info) 828 { 829 TypeInfo type_info = { 830 .parent = TYPE_AARCH64_CPU, 831 .instance_init = aarch64_cpu_instance_init, 832 .class_init = info->class_init ?: cpu_register_class_init, 833 .class_data = (void *)info, 834 }; 835 836 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 837 type_register(&type_info); 838 g_free((void *)type_info.name); 839 } 840 841 static const TypeInfo aarch64_cpu_type_info = { 842 .name = TYPE_AARCH64_CPU, 843 .parent = TYPE_ARM_CPU, 844 .instance_finalize = aarch64_cpu_finalizefn, 845 .abstract = true, 846 .class_init = aarch64_cpu_class_init, 847 }; 848 849 static void aarch64_cpu_register_types(void) 850 { 851 size_t i; 852 853 type_register_static(&aarch64_cpu_type_info); 854 855 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { 856 aarch64_cpu_register(&aarch64_cpus[i]); 857 } 858 } 859 860 type_init(aarch64_cpu_register_types) 861