1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 typedef struct { 170 uint64_t raw_tcr; 171 uint32_t mask; 172 uint32_t base_mask; 173 } TCR; 174 175 #define VTCR_NSW (1u << 29) 176 #define VTCR_NSA (1u << 30) 177 #define VSTCR_SW VTCR_NSW 178 #define VSTCR_SA VTCR_NSA 179 180 /* Define a maximum sized vector register. 181 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 182 * For 64-bit, this is a 2048-bit SVE register. 183 * 184 * Note that the mapping between S, D, and Q views of the register bank 185 * differs between AArch64 and AArch32. 186 * In AArch32: 187 * Qn = regs[n].d[1]:regs[n].d[0] 188 * Dn = regs[n / 2].d[n & 1] 189 * Sn = regs[n / 4].d[n % 4 / 2], 190 * bits 31..0 for even n, and bits 63..32 for odd n 191 * (and regs[16] to regs[31] are inaccessible) 192 * In AArch64: 193 * Zn = regs[n].d[*] 194 * Qn = regs[n].d[1]:regs[n].d[0] 195 * Dn = regs[n].d[0] 196 * Sn = regs[n].d[0] bits 31..0 197 * Hn = regs[n].d[0] bits 15..0 198 * 199 * This corresponds to the architecturally defined mapping between 200 * the two execution states, and means we do not need to explicitly 201 * map these registers when changing states. 202 * 203 * Align the data for use with TCG host vector operations. 204 */ 205 206 #ifdef TARGET_AARCH64 207 # define ARM_MAX_VQ 16 208 #else 209 # define ARM_MAX_VQ 1 210 #endif 211 212 typedef struct ARMVectorReg { 213 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 214 } ARMVectorReg; 215 216 #ifdef TARGET_AARCH64 217 /* In AArch32 mode, predicate registers do not exist at all. */ 218 typedef struct ARMPredicateReg { 219 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 220 } ARMPredicateReg; 221 222 /* In AArch32 mode, PAC keys do not exist at all. */ 223 typedef struct ARMPACKey { 224 uint64_t lo, hi; 225 } ARMPACKey; 226 #endif 227 228 /* See the commentary above the TBFLAG field definitions. */ 229 typedef struct CPUARMTBFlags { 230 uint32_t flags; 231 target_ulong flags2; 232 } CPUARMTBFlags; 233 234 typedef struct CPUArchState { 235 /* Regs for current mode. */ 236 uint32_t regs[16]; 237 238 /* 32/64 switch only happens when taking and returning from 239 * exceptions so the overlap semantics are taken care of then 240 * instead of having a complicated union. 241 */ 242 /* Regs for A64 mode. */ 243 uint64_t xregs[32]; 244 uint64_t pc; 245 /* PSTATE isn't an architectural register for ARMv8. However, it is 246 * convenient for us to assemble the underlying state into a 32 bit format 247 * identical to the architectural format used for the SPSR. (This is also 248 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 249 * 'pstate' register are.) Of the PSTATE bits: 250 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 251 * semantics as for AArch32, as described in the comments on each field) 252 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 253 * DAIF (exception masks) are kept in env->daif 254 * BTYPE is kept in env->btype 255 * SM and ZA are kept in env->svcr 256 * all other bits are stored in their correct places in env->pstate 257 */ 258 uint32_t pstate; 259 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 260 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 261 262 /* Cached TBFLAGS state. See below for which bits are included. */ 263 CPUARMTBFlags hflags; 264 265 /* Frequently accessed CPSR bits are stored separately for efficiency. 266 This contains all the other bits. Use cpsr_{read,write} to access 267 the whole CPSR. */ 268 uint32_t uncached_cpsr; 269 uint32_t spsr; 270 271 /* Banked registers. */ 272 uint64_t banked_spsr[8]; 273 uint32_t banked_r13[8]; 274 uint32_t banked_r14[8]; 275 276 /* These hold r8-r12. */ 277 uint32_t usr_regs[5]; 278 uint32_t fiq_regs[5]; 279 280 /* cpsr flag cache for faster execution */ 281 uint32_t CF; /* 0 or 1 */ 282 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 283 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 284 uint32_t ZF; /* Z set if zero. */ 285 uint32_t QF; /* 0 or 1 */ 286 uint32_t GE; /* cpsr[19:16] */ 287 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 288 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 289 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 290 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 291 292 uint64_t elr_el[4]; /* AArch64 exception link regs */ 293 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 294 295 /* System control coprocessor (cp15) */ 296 struct { 297 uint32_t c0_cpuid; 298 union { /* Cache size selection */ 299 struct { 300 uint64_t _unused_csselr0; 301 uint64_t csselr_ns; 302 uint64_t _unused_csselr1; 303 uint64_t csselr_s; 304 }; 305 uint64_t csselr_el[4]; 306 }; 307 union { /* System control register. */ 308 struct { 309 uint64_t _unused_sctlr; 310 uint64_t sctlr_ns; 311 uint64_t hsctlr; 312 uint64_t sctlr_s; 313 }; 314 uint64_t sctlr_el[4]; 315 }; 316 uint64_t cpacr_el1; /* Architectural feature access control register */ 317 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 318 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 319 uint64_t sder; /* Secure debug enable register. */ 320 uint32_t nsacr; /* Non-secure access control register. */ 321 union { /* MMU translation table base 0. */ 322 struct { 323 uint64_t _unused_ttbr0_0; 324 uint64_t ttbr0_ns; 325 uint64_t _unused_ttbr0_1; 326 uint64_t ttbr0_s; 327 }; 328 uint64_t ttbr0_el[4]; 329 }; 330 union { /* MMU translation table base 1. */ 331 struct { 332 uint64_t _unused_ttbr1_0; 333 uint64_t ttbr1_ns; 334 uint64_t _unused_ttbr1_1; 335 uint64_t ttbr1_s; 336 }; 337 uint64_t ttbr1_el[4]; 338 }; 339 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 340 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 341 /* MMU translation table base control. */ 342 TCR tcr_el[4]; 343 TCR vtcr_el2; /* Virtualization Translation Control. */ 344 TCR vstcr_el2; /* Secure Virtualization Translation Control. */ 345 uint32_t c2_data; /* MPU data cacheable bits. */ 346 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 347 union { /* MMU domain access control register 348 * MPU write buffer control. 349 */ 350 struct { 351 uint64_t dacr_ns; 352 uint64_t dacr_s; 353 }; 354 struct { 355 uint64_t dacr32_el2; 356 }; 357 }; 358 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 359 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 360 uint64_t hcr_el2; /* Hypervisor configuration register */ 361 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 362 uint64_t scr_el3; /* Secure configuration register. */ 363 union { /* Fault status registers. */ 364 struct { 365 uint64_t ifsr_ns; 366 uint64_t ifsr_s; 367 }; 368 struct { 369 uint64_t ifsr32_el2; 370 }; 371 }; 372 union { 373 struct { 374 uint64_t _unused_dfsr; 375 uint64_t dfsr_ns; 376 uint64_t hsr; 377 uint64_t dfsr_s; 378 }; 379 uint64_t esr_el[4]; 380 }; 381 uint32_t c6_region[8]; /* MPU base/size registers. */ 382 union { /* Fault address registers. */ 383 struct { 384 uint64_t _unused_far0; 385 #if HOST_BIG_ENDIAN 386 uint32_t ifar_ns; 387 uint32_t dfar_ns; 388 uint32_t ifar_s; 389 uint32_t dfar_s; 390 #else 391 uint32_t dfar_ns; 392 uint32_t ifar_ns; 393 uint32_t dfar_s; 394 uint32_t ifar_s; 395 #endif 396 uint64_t _unused_far3; 397 }; 398 uint64_t far_el[4]; 399 }; 400 uint64_t hpfar_el2; 401 uint64_t hstr_el2; 402 union { /* Translation result. */ 403 struct { 404 uint64_t _unused_par_0; 405 uint64_t par_ns; 406 uint64_t _unused_par_1; 407 uint64_t par_s; 408 }; 409 uint64_t par_el[4]; 410 }; 411 412 uint32_t c9_insn; /* Cache lockdown registers. */ 413 uint32_t c9_data; 414 uint64_t c9_pmcr; /* performance monitor control register */ 415 uint64_t c9_pmcnten; /* perf monitor counter enables */ 416 uint64_t c9_pmovsr; /* perf monitor overflow status */ 417 uint64_t c9_pmuserenr; /* perf monitor user enable */ 418 uint64_t c9_pmselr; /* perf monitor counter selection register */ 419 uint64_t c9_pminten; /* perf monitor interrupt enables */ 420 union { /* Memory attribute redirection */ 421 struct { 422 #if HOST_BIG_ENDIAN 423 uint64_t _unused_mair_0; 424 uint32_t mair1_ns; 425 uint32_t mair0_ns; 426 uint64_t _unused_mair_1; 427 uint32_t mair1_s; 428 uint32_t mair0_s; 429 #else 430 uint64_t _unused_mair_0; 431 uint32_t mair0_ns; 432 uint32_t mair1_ns; 433 uint64_t _unused_mair_1; 434 uint32_t mair0_s; 435 uint32_t mair1_s; 436 #endif 437 }; 438 uint64_t mair_el[4]; 439 }; 440 union { /* vector base address register */ 441 struct { 442 uint64_t _unused_vbar; 443 uint64_t vbar_ns; 444 uint64_t hvbar; 445 uint64_t vbar_s; 446 }; 447 uint64_t vbar_el[4]; 448 }; 449 uint32_t mvbar; /* (monitor) vector base address register */ 450 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 451 struct { /* FCSE PID. */ 452 uint32_t fcseidr_ns; 453 uint32_t fcseidr_s; 454 }; 455 union { /* Context ID. */ 456 struct { 457 uint64_t _unused_contextidr_0; 458 uint64_t contextidr_ns; 459 uint64_t _unused_contextidr_1; 460 uint64_t contextidr_s; 461 }; 462 uint64_t contextidr_el[4]; 463 }; 464 union { /* User RW Thread register. */ 465 struct { 466 uint64_t tpidrurw_ns; 467 uint64_t tpidrprw_ns; 468 uint64_t htpidr; 469 uint64_t _tpidr_el3; 470 }; 471 uint64_t tpidr_el[4]; 472 }; 473 uint64_t tpidr2_el0; 474 /* The secure banks of these registers don't map anywhere */ 475 uint64_t tpidrurw_s; 476 uint64_t tpidrprw_s; 477 uint64_t tpidruro_s; 478 479 union { /* User RO Thread register. */ 480 uint64_t tpidruro_ns; 481 uint64_t tpidrro_el[1]; 482 }; 483 uint64_t c14_cntfrq; /* Counter Frequency register */ 484 uint64_t c14_cntkctl; /* Timer Control register */ 485 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 486 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 487 ARMGenericTimer c14_timer[NUM_GTIMERS]; 488 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 489 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 490 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 491 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 492 uint32_t c15_threadid; /* TI debugger thread-ID. */ 493 uint32_t c15_config_base_address; /* SCU base address. */ 494 uint32_t c15_diagnostic; /* diagnostic register */ 495 uint32_t c15_power_diagnostic; 496 uint32_t c15_power_control; /* power control */ 497 uint64_t dbgbvr[16]; /* breakpoint value registers */ 498 uint64_t dbgbcr[16]; /* breakpoint control registers */ 499 uint64_t dbgwvr[16]; /* watchpoint value registers */ 500 uint64_t dbgwcr[16]; /* watchpoint control registers */ 501 uint64_t mdscr_el1; 502 uint64_t oslsr_el1; /* OS Lock Status */ 503 uint64_t mdcr_el2; 504 uint64_t mdcr_el3; 505 /* Stores the architectural value of the counter *the last time it was 506 * updated* by pmccntr_op_start. Accesses should always be surrounded 507 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 508 * architecturally-correct value is being read/set. 509 */ 510 uint64_t c15_ccnt; 511 /* Stores the delta between the architectural value and the underlying 512 * cycle count during normal operation. It is used to update c15_ccnt 513 * to be the correct architectural value before accesses. During 514 * accesses, c15_ccnt_delta contains the underlying count being used 515 * for the access, after which it reverts to the delta value in 516 * pmccntr_op_finish. 517 */ 518 uint64_t c15_ccnt_delta; 519 uint64_t c14_pmevcntr[31]; 520 uint64_t c14_pmevcntr_delta[31]; 521 uint64_t c14_pmevtyper[31]; 522 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 523 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 524 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 525 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 526 uint64_t gcr_el1; 527 uint64_t rgsr_el1; 528 529 /* Minimal RAS registers */ 530 uint64_t disr_el1; 531 uint64_t vdisr_el2; 532 uint64_t vsesr_el2; 533 } cp15; 534 535 struct { 536 /* M profile has up to 4 stack pointers: 537 * a Main Stack Pointer and a Process Stack Pointer for each 538 * of the Secure and Non-Secure states. (If the CPU doesn't support 539 * the security extension then it has only two SPs.) 540 * In QEMU we always store the currently active SP in regs[13], 541 * and the non-active SP for the current security state in 542 * v7m.other_sp. The stack pointers for the inactive security state 543 * are stored in other_ss_msp and other_ss_psp. 544 * switch_v7m_security_state() is responsible for rearranging them 545 * when we change security state. 546 */ 547 uint32_t other_sp; 548 uint32_t other_ss_msp; 549 uint32_t other_ss_psp; 550 uint32_t vecbase[M_REG_NUM_BANKS]; 551 uint32_t basepri[M_REG_NUM_BANKS]; 552 uint32_t control[M_REG_NUM_BANKS]; 553 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 554 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 555 uint32_t hfsr; /* HardFault Status */ 556 uint32_t dfsr; /* Debug Fault Status Register */ 557 uint32_t sfsr; /* Secure Fault Status Register */ 558 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 559 uint32_t bfar; /* BusFault Address */ 560 uint32_t sfar; /* Secure Fault Address Register */ 561 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 562 int exception; 563 uint32_t primask[M_REG_NUM_BANKS]; 564 uint32_t faultmask[M_REG_NUM_BANKS]; 565 uint32_t aircr; /* only holds r/w state if security extn implemented */ 566 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 567 uint32_t csselr[M_REG_NUM_BANKS]; 568 uint32_t scr[M_REG_NUM_BANKS]; 569 uint32_t msplim[M_REG_NUM_BANKS]; 570 uint32_t psplim[M_REG_NUM_BANKS]; 571 uint32_t fpcar[M_REG_NUM_BANKS]; 572 uint32_t fpccr[M_REG_NUM_BANKS]; 573 uint32_t fpdscr[M_REG_NUM_BANKS]; 574 uint32_t cpacr[M_REG_NUM_BANKS]; 575 uint32_t nsacr; 576 uint32_t ltpsize; 577 uint32_t vpr; 578 } v7m; 579 580 /* Information associated with an exception about to be taken: 581 * code which raises an exception must set cs->exception_index and 582 * the relevant parts of this structure; the cpu_do_interrupt function 583 * will then set the guest-visible registers as part of the exception 584 * entry process. 585 */ 586 struct { 587 uint32_t syndrome; /* AArch64 format syndrome register */ 588 uint32_t fsr; /* AArch32 format fault status register info */ 589 uint64_t vaddress; /* virtual addr associated with exception, if any */ 590 uint32_t target_el; /* EL the exception should be targeted for */ 591 /* If we implement EL2 we will also need to store information 592 * about the intermediate physical address for stage 2 faults. 593 */ 594 } exception; 595 596 /* Information associated with an SError */ 597 struct { 598 uint8_t pending; 599 uint8_t has_esr; 600 uint64_t esr; 601 } serror; 602 603 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 604 605 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 606 uint32_t irq_line_state; 607 608 /* Thumb-2 EE state. */ 609 uint32_t teecr; 610 uint32_t teehbr; 611 612 /* VFP coprocessor state. */ 613 struct { 614 ARMVectorReg zregs[32]; 615 616 #ifdef TARGET_AARCH64 617 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 618 #define FFR_PRED_NUM 16 619 ARMPredicateReg pregs[17]; 620 /* Scratch space for aa64 sve predicate temporary. */ 621 ARMPredicateReg preg_tmp; 622 #endif 623 624 /* We store these fpcsr fields separately for convenience. */ 625 uint32_t qc[4] QEMU_ALIGNED(16); 626 int vec_len; 627 int vec_stride; 628 629 uint32_t xregs[16]; 630 631 /* Scratch space for aa32 neon expansion. */ 632 uint32_t scratch[8]; 633 634 /* There are a number of distinct float control structures: 635 * 636 * fp_status: is the "normal" fp status. 637 * fp_status_fp16: used for half-precision calculations 638 * standard_fp_status : the ARM "Standard FPSCR Value" 639 * standard_fp_status_fp16 : used for half-precision 640 * calculations with the ARM "Standard FPSCR Value" 641 * 642 * Half-precision operations are governed by a separate 643 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 644 * status structure to control this. 645 * 646 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 647 * round-to-nearest and is used by any operations (generally 648 * Neon) which the architecture defines as controlled by the 649 * standard FPSCR value rather than the FPSCR. 650 * 651 * The "standard FPSCR but for fp16 ops" is needed because 652 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 653 * using a fixed value for it. 654 * 655 * To avoid having to transfer exception bits around, we simply 656 * say that the FPSCR cumulative exception flags are the logical 657 * OR of the flags in the four fp statuses. This relies on the 658 * only thing which needs to read the exception flags being 659 * an explicit FPSCR read. 660 */ 661 float_status fp_status; 662 float_status fp_status_f16; 663 float_status standard_fp_status; 664 float_status standard_fp_status_f16; 665 666 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 667 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 668 } vfp; 669 uint64_t exclusive_addr; 670 uint64_t exclusive_val; 671 uint64_t exclusive_high; 672 673 /* iwMMXt coprocessor state. */ 674 struct { 675 uint64_t regs[16]; 676 uint64_t val; 677 678 uint32_t cregs[16]; 679 } iwmmxt; 680 681 #ifdef TARGET_AARCH64 682 struct { 683 ARMPACKey apia; 684 ARMPACKey apib; 685 ARMPACKey apda; 686 ARMPACKey apdb; 687 ARMPACKey apga; 688 } keys; 689 690 uint64_t scxtnum_el[4]; 691 692 /* 693 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 694 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 695 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 696 * When SVL is less than the architectural maximum, the accessible 697 * storage is restricted, such that if the SVL is X bytes the guest can 698 * see only the bottom X elements of zarray[], and only the least 699 * significant X bytes of each element of the array. (In other words, 700 * the observable part is always square.) 701 * 702 * The ZA storage can also be considered as a set of square tiles of 703 * elements of different sizes. The mapping from tiles to the ZA array 704 * is architecturally defined, such that for tiles of elements of esz 705 * bytes, the Nth row (or "horizontal slice") of tile T is in 706 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 707 * in the ZA storage, because its rows are striped through the ZA array. 708 * 709 * Because this is so large, keep this toward the end of the reset area, 710 * to keep the offsets into the rest of the structure smaller. 711 */ 712 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 713 #endif 714 715 #if defined(CONFIG_USER_ONLY) 716 /* For usermode syscall translation. */ 717 int eabi; 718 #endif 719 720 struct CPUBreakpoint *cpu_breakpoint[16]; 721 struct CPUWatchpoint *cpu_watchpoint[16]; 722 723 /* Fields up to this point are cleared by a CPU reset */ 724 struct {} end_reset_fields; 725 726 /* Fields after this point are preserved across CPU reset. */ 727 728 /* Internal CPU feature flags. */ 729 uint64_t features; 730 731 /* PMSAv7 MPU */ 732 struct { 733 uint32_t *drbar; 734 uint32_t *drsr; 735 uint32_t *dracr; 736 uint32_t rnr[M_REG_NUM_BANKS]; 737 } pmsav7; 738 739 /* PMSAv8 MPU */ 740 struct { 741 /* The PMSAv8 implementation also shares some PMSAv7 config 742 * and state: 743 * pmsav7.rnr (region number register) 744 * pmsav7_dregion (number of configured regions) 745 */ 746 uint32_t *rbar[M_REG_NUM_BANKS]; 747 uint32_t *rlar[M_REG_NUM_BANKS]; 748 uint32_t mair0[M_REG_NUM_BANKS]; 749 uint32_t mair1[M_REG_NUM_BANKS]; 750 } pmsav8; 751 752 /* v8M SAU */ 753 struct { 754 uint32_t *rbar; 755 uint32_t *rlar; 756 uint32_t rnr; 757 uint32_t ctrl; 758 } sau; 759 760 void *nvic; 761 const struct arm_boot_info *boot_info; 762 /* Store GICv3CPUState to access from this struct */ 763 void *gicv3state; 764 765 #ifdef TARGET_TAGGED_ADDRESSES 766 /* Linux syscall tagged address support */ 767 bool tagged_addr_enable; 768 #endif 769 } CPUARMState; 770 771 static inline void set_feature(CPUARMState *env, int feature) 772 { 773 env->features |= 1ULL << feature; 774 } 775 776 static inline void unset_feature(CPUARMState *env, int feature) 777 { 778 env->features &= ~(1ULL << feature); 779 } 780 781 /** 782 * ARMELChangeHookFn: 783 * type of a function which can be registered via arm_register_el_change_hook() 784 * to get callbacks when the CPU changes its exception level or mode. 785 */ 786 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 787 typedef struct ARMELChangeHook ARMELChangeHook; 788 struct ARMELChangeHook { 789 ARMELChangeHookFn *hook; 790 void *opaque; 791 QLIST_ENTRY(ARMELChangeHook) node; 792 }; 793 794 /* These values map onto the return values for 795 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 796 typedef enum ARMPSCIState { 797 PSCI_ON = 0, 798 PSCI_OFF = 1, 799 PSCI_ON_PENDING = 2 800 } ARMPSCIState; 801 802 typedef struct ARMISARegisters ARMISARegisters; 803 804 /* 805 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 806 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 807 * 808 * While processing properties during initialization, corresponding init bits 809 * are set for bits in sve_vq_map that have been set by properties. 810 * 811 * Bits set in supported represent valid vector lengths for the CPU type. 812 */ 813 typedef struct { 814 uint32_t map, init, supported; 815 } ARMVQMap; 816 817 /** 818 * ARMCPU: 819 * @env: #CPUARMState 820 * 821 * An ARM CPU core. 822 */ 823 struct ArchCPU { 824 /*< private >*/ 825 CPUState parent_obj; 826 /*< public >*/ 827 828 CPUNegativeOffsetState neg; 829 CPUARMState env; 830 831 /* Coprocessor information */ 832 GHashTable *cp_regs; 833 /* For marshalling (mostly coprocessor) register state between the 834 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 835 * we use these arrays. 836 */ 837 /* List of register indexes managed via these arrays; (full KVM style 838 * 64 bit indexes, not CPRegInfo 32 bit indexes) 839 */ 840 uint64_t *cpreg_indexes; 841 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 842 uint64_t *cpreg_values; 843 /* Length of the indexes, values, reset_values arrays */ 844 int32_t cpreg_array_len; 845 /* These are used only for migration: incoming data arrives in 846 * these fields and is sanity checked in post_load before copying 847 * to the working data structures above. 848 */ 849 uint64_t *cpreg_vmstate_indexes; 850 uint64_t *cpreg_vmstate_values; 851 int32_t cpreg_vmstate_array_len; 852 853 DynamicGDBXMLInfo dyn_sysreg_xml; 854 DynamicGDBXMLInfo dyn_svereg_xml; 855 856 /* Timers used by the generic (architected) timer */ 857 QEMUTimer *gt_timer[NUM_GTIMERS]; 858 /* 859 * Timer used by the PMU. Its state is restored after migration by 860 * pmu_op_finish() - it does not need other handling during migration 861 */ 862 QEMUTimer *pmu_timer; 863 /* GPIO outputs for generic timer */ 864 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 865 /* GPIO output for GICv3 maintenance interrupt signal */ 866 qemu_irq gicv3_maintenance_interrupt; 867 /* GPIO output for the PMU interrupt */ 868 qemu_irq pmu_interrupt; 869 870 /* MemoryRegion to use for secure physical accesses */ 871 MemoryRegion *secure_memory; 872 873 /* MemoryRegion to use for allocation tag accesses */ 874 MemoryRegion *tag_memory; 875 MemoryRegion *secure_tag_memory; 876 877 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 878 Object *idau; 879 880 /* 'compatible' string for this CPU for Linux device trees */ 881 const char *dtb_compatible; 882 883 /* PSCI version for this CPU 884 * Bits[31:16] = Major Version 885 * Bits[15:0] = Minor Version 886 */ 887 uint32_t psci_version; 888 889 /* Current power state, access guarded by BQL */ 890 ARMPSCIState power_state; 891 892 /* CPU has virtualization extension */ 893 bool has_el2; 894 /* CPU has security extension */ 895 bool has_el3; 896 /* CPU has PMU (Performance Monitor Unit) */ 897 bool has_pmu; 898 /* CPU has VFP */ 899 bool has_vfp; 900 /* CPU has Neon */ 901 bool has_neon; 902 /* CPU has M-profile DSP extension */ 903 bool has_dsp; 904 905 /* CPU has memory protection unit */ 906 bool has_mpu; 907 /* PMSAv7 MPU number of supported regions */ 908 uint32_t pmsav7_dregion; 909 /* v8M SAU number of supported regions */ 910 uint32_t sau_sregion; 911 912 /* PSCI conduit used to invoke PSCI methods 913 * 0 - disabled, 1 - smc, 2 - hvc 914 */ 915 uint32_t psci_conduit; 916 917 /* For v8M, initial value of the Secure VTOR */ 918 uint32_t init_svtor; 919 /* For v8M, initial value of the Non-secure VTOR */ 920 uint32_t init_nsvtor; 921 922 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 923 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 924 */ 925 uint32_t kvm_target; 926 927 /* KVM init features for this CPU */ 928 uint32_t kvm_init_features[7]; 929 930 /* KVM CPU state */ 931 932 /* KVM virtual time adjustment */ 933 bool kvm_adjvtime; 934 bool kvm_vtime_dirty; 935 uint64_t kvm_vtime; 936 937 /* KVM steal time */ 938 OnOffAuto kvm_steal_time; 939 940 /* Uniprocessor system with MP extensions */ 941 bool mp_is_up; 942 943 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 944 * and the probe failed (so we need to report the error in realize) 945 */ 946 bool host_cpu_probe_failed; 947 948 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 949 * register. 950 */ 951 int32_t core_count; 952 953 /* The instance init functions for implementation-specific subclasses 954 * set these fields to specify the implementation-dependent values of 955 * various constant registers and reset values of non-constant 956 * registers. 957 * Some of these might become QOM properties eventually. 958 * Field names match the official register names as defined in the 959 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 960 * is used for reset values of non-constant registers; no reset_ 961 * prefix means a constant register. 962 * Some of these registers are split out into a substructure that 963 * is shared with the translators to control the ISA. 964 * 965 * Note that if you add an ID register to the ARMISARegisters struct 966 * you need to also update the 32-bit and 64-bit versions of the 967 * kvm_arm_get_host_cpu_features() function to correctly populate the 968 * field by reading the value from the KVM vCPU. 969 */ 970 struct ARMISARegisters { 971 uint32_t id_isar0; 972 uint32_t id_isar1; 973 uint32_t id_isar2; 974 uint32_t id_isar3; 975 uint32_t id_isar4; 976 uint32_t id_isar5; 977 uint32_t id_isar6; 978 uint32_t id_mmfr0; 979 uint32_t id_mmfr1; 980 uint32_t id_mmfr2; 981 uint32_t id_mmfr3; 982 uint32_t id_mmfr4; 983 uint32_t id_pfr0; 984 uint32_t id_pfr1; 985 uint32_t id_pfr2; 986 uint32_t mvfr0; 987 uint32_t mvfr1; 988 uint32_t mvfr2; 989 uint32_t id_dfr0; 990 uint32_t dbgdidr; 991 uint64_t id_aa64isar0; 992 uint64_t id_aa64isar1; 993 uint64_t id_aa64pfr0; 994 uint64_t id_aa64pfr1; 995 uint64_t id_aa64mmfr0; 996 uint64_t id_aa64mmfr1; 997 uint64_t id_aa64mmfr2; 998 uint64_t id_aa64dfr0; 999 uint64_t id_aa64dfr1; 1000 uint64_t id_aa64zfr0; 1001 uint64_t id_aa64smfr0; 1002 uint64_t reset_pmcr_el0; 1003 } isar; 1004 uint64_t midr; 1005 uint32_t revidr; 1006 uint32_t reset_fpsid; 1007 uint64_t ctr; 1008 uint32_t reset_sctlr; 1009 uint64_t pmceid0; 1010 uint64_t pmceid1; 1011 uint32_t id_afr0; 1012 uint64_t id_aa64afr0; 1013 uint64_t id_aa64afr1; 1014 uint64_t clidr; 1015 uint64_t mp_affinity; /* MP ID without feature bits */ 1016 /* The elements of this array are the CCSIDR values for each cache, 1017 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1018 */ 1019 uint64_t ccsidr[16]; 1020 uint64_t reset_cbar; 1021 uint32_t reset_auxcr; 1022 bool reset_hivecs; 1023 1024 /* 1025 * Intermediate values used during property parsing. 1026 * Once finalized, the values should be read from ID_AA64*. 1027 */ 1028 bool prop_pauth; 1029 bool prop_pauth_impdef; 1030 bool prop_lpa2; 1031 1032 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1033 uint32_t dcz_blocksize; 1034 uint64_t rvbar_prop; /* Property/input signals. */ 1035 1036 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1037 int gic_num_lrs; /* number of list registers */ 1038 int gic_vpribits; /* number of virtual priority bits */ 1039 int gic_vprebits; /* number of virtual preemption bits */ 1040 int gic_pribits; /* number of physical priority bits */ 1041 1042 /* Whether the cfgend input is high (i.e. this CPU should reset into 1043 * big-endian mode). This setting isn't used directly: instead it modifies 1044 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1045 * architecture version. 1046 */ 1047 bool cfgend; 1048 1049 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1050 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1051 1052 int32_t node_id; /* NUMA node this CPU belongs to */ 1053 1054 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1055 uint8_t device_irq_level; 1056 1057 /* Used to set the maximum vector length the cpu will support. */ 1058 uint32_t sve_max_vq; 1059 1060 #ifdef CONFIG_USER_ONLY 1061 /* Used to set the default vector length at process start. */ 1062 uint32_t sve_default_vq; 1063 uint32_t sme_default_vq; 1064 #endif 1065 1066 ARMVQMap sve_vq; 1067 ARMVQMap sme_vq; 1068 1069 /* Generic timer counter frequency, in Hz */ 1070 uint64_t gt_cntfrq_hz; 1071 }; 1072 1073 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1074 1075 void arm_cpu_post_init(Object *obj); 1076 1077 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1078 1079 #ifndef CONFIG_USER_ONLY 1080 extern const VMStateDescription vmstate_arm_cpu; 1081 1082 void arm_cpu_do_interrupt(CPUState *cpu); 1083 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1084 #endif /* !CONFIG_USER_ONLY */ 1085 1086 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1087 MemTxAttrs *attrs); 1088 1089 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1090 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1091 1092 /* 1093 * Helpers to dynamically generates XML descriptions of the sysregs 1094 * and SVE registers. Returns the number of registers in each set. 1095 */ 1096 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1097 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1098 1099 /* Returns the dynamically generated XML for the gdb stub. 1100 * Returns a pointer to the XML contents for the specified XML file or NULL 1101 * if the XML name doesn't match the predefined one. 1102 */ 1103 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1104 1105 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1106 int cpuid, void *opaque); 1107 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1108 int cpuid, void *opaque); 1109 1110 #ifdef TARGET_AARCH64 1111 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1112 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1113 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1114 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1115 int new_el, bool el0_a64); 1116 void arm_reset_sve_state(CPUARMState *env); 1117 1118 /* 1119 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1120 * The byte at offset i from the start of the in-memory representation contains 1121 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1122 * lowest offsets are stored in the lowest memory addresses, then that nearly 1123 * matches QEMU's representation, which is to use an array of host-endian 1124 * uint64_t's, where the lower offsets are at the lower indices. To complete 1125 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1126 */ 1127 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1128 { 1129 #if HOST_BIG_ENDIAN 1130 int i; 1131 1132 for (i = 0; i < nr; ++i) { 1133 dst[i] = bswap64(src[i]); 1134 } 1135 1136 return dst; 1137 #else 1138 return src; 1139 #endif 1140 } 1141 1142 #else 1143 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1144 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1145 int n, bool a) 1146 { } 1147 #endif 1148 1149 void aarch64_sync_32_to_64(CPUARMState *env); 1150 void aarch64_sync_64_to_32(CPUARMState *env); 1151 1152 int fp_exception_el(CPUARMState *env, int cur_el); 1153 int sve_exception_el(CPUARMState *env, int cur_el); 1154 int sme_exception_el(CPUARMState *env, int cur_el); 1155 1156 /** 1157 * sve_vqm1_for_el_sm: 1158 * @env: CPUARMState 1159 * @el: exception level 1160 * @sm: streaming mode 1161 * 1162 * Compute the current vector length for @el & @sm, in units of 1163 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1164 * If @sm, compute for SVL, otherwise NVL. 1165 */ 1166 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1167 1168 /* Likewise, but using @sm = PSTATE.SM. */ 1169 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1170 1171 static inline bool is_a64(CPUARMState *env) 1172 { 1173 return env->aarch64; 1174 } 1175 1176 /** 1177 * pmu_op_start/finish 1178 * @env: CPUARMState 1179 * 1180 * Convert all PMU counters between their delta form (the typical mode when 1181 * they are enabled) and the guest-visible values. These two calls must 1182 * surround any action which might affect the counters. 1183 */ 1184 void pmu_op_start(CPUARMState *env); 1185 void pmu_op_finish(CPUARMState *env); 1186 1187 /* 1188 * Called when a PMU counter is due to overflow 1189 */ 1190 void arm_pmu_timer_cb(void *opaque); 1191 1192 /** 1193 * Functions to register as EL change hooks for PMU mode filtering 1194 */ 1195 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1196 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1197 1198 /* 1199 * pmu_init 1200 * @cpu: ARMCPU 1201 * 1202 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1203 * for the current configuration 1204 */ 1205 void pmu_init(ARMCPU *cpu); 1206 1207 /* SCTLR bit meanings. Several bits have been reused in newer 1208 * versions of the architecture; in that case we define constants 1209 * for both old and new bit meanings. Code which tests against those 1210 * bits should probably check or otherwise arrange that the CPU 1211 * is the architectural version it expects. 1212 */ 1213 #define SCTLR_M (1U << 0) 1214 #define SCTLR_A (1U << 1) 1215 #define SCTLR_C (1U << 2) 1216 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1217 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1218 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1219 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1220 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1221 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1222 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1223 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1224 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1225 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1226 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1227 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1228 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1229 #define SCTLR_SED (1U << 8) /* v8 onward */ 1230 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1231 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1232 #define SCTLR_F (1U << 10) /* up to v6 */ 1233 #define SCTLR_SW (1U << 10) /* v7 */ 1234 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1235 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1236 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1237 #define SCTLR_I (1U << 12) 1238 #define SCTLR_V (1U << 13) /* AArch32 only */ 1239 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1240 #define SCTLR_RR (1U << 14) /* up to v7 */ 1241 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1242 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1243 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1244 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1245 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1246 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1247 #define SCTLR_BR (1U << 17) /* PMSA only */ 1248 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1249 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1250 #define SCTLR_WXN (1U << 19) 1251 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1252 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1253 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1254 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1255 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1256 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1257 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1258 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1259 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1260 #define SCTLR_VE (1U << 24) /* up to v7 */ 1261 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1262 #define SCTLR_EE (1U << 25) 1263 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1264 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1265 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1266 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1267 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1268 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1269 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1270 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1271 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1272 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1273 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1274 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1275 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1276 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1277 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1278 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1279 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1280 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1281 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1282 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1283 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1284 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1285 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1286 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1287 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1288 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1289 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1290 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1291 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1292 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1293 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1294 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1295 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1296 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1297 1298 /* Bit definitions for CPACR (AArch32 only) */ 1299 FIELD(CPACR, CP10, 20, 2) 1300 FIELD(CPACR, CP11, 22, 2) 1301 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1302 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1303 FIELD(CPACR, ASEDIS, 31, 1) 1304 1305 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1306 FIELD(CPACR_EL1, ZEN, 16, 2) 1307 FIELD(CPACR_EL1, FPEN, 20, 2) 1308 FIELD(CPACR_EL1, SMEN, 24, 2) 1309 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1310 1311 /* Bit definitions for HCPTR (AArch32 only) */ 1312 FIELD(HCPTR, TCP10, 10, 1) 1313 FIELD(HCPTR, TCP11, 11, 1) 1314 FIELD(HCPTR, TASE, 15, 1) 1315 FIELD(HCPTR, TTA, 20, 1) 1316 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1317 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1318 1319 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1320 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1321 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1322 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1323 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1324 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1325 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1326 FIELD(CPTR_EL2, TTA, 28, 1) 1327 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1328 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1329 1330 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1331 FIELD(CPTR_EL3, EZ, 8, 1) 1332 FIELD(CPTR_EL3, TFP, 10, 1) 1333 FIELD(CPTR_EL3, ESM, 12, 1) 1334 FIELD(CPTR_EL3, TTA, 20, 1) 1335 FIELD(CPTR_EL3, TAM, 30, 1) 1336 FIELD(CPTR_EL3, TCPAC, 31, 1) 1337 1338 #define MDCR_EPMAD (1U << 21) 1339 #define MDCR_EDAD (1U << 20) 1340 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1341 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1342 #define MDCR_SDD (1U << 16) 1343 #define MDCR_SPD (3U << 14) 1344 #define MDCR_TDRA (1U << 11) 1345 #define MDCR_TDOSA (1U << 10) 1346 #define MDCR_TDA (1U << 9) 1347 #define MDCR_TDE (1U << 8) 1348 #define MDCR_HPME (1U << 7) 1349 #define MDCR_TPM (1U << 6) 1350 #define MDCR_TPMCR (1U << 5) 1351 #define MDCR_HPMN (0x1fU) 1352 1353 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1354 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1355 1356 #define CPSR_M (0x1fU) 1357 #define CPSR_T (1U << 5) 1358 #define CPSR_F (1U << 6) 1359 #define CPSR_I (1U << 7) 1360 #define CPSR_A (1U << 8) 1361 #define CPSR_E (1U << 9) 1362 #define CPSR_IT_2_7 (0xfc00U) 1363 #define CPSR_GE (0xfU << 16) 1364 #define CPSR_IL (1U << 20) 1365 #define CPSR_DIT (1U << 21) 1366 #define CPSR_PAN (1U << 22) 1367 #define CPSR_SSBS (1U << 23) 1368 #define CPSR_J (1U << 24) 1369 #define CPSR_IT_0_1 (3U << 25) 1370 #define CPSR_Q (1U << 27) 1371 #define CPSR_V (1U << 28) 1372 #define CPSR_C (1U << 29) 1373 #define CPSR_Z (1U << 30) 1374 #define CPSR_N (1U << 31) 1375 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1376 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1377 1378 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1379 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1380 | CPSR_NZCV) 1381 /* Bits writable in user mode. */ 1382 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1383 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1384 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1385 1386 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1387 #define XPSR_EXCP 0x1ffU 1388 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1389 #define XPSR_IT_2_7 CPSR_IT_2_7 1390 #define XPSR_GE CPSR_GE 1391 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1392 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1393 #define XPSR_IT_0_1 CPSR_IT_0_1 1394 #define XPSR_Q CPSR_Q 1395 #define XPSR_V CPSR_V 1396 #define XPSR_C CPSR_C 1397 #define XPSR_Z CPSR_Z 1398 #define XPSR_N CPSR_N 1399 #define XPSR_NZCV CPSR_NZCV 1400 #define XPSR_IT CPSR_IT 1401 1402 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1403 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1404 #define TTBCR_PD0 (1U << 4) 1405 #define TTBCR_PD1 (1U << 5) 1406 #define TTBCR_EPD0 (1U << 7) 1407 #define TTBCR_IRGN0 (3U << 8) 1408 #define TTBCR_ORGN0 (3U << 10) 1409 #define TTBCR_SH0 (3U << 12) 1410 #define TTBCR_T1SZ (3U << 16) 1411 #define TTBCR_A1 (1U << 22) 1412 #define TTBCR_EPD1 (1U << 23) 1413 #define TTBCR_IRGN1 (3U << 24) 1414 #define TTBCR_ORGN1 (3U << 26) 1415 #define TTBCR_SH1 (1U << 28) 1416 #define TTBCR_EAE (1U << 31) 1417 1418 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1419 * Only these are valid when in AArch64 mode; in 1420 * AArch32 mode SPSRs are basically CPSR-format. 1421 */ 1422 #define PSTATE_SP (1U) 1423 #define PSTATE_M (0xFU) 1424 #define PSTATE_nRW (1U << 4) 1425 #define PSTATE_F (1U << 6) 1426 #define PSTATE_I (1U << 7) 1427 #define PSTATE_A (1U << 8) 1428 #define PSTATE_D (1U << 9) 1429 #define PSTATE_BTYPE (3U << 10) 1430 #define PSTATE_SSBS (1U << 12) 1431 #define PSTATE_IL (1U << 20) 1432 #define PSTATE_SS (1U << 21) 1433 #define PSTATE_PAN (1U << 22) 1434 #define PSTATE_UAO (1U << 23) 1435 #define PSTATE_DIT (1U << 24) 1436 #define PSTATE_TCO (1U << 25) 1437 #define PSTATE_V (1U << 28) 1438 #define PSTATE_C (1U << 29) 1439 #define PSTATE_Z (1U << 30) 1440 #define PSTATE_N (1U << 31) 1441 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1442 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1443 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1444 /* Mode values for AArch64 */ 1445 #define PSTATE_MODE_EL3h 13 1446 #define PSTATE_MODE_EL3t 12 1447 #define PSTATE_MODE_EL2h 9 1448 #define PSTATE_MODE_EL2t 8 1449 #define PSTATE_MODE_EL1h 5 1450 #define PSTATE_MODE_EL1t 4 1451 #define PSTATE_MODE_EL0t 0 1452 1453 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1454 FIELD(SVCR, SM, 0, 1) 1455 FIELD(SVCR, ZA, 1, 1) 1456 1457 /* Fields for SMCR_ELx. */ 1458 FIELD(SMCR, LEN, 0, 4) 1459 FIELD(SMCR, FA64, 31, 1) 1460 1461 /* Write a new value to v7m.exception, thus transitioning into or out 1462 * of Handler mode; this may result in a change of active stack pointer. 1463 */ 1464 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1465 1466 /* Map EL and handler into a PSTATE_MODE. */ 1467 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1468 { 1469 return (el << 2) | handler; 1470 } 1471 1472 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1473 * interprocessing, so we don't attempt to sync with the cpsr state used by 1474 * the 32 bit decoder. 1475 */ 1476 static inline uint32_t pstate_read(CPUARMState *env) 1477 { 1478 int ZF; 1479 1480 ZF = (env->ZF == 0); 1481 return (env->NF & 0x80000000) | (ZF << 30) 1482 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1483 | env->pstate | env->daif | (env->btype << 10); 1484 } 1485 1486 static inline void pstate_write(CPUARMState *env, uint32_t val) 1487 { 1488 env->ZF = (~val) & PSTATE_Z; 1489 env->NF = val; 1490 env->CF = (val >> 29) & 1; 1491 env->VF = (val << 3) & 0x80000000; 1492 env->daif = val & PSTATE_DAIF; 1493 env->btype = (val >> 10) & 3; 1494 env->pstate = val & ~CACHED_PSTATE_BITS; 1495 } 1496 1497 /* Return the current CPSR value. */ 1498 uint32_t cpsr_read(CPUARMState *env); 1499 1500 typedef enum CPSRWriteType { 1501 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1502 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1503 CPSRWriteRaw = 2, 1504 /* trust values, no reg bank switch, no hflags rebuild */ 1505 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1506 } CPSRWriteType; 1507 1508 /* 1509 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1510 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1511 * correspond to TB flags bits cached in the hflags, unless @write_type 1512 * is CPSRWriteRaw. 1513 */ 1514 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1515 CPSRWriteType write_type); 1516 1517 /* Return the current xPSR value. */ 1518 static inline uint32_t xpsr_read(CPUARMState *env) 1519 { 1520 int ZF; 1521 ZF = (env->ZF == 0); 1522 return (env->NF & 0x80000000) | (ZF << 30) 1523 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1524 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1525 | ((env->condexec_bits & 0xfc) << 8) 1526 | (env->GE << 16) 1527 | env->v7m.exception; 1528 } 1529 1530 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1531 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1532 { 1533 if (mask & XPSR_NZCV) { 1534 env->ZF = (~val) & XPSR_Z; 1535 env->NF = val; 1536 env->CF = (val >> 29) & 1; 1537 env->VF = (val << 3) & 0x80000000; 1538 } 1539 if (mask & XPSR_Q) { 1540 env->QF = ((val & XPSR_Q) != 0); 1541 } 1542 if (mask & XPSR_GE) { 1543 env->GE = (val & XPSR_GE) >> 16; 1544 } 1545 #ifndef CONFIG_USER_ONLY 1546 if (mask & XPSR_T) { 1547 env->thumb = ((val & XPSR_T) != 0); 1548 } 1549 if (mask & XPSR_IT_0_1) { 1550 env->condexec_bits &= ~3; 1551 env->condexec_bits |= (val >> 25) & 3; 1552 } 1553 if (mask & XPSR_IT_2_7) { 1554 env->condexec_bits &= 3; 1555 env->condexec_bits |= (val >> 8) & 0xfc; 1556 } 1557 if (mask & XPSR_EXCP) { 1558 /* Note that this only happens on exception exit */ 1559 write_v7m_exception(env, val & XPSR_EXCP); 1560 } 1561 #endif 1562 } 1563 1564 #define HCR_VM (1ULL << 0) 1565 #define HCR_SWIO (1ULL << 1) 1566 #define HCR_PTW (1ULL << 2) 1567 #define HCR_FMO (1ULL << 3) 1568 #define HCR_IMO (1ULL << 4) 1569 #define HCR_AMO (1ULL << 5) 1570 #define HCR_VF (1ULL << 6) 1571 #define HCR_VI (1ULL << 7) 1572 #define HCR_VSE (1ULL << 8) 1573 #define HCR_FB (1ULL << 9) 1574 #define HCR_BSU_MASK (3ULL << 10) 1575 #define HCR_DC (1ULL << 12) 1576 #define HCR_TWI (1ULL << 13) 1577 #define HCR_TWE (1ULL << 14) 1578 #define HCR_TID0 (1ULL << 15) 1579 #define HCR_TID1 (1ULL << 16) 1580 #define HCR_TID2 (1ULL << 17) 1581 #define HCR_TID3 (1ULL << 18) 1582 #define HCR_TSC (1ULL << 19) 1583 #define HCR_TIDCP (1ULL << 20) 1584 #define HCR_TACR (1ULL << 21) 1585 #define HCR_TSW (1ULL << 22) 1586 #define HCR_TPCP (1ULL << 23) 1587 #define HCR_TPU (1ULL << 24) 1588 #define HCR_TTLB (1ULL << 25) 1589 #define HCR_TVM (1ULL << 26) 1590 #define HCR_TGE (1ULL << 27) 1591 #define HCR_TDZ (1ULL << 28) 1592 #define HCR_HCD (1ULL << 29) 1593 #define HCR_TRVM (1ULL << 30) 1594 #define HCR_RW (1ULL << 31) 1595 #define HCR_CD (1ULL << 32) 1596 #define HCR_ID (1ULL << 33) 1597 #define HCR_E2H (1ULL << 34) 1598 #define HCR_TLOR (1ULL << 35) 1599 #define HCR_TERR (1ULL << 36) 1600 #define HCR_TEA (1ULL << 37) 1601 #define HCR_MIOCNCE (1ULL << 38) 1602 /* RES0 bit 39 */ 1603 #define HCR_APK (1ULL << 40) 1604 #define HCR_API (1ULL << 41) 1605 #define HCR_NV (1ULL << 42) 1606 #define HCR_NV1 (1ULL << 43) 1607 #define HCR_AT (1ULL << 44) 1608 #define HCR_NV2 (1ULL << 45) 1609 #define HCR_FWB (1ULL << 46) 1610 #define HCR_FIEN (1ULL << 47) 1611 /* RES0 bit 48 */ 1612 #define HCR_TID4 (1ULL << 49) 1613 #define HCR_TICAB (1ULL << 50) 1614 #define HCR_AMVOFFEN (1ULL << 51) 1615 #define HCR_TOCU (1ULL << 52) 1616 #define HCR_ENSCXT (1ULL << 53) 1617 #define HCR_TTLBIS (1ULL << 54) 1618 #define HCR_TTLBOS (1ULL << 55) 1619 #define HCR_ATA (1ULL << 56) 1620 #define HCR_DCT (1ULL << 57) 1621 #define HCR_TID5 (1ULL << 58) 1622 #define HCR_TWEDEN (1ULL << 59) 1623 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1624 1625 #define HCRX_ENAS0 (1ULL << 0) 1626 #define HCRX_ENALS (1ULL << 1) 1627 #define HCRX_ENASR (1ULL << 2) 1628 #define HCRX_FNXS (1ULL << 3) 1629 #define HCRX_FGTNXS (1ULL << 4) 1630 #define HCRX_SMPME (1ULL << 5) 1631 #define HCRX_TALLINT (1ULL << 6) 1632 #define HCRX_VINMI (1ULL << 7) 1633 #define HCRX_VFNMI (1ULL << 8) 1634 #define HCRX_CMOW (1ULL << 9) 1635 #define HCRX_MCE2 (1ULL << 10) 1636 #define HCRX_MSCEN (1ULL << 11) 1637 1638 #define HPFAR_NS (1ULL << 63) 1639 1640 #define SCR_NS (1U << 0) 1641 #define SCR_IRQ (1U << 1) 1642 #define SCR_FIQ (1U << 2) 1643 #define SCR_EA (1U << 3) 1644 #define SCR_FW (1U << 4) 1645 #define SCR_AW (1U << 5) 1646 #define SCR_NET (1U << 6) 1647 #define SCR_SMD (1U << 7) 1648 #define SCR_HCE (1U << 8) 1649 #define SCR_SIF (1U << 9) 1650 #define SCR_RW (1U << 10) 1651 #define SCR_ST (1U << 11) 1652 #define SCR_TWI (1U << 12) 1653 #define SCR_TWE (1U << 13) 1654 #define SCR_TLOR (1U << 14) 1655 #define SCR_TERR (1U << 15) 1656 #define SCR_APK (1U << 16) 1657 #define SCR_API (1U << 17) 1658 #define SCR_EEL2 (1U << 18) 1659 #define SCR_EASE (1U << 19) 1660 #define SCR_NMEA (1U << 20) 1661 #define SCR_FIEN (1U << 21) 1662 #define SCR_ENSCXT (1U << 25) 1663 #define SCR_ATA (1U << 26) 1664 #define SCR_FGTEN (1U << 27) 1665 #define SCR_ECVEN (1U << 28) 1666 #define SCR_TWEDEN (1U << 29) 1667 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1668 #define SCR_TME (1ULL << 34) 1669 #define SCR_AMVOFFEN (1ULL << 35) 1670 #define SCR_ENAS0 (1ULL << 36) 1671 #define SCR_ADEN (1ULL << 37) 1672 #define SCR_HXEN (1ULL << 38) 1673 #define SCR_TRNDR (1ULL << 40) 1674 #define SCR_ENTP2 (1ULL << 41) 1675 #define SCR_GPF (1ULL << 48) 1676 1677 #define HSTR_TTEE (1 << 16) 1678 #define HSTR_TJDBX (1 << 17) 1679 1680 /* Return the current FPSCR value. */ 1681 uint32_t vfp_get_fpscr(CPUARMState *env); 1682 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1683 1684 /* FPCR, Floating Point Control Register 1685 * FPSR, Floating Poiht Status Register 1686 * 1687 * For A64 the FPSCR is split into two logically distinct registers, 1688 * FPCR and FPSR. However since they still use non-overlapping bits 1689 * we store the underlying state in fpscr and just mask on read/write. 1690 */ 1691 #define FPSR_MASK 0xf800009f 1692 #define FPCR_MASK 0x07ff9f00 1693 1694 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1695 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1696 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1697 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1698 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1699 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1700 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1701 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1702 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1703 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1704 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1705 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1706 #define FPCR_V (1 << 28) /* FP overflow flag */ 1707 #define FPCR_C (1 << 29) /* FP carry flag */ 1708 #define FPCR_Z (1 << 30) /* FP zero flag */ 1709 #define FPCR_N (1 << 31) /* FP negative flag */ 1710 1711 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1712 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1713 #define FPCR_LTPSIZE_LENGTH 3 1714 1715 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1716 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1717 1718 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1719 { 1720 return vfp_get_fpscr(env) & FPSR_MASK; 1721 } 1722 1723 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1724 { 1725 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1726 vfp_set_fpscr(env, new_fpscr); 1727 } 1728 1729 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1730 { 1731 return vfp_get_fpscr(env) & FPCR_MASK; 1732 } 1733 1734 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1735 { 1736 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1737 vfp_set_fpscr(env, new_fpscr); 1738 } 1739 1740 enum arm_cpu_mode { 1741 ARM_CPU_MODE_USR = 0x10, 1742 ARM_CPU_MODE_FIQ = 0x11, 1743 ARM_CPU_MODE_IRQ = 0x12, 1744 ARM_CPU_MODE_SVC = 0x13, 1745 ARM_CPU_MODE_MON = 0x16, 1746 ARM_CPU_MODE_ABT = 0x17, 1747 ARM_CPU_MODE_HYP = 0x1a, 1748 ARM_CPU_MODE_UND = 0x1b, 1749 ARM_CPU_MODE_SYS = 0x1f 1750 }; 1751 1752 /* VFP system registers. */ 1753 #define ARM_VFP_FPSID 0 1754 #define ARM_VFP_FPSCR 1 1755 #define ARM_VFP_MVFR2 5 1756 #define ARM_VFP_MVFR1 6 1757 #define ARM_VFP_MVFR0 7 1758 #define ARM_VFP_FPEXC 8 1759 #define ARM_VFP_FPINST 9 1760 #define ARM_VFP_FPINST2 10 1761 /* These ones are M-profile only */ 1762 #define ARM_VFP_FPSCR_NZCVQC 2 1763 #define ARM_VFP_VPR 12 1764 #define ARM_VFP_P0 13 1765 #define ARM_VFP_FPCXT_NS 14 1766 #define ARM_VFP_FPCXT_S 15 1767 1768 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1769 #define QEMU_VFP_FPSCR_NZCV 0xffff 1770 1771 /* iwMMXt coprocessor control registers. */ 1772 #define ARM_IWMMXT_wCID 0 1773 #define ARM_IWMMXT_wCon 1 1774 #define ARM_IWMMXT_wCSSF 2 1775 #define ARM_IWMMXT_wCASF 3 1776 #define ARM_IWMMXT_wCGR0 8 1777 #define ARM_IWMMXT_wCGR1 9 1778 #define ARM_IWMMXT_wCGR2 10 1779 #define ARM_IWMMXT_wCGR3 11 1780 1781 /* V7M CCR bits */ 1782 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1783 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1784 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1785 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1786 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1787 FIELD(V7M_CCR, STKALIGN, 9, 1) 1788 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1789 FIELD(V7M_CCR, DC, 16, 1) 1790 FIELD(V7M_CCR, IC, 17, 1) 1791 FIELD(V7M_CCR, BP, 18, 1) 1792 FIELD(V7M_CCR, LOB, 19, 1) 1793 FIELD(V7M_CCR, TRD, 20, 1) 1794 1795 /* V7M SCR bits */ 1796 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1797 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1798 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1799 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1800 1801 /* V7M AIRCR bits */ 1802 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1803 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1804 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1805 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1806 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1807 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1808 FIELD(V7M_AIRCR, PRIS, 14, 1) 1809 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1810 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1811 1812 /* V7M CFSR bits for MMFSR */ 1813 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1814 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1815 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1816 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1817 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1818 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1819 1820 /* V7M CFSR bits for BFSR */ 1821 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1822 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1823 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1824 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1825 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1826 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1827 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1828 1829 /* V7M CFSR bits for UFSR */ 1830 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1831 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1832 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1833 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1834 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1835 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1836 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1837 1838 /* V7M CFSR bit masks covering all of the subregister bits */ 1839 FIELD(V7M_CFSR, MMFSR, 0, 8) 1840 FIELD(V7M_CFSR, BFSR, 8, 8) 1841 FIELD(V7M_CFSR, UFSR, 16, 16) 1842 1843 /* V7M HFSR bits */ 1844 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1845 FIELD(V7M_HFSR, FORCED, 30, 1) 1846 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1847 1848 /* V7M DFSR bits */ 1849 FIELD(V7M_DFSR, HALTED, 0, 1) 1850 FIELD(V7M_DFSR, BKPT, 1, 1) 1851 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1852 FIELD(V7M_DFSR, VCATCH, 3, 1) 1853 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1854 1855 /* V7M SFSR bits */ 1856 FIELD(V7M_SFSR, INVEP, 0, 1) 1857 FIELD(V7M_SFSR, INVIS, 1, 1) 1858 FIELD(V7M_SFSR, INVER, 2, 1) 1859 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1860 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1861 FIELD(V7M_SFSR, LSPERR, 5, 1) 1862 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1863 FIELD(V7M_SFSR, LSERR, 7, 1) 1864 1865 /* v7M MPU_CTRL bits */ 1866 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1867 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1868 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1869 1870 /* v7M CLIDR bits */ 1871 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1872 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1873 FIELD(V7M_CLIDR, LOC, 24, 3) 1874 FIELD(V7M_CLIDR, LOUU, 27, 3) 1875 FIELD(V7M_CLIDR, ICB, 30, 2) 1876 1877 FIELD(V7M_CSSELR, IND, 0, 1) 1878 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1879 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1880 * define a mask for this and check that it doesn't permit running off 1881 * the end of the array. 1882 */ 1883 FIELD(V7M_CSSELR, INDEX, 0, 4) 1884 1885 /* v7M FPCCR bits */ 1886 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1887 FIELD(V7M_FPCCR, USER, 1, 1) 1888 FIELD(V7M_FPCCR, S, 2, 1) 1889 FIELD(V7M_FPCCR, THREAD, 3, 1) 1890 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1891 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1892 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1893 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1894 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1895 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1896 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1897 FIELD(V7M_FPCCR, RES0, 11, 15) 1898 FIELD(V7M_FPCCR, TS, 26, 1) 1899 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1900 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1901 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1902 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1903 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1904 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1905 #define R_V7M_FPCCR_BANKED_MASK \ 1906 (R_V7M_FPCCR_LSPACT_MASK | \ 1907 R_V7M_FPCCR_USER_MASK | \ 1908 R_V7M_FPCCR_THREAD_MASK | \ 1909 R_V7M_FPCCR_MMRDY_MASK | \ 1910 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1911 R_V7M_FPCCR_UFRDY_MASK | \ 1912 R_V7M_FPCCR_ASPEN_MASK) 1913 1914 /* v7M VPR bits */ 1915 FIELD(V7M_VPR, P0, 0, 16) 1916 FIELD(V7M_VPR, MASK01, 16, 4) 1917 FIELD(V7M_VPR, MASK23, 20, 4) 1918 1919 /* 1920 * System register ID fields. 1921 */ 1922 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1923 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1924 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1925 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1926 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1927 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1928 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1929 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1930 FIELD(CLIDR_EL1, LOC, 24, 3) 1931 FIELD(CLIDR_EL1, LOUU, 27, 3) 1932 FIELD(CLIDR_EL1, ICB, 30, 3) 1933 1934 /* When FEAT_CCIDX is implemented */ 1935 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1936 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1937 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1938 1939 /* When FEAT_CCIDX is not implemented */ 1940 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1941 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1942 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1943 1944 FIELD(CTR_EL0, IMINLINE, 0, 4) 1945 FIELD(CTR_EL0, L1IP, 14, 2) 1946 FIELD(CTR_EL0, DMINLINE, 16, 4) 1947 FIELD(CTR_EL0, ERG, 20, 4) 1948 FIELD(CTR_EL0, CWG, 24, 4) 1949 FIELD(CTR_EL0, IDC, 28, 1) 1950 FIELD(CTR_EL0, DIC, 29, 1) 1951 FIELD(CTR_EL0, TMINLINE, 32, 6) 1952 1953 FIELD(MIDR_EL1, REVISION, 0, 4) 1954 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1955 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1956 FIELD(MIDR_EL1, VARIANT, 20, 4) 1957 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1958 1959 FIELD(ID_ISAR0, SWAP, 0, 4) 1960 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1961 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1962 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1963 FIELD(ID_ISAR0, COPROC, 16, 4) 1964 FIELD(ID_ISAR0, DEBUG, 20, 4) 1965 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1966 1967 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1968 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1969 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1970 FIELD(ID_ISAR1, EXTEND, 12, 4) 1971 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1972 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1973 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1974 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1975 1976 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1977 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1978 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1979 FIELD(ID_ISAR2, MULT, 12, 4) 1980 FIELD(ID_ISAR2, MULTS, 16, 4) 1981 FIELD(ID_ISAR2, MULTU, 20, 4) 1982 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1983 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1984 1985 FIELD(ID_ISAR3, SATURATE, 0, 4) 1986 FIELD(ID_ISAR3, SIMD, 4, 4) 1987 FIELD(ID_ISAR3, SVC, 8, 4) 1988 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1989 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1990 FIELD(ID_ISAR3, T32COPY, 20, 4) 1991 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1992 FIELD(ID_ISAR3, T32EE, 28, 4) 1993 1994 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1995 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1996 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1997 FIELD(ID_ISAR4, SMC, 12, 4) 1998 FIELD(ID_ISAR4, BARRIER, 16, 4) 1999 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2000 FIELD(ID_ISAR4, PSR_M, 24, 4) 2001 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2002 2003 FIELD(ID_ISAR5, SEVL, 0, 4) 2004 FIELD(ID_ISAR5, AES, 4, 4) 2005 FIELD(ID_ISAR5, SHA1, 8, 4) 2006 FIELD(ID_ISAR5, SHA2, 12, 4) 2007 FIELD(ID_ISAR5, CRC32, 16, 4) 2008 FIELD(ID_ISAR5, RDM, 24, 4) 2009 FIELD(ID_ISAR5, VCMA, 28, 4) 2010 2011 FIELD(ID_ISAR6, JSCVT, 0, 4) 2012 FIELD(ID_ISAR6, DP, 4, 4) 2013 FIELD(ID_ISAR6, FHM, 8, 4) 2014 FIELD(ID_ISAR6, SB, 12, 4) 2015 FIELD(ID_ISAR6, SPECRES, 16, 4) 2016 FIELD(ID_ISAR6, BF16, 20, 4) 2017 FIELD(ID_ISAR6, I8MM, 24, 4) 2018 2019 FIELD(ID_MMFR0, VMSA, 0, 4) 2020 FIELD(ID_MMFR0, PMSA, 4, 4) 2021 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2022 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2023 FIELD(ID_MMFR0, TCM, 16, 4) 2024 FIELD(ID_MMFR0, AUXREG, 20, 4) 2025 FIELD(ID_MMFR0, FCSE, 24, 4) 2026 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2027 2028 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2029 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2030 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2031 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2032 FIELD(ID_MMFR1, L1HVD, 16, 4) 2033 FIELD(ID_MMFR1, L1UNI, 20, 4) 2034 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2035 FIELD(ID_MMFR1, BPRED, 28, 4) 2036 2037 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2038 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2039 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2040 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2041 FIELD(ID_MMFR2, UNITLB, 16, 4) 2042 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2043 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2044 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2045 2046 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2047 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2048 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2049 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2050 FIELD(ID_MMFR3, PAN, 16, 4) 2051 FIELD(ID_MMFR3, COHWALK, 20, 4) 2052 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2053 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2054 2055 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2056 FIELD(ID_MMFR4, AC2, 4, 4) 2057 FIELD(ID_MMFR4, XNX, 8, 4) 2058 FIELD(ID_MMFR4, CNP, 12, 4) 2059 FIELD(ID_MMFR4, HPDS, 16, 4) 2060 FIELD(ID_MMFR4, LSM, 20, 4) 2061 FIELD(ID_MMFR4, CCIDX, 24, 4) 2062 FIELD(ID_MMFR4, EVT, 28, 4) 2063 2064 FIELD(ID_MMFR5, ETS, 0, 4) 2065 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2066 2067 FIELD(ID_PFR0, STATE0, 0, 4) 2068 FIELD(ID_PFR0, STATE1, 4, 4) 2069 FIELD(ID_PFR0, STATE2, 8, 4) 2070 FIELD(ID_PFR0, STATE3, 12, 4) 2071 FIELD(ID_PFR0, CSV2, 16, 4) 2072 FIELD(ID_PFR0, AMU, 20, 4) 2073 FIELD(ID_PFR0, DIT, 24, 4) 2074 FIELD(ID_PFR0, RAS, 28, 4) 2075 2076 FIELD(ID_PFR1, PROGMOD, 0, 4) 2077 FIELD(ID_PFR1, SECURITY, 4, 4) 2078 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2079 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2080 FIELD(ID_PFR1, GENTIMER, 16, 4) 2081 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2082 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2083 FIELD(ID_PFR1, GIC, 28, 4) 2084 2085 FIELD(ID_PFR2, CSV3, 0, 4) 2086 FIELD(ID_PFR2, SSBS, 4, 4) 2087 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2088 2089 FIELD(ID_AA64ISAR0, AES, 4, 4) 2090 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2091 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2092 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2093 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2094 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2095 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2096 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2097 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2098 FIELD(ID_AA64ISAR0, DP, 44, 4) 2099 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2100 FIELD(ID_AA64ISAR0, TS, 52, 4) 2101 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2102 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2103 2104 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2105 FIELD(ID_AA64ISAR1, APA, 4, 4) 2106 FIELD(ID_AA64ISAR1, API, 8, 4) 2107 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2108 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2109 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2110 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2111 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2112 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2113 FIELD(ID_AA64ISAR1, SB, 36, 4) 2114 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2115 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2116 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2117 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2118 FIELD(ID_AA64ISAR1, XS, 56, 4) 2119 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2120 2121 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2122 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2123 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2124 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2125 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2126 FIELD(ID_AA64ISAR2, BC, 20, 4) 2127 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2128 2129 FIELD(ID_AA64PFR0, EL0, 0, 4) 2130 FIELD(ID_AA64PFR0, EL1, 4, 4) 2131 FIELD(ID_AA64PFR0, EL2, 8, 4) 2132 FIELD(ID_AA64PFR0, EL3, 12, 4) 2133 FIELD(ID_AA64PFR0, FP, 16, 4) 2134 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2135 FIELD(ID_AA64PFR0, GIC, 24, 4) 2136 FIELD(ID_AA64PFR0, RAS, 28, 4) 2137 FIELD(ID_AA64PFR0, SVE, 32, 4) 2138 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2139 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2140 FIELD(ID_AA64PFR0, AMU, 44, 4) 2141 FIELD(ID_AA64PFR0, DIT, 48, 4) 2142 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2143 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2144 2145 FIELD(ID_AA64PFR1, BT, 0, 4) 2146 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2147 FIELD(ID_AA64PFR1, MTE, 8, 4) 2148 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2149 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2150 FIELD(ID_AA64PFR1, SME, 24, 4) 2151 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2152 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2153 FIELD(ID_AA64PFR1, NMI, 36, 4) 2154 2155 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2156 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2157 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2158 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2159 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2160 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2161 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2162 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2163 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2164 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2165 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2166 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2167 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2168 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2169 2170 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2171 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2172 FIELD(ID_AA64MMFR1, VH, 8, 4) 2173 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2174 FIELD(ID_AA64MMFR1, LO, 16, 4) 2175 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2176 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2177 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2178 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2179 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2180 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2181 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2182 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2183 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2184 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2185 2186 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2187 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2188 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2189 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2190 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2191 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2192 FIELD(ID_AA64MMFR2, NV, 24, 4) 2193 FIELD(ID_AA64MMFR2, ST, 28, 4) 2194 FIELD(ID_AA64MMFR2, AT, 32, 4) 2195 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2196 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2197 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2198 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2199 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2200 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2201 2202 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2203 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2204 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2205 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2206 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2207 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2208 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2209 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2210 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2211 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2212 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2213 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2214 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2215 2216 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2217 FIELD(ID_AA64ZFR0, AES, 4, 4) 2218 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2219 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2220 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2221 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2222 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2223 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2224 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2225 2226 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2227 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2228 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2229 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2230 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2231 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2232 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2233 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2234 2235 FIELD(ID_DFR0, COPDBG, 0, 4) 2236 FIELD(ID_DFR0, COPSDBG, 4, 4) 2237 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2238 FIELD(ID_DFR0, COPTRC, 12, 4) 2239 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2240 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2241 FIELD(ID_DFR0, PERFMON, 24, 4) 2242 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2243 2244 FIELD(ID_DFR1, MTPMU, 0, 4) 2245 FIELD(ID_DFR1, HPMN0, 4, 4) 2246 2247 FIELD(DBGDIDR, SE_IMP, 12, 1) 2248 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2249 FIELD(DBGDIDR, VERSION, 16, 4) 2250 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2251 FIELD(DBGDIDR, BRPS, 24, 4) 2252 FIELD(DBGDIDR, WRPS, 28, 4) 2253 2254 FIELD(MVFR0, SIMDREG, 0, 4) 2255 FIELD(MVFR0, FPSP, 4, 4) 2256 FIELD(MVFR0, FPDP, 8, 4) 2257 FIELD(MVFR0, FPTRAP, 12, 4) 2258 FIELD(MVFR0, FPDIVIDE, 16, 4) 2259 FIELD(MVFR0, FPSQRT, 20, 4) 2260 FIELD(MVFR0, FPSHVEC, 24, 4) 2261 FIELD(MVFR0, FPROUND, 28, 4) 2262 2263 FIELD(MVFR1, FPFTZ, 0, 4) 2264 FIELD(MVFR1, FPDNAN, 4, 4) 2265 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2266 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2267 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2268 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2269 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2270 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2271 FIELD(MVFR1, FPHP, 24, 4) 2272 FIELD(MVFR1, SIMDFMAC, 28, 4) 2273 2274 FIELD(MVFR2, SIMDMISC, 0, 4) 2275 FIELD(MVFR2, FPMISC, 4, 4) 2276 2277 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2278 2279 /* If adding a feature bit which corresponds to a Linux ELF 2280 * HWCAP bit, remember to update the feature-bit-to-hwcap 2281 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2282 */ 2283 enum arm_features { 2284 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2285 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2286 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2287 ARM_FEATURE_V6, 2288 ARM_FEATURE_V6K, 2289 ARM_FEATURE_V7, 2290 ARM_FEATURE_THUMB2, 2291 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2292 ARM_FEATURE_NEON, 2293 ARM_FEATURE_M, /* Microcontroller profile. */ 2294 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2295 ARM_FEATURE_THUMB2EE, 2296 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2297 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2298 ARM_FEATURE_V4T, 2299 ARM_FEATURE_V5, 2300 ARM_FEATURE_STRONGARM, 2301 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2302 ARM_FEATURE_GENERIC_TIMER, 2303 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2304 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2305 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2306 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2307 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2308 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2309 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2310 ARM_FEATURE_V8, 2311 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2312 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2313 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2314 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2315 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2316 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2317 ARM_FEATURE_PMU, /* has PMU support */ 2318 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2319 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2320 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2321 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2322 }; 2323 2324 static inline int arm_feature(CPUARMState *env, int feature) 2325 { 2326 return (env->features & (1ULL << feature)) != 0; 2327 } 2328 2329 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2330 2331 #if !defined(CONFIG_USER_ONLY) 2332 /* Return true if exception levels below EL3 are in secure state, 2333 * or would be following an exception return to that level. 2334 * Unlike arm_is_secure() (which is always a question about the 2335 * _current_ state of the CPU) this doesn't care about the current 2336 * EL or mode. 2337 */ 2338 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2339 { 2340 if (arm_feature(env, ARM_FEATURE_EL3)) { 2341 return !(env->cp15.scr_el3 & SCR_NS); 2342 } else { 2343 /* If EL3 is not supported then the secure state is implementation 2344 * defined, in which case QEMU defaults to non-secure. 2345 */ 2346 return false; 2347 } 2348 } 2349 2350 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2351 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2352 { 2353 if (arm_feature(env, ARM_FEATURE_EL3)) { 2354 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2355 /* CPU currently in AArch64 state and EL3 */ 2356 return true; 2357 } else if (!is_a64(env) && 2358 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2359 /* CPU currently in AArch32 state and monitor mode */ 2360 return true; 2361 } 2362 } 2363 return false; 2364 } 2365 2366 /* Return true if the processor is in secure state */ 2367 static inline bool arm_is_secure(CPUARMState *env) 2368 { 2369 if (arm_is_el3_or_mon(env)) { 2370 return true; 2371 } 2372 return arm_is_secure_below_el3(env); 2373 } 2374 2375 /* 2376 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2377 * This corresponds to the pseudocode EL2Enabled() 2378 */ 2379 static inline bool arm_is_el2_enabled(CPUARMState *env) 2380 { 2381 if (arm_feature(env, ARM_FEATURE_EL2)) { 2382 if (arm_is_secure_below_el3(env)) { 2383 return (env->cp15.scr_el3 & SCR_EEL2) != 0; 2384 } 2385 return true; 2386 } 2387 return false; 2388 } 2389 2390 #else 2391 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2392 { 2393 return false; 2394 } 2395 2396 static inline bool arm_is_secure(CPUARMState *env) 2397 { 2398 return false; 2399 } 2400 2401 static inline bool arm_is_el2_enabled(CPUARMState *env) 2402 { 2403 return false; 2404 } 2405 #endif 2406 2407 /** 2408 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2409 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2410 * "for all purposes other than a direct read or write access of HCR_EL2." 2411 * Not included here is HCR_RW. 2412 */ 2413 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2414 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2415 2416 /* Return true if the specified exception level is running in AArch64 state. */ 2417 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2418 { 2419 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2420 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2421 */ 2422 assert(el >= 1 && el <= 3); 2423 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2424 2425 /* The highest exception level is always at the maximum supported 2426 * register width, and then lower levels have a register width controlled 2427 * by bits in the SCR or HCR registers. 2428 */ 2429 if (el == 3) { 2430 return aa64; 2431 } 2432 2433 if (arm_feature(env, ARM_FEATURE_EL3) && 2434 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2435 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2436 } 2437 2438 if (el == 2) { 2439 return aa64; 2440 } 2441 2442 if (arm_is_el2_enabled(env)) { 2443 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2444 } 2445 2446 return aa64; 2447 } 2448 2449 /* Function for determing whether guest cp register reads and writes should 2450 * access the secure or non-secure bank of a cp register. When EL3 is 2451 * operating in AArch32 state, the NS-bit determines whether the secure 2452 * instance of a cp register should be used. When EL3 is AArch64 (or if 2453 * it doesn't exist at all) then there is no register banking, and all 2454 * accesses are to the non-secure version. 2455 */ 2456 static inline bool access_secure_reg(CPUARMState *env) 2457 { 2458 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2459 !arm_el_is_aa64(env, 3) && 2460 !(env->cp15.scr_el3 & SCR_NS)); 2461 2462 return ret; 2463 } 2464 2465 /* Macros for accessing a specified CP register bank */ 2466 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2467 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2468 2469 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2470 do { \ 2471 if (_secure) { \ 2472 (_env)->cp15._regname##_s = (_val); \ 2473 } else { \ 2474 (_env)->cp15._regname##_ns = (_val); \ 2475 } \ 2476 } while (0) 2477 2478 /* Macros for automatically accessing a specific CP register bank depending on 2479 * the current secure state of the system. These macros are not intended for 2480 * supporting instruction translation reads/writes as these are dependent 2481 * solely on the SCR.NS bit and not the mode. 2482 */ 2483 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2484 A32_BANKED_REG_GET((_env), _regname, \ 2485 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2486 2487 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2488 A32_BANKED_REG_SET((_env), _regname, \ 2489 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2490 (_val)) 2491 2492 void arm_cpu_list(void); 2493 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2494 uint32_t cur_el, bool secure); 2495 2496 /* Interface between CPU and Interrupt controller. */ 2497 #ifndef CONFIG_USER_ONLY 2498 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2499 #else 2500 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2501 { 2502 return true; 2503 } 2504 #endif 2505 /** 2506 * armv7m_nvic_set_pending: mark the specified exception as pending 2507 * @opaque: the NVIC 2508 * @irq: the exception number to mark pending 2509 * @secure: false for non-banked exceptions or for the nonsecure 2510 * version of a banked exception, true for the secure version of a banked 2511 * exception. 2512 * 2513 * Marks the specified exception as pending. Note that we will assert() 2514 * if @secure is true and @irq does not specify one of the fixed set 2515 * of architecturally banked exceptions. 2516 */ 2517 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2518 /** 2519 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2520 * @opaque: the NVIC 2521 * @irq: the exception number to mark pending 2522 * @secure: false for non-banked exceptions or for the nonsecure 2523 * version of a banked exception, true for the secure version of a banked 2524 * exception. 2525 * 2526 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2527 * exceptions (exceptions generated in the course of trying to take 2528 * a different exception). 2529 */ 2530 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2531 /** 2532 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2533 * @opaque: the NVIC 2534 * @irq: the exception number to mark pending 2535 * @secure: false for non-banked exceptions or for the nonsecure 2536 * version of a banked exception, true for the secure version of a banked 2537 * exception. 2538 * 2539 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2540 * generated in the course of lazy stacking of FP registers. 2541 */ 2542 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2543 /** 2544 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2545 * exception, and whether it targets Secure state 2546 * @opaque: the NVIC 2547 * @pirq: set to pending exception number 2548 * @ptargets_secure: set to whether pending exception targets Secure 2549 * 2550 * This function writes the number of the highest priority pending 2551 * exception (the one which would be made active by 2552 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2553 * to true if the current highest priority pending exception should 2554 * be taken to Secure state, false for NS. 2555 */ 2556 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2557 bool *ptargets_secure); 2558 /** 2559 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2560 * @opaque: the NVIC 2561 * 2562 * Move the current highest priority pending exception from the pending 2563 * state to the active state, and update v7m.exception to indicate that 2564 * it is the exception currently being handled. 2565 */ 2566 void armv7m_nvic_acknowledge_irq(void *opaque); 2567 /** 2568 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2569 * @opaque: the NVIC 2570 * @irq: the exception number to complete 2571 * @secure: true if this exception was secure 2572 * 2573 * Returns: -1 if the irq was not active 2574 * 1 if completing this irq brought us back to base (no active irqs) 2575 * 0 if there is still an irq active after this one was completed 2576 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2577 */ 2578 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2579 /** 2580 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2581 * @opaque: the NVIC 2582 * @irq: the exception number to mark pending 2583 * @secure: false for non-banked exceptions or for the nonsecure 2584 * version of a banked exception, true for the secure version of a banked 2585 * exception. 2586 * 2587 * Return whether an exception is "ready", i.e. whether the exception is 2588 * enabled and is configured at a priority which would allow it to 2589 * interrupt the current execution priority. This controls whether the 2590 * RDY bit for it in the FPCCR is set. 2591 */ 2592 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2593 /** 2594 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2595 * @opaque: the NVIC 2596 * 2597 * Returns: the raw execution priority as defined by the v8M architecture. 2598 * This is the execution priority minus the effects of AIRCR.PRIS, 2599 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2600 * (v8M ARM ARM I_PKLD.) 2601 */ 2602 int armv7m_nvic_raw_execution_priority(void *opaque); 2603 /** 2604 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2605 * priority is negative for the specified security state. 2606 * @opaque: the NVIC 2607 * @secure: the security state to test 2608 * This corresponds to the pseudocode IsReqExecPriNeg(). 2609 */ 2610 #ifndef CONFIG_USER_ONLY 2611 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2612 #else 2613 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2614 { 2615 return false; 2616 } 2617 #endif 2618 2619 /* Interface for defining coprocessor registers. 2620 * Registers are defined in tables of arm_cp_reginfo structs 2621 * which are passed to define_arm_cp_regs(). 2622 */ 2623 2624 /* When looking up a coprocessor register we look for it 2625 * via an integer which encodes all of: 2626 * coprocessor number 2627 * Crn, Crm, opc1, opc2 fields 2628 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2629 * or via MRRC/MCRR?) 2630 * non-secure/secure bank (AArch32 only) 2631 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2632 * (In this case crn and opc2 should be zero.) 2633 * For AArch64, there is no 32/64 bit size distinction; 2634 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2635 * and 4 bit CRn and CRm. The encoding patterns are chosen 2636 * to be easy to convert to and from the KVM encodings, and also 2637 * so that the hashtable can contain both AArch32 and AArch64 2638 * registers (to allow for interprocessing where we might run 2639 * 32 bit code on a 64 bit core). 2640 */ 2641 /* This bit is private to our hashtable cpreg; in KVM register 2642 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2643 * in the upper bits of the 64 bit ID. 2644 */ 2645 #define CP_REG_AA64_SHIFT 28 2646 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2647 2648 /* To enable banking of coprocessor registers depending on ns-bit we 2649 * add a bit to distinguish between secure and non-secure cpregs in the 2650 * hashtable. 2651 */ 2652 #define CP_REG_NS_SHIFT 29 2653 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2654 2655 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2656 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2657 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2658 2659 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2660 (CP_REG_AA64_MASK | \ 2661 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2662 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2663 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2664 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2665 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2666 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2667 2668 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2669 * version used as a key for the coprocessor register hashtable 2670 */ 2671 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2672 { 2673 uint32_t cpregid = kvmid; 2674 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2675 cpregid |= CP_REG_AA64_MASK; 2676 } else { 2677 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2678 cpregid |= (1 << 15); 2679 } 2680 2681 /* KVM is always non-secure so add the NS flag on AArch32 register 2682 * entries. 2683 */ 2684 cpregid |= 1 << CP_REG_NS_SHIFT; 2685 } 2686 return cpregid; 2687 } 2688 2689 /* Convert a truncated 32 bit hashtable key into the full 2690 * 64 bit KVM register ID. 2691 */ 2692 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2693 { 2694 uint64_t kvmid; 2695 2696 if (cpregid & CP_REG_AA64_MASK) { 2697 kvmid = cpregid & ~CP_REG_AA64_MASK; 2698 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2699 } else { 2700 kvmid = cpregid & ~(1 << 15); 2701 if (cpregid & (1 << 15)) { 2702 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2703 } else { 2704 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2705 } 2706 } 2707 return kvmid; 2708 } 2709 2710 /* Return the highest implemented Exception Level */ 2711 static inline int arm_highest_el(CPUARMState *env) 2712 { 2713 if (arm_feature(env, ARM_FEATURE_EL3)) { 2714 return 3; 2715 } 2716 if (arm_feature(env, ARM_FEATURE_EL2)) { 2717 return 2; 2718 } 2719 return 1; 2720 } 2721 2722 /* Return true if a v7M CPU is in Handler mode */ 2723 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2724 { 2725 return env->v7m.exception != 0; 2726 } 2727 2728 /* Return the current Exception Level (as per ARMv8; note that this differs 2729 * from the ARMv7 Privilege Level). 2730 */ 2731 static inline int arm_current_el(CPUARMState *env) 2732 { 2733 if (arm_feature(env, ARM_FEATURE_M)) { 2734 return arm_v7m_is_handler_mode(env) || 2735 !(env->v7m.control[env->v7m.secure] & 1); 2736 } 2737 2738 if (is_a64(env)) { 2739 return extract32(env->pstate, 2, 2); 2740 } 2741 2742 switch (env->uncached_cpsr & 0x1f) { 2743 case ARM_CPU_MODE_USR: 2744 return 0; 2745 case ARM_CPU_MODE_HYP: 2746 return 2; 2747 case ARM_CPU_MODE_MON: 2748 return 3; 2749 default: 2750 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2751 /* If EL3 is 32-bit then all secure privileged modes run in 2752 * EL3 2753 */ 2754 return 3; 2755 } 2756 2757 return 1; 2758 } 2759 } 2760 2761 /** 2762 * write_list_to_cpustate 2763 * @cpu: ARMCPU 2764 * 2765 * For each register listed in the ARMCPU cpreg_indexes list, write 2766 * its value from the cpreg_values list into the ARMCPUState structure. 2767 * This updates TCG's working data structures from KVM data or 2768 * from incoming migration state. 2769 * 2770 * Returns: true if all register values were updated correctly, 2771 * false if some register was unknown or could not be written. 2772 * Note that we do not stop early on failure -- we will attempt 2773 * writing all registers in the list. 2774 */ 2775 bool write_list_to_cpustate(ARMCPU *cpu); 2776 2777 /** 2778 * write_cpustate_to_list: 2779 * @cpu: ARMCPU 2780 * @kvm_sync: true if this is for syncing back to KVM 2781 * 2782 * For each register listed in the ARMCPU cpreg_indexes list, write 2783 * its value from the ARMCPUState structure into the cpreg_values list. 2784 * This is used to copy info from TCG's working data structures into 2785 * KVM or for outbound migration. 2786 * 2787 * @kvm_sync is true if we are doing this in order to sync the 2788 * register state back to KVM. In this case we will only update 2789 * values in the list if the previous list->cpustate sync actually 2790 * successfully wrote the CPU state. Otherwise we will keep the value 2791 * that is in the list. 2792 * 2793 * Returns: true if all register values were read correctly, 2794 * false if some register was unknown or could not be read. 2795 * Note that we do not stop early on failure -- we will attempt 2796 * reading all registers in the list. 2797 */ 2798 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2799 2800 #define ARM_CPUID_TI915T 0x54029152 2801 #define ARM_CPUID_TI925T 0x54029252 2802 2803 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2804 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2805 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2806 2807 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2808 2809 #define cpu_list arm_cpu_list 2810 2811 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2812 * 2813 * If EL3 is 64-bit: 2814 * + NonSecure EL1 & 0 stage 1 2815 * + NonSecure EL1 & 0 stage 2 2816 * + NonSecure EL2 2817 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2818 * + Secure EL1 & 0 2819 * + Secure EL3 2820 * If EL3 is 32-bit: 2821 * + NonSecure PL1 & 0 stage 1 2822 * + NonSecure PL1 & 0 stage 2 2823 * + NonSecure PL2 2824 * + Secure PL0 2825 * + Secure PL1 2826 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2827 * 2828 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2829 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2830 * because they may differ in access permissions even if the VA->PA map is 2831 * the same 2832 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2833 * translation, which means that we have one mmu_idx that deals with two 2834 * concatenated translation regimes [this sort of combined s1+2 TLB is 2835 * architecturally permitted] 2836 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2837 * handling via the TLB. The only way to do a stage 1 translation without 2838 * the immediate stage 2 translation is via the ATS or AT system insns, 2839 * which can be slow-pathed and always do a page table walk. 2840 * The only use of stage 2 translations is either as part of an s1+2 2841 * lookup or when loading the descriptors during a stage 1 page table walk, 2842 * and in both those cases we don't use the TLB. 2843 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2844 * translation regimes, because they map reasonably well to each other 2845 * and they can't both be active at the same time. 2846 * 5. we want to be able to use the TLB for accesses done as part of a 2847 * stage1 page table walk, rather than having to walk the stage2 page 2848 * table over and over. 2849 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2850 * Never (PAN) bit within PSTATE. 2851 * 2852 * This gives us the following list of cases: 2853 * 2854 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 2855 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 2856 * NS EL1 EL1&0 stage 1+2 +PAN 2857 * NS EL0 EL2&0 2858 * NS EL2 EL2&0 2859 * NS EL2 EL2&0 +PAN 2860 * NS EL2 (aka NS PL2) 2861 * S EL0 EL1&0 (aka S PL0) 2862 * S EL1 EL1&0 (not used if EL3 is 32 bit) 2863 * S EL1 EL1&0 +PAN 2864 * S EL3 (aka S PL1) 2865 * 2866 * for a total of 11 different mmu_idx. 2867 * 2868 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2869 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2870 * NS EL2 if we ever model a Cortex-R52). 2871 * 2872 * M profile CPUs are rather different as they do not have a true MMU. 2873 * They have the following different MMU indexes: 2874 * User 2875 * Privileged 2876 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2877 * Privileged, execution priority negative (ditto) 2878 * If the CPU supports the v8M Security Extension then there are also: 2879 * Secure User 2880 * Secure Privileged 2881 * Secure User, execution priority negative 2882 * Secure Privileged, execution priority negative 2883 * 2884 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2885 * are not quite the same -- different CPU types (most notably M profile 2886 * vs A/R profile) would like to use MMU indexes with different semantics, 2887 * but since we don't ever need to use all of those in a single CPU we 2888 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2889 * modes + total number of M profile MMU modes". The lower bits of 2890 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2891 * the same for any particular CPU. 2892 * Variables of type ARMMUIdx are always full values, and the core 2893 * index values are in variables of type 'int'. 2894 * 2895 * Our enumeration includes at the end some entries which are not "true" 2896 * mmu_idx values in that they don't have corresponding TLBs and are only 2897 * valid for doing slow path page table walks. 2898 * 2899 * The constant names here are patterned after the general style of the names 2900 * of the AT/ATS operations. 2901 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2902 * For M profile we arrange them to have a bit for priv, a bit for negpri 2903 * and a bit for secure. 2904 */ 2905 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2906 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2907 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2908 2909 /* Meanings of the bits for A profile mmu idx values */ 2910 #define ARM_MMU_IDX_A_NS 0x8 2911 2912 /* Meanings of the bits for M profile mmu idx values */ 2913 #define ARM_MMU_IDX_M_PRIV 0x1 2914 #define ARM_MMU_IDX_M_NEGPRI 0x2 2915 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2916 2917 #define ARM_MMU_IDX_TYPE_MASK \ 2918 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2919 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2920 2921 typedef enum ARMMMUIdx { 2922 /* 2923 * A-profile. 2924 */ 2925 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, 2926 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, 2927 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, 2928 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, 2929 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, 2930 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, 2931 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, 2932 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, 2933 2934 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, 2935 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, 2936 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, 2937 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, 2938 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, 2939 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, 2940 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, 2941 2942 /* 2943 * These are not allocated TLBs and are used only for AT system 2944 * instructions or for the first stage of an S12 page table walk. 2945 */ 2946 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2947 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2948 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2949 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, 2950 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, 2951 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, 2952 /* 2953 * Not allocated a TLB: used only for second stage of an S12 page 2954 * table walk, or for descriptor loads during first stage of an S1 2955 * page table walk. Note that if we ever want to have a TLB for this 2956 * then various TLB flush insns which currently are no-ops or flush 2957 * only stage 1 MMU indexes will need to change to flush stage 2. 2958 */ 2959 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, 2960 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, 2961 2962 /* 2963 * M-profile. 2964 */ 2965 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2966 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2967 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2968 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2969 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2970 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2971 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2972 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2973 } ARMMMUIdx; 2974 2975 /* 2976 * Bit macros for the core-mmu-index values for each index, 2977 * for use when calling tlb_flush_by_mmuidx() and friends. 2978 */ 2979 #define TO_CORE_BIT(NAME) \ 2980 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2981 2982 typedef enum ARMMMUIdxBit { 2983 TO_CORE_BIT(E10_0), 2984 TO_CORE_BIT(E20_0), 2985 TO_CORE_BIT(E10_1), 2986 TO_CORE_BIT(E10_1_PAN), 2987 TO_CORE_BIT(E2), 2988 TO_CORE_BIT(E20_2), 2989 TO_CORE_BIT(E20_2_PAN), 2990 TO_CORE_BIT(SE10_0), 2991 TO_CORE_BIT(SE20_0), 2992 TO_CORE_BIT(SE10_1), 2993 TO_CORE_BIT(SE20_2), 2994 TO_CORE_BIT(SE10_1_PAN), 2995 TO_CORE_BIT(SE20_2_PAN), 2996 TO_CORE_BIT(SE2), 2997 TO_CORE_BIT(SE3), 2998 2999 TO_CORE_BIT(MUser), 3000 TO_CORE_BIT(MPriv), 3001 TO_CORE_BIT(MUserNegPri), 3002 TO_CORE_BIT(MPrivNegPri), 3003 TO_CORE_BIT(MSUser), 3004 TO_CORE_BIT(MSPriv), 3005 TO_CORE_BIT(MSUserNegPri), 3006 TO_CORE_BIT(MSPrivNegPri), 3007 } ARMMMUIdxBit; 3008 3009 #undef TO_CORE_BIT 3010 3011 #define MMU_USER_IDX 0 3012 3013 /* Indexes used when registering address spaces with cpu_address_space_init */ 3014 typedef enum ARMASIdx { 3015 ARMASIdx_NS = 0, 3016 ARMASIdx_S = 1, 3017 ARMASIdx_TagNS = 2, 3018 ARMASIdx_TagS = 3, 3019 } ARMASIdx; 3020 3021 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3022 { 3023 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3024 * CSSELR is RAZ/WI. 3025 */ 3026 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3027 } 3028 3029 static inline bool arm_sctlr_b(CPUARMState *env) 3030 { 3031 return 3032 /* We need not implement SCTLR.ITD in user-mode emulation, so 3033 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3034 * This lets people run BE32 binaries with "-cpu any". 3035 */ 3036 #ifndef CONFIG_USER_ONLY 3037 !arm_feature(env, ARM_FEATURE_V7) && 3038 #endif 3039 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3040 } 3041 3042 uint64_t arm_sctlr(CPUARMState *env, int el); 3043 3044 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3045 bool sctlr_b) 3046 { 3047 #ifdef CONFIG_USER_ONLY 3048 /* 3049 * In system mode, BE32 is modelled in line with the 3050 * architecture (as word-invariant big-endianness), where loads 3051 * and stores are done little endian but from addresses which 3052 * are adjusted by XORing with the appropriate constant. So the 3053 * endianness to use for the raw data access is not affected by 3054 * SCTLR.B. 3055 * In user mode, however, we model BE32 as byte-invariant 3056 * big-endianness (because user-only code cannot tell the 3057 * difference), and so we need to use a data access endianness 3058 * that depends on SCTLR.B. 3059 */ 3060 if (sctlr_b) { 3061 return true; 3062 } 3063 #endif 3064 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3065 return env->uncached_cpsr & CPSR_E; 3066 } 3067 3068 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3069 { 3070 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3071 } 3072 3073 /* Return true if the processor is in big-endian mode. */ 3074 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3075 { 3076 if (!is_a64(env)) { 3077 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3078 } else { 3079 int cur_el = arm_current_el(env); 3080 uint64_t sctlr = arm_sctlr(env, cur_el); 3081 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3082 } 3083 } 3084 3085 #include "exec/cpu-all.h" 3086 3087 /* 3088 * We have more than 32-bits worth of state per TB, so we split the data 3089 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3090 * We collect these two parts in CPUARMTBFlags where they are named 3091 * flags and flags2 respectively. 3092 * 3093 * The flags that are shared between all execution modes, TBFLAG_ANY, 3094 * are stored in flags. The flags that are specific to a given mode 3095 * are stores in flags2. Since cs_base is sized on the configured 3096 * address size, flags2 always has 64-bits for A64, and a minimum of 3097 * 32-bits for A32 and M32. 3098 * 3099 * The bits for 32-bit A-profile and M-profile partially overlap: 3100 * 3101 * 31 23 11 10 0 3102 * +-------------+----------+----------------+ 3103 * | | | TBFLAG_A32 | 3104 * | TBFLAG_AM32 | +-----+----------+ 3105 * | | |TBFLAG_M32| 3106 * +-------------+----------------+----------+ 3107 * 31 23 6 5 0 3108 * 3109 * Unless otherwise noted, these bits are cached in env->hflags. 3110 */ 3111 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3112 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3113 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3114 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3115 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3116 /* Target EL if we take a floating-point-disabled exception */ 3117 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3118 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3119 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3120 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3121 3122 /* 3123 * Bit usage when in AArch32 state, both A- and M-profile. 3124 */ 3125 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3126 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3127 3128 /* 3129 * Bit usage when in AArch32 state, for A-profile only. 3130 */ 3131 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3132 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3133 /* 3134 * We store the bottom two bits of the CPAR as TB flags and handle 3135 * checks on the other bits at runtime. This shares the same bits as 3136 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3137 * Not cached, because VECLEN+VECSTRIDE are not cached. 3138 */ 3139 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3140 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3141 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3142 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3143 /* 3144 * Indicates whether cp register reads and writes by guest code should access 3145 * the secure or nonsecure bank of banked registers; note that this is not 3146 * the same thing as the current security state of the processor! 3147 */ 3148 FIELD(TBFLAG_A32, NS, 10, 1) 3149 3150 /* 3151 * Bit usage when in AArch32 state, for M-profile only. 3152 */ 3153 /* Handler (ie not Thread) mode */ 3154 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3155 /* Whether we should generate stack-limit checks */ 3156 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3157 /* Set if FPCCR.LSPACT is set */ 3158 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3159 /* Set if we must create a new FP context */ 3160 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3161 /* Set if FPCCR.S does not match current security state */ 3162 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3163 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3164 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3165 3166 /* 3167 * Bit usage when in AArch64 state 3168 */ 3169 FIELD(TBFLAG_A64, TBII, 0, 2) 3170 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3171 /* The current vector length, either NVL or SVL. */ 3172 FIELD(TBFLAG_A64, VL, 4, 4) 3173 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3174 FIELD(TBFLAG_A64, BT, 9, 1) 3175 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3176 FIELD(TBFLAG_A64, TBID, 12, 2) 3177 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3178 FIELD(TBFLAG_A64, ATA, 15, 1) 3179 FIELD(TBFLAG_A64, TCMA, 16, 2) 3180 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3181 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3182 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3183 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3184 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3185 FIELD(TBFLAG_A64, SVL, 24, 4) 3186 3187 /* 3188 * Helpers for using the above. 3189 */ 3190 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3191 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3192 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3193 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3194 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3195 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3196 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3197 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3198 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3199 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3200 3201 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3202 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3203 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3204 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3205 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3206 3207 /** 3208 * cpu_mmu_index: 3209 * @env: The cpu environment 3210 * @ifetch: True for code access, false for data access. 3211 * 3212 * Return the core mmu index for the current translation regime. 3213 * This function is used by generic TCG code paths. 3214 */ 3215 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3216 { 3217 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3218 } 3219 3220 /** 3221 * sve_vq 3222 * @env: the cpu context 3223 * 3224 * Return the VL cached within env->hflags, in units of quadwords. 3225 */ 3226 static inline int sve_vq(CPUARMState *env) 3227 { 3228 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3229 } 3230 3231 /** 3232 * sme_vq 3233 * @env: the cpu context 3234 * 3235 * Return the SVL cached within env->hflags, in units of quadwords. 3236 */ 3237 static inline int sme_vq(CPUARMState *env) 3238 { 3239 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3240 } 3241 3242 static inline bool bswap_code(bool sctlr_b) 3243 { 3244 #ifdef CONFIG_USER_ONLY 3245 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3246 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3247 * would also end up as a mixed-endian mode with BE code, LE data. 3248 */ 3249 return 3250 #if TARGET_BIG_ENDIAN 3251 1 ^ 3252 #endif 3253 sctlr_b; 3254 #else 3255 /* All code access in ARM is little endian, and there are no loaders 3256 * doing swaps that need to be reversed 3257 */ 3258 return 0; 3259 #endif 3260 } 3261 3262 #ifdef CONFIG_USER_ONLY 3263 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3264 { 3265 return 3266 #if TARGET_BIG_ENDIAN 3267 1 ^ 3268 #endif 3269 arm_cpu_data_is_big_endian(env); 3270 } 3271 #endif 3272 3273 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3274 target_ulong *cs_base, uint32_t *flags); 3275 3276 enum { 3277 QEMU_PSCI_CONDUIT_DISABLED = 0, 3278 QEMU_PSCI_CONDUIT_SMC = 1, 3279 QEMU_PSCI_CONDUIT_HVC = 2, 3280 }; 3281 3282 #ifndef CONFIG_USER_ONLY 3283 /* Return the address space index to use for a memory access */ 3284 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3285 { 3286 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3287 } 3288 3289 /* Return the AddressSpace to use for a memory access 3290 * (which depends on whether the access is S or NS, and whether 3291 * the board gave us a separate AddressSpace for S accesses). 3292 */ 3293 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3294 { 3295 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3296 } 3297 #endif 3298 3299 /** 3300 * arm_register_pre_el_change_hook: 3301 * Register a hook function which will be called immediately before this 3302 * CPU changes exception level or mode. The hook function will be 3303 * passed a pointer to the ARMCPU and the opaque data pointer passed 3304 * to this function when the hook was registered. 3305 * 3306 * Note that if a pre-change hook is called, any registered post-change hooks 3307 * are guaranteed to subsequently be called. 3308 */ 3309 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3310 void *opaque); 3311 /** 3312 * arm_register_el_change_hook: 3313 * Register a hook function which will be called immediately after this 3314 * CPU changes exception level or mode. The hook function will be 3315 * passed a pointer to the ARMCPU and the opaque data pointer passed 3316 * to this function when the hook was registered. 3317 * 3318 * Note that any registered hooks registered here are guaranteed to be called 3319 * if pre-change hooks have been. 3320 */ 3321 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3322 *opaque); 3323 3324 /** 3325 * arm_rebuild_hflags: 3326 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3327 */ 3328 void arm_rebuild_hflags(CPUARMState *env); 3329 3330 /** 3331 * aa32_vfp_dreg: 3332 * Return a pointer to the Dn register within env in 32-bit mode. 3333 */ 3334 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3335 { 3336 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3337 } 3338 3339 /** 3340 * aa32_vfp_qreg: 3341 * Return a pointer to the Qn register within env in 32-bit mode. 3342 */ 3343 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3344 { 3345 return &env->vfp.zregs[regno].d[0]; 3346 } 3347 3348 /** 3349 * aa64_vfp_qreg: 3350 * Return a pointer to the Qn register within env in 64-bit mode. 3351 */ 3352 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3353 { 3354 return &env->vfp.zregs[regno].d[0]; 3355 } 3356 3357 /* Shared between translate-sve.c and sve_helper.c. */ 3358 extern const uint64_t pred_esz_masks[4]; 3359 3360 /* Helper for the macros below, validating the argument type. */ 3361 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) 3362 { 3363 return x; 3364 } 3365 3366 /* 3367 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. 3368 * Using these should be a bit more self-documenting than using the 3369 * generic target bits directly. 3370 */ 3371 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) 3372 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) 3373 3374 /* 3375 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3376 */ 3377 #define PAGE_BTI PAGE_TARGET_1 3378 #define PAGE_MTE PAGE_TARGET_2 3379 3380 #ifdef TARGET_TAGGED_ADDRESSES 3381 /** 3382 * cpu_untagged_addr: 3383 * @cs: CPU context 3384 * @x: tagged address 3385 * 3386 * Remove any address tag from @x. This is explicitly related to the 3387 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3388 * 3389 * There should be a better place to put this, but we need this in 3390 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3391 */ 3392 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3393 { 3394 ARMCPU *cpu = ARM_CPU(cs); 3395 if (cpu->env.tagged_addr_enable) { 3396 /* 3397 * TBI is enabled for userspace but not kernelspace addresses. 3398 * Only clear the tag if bit 55 is clear. 3399 */ 3400 x &= sextract64(x, 0, 56); 3401 } 3402 return x; 3403 } 3404 #endif 3405 3406 /* 3407 * Naming convention for isar_feature functions: 3408 * Functions which test 32-bit ID registers should have _aa32_ in 3409 * their name. Functions which test 64-bit ID registers should have 3410 * _aa64_ in their name. These must only be used in code where we 3411 * know for certain that the CPU has AArch32 or AArch64 respectively 3412 * or where the correct answer for a CPU which doesn't implement that 3413 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3414 * system registers that are specific to that CPU state, for "should 3415 * we let this system register bit be set" tests where the 32-bit 3416 * flavour of the register doesn't have the bit, and so on). 3417 * Functions which simply ask "does this feature exist at all" have 3418 * _any_ in their name, and always return the logical OR of the _aa64_ 3419 * and the _aa32_ function. 3420 */ 3421 3422 /* 3423 * 32-bit feature tests via id registers. 3424 */ 3425 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3426 { 3427 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3428 } 3429 3430 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3431 { 3432 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3433 } 3434 3435 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3436 { 3437 /* (M-profile) low-overhead loops and branch future */ 3438 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3439 } 3440 3441 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3442 { 3443 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3444 } 3445 3446 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3447 { 3448 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3449 } 3450 3451 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3452 { 3453 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3454 } 3455 3456 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3457 { 3458 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3459 } 3460 3461 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3462 { 3463 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3464 } 3465 3466 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3467 { 3468 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3469 } 3470 3471 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3472 { 3473 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3474 } 3475 3476 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3477 { 3478 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3479 } 3480 3481 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3482 { 3483 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3484 } 3485 3486 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3487 { 3488 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3489 } 3490 3491 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3492 { 3493 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3494 } 3495 3496 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3497 { 3498 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3499 } 3500 3501 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3502 { 3503 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3504 } 3505 3506 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3507 { 3508 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3509 } 3510 3511 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3512 { 3513 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3514 } 3515 3516 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3517 { 3518 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3519 } 3520 3521 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3522 { 3523 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3524 } 3525 3526 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3527 { 3528 /* 3529 * Return true if M-profile state handling insns 3530 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3531 */ 3532 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3533 } 3534 3535 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3536 { 3537 /* Sadly this is encoded differently for A-profile and M-profile */ 3538 if (isar_feature_aa32_mprofile(id)) { 3539 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3540 } else { 3541 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3542 } 3543 } 3544 3545 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3546 { 3547 /* 3548 * Return true if MVE is supported (either integer or floating point). 3549 * We must check for M-profile as the MVFR1 field means something 3550 * else for A-profile. 3551 */ 3552 return isar_feature_aa32_mprofile(id) && 3553 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3554 } 3555 3556 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3557 { 3558 /* 3559 * Return true if MVE is supported (either integer or floating point). 3560 * We must check for M-profile as the MVFR1 field means something 3561 * else for A-profile. 3562 */ 3563 return isar_feature_aa32_mprofile(id) && 3564 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3565 } 3566 3567 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3568 { 3569 /* 3570 * Return true if either VFP or SIMD is implemented. 3571 * In this case, a minimum of VFP w/ D0-D15. 3572 */ 3573 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3574 } 3575 3576 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3577 { 3578 /* Return true if D16-D31 are implemented */ 3579 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3580 } 3581 3582 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3583 { 3584 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3585 } 3586 3587 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3588 { 3589 /* Return true if CPU supports single precision floating point, VFPv2 */ 3590 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3591 } 3592 3593 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3594 { 3595 /* Return true if CPU supports single precision floating point, VFPv3 */ 3596 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3597 } 3598 3599 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3600 { 3601 /* Return true if CPU supports double precision floating point, VFPv2 */ 3602 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3603 } 3604 3605 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3606 { 3607 /* Return true if CPU supports double precision floating point, VFPv3 */ 3608 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3609 } 3610 3611 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3612 { 3613 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3614 } 3615 3616 /* 3617 * We always set the FP and SIMD FP16 fields to indicate identical 3618 * levels of support (assuming SIMD is implemented at all), so 3619 * we only need one set of accessors. 3620 */ 3621 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3622 { 3623 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3624 } 3625 3626 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3627 { 3628 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3629 } 3630 3631 /* 3632 * Note that this ID register field covers both VFP and Neon FMAC, 3633 * so should usually be tested in combination with some other 3634 * check that confirms the presence of whichever of VFP or Neon is 3635 * relevant, to avoid accidentally enabling a Neon feature on 3636 * a VFP-no-Neon core or vice-versa. 3637 */ 3638 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3639 { 3640 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3641 } 3642 3643 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3644 { 3645 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3646 } 3647 3648 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3649 { 3650 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3651 } 3652 3653 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3654 { 3655 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3656 } 3657 3658 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3659 { 3660 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3661 } 3662 3663 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3664 { 3665 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3666 } 3667 3668 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3669 { 3670 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3671 } 3672 3673 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3674 { 3675 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3676 } 3677 3678 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3679 { 3680 /* 0xf means "non-standard IMPDEF PMU" */ 3681 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3682 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3683 } 3684 3685 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3686 { 3687 /* 0xf means "non-standard IMPDEF PMU" */ 3688 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3689 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3690 } 3691 3692 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3693 { 3694 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3695 } 3696 3697 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3698 { 3699 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3700 } 3701 3702 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3703 { 3704 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3705 } 3706 3707 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3708 { 3709 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3710 } 3711 3712 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3713 { 3714 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3715 } 3716 3717 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3718 { 3719 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3720 } 3721 3722 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3723 { 3724 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3725 } 3726 3727 /* 3728 * 64-bit feature tests via id registers. 3729 */ 3730 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3731 { 3732 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3733 } 3734 3735 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3736 { 3737 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3738 } 3739 3740 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3741 { 3742 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3743 } 3744 3745 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3746 { 3747 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3748 } 3749 3750 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3751 { 3752 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3753 } 3754 3755 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3756 { 3757 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3758 } 3759 3760 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3761 { 3762 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3763 } 3764 3765 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3766 { 3767 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3768 } 3769 3770 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3771 { 3772 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3773 } 3774 3775 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3776 { 3777 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3778 } 3779 3780 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3781 { 3782 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3783 } 3784 3785 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3786 { 3787 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3788 } 3789 3790 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3791 { 3792 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3793 } 3794 3795 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3796 { 3797 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3798 } 3799 3800 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3801 { 3802 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3803 } 3804 3805 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3806 { 3807 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3808 } 3809 3810 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3811 { 3812 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3813 } 3814 3815 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3816 { 3817 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3818 } 3819 3820 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3821 { 3822 /* 3823 * Return true if any form of pauth is enabled, as this 3824 * predicate controls migration of the 128-bit keys. 3825 */ 3826 return (id->id_aa64isar1 & 3827 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3828 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3829 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3830 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3831 } 3832 3833 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3834 { 3835 /* 3836 * Return true if pauth is enabled with the architected QARMA algorithm. 3837 * QEMU will always set APA+GPA to the same value. 3838 */ 3839 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3840 } 3841 3842 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3843 { 3844 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3845 } 3846 3847 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3848 { 3849 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3850 } 3851 3852 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3853 { 3854 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3855 } 3856 3857 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3858 { 3859 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3860 } 3861 3862 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3863 { 3864 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3865 } 3866 3867 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3868 { 3869 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3870 } 3871 3872 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3873 { 3874 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3875 } 3876 3877 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3878 { 3879 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3880 } 3881 3882 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3883 { 3884 /* We always set the AdvSIMD and FP fields identically. */ 3885 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3886 } 3887 3888 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3889 { 3890 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3891 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3892 } 3893 3894 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3895 { 3896 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3897 } 3898 3899 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3900 { 3901 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3902 } 3903 3904 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) 3905 { 3906 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; 3907 } 3908 3909 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3910 { 3911 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 3912 } 3913 3914 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) 3915 { 3916 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2; 3917 } 3918 3919 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3920 { 3921 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3922 } 3923 3924 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 3925 { 3926 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 3927 } 3928 3929 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3930 { 3931 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3932 } 3933 3934 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3935 { 3936 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3937 } 3938 3939 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3940 { 3941 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3942 } 3943 3944 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3945 { 3946 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3947 } 3948 3949 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) 3950 { 3951 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; 3952 } 3953 3954 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 3955 { 3956 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 3957 } 3958 3959 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 3960 { 3961 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 3962 } 3963 3964 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) 3965 { 3966 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; 3967 } 3968 3969 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) 3970 { 3971 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; 3972 } 3973 3974 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3975 { 3976 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3977 } 3978 3979 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 3980 { 3981 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 3982 } 3983 3984 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 3985 { 3986 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 3987 } 3988 3989 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) 3990 { 3991 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; 3992 } 3993 3994 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 3995 { 3996 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 3997 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3998 } 3999 4000 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 4001 { 4002 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 4003 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4004 } 4005 4006 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 4007 { 4008 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 4009 } 4010 4011 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 4012 { 4013 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 4014 } 4015 4016 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 4017 { 4018 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 4019 } 4020 4021 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 4022 { 4023 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 4024 } 4025 4026 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 4027 { 4028 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4029 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 4030 } 4031 4032 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 4033 { 4034 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 4035 } 4036 4037 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 4038 { 4039 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4040 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 4041 } 4042 4043 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4044 { 4045 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4046 } 4047 4048 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4049 { 4050 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4051 } 4052 4053 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4054 { 4055 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4056 } 4057 4058 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4059 { 4060 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4061 } 4062 4063 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 4064 { 4065 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); 4066 if (key >= 2) { 4067 return true; /* FEAT_CSV2_2 */ 4068 } 4069 if (key == 1) { 4070 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); 4071 return key >= 2; /* FEAT_CSV2_1p2 */ 4072 } 4073 return false; 4074 } 4075 4076 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4077 { 4078 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4079 } 4080 4081 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4082 { 4083 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4084 } 4085 4086 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4087 { 4088 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4089 } 4090 4091 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4092 { 4093 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4094 } 4095 4096 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4097 { 4098 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4099 } 4100 4101 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4102 { 4103 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4104 } 4105 4106 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4107 { 4108 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4109 } 4110 4111 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4112 { 4113 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4114 } 4115 4116 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4117 { 4118 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4119 } 4120 4121 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4122 { 4123 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4124 } 4125 4126 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4127 { 4128 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4129 } 4130 4131 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4132 { 4133 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4134 } 4135 4136 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) 4137 { 4138 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); 4139 } 4140 4141 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) 4142 { 4143 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; 4144 } 4145 4146 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) 4147 { 4148 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); 4149 } 4150 4151 /* 4152 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4153 */ 4154 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4155 { 4156 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4157 } 4158 4159 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4160 { 4161 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4162 } 4163 4164 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 4165 { 4166 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 4167 } 4168 4169 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 4170 { 4171 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 4172 } 4173 4174 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4175 { 4176 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4177 } 4178 4179 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4180 { 4181 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4182 } 4183 4184 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4185 { 4186 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4187 } 4188 4189 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4190 { 4191 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4192 } 4193 4194 /* 4195 * Forward to the above feature tests given an ARMCPU pointer. 4196 */ 4197 #define cpu_isar_feature(name, cpu) \ 4198 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4199 4200 #endif 4201