1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 60 61 #define ARMV7M_EXCP_RESET 1 62 #define ARMV7M_EXCP_NMI 2 63 #define ARMV7M_EXCP_HARD 3 64 #define ARMV7M_EXCP_MEM 4 65 #define ARMV7M_EXCP_BUS 5 66 #define ARMV7M_EXCP_USAGE 6 67 #define ARMV7M_EXCP_SECURE 7 68 #define ARMV7M_EXCP_SVC 11 69 #define ARMV7M_EXCP_DEBUG 12 70 #define ARMV7M_EXCP_PENDSV 14 71 #define ARMV7M_EXCP_SYSTICK 15 72 73 /* For M profile, some registers are banked secure vs non-secure; 74 * these are represented as a 2-element array where the first element 75 * is the non-secure copy and the second is the secure copy. 76 * When the CPU does not have implement the security extension then 77 * only the first element is used. 78 * This means that the copy for the current security state can be 79 * accessed via env->registerfield[env->v7m.secure] (whether the security 80 * extension is implemented or not). 81 */ 82 enum { 83 M_REG_NS = 0, 84 M_REG_S = 1, 85 M_REG_NUM_BANKS = 2, 86 }; 87 88 /* ARM-specific interrupt pending bits. */ 89 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 90 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 91 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 92 93 /* The usual mapping for an AArch64 system register to its AArch32 94 * counterpart is for the 32 bit world to have access to the lower 95 * half only (with writes leaving the upper half untouched). It's 96 * therefore useful to be able to pass TCG the offset of the least 97 * significant half of a uint64_t struct member. 98 */ 99 #if HOST_BIG_ENDIAN 100 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 101 #define offsetofhigh32(S, M) offsetof(S, M) 102 #else 103 #define offsetoflow32(S, M) offsetof(S, M) 104 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 105 #endif 106 107 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 108 #define ARM_CPU_IRQ 0 109 #define ARM_CPU_FIQ 1 110 #define ARM_CPU_VIRQ 2 111 #define ARM_CPU_VFIQ 3 112 113 /* ARM-specific extra insn start words: 114 * 1: Conditional execution bits 115 * 2: Partial exception syndrome for data aborts 116 */ 117 #define TARGET_INSN_START_EXTRA_WORDS 2 118 119 /* The 2nd extra word holding syndrome info for data aborts does not use 120 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 121 * help the sleb128 encoder do a better job. 122 * When restoring the CPU state, we shift it back up. 123 */ 124 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 125 #define ARM_INSN_START_WORD2_SHIFT 14 126 127 /* We currently assume float and double are IEEE single and double 128 precision respectively. 129 Doing runtime conversions is tricky because VFP registers may contain 130 integer values (eg. as the result of a FTOSI instruction). 131 s<2n> maps to the least significant half of d<n> 132 s<2n+1> maps to the most significant half of d<n> 133 */ 134 135 /** 136 * DynamicGDBXMLInfo: 137 * @desc: Contains the XML descriptions. 138 * @num: Number of the registers in this XML seen by GDB. 139 * @data: A union with data specific to the set of registers 140 * @cpregs_keys: Array that contains the corresponding Key of 141 * a given cpreg with the same order of the cpreg 142 * in the XML description. 143 */ 144 typedef struct DynamicGDBXMLInfo { 145 char *desc; 146 int num; 147 union { 148 struct { 149 uint32_t *keys; 150 } cpregs; 151 } data; 152 } DynamicGDBXMLInfo; 153 154 /* CPU state for each instance of a generic timer (in cp15 c14) */ 155 typedef struct ARMGenericTimer { 156 uint64_t cval; /* Timer CompareValue register */ 157 uint64_t ctl; /* Timer Control register */ 158 } ARMGenericTimer; 159 160 #define GTIMER_PHYS 0 161 #define GTIMER_VIRT 1 162 #define GTIMER_HYP 2 163 #define GTIMER_SEC 3 164 #define GTIMER_HYPVIRT 4 165 #define NUM_GTIMERS 5 166 167 typedef struct { 168 uint64_t raw_tcr; 169 uint32_t mask; 170 uint32_t base_mask; 171 } TCR; 172 173 #define VTCR_NSW (1u << 29) 174 #define VTCR_NSA (1u << 30) 175 #define VSTCR_SW VTCR_NSW 176 #define VSTCR_SA VTCR_NSA 177 178 /* Define a maximum sized vector register. 179 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 180 * For 64-bit, this is a 2048-bit SVE register. 181 * 182 * Note that the mapping between S, D, and Q views of the register bank 183 * differs between AArch64 and AArch32. 184 * In AArch32: 185 * Qn = regs[n].d[1]:regs[n].d[0] 186 * Dn = regs[n / 2].d[n & 1] 187 * Sn = regs[n / 4].d[n % 4 / 2], 188 * bits 31..0 for even n, and bits 63..32 for odd n 189 * (and regs[16] to regs[31] are inaccessible) 190 * In AArch64: 191 * Zn = regs[n].d[*] 192 * Qn = regs[n].d[1]:regs[n].d[0] 193 * Dn = regs[n].d[0] 194 * Sn = regs[n].d[0] bits 31..0 195 * Hn = regs[n].d[0] bits 15..0 196 * 197 * This corresponds to the architecturally defined mapping between 198 * the two execution states, and means we do not need to explicitly 199 * map these registers when changing states. 200 * 201 * Align the data for use with TCG host vector operations. 202 */ 203 204 #ifdef TARGET_AARCH64 205 # define ARM_MAX_VQ 16 206 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 207 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); 208 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); 209 #else 210 # define ARM_MAX_VQ 1 211 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 212 static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } 213 static inline void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { } 214 #endif 215 216 typedef struct ARMVectorReg { 217 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 218 } ARMVectorReg; 219 220 #ifdef TARGET_AARCH64 221 /* In AArch32 mode, predicate registers do not exist at all. */ 222 typedef struct ARMPredicateReg { 223 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 224 } ARMPredicateReg; 225 226 /* In AArch32 mode, PAC keys do not exist at all. */ 227 typedef struct ARMPACKey { 228 uint64_t lo, hi; 229 } ARMPACKey; 230 #endif 231 232 /* See the commentary above the TBFLAG field definitions. */ 233 typedef struct CPUARMTBFlags { 234 uint32_t flags; 235 target_ulong flags2; 236 } CPUARMTBFlags; 237 238 typedef struct CPUArchState { 239 /* Regs for current mode. */ 240 uint32_t regs[16]; 241 242 /* 32/64 switch only happens when taking and returning from 243 * exceptions so the overlap semantics are taken care of then 244 * instead of having a complicated union. 245 */ 246 /* Regs for A64 mode. */ 247 uint64_t xregs[32]; 248 uint64_t pc; 249 /* PSTATE isn't an architectural register for ARMv8. However, it is 250 * convenient for us to assemble the underlying state into a 32 bit format 251 * identical to the architectural format used for the SPSR. (This is also 252 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 253 * 'pstate' register are.) Of the PSTATE bits: 254 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 255 * semantics as for AArch32, as described in the comments on each field) 256 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 257 * DAIF (exception masks) are kept in env->daif 258 * BTYPE is kept in env->btype 259 * all other bits are stored in their correct places in env->pstate 260 */ 261 uint32_t pstate; 262 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 263 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 264 265 /* Cached TBFLAGS state. See below for which bits are included. */ 266 CPUARMTBFlags hflags; 267 268 /* Frequently accessed CPSR bits are stored separately for efficiency. 269 This contains all the other bits. Use cpsr_{read,write} to access 270 the whole CPSR. */ 271 uint32_t uncached_cpsr; 272 uint32_t spsr; 273 274 /* Banked registers. */ 275 uint64_t banked_spsr[8]; 276 uint32_t banked_r13[8]; 277 uint32_t banked_r14[8]; 278 279 /* These hold r8-r12. */ 280 uint32_t usr_regs[5]; 281 uint32_t fiq_regs[5]; 282 283 /* cpsr flag cache for faster execution */ 284 uint32_t CF; /* 0 or 1 */ 285 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 286 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 287 uint32_t ZF; /* Z set if zero. */ 288 uint32_t QF; /* 0 or 1 */ 289 uint32_t GE; /* cpsr[19:16] */ 290 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 291 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 292 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 293 294 uint64_t elr_el[4]; /* AArch64 exception link regs */ 295 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 296 297 /* System control coprocessor (cp15) */ 298 struct { 299 uint32_t c0_cpuid; 300 union { /* Cache size selection */ 301 struct { 302 uint64_t _unused_csselr0; 303 uint64_t csselr_ns; 304 uint64_t _unused_csselr1; 305 uint64_t csselr_s; 306 }; 307 uint64_t csselr_el[4]; 308 }; 309 union { /* System control register. */ 310 struct { 311 uint64_t _unused_sctlr; 312 uint64_t sctlr_ns; 313 uint64_t hsctlr; 314 uint64_t sctlr_s; 315 }; 316 uint64_t sctlr_el[4]; 317 }; 318 uint64_t cpacr_el1; /* Architectural feature access control register */ 319 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 320 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 321 uint64_t sder; /* Secure debug enable register. */ 322 uint32_t nsacr; /* Non-secure access control register. */ 323 union { /* MMU translation table base 0. */ 324 struct { 325 uint64_t _unused_ttbr0_0; 326 uint64_t ttbr0_ns; 327 uint64_t _unused_ttbr0_1; 328 uint64_t ttbr0_s; 329 }; 330 uint64_t ttbr0_el[4]; 331 }; 332 union { /* MMU translation table base 1. */ 333 struct { 334 uint64_t _unused_ttbr1_0; 335 uint64_t ttbr1_ns; 336 uint64_t _unused_ttbr1_1; 337 uint64_t ttbr1_s; 338 }; 339 uint64_t ttbr1_el[4]; 340 }; 341 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 342 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 343 /* MMU translation table base control. */ 344 TCR tcr_el[4]; 345 TCR vtcr_el2; /* Virtualization Translation Control. */ 346 TCR vstcr_el2; /* Secure Virtualization Translation Control. */ 347 uint32_t c2_data; /* MPU data cacheable bits. */ 348 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 349 union { /* MMU domain access control register 350 * MPU write buffer control. 351 */ 352 struct { 353 uint64_t dacr_ns; 354 uint64_t dacr_s; 355 }; 356 struct { 357 uint64_t dacr32_el2; 358 }; 359 }; 360 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 361 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 362 uint64_t hcr_el2; /* Hypervisor configuration register */ 363 uint64_t scr_el3; /* Secure configuration register. */ 364 union { /* Fault status registers. */ 365 struct { 366 uint64_t ifsr_ns; 367 uint64_t ifsr_s; 368 }; 369 struct { 370 uint64_t ifsr32_el2; 371 }; 372 }; 373 union { 374 struct { 375 uint64_t _unused_dfsr; 376 uint64_t dfsr_ns; 377 uint64_t hsr; 378 uint64_t dfsr_s; 379 }; 380 uint64_t esr_el[4]; 381 }; 382 uint32_t c6_region[8]; /* MPU base/size registers. */ 383 union { /* Fault address registers. */ 384 struct { 385 uint64_t _unused_far0; 386 #if HOST_BIG_ENDIAN 387 uint32_t ifar_ns; 388 uint32_t dfar_ns; 389 uint32_t ifar_s; 390 uint32_t dfar_s; 391 #else 392 uint32_t dfar_ns; 393 uint32_t ifar_ns; 394 uint32_t dfar_s; 395 uint32_t ifar_s; 396 #endif 397 uint64_t _unused_far3; 398 }; 399 uint64_t far_el[4]; 400 }; 401 uint64_t hpfar_el2; 402 uint64_t hstr_el2; 403 union { /* Translation result. */ 404 struct { 405 uint64_t _unused_par_0; 406 uint64_t par_ns; 407 uint64_t _unused_par_1; 408 uint64_t par_s; 409 }; 410 uint64_t par_el[4]; 411 }; 412 413 uint32_t c9_insn; /* Cache lockdown registers. */ 414 uint32_t c9_data; 415 uint64_t c9_pmcr; /* performance monitor control register */ 416 uint64_t c9_pmcnten; /* perf monitor counter enables */ 417 uint64_t c9_pmovsr; /* perf monitor overflow status */ 418 uint64_t c9_pmuserenr; /* perf monitor user enable */ 419 uint64_t c9_pmselr; /* perf monitor counter selection register */ 420 uint64_t c9_pminten; /* perf monitor interrupt enables */ 421 union { /* Memory attribute redirection */ 422 struct { 423 #if HOST_BIG_ENDIAN 424 uint64_t _unused_mair_0; 425 uint32_t mair1_ns; 426 uint32_t mair0_ns; 427 uint64_t _unused_mair_1; 428 uint32_t mair1_s; 429 uint32_t mair0_s; 430 #else 431 uint64_t _unused_mair_0; 432 uint32_t mair0_ns; 433 uint32_t mair1_ns; 434 uint64_t _unused_mair_1; 435 uint32_t mair0_s; 436 uint32_t mair1_s; 437 #endif 438 }; 439 uint64_t mair_el[4]; 440 }; 441 union { /* vector base address register */ 442 struct { 443 uint64_t _unused_vbar; 444 uint64_t vbar_ns; 445 uint64_t hvbar; 446 uint64_t vbar_s; 447 }; 448 uint64_t vbar_el[4]; 449 }; 450 uint32_t mvbar; /* (monitor) vector base address register */ 451 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 452 struct { /* FCSE PID. */ 453 uint32_t fcseidr_ns; 454 uint32_t fcseidr_s; 455 }; 456 union { /* Context ID. */ 457 struct { 458 uint64_t _unused_contextidr_0; 459 uint64_t contextidr_ns; 460 uint64_t _unused_contextidr_1; 461 uint64_t contextidr_s; 462 }; 463 uint64_t contextidr_el[4]; 464 }; 465 union { /* User RW Thread register. */ 466 struct { 467 uint64_t tpidrurw_ns; 468 uint64_t tpidrprw_ns; 469 uint64_t htpidr; 470 uint64_t _tpidr_el3; 471 }; 472 uint64_t tpidr_el[4]; 473 }; 474 /* The secure banks of these registers don't map anywhere */ 475 uint64_t tpidrurw_s; 476 uint64_t tpidrprw_s; 477 uint64_t tpidruro_s; 478 479 union { /* User RO Thread register. */ 480 uint64_t tpidruro_ns; 481 uint64_t tpidrro_el[1]; 482 }; 483 uint64_t c14_cntfrq; /* Counter Frequency register */ 484 uint64_t c14_cntkctl; /* Timer Control register */ 485 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 486 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 487 ARMGenericTimer c14_timer[NUM_GTIMERS]; 488 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 489 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 490 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 491 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 492 uint32_t c15_threadid; /* TI debugger thread-ID. */ 493 uint32_t c15_config_base_address; /* SCU base address. */ 494 uint32_t c15_diagnostic; /* diagnostic register */ 495 uint32_t c15_power_diagnostic; 496 uint32_t c15_power_control; /* power control */ 497 uint64_t dbgbvr[16]; /* breakpoint value registers */ 498 uint64_t dbgbcr[16]; /* breakpoint control registers */ 499 uint64_t dbgwvr[16]; /* watchpoint value registers */ 500 uint64_t dbgwcr[16]; /* watchpoint control registers */ 501 uint64_t mdscr_el1; 502 uint64_t oslsr_el1; /* OS Lock Status */ 503 uint64_t mdcr_el2; 504 uint64_t mdcr_el3; 505 /* Stores the architectural value of the counter *the last time it was 506 * updated* by pmccntr_op_start. Accesses should always be surrounded 507 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 508 * architecturally-correct value is being read/set. 509 */ 510 uint64_t c15_ccnt; 511 /* Stores the delta between the architectural value and the underlying 512 * cycle count during normal operation. It is used to update c15_ccnt 513 * to be the correct architectural value before accesses. During 514 * accesses, c15_ccnt_delta contains the underlying count being used 515 * for the access, after which it reverts to the delta value in 516 * pmccntr_op_finish. 517 */ 518 uint64_t c15_ccnt_delta; 519 uint64_t c14_pmevcntr[31]; 520 uint64_t c14_pmevcntr_delta[31]; 521 uint64_t c14_pmevtyper[31]; 522 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 523 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 524 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 525 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 526 uint64_t gcr_el1; 527 uint64_t rgsr_el1; 528 } cp15; 529 530 struct { 531 /* M profile has up to 4 stack pointers: 532 * a Main Stack Pointer and a Process Stack Pointer for each 533 * of the Secure and Non-Secure states. (If the CPU doesn't support 534 * the security extension then it has only two SPs.) 535 * In QEMU we always store the currently active SP in regs[13], 536 * and the non-active SP for the current security state in 537 * v7m.other_sp. The stack pointers for the inactive security state 538 * are stored in other_ss_msp and other_ss_psp. 539 * switch_v7m_security_state() is responsible for rearranging them 540 * when we change security state. 541 */ 542 uint32_t other_sp; 543 uint32_t other_ss_msp; 544 uint32_t other_ss_psp; 545 uint32_t vecbase[M_REG_NUM_BANKS]; 546 uint32_t basepri[M_REG_NUM_BANKS]; 547 uint32_t control[M_REG_NUM_BANKS]; 548 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 549 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 550 uint32_t hfsr; /* HardFault Status */ 551 uint32_t dfsr; /* Debug Fault Status Register */ 552 uint32_t sfsr; /* Secure Fault Status Register */ 553 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 554 uint32_t bfar; /* BusFault Address */ 555 uint32_t sfar; /* Secure Fault Address Register */ 556 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 557 int exception; 558 uint32_t primask[M_REG_NUM_BANKS]; 559 uint32_t faultmask[M_REG_NUM_BANKS]; 560 uint32_t aircr; /* only holds r/w state if security extn implemented */ 561 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 562 uint32_t csselr[M_REG_NUM_BANKS]; 563 uint32_t scr[M_REG_NUM_BANKS]; 564 uint32_t msplim[M_REG_NUM_BANKS]; 565 uint32_t psplim[M_REG_NUM_BANKS]; 566 uint32_t fpcar[M_REG_NUM_BANKS]; 567 uint32_t fpccr[M_REG_NUM_BANKS]; 568 uint32_t fpdscr[M_REG_NUM_BANKS]; 569 uint32_t cpacr[M_REG_NUM_BANKS]; 570 uint32_t nsacr; 571 uint32_t ltpsize; 572 uint32_t vpr; 573 } v7m; 574 575 /* Information associated with an exception about to be taken: 576 * code which raises an exception must set cs->exception_index and 577 * the relevant parts of this structure; the cpu_do_interrupt function 578 * will then set the guest-visible registers as part of the exception 579 * entry process. 580 */ 581 struct { 582 uint32_t syndrome; /* AArch64 format syndrome register */ 583 uint32_t fsr; /* AArch32 format fault status register info */ 584 uint64_t vaddress; /* virtual addr associated with exception, if any */ 585 uint32_t target_el; /* EL the exception should be targeted for */ 586 /* If we implement EL2 we will also need to store information 587 * about the intermediate physical address for stage 2 faults. 588 */ 589 } exception; 590 591 /* Information associated with an SError */ 592 struct { 593 uint8_t pending; 594 uint8_t has_esr; 595 uint64_t esr; 596 } serror; 597 598 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 599 600 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 601 uint32_t irq_line_state; 602 603 /* Thumb-2 EE state. */ 604 uint32_t teecr; 605 uint32_t teehbr; 606 607 /* VFP coprocessor state. */ 608 struct { 609 ARMVectorReg zregs[32]; 610 611 #ifdef TARGET_AARCH64 612 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 613 #define FFR_PRED_NUM 16 614 ARMPredicateReg pregs[17]; 615 /* Scratch space for aa64 sve predicate temporary. */ 616 ARMPredicateReg preg_tmp; 617 #endif 618 619 /* We store these fpcsr fields separately for convenience. */ 620 uint32_t qc[4] QEMU_ALIGNED(16); 621 int vec_len; 622 int vec_stride; 623 624 uint32_t xregs[16]; 625 626 /* Scratch space for aa32 neon expansion. */ 627 uint32_t scratch[8]; 628 629 /* There are a number of distinct float control structures: 630 * 631 * fp_status: is the "normal" fp status. 632 * fp_status_fp16: used for half-precision calculations 633 * standard_fp_status : the ARM "Standard FPSCR Value" 634 * standard_fp_status_fp16 : used for half-precision 635 * calculations with the ARM "Standard FPSCR Value" 636 * 637 * Half-precision operations are governed by a separate 638 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 639 * status structure to control this. 640 * 641 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 642 * round-to-nearest and is used by any operations (generally 643 * Neon) which the architecture defines as controlled by the 644 * standard FPSCR value rather than the FPSCR. 645 * 646 * The "standard FPSCR but for fp16 ops" is needed because 647 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 648 * using a fixed value for it. 649 * 650 * To avoid having to transfer exception bits around, we simply 651 * say that the FPSCR cumulative exception flags are the logical 652 * OR of the flags in the four fp statuses. This relies on the 653 * only thing which needs to read the exception flags being 654 * an explicit FPSCR read. 655 */ 656 float_status fp_status; 657 float_status fp_status_f16; 658 float_status standard_fp_status; 659 float_status standard_fp_status_f16; 660 661 /* ZCR_EL[1-3] */ 662 uint64_t zcr_el[4]; 663 } vfp; 664 uint64_t exclusive_addr; 665 uint64_t exclusive_val; 666 uint64_t exclusive_high; 667 668 /* iwMMXt coprocessor state. */ 669 struct { 670 uint64_t regs[16]; 671 uint64_t val; 672 673 uint32_t cregs[16]; 674 } iwmmxt; 675 676 #ifdef TARGET_AARCH64 677 struct { 678 ARMPACKey apia; 679 ARMPACKey apib; 680 ARMPACKey apda; 681 ARMPACKey apdb; 682 ARMPACKey apga; 683 } keys; 684 #endif 685 686 #if defined(CONFIG_USER_ONLY) 687 /* For usermode syscall translation. */ 688 int eabi; 689 #endif 690 691 struct CPUBreakpoint *cpu_breakpoint[16]; 692 struct CPUWatchpoint *cpu_watchpoint[16]; 693 694 /* Fields up to this point are cleared by a CPU reset */ 695 struct {} end_reset_fields; 696 697 /* Fields after this point are preserved across CPU reset. */ 698 699 /* Internal CPU feature flags. */ 700 uint64_t features; 701 702 /* PMSAv7 MPU */ 703 struct { 704 uint32_t *drbar; 705 uint32_t *drsr; 706 uint32_t *dracr; 707 uint32_t rnr[M_REG_NUM_BANKS]; 708 } pmsav7; 709 710 /* PMSAv8 MPU */ 711 struct { 712 /* The PMSAv8 implementation also shares some PMSAv7 config 713 * and state: 714 * pmsav7.rnr (region number register) 715 * pmsav7_dregion (number of configured regions) 716 */ 717 uint32_t *rbar[M_REG_NUM_BANKS]; 718 uint32_t *rlar[M_REG_NUM_BANKS]; 719 uint32_t mair0[M_REG_NUM_BANKS]; 720 uint32_t mair1[M_REG_NUM_BANKS]; 721 } pmsav8; 722 723 /* v8M SAU */ 724 struct { 725 uint32_t *rbar; 726 uint32_t *rlar; 727 uint32_t rnr; 728 uint32_t ctrl; 729 } sau; 730 731 void *nvic; 732 const struct arm_boot_info *boot_info; 733 /* Store GICv3CPUState to access from this struct */ 734 void *gicv3state; 735 736 #ifdef TARGET_TAGGED_ADDRESSES 737 /* Linux syscall tagged address support */ 738 bool tagged_addr_enable; 739 #endif 740 } CPUARMState; 741 742 static inline void set_feature(CPUARMState *env, int feature) 743 { 744 env->features |= 1ULL << feature; 745 } 746 747 static inline void unset_feature(CPUARMState *env, int feature) 748 { 749 env->features &= ~(1ULL << feature); 750 } 751 752 /** 753 * ARMELChangeHookFn: 754 * type of a function which can be registered via arm_register_el_change_hook() 755 * to get callbacks when the CPU changes its exception level or mode. 756 */ 757 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 758 typedef struct ARMELChangeHook ARMELChangeHook; 759 struct ARMELChangeHook { 760 ARMELChangeHookFn *hook; 761 void *opaque; 762 QLIST_ENTRY(ARMELChangeHook) node; 763 }; 764 765 /* These values map onto the return values for 766 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 767 typedef enum ARMPSCIState { 768 PSCI_ON = 0, 769 PSCI_OFF = 1, 770 PSCI_ON_PENDING = 2 771 } ARMPSCIState; 772 773 typedef struct ARMISARegisters ARMISARegisters; 774 775 /** 776 * ARMCPU: 777 * @env: #CPUARMState 778 * 779 * An ARM CPU core. 780 */ 781 struct ArchCPU { 782 /*< private >*/ 783 CPUState parent_obj; 784 /*< public >*/ 785 786 CPUNegativeOffsetState neg; 787 CPUARMState env; 788 789 /* Coprocessor information */ 790 GHashTable *cp_regs; 791 /* For marshalling (mostly coprocessor) register state between the 792 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 793 * we use these arrays. 794 */ 795 /* List of register indexes managed via these arrays; (full KVM style 796 * 64 bit indexes, not CPRegInfo 32 bit indexes) 797 */ 798 uint64_t *cpreg_indexes; 799 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 800 uint64_t *cpreg_values; 801 /* Length of the indexes, values, reset_values arrays */ 802 int32_t cpreg_array_len; 803 /* These are used only for migration: incoming data arrives in 804 * these fields and is sanity checked in post_load before copying 805 * to the working data structures above. 806 */ 807 uint64_t *cpreg_vmstate_indexes; 808 uint64_t *cpreg_vmstate_values; 809 int32_t cpreg_vmstate_array_len; 810 811 DynamicGDBXMLInfo dyn_sysreg_xml; 812 DynamicGDBXMLInfo dyn_svereg_xml; 813 814 /* Timers used by the generic (architected) timer */ 815 QEMUTimer *gt_timer[NUM_GTIMERS]; 816 /* 817 * Timer used by the PMU. Its state is restored after migration by 818 * pmu_op_finish() - it does not need other handling during migration 819 */ 820 QEMUTimer *pmu_timer; 821 /* GPIO outputs for generic timer */ 822 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 823 /* GPIO output for GICv3 maintenance interrupt signal */ 824 qemu_irq gicv3_maintenance_interrupt; 825 /* GPIO output for the PMU interrupt */ 826 qemu_irq pmu_interrupt; 827 828 /* MemoryRegion to use for secure physical accesses */ 829 MemoryRegion *secure_memory; 830 831 /* MemoryRegion to use for allocation tag accesses */ 832 MemoryRegion *tag_memory; 833 MemoryRegion *secure_tag_memory; 834 835 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 836 Object *idau; 837 838 /* 'compatible' string for this CPU for Linux device trees */ 839 const char *dtb_compatible; 840 841 /* PSCI version for this CPU 842 * Bits[31:16] = Major Version 843 * Bits[15:0] = Minor Version 844 */ 845 uint32_t psci_version; 846 847 /* Current power state, access guarded by BQL */ 848 ARMPSCIState power_state; 849 850 /* CPU has virtualization extension */ 851 bool has_el2; 852 /* CPU has security extension */ 853 bool has_el3; 854 /* CPU has PMU (Performance Monitor Unit) */ 855 bool has_pmu; 856 /* CPU has VFP */ 857 bool has_vfp; 858 /* CPU has Neon */ 859 bool has_neon; 860 /* CPU has M-profile DSP extension */ 861 bool has_dsp; 862 863 /* CPU has memory protection unit */ 864 bool has_mpu; 865 /* PMSAv7 MPU number of supported regions */ 866 uint32_t pmsav7_dregion; 867 /* v8M SAU number of supported regions */ 868 uint32_t sau_sregion; 869 870 /* PSCI conduit used to invoke PSCI methods 871 * 0 - disabled, 1 - smc, 2 - hvc 872 */ 873 uint32_t psci_conduit; 874 875 /* For v8M, initial value of the Secure VTOR */ 876 uint32_t init_svtor; 877 /* For v8M, initial value of the Non-secure VTOR */ 878 uint32_t init_nsvtor; 879 880 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 881 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 882 */ 883 uint32_t kvm_target; 884 885 /* KVM init features for this CPU */ 886 uint32_t kvm_init_features[7]; 887 888 /* KVM CPU state */ 889 890 /* KVM virtual time adjustment */ 891 bool kvm_adjvtime; 892 bool kvm_vtime_dirty; 893 uint64_t kvm_vtime; 894 895 /* KVM steal time */ 896 OnOffAuto kvm_steal_time; 897 898 /* Uniprocessor system with MP extensions */ 899 bool mp_is_up; 900 901 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 902 * and the probe failed (so we need to report the error in realize) 903 */ 904 bool host_cpu_probe_failed; 905 906 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 907 * register. 908 */ 909 int32_t core_count; 910 911 /* The instance init functions for implementation-specific subclasses 912 * set these fields to specify the implementation-dependent values of 913 * various constant registers and reset values of non-constant 914 * registers. 915 * Some of these might become QOM properties eventually. 916 * Field names match the official register names as defined in the 917 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 918 * is used for reset values of non-constant registers; no reset_ 919 * prefix means a constant register. 920 * Some of these registers are split out into a substructure that 921 * is shared with the translators to control the ISA. 922 * 923 * Note that if you add an ID register to the ARMISARegisters struct 924 * you need to also update the 32-bit and 64-bit versions of the 925 * kvm_arm_get_host_cpu_features() function to correctly populate the 926 * field by reading the value from the KVM vCPU. 927 */ 928 struct ARMISARegisters { 929 uint32_t id_isar0; 930 uint32_t id_isar1; 931 uint32_t id_isar2; 932 uint32_t id_isar3; 933 uint32_t id_isar4; 934 uint32_t id_isar5; 935 uint32_t id_isar6; 936 uint32_t id_mmfr0; 937 uint32_t id_mmfr1; 938 uint32_t id_mmfr2; 939 uint32_t id_mmfr3; 940 uint32_t id_mmfr4; 941 uint32_t id_pfr0; 942 uint32_t id_pfr1; 943 uint32_t id_pfr2; 944 uint32_t mvfr0; 945 uint32_t mvfr1; 946 uint32_t mvfr2; 947 uint32_t id_dfr0; 948 uint32_t dbgdidr; 949 uint64_t id_aa64isar0; 950 uint64_t id_aa64isar1; 951 uint64_t id_aa64pfr0; 952 uint64_t id_aa64pfr1; 953 uint64_t id_aa64mmfr0; 954 uint64_t id_aa64mmfr1; 955 uint64_t id_aa64mmfr2; 956 uint64_t id_aa64dfr0; 957 uint64_t id_aa64dfr1; 958 uint64_t id_aa64zfr0; 959 } isar; 960 uint64_t midr; 961 uint32_t revidr; 962 uint32_t reset_fpsid; 963 uint64_t ctr; 964 uint32_t reset_sctlr; 965 uint64_t pmceid0; 966 uint64_t pmceid1; 967 uint32_t id_afr0; 968 uint64_t id_aa64afr0; 969 uint64_t id_aa64afr1; 970 uint64_t clidr; 971 uint64_t mp_affinity; /* MP ID without feature bits */ 972 /* The elements of this array are the CCSIDR values for each cache, 973 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 974 */ 975 uint64_t ccsidr[16]; 976 uint64_t reset_cbar; 977 uint32_t reset_auxcr; 978 bool reset_hivecs; 979 980 /* 981 * Intermediate values used during property parsing. 982 * Once finalized, the values should be read from ID_AA64*. 983 */ 984 bool prop_pauth; 985 bool prop_pauth_impdef; 986 bool prop_lpa2; 987 988 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 989 uint32_t dcz_blocksize; 990 uint64_t rvbar_prop; /* Property/input signals. */ 991 992 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 993 int gic_num_lrs; /* number of list registers */ 994 int gic_vpribits; /* number of virtual priority bits */ 995 int gic_vprebits; /* number of virtual preemption bits */ 996 997 /* Whether the cfgend input is high (i.e. this CPU should reset into 998 * big-endian mode). This setting isn't used directly: instead it modifies 999 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1000 * architecture version. 1001 */ 1002 bool cfgend; 1003 1004 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1005 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1006 1007 int32_t node_id; /* NUMA node this CPU belongs to */ 1008 1009 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1010 uint8_t device_irq_level; 1011 1012 /* Used to set the maximum vector length the cpu will support. */ 1013 uint32_t sve_max_vq; 1014 1015 #ifdef CONFIG_USER_ONLY 1016 /* Used to set the default vector length at process start. */ 1017 uint32_t sve_default_vq; 1018 #endif 1019 1020 /* 1021 * In sve_vq_map each set bit is a supported vector length of 1022 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 1023 * length in quadwords. 1024 * 1025 * While processing properties during initialization, corresponding 1026 * sve_vq_init bits are set for bits in sve_vq_map that have been 1027 * set by properties. 1028 * 1029 * Bits set in sve_vq_supported represent valid vector lengths for 1030 * the CPU type. 1031 */ 1032 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 1033 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 1034 DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ); 1035 1036 /* Generic timer counter frequency, in Hz */ 1037 uint64_t gt_cntfrq_hz; 1038 }; 1039 1040 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1041 1042 void arm_cpu_post_init(Object *obj); 1043 1044 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1045 1046 #ifndef CONFIG_USER_ONLY 1047 extern const VMStateDescription vmstate_arm_cpu; 1048 1049 void arm_cpu_do_interrupt(CPUState *cpu); 1050 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1051 #endif /* !CONFIG_USER_ONLY */ 1052 1053 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1054 MemTxAttrs *attrs); 1055 1056 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1057 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1058 1059 /* 1060 * Helpers to dynamically generates XML descriptions of the sysregs 1061 * and SVE registers. Returns the number of registers in each set. 1062 */ 1063 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1064 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1065 1066 /* Returns the dynamically generated XML for the gdb stub. 1067 * Returns a pointer to the XML contents for the specified XML file or NULL 1068 * if the XML name doesn't match the predefined one. 1069 */ 1070 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1071 1072 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1073 int cpuid, void *opaque); 1074 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1075 int cpuid, void *opaque); 1076 1077 #ifdef TARGET_AARCH64 1078 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1079 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1080 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1081 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1082 int new_el, bool el0_a64); 1083 void aarch64_add_sve_properties(Object *obj); 1084 void aarch64_add_pauth_properties(Object *obj); 1085 1086 /* 1087 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1088 * The byte at offset i from the start of the in-memory representation contains 1089 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1090 * lowest offsets are stored in the lowest memory addresses, then that nearly 1091 * matches QEMU's representation, which is to use an array of host-endian 1092 * uint64_t's, where the lower offsets are at the lower indices. To complete 1093 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1094 */ 1095 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1096 { 1097 #if HOST_BIG_ENDIAN 1098 int i; 1099 1100 for (i = 0; i < nr; ++i) { 1101 dst[i] = bswap64(src[i]); 1102 } 1103 1104 return dst; 1105 #else 1106 return src; 1107 #endif 1108 } 1109 1110 #else 1111 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1112 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1113 int n, bool a) 1114 { } 1115 static inline void aarch64_add_sve_properties(Object *obj) { } 1116 #endif 1117 1118 void aarch64_sync_32_to_64(CPUARMState *env); 1119 void aarch64_sync_64_to_32(CPUARMState *env); 1120 1121 int fp_exception_el(CPUARMState *env, int cur_el); 1122 int sve_exception_el(CPUARMState *env, int cur_el); 1123 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1124 1125 static inline bool is_a64(CPUARMState *env) 1126 { 1127 return env->aarch64; 1128 } 1129 1130 /** 1131 * pmu_op_start/finish 1132 * @env: CPUARMState 1133 * 1134 * Convert all PMU counters between their delta form (the typical mode when 1135 * they are enabled) and the guest-visible values. These two calls must 1136 * surround any action which might affect the counters. 1137 */ 1138 void pmu_op_start(CPUARMState *env); 1139 void pmu_op_finish(CPUARMState *env); 1140 1141 /* 1142 * Called when a PMU counter is due to overflow 1143 */ 1144 void arm_pmu_timer_cb(void *opaque); 1145 1146 /** 1147 * Functions to register as EL change hooks for PMU mode filtering 1148 */ 1149 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1150 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1151 1152 /* 1153 * pmu_init 1154 * @cpu: ARMCPU 1155 * 1156 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1157 * for the current configuration 1158 */ 1159 void pmu_init(ARMCPU *cpu); 1160 1161 /* SCTLR bit meanings. Several bits have been reused in newer 1162 * versions of the architecture; in that case we define constants 1163 * for both old and new bit meanings. Code which tests against those 1164 * bits should probably check or otherwise arrange that the CPU 1165 * is the architectural version it expects. 1166 */ 1167 #define SCTLR_M (1U << 0) 1168 #define SCTLR_A (1U << 1) 1169 #define SCTLR_C (1U << 2) 1170 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1171 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1172 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1173 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1174 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1175 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1176 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1177 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1178 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1179 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1180 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1181 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1182 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1183 #define SCTLR_SED (1U << 8) /* v8 onward */ 1184 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1185 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1186 #define SCTLR_F (1U << 10) /* up to v6 */ 1187 #define SCTLR_SW (1U << 10) /* v7 */ 1188 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1189 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1190 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1191 #define SCTLR_I (1U << 12) 1192 #define SCTLR_V (1U << 13) /* AArch32 only */ 1193 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1194 #define SCTLR_RR (1U << 14) /* up to v7 */ 1195 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1196 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1197 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1198 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1199 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1200 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1201 #define SCTLR_BR (1U << 17) /* PMSA only */ 1202 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1203 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1204 #define SCTLR_WXN (1U << 19) 1205 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1206 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1207 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1208 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1209 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1210 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1211 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1212 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1213 #define SCTLR_VE (1U << 24) /* up to v7 */ 1214 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1215 #define SCTLR_EE (1U << 25) 1216 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1217 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1218 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1219 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1220 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1221 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1222 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1223 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1224 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1225 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1226 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1227 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1228 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1229 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1230 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1231 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1232 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1233 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1234 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1235 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1236 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1237 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1238 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1239 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1240 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1241 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1242 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1243 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1244 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1245 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1246 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1247 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1248 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1249 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1250 1251 #define CPTR_TCPAC (1U << 31) 1252 #define CPTR_TTA (1U << 20) 1253 #define CPTR_TFP (1U << 10) 1254 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1255 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1256 1257 #define MDCR_EPMAD (1U << 21) 1258 #define MDCR_EDAD (1U << 20) 1259 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1260 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1261 #define MDCR_SDD (1U << 16) 1262 #define MDCR_SPD (3U << 14) 1263 #define MDCR_TDRA (1U << 11) 1264 #define MDCR_TDOSA (1U << 10) 1265 #define MDCR_TDA (1U << 9) 1266 #define MDCR_TDE (1U << 8) 1267 #define MDCR_HPME (1U << 7) 1268 #define MDCR_TPM (1U << 6) 1269 #define MDCR_TPMCR (1U << 5) 1270 #define MDCR_HPMN (0x1fU) 1271 1272 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1273 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1274 1275 #define CPSR_M (0x1fU) 1276 #define CPSR_T (1U << 5) 1277 #define CPSR_F (1U << 6) 1278 #define CPSR_I (1U << 7) 1279 #define CPSR_A (1U << 8) 1280 #define CPSR_E (1U << 9) 1281 #define CPSR_IT_2_7 (0xfc00U) 1282 #define CPSR_GE (0xfU << 16) 1283 #define CPSR_IL (1U << 20) 1284 #define CPSR_DIT (1U << 21) 1285 #define CPSR_PAN (1U << 22) 1286 #define CPSR_SSBS (1U << 23) 1287 #define CPSR_J (1U << 24) 1288 #define CPSR_IT_0_1 (3U << 25) 1289 #define CPSR_Q (1U << 27) 1290 #define CPSR_V (1U << 28) 1291 #define CPSR_C (1U << 29) 1292 #define CPSR_Z (1U << 30) 1293 #define CPSR_N (1U << 31) 1294 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1295 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1296 1297 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1298 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1299 | CPSR_NZCV) 1300 /* Bits writable in user mode. */ 1301 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1302 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1303 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1304 1305 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1306 #define XPSR_EXCP 0x1ffU 1307 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1308 #define XPSR_IT_2_7 CPSR_IT_2_7 1309 #define XPSR_GE CPSR_GE 1310 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1311 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1312 #define XPSR_IT_0_1 CPSR_IT_0_1 1313 #define XPSR_Q CPSR_Q 1314 #define XPSR_V CPSR_V 1315 #define XPSR_C CPSR_C 1316 #define XPSR_Z CPSR_Z 1317 #define XPSR_N CPSR_N 1318 #define XPSR_NZCV CPSR_NZCV 1319 #define XPSR_IT CPSR_IT 1320 1321 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1322 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1323 #define TTBCR_PD0 (1U << 4) 1324 #define TTBCR_PD1 (1U << 5) 1325 #define TTBCR_EPD0 (1U << 7) 1326 #define TTBCR_IRGN0 (3U << 8) 1327 #define TTBCR_ORGN0 (3U << 10) 1328 #define TTBCR_SH0 (3U << 12) 1329 #define TTBCR_T1SZ (3U << 16) 1330 #define TTBCR_A1 (1U << 22) 1331 #define TTBCR_EPD1 (1U << 23) 1332 #define TTBCR_IRGN1 (3U << 24) 1333 #define TTBCR_ORGN1 (3U << 26) 1334 #define TTBCR_SH1 (1U << 28) 1335 #define TTBCR_EAE (1U << 31) 1336 1337 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1338 * Only these are valid when in AArch64 mode; in 1339 * AArch32 mode SPSRs are basically CPSR-format. 1340 */ 1341 #define PSTATE_SP (1U) 1342 #define PSTATE_M (0xFU) 1343 #define PSTATE_nRW (1U << 4) 1344 #define PSTATE_F (1U << 6) 1345 #define PSTATE_I (1U << 7) 1346 #define PSTATE_A (1U << 8) 1347 #define PSTATE_D (1U << 9) 1348 #define PSTATE_BTYPE (3U << 10) 1349 #define PSTATE_SSBS (1U << 12) 1350 #define PSTATE_IL (1U << 20) 1351 #define PSTATE_SS (1U << 21) 1352 #define PSTATE_PAN (1U << 22) 1353 #define PSTATE_UAO (1U << 23) 1354 #define PSTATE_DIT (1U << 24) 1355 #define PSTATE_TCO (1U << 25) 1356 #define PSTATE_V (1U << 28) 1357 #define PSTATE_C (1U << 29) 1358 #define PSTATE_Z (1U << 30) 1359 #define PSTATE_N (1U << 31) 1360 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1361 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1362 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1363 /* Mode values for AArch64 */ 1364 #define PSTATE_MODE_EL3h 13 1365 #define PSTATE_MODE_EL3t 12 1366 #define PSTATE_MODE_EL2h 9 1367 #define PSTATE_MODE_EL2t 8 1368 #define PSTATE_MODE_EL1h 5 1369 #define PSTATE_MODE_EL1t 4 1370 #define PSTATE_MODE_EL0t 0 1371 1372 /* Write a new value to v7m.exception, thus transitioning into or out 1373 * of Handler mode; this may result in a change of active stack pointer. 1374 */ 1375 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1376 1377 /* Map EL and handler into a PSTATE_MODE. */ 1378 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1379 { 1380 return (el << 2) | handler; 1381 } 1382 1383 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1384 * interprocessing, so we don't attempt to sync with the cpsr state used by 1385 * the 32 bit decoder. 1386 */ 1387 static inline uint32_t pstate_read(CPUARMState *env) 1388 { 1389 int ZF; 1390 1391 ZF = (env->ZF == 0); 1392 return (env->NF & 0x80000000) | (ZF << 30) 1393 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1394 | env->pstate | env->daif | (env->btype << 10); 1395 } 1396 1397 static inline void pstate_write(CPUARMState *env, uint32_t val) 1398 { 1399 env->ZF = (~val) & PSTATE_Z; 1400 env->NF = val; 1401 env->CF = (val >> 29) & 1; 1402 env->VF = (val << 3) & 0x80000000; 1403 env->daif = val & PSTATE_DAIF; 1404 env->btype = (val >> 10) & 3; 1405 env->pstate = val & ~CACHED_PSTATE_BITS; 1406 } 1407 1408 /* Return the current CPSR value. */ 1409 uint32_t cpsr_read(CPUARMState *env); 1410 1411 typedef enum CPSRWriteType { 1412 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1413 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1414 CPSRWriteRaw = 2, 1415 /* trust values, no reg bank switch, no hflags rebuild */ 1416 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1417 } CPSRWriteType; 1418 1419 /* 1420 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1421 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1422 * correspond to TB flags bits cached in the hflags, unless @write_type 1423 * is CPSRWriteRaw. 1424 */ 1425 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1426 CPSRWriteType write_type); 1427 1428 /* Return the current xPSR value. */ 1429 static inline uint32_t xpsr_read(CPUARMState *env) 1430 { 1431 int ZF; 1432 ZF = (env->ZF == 0); 1433 return (env->NF & 0x80000000) | (ZF << 30) 1434 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1435 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1436 | ((env->condexec_bits & 0xfc) << 8) 1437 | (env->GE << 16) 1438 | env->v7m.exception; 1439 } 1440 1441 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1442 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1443 { 1444 if (mask & XPSR_NZCV) { 1445 env->ZF = (~val) & XPSR_Z; 1446 env->NF = val; 1447 env->CF = (val >> 29) & 1; 1448 env->VF = (val << 3) & 0x80000000; 1449 } 1450 if (mask & XPSR_Q) { 1451 env->QF = ((val & XPSR_Q) != 0); 1452 } 1453 if (mask & XPSR_GE) { 1454 env->GE = (val & XPSR_GE) >> 16; 1455 } 1456 #ifndef CONFIG_USER_ONLY 1457 if (mask & XPSR_T) { 1458 env->thumb = ((val & XPSR_T) != 0); 1459 } 1460 if (mask & XPSR_IT_0_1) { 1461 env->condexec_bits &= ~3; 1462 env->condexec_bits |= (val >> 25) & 3; 1463 } 1464 if (mask & XPSR_IT_2_7) { 1465 env->condexec_bits &= 3; 1466 env->condexec_bits |= (val >> 8) & 0xfc; 1467 } 1468 if (mask & XPSR_EXCP) { 1469 /* Note that this only happens on exception exit */ 1470 write_v7m_exception(env, val & XPSR_EXCP); 1471 } 1472 #endif 1473 } 1474 1475 #define HCR_VM (1ULL << 0) 1476 #define HCR_SWIO (1ULL << 1) 1477 #define HCR_PTW (1ULL << 2) 1478 #define HCR_FMO (1ULL << 3) 1479 #define HCR_IMO (1ULL << 4) 1480 #define HCR_AMO (1ULL << 5) 1481 #define HCR_VF (1ULL << 6) 1482 #define HCR_VI (1ULL << 7) 1483 #define HCR_VSE (1ULL << 8) 1484 #define HCR_FB (1ULL << 9) 1485 #define HCR_BSU_MASK (3ULL << 10) 1486 #define HCR_DC (1ULL << 12) 1487 #define HCR_TWI (1ULL << 13) 1488 #define HCR_TWE (1ULL << 14) 1489 #define HCR_TID0 (1ULL << 15) 1490 #define HCR_TID1 (1ULL << 16) 1491 #define HCR_TID2 (1ULL << 17) 1492 #define HCR_TID3 (1ULL << 18) 1493 #define HCR_TSC (1ULL << 19) 1494 #define HCR_TIDCP (1ULL << 20) 1495 #define HCR_TACR (1ULL << 21) 1496 #define HCR_TSW (1ULL << 22) 1497 #define HCR_TPCP (1ULL << 23) 1498 #define HCR_TPU (1ULL << 24) 1499 #define HCR_TTLB (1ULL << 25) 1500 #define HCR_TVM (1ULL << 26) 1501 #define HCR_TGE (1ULL << 27) 1502 #define HCR_TDZ (1ULL << 28) 1503 #define HCR_HCD (1ULL << 29) 1504 #define HCR_TRVM (1ULL << 30) 1505 #define HCR_RW (1ULL << 31) 1506 #define HCR_CD (1ULL << 32) 1507 #define HCR_ID (1ULL << 33) 1508 #define HCR_E2H (1ULL << 34) 1509 #define HCR_TLOR (1ULL << 35) 1510 #define HCR_TERR (1ULL << 36) 1511 #define HCR_TEA (1ULL << 37) 1512 #define HCR_MIOCNCE (1ULL << 38) 1513 /* RES0 bit 39 */ 1514 #define HCR_APK (1ULL << 40) 1515 #define HCR_API (1ULL << 41) 1516 #define HCR_NV (1ULL << 42) 1517 #define HCR_NV1 (1ULL << 43) 1518 #define HCR_AT (1ULL << 44) 1519 #define HCR_NV2 (1ULL << 45) 1520 #define HCR_FWB (1ULL << 46) 1521 #define HCR_FIEN (1ULL << 47) 1522 /* RES0 bit 48 */ 1523 #define HCR_TID4 (1ULL << 49) 1524 #define HCR_TICAB (1ULL << 50) 1525 #define HCR_AMVOFFEN (1ULL << 51) 1526 #define HCR_TOCU (1ULL << 52) 1527 #define HCR_ENSCXT (1ULL << 53) 1528 #define HCR_TTLBIS (1ULL << 54) 1529 #define HCR_TTLBOS (1ULL << 55) 1530 #define HCR_ATA (1ULL << 56) 1531 #define HCR_DCT (1ULL << 57) 1532 #define HCR_TID5 (1ULL << 58) 1533 #define HCR_TWEDEN (1ULL << 59) 1534 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1535 1536 #define HPFAR_NS (1ULL << 63) 1537 1538 #define SCR_NS (1U << 0) 1539 #define SCR_IRQ (1U << 1) 1540 #define SCR_FIQ (1U << 2) 1541 #define SCR_EA (1U << 3) 1542 #define SCR_FW (1U << 4) 1543 #define SCR_AW (1U << 5) 1544 #define SCR_NET (1U << 6) 1545 #define SCR_SMD (1U << 7) 1546 #define SCR_HCE (1U << 8) 1547 #define SCR_SIF (1U << 9) 1548 #define SCR_RW (1U << 10) 1549 #define SCR_ST (1U << 11) 1550 #define SCR_TWI (1U << 12) 1551 #define SCR_TWE (1U << 13) 1552 #define SCR_TLOR (1U << 14) 1553 #define SCR_TERR (1U << 15) 1554 #define SCR_APK (1U << 16) 1555 #define SCR_API (1U << 17) 1556 #define SCR_EEL2 (1U << 18) 1557 #define SCR_EASE (1U << 19) 1558 #define SCR_NMEA (1U << 20) 1559 #define SCR_FIEN (1U << 21) 1560 #define SCR_ENSCXT (1U << 25) 1561 #define SCR_ATA (1U << 26) 1562 #define SCR_FGTEN (1U << 27) 1563 #define SCR_ECVEN (1U << 28) 1564 #define SCR_TWEDEN (1U << 29) 1565 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1566 #define SCR_TME (1ULL << 34) 1567 #define SCR_AMVOFFEN (1ULL << 35) 1568 #define SCR_ENAS0 (1ULL << 36) 1569 #define SCR_ADEN (1ULL << 37) 1570 #define SCR_HXEN (1ULL << 38) 1571 #define SCR_TRNDR (1ULL << 40) 1572 #define SCR_ENTP2 (1ULL << 41) 1573 #define SCR_GPF (1ULL << 48) 1574 1575 #define HSTR_TTEE (1 << 16) 1576 #define HSTR_TJDBX (1 << 17) 1577 1578 /* Return the current FPSCR value. */ 1579 uint32_t vfp_get_fpscr(CPUARMState *env); 1580 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1581 1582 /* FPCR, Floating Point Control Register 1583 * FPSR, Floating Poiht Status Register 1584 * 1585 * For A64 the FPSCR is split into two logically distinct registers, 1586 * FPCR and FPSR. However since they still use non-overlapping bits 1587 * we store the underlying state in fpscr and just mask on read/write. 1588 */ 1589 #define FPSR_MASK 0xf800009f 1590 #define FPCR_MASK 0x07ff9f00 1591 1592 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1593 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1594 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1595 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1596 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1597 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1598 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1599 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1600 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1601 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1602 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1603 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1604 #define FPCR_V (1 << 28) /* FP overflow flag */ 1605 #define FPCR_C (1 << 29) /* FP carry flag */ 1606 #define FPCR_Z (1 << 30) /* FP zero flag */ 1607 #define FPCR_N (1 << 31) /* FP negative flag */ 1608 1609 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1610 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1611 #define FPCR_LTPSIZE_LENGTH 3 1612 1613 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1614 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1615 1616 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1617 { 1618 return vfp_get_fpscr(env) & FPSR_MASK; 1619 } 1620 1621 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1622 { 1623 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1624 vfp_set_fpscr(env, new_fpscr); 1625 } 1626 1627 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1628 { 1629 return vfp_get_fpscr(env) & FPCR_MASK; 1630 } 1631 1632 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1633 { 1634 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1635 vfp_set_fpscr(env, new_fpscr); 1636 } 1637 1638 enum arm_cpu_mode { 1639 ARM_CPU_MODE_USR = 0x10, 1640 ARM_CPU_MODE_FIQ = 0x11, 1641 ARM_CPU_MODE_IRQ = 0x12, 1642 ARM_CPU_MODE_SVC = 0x13, 1643 ARM_CPU_MODE_MON = 0x16, 1644 ARM_CPU_MODE_ABT = 0x17, 1645 ARM_CPU_MODE_HYP = 0x1a, 1646 ARM_CPU_MODE_UND = 0x1b, 1647 ARM_CPU_MODE_SYS = 0x1f 1648 }; 1649 1650 /* VFP system registers. */ 1651 #define ARM_VFP_FPSID 0 1652 #define ARM_VFP_FPSCR 1 1653 #define ARM_VFP_MVFR2 5 1654 #define ARM_VFP_MVFR1 6 1655 #define ARM_VFP_MVFR0 7 1656 #define ARM_VFP_FPEXC 8 1657 #define ARM_VFP_FPINST 9 1658 #define ARM_VFP_FPINST2 10 1659 /* These ones are M-profile only */ 1660 #define ARM_VFP_FPSCR_NZCVQC 2 1661 #define ARM_VFP_VPR 12 1662 #define ARM_VFP_P0 13 1663 #define ARM_VFP_FPCXT_NS 14 1664 #define ARM_VFP_FPCXT_S 15 1665 1666 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1667 #define QEMU_VFP_FPSCR_NZCV 0xffff 1668 1669 /* iwMMXt coprocessor control registers. */ 1670 #define ARM_IWMMXT_wCID 0 1671 #define ARM_IWMMXT_wCon 1 1672 #define ARM_IWMMXT_wCSSF 2 1673 #define ARM_IWMMXT_wCASF 3 1674 #define ARM_IWMMXT_wCGR0 8 1675 #define ARM_IWMMXT_wCGR1 9 1676 #define ARM_IWMMXT_wCGR2 10 1677 #define ARM_IWMMXT_wCGR3 11 1678 1679 /* V7M CCR bits */ 1680 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1681 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1682 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1683 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1684 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1685 FIELD(V7M_CCR, STKALIGN, 9, 1) 1686 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1687 FIELD(V7M_CCR, DC, 16, 1) 1688 FIELD(V7M_CCR, IC, 17, 1) 1689 FIELD(V7M_CCR, BP, 18, 1) 1690 FIELD(V7M_CCR, LOB, 19, 1) 1691 FIELD(V7M_CCR, TRD, 20, 1) 1692 1693 /* V7M SCR bits */ 1694 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1695 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1696 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1697 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1698 1699 /* V7M AIRCR bits */ 1700 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1701 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1702 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1703 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1704 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1705 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1706 FIELD(V7M_AIRCR, PRIS, 14, 1) 1707 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1708 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1709 1710 /* V7M CFSR bits for MMFSR */ 1711 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1712 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1713 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1714 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1715 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1716 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1717 1718 /* V7M CFSR bits for BFSR */ 1719 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1720 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1721 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1722 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1723 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1724 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1725 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1726 1727 /* V7M CFSR bits for UFSR */ 1728 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1729 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1730 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1731 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1732 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1733 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1734 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1735 1736 /* V7M CFSR bit masks covering all of the subregister bits */ 1737 FIELD(V7M_CFSR, MMFSR, 0, 8) 1738 FIELD(V7M_CFSR, BFSR, 8, 8) 1739 FIELD(V7M_CFSR, UFSR, 16, 16) 1740 1741 /* V7M HFSR bits */ 1742 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1743 FIELD(V7M_HFSR, FORCED, 30, 1) 1744 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1745 1746 /* V7M DFSR bits */ 1747 FIELD(V7M_DFSR, HALTED, 0, 1) 1748 FIELD(V7M_DFSR, BKPT, 1, 1) 1749 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1750 FIELD(V7M_DFSR, VCATCH, 3, 1) 1751 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1752 1753 /* V7M SFSR bits */ 1754 FIELD(V7M_SFSR, INVEP, 0, 1) 1755 FIELD(V7M_SFSR, INVIS, 1, 1) 1756 FIELD(V7M_SFSR, INVER, 2, 1) 1757 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1758 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1759 FIELD(V7M_SFSR, LSPERR, 5, 1) 1760 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1761 FIELD(V7M_SFSR, LSERR, 7, 1) 1762 1763 /* v7M MPU_CTRL bits */ 1764 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1765 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1766 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1767 1768 /* v7M CLIDR bits */ 1769 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1770 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1771 FIELD(V7M_CLIDR, LOC, 24, 3) 1772 FIELD(V7M_CLIDR, LOUU, 27, 3) 1773 FIELD(V7M_CLIDR, ICB, 30, 2) 1774 1775 FIELD(V7M_CSSELR, IND, 0, 1) 1776 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1777 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1778 * define a mask for this and check that it doesn't permit running off 1779 * the end of the array. 1780 */ 1781 FIELD(V7M_CSSELR, INDEX, 0, 4) 1782 1783 /* v7M FPCCR bits */ 1784 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1785 FIELD(V7M_FPCCR, USER, 1, 1) 1786 FIELD(V7M_FPCCR, S, 2, 1) 1787 FIELD(V7M_FPCCR, THREAD, 3, 1) 1788 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1789 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1790 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1791 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1792 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1793 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1794 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1795 FIELD(V7M_FPCCR, RES0, 11, 15) 1796 FIELD(V7M_FPCCR, TS, 26, 1) 1797 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1798 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1799 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1800 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1801 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1802 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1803 #define R_V7M_FPCCR_BANKED_MASK \ 1804 (R_V7M_FPCCR_LSPACT_MASK | \ 1805 R_V7M_FPCCR_USER_MASK | \ 1806 R_V7M_FPCCR_THREAD_MASK | \ 1807 R_V7M_FPCCR_MMRDY_MASK | \ 1808 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1809 R_V7M_FPCCR_UFRDY_MASK | \ 1810 R_V7M_FPCCR_ASPEN_MASK) 1811 1812 /* v7M VPR bits */ 1813 FIELD(V7M_VPR, P0, 0, 16) 1814 FIELD(V7M_VPR, MASK01, 16, 4) 1815 FIELD(V7M_VPR, MASK23, 20, 4) 1816 1817 /* 1818 * System register ID fields. 1819 */ 1820 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1821 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1822 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1823 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1824 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1825 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1826 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1827 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1828 FIELD(CLIDR_EL1, LOC, 24, 3) 1829 FIELD(CLIDR_EL1, LOUU, 27, 3) 1830 FIELD(CLIDR_EL1, ICB, 30, 3) 1831 1832 /* When FEAT_CCIDX is implemented */ 1833 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1834 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1835 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1836 1837 /* When FEAT_CCIDX is not implemented */ 1838 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1839 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1840 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1841 1842 FIELD(CTR_EL0, IMINLINE, 0, 4) 1843 FIELD(CTR_EL0, L1IP, 14, 2) 1844 FIELD(CTR_EL0, DMINLINE, 16, 4) 1845 FIELD(CTR_EL0, ERG, 20, 4) 1846 FIELD(CTR_EL0, CWG, 24, 4) 1847 FIELD(CTR_EL0, IDC, 28, 1) 1848 FIELD(CTR_EL0, DIC, 29, 1) 1849 FIELD(CTR_EL0, TMINLINE, 32, 6) 1850 1851 FIELD(MIDR_EL1, REVISION, 0, 4) 1852 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1853 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1854 FIELD(MIDR_EL1, VARIANT, 20, 4) 1855 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1856 1857 FIELD(ID_ISAR0, SWAP, 0, 4) 1858 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1859 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1860 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1861 FIELD(ID_ISAR0, COPROC, 16, 4) 1862 FIELD(ID_ISAR0, DEBUG, 20, 4) 1863 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1864 1865 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1866 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1867 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1868 FIELD(ID_ISAR1, EXTEND, 12, 4) 1869 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1870 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1871 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1872 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1873 1874 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1875 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1876 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1877 FIELD(ID_ISAR2, MULT, 12, 4) 1878 FIELD(ID_ISAR2, MULTS, 16, 4) 1879 FIELD(ID_ISAR2, MULTU, 20, 4) 1880 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1881 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1882 1883 FIELD(ID_ISAR3, SATURATE, 0, 4) 1884 FIELD(ID_ISAR3, SIMD, 4, 4) 1885 FIELD(ID_ISAR3, SVC, 8, 4) 1886 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1887 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1888 FIELD(ID_ISAR3, T32COPY, 20, 4) 1889 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1890 FIELD(ID_ISAR3, T32EE, 28, 4) 1891 1892 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1893 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1894 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1895 FIELD(ID_ISAR4, SMC, 12, 4) 1896 FIELD(ID_ISAR4, BARRIER, 16, 4) 1897 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1898 FIELD(ID_ISAR4, PSR_M, 24, 4) 1899 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1900 1901 FIELD(ID_ISAR5, SEVL, 0, 4) 1902 FIELD(ID_ISAR5, AES, 4, 4) 1903 FIELD(ID_ISAR5, SHA1, 8, 4) 1904 FIELD(ID_ISAR5, SHA2, 12, 4) 1905 FIELD(ID_ISAR5, CRC32, 16, 4) 1906 FIELD(ID_ISAR5, RDM, 24, 4) 1907 FIELD(ID_ISAR5, VCMA, 28, 4) 1908 1909 FIELD(ID_ISAR6, JSCVT, 0, 4) 1910 FIELD(ID_ISAR6, DP, 4, 4) 1911 FIELD(ID_ISAR6, FHM, 8, 4) 1912 FIELD(ID_ISAR6, SB, 12, 4) 1913 FIELD(ID_ISAR6, SPECRES, 16, 4) 1914 FIELD(ID_ISAR6, BF16, 20, 4) 1915 FIELD(ID_ISAR6, I8MM, 24, 4) 1916 1917 FIELD(ID_MMFR0, VMSA, 0, 4) 1918 FIELD(ID_MMFR0, PMSA, 4, 4) 1919 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 1920 FIELD(ID_MMFR0, SHARELVL, 12, 4) 1921 FIELD(ID_MMFR0, TCM, 16, 4) 1922 FIELD(ID_MMFR0, AUXREG, 20, 4) 1923 FIELD(ID_MMFR0, FCSE, 24, 4) 1924 FIELD(ID_MMFR0, INNERSHR, 28, 4) 1925 1926 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 1927 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 1928 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 1929 FIELD(ID_MMFR1, L1UNISW, 12, 4) 1930 FIELD(ID_MMFR1, L1HVD, 16, 4) 1931 FIELD(ID_MMFR1, L1UNI, 20, 4) 1932 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 1933 FIELD(ID_MMFR1, BPRED, 28, 4) 1934 1935 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 1936 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 1937 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 1938 FIELD(ID_MMFR2, HVDTLB, 12, 4) 1939 FIELD(ID_MMFR2, UNITLB, 16, 4) 1940 FIELD(ID_MMFR2, MEMBARR, 20, 4) 1941 FIELD(ID_MMFR2, WFISTALL, 24, 4) 1942 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 1943 1944 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 1945 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 1946 FIELD(ID_MMFR3, BPMAINT, 8, 4) 1947 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 1948 FIELD(ID_MMFR3, PAN, 16, 4) 1949 FIELD(ID_MMFR3, COHWALK, 20, 4) 1950 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 1951 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 1952 1953 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1954 FIELD(ID_MMFR4, AC2, 4, 4) 1955 FIELD(ID_MMFR4, XNX, 8, 4) 1956 FIELD(ID_MMFR4, CNP, 12, 4) 1957 FIELD(ID_MMFR4, HPDS, 16, 4) 1958 FIELD(ID_MMFR4, LSM, 20, 4) 1959 FIELD(ID_MMFR4, CCIDX, 24, 4) 1960 FIELD(ID_MMFR4, EVT, 28, 4) 1961 1962 FIELD(ID_MMFR5, ETS, 0, 4) 1963 FIELD(ID_MMFR5, NTLBPA, 4, 4) 1964 1965 FIELD(ID_PFR0, STATE0, 0, 4) 1966 FIELD(ID_PFR0, STATE1, 4, 4) 1967 FIELD(ID_PFR0, STATE2, 8, 4) 1968 FIELD(ID_PFR0, STATE3, 12, 4) 1969 FIELD(ID_PFR0, CSV2, 16, 4) 1970 FIELD(ID_PFR0, AMU, 20, 4) 1971 FIELD(ID_PFR0, DIT, 24, 4) 1972 FIELD(ID_PFR0, RAS, 28, 4) 1973 1974 FIELD(ID_PFR1, PROGMOD, 0, 4) 1975 FIELD(ID_PFR1, SECURITY, 4, 4) 1976 FIELD(ID_PFR1, MPROGMOD, 8, 4) 1977 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 1978 FIELD(ID_PFR1, GENTIMER, 16, 4) 1979 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 1980 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 1981 FIELD(ID_PFR1, GIC, 28, 4) 1982 1983 FIELD(ID_PFR2, CSV3, 0, 4) 1984 FIELD(ID_PFR2, SSBS, 4, 4) 1985 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 1986 1987 FIELD(ID_AA64ISAR0, AES, 4, 4) 1988 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1989 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1990 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1991 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1992 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1993 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1994 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1995 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1996 FIELD(ID_AA64ISAR0, DP, 44, 4) 1997 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1998 FIELD(ID_AA64ISAR0, TS, 52, 4) 1999 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2000 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2001 2002 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2003 FIELD(ID_AA64ISAR1, APA, 4, 4) 2004 FIELD(ID_AA64ISAR1, API, 8, 4) 2005 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2006 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2007 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2008 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2009 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2010 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2011 FIELD(ID_AA64ISAR1, SB, 36, 4) 2012 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2013 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2014 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2015 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2016 FIELD(ID_AA64ISAR1, XS, 56, 4) 2017 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2018 2019 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2020 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2021 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2022 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2023 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2024 FIELD(ID_AA64ISAR2, BC, 20, 4) 2025 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2026 2027 FIELD(ID_AA64PFR0, EL0, 0, 4) 2028 FIELD(ID_AA64PFR0, EL1, 4, 4) 2029 FIELD(ID_AA64PFR0, EL2, 8, 4) 2030 FIELD(ID_AA64PFR0, EL3, 12, 4) 2031 FIELD(ID_AA64PFR0, FP, 16, 4) 2032 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2033 FIELD(ID_AA64PFR0, GIC, 24, 4) 2034 FIELD(ID_AA64PFR0, RAS, 28, 4) 2035 FIELD(ID_AA64PFR0, SVE, 32, 4) 2036 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2037 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2038 FIELD(ID_AA64PFR0, AMU, 44, 4) 2039 FIELD(ID_AA64PFR0, DIT, 48, 4) 2040 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2041 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2042 2043 FIELD(ID_AA64PFR1, BT, 0, 4) 2044 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2045 FIELD(ID_AA64PFR1, MTE, 8, 4) 2046 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2047 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2048 FIELD(ID_AA64PFR1, SME, 24, 4) 2049 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2050 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2051 FIELD(ID_AA64PFR1, NMI, 36, 4) 2052 2053 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2054 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2055 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2056 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2057 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2058 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2059 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2060 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2061 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2062 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2063 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2064 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2065 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2066 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2067 2068 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2069 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2070 FIELD(ID_AA64MMFR1, VH, 8, 4) 2071 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2072 FIELD(ID_AA64MMFR1, LO, 16, 4) 2073 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2074 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2075 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2076 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2077 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2078 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2079 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2080 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2081 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2082 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2083 2084 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2085 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2086 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2087 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2088 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2089 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2090 FIELD(ID_AA64MMFR2, NV, 24, 4) 2091 FIELD(ID_AA64MMFR2, ST, 28, 4) 2092 FIELD(ID_AA64MMFR2, AT, 32, 4) 2093 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2094 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2095 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2096 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2097 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2098 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2099 2100 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2101 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2102 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2103 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2104 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2105 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2106 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2107 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2108 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2109 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2110 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2111 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2112 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2113 2114 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2115 FIELD(ID_AA64ZFR0, AES, 4, 4) 2116 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2117 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2118 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2119 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2120 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2121 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2122 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2123 2124 FIELD(ID_DFR0, COPDBG, 0, 4) 2125 FIELD(ID_DFR0, COPSDBG, 4, 4) 2126 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2127 FIELD(ID_DFR0, COPTRC, 12, 4) 2128 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2129 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2130 FIELD(ID_DFR0, PERFMON, 24, 4) 2131 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2132 2133 FIELD(ID_DFR1, MTPMU, 0, 4) 2134 FIELD(ID_DFR1, HPMN0, 4, 4) 2135 2136 FIELD(DBGDIDR, SE_IMP, 12, 1) 2137 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2138 FIELD(DBGDIDR, VERSION, 16, 4) 2139 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2140 FIELD(DBGDIDR, BRPS, 24, 4) 2141 FIELD(DBGDIDR, WRPS, 28, 4) 2142 2143 FIELD(MVFR0, SIMDREG, 0, 4) 2144 FIELD(MVFR0, FPSP, 4, 4) 2145 FIELD(MVFR0, FPDP, 8, 4) 2146 FIELD(MVFR0, FPTRAP, 12, 4) 2147 FIELD(MVFR0, FPDIVIDE, 16, 4) 2148 FIELD(MVFR0, FPSQRT, 20, 4) 2149 FIELD(MVFR0, FPSHVEC, 24, 4) 2150 FIELD(MVFR0, FPROUND, 28, 4) 2151 2152 FIELD(MVFR1, FPFTZ, 0, 4) 2153 FIELD(MVFR1, FPDNAN, 4, 4) 2154 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2155 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2156 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2157 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2158 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2159 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2160 FIELD(MVFR1, FPHP, 24, 4) 2161 FIELD(MVFR1, SIMDFMAC, 28, 4) 2162 2163 FIELD(MVFR2, SIMDMISC, 0, 4) 2164 FIELD(MVFR2, FPMISC, 4, 4) 2165 2166 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2167 2168 /* If adding a feature bit which corresponds to a Linux ELF 2169 * HWCAP bit, remember to update the feature-bit-to-hwcap 2170 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2171 */ 2172 enum arm_features { 2173 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2174 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2175 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2176 ARM_FEATURE_V6, 2177 ARM_FEATURE_V6K, 2178 ARM_FEATURE_V7, 2179 ARM_FEATURE_THUMB2, 2180 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2181 ARM_FEATURE_NEON, 2182 ARM_FEATURE_M, /* Microcontroller profile. */ 2183 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2184 ARM_FEATURE_THUMB2EE, 2185 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2186 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2187 ARM_FEATURE_V4T, 2188 ARM_FEATURE_V5, 2189 ARM_FEATURE_STRONGARM, 2190 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2191 ARM_FEATURE_GENERIC_TIMER, 2192 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2193 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2194 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2195 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2196 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2197 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2198 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2199 ARM_FEATURE_V8, 2200 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2201 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2202 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2203 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2204 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2205 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2206 ARM_FEATURE_PMU, /* has PMU support */ 2207 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2208 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2209 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2210 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2211 }; 2212 2213 static inline int arm_feature(CPUARMState *env, int feature) 2214 { 2215 return (env->features & (1ULL << feature)) != 0; 2216 } 2217 2218 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2219 2220 #if !defined(CONFIG_USER_ONLY) 2221 /* Return true if exception levels below EL3 are in secure state, 2222 * or would be following an exception return to that level. 2223 * Unlike arm_is_secure() (which is always a question about the 2224 * _current_ state of the CPU) this doesn't care about the current 2225 * EL or mode. 2226 */ 2227 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2228 { 2229 if (arm_feature(env, ARM_FEATURE_EL3)) { 2230 return !(env->cp15.scr_el3 & SCR_NS); 2231 } else { 2232 /* If EL3 is not supported then the secure state is implementation 2233 * defined, in which case QEMU defaults to non-secure. 2234 */ 2235 return false; 2236 } 2237 } 2238 2239 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2240 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2241 { 2242 if (arm_feature(env, ARM_FEATURE_EL3)) { 2243 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2244 /* CPU currently in AArch64 state and EL3 */ 2245 return true; 2246 } else if (!is_a64(env) && 2247 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2248 /* CPU currently in AArch32 state and monitor mode */ 2249 return true; 2250 } 2251 } 2252 return false; 2253 } 2254 2255 /* Return true if the processor is in secure state */ 2256 static inline bool arm_is_secure(CPUARMState *env) 2257 { 2258 if (arm_is_el3_or_mon(env)) { 2259 return true; 2260 } 2261 return arm_is_secure_below_el3(env); 2262 } 2263 2264 /* 2265 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2266 * This corresponds to the pseudocode EL2Enabled() 2267 */ 2268 static inline bool arm_is_el2_enabled(CPUARMState *env) 2269 { 2270 if (arm_feature(env, ARM_FEATURE_EL2)) { 2271 if (arm_is_secure_below_el3(env)) { 2272 return (env->cp15.scr_el3 & SCR_EEL2) != 0; 2273 } 2274 return true; 2275 } 2276 return false; 2277 } 2278 2279 #else 2280 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2281 { 2282 return false; 2283 } 2284 2285 static inline bool arm_is_secure(CPUARMState *env) 2286 { 2287 return false; 2288 } 2289 2290 static inline bool arm_is_el2_enabled(CPUARMState *env) 2291 { 2292 return false; 2293 } 2294 #endif 2295 2296 /** 2297 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2298 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2299 * "for all purposes other than a direct read or write access of HCR_EL2." 2300 * Not included here is HCR_RW. 2301 */ 2302 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2303 2304 /* Return true if the specified exception level is running in AArch64 state. */ 2305 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2306 { 2307 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2308 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2309 */ 2310 assert(el >= 1 && el <= 3); 2311 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2312 2313 /* The highest exception level is always at the maximum supported 2314 * register width, and then lower levels have a register width controlled 2315 * by bits in the SCR or HCR registers. 2316 */ 2317 if (el == 3) { 2318 return aa64; 2319 } 2320 2321 if (arm_feature(env, ARM_FEATURE_EL3) && 2322 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2323 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2324 } 2325 2326 if (el == 2) { 2327 return aa64; 2328 } 2329 2330 if (arm_is_el2_enabled(env)) { 2331 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2332 } 2333 2334 return aa64; 2335 } 2336 2337 /* Function for determing whether guest cp register reads and writes should 2338 * access the secure or non-secure bank of a cp register. When EL3 is 2339 * operating in AArch32 state, the NS-bit determines whether the secure 2340 * instance of a cp register should be used. When EL3 is AArch64 (or if 2341 * it doesn't exist at all) then there is no register banking, and all 2342 * accesses are to the non-secure version. 2343 */ 2344 static inline bool access_secure_reg(CPUARMState *env) 2345 { 2346 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2347 !arm_el_is_aa64(env, 3) && 2348 !(env->cp15.scr_el3 & SCR_NS)); 2349 2350 return ret; 2351 } 2352 2353 /* Macros for accessing a specified CP register bank */ 2354 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2355 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2356 2357 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2358 do { \ 2359 if (_secure) { \ 2360 (_env)->cp15._regname##_s = (_val); \ 2361 } else { \ 2362 (_env)->cp15._regname##_ns = (_val); \ 2363 } \ 2364 } while (0) 2365 2366 /* Macros for automatically accessing a specific CP register bank depending on 2367 * the current secure state of the system. These macros are not intended for 2368 * supporting instruction translation reads/writes as these are dependent 2369 * solely on the SCR.NS bit and not the mode. 2370 */ 2371 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2372 A32_BANKED_REG_GET((_env), _regname, \ 2373 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2374 2375 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2376 A32_BANKED_REG_SET((_env), _regname, \ 2377 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2378 (_val)) 2379 2380 void arm_cpu_list(void); 2381 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2382 uint32_t cur_el, bool secure); 2383 2384 /* Interface between CPU and Interrupt controller. */ 2385 #ifndef CONFIG_USER_ONLY 2386 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2387 #else 2388 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2389 { 2390 return true; 2391 } 2392 #endif 2393 /** 2394 * armv7m_nvic_set_pending: mark the specified exception as pending 2395 * @opaque: the NVIC 2396 * @irq: the exception number to mark pending 2397 * @secure: false for non-banked exceptions or for the nonsecure 2398 * version of a banked exception, true for the secure version of a banked 2399 * exception. 2400 * 2401 * Marks the specified exception as pending. Note that we will assert() 2402 * if @secure is true and @irq does not specify one of the fixed set 2403 * of architecturally banked exceptions. 2404 */ 2405 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2406 /** 2407 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2408 * @opaque: the NVIC 2409 * @irq: the exception number to mark pending 2410 * @secure: false for non-banked exceptions or for the nonsecure 2411 * version of a banked exception, true for the secure version of a banked 2412 * exception. 2413 * 2414 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2415 * exceptions (exceptions generated in the course of trying to take 2416 * a different exception). 2417 */ 2418 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2419 /** 2420 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2421 * @opaque: the NVIC 2422 * @irq: the exception number to mark pending 2423 * @secure: false for non-banked exceptions or for the nonsecure 2424 * version of a banked exception, true for the secure version of a banked 2425 * exception. 2426 * 2427 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2428 * generated in the course of lazy stacking of FP registers. 2429 */ 2430 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2431 /** 2432 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2433 * exception, and whether it targets Secure state 2434 * @opaque: the NVIC 2435 * @pirq: set to pending exception number 2436 * @ptargets_secure: set to whether pending exception targets Secure 2437 * 2438 * This function writes the number of the highest priority pending 2439 * exception (the one which would be made active by 2440 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2441 * to true if the current highest priority pending exception should 2442 * be taken to Secure state, false for NS. 2443 */ 2444 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2445 bool *ptargets_secure); 2446 /** 2447 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2448 * @opaque: the NVIC 2449 * 2450 * Move the current highest priority pending exception from the pending 2451 * state to the active state, and update v7m.exception to indicate that 2452 * it is the exception currently being handled. 2453 */ 2454 void armv7m_nvic_acknowledge_irq(void *opaque); 2455 /** 2456 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2457 * @opaque: the NVIC 2458 * @irq: the exception number to complete 2459 * @secure: true if this exception was secure 2460 * 2461 * Returns: -1 if the irq was not active 2462 * 1 if completing this irq brought us back to base (no active irqs) 2463 * 0 if there is still an irq active after this one was completed 2464 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2465 */ 2466 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2467 /** 2468 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2469 * @opaque: the NVIC 2470 * @irq: the exception number to mark pending 2471 * @secure: false for non-banked exceptions or for the nonsecure 2472 * version of a banked exception, true for the secure version of a banked 2473 * exception. 2474 * 2475 * Return whether an exception is "ready", i.e. whether the exception is 2476 * enabled and is configured at a priority which would allow it to 2477 * interrupt the current execution priority. This controls whether the 2478 * RDY bit for it in the FPCCR is set. 2479 */ 2480 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2481 /** 2482 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2483 * @opaque: the NVIC 2484 * 2485 * Returns: the raw execution priority as defined by the v8M architecture. 2486 * This is the execution priority minus the effects of AIRCR.PRIS, 2487 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2488 * (v8M ARM ARM I_PKLD.) 2489 */ 2490 int armv7m_nvic_raw_execution_priority(void *opaque); 2491 /** 2492 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2493 * priority is negative for the specified security state. 2494 * @opaque: the NVIC 2495 * @secure: the security state to test 2496 * This corresponds to the pseudocode IsReqExecPriNeg(). 2497 */ 2498 #ifndef CONFIG_USER_ONLY 2499 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2500 #else 2501 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2502 { 2503 return false; 2504 } 2505 #endif 2506 2507 /* Interface for defining coprocessor registers. 2508 * Registers are defined in tables of arm_cp_reginfo structs 2509 * which are passed to define_arm_cp_regs(). 2510 */ 2511 2512 /* When looking up a coprocessor register we look for it 2513 * via an integer which encodes all of: 2514 * coprocessor number 2515 * Crn, Crm, opc1, opc2 fields 2516 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2517 * or via MRRC/MCRR?) 2518 * non-secure/secure bank (AArch32 only) 2519 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2520 * (In this case crn and opc2 should be zero.) 2521 * For AArch64, there is no 32/64 bit size distinction; 2522 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2523 * and 4 bit CRn and CRm. The encoding patterns are chosen 2524 * to be easy to convert to and from the KVM encodings, and also 2525 * so that the hashtable can contain both AArch32 and AArch64 2526 * registers (to allow for interprocessing where we might run 2527 * 32 bit code on a 64 bit core). 2528 */ 2529 /* This bit is private to our hashtable cpreg; in KVM register 2530 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2531 * in the upper bits of the 64 bit ID. 2532 */ 2533 #define CP_REG_AA64_SHIFT 28 2534 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2535 2536 /* To enable banking of coprocessor registers depending on ns-bit we 2537 * add a bit to distinguish between secure and non-secure cpregs in the 2538 * hashtable. 2539 */ 2540 #define CP_REG_NS_SHIFT 29 2541 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2542 2543 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2544 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2545 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2546 2547 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2548 (CP_REG_AA64_MASK | \ 2549 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2550 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2551 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2552 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2553 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2554 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2555 2556 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2557 * version used as a key for the coprocessor register hashtable 2558 */ 2559 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2560 { 2561 uint32_t cpregid = kvmid; 2562 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2563 cpregid |= CP_REG_AA64_MASK; 2564 } else { 2565 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2566 cpregid |= (1 << 15); 2567 } 2568 2569 /* KVM is always non-secure so add the NS flag on AArch32 register 2570 * entries. 2571 */ 2572 cpregid |= 1 << CP_REG_NS_SHIFT; 2573 } 2574 return cpregid; 2575 } 2576 2577 /* Convert a truncated 32 bit hashtable key into the full 2578 * 64 bit KVM register ID. 2579 */ 2580 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2581 { 2582 uint64_t kvmid; 2583 2584 if (cpregid & CP_REG_AA64_MASK) { 2585 kvmid = cpregid & ~CP_REG_AA64_MASK; 2586 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2587 } else { 2588 kvmid = cpregid & ~(1 << 15); 2589 if (cpregid & (1 << 15)) { 2590 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2591 } else { 2592 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2593 } 2594 } 2595 return kvmid; 2596 } 2597 2598 /* Return the highest implemented Exception Level */ 2599 static inline int arm_highest_el(CPUARMState *env) 2600 { 2601 if (arm_feature(env, ARM_FEATURE_EL3)) { 2602 return 3; 2603 } 2604 if (arm_feature(env, ARM_FEATURE_EL2)) { 2605 return 2; 2606 } 2607 return 1; 2608 } 2609 2610 /* Return true if a v7M CPU is in Handler mode */ 2611 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2612 { 2613 return env->v7m.exception != 0; 2614 } 2615 2616 /* Return the current Exception Level (as per ARMv8; note that this differs 2617 * from the ARMv7 Privilege Level). 2618 */ 2619 static inline int arm_current_el(CPUARMState *env) 2620 { 2621 if (arm_feature(env, ARM_FEATURE_M)) { 2622 return arm_v7m_is_handler_mode(env) || 2623 !(env->v7m.control[env->v7m.secure] & 1); 2624 } 2625 2626 if (is_a64(env)) { 2627 return extract32(env->pstate, 2, 2); 2628 } 2629 2630 switch (env->uncached_cpsr & 0x1f) { 2631 case ARM_CPU_MODE_USR: 2632 return 0; 2633 case ARM_CPU_MODE_HYP: 2634 return 2; 2635 case ARM_CPU_MODE_MON: 2636 return 3; 2637 default: 2638 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2639 /* If EL3 is 32-bit then all secure privileged modes run in 2640 * EL3 2641 */ 2642 return 3; 2643 } 2644 2645 return 1; 2646 } 2647 } 2648 2649 /** 2650 * write_list_to_cpustate 2651 * @cpu: ARMCPU 2652 * 2653 * For each register listed in the ARMCPU cpreg_indexes list, write 2654 * its value from the cpreg_values list into the ARMCPUState structure. 2655 * This updates TCG's working data structures from KVM data or 2656 * from incoming migration state. 2657 * 2658 * Returns: true if all register values were updated correctly, 2659 * false if some register was unknown or could not be written. 2660 * Note that we do not stop early on failure -- we will attempt 2661 * writing all registers in the list. 2662 */ 2663 bool write_list_to_cpustate(ARMCPU *cpu); 2664 2665 /** 2666 * write_cpustate_to_list: 2667 * @cpu: ARMCPU 2668 * @kvm_sync: true if this is for syncing back to KVM 2669 * 2670 * For each register listed in the ARMCPU cpreg_indexes list, write 2671 * its value from the ARMCPUState structure into the cpreg_values list. 2672 * This is used to copy info from TCG's working data structures into 2673 * KVM or for outbound migration. 2674 * 2675 * @kvm_sync is true if we are doing this in order to sync the 2676 * register state back to KVM. In this case we will only update 2677 * values in the list if the previous list->cpustate sync actually 2678 * successfully wrote the CPU state. Otherwise we will keep the value 2679 * that is in the list. 2680 * 2681 * Returns: true if all register values were read correctly, 2682 * false if some register was unknown or could not be read. 2683 * Note that we do not stop early on failure -- we will attempt 2684 * reading all registers in the list. 2685 */ 2686 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2687 2688 #define ARM_CPUID_TI915T 0x54029152 2689 #define ARM_CPUID_TI925T 0x54029252 2690 2691 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2692 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2693 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2694 2695 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2696 2697 #define cpu_list arm_cpu_list 2698 2699 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2700 * 2701 * If EL3 is 64-bit: 2702 * + NonSecure EL1 & 0 stage 1 2703 * + NonSecure EL1 & 0 stage 2 2704 * + NonSecure EL2 2705 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2706 * + Secure EL1 & 0 2707 * + Secure EL3 2708 * If EL3 is 32-bit: 2709 * + NonSecure PL1 & 0 stage 1 2710 * + NonSecure PL1 & 0 stage 2 2711 * + NonSecure PL2 2712 * + Secure PL0 2713 * + Secure PL1 2714 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2715 * 2716 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2717 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2718 * because they may differ in access permissions even if the VA->PA map is 2719 * the same 2720 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2721 * translation, which means that we have one mmu_idx that deals with two 2722 * concatenated translation regimes [this sort of combined s1+2 TLB is 2723 * architecturally permitted] 2724 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2725 * handling via the TLB. The only way to do a stage 1 translation without 2726 * the immediate stage 2 translation is via the ATS or AT system insns, 2727 * which can be slow-pathed and always do a page table walk. 2728 * The only use of stage 2 translations is either as part of an s1+2 2729 * lookup or when loading the descriptors during a stage 1 page table walk, 2730 * and in both those cases we don't use the TLB. 2731 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2732 * translation regimes, because they map reasonably well to each other 2733 * and they can't both be active at the same time. 2734 * 5. we want to be able to use the TLB for accesses done as part of a 2735 * stage1 page table walk, rather than having to walk the stage2 page 2736 * table over and over. 2737 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2738 * Never (PAN) bit within PSTATE. 2739 * 2740 * This gives us the following list of cases: 2741 * 2742 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 2743 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 2744 * NS EL1 EL1&0 stage 1+2 +PAN 2745 * NS EL0 EL2&0 2746 * NS EL2 EL2&0 2747 * NS EL2 EL2&0 +PAN 2748 * NS EL2 (aka NS PL2) 2749 * S EL0 EL1&0 (aka S PL0) 2750 * S EL1 EL1&0 (not used if EL3 is 32 bit) 2751 * S EL1 EL1&0 +PAN 2752 * S EL3 (aka S PL1) 2753 * 2754 * for a total of 11 different mmu_idx. 2755 * 2756 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2757 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2758 * NS EL2 if we ever model a Cortex-R52). 2759 * 2760 * M profile CPUs are rather different as they do not have a true MMU. 2761 * They have the following different MMU indexes: 2762 * User 2763 * Privileged 2764 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2765 * Privileged, execution priority negative (ditto) 2766 * If the CPU supports the v8M Security Extension then there are also: 2767 * Secure User 2768 * Secure Privileged 2769 * Secure User, execution priority negative 2770 * Secure Privileged, execution priority negative 2771 * 2772 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2773 * are not quite the same -- different CPU types (most notably M profile 2774 * vs A/R profile) would like to use MMU indexes with different semantics, 2775 * but since we don't ever need to use all of those in a single CPU we 2776 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2777 * modes + total number of M profile MMU modes". The lower bits of 2778 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2779 * the same for any particular CPU. 2780 * Variables of type ARMMUIdx are always full values, and the core 2781 * index values are in variables of type 'int'. 2782 * 2783 * Our enumeration includes at the end some entries which are not "true" 2784 * mmu_idx values in that they don't have corresponding TLBs and are only 2785 * valid for doing slow path page table walks. 2786 * 2787 * The constant names here are patterned after the general style of the names 2788 * of the AT/ATS operations. 2789 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2790 * For M profile we arrange them to have a bit for priv, a bit for negpri 2791 * and a bit for secure. 2792 */ 2793 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2794 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2795 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2796 2797 /* Meanings of the bits for A profile mmu idx values */ 2798 #define ARM_MMU_IDX_A_NS 0x8 2799 2800 /* Meanings of the bits for M profile mmu idx values */ 2801 #define ARM_MMU_IDX_M_PRIV 0x1 2802 #define ARM_MMU_IDX_M_NEGPRI 0x2 2803 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2804 2805 #define ARM_MMU_IDX_TYPE_MASK \ 2806 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2807 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2808 2809 typedef enum ARMMMUIdx { 2810 /* 2811 * A-profile. 2812 */ 2813 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, 2814 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, 2815 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, 2816 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, 2817 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, 2818 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, 2819 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, 2820 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, 2821 2822 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, 2823 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, 2824 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, 2825 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, 2826 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, 2827 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, 2828 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, 2829 2830 /* 2831 * These are not allocated TLBs and are used only for AT system 2832 * instructions or for the first stage of an S12 page table walk. 2833 */ 2834 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2835 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2836 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2837 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, 2838 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, 2839 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, 2840 /* 2841 * Not allocated a TLB: used only for second stage of an S12 page 2842 * table walk, or for descriptor loads during first stage of an S1 2843 * page table walk. Note that if we ever want to have a TLB for this 2844 * then various TLB flush insns which currently are no-ops or flush 2845 * only stage 1 MMU indexes will need to change to flush stage 2. 2846 */ 2847 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, 2848 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, 2849 2850 /* 2851 * M-profile. 2852 */ 2853 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2854 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2855 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2856 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2857 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2858 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2859 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2860 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2861 } ARMMMUIdx; 2862 2863 /* 2864 * Bit macros for the core-mmu-index values for each index, 2865 * for use when calling tlb_flush_by_mmuidx() and friends. 2866 */ 2867 #define TO_CORE_BIT(NAME) \ 2868 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2869 2870 typedef enum ARMMMUIdxBit { 2871 TO_CORE_BIT(E10_0), 2872 TO_CORE_BIT(E20_0), 2873 TO_CORE_BIT(E10_1), 2874 TO_CORE_BIT(E10_1_PAN), 2875 TO_CORE_BIT(E2), 2876 TO_CORE_BIT(E20_2), 2877 TO_CORE_BIT(E20_2_PAN), 2878 TO_CORE_BIT(SE10_0), 2879 TO_CORE_BIT(SE20_0), 2880 TO_CORE_BIT(SE10_1), 2881 TO_CORE_BIT(SE20_2), 2882 TO_CORE_BIT(SE10_1_PAN), 2883 TO_CORE_BIT(SE20_2_PAN), 2884 TO_CORE_BIT(SE2), 2885 TO_CORE_BIT(SE3), 2886 2887 TO_CORE_BIT(MUser), 2888 TO_CORE_BIT(MPriv), 2889 TO_CORE_BIT(MUserNegPri), 2890 TO_CORE_BIT(MPrivNegPri), 2891 TO_CORE_BIT(MSUser), 2892 TO_CORE_BIT(MSPriv), 2893 TO_CORE_BIT(MSUserNegPri), 2894 TO_CORE_BIT(MSPrivNegPri), 2895 } ARMMMUIdxBit; 2896 2897 #undef TO_CORE_BIT 2898 2899 #define MMU_USER_IDX 0 2900 2901 /* Indexes used when registering address spaces with cpu_address_space_init */ 2902 typedef enum ARMASIdx { 2903 ARMASIdx_NS = 0, 2904 ARMASIdx_S = 1, 2905 ARMASIdx_TagNS = 2, 2906 ARMASIdx_TagS = 3, 2907 } ARMASIdx; 2908 2909 /* Return the Exception Level targeted by debug exceptions. */ 2910 static inline int arm_debug_target_el(CPUARMState *env) 2911 { 2912 bool secure = arm_is_secure(env); 2913 bool route_to_el2 = false; 2914 2915 if (arm_is_el2_enabled(env)) { 2916 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2917 env->cp15.mdcr_el2 & MDCR_TDE; 2918 } 2919 2920 if (route_to_el2) { 2921 return 2; 2922 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2923 !arm_el_is_aa64(env, 3) && secure) { 2924 return 3; 2925 } else { 2926 return 1; 2927 } 2928 } 2929 2930 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2931 { 2932 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2933 * CSSELR is RAZ/WI. 2934 */ 2935 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2936 } 2937 2938 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 2939 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2940 { 2941 int cur_el = arm_current_el(env); 2942 int debug_el; 2943 2944 if (cur_el == 3) { 2945 return false; 2946 } 2947 2948 /* MDCR_EL3.SDD disables debug events from Secure state */ 2949 if (arm_is_secure_below_el3(env) 2950 && extract32(env->cp15.mdcr_el3, 16, 1)) { 2951 return false; 2952 } 2953 2954 /* 2955 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 2956 * while not masking the (D)ebug bit in DAIF. 2957 */ 2958 debug_el = arm_debug_target_el(env); 2959 2960 if (cur_el == debug_el) { 2961 return extract32(env->cp15.mdscr_el1, 13, 1) 2962 && !(env->daif & PSTATE_D); 2963 } 2964 2965 /* Otherwise the debug target needs to be a higher EL */ 2966 return debug_el > cur_el; 2967 } 2968 2969 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2970 { 2971 int el = arm_current_el(env); 2972 2973 if (el == 0 && arm_el_is_aa64(env, 1)) { 2974 return aa64_generate_debug_exceptions(env); 2975 } 2976 2977 if (arm_is_secure(env)) { 2978 int spd; 2979 2980 if (el == 0 && (env->cp15.sder & 1)) { 2981 /* SDER.SUIDEN means debug exceptions from Secure EL0 2982 * are always enabled. Otherwise they are controlled by 2983 * SDCR.SPD like those from other Secure ELs. 2984 */ 2985 return true; 2986 } 2987 2988 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2989 switch (spd) { 2990 case 1: 2991 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2992 case 0: 2993 /* For 0b00 we return true if external secure invasive debug 2994 * is enabled. On real hardware this is controlled by external 2995 * signals to the core. QEMU always permits debug, and behaves 2996 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2997 */ 2998 return true; 2999 case 2: 3000 return false; 3001 case 3: 3002 return true; 3003 } 3004 } 3005 3006 return el != 2; 3007 } 3008 3009 /* Return true if debugging exceptions are currently enabled. 3010 * This corresponds to what in ARM ARM pseudocode would be 3011 * if UsingAArch32() then 3012 * return AArch32.GenerateDebugExceptions() 3013 * else 3014 * return AArch64.GenerateDebugExceptions() 3015 * We choose to push the if() down into this function for clarity, 3016 * since the pseudocode has it at all callsites except for the one in 3017 * CheckSoftwareStep(), where it is elided because both branches would 3018 * always return the same value. 3019 */ 3020 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3021 { 3022 if (env->aarch64) { 3023 return aa64_generate_debug_exceptions(env); 3024 } else { 3025 return aa32_generate_debug_exceptions(env); 3026 } 3027 } 3028 3029 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3030 * implicitly means this always returns false in pre-v8 CPUs.) 3031 */ 3032 static inline bool arm_singlestep_active(CPUARMState *env) 3033 { 3034 return extract32(env->cp15.mdscr_el1, 0, 1) 3035 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3036 && arm_generate_debug_exceptions(env); 3037 } 3038 3039 static inline bool arm_sctlr_b(CPUARMState *env) 3040 { 3041 return 3042 /* We need not implement SCTLR.ITD in user-mode emulation, so 3043 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3044 * This lets people run BE32 binaries with "-cpu any". 3045 */ 3046 #ifndef CONFIG_USER_ONLY 3047 !arm_feature(env, ARM_FEATURE_V7) && 3048 #endif 3049 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3050 } 3051 3052 uint64_t arm_sctlr(CPUARMState *env, int el); 3053 3054 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3055 bool sctlr_b) 3056 { 3057 #ifdef CONFIG_USER_ONLY 3058 /* 3059 * In system mode, BE32 is modelled in line with the 3060 * architecture (as word-invariant big-endianness), where loads 3061 * and stores are done little endian but from addresses which 3062 * are adjusted by XORing with the appropriate constant. So the 3063 * endianness to use for the raw data access is not affected by 3064 * SCTLR.B. 3065 * In user mode, however, we model BE32 as byte-invariant 3066 * big-endianness (because user-only code cannot tell the 3067 * difference), and so we need to use a data access endianness 3068 * that depends on SCTLR.B. 3069 */ 3070 if (sctlr_b) { 3071 return true; 3072 } 3073 #endif 3074 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3075 return env->uncached_cpsr & CPSR_E; 3076 } 3077 3078 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3079 { 3080 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3081 } 3082 3083 /* Return true if the processor is in big-endian mode. */ 3084 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3085 { 3086 if (!is_a64(env)) { 3087 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3088 } else { 3089 int cur_el = arm_current_el(env); 3090 uint64_t sctlr = arm_sctlr(env, cur_el); 3091 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3092 } 3093 } 3094 3095 #include "exec/cpu-all.h" 3096 3097 /* 3098 * We have more than 32-bits worth of state per TB, so we split the data 3099 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3100 * We collect these two parts in CPUARMTBFlags where they are named 3101 * flags and flags2 respectively. 3102 * 3103 * The flags that are shared between all execution modes, TBFLAG_ANY, 3104 * are stored in flags. The flags that are specific to a given mode 3105 * are stores in flags2. Since cs_base is sized on the configured 3106 * address size, flags2 always has 64-bits for A64, and a minimum of 3107 * 32-bits for A32 and M32. 3108 * 3109 * The bits for 32-bit A-profile and M-profile partially overlap: 3110 * 3111 * 31 23 11 10 0 3112 * +-------------+----------+----------------+ 3113 * | | | TBFLAG_A32 | 3114 * | TBFLAG_AM32 | +-----+----------+ 3115 * | | |TBFLAG_M32| 3116 * +-------------+----------------+----------+ 3117 * 31 23 6 5 0 3118 * 3119 * Unless otherwise noted, these bits are cached in env->hflags. 3120 */ 3121 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3122 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3123 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3124 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3125 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3126 /* Target EL if we take a floating-point-disabled exception */ 3127 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3128 /* For A-profile only, target EL for debug exceptions. */ 3129 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) 3130 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3131 FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) 3132 FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1) 3133 3134 /* 3135 * Bit usage when in AArch32 state, both A- and M-profile. 3136 */ 3137 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3138 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3139 3140 /* 3141 * Bit usage when in AArch32 state, for A-profile only. 3142 */ 3143 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3144 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3145 /* 3146 * We store the bottom two bits of the CPAR as TB flags and handle 3147 * checks on the other bits at runtime. This shares the same bits as 3148 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3149 * Not cached, because VECLEN+VECSTRIDE are not cached. 3150 */ 3151 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3152 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3153 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3154 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3155 /* 3156 * Indicates whether cp register reads and writes by guest code should access 3157 * the secure or nonsecure bank of banked registers; note that this is not 3158 * the same thing as the current security state of the processor! 3159 */ 3160 FIELD(TBFLAG_A32, NS, 10, 1) 3161 3162 /* 3163 * Bit usage when in AArch32 state, for M-profile only. 3164 */ 3165 /* Handler (ie not Thread) mode */ 3166 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3167 /* Whether we should generate stack-limit checks */ 3168 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3169 /* Set if FPCCR.LSPACT is set */ 3170 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3171 /* Set if we must create a new FP context */ 3172 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3173 /* Set if FPCCR.S does not match current security state */ 3174 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3175 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3176 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3177 3178 /* 3179 * Bit usage when in AArch64 state 3180 */ 3181 FIELD(TBFLAG_A64, TBII, 0, 2) 3182 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3183 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3184 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3185 FIELD(TBFLAG_A64, BT, 9, 1) 3186 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3187 FIELD(TBFLAG_A64, TBID, 12, 2) 3188 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3189 FIELD(TBFLAG_A64, ATA, 15, 1) 3190 FIELD(TBFLAG_A64, TCMA, 16, 2) 3191 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3192 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3193 3194 /* 3195 * Helpers for using the above. 3196 */ 3197 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3198 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3199 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3200 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3201 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3202 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3203 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3204 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3205 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3206 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3207 3208 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3209 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3210 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3211 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3212 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3213 3214 /** 3215 * cpu_mmu_index: 3216 * @env: The cpu environment 3217 * @ifetch: True for code access, false for data access. 3218 * 3219 * Return the core mmu index for the current translation regime. 3220 * This function is used by generic TCG code paths. 3221 */ 3222 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3223 { 3224 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3225 } 3226 3227 static inline bool bswap_code(bool sctlr_b) 3228 { 3229 #ifdef CONFIG_USER_ONLY 3230 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3231 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3232 * would also end up as a mixed-endian mode with BE code, LE data. 3233 */ 3234 return 3235 #if TARGET_BIG_ENDIAN 3236 1 ^ 3237 #endif 3238 sctlr_b; 3239 #else 3240 /* All code access in ARM is little endian, and there are no loaders 3241 * doing swaps that need to be reversed 3242 */ 3243 return 0; 3244 #endif 3245 } 3246 3247 #ifdef CONFIG_USER_ONLY 3248 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3249 { 3250 return 3251 #if TARGET_BIG_ENDIAN 3252 1 ^ 3253 #endif 3254 arm_cpu_data_is_big_endian(env); 3255 } 3256 #endif 3257 3258 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3259 target_ulong *cs_base, uint32_t *flags); 3260 3261 enum { 3262 QEMU_PSCI_CONDUIT_DISABLED = 0, 3263 QEMU_PSCI_CONDUIT_SMC = 1, 3264 QEMU_PSCI_CONDUIT_HVC = 2, 3265 }; 3266 3267 #ifndef CONFIG_USER_ONLY 3268 /* Return the address space index to use for a memory access */ 3269 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3270 { 3271 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3272 } 3273 3274 /* Return the AddressSpace to use for a memory access 3275 * (which depends on whether the access is S or NS, and whether 3276 * the board gave us a separate AddressSpace for S accesses). 3277 */ 3278 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3279 { 3280 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3281 } 3282 #endif 3283 3284 /** 3285 * arm_register_pre_el_change_hook: 3286 * Register a hook function which will be called immediately before this 3287 * CPU changes exception level or mode. The hook function will be 3288 * passed a pointer to the ARMCPU and the opaque data pointer passed 3289 * to this function when the hook was registered. 3290 * 3291 * Note that if a pre-change hook is called, any registered post-change hooks 3292 * are guaranteed to subsequently be called. 3293 */ 3294 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3295 void *opaque); 3296 /** 3297 * arm_register_el_change_hook: 3298 * Register a hook function which will be called immediately after this 3299 * CPU changes exception level or mode. The hook function will be 3300 * passed a pointer to the ARMCPU and the opaque data pointer passed 3301 * to this function when the hook was registered. 3302 * 3303 * Note that any registered hooks registered here are guaranteed to be called 3304 * if pre-change hooks have been. 3305 */ 3306 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3307 *opaque); 3308 3309 /** 3310 * arm_rebuild_hflags: 3311 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3312 */ 3313 void arm_rebuild_hflags(CPUARMState *env); 3314 3315 /** 3316 * aa32_vfp_dreg: 3317 * Return a pointer to the Dn register within env in 32-bit mode. 3318 */ 3319 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3320 { 3321 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3322 } 3323 3324 /** 3325 * aa32_vfp_qreg: 3326 * Return a pointer to the Qn register within env in 32-bit mode. 3327 */ 3328 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3329 { 3330 return &env->vfp.zregs[regno].d[0]; 3331 } 3332 3333 /** 3334 * aa64_vfp_qreg: 3335 * Return a pointer to the Qn register within env in 64-bit mode. 3336 */ 3337 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3338 { 3339 return &env->vfp.zregs[regno].d[0]; 3340 } 3341 3342 /* Shared between translate-sve.c and sve_helper.c. */ 3343 extern const uint64_t pred_esz_masks[4]; 3344 3345 /* Helper for the macros below, validating the argument type. */ 3346 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) 3347 { 3348 return x; 3349 } 3350 3351 /* 3352 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. 3353 * Using these should be a bit more self-documenting than using the 3354 * generic target bits directly. 3355 */ 3356 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) 3357 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) 3358 3359 /* 3360 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3361 */ 3362 #define PAGE_BTI PAGE_TARGET_1 3363 #define PAGE_MTE PAGE_TARGET_2 3364 3365 #ifdef TARGET_TAGGED_ADDRESSES 3366 /** 3367 * cpu_untagged_addr: 3368 * @cs: CPU context 3369 * @x: tagged address 3370 * 3371 * Remove any address tag from @x. This is explicitly related to the 3372 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3373 * 3374 * There should be a better place to put this, but we need this in 3375 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3376 */ 3377 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3378 { 3379 ARMCPU *cpu = ARM_CPU(cs); 3380 if (cpu->env.tagged_addr_enable) { 3381 /* 3382 * TBI is enabled for userspace but not kernelspace addresses. 3383 * Only clear the tag if bit 55 is clear. 3384 */ 3385 x &= sextract64(x, 0, 56); 3386 } 3387 return x; 3388 } 3389 #endif 3390 3391 /* 3392 * Naming convention for isar_feature functions: 3393 * Functions which test 32-bit ID registers should have _aa32_ in 3394 * their name. Functions which test 64-bit ID registers should have 3395 * _aa64_ in their name. These must only be used in code where we 3396 * know for certain that the CPU has AArch32 or AArch64 respectively 3397 * or where the correct answer for a CPU which doesn't implement that 3398 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3399 * system registers that are specific to that CPU state, for "should 3400 * we let this system register bit be set" tests where the 32-bit 3401 * flavour of the register doesn't have the bit, and so on). 3402 * Functions which simply ask "does this feature exist at all" have 3403 * _any_ in their name, and always return the logical OR of the _aa64_ 3404 * and the _aa32_ function. 3405 */ 3406 3407 /* 3408 * 32-bit feature tests via id registers. 3409 */ 3410 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3411 { 3412 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3413 } 3414 3415 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3416 { 3417 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3418 } 3419 3420 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3421 { 3422 /* (M-profile) low-overhead loops and branch future */ 3423 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3424 } 3425 3426 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3427 { 3428 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3429 } 3430 3431 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3432 { 3433 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3434 } 3435 3436 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3437 { 3438 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3439 } 3440 3441 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3442 { 3443 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3444 } 3445 3446 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3447 { 3448 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3449 } 3450 3451 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3452 { 3453 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3454 } 3455 3456 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3457 { 3458 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3459 } 3460 3461 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3462 { 3463 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3464 } 3465 3466 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3467 { 3468 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3469 } 3470 3471 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3472 { 3473 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3474 } 3475 3476 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3477 { 3478 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3479 } 3480 3481 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3482 { 3483 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3484 } 3485 3486 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3487 { 3488 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3489 } 3490 3491 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3492 { 3493 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3494 } 3495 3496 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3497 { 3498 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3499 } 3500 3501 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3502 { 3503 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3504 } 3505 3506 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3507 { 3508 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3509 } 3510 3511 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3512 { 3513 /* 3514 * Return true if M-profile state handling insns 3515 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3516 */ 3517 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3518 } 3519 3520 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3521 { 3522 /* Sadly this is encoded differently for A-profile and M-profile */ 3523 if (isar_feature_aa32_mprofile(id)) { 3524 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3525 } else { 3526 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3527 } 3528 } 3529 3530 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3531 { 3532 /* 3533 * Return true if MVE is supported (either integer or floating point). 3534 * We must check for M-profile as the MVFR1 field means something 3535 * else for A-profile. 3536 */ 3537 return isar_feature_aa32_mprofile(id) && 3538 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3539 } 3540 3541 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3542 { 3543 /* 3544 * Return true if MVE is supported (either integer or floating point). 3545 * We must check for M-profile as the MVFR1 field means something 3546 * else for A-profile. 3547 */ 3548 return isar_feature_aa32_mprofile(id) && 3549 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3550 } 3551 3552 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3553 { 3554 /* 3555 * Return true if either VFP or SIMD is implemented. 3556 * In this case, a minimum of VFP w/ D0-D15. 3557 */ 3558 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3559 } 3560 3561 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3562 { 3563 /* Return true if D16-D31 are implemented */ 3564 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3565 } 3566 3567 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3568 { 3569 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3570 } 3571 3572 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3573 { 3574 /* Return true if CPU supports single precision floating point, VFPv2 */ 3575 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3576 } 3577 3578 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3579 { 3580 /* Return true if CPU supports single precision floating point, VFPv3 */ 3581 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3582 } 3583 3584 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3585 { 3586 /* Return true if CPU supports double precision floating point, VFPv2 */ 3587 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3588 } 3589 3590 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3591 { 3592 /* Return true if CPU supports double precision floating point, VFPv3 */ 3593 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3594 } 3595 3596 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3597 { 3598 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3599 } 3600 3601 /* 3602 * We always set the FP and SIMD FP16 fields to indicate identical 3603 * levels of support (assuming SIMD is implemented at all), so 3604 * we only need one set of accessors. 3605 */ 3606 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3607 { 3608 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3609 } 3610 3611 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3612 { 3613 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3614 } 3615 3616 /* 3617 * Note that this ID register field covers both VFP and Neon FMAC, 3618 * so should usually be tested in combination with some other 3619 * check that confirms the presence of whichever of VFP or Neon is 3620 * relevant, to avoid accidentally enabling a Neon feature on 3621 * a VFP-no-Neon core or vice-versa. 3622 */ 3623 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3624 { 3625 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3626 } 3627 3628 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3629 { 3630 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3631 } 3632 3633 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3634 { 3635 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3636 } 3637 3638 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3639 { 3640 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3641 } 3642 3643 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3644 { 3645 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3646 } 3647 3648 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3649 { 3650 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3651 } 3652 3653 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3654 { 3655 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3656 } 3657 3658 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3659 { 3660 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3661 } 3662 3663 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3664 { 3665 /* 0xf means "non-standard IMPDEF PMU" */ 3666 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3667 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3668 } 3669 3670 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3671 { 3672 /* 0xf means "non-standard IMPDEF PMU" */ 3673 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3674 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3675 } 3676 3677 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3678 { 3679 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3680 } 3681 3682 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3683 { 3684 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3685 } 3686 3687 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3688 { 3689 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3690 } 3691 3692 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3693 { 3694 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3695 } 3696 3697 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3698 { 3699 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3700 } 3701 3702 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3703 { 3704 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3705 } 3706 3707 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3708 { 3709 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3710 } 3711 3712 /* 3713 * 64-bit feature tests via id registers. 3714 */ 3715 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3716 { 3717 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3718 } 3719 3720 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3721 { 3722 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3723 } 3724 3725 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3726 { 3727 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3728 } 3729 3730 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3731 { 3732 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3733 } 3734 3735 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3736 { 3737 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3738 } 3739 3740 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3741 { 3742 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3743 } 3744 3745 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3746 { 3747 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3748 } 3749 3750 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3751 { 3752 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3753 } 3754 3755 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3756 { 3757 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3758 } 3759 3760 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3761 { 3762 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3763 } 3764 3765 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3766 { 3767 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3768 } 3769 3770 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3771 { 3772 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3773 } 3774 3775 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3776 { 3777 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3778 } 3779 3780 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3781 { 3782 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3783 } 3784 3785 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3786 { 3787 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3788 } 3789 3790 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3791 { 3792 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3793 } 3794 3795 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3796 { 3797 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3798 } 3799 3800 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3801 { 3802 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3803 } 3804 3805 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3806 { 3807 /* 3808 * Return true if any form of pauth is enabled, as this 3809 * predicate controls migration of the 128-bit keys. 3810 */ 3811 return (id->id_aa64isar1 & 3812 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3813 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3814 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3815 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3816 } 3817 3818 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3819 { 3820 /* 3821 * Return true if pauth is enabled with the architected QARMA algorithm. 3822 * QEMU will always set APA+GPA to the same value. 3823 */ 3824 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3825 } 3826 3827 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3828 { 3829 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3830 } 3831 3832 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3833 { 3834 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3835 } 3836 3837 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3838 { 3839 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3840 } 3841 3842 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3843 { 3844 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3845 } 3846 3847 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3848 { 3849 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3850 } 3851 3852 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3853 { 3854 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3855 } 3856 3857 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3858 { 3859 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3860 } 3861 3862 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3863 { 3864 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3865 } 3866 3867 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3868 { 3869 /* We always set the AdvSIMD and FP fields identically. */ 3870 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3871 } 3872 3873 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3874 { 3875 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3876 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3877 } 3878 3879 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3880 { 3881 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3882 } 3883 3884 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3885 { 3886 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3887 } 3888 3889 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3890 { 3891 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 3892 } 3893 3894 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3895 { 3896 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3897 } 3898 3899 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 3900 { 3901 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 3902 } 3903 3904 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3905 { 3906 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3907 } 3908 3909 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3910 { 3911 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3912 } 3913 3914 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3915 { 3916 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3917 } 3918 3919 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3920 { 3921 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3922 } 3923 3924 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 3925 { 3926 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 3927 } 3928 3929 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 3930 { 3931 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 3932 } 3933 3934 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3935 { 3936 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3937 } 3938 3939 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 3940 { 3941 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 3942 } 3943 3944 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 3945 { 3946 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 3947 } 3948 3949 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 3950 { 3951 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 3952 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3953 } 3954 3955 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 3956 { 3957 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 3958 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3959 } 3960 3961 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 3962 { 3963 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 3964 } 3965 3966 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 3967 { 3968 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 3969 } 3970 3971 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 3972 { 3973 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 3974 } 3975 3976 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 3977 { 3978 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 3979 } 3980 3981 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 3982 { 3983 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 3984 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 3985 } 3986 3987 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 3988 { 3989 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 3990 } 3991 3992 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 3993 { 3994 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 3995 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 3996 } 3997 3998 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 3999 { 4000 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4001 } 4002 4003 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4004 { 4005 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4006 } 4007 4008 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4009 { 4010 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4011 } 4012 4013 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4014 { 4015 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4016 } 4017 4018 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4019 { 4020 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4021 } 4022 4023 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4024 { 4025 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4026 } 4027 4028 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4029 { 4030 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4031 } 4032 4033 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4034 { 4035 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4036 } 4037 4038 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4039 { 4040 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4041 } 4042 4043 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4044 { 4045 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4046 } 4047 4048 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4049 { 4050 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4051 } 4052 4053 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4054 { 4055 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4056 } 4057 4058 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4059 { 4060 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4061 } 4062 4063 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4064 { 4065 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4066 } 4067 4068 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4069 { 4070 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4071 } 4072 4073 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4074 { 4075 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4076 } 4077 4078 /* 4079 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4080 */ 4081 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4082 { 4083 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4084 } 4085 4086 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4087 { 4088 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4089 } 4090 4091 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 4092 { 4093 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 4094 } 4095 4096 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 4097 { 4098 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 4099 } 4100 4101 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4102 { 4103 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4104 } 4105 4106 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4107 { 4108 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4109 } 4110 4111 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4112 { 4113 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4114 } 4115 4116 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4117 { 4118 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4119 } 4120 4121 /* 4122 * Forward to the above feature tests given an ARMCPU pointer. 4123 */ 4124 #define cpu_isar_feature(name, cpu) \ 4125 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4126 4127 #endif 4128