1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 #include "cpu-qom.h" 26 #include "exec/cpu-defs.h" 27 28 /* ARM processors have a weak memory model */ 29 #define TCG_GUEST_DEFAULT_MO (0) 30 31 #define EXCP_UDEF 1 /* undefined instruction */ 32 #define EXCP_SWI 2 /* software interrupt */ 33 #define EXCP_PREFETCH_ABORT 3 34 #define EXCP_DATA_ABORT 4 35 #define EXCP_IRQ 5 36 #define EXCP_FIQ 6 37 #define EXCP_BKPT 7 38 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 39 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 40 #define EXCP_HVC 11 /* HyperVisor Call */ 41 #define EXCP_HYP_TRAP 12 42 #define EXCP_SMC 13 /* Secure Monitor Call */ 43 #define EXCP_VIRQ 14 44 #define EXCP_VFIQ 15 45 #define EXCP_SEMIHOST 16 /* semihosting call */ 46 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 47 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 48 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 49 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 50 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 51 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 52 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 53 54 #define ARMV7M_EXCP_RESET 1 55 #define ARMV7M_EXCP_NMI 2 56 #define ARMV7M_EXCP_HARD 3 57 #define ARMV7M_EXCP_MEM 4 58 #define ARMV7M_EXCP_BUS 5 59 #define ARMV7M_EXCP_USAGE 6 60 #define ARMV7M_EXCP_SECURE 7 61 #define ARMV7M_EXCP_SVC 11 62 #define ARMV7M_EXCP_DEBUG 12 63 #define ARMV7M_EXCP_PENDSV 14 64 #define ARMV7M_EXCP_SYSTICK 15 65 66 /* For M profile, some registers are banked secure vs non-secure; 67 * these are represented as a 2-element array where the first element 68 * is the non-secure copy and the second is the secure copy. 69 * When the CPU does not have implement the security extension then 70 * only the first element is used. 71 * This means that the copy for the current security state can be 72 * accessed via env->registerfield[env->v7m.secure] (whether the security 73 * extension is implemented or not). 74 */ 75 enum { 76 M_REG_NS = 0, 77 M_REG_S = 1, 78 M_REG_NUM_BANKS = 2, 79 }; 80 81 /* ARM-specific interrupt pending bits. */ 82 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 83 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 84 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 85 86 /* The usual mapping for an AArch64 system register to its AArch32 87 * counterpart is for the 32 bit world to have access to the lower 88 * half only (with writes leaving the upper half untouched). It's 89 * therefore useful to be able to pass TCG the offset of the least 90 * significant half of a uint64_t struct member. 91 */ 92 #ifdef HOST_WORDS_BIGENDIAN 93 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 94 #define offsetofhigh32(S, M) offsetof(S, M) 95 #else 96 #define offsetoflow32(S, M) offsetof(S, M) 97 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 98 #endif 99 100 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 101 #define ARM_CPU_IRQ 0 102 #define ARM_CPU_FIQ 1 103 #define ARM_CPU_VIRQ 2 104 #define ARM_CPU_VFIQ 3 105 106 /* ARM-specific extra insn start words: 107 * 1: Conditional execution bits 108 * 2: Partial exception syndrome for data aborts 109 */ 110 #define TARGET_INSN_START_EXTRA_WORDS 2 111 112 /* The 2nd extra word holding syndrome info for data aborts does not use 113 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 114 * help the sleb128 encoder do a better job. 115 * When restoring the CPU state, we shift it back up. 116 */ 117 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 118 #define ARM_INSN_START_WORD2_SHIFT 14 119 120 /* We currently assume float and double are IEEE single and double 121 precision respectively. 122 Doing runtime conversions is tricky because VFP registers may contain 123 integer values (eg. as the result of a FTOSI instruction). 124 s<2n> maps to the least significant half of d<n> 125 s<2n+1> maps to the most significant half of d<n> 126 */ 127 128 /** 129 * DynamicGDBXMLInfo: 130 * @desc: Contains the XML descriptions. 131 * @num_cpregs: Number of the Coprocessor registers seen by GDB. 132 * @cpregs_keys: Array that contains the corresponding Key of 133 * a given cpreg with the same order of the cpreg in the XML description. 134 */ 135 typedef struct DynamicGDBXMLInfo { 136 char *desc; 137 int num_cpregs; 138 uint32_t *cpregs_keys; 139 } DynamicGDBXMLInfo; 140 141 /* CPU state for each instance of a generic timer (in cp15 c14) */ 142 typedef struct ARMGenericTimer { 143 uint64_t cval; /* Timer CompareValue register */ 144 uint64_t ctl; /* Timer Control register */ 145 } ARMGenericTimer; 146 147 #define GTIMER_PHYS 0 148 #define GTIMER_VIRT 1 149 #define GTIMER_HYP 2 150 #define GTIMER_SEC 3 151 #define NUM_GTIMERS 4 152 153 typedef struct { 154 uint64_t raw_tcr; 155 uint32_t mask; 156 uint32_t base_mask; 157 } TCR; 158 159 /* Define a maximum sized vector register. 160 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 161 * For 64-bit, this is a 2048-bit SVE register. 162 * 163 * Note that the mapping between S, D, and Q views of the register bank 164 * differs between AArch64 and AArch32. 165 * In AArch32: 166 * Qn = regs[n].d[1]:regs[n].d[0] 167 * Dn = regs[n / 2].d[n & 1] 168 * Sn = regs[n / 4].d[n % 4 / 2], 169 * bits 31..0 for even n, and bits 63..32 for odd n 170 * (and regs[16] to regs[31] are inaccessible) 171 * In AArch64: 172 * Zn = regs[n].d[*] 173 * Qn = regs[n].d[1]:regs[n].d[0] 174 * Dn = regs[n].d[0] 175 * Sn = regs[n].d[0] bits 31..0 176 * Hn = regs[n].d[0] bits 15..0 177 * 178 * This corresponds to the architecturally defined mapping between 179 * the two execution states, and means we do not need to explicitly 180 * map these registers when changing states. 181 * 182 * Align the data for use with TCG host vector operations. 183 */ 184 185 #ifdef TARGET_AARCH64 186 # define ARM_MAX_VQ 16 187 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 188 uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq); 189 #else 190 # define ARM_MAX_VQ 1 191 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 192 static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq) 193 { return 0; } 194 #endif 195 196 typedef struct ARMVectorReg { 197 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 198 } ARMVectorReg; 199 200 #ifdef TARGET_AARCH64 201 /* In AArch32 mode, predicate registers do not exist at all. */ 202 typedef struct ARMPredicateReg { 203 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 204 } ARMPredicateReg; 205 206 /* In AArch32 mode, PAC keys do not exist at all. */ 207 typedef struct ARMPACKey { 208 uint64_t lo, hi; 209 } ARMPACKey; 210 #endif 211 212 213 typedef struct CPUARMState { 214 /* Regs for current mode. */ 215 uint32_t regs[16]; 216 217 /* 32/64 switch only happens when taking and returning from 218 * exceptions so the overlap semantics are taken care of then 219 * instead of having a complicated union. 220 */ 221 /* Regs for A64 mode. */ 222 uint64_t xregs[32]; 223 uint64_t pc; 224 /* PSTATE isn't an architectural register for ARMv8. However, it is 225 * convenient for us to assemble the underlying state into a 32 bit format 226 * identical to the architectural format used for the SPSR. (This is also 227 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 228 * 'pstate' register are.) Of the PSTATE bits: 229 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 230 * semantics as for AArch32, as described in the comments on each field) 231 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 232 * DAIF (exception masks) are kept in env->daif 233 * BTYPE is kept in env->btype 234 * all other bits are stored in their correct places in env->pstate 235 */ 236 uint32_t pstate; 237 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 238 239 /* Cached TBFLAGS state. See below for which bits are included. */ 240 uint32_t hflags; 241 242 /* Frequently accessed CPSR bits are stored separately for efficiency. 243 This contains all the other bits. Use cpsr_{read,write} to access 244 the whole CPSR. */ 245 uint32_t uncached_cpsr; 246 uint32_t spsr; 247 248 /* Banked registers. */ 249 uint64_t banked_spsr[8]; 250 uint32_t banked_r13[8]; 251 uint32_t banked_r14[8]; 252 253 /* These hold r8-r12. */ 254 uint32_t usr_regs[5]; 255 uint32_t fiq_regs[5]; 256 257 /* cpsr flag cache for faster execution */ 258 uint32_t CF; /* 0 or 1 */ 259 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 260 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 261 uint32_t ZF; /* Z set if zero. */ 262 uint32_t QF; /* 0 or 1 */ 263 uint32_t GE; /* cpsr[19:16] */ 264 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 265 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 266 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 267 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 268 269 uint64_t elr_el[4]; /* AArch64 exception link regs */ 270 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 271 272 /* System control coprocessor (cp15) */ 273 struct { 274 uint32_t c0_cpuid; 275 union { /* Cache size selection */ 276 struct { 277 uint64_t _unused_csselr0; 278 uint64_t csselr_ns; 279 uint64_t _unused_csselr1; 280 uint64_t csselr_s; 281 }; 282 uint64_t csselr_el[4]; 283 }; 284 union { /* System control register. */ 285 struct { 286 uint64_t _unused_sctlr; 287 uint64_t sctlr_ns; 288 uint64_t hsctlr; 289 uint64_t sctlr_s; 290 }; 291 uint64_t sctlr_el[4]; 292 }; 293 uint64_t cpacr_el1; /* Architectural feature access control register */ 294 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 295 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 296 uint64_t sder; /* Secure debug enable register. */ 297 uint32_t nsacr; /* Non-secure access control register. */ 298 union { /* MMU translation table base 0. */ 299 struct { 300 uint64_t _unused_ttbr0_0; 301 uint64_t ttbr0_ns; 302 uint64_t _unused_ttbr0_1; 303 uint64_t ttbr0_s; 304 }; 305 uint64_t ttbr0_el[4]; 306 }; 307 union { /* MMU translation table base 1. */ 308 struct { 309 uint64_t _unused_ttbr1_0; 310 uint64_t ttbr1_ns; 311 uint64_t _unused_ttbr1_1; 312 uint64_t ttbr1_s; 313 }; 314 uint64_t ttbr1_el[4]; 315 }; 316 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 317 /* MMU translation table base control. */ 318 TCR tcr_el[4]; 319 TCR vtcr_el2; /* Virtualization Translation Control. */ 320 uint32_t c2_data; /* MPU data cacheable bits. */ 321 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 322 union { /* MMU domain access control register 323 * MPU write buffer control. 324 */ 325 struct { 326 uint64_t dacr_ns; 327 uint64_t dacr_s; 328 }; 329 struct { 330 uint64_t dacr32_el2; 331 }; 332 }; 333 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 334 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 335 uint64_t hcr_el2; /* Hypervisor configuration register */ 336 uint64_t scr_el3; /* Secure configuration register. */ 337 union { /* Fault status registers. */ 338 struct { 339 uint64_t ifsr_ns; 340 uint64_t ifsr_s; 341 }; 342 struct { 343 uint64_t ifsr32_el2; 344 }; 345 }; 346 union { 347 struct { 348 uint64_t _unused_dfsr; 349 uint64_t dfsr_ns; 350 uint64_t hsr; 351 uint64_t dfsr_s; 352 }; 353 uint64_t esr_el[4]; 354 }; 355 uint32_t c6_region[8]; /* MPU base/size registers. */ 356 union { /* Fault address registers. */ 357 struct { 358 uint64_t _unused_far0; 359 #ifdef HOST_WORDS_BIGENDIAN 360 uint32_t ifar_ns; 361 uint32_t dfar_ns; 362 uint32_t ifar_s; 363 uint32_t dfar_s; 364 #else 365 uint32_t dfar_ns; 366 uint32_t ifar_ns; 367 uint32_t dfar_s; 368 uint32_t ifar_s; 369 #endif 370 uint64_t _unused_far3; 371 }; 372 uint64_t far_el[4]; 373 }; 374 uint64_t hpfar_el2; 375 uint64_t hstr_el2; 376 union { /* Translation result. */ 377 struct { 378 uint64_t _unused_par_0; 379 uint64_t par_ns; 380 uint64_t _unused_par_1; 381 uint64_t par_s; 382 }; 383 uint64_t par_el[4]; 384 }; 385 386 uint32_t c9_insn; /* Cache lockdown registers. */ 387 uint32_t c9_data; 388 uint64_t c9_pmcr; /* performance monitor control register */ 389 uint64_t c9_pmcnten; /* perf monitor counter enables */ 390 uint64_t c9_pmovsr; /* perf monitor overflow status */ 391 uint64_t c9_pmuserenr; /* perf monitor user enable */ 392 uint64_t c9_pmselr; /* perf monitor counter selection register */ 393 uint64_t c9_pminten; /* perf monitor interrupt enables */ 394 union { /* Memory attribute redirection */ 395 struct { 396 #ifdef HOST_WORDS_BIGENDIAN 397 uint64_t _unused_mair_0; 398 uint32_t mair1_ns; 399 uint32_t mair0_ns; 400 uint64_t _unused_mair_1; 401 uint32_t mair1_s; 402 uint32_t mair0_s; 403 #else 404 uint64_t _unused_mair_0; 405 uint32_t mair0_ns; 406 uint32_t mair1_ns; 407 uint64_t _unused_mair_1; 408 uint32_t mair0_s; 409 uint32_t mair1_s; 410 #endif 411 }; 412 uint64_t mair_el[4]; 413 }; 414 union { /* vector base address register */ 415 struct { 416 uint64_t _unused_vbar; 417 uint64_t vbar_ns; 418 uint64_t hvbar; 419 uint64_t vbar_s; 420 }; 421 uint64_t vbar_el[4]; 422 }; 423 uint32_t mvbar; /* (monitor) vector base address register */ 424 struct { /* FCSE PID. */ 425 uint32_t fcseidr_ns; 426 uint32_t fcseidr_s; 427 }; 428 union { /* Context ID. */ 429 struct { 430 uint64_t _unused_contextidr_0; 431 uint64_t contextidr_ns; 432 uint64_t _unused_contextidr_1; 433 uint64_t contextidr_s; 434 }; 435 uint64_t contextidr_el[4]; 436 }; 437 union { /* User RW Thread register. */ 438 struct { 439 uint64_t tpidrurw_ns; 440 uint64_t tpidrprw_ns; 441 uint64_t htpidr; 442 uint64_t _tpidr_el3; 443 }; 444 uint64_t tpidr_el[4]; 445 }; 446 /* The secure banks of these registers don't map anywhere */ 447 uint64_t tpidrurw_s; 448 uint64_t tpidrprw_s; 449 uint64_t tpidruro_s; 450 451 union { /* User RO Thread register. */ 452 uint64_t tpidruro_ns; 453 uint64_t tpidrro_el[1]; 454 }; 455 uint64_t c14_cntfrq; /* Counter Frequency register */ 456 uint64_t c14_cntkctl; /* Timer Control register */ 457 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 458 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 459 ARMGenericTimer c14_timer[NUM_GTIMERS]; 460 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 461 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 462 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 463 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 464 uint32_t c15_threadid; /* TI debugger thread-ID. */ 465 uint32_t c15_config_base_address; /* SCU base address. */ 466 uint32_t c15_diagnostic; /* diagnostic register */ 467 uint32_t c15_power_diagnostic; 468 uint32_t c15_power_control; /* power control */ 469 uint64_t dbgbvr[16]; /* breakpoint value registers */ 470 uint64_t dbgbcr[16]; /* breakpoint control registers */ 471 uint64_t dbgwvr[16]; /* watchpoint value registers */ 472 uint64_t dbgwcr[16]; /* watchpoint control registers */ 473 uint64_t mdscr_el1; 474 uint64_t oslsr_el1; /* OS Lock Status */ 475 uint64_t mdcr_el2; 476 uint64_t mdcr_el3; 477 /* Stores the architectural value of the counter *the last time it was 478 * updated* by pmccntr_op_start. Accesses should always be surrounded 479 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 480 * architecturally-correct value is being read/set. 481 */ 482 uint64_t c15_ccnt; 483 /* Stores the delta between the architectural value and the underlying 484 * cycle count during normal operation. It is used to update c15_ccnt 485 * to be the correct architectural value before accesses. During 486 * accesses, c15_ccnt_delta contains the underlying count being used 487 * for the access, after which it reverts to the delta value in 488 * pmccntr_op_finish. 489 */ 490 uint64_t c15_ccnt_delta; 491 uint64_t c14_pmevcntr[31]; 492 uint64_t c14_pmevcntr_delta[31]; 493 uint64_t c14_pmevtyper[31]; 494 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 495 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 496 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 497 } cp15; 498 499 struct { 500 /* M profile has up to 4 stack pointers: 501 * a Main Stack Pointer and a Process Stack Pointer for each 502 * of the Secure and Non-Secure states. (If the CPU doesn't support 503 * the security extension then it has only two SPs.) 504 * In QEMU we always store the currently active SP in regs[13], 505 * and the non-active SP for the current security state in 506 * v7m.other_sp. The stack pointers for the inactive security state 507 * are stored in other_ss_msp and other_ss_psp. 508 * switch_v7m_security_state() is responsible for rearranging them 509 * when we change security state. 510 */ 511 uint32_t other_sp; 512 uint32_t other_ss_msp; 513 uint32_t other_ss_psp; 514 uint32_t vecbase[M_REG_NUM_BANKS]; 515 uint32_t basepri[M_REG_NUM_BANKS]; 516 uint32_t control[M_REG_NUM_BANKS]; 517 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 518 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 519 uint32_t hfsr; /* HardFault Status */ 520 uint32_t dfsr; /* Debug Fault Status Register */ 521 uint32_t sfsr; /* Secure Fault Status Register */ 522 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 523 uint32_t bfar; /* BusFault Address */ 524 uint32_t sfar; /* Secure Fault Address Register */ 525 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 526 int exception; 527 uint32_t primask[M_REG_NUM_BANKS]; 528 uint32_t faultmask[M_REG_NUM_BANKS]; 529 uint32_t aircr; /* only holds r/w state if security extn implemented */ 530 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 531 uint32_t csselr[M_REG_NUM_BANKS]; 532 uint32_t scr[M_REG_NUM_BANKS]; 533 uint32_t msplim[M_REG_NUM_BANKS]; 534 uint32_t psplim[M_REG_NUM_BANKS]; 535 uint32_t fpcar[M_REG_NUM_BANKS]; 536 uint32_t fpccr[M_REG_NUM_BANKS]; 537 uint32_t fpdscr[M_REG_NUM_BANKS]; 538 uint32_t cpacr[M_REG_NUM_BANKS]; 539 uint32_t nsacr; 540 } v7m; 541 542 /* Information associated with an exception about to be taken: 543 * code which raises an exception must set cs->exception_index and 544 * the relevant parts of this structure; the cpu_do_interrupt function 545 * will then set the guest-visible registers as part of the exception 546 * entry process. 547 */ 548 struct { 549 uint32_t syndrome; /* AArch64 format syndrome register */ 550 uint32_t fsr; /* AArch32 format fault status register info */ 551 uint64_t vaddress; /* virtual addr associated with exception, if any */ 552 uint32_t target_el; /* EL the exception should be targeted for */ 553 /* If we implement EL2 we will also need to store information 554 * about the intermediate physical address for stage 2 faults. 555 */ 556 } exception; 557 558 /* Information associated with an SError */ 559 struct { 560 uint8_t pending; 561 uint8_t has_esr; 562 uint64_t esr; 563 } serror; 564 565 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 566 uint32_t irq_line_state; 567 568 /* Thumb-2 EE state. */ 569 uint32_t teecr; 570 uint32_t teehbr; 571 572 /* VFP coprocessor state. */ 573 struct { 574 ARMVectorReg zregs[32]; 575 576 #ifdef TARGET_AARCH64 577 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 578 #define FFR_PRED_NUM 16 579 ARMPredicateReg pregs[17]; 580 /* Scratch space for aa64 sve predicate temporary. */ 581 ARMPredicateReg preg_tmp; 582 #endif 583 584 /* We store these fpcsr fields separately for convenience. */ 585 uint32_t qc[4] QEMU_ALIGNED(16); 586 int vec_len; 587 int vec_stride; 588 589 uint32_t xregs[16]; 590 591 /* Scratch space for aa32 neon expansion. */ 592 uint32_t scratch[8]; 593 594 /* There are a number of distinct float control structures: 595 * 596 * fp_status: is the "normal" fp status. 597 * fp_status_fp16: used for half-precision calculations 598 * standard_fp_status : the ARM "Standard FPSCR Value" 599 * 600 * Half-precision operations are governed by a separate 601 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 602 * status structure to control this. 603 * 604 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 605 * round-to-nearest and is used by any operations (generally 606 * Neon) which the architecture defines as controlled by the 607 * standard FPSCR value rather than the FPSCR. 608 * 609 * To avoid having to transfer exception bits around, we simply 610 * say that the FPSCR cumulative exception flags are the logical 611 * OR of the flags in the three fp statuses. This relies on the 612 * only thing which needs to read the exception flags being 613 * an explicit FPSCR read. 614 */ 615 float_status fp_status; 616 float_status fp_status_f16; 617 float_status standard_fp_status; 618 619 /* ZCR_EL[1-3] */ 620 uint64_t zcr_el[4]; 621 } vfp; 622 uint64_t exclusive_addr; 623 uint64_t exclusive_val; 624 uint64_t exclusive_high; 625 626 /* iwMMXt coprocessor state. */ 627 struct { 628 uint64_t regs[16]; 629 uint64_t val; 630 631 uint32_t cregs[16]; 632 } iwmmxt; 633 634 #ifdef TARGET_AARCH64 635 struct { 636 ARMPACKey apia; 637 ARMPACKey apib; 638 ARMPACKey apda; 639 ARMPACKey apdb; 640 ARMPACKey apga; 641 } keys; 642 #endif 643 644 #if defined(CONFIG_USER_ONLY) 645 /* For usermode syscall translation. */ 646 int eabi; 647 #endif 648 649 struct CPUBreakpoint *cpu_breakpoint[16]; 650 struct CPUWatchpoint *cpu_watchpoint[16]; 651 652 /* Fields up to this point are cleared by a CPU reset */ 653 struct {} end_reset_fields; 654 655 /* Fields after this point are preserved across CPU reset. */ 656 657 /* Internal CPU feature flags. */ 658 uint64_t features; 659 660 /* PMSAv7 MPU */ 661 struct { 662 uint32_t *drbar; 663 uint32_t *drsr; 664 uint32_t *dracr; 665 uint32_t rnr[M_REG_NUM_BANKS]; 666 } pmsav7; 667 668 /* PMSAv8 MPU */ 669 struct { 670 /* The PMSAv8 implementation also shares some PMSAv7 config 671 * and state: 672 * pmsav7.rnr (region number register) 673 * pmsav7_dregion (number of configured regions) 674 */ 675 uint32_t *rbar[M_REG_NUM_BANKS]; 676 uint32_t *rlar[M_REG_NUM_BANKS]; 677 uint32_t mair0[M_REG_NUM_BANKS]; 678 uint32_t mair1[M_REG_NUM_BANKS]; 679 } pmsav8; 680 681 /* v8M SAU */ 682 struct { 683 uint32_t *rbar; 684 uint32_t *rlar; 685 uint32_t rnr; 686 uint32_t ctrl; 687 } sau; 688 689 void *nvic; 690 const struct arm_boot_info *boot_info; 691 /* Store GICv3CPUState to access from this struct */ 692 void *gicv3state; 693 } CPUARMState; 694 695 /** 696 * ARMELChangeHookFn: 697 * type of a function which can be registered via arm_register_el_change_hook() 698 * to get callbacks when the CPU changes its exception level or mode. 699 */ 700 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 701 typedef struct ARMELChangeHook ARMELChangeHook; 702 struct ARMELChangeHook { 703 ARMELChangeHookFn *hook; 704 void *opaque; 705 QLIST_ENTRY(ARMELChangeHook) node; 706 }; 707 708 /* These values map onto the return values for 709 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 710 typedef enum ARMPSCIState { 711 PSCI_ON = 0, 712 PSCI_OFF = 1, 713 PSCI_ON_PENDING = 2 714 } ARMPSCIState; 715 716 typedef struct ARMISARegisters ARMISARegisters; 717 718 /** 719 * ARMCPU: 720 * @env: #CPUARMState 721 * 722 * An ARM CPU core. 723 */ 724 struct ARMCPU { 725 /*< private >*/ 726 CPUState parent_obj; 727 /*< public >*/ 728 729 CPUNegativeOffsetState neg; 730 CPUARMState env; 731 732 /* Coprocessor information */ 733 GHashTable *cp_regs; 734 /* For marshalling (mostly coprocessor) register state between the 735 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 736 * we use these arrays. 737 */ 738 /* List of register indexes managed via these arrays; (full KVM style 739 * 64 bit indexes, not CPRegInfo 32 bit indexes) 740 */ 741 uint64_t *cpreg_indexes; 742 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 743 uint64_t *cpreg_values; 744 /* Length of the indexes, values, reset_values arrays */ 745 int32_t cpreg_array_len; 746 /* These are used only for migration: incoming data arrives in 747 * these fields and is sanity checked in post_load before copying 748 * to the working data structures above. 749 */ 750 uint64_t *cpreg_vmstate_indexes; 751 uint64_t *cpreg_vmstate_values; 752 int32_t cpreg_vmstate_array_len; 753 754 DynamicGDBXMLInfo dyn_xml; 755 756 /* Timers used by the generic (architected) timer */ 757 QEMUTimer *gt_timer[NUM_GTIMERS]; 758 /* 759 * Timer used by the PMU. Its state is restored after migration by 760 * pmu_op_finish() - it does not need other handling during migration 761 */ 762 QEMUTimer *pmu_timer; 763 /* GPIO outputs for generic timer */ 764 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 765 /* GPIO output for GICv3 maintenance interrupt signal */ 766 qemu_irq gicv3_maintenance_interrupt; 767 /* GPIO output for the PMU interrupt */ 768 qemu_irq pmu_interrupt; 769 770 /* MemoryRegion to use for secure physical accesses */ 771 MemoryRegion *secure_memory; 772 773 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 774 Object *idau; 775 776 /* 'compatible' string for this CPU for Linux device trees */ 777 const char *dtb_compatible; 778 779 /* PSCI version for this CPU 780 * Bits[31:16] = Major Version 781 * Bits[15:0] = Minor Version 782 */ 783 uint32_t psci_version; 784 785 /* Should CPU start in PSCI powered-off state? */ 786 bool start_powered_off; 787 788 /* Current power state, access guarded by BQL */ 789 ARMPSCIState power_state; 790 791 /* CPU has virtualization extension */ 792 bool has_el2; 793 /* CPU has security extension */ 794 bool has_el3; 795 /* CPU has PMU (Performance Monitor Unit) */ 796 bool has_pmu; 797 /* CPU has VFP */ 798 bool has_vfp; 799 /* CPU has Neon */ 800 bool has_neon; 801 /* CPU has M-profile DSP extension */ 802 bool has_dsp; 803 804 /* CPU has memory protection unit */ 805 bool has_mpu; 806 /* PMSAv7 MPU number of supported regions */ 807 uint32_t pmsav7_dregion; 808 /* v8M SAU number of supported regions */ 809 uint32_t sau_sregion; 810 811 /* PSCI conduit used to invoke PSCI methods 812 * 0 - disabled, 1 - smc, 2 - hvc 813 */ 814 uint32_t psci_conduit; 815 816 /* For v8M, initial value of the Secure VTOR */ 817 uint32_t init_svtor; 818 819 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 820 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 821 */ 822 uint32_t kvm_target; 823 824 /* KVM init features for this CPU */ 825 uint32_t kvm_init_features[7]; 826 827 /* Uniprocessor system with MP extensions */ 828 bool mp_is_up; 829 830 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 831 * and the probe failed (so we need to report the error in realize) 832 */ 833 bool host_cpu_probe_failed; 834 835 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 836 * register. 837 */ 838 int32_t core_count; 839 840 /* The instance init functions for implementation-specific subclasses 841 * set these fields to specify the implementation-dependent values of 842 * various constant registers and reset values of non-constant 843 * registers. 844 * Some of these might become QOM properties eventually. 845 * Field names match the official register names as defined in the 846 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 847 * is used for reset values of non-constant registers; no reset_ 848 * prefix means a constant register. 849 * Some of these registers are split out into a substructure that 850 * is shared with the translators to control the ISA. 851 */ 852 struct ARMISARegisters { 853 uint32_t id_isar0; 854 uint32_t id_isar1; 855 uint32_t id_isar2; 856 uint32_t id_isar3; 857 uint32_t id_isar4; 858 uint32_t id_isar5; 859 uint32_t id_isar6; 860 uint32_t mvfr0; 861 uint32_t mvfr1; 862 uint32_t mvfr2; 863 uint64_t id_aa64isar0; 864 uint64_t id_aa64isar1; 865 uint64_t id_aa64pfr0; 866 uint64_t id_aa64pfr1; 867 uint64_t id_aa64mmfr0; 868 uint64_t id_aa64mmfr1; 869 } isar; 870 uint32_t midr; 871 uint32_t revidr; 872 uint32_t reset_fpsid; 873 uint32_t ctr; 874 uint32_t reset_sctlr; 875 uint32_t id_pfr0; 876 uint32_t id_pfr1; 877 uint32_t id_dfr0; 878 uint64_t pmceid0; 879 uint64_t pmceid1; 880 uint32_t id_afr0; 881 uint32_t id_mmfr0; 882 uint32_t id_mmfr1; 883 uint32_t id_mmfr2; 884 uint32_t id_mmfr3; 885 uint32_t id_mmfr4; 886 uint64_t id_aa64dfr0; 887 uint64_t id_aa64dfr1; 888 uint64_t id_aa64afr0; 889 uint64_t id_aa64afr1; 890 uint32_t dbgdidr; 891 uint32_t clidr; 892 uint64_t mp_affinity; /* MP ID without feature bits */ 893 /* The elements of this array are the CCSIDR values for each cache, 894 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 895 */ 896 uint32_t ccsidr[16]; 897 uint64_t reset_cbar; 898 uint32_t reset_auxcr; 899 bool reset_hivecs; 900 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 901 uint32_t dcz_blocksize; 902 uint64_t rvbar; 903 904 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 905 int gic_num_lrs; /* number of list registers */ 906 int gic_vpribits; /* number of virtual priority bits */ 907 int gic_vprebits; /* number of virtual preemption bits */ 908 909 /* Whether the cfgend input is high (i.e. this CPU should reset into 910 * big-endian mode). This setting isn't used directly: instead it modifies 911 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 912 * architecture version. 913 */ 914 bool cfgend; 915 916 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 917 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 918 919 int32_t node_id; /* NUMA node this CPU belongs to */ 920 921 /* Used to synchronize KVM and QEMU in-kernel device levels */ 922 uint8_t device_irq_level; 923 924 /* Used to set the maximum vector length the cpu will support. */ 925 uint32_t sve_max_vq; 926 927 /* 928 * In sve_vq_map each set bit is a supported vector length of 929 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 930 * length in quadwords. 931 * 932 * While processing properties during initialization, corresponding 933 * sve_vq_init bits are set for bits in sve_vq_map that have been 934 * set by properties. 935 */ 936 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 937 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 938 }; 939 940 void arm_cpu_post_init(Object *obj); 941 942 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 943 944 #ifndef CONFIG_USER_ONLY 945 extern const VMStateDescription vmstate_arm_cpu; 946 #endif 947 948 void arm_cpu_do_interrupt(CPUState *cpu); 949 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 950 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 951 952 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 953 MemTxAttrs *attrs); 954 955 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 956 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 957 958 /* Dynamically generates for gdb stub an XML description of the sysregs from 959 * the cp_regs hashtable. Returns the registered sysregs number. 960 */ 961 int arm_gen_dynamic_xml(CPUState *cpu); 962 963 /* Returns the dynamically generated XML for the gdb stub. 964 * Returns a pointer to the XML contents for the specified XML file or NULL 965 * if the XML name doesn't match the predefined one. 966 */ 967 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 968 969 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 970 int cpuid, void *opaque); 971 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 972 int cpuid, void *opaque); 973 974 #ifdef TARGET_AARCH64 975 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 976 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 977 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 978 void aarch64_sve_change_el(CPUARMState *env, int old_el, 979 int new_el, bool el0_a64); 980 void aarch64_add_sve_properties(Object *obj); 981 #else 982 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 983 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 984 int n, bool a) 985 { } 986 static inline void aarch64_add_sve_properties(Object *obj) { } 987 #endif 988 989 #if !defined(CONFIG_TCG) 990 static inline target_ulong do_arm_semihosting(CPUARMState *env) 991 { 992 g_assert_not_reached(); 993 } 994 #else 995 target_ulong do_arm_semihosting(CPUARMState *env); 996 #endif 997 void aarch64_sync_32_to_64(CPUARMState *env); 998 void aarch64_sync_64_to_32(CPUARMState *env); 999 1000 int fp_exception_el(CPUARMState *env, int cur_el); 1001 int sve_exception_el(CPUARMState *env, int cur_el); 1002 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1003 1004 static inline bool is_a64(CPUARMState *env) 1005 { 1006 return env->aarch64; 1007 } 1008 1009 /* you can call this signal handler from your SIGBUS and SIGSEGV 1010 signal handlers to inform the virtual CPU of exceptions. non zero 1011 is returned if the signal was handled by the virtual CPU. */ 1012 int cpu_arm_signal_handler(int host_signum, void *pinfo, 1013 void *puc); 1014 1015 /** 1016 * pmu_op_start/finish 1017 * @env: CPUARMState 1018 * 1019 * Convert all PMU counters between their delta form (the typical mode when 1020 * they are enabled) and the guest-visible values. These two calls must 1021 * surround any action which might affect the counters. 1022 */ 1023 void pmu_op_start(CPUARMState *env); 1024 void pmu_op_finish(CPUARMState *env); 1025 1026 /* 1027 * Called when a PMU counter is due to overflow 1028 */ 1029 void arm_pmu_timer_cb(void *opaque); 1030 1031 /** 1032 * Functions to register as EL change hooks for PMU mode filtering 1033 */ 1034 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1035 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1036 1037 /* 1038 * pmu_init 1039 * @cpu: ARMCPU 1040 * 1041 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1042 * for the current configuration 1043 */ 1044 void pmu_init(ARMCPU *cpu); 1045 1046 /* SCTLR bit meanings. Several bits have been reused in newer 1047 * versions of the architecture; in that case we define constants 1048 * for both old and new bit meanings. Code which tests against those 1049 * bits should probably check or otherwise arrange that the CPU 1050 * is the architectural version it expects. 1051 */ 1052 #define SCTLR_M (1U << 0) 1053 #define SCTLR_A (1U << 1) 1054 #define SCTLR_C (1U << 2) 1055 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1056 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1057 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1058 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1059 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1060 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1061 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1062 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1063 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1064 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1065 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1066 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1067 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1068 #define SCTLR_SED (1U << 8) /* v8 onward */ 1069 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1070 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1071 #define SCTLR_F (1U << 10) /* up to v6 */ 1072 #define SCTLR_SW (1U << 10) /* v7 */ 1073 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1074 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1075 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1076 #define SCTLR_I (1U << 12) 1077 #define SCTLR_V (1U << 13) /* AArch32 only */ 1078 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1079 #define SCTLR_RR (1U << 14) /* up to v7 */ 1080 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1081 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1082 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1083 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1084 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1085 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1086 #define SCTLR_BR (1U << 17) /* PMSA only */ 1087 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1088 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1089 #define SCTLR_WXN (1U << 19) 1090 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1091 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1092 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1093 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1094 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1095 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1096 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1097 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1098 #define SCTLR_VE (1U << 24) /* up to v7 */ 1099 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1100 #define SCTLR_EE (1U << 25) 1101 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1102 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1103 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1104 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1105 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1106 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1107 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1108 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1109 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1110 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1111 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1112 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1113 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1114 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1115 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1116 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1117 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1118 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1119 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1120 1121 #define CPTR_TCPAC (1U << 31) 1122 #define CPTR_TTA (1U << 20) 1123 #define CPTR_TFP (1U << 10) 1124 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1125 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1126 1127 #define MDCR_EPMAD (1U << 21) 1128 #define MDCR_EDAD (1U << 20) 1129 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1130 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1131 #define MDCR_SDD (1U << 16) 1132 #define MDCR_SPD (3U << 14) 1133 #define MDCR_TDRA (1U << 11) 1134 #define MDCR_TDOSA (1U << 10) 1135 #define MDCR_TDA (1U << 9) 1136 #define MDCR_TDE (1U << 8) 1137 #define MDCR_HPME (1U << 7) 1138 #define MDCR_TPM (1U << 6) 1139 #define MDCR_TPMCR (1U << 5) 1140 #define MDCR_HPMN (0x1fU) 1141 1142 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1143 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1144 1145 #define CPSR_M (0x1fU) 1146 #define CPSR_T (1U << 5) 1147 #define CPSR_F (1U << 6) 1148 #define CPSR_I (1U << 7) 1149 #define CPSR_A (1U << 8) 1150 #define CPSR_E (1U << 9) 1151 #define CPSR_IT_2_7 (0xfc00U) 1152 #define CPSR_GE (0xfU << 16) 1153 #define CPSR_IL (1U << 20) 1154 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 1155 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 1156 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 1157 * where it is live state but not accessible to the AArch32 code. 1158 */ 1159 #define CPSR_RESERVED (0x7U << 21) 1160 #define CPSR_J (1U << 24) 1161 #define CPSR_IT_0_1 (3U << 25) 1162 #define CPSR_Q (1U << 27) 1163 #define CPSR_V (1U << 28) 1164 #define CPSR_C (1U << 29) 1165 #define CPSR_Z (1U << 30) 1166 #define CPSR_N (1U << 31) 1167 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1168 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1169 1170 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1171 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1172 | CPSR_NZCV) 1173 /* Bits writable in user mode. */ 1174 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1175 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1176 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1177 /* Mask of bits which may be set by exception return copying them from SPSR */ 1178 #define CPSR_ERET_MASK (~CPSR_RESERVED) 1179 1180 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1181 #define XPSR_EXCP 0x1ffU 1182 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1183 #define XPSR_IT_2_7 CPSR_IT_2_7 1184 #define XPSR_GE CPSR_GE 1185 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1186 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1187 #define XPSR_IT_0_1 CPSR_IT_0_1 1188 #define XPSR_Q CPSR_Q 1189 #define XPSR_V CPSR_V 1190 #define XPSR_C CPSR_C 1191 #define XPSR_Z CPSR_Z 1192 #define XPSR_N CPSR_N 1193 #define XPSR_NZCV CPSR_NZCV 1194 #define XPSR_IT CPSR_IT 1195 1196 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1197 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1198 #define TTBCR_PD0 (1U << 4) 1199 #define TTBCR_PD1 (1U << 5) 1200 #define TTBCR_EPD0 (1U << 7) 1201 #define TTBCR_IRGN0 (3U << 8) 1202 #define TTBCR_ORGN0 (3U << 10) 1203 #define TTBCR_SH0 (3U << 12) 1204 #define TTBCR_T1SZ (3U << 16) 1205 #define TTBCR_A1 (1U << 22) 1206 #define TTBCR_EPD1 (1U << 23) 1207 #define TTBCR_IRGN1 (3U << 24) 1208 #define TTBCR_ORGN1 (3U << 26) 1209 #define TTBCR_SH1 (1U << 28) 1210 #define TTBCR_EAE (1U << 31) 1211 1212 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1213 * Only these are valid when in AArch64 mode; in 1214 * AArch32 mode SPSRs are basically CPSR-format. 1215 */ 1216 #define PSTATE_SP (1U) 1217 #define PSTATE_M (0xFU) 1218 #define PSTATE_nRW (1U << 4) 1219 #define PSTATE_F (1U << 6) 1220 #define PSTATE_I (1U << 7) 1221 #define PSTATE_A (1U << 8) 1222 #define PSTATE_D (1U << 9) 1223 #define PSTATE_BTYPE (3U << 10) 1224 #define PSTATE_IL (1U << 20) 1225 #define PSTATE_SS (1U << 21) 1226 #define PSTATE_V (1U << 28) 1227 #define PSTATE_C (1U << 29) 1228 #define PSTATE_Z (1U << 30) 1229 #define PSTATE_N (1U << 31) 1230 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1231 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1232 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1233 /* Mode values for AArch64 */ 1234 #define PSTATE_MODE_EL3h 13 1235 #define PSTATE_MODE_EL3t 12 1236 #define PSTATE_MODE_EL2h 9 1237 #define PSTATE_MODE_EL2t 8 1238 #define PSTATE_MODE_EL1h 5 1239 #define PSTATE_MODE_EL1t 4 1240 #define PSTATE_MODE_EL0t 0 1241 1242 /* Write a new value to v7m.exception, thus transitioning into or out 1243 * of Handler mode; this may result in a change of active stack pointer. 1244 */ 1245 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1246 1247 /* Map EL and handler into a PSTATE_MODE. */ 1248 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1249 { 1250 return (el << 2) | handler; 1251 } 1252 1253 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1254 * interprocessing, so we don't attempt to sync with the cpsr state used by 1255 * the 32 bit decoder. 1256 */ 1257 static inline uint32_t pstate_read(CPUARMState *env) 1258 { 1259 int ZF; 1260 1261 ZF = (env->ZF == 0); 1262 return (env->NF & 0x80000000) | (ZF << 30) 1263 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1264 | env->pstate | env->daif | (env->btype << 10); 1265 } 1266 1267 static inline void pstate_write(CPUARMState *env, uint32_t val) 1268 { 1269 env->ZF = (~val) & PSTATE_Z; 1270 env->NF = val; 1271 env->CF = (val >> 29) & 1; 1272 env->VF = (val << 3) & 0x80000000; 1273 env->daif = val & PSTATE_DAIF; 1274 env->btype = (val >> 10) & 3; 1275 env->pstate = val & ~CACHED_PSTATE_BITS; 1276 } 1277 1278 /* Return the current CPSR value. */ 1279 uint32_t cpsr_read(CPUARMState *env); 1280 1281 typedef enum CPSRWriteType { 1282 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1283 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1284 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1285 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1286 } CPSRWriteType; 1287 1288 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1289 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1290 CPSRWriteType write_type); 1291 1292 /* Return the current xPSR value. */ 1293 static inline uint32_t xpsr_read(CPUARMState *env) 1294 { 1295 int ZF; 1296 ZF = (env->ZF == 0); 1297 return (env->NF & 0x80000000) | (ZF << 30) 1298 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1299 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1300 | ((env->condexec_bits & 0xfc) << 8) 1301 | (env->GE << 16) 1302 | env->v7m.exception; 1303 } 1304 1305 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1306 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1307 { 1308 if (mask & XPSR_NZCV) { 1309 env->ZF = (~val) & XPSR_Z; 1310 env->NF = val; 1311 env->CF = (val >> 29) & 1; 1312 env->VF = (val << 3) & 0x80000000; 1313 } 1314 if (mask & XPSR_Q) { 1315 env->QF = ((val & XPSR_Q) != 0); 1316 } 1317 if (mask & XPSR_GE) { 1318 env->GE = (val & XPSR_GE) >> 16; 1319 } 1320 if (mask & XPSR_T) { 1321 env->thumb = ((val & XPSR_T) != 0); 1322 } 1323 if (mask & XPSR_IT_0_1) { 1324 env->condexec_bits &= ~3; 1325 env->condexec_bits |= (val >> 25) & 3; 1326 } 1327 if (mask & XPSR_IT_2_7) { 1328 env->condexec_bits &= 3; 1329 env->condexec_bits |= (val >> 8) & 0xfc; 1330 } 1331 if (mask & XPSR_EXCP) { 1332 /* Note that this only happens on exception exit */ 1333 write_v7m_exception(env, val & XPSR_EXCP); 1334 } 1335 } 1336 1337 #define HCR_VM (1ULL << 0) 1338 #define HCR_SWIO (1ULL << 1) 1339 #define HCR_PTW (1ULL << 2) 1340 #define HCR_FMO (1ULL << 3) 1341 #define HCR_IMO (1ULL << 4) 1342 #define HCR_AMO (1ULL << 5) 1343 #define HCR_VF (1ULL << 6) 1344 #define HCR_VI (1ULL << 7) 1345 #define HCR_VSE (1ULL << 8) 1346 #define HCR_FB (1ULL << 9) 1347 #define HCR_BSU_MASK (3ULL << 10) 1348 #define HCR_DC (1ULL << 12) 1349 #define HCR_TWI (1ULL << 13) 1350 #define HCR_TWE (1ULL << 14) 1351 #define HCR_TID0 (1ULL << 15) 1352 #define HCR_TID1 (1ULL << 16) 1353 #define HCR_TID2 (1ULL << 17) 1354 #define HCR_TID3 (1ULL << 18) 1355 #define HCR_TSC (1ULL << 19) 1356 #define HCR_TIDCP (1ULL << 20) 1357 #define HCR_TACR (1ULL << 21) 1358 #define HCR_TSW (1ULL << 22) 1359 #define HCR_TPCP (1ULL << 23) 1360 #define HCR_TPU (1ULL << 24) 1361 #define HCR_TTLB (1ULL << 25) 1362 #define HCR_TVM (1ULL << 26) 1363 #define HCR_TGE (1ULL << 27) 1364 #define HCR_TDZ (1ULL << 28) 1365 #define HCR_HCD (1ULL << 29) 1366 #define HCR_TRVM (1ULL << 30) 1367 #define HCR_RW (1ULL << 31) 1368 #define HCR_CD (1ULL << 32) 1369 #define HCR_ID (1ULL << 33) 1370 #define HCR_E2H (1ULL << 34) 1371 #define HCR_TLOR (1ULL << 35) 1372 #define HCR_TERR (1ULL << 36) 1373 #define HCR_TEA (1ULL << 37) 1374 #define HCR_MIOCNCE (1ULL << 38) 1375 #define HCR_APK (1ULL << 40) 1376 #define HCR_API (1ULL << 41) 1377 #define HCR_NV (1ULL << 42) 1378 #define HCR_NV1 (1ULL << 43) 1379 #define HCR_AT (1ULL << 44) 1380 #define HCR_NV2 (1ULL << 45) 1381 #define HCR_FWB (1ULL << 46) 1382 #define HCR_FIEN (1ULL << 47) 1383 #define HCR_TID4 (1ULL << 49) 1384 #define HCR_TICAB (1ULL << 50) 1385 #define HCR_TOCU (1ULL << 52) 1386 #define HCR_TTLBIS (1ULL << 54) 1387 #define HCR_TTLBOS (1ULL << 55) 1388 #define HCR_ATA (1ULL << 56) 1389 #define HCR_DCT (1ULL << 57) 1390 1391 /* 1392 * When we actually implement ARMv8.1-VHE we should add HCR_E2H to 1393 * HCR_MASK and then clear it again if the feature bit is not set in 1394 * hcr_write(). 1395 */ 1396 #define HCR_MASK ((1ULL << 34) - 1) 1397 1398 #define SCR_NS (1U << 0) 1399 #define SCR_IRQ (1U << 1) 1400 #define SCR_FIQ (1U << 2) 1401 #define SCR_EA (1U << 3) 1402 #define SCR_FW (1U << 4) 1403 #define SCR_AW (1U << 5) 1404 #define SCR_NET (1U << 6) 1405 #define SCR_SMD (1U << 7) 1406 #define SCR_HCE (1U << 8) 1407 #define SCR_SIF (1U << 9) 1408 #define SCR_RW (1U << 10) 1409 #define SCR_ST (1U << 11) 1410 #define SCR_TWI (1U << 12) 1411 #define SCR_TWE (1U << 13) 1412 #define SCR_TLOR (1U << 14) 1413 #define SCR_TERR (1U << 15) 1414 #define SCR_APK (1U << 16) 1415 #define SCR_API (1U << 17) 1416 #define SCR_EEL2 (1U << 18) 1417 #define SCR_EASE (1U << 19) 1418 #define SCR_NMEA (1U << 20) 1419 #define SCR_FIEN (1U << 21) 1420 #define SCR_ENSCXT (1U << 25) 1421 #define SCR_ATA (1U << 26) 1422 1423 /* Return the current FPSCR value. */ 1424 uint32_t vfp_get_fpscr(CPUARMState *env); 1425 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1426 1427 /* FPCR, Floating Point Control Register 1428 * FPSR, Floating Poiht Status Register 1429 * 1430 * For A64 the FPSCR is split into two logically distinct registers, 1431 * FPCR and FPSR. However since they still use non-overlapping bits 1432 * we store the underlying state in fpscr and just mask on read/write. 1433 */ 1434 #define FPSR_MASK 0xf800009f 1435 #define FPCR_MASK 0x07ff9f00 1436 1437 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1438 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1439 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1440 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1441 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1442 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1443 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1444 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1445 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1446 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1447 1448 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1449 { 1450 return vfp_get_fpscr(env) & FPSR_MASK; 1451 } 1452 1453 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1454 { 1455 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1456 vfp_set_fpscr(env, new_fpscr); 1457 } 1458 1459 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1460 { 1461 return vfp_get_fpscr(env) & FPCR_MASK; 1462 } 1463 1464 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1465 { 1466 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1467 vfp_set_fpscr(env, new_fpscr); 1468 } 1469 1470 enum arm_cpu_mode { 1471 ARM_CPU_MODE_USR = 0x10, 1472 ARM_CPU_MODE_FIQ = 0x11, 1473 ARM_CPU_MODE_IRQ = 0x12, 1474 ARM_CPU_MODE_SVC = 0x13, 1475 ARM_CPU_MODE_MON = 0x16, 1476 ARM_CPU_MODE_ABT = 0x17, 1477 ARM_CPU_MODE_HYP = 0x1a, 1478 ARM_CPU_MODE_UND = 0x1b, 1479 ARM_CPU_MODE_SYS = 0x1f 1480 }; 1481 1482 /* VFP system registers. */ 1483 #define ARM_VFP_FPSID 0 1484 #define ARM_VFP_FPSCR 1 1485 #define ARM_VFP_MVFR2 5 1486 #define ARM_VFP_MVFR1 6 1487 #define ARM_VFP_MVFR0 7 1488 #define ARM_VFP_FPEXC 8 1489 #define ARM_VFP_FPINST 9 1490 #define ARM_VFP_FPINST2 10 1491 1492 /* iwMMXt coprocessor control registers. */ 1493 #define ARM_IWMMXT_wCID 0 1494 #define ARM_IWMMXT_wCon 1 1495 #define ARM_IWMMXT_wCSSF 2 1496 #define ARM_IWMMXT_wCASF 3 1497 #define ARM_IWMMXT_wCGR0 8 1498 #define ARM_IWMMXT_wCGR1 9 1499 #define ARM_IWMMXT_wCGR2 10 1500 #define ARM_IWMMXT_wCGR3 11 1501 1502 /* V7M CCR bits */ 1503 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1504 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1505 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1506 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1507 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1508 FIELD(V7M_CCR, STKALIGN, 9, 1) 1509 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1510 FIELD(V7M_CCR, DC, 16, 1) 1511 FIELD(V7M_CCR, IC, 17, 1) 1512 FIELD(V7M_CCR, BP, 18, 1) 1513 1514 /* V7M SCR bits */ 1515 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1516 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1517 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1518 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1519 1520 /* V7M AIRCR bits */ 1521 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1522 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1523 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1524 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1525 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1526 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1527 FIELD(V7M_AIRCR, PRIS, 14, 1) 1528 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1529 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1530 1531 /* V7M CFSR bits for MMFSR */ 1532 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1533 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1534 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1535 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1536 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1537 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1538 1539 /* V7M CFSR bits for BFSR */ 1540 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1541 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1542 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1543 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1544 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1545 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1546 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1547 1548 /* V7M CFSR bits for UFSR */ 1549 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1550 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1551 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1552 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1553 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1554 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1555 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1556 1557 /* V7M CFSR bit masks covering all of the subregister bits */ 1558 FIELD(V7M_CFSR, MMFSR, 0, 8) 1559 FIELD(V7M_CFSR, BFSR, 8, 8) 1560 FIELD(V7M_CFSR, UFSR, 16, 16) 1561 1562 /* V7M HFSR bits */ 1563 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1564 FIELD(V7M_HFSR, FORCED, 30, 1) 1565 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1566 1567 /* V7M DFSR bits */ 1568 FIELD(V7M_DFSR, HALTED, 0, 1) 1569 FIELD(V7M_DFSR, BKPT, 1, 1) 1570 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1571 FIELD(V7M_DFSR, VCATCH, 3, 1) 1572 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1573 1574 /* V7M SFSR bits */ 1575 FIELD(V7M_SFSR, INVEP, 0, 1) 1576 FIELD(V7M_SFSR, INVIS, 1, 1) 1577 FIELD(V7M_SFSR, INVER, 2, 1) 1578 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1579 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1580 FIELD(V7M_SFSR, LSPERR, 5, 1) 1581 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1582 FIELD(V7M_SFSR, LSERR, 7, 1) 1583 1584 /* v7M MPU_CTRL bits */ 1585 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1586 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1587 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1588 1589 /* v7M CLIDR bits */ 1590 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1591 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1592 FIELD(V7M_CLIDR, LOC, 24, 3) 1593 FIELD(V7M_CLIDR, LOUU, 27, 3) 1594 FIELD(V7M_CLIDR, ICB, 30, 2) 1595 1596 FIELD(V7M_CSSELR, IND, 0, 1) 1597 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1598 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1599 * define a mask for this and check that it doesn't permit running off 1600 * the end of the array. 1601 */ 1602 FIELD(V7M_CSSELR, INDEX, 0, 4) 1603 1604 /* v7M FPCCR bits */ 1605 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1606 FIELD(V7M_FPCCR, USER, 1, 1) 1607 FIELD(V7M_FPCCR, S, 2, 1) 1608 FIELD(V7M_FPCCR, THREAD, 3, 1) 1609 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1610 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1611 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1612 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1613 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1614 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1615 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1616 FIELD(V7M_FPCCR, RES0, 11, 15) 1617 FIELD(V7M_FPCCR, TS, 26, 1) 1618 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1619 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1620 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1621 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1622 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1623 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1624 #define R_V7M_FPCCR_BANKED_MASK \ 1625 (R_V7M_FPCCR_LSPACT_MASK | \ 1626 R_V7M_FPCCR_USER_MASK | \ 1627 R_V7M_FPCCR_THREAD_MASK | \ 1628 R_V7M_FPCCR_MMRDY_MASK | \ 1629 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1630 R_V7M_FPCCR_UFRDY_MASK | \ 1631 R_V7M_FPCCR_ASPEN_MASK) 1632 1633 /* 1634 * System register ID fields. 1635 */ 1636 FIELD(MIDR_EL1, REVISION, 0, 4) 1637 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1638 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1639 FIELD(MIDR_EL1, VARIANT, 20, 4) 1640 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1641 1642 FIELD(ID_ISAR0, SWAP, 0, 4) 1643 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1644 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1645 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1646 FIELD(ID_ISAR0, COPROC, 16, 4) 1647 FIELD(ID_ISAR0, DEBUG, 20, 4) 1648 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1649 1650 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1651 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1652 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1653 FIELD(ID_ISAR1, EXTEND, 12, 4) 1654 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1655 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1656 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1657 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1658 1659 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1660 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1661 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1662 FIELD(ID_ISAR2, MULT, 12, 4) 1663 FIELD(ID_ISAR2, MULTS, 16, 4) 1664 FIELD(ID_ISAR2, MULTU, 20, 4) 1665 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1666 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1667 1668 FIELD(ID_ISAR3, SATURATE, 0, 4) 1669 FIELD(ID_ISAR3, SIMD, 4, 4) 1670 FIELD(ID_ISAR3, SVC, 8, 4) 1671 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1672 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1673 FIELD(ID_ISAR3, T32COPY, 20, 4) 1674 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1675 FIELD(ID_ISAR3, T32EE, 28, 4) 1676 1677 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1678 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1679 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1680 FIELD(ID_ISAR4, SMC, 12, 4) 1681 FIELD(ID_ISAR4, BARRIER, 16, 4) 1682 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1683 FIELD(ID_ISAR4, PSR_M, 24, 4) 1684 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1685 1686 FIELD(ID_ISAR5, SEVL, 0, 4) 1687 FIELD(ID_ISAR5, AES, 4, 4) 1688 FIELD(ID_ISAR5, SHA1, 8, 4) 1689 FIELD(ID_ISAR5, SHA2, 12, 4) 1690 FIELD(ID_ISAR5, CRC32, 16, 4) 1691 FIELD(ID_ISAR5, RDM, 24, 4) 1692 FIELD(ID_ISAR5, VCMA, 28, 4) 1693 1694 FIELD(ID_ISAR6, JSCVT, 0, 4) 1695 FIELD(ID_ISAR6, DP, 4, 4) 1696 FIELD(ID_ISAR6, FHM, 8, 4) 1697 FIELD(ID_ISAR6, SB, 12, 4) 1698 FIELD(ID_ISAR6, SPECRES, 16, 4) 1699 1700 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1701 FIELD(ID_MMFR4, AC2, 4, 4) 1702 FIELD(ID_MMFR4, XNX, 8, 4) 1703 FIELD(ID_MMFR4, CNP, 12, 4) 1704 FIELD(ID_MMFR4, HPDS, 16, 4) 1705 FIELD(ID_MMFR4, LSM, 20, 4) 1706 FIELD(ID_MMFR4, CCIDX, 24, 4) 1707 FIELD(ID_MMFR4, EVT, 28, 4) 1708 1709 FIELD(ID_AA64ISAR0, AES, 4, 4) 1710 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1711 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1712 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1713 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1714 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1715 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1716 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1717 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1718 FIELD(ID_AA64ISAR0, DP, 44, 4) 1719 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1720 FIELD(ID_AA64ISAR0, TS, 52, 4) 1721 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1722 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1723 1724 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1725 FIELD(ID_AA64ISAR1, APA, 4, 4) 1726 FIELD(ID_AA64ISAR1, API, 8, 4) 1727 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1728 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1729 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1730 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1731 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1732 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1733 FIELD(ID_AA64ISAR1, SB, 36, 4) 1734 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1735 1736 FIELD(ID_AA64PFR0, EL0, 0, 4) 1737 FIELD(ID_AA64PFR0, EL1, 4, 4) 1738 FIELD(ID_AA64PFR0, EL2, 8, 4) 1739 FIELD(ID_AA64PFR0, EL3, 12, 4) 1740 FIELD(ID_AA64PFR0, FP, 16, 4) 1741 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1742 FIELD(ID_AA64PFR0, GIC, 24, 4) 1743 FIELD(ID_AA64PFR0, RAS, 28, 4) 1744 FIELD(ID_AA64PFR0, SVE, 32, 4) 1745 1746 FIELD(ID_AA64PFR1, BT, 0, 4) 1747 FIELD(ID_AA64PFR1, SBSS, 4, 4) 1748 FIELD(ID_AA64PFR1, MTE, 8, 4) 1749 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1750 1751 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1752 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1753 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1754 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1755 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1756 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1757 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1758 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1759 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1760 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1761 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1762 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1763 1764 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1765 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1766 FIELD(ID_AA64MMFR1, VH, 8, 4) 1767 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1768 FIELD(ID_AA64MMFR1, LO, 16, 4) 1769 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1770 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1771 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1772 1773 FIELD(ID_DFR0, COPDBG, 0, 4) 1774 FIELD(ID_DFR0, COPSDBG, 4, 4) 1775 FIELD(ID_DFR0, MMAPDBG, 8, 4) 1776 FIELD(ID_DFR0, COPTRC, 12, 4) 1777 FIELD(ID_DFR0, MMAPTRC, 16, 4) 1778 FIELD(ID_DFR0, MPROFDBG, 20, 4) 1779 FIELD(ID_DFR0, PERFMON, 24, 4) 1780 FIELD(ID_DFR0, TRACEFILT, 28, 4) 1781 1782 FIELD(MVFR0, SIMDREG, 0, 4) 1783 FIELD(MVFR0, FPSP, 4, 4) 1784 FIELD(MVFR0, FPDP, 8, 4) 1785 FIELD(MVFR0, FPTRAP, 12, 4) 1786 FIELD(MVFR0, FPDIVIDE, 16, 4) 1787 FIELD(MVFR0, FPSQRT, 20, 4) 1788 FIELD(MVFR0, FPSHVEC, 24, 4) 1789 FIELD(MVFR0, FPROUND, 28, 4) 1790 1791 FIELD(MVFR1, FPFTZ, 0, 4) 1792 FIELD(MVFR1, FPDNAN, 4, 4) 1793 FIELD(MVFR1, SIMDLS, 8, 4) 1794 FIELD(MVFR1, SIMDINT, 12, 4) 1795 FIELD(MVFR1, SIMDSP, 16, 4) 1796 FIELD(MVFR1, SIMDHP, 20, 4) 1797 FIELD(MVFR1, FPHP, 24, 4) 1798 FIELD(MVFR1, SIMDFMAC, 28, 4) 1799 1800 FIELD(MVFR2, SIMDMISC, 0, 4) 1801 FIELD(MVFR2, FPMISC, 4, 4) 1802 1803 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1804 1805 /* If adding a feature bit which corresponds to a Linux ELF 1806 * HWCAP bit, remember to update the feature-bit-to-hwcap 1807 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1808 */ 1809 enum arm_features { 1810 ARM_FEATURE_VFP, 1811 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1812 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1813 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1814 ARM_FEATURE_V6, 1815 ARM_FEATURE_V6K, 1816 ARM_FEATURE_V7, 1817 ARM_FEATURE_THUMB2, 1818 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1819 ARM_FEATURE_VFP3, 1820 ARM_FEATURE_NEON, 1821 ARM_FEATURE_M, /* Microcontroller profile. */ 1822 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1823 ARM_FEATURE_THUMB2EE, 1824 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1825 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1826 ARM_FEATURE_V4T, 1827 ARM_FEATURE_V5, 1828 ARM_FEATURE_STRONGARM, 1829 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1830 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1831 ARM_FEATURE_GENERIC_TIMER, 1832 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1833 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1834 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1835 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1836 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1837 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1838 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1839 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1840 ARM_FEATURE_V8, 1841 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1842 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1843 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1844 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1845 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1846 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1847 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1848 ARM_FEATURE_PMU, /* has PMU support */ 1849 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1850 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1851 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1852 }; 1853 1854 static inline int arm_feature(CPUARMState *env, int feature) 1855 { 1856 return (env->features & (1ULL << feature)) != 0; 1857 } 1858 1859 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 1860 1861 #if !defined(CONFIG_USER_ONLY) 1862 /* Return true if exception levels below EL3 are in secure state, 1863 * or would be following an exception return to that level. 1864 * Unlike arm_is_secure() (which is always a question about the 1865 * _current_ state of the CPU) this doesn't care about the current 1866 * EL or mode. 1867 */ 1868 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1869 { 1870 if (arm_feature(env, ARM_FEATURE_EL3)) { 1871 return !(env->cp15.scr_el3 & SCR_NS); 1872 } else { 1873 /* If EL3 is not supported then the secure state is implementation 1874 * defined, in which case QEMU defaults to non-secure. 1875 */ 1876 return false; 1877 } 1878 } 1879 1880 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1881 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1882 { 1883 if (arm_feature(env, ARM_FEATURE_EL3)) { 1884 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1885 /* CPU currently in AArch64 state and EL3 */ 1886 return true; 1887 } else if (!is_a64(env) && 1888 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1889 /* CPU currently in AArch32 state and monitor mode */ 1890 return true; 1891 } 1892 } 1893 return false; 1894 } 1895 1896 /* Return true if the processor is in secure state */ 1897 static inline bool arm_is_secure(CPUARMState *env) 1898 { 1899 if (arm_is_el3_or_mon(env)) { 1900 return true; 1901 } 1902 return arm_is_secure_below_el3(env); 1903 } 1904 1905 #else 1906 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1907 { 1908 return false; 1909 } 1910 1911 static inline bool arm_is_secure(CPUARMState *env) 1912 { 1913 return false; 1914 } 1915 #endif 1916 1917 /** 1918 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 1919 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 1920 * "for all purposes other than a direct read or write access of HCR_EL2." 1921 * Not included here is HCR_RW. 1922 */ 1923 uint64_t arm_hcr_el2_eff(CPUARMState *env); 1924 1925 /* Return true if the specified exception level is running in AArch64 state. */ 1926 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1927 { 1928 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1929 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1930 */ 1931 assert(el >= 1 && el <= 3); 1932 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1933 1934 /* The highest exception level is always at the maximum supported 1935 * register width, and then lower levels have a register width controlled 1936 * by bits in the SCR or HCR registers. 1937 */ 1938 if (el == 3) { 1939 return aa64; 1940 } 1941 1942 if (arm_feature(env, ARM_FEATURE_EL3)) { 1943 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1944 } 1945 1946 if (el == 2) { 1947 return aa64; 1948 } 1949 1950 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1951 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1952 } 1953 1954 return aa64; 1955 } 1956 1957 /* Function for determing whether guest cp register reads and writes should 1958 * access the secure or non-secure bank of a cp register. When EL3 is 1959 * operating in AArch32 state, the NS-bit determines whether the secure 1960 * instance of a cp register should be used. When EL3 is AArch64 (or if 1961 * it doesn't exist at all) then there is no register banking, and all 1962 * accesses are to the non-secure version. 1963 */ 1964 static inline bool access_secure_reg(CPUARMState *env) 1965 { 1966 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1967 !arm_el_is_aa64(env, 3) && 1968 !(env->cp15.scr_el3 & SCR_NS)); 1969 1970 return ret; 1971 } 1972 1973 /* Macros for accessing a specified CP register bank */ 1974 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1975 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1976 1977 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1978 do { \ 1979 if (_secure) { \ 1980 (_env)->cp15._regname##_s = (_val); \ 1981 } else { \ 1982 (_env)->cp15._regname##_ns = (_val); \ 1983 } \ 1984 } while (0) 1985 1986 /* Macros for automatically accessing a specific CP register bank depending on 1987 * the current secure state of the system. These macros are not intended for 1988 * supporting instruction translation reads/writes as these are dependent 1989 * solely on the SCR.NS bit and not the mode. 1990 */ 1991 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1992 A32_BANKED_REG_GET((_env), _regname, \ 1993 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1994 1995 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1996 A32_BANKED_REG_SET((_env), _regname, \ 1997 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1998 (_val)) 1999 2000 void arm_cpu_list(void); 2001 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2002 uint32_t cur_el, bool secure); 2003 2004 /* Interface between CPU and Interrupt controller. */ 2005 #ifndef CONFIG_USER_ONLY 2006 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2007 #else 2008 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2009 { 2010 return true; 2011 } 2012 #endif 2013 /** 2014 * armv7m_nvic_set_pending: mark the specified exception as pending 2015 * @opaque: the NVIC 2016 * @irq: the exception number to mark pending 2017 * @secure: false for non-banked exceptions or for the nonsecure 2018 * version of a banked exception, true for the secure version of a banked 2019 * exception. 2020 * 2021 * Marks the specified exception as pending. Note that we will assert() 2022 * if @secure is true and @irq does not specify one of the fixed set 2023 * of architecturally banked exceptions. 2024 */ 2025 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2026 /** 2027 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2028 * @opaque: the NVIC 2029 * @irq: the exception number to mark pending 2030 * @secure: false for non-banked exceptions or for the nonsecure 2031 * version of a banked exception, true for the secure version of a banked 2032 * exception. 2033 * 2034 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2035 * exceptions (exceptions generated in the course of trying to take 2036 * a different exception). 2037 */ 2038 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2039 /** 2040 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2041 * @opaque: the NVIC 2042 * @irq: the exception number to mark pending 2043 * @secure: false for non-banked exceptions or for the nonsecure 2044 * version of a banked exception, true for the secure version of a banked 2045 * exception. 2046 * 2047 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2048 * generated in the course of lazy stacking of FP registers. 2049 */ 2050 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2051 /** 2052 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2053 * exception, and whether it targets Secure state 2054 * @opaque: the NVIC 2055 * @pirq: set to pending exception number 2056 * @ptargets_secure: set to whether pending exception targets Secure 2057 * 2058 * This function writes the number of the highest priority pending 2059 * exception (the one which would be made active by 2060 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2061 * to true if the current highest priority pending exception should 2062 * be taken to Secure state, false for NS. 2063 */ 2064 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2065 bool *ptargets_secure); 2066 /** 2067 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2068 * @opaque: the NVIC 2069 * 2070 * Move the current highest priority pending exception from the pending 2071 * state to the active state, and update v7m.exception to indicate that 2072 * it is the exception currently being handled. 2073 */ 2074 void armv7m_nvic_acknowledge_irq(void *opaque); 2075 /** 2076 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2077 * @opaque: the NVIC 2078 * @irq: the exception number to complete 2079 * @secure: true if this exception was secure 2080 * 2081 * Returns: -1 if the irq was not active 2082 * 1 if completing this irq brought us back to base (no active irqs) 2083 * 0 if there is still an irq active after this one was completed 2084 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2085 */ 2086 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2087 /** 2088 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2089 * @opaque: the NVIC 2090 * @irq: the exception number to mark pending 2091 * @secure: false for non-banked exceptions or for the nonsecure 2092 * version of a banked exception, true for the secure version of a banked 2093 * exception. 2094 * 2095 * Return whether an exception is "ready", i.e. whether the exception is 2096 * enabled and is configured at a priority which would allow it to 2097 * interrupt the current execution priority. This controls whether the 2098 * RDY bit for it in the FPCCR is set. 2099 */ 2100 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2101 /** 2102 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2103 * @opaque: the NVIC 2104 * 2105 * Returns: the raw execution priority as defined by the v8M architecture. 2106 * This is the execution priority minus the effects of AIRCR.PRIS, 2107 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2108 * (v8M ARM ARM I_PKLD.) 2109 */ 2110 int armv7m_nvic_raw_execution_priority(void *opaque); 2111 /** 2112 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2113 * priority is negative for the specified security state. 2114 * @opaque: the NVIC 2115 * @secure: the security state to test 2116 * This corresponds to the pseudocode IsReqExecPriNeg(). 2117 */ 2118 #ifndef CONFIG_USER_ONLY 2119 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2120 #else 2121 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2122 { 2123 return false; 2124 } 2125 #endif 2126 2127 /* Interface for defining coprocessor registers. 2128 * Registers are defined in tables of arm_cp_reginfo structs 2129 * which are passed to define_arm_cp_regs(). 2130 */ 2131 2132 /* When looking up a coprocessor register we look for it 2133 * via an integer which encodes all of: 2134 * coprocessor number 2135 * Crn, Crm, opc1, opc2 fields 2136 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2137 * or via MRRC/MCRR?) 2138 * non-secure/secure bank (AArch32 only) 2139 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2140 * (In this case crn and opc2 should be zero.) 2141 * For AArch64, there is no 32/64 bit size distinction; 2142 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2143 * and 4 bit CRn and CRm. The encoding patterns are chosen 2144 * to be easy to convert to and from the KVM encodings, and also 2145 * so that the hashtable can contain both AArch32 and AArch64 2146 * registers (to allow for interprocessing where we might run 2147 * 32 bit code on a 64 bit core). 2148 */ 2149 /* This bit is private to our hashtable cpreg; in KVM register 2150 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2151 * in the upper bits of the 64 bit ID. 2152 */ 2153 #define CP_REG_AA64_SHIFT 28 2154 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2155 2156 /* To enable banking of coprocessor registers depending on ns-bit we 2157 * add a bit to distinguish between secure and non-secure cpregs in the 2158 * hashtable. 2159 */ 2160 #define CP_REG_NS_SHIFT 29 2161 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2162 2163 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2164 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2165 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2166 2167 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2168 (CP_REG_AA64_MASK | \ 2169 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2170 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2171 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2172 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2173 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2174 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2175 2176 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2177 * version used as a key for the coprocessor register hashtable 2178 */ 2179 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2180 { 2181 uint32_t cpregid = kvmid; 2182 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2183 cpregid |= CP_REG_AA64_MASK; 2184 } else { 2185 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2186 cpregid |= (1 << 15); 2187 } 2188 2189 /* KVM is always non-secure so add the NS flag on AArch32 register 2190 * entries. 2191 */ 2192 cpregid |= 1 << CP_REG_NS_SHIFT; 2193 } 2194 return cpregid; 2195 } 2196 2197 /* Convert a truncated 32 bit hashtable key into the full 2198 * 64 bit KVM register ID. 2199 */ 2200 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2201 { 2202 uint64_t kvmid; 2203 2204 if (cpregid & CP_REG_AA64_MASK) { 2205 kvmid = cpregid & ~CP_REG_AA64_MASK; 2206 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2207 } else { 2208 kvmid = cpregid & ~(1 << 15); 2209 if (cpregid & (1 << 15)) { 2210 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2211 } else { 2212 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2213 } 2214 } 2215 return kvmid; 2216 } 2217 2218 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2219 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2220 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2221 * TCG can assume the value to be constant (ie load at translate time) 2222 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2223 * indicates that the TB should not be ended after a write to this register 2224 * (the default is that the TB ends after cp writes). OVERRIDE permits 2225 * a register definition to override a previous definition for the 2226 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2227 * old must have the OVERRIDE bit set. 2228 * ALIAS indicates that this register is an alias view of some underlying 2229 * state which is also visible via another register, and that the other 2230 * register is handling migration and reset; registers marked ALIAS will not be 2231 * migrated but may have their state set by syncing of register state from KVM. 2232 * NO_RAW indicates that this register has no underlying state and does not 2233 * support raw access for state saving/loading; it will not be used for either 2234 * migration or KVM state synchronization. (Typically this is for "registers" 2235 * which are actually used as instructions for cache maintenance and so on.) 2236 * IO indicates that this register does I/O and therefore its accesses 2237 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2238 * registers which implement clocks or timers require this. 2239 * RAISES_EXC is for when the read or write hook might raise an exception; 2240 * the generated code will synchronize the CPU state before calling the hook 2241 * so that it is safe for the hook to call raise_exception(). 2242 */ 2243 #define ARM_CP_SPECIAL 0x0001 2244 #define ARM_CP_CONST 0x0002 2245 #define ARM_CP_64BIT 0x0004 2246 #define ARM_CP_SUPPRESS_TB_END 0x0008 2247 #define ARM_CP_OVERRIDE 0x0010 2248 #define ARM_CP_ALIAS 0x0020 2249 #define ARM_CP_IO 0x0040 2250 #define ARM_CP_NO_RAW 0x0080 2251 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2252 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2253 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2254 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2255 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2256 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2257 #define ARM_CP_FPU 0x1000 2258 #define ARM_CP_SVE 0x2000 2259 #define ARM_CP_NO_GDB 0x4000 2260 #define ARM_CP_RAISES_EXC 0x8000 2261 /* Used only as a terminator for ARMCPRegInfo lists */ 2262 #define ARM_CP_SENTINEL 0xffff 2263 /* Mask of only the flag bits in a type field */ 2264 #define ARM_CP_FLAG_MASK 0xf0ff 2265 2266 /* Valid values for ARMCPRegInfo state field, indicating which of 2267 * the AArch32 and AArch64 execution states this register is visible in. 2268 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2269 * If the reginfo is declared to be visible in both states then a second 2270 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2271 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2272 * Note that we rely on the values of these enums as we iterate through 2273 * the various states in some places. 2274 */ 2275 enum { 2276 ARM_CP_STATE_AA32 = 0, 2277 ARM_CP_STATE_AA64 = 1, 2278 ARM_CP_STATE_BOTH = 2, 2279 }; 2280 2281 /* ARM CP register secure state flags. These flags identify security state 2282 * attributes for a given CP register entry. 2283 * The existence of both or neither secure and non-secure flags indicates that 2284 * the register has both a secure and non-secure hash entry. A single one of 2285 * these flags causes the register to only be hashed for the specified 2286 * security state. 2287 * Although definitions may have any combination of the S/NS bits, each 2288 * registered entry will only have one to identify whether the entry is secure 2289 * or non-secure. 2290 */ 2291 enum { 2292 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2293 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2294 }; 2295 2296 /* Return true if cptype is a valid type field. This is used to try to 2297 * catch errors where the sentinel has been accidentally left off the end 2298 * of a list of registers. 2299 */ 2300 static inline bool cptype_valid(int cptype) 2301 { 2302 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2303 || ((cptype & ARM_CP_SPECIAL) && 2304 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2305 } 2306 2307 /* Access rights: 2308 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2309 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2310 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2311 * (ie any of the privileged modes in Secure state, or Monitor mode). 2312 * If a register is accessible in one privilege level it's always accessible 2313 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2314 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2315 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2316 * terminology a little and call this PL3. 2317 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2318 * with the ELx exception levels. 2319 * 2320 * If access permissions for a register are more complex than can be 2321 * described with these bits, then use a laxer set of restrictions, and 2322 * do the more restrictive/complex check inside a helper function. 2323 */ 2324 #define PL3_R 0x80 2325 #define PL3_W 0x40 2326 #define PL2_R (0x20 | PL3_R) 2327 #define PL2_W (0x10 | PL3_W) 2328 #define PL1_R (0x08 | PL2_R) 2329 #define PL1_W (0x04 | PL2_W) 2330 #define PL0_R (0x02 | PL1_R) 2331 #define PL0_W (0x01 | PL1_W) 2332 2333 /* 2334 * For user-mode some registers are accessible to EL0 via a kernel 2335 * trap-and-emulate ABI. In this case we define the read permissions 2336 * as actually being PL0_R. However some bits of any given register 2337 * may still be masked. 2338 */ 2339 #ifdef CONFIG_USER_ONLY 2340 #define PL0U_R PL0_R 2341 #else 2342 #define PL0U_R PL1_R 2343 #endif 2344 2345 #define PL3_RW (PL3_R | PL3_W) 2346 #define PL2_RW (PL2_R | PL2_W) 2347 #define PL1_RW (PL1_R | PL1_W) 2348 #define PL0_RW (PL0_R | PL0_W) 2349 2350 /* Return the highest implemented Exception Level */ 2351 static inline int arm_highest_el(CPUARMState *env) 2352 { 2353 if (arm_feature(env, ARM_FEATURE_EL3)) { 2354 return 3; 2355 } 2356 if (arm_feature(env, ARM_FEATURE_EL2)) { 2357 return 2; 2358 } 2359 return 1; 2360 } 2361 2362 /* Return true if a v7M CPU is in Handler mode */ 2363 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2364 { 2365 return env->v7m.exception != 0; 2366 } 2367 2368 /* Return the current Exception Level (as per ARMv8; note that this differs 2369 * from the ARMv7 Privilege Level). 2370 */ 2371 static inline int arm_current_el(CPUARMState *env) 2372 { 2373 if (arm_feature(env, ARM_FEATURE_M)) { 2374 return arm_v7m_is_handler_mode(env) || 2375 !(env->v7m.control[env->v7m.secure] & 1); 2376 } 2377 2378 if (is_a64(env)) { 2379 return extract32(env->pstate, 2, 2); 2380 } 2381 2382 switch (env->uncached_cpsr & 0x1f) { 2383 case ARM_CPU_MODE_USR: 2384 return 0; 2385 case ARM_CPU_MODE_HYP: 2386 return 2; 2387 case ARM_CPU_MODE_MON: 2388 return 3; 2389 default: 2390 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2391 /* If EL3 is 32-bit then all secure privileged modes run in 2392 * EL3 2393 */ 2394 return 3; 2395 } 2396 2397 return 1; 2398 } 2399 } 2400 2401 typedef struct ARMCPRegInfo ARMCPRegInfo; 2402 2403 typedef enum CPAccessResult { 2404 /* Access is permitted */ 2405 CP_ACCESS_OK = 0, 2406 /* Access fails due to a configurable trap or enable which would 2407 * result in a categorized exception syndrome giving information about 2408 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2409 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2410 * PL1 if in EL0, otherwise to the current EL). 2411 */ 2412 CP_ACCESS_TRAP = 1, 2413 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2414 * Note that this is not a catch-all case -- the set of cases which may 2415 * result in this failure is specifically defined by the architecture. 2416 */ 2417 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2418 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2419 CP_ACCESS_TRAP_EL2 = 3, 2420 CP_ACCESS_TRAP_EL3 = 4, 2421 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2422 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2423 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2424 /* Access fails and results in an exception syndrome for an FP access, 2425 * trapped directly to EL2 or EL3 2426 */ 2427 CP_ACCESS_TRAP_FP_EL2 = 7, 2428 CP_ACCESS_TRAP_FP_EL3 = 8, 2429 } CPAccessResult; 2430 2431 /* Access functions for coprocessor registers. These cannot fail and 2432 * may not raise exceptions. 2433 */ 2434 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2435 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2436 uint64_t value); 2437 /* Access permission check functions for coprocessor registers. */ 2438 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2439 const ARMCPRegInfo *opaque, 2440 bool isread); 2441 /* Hook function for register reset */ 2442 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2443 2444 #define CP_ANY 0xff 2445 2446 /* Definition of an ARM coprocessor register */ 2447 struct ARMCPRegInfo { 2448 /* Name of register (useful mainly for debugging, need not be unique) */ 2449 const char *name; 2450 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2451 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2452 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2453 * will be decoded to this register. The register read and write 2454 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2455 * used by the program, so it is possible to register a wildcard and 2456 * then behave differently on read/write if necessary. 2457 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2458 * must both be zero. 2459 * For AArch64-visible registers, opc0 is also used. 2460 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2461 * way to distinguish (for KVM's benefit) guest-visible system registers 2462 * from demuxed ones provided to preserve the "no side effects on 2463 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2464 * visible (to match KVM's encoding); cp==0 will be converted to 2465 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2466 */ 2467 uint8_t cp; 2468 uint8_t crn; 2469 uint8_t crm; 2470 uint8_t opc0; 2471 uint8_t opc1; 2472 uint8_t opc2; 2473 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2474 int state; 2475 /* Register type: ARM_CP_* bits/values */ 2476 int type; 2477 /* Access rights: PL*_[RW] */ 2478 int access; 2479 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2480 int secure; 2481 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2482 * this register was defined: can be used to hand data through to the 2483 * register read/write functions, since they are passed the ARMCPRegInfo*. 2484 */ 2485 void *opaque; 2486 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2487 * fieldoffset is non-zero, the reset value of the register. 2488 */ 2489 uint64_t resetvalue; 2490 /* Offset of the field in CPUARMState for this register. 2491 * 2492 * This is not needed if either: 2493 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2494 * 2. both readfn and writefn are specified 2495 */ 2496 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2497 2498 /* Offsets of the secure and non-secure fields in CPUARMState for the 2499 * register if it is banked. These fields are only used during the static 2500 * registration of a register. During hashing the bank associated 2501 * with a given security state is copied to fieldoffset which is used from 2502 * there on out. 2503 * 2504 * It is expected that register definitions use either fieldoffset or 2505 * bank_fieldoffsets in the definition but not both. It is also expected 2506 * that both bank offsets are set when defining a banked register. This 2507 * use indicates that a register is banked. 2508 */ 2509 ptrdiff_t bank_fieldoffsets[2]; 2510 2511 /* Function for making any access checks for this register in addition to 2512 * those specified by the 'access' permissions bits. If NULL, no extra 2513 * checks required. The access check is performed at runtime, not at 2514 * translate time. 2515 */ 2516 CPAccessFn *accessfn; 2517 /* Function for handling reads of this register. If NULL, then reads 2518 * will be done by loading from the offset into CPUARMState specified 2519 * by fieldoffset. 2520 */ 2521 CPReadFn *readfn; 2522 /* Function for handling writes of this register. If NULL, then writes 2523 * will be done by writing to the offset into CPUARMState specified 2524 * by fieldoffset. 2525 */ 2526 CPWriteFn *writefn; 2527 /* Function for doing a "raw" read; used when we need to copy 2528 * coprocessor state to the kernel for KVM or out for 2529 * migration. This only needs to be provided if there is also a 2530 * readfn and it has side effects (for instance clear-on-read bits). 2531 */ 2532 CPReadFn *raw_readfn; 2533 /* Function for doing a "raw" write; used when we need to copy KVM 2534 * kernel coprocessor state into userspace, or for inbound 2535 * migration. This only needs to be provided if there is also a 2536 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2537 * or similar behaviour. 2538 */ 2539 CPWriteFn *raw_writefn; 2540 /* Function for resetting the register. If NULL, then reset will be done 2541 * by writing resetvalue to the field specified in fieldoffset. If 2542 * fieldoffset is 0 then no reset will be done. 2543 */ 2544 CPResetFn *resetfn; 2545 }; 2546 2547 /* Macros which are lvalues for the field in CPUARMState for the 2548 * ARMCPRegInfo *ri. 2549 */ 2550 #define CPREG_FIELD32(env, ri) \ 2551 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2552 #define CPREG_FIELD64(env, ri) \ 2553 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2554 2555 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2556 2557 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2558 const ARMCPRegInfo *regs, void *opaque); 2559 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2560 const ARMCPRegInfo *regs, void *opaque); 2561 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2562 { 2563 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2564 } 2565 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2566 { 2567 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2568 } 2569 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2570 2571 /* 2572 * Definition of an ARM co-processor register as viewed from 2573 * userspace. This is used for presenting sanitised versions of 2574 * registers to userspace when emulating the Linux AArch64 CPU 2575 * ID/feature ABI (advertised as HWCAP_CPUID). 2576 */ 2577 typedef struct ARMCPRegUserSpaceInfo { 2578 /* Name of register */ 2579 const char *name; 2580 2581 /* Is the name actually a glob pattern */ 2582 bool is_glob; 2583 2584 /* Only some bits are exported to user space */ 2585 uint64_t exported_bits; 2586 2587 /* Fixed bits are applied after the mask */ 2588 uint64_t fixed_bits; 2589 } ARMCPRegUserSpaceInfo; 2590 2591 #define REGUSERINFO_SENTINEL { .name = NULL } 2592 2593 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2594 2595 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2596 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2597 uint64_t value); 2598 /* CPReadFn that can be used for read-as-zero behaviour */ 2599 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2600 2601 /* CPResetFn that does nothing, for use if no reset is required even 2602 * if fieldoffset is non zero. 2603 */ 2604 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2605 2606 /* Return true if this reginfo struct's field in the cpu state struct 2607 * is 64 bits wide. 2608 */ 2609 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2610 { 2611 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2612 } 2613 2614 static inline bool cp_access_ok(int current_el, 2615 const ARMCPRegInfo *ri, int isread) 2616 { 2617 return (ri->access >> ((current_el * 2) + isread)) & 1; 2618 } 2619 2620 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2621 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2622 2623 /** 2624 * write_list_to_cpustate 2625 * @cpu: ARMCPU 2626 * 2627 * For each register listed in the ARMCPU cpreg_indexes list, write 2628 * its value from the cpreg_values list into the ARMCPUState structure. 2629 * This updates TCG's working data structures from KVM data or 2630 * from incoming migration state. 2631 * 2632 * Returns: true if all register values were updated correctly, 2633 * false if some register was unknown or could not be written. 2634 * Note that we do not stop early on failure -- we will attempt 2635 * writing all registers in the list. 2636 */ 2637 bool write_list_to_cpustate(ARMCPU *cpu); 2638 2639 /** 2640 * write_cpustate_to_list: 2641 * @cpu: ARMCPU 2642 * @kvm_sync: true if this is for syncing back to KVM 2643 * 2644 * For each register listed in the ARMCPU cpreg_indexes list, write 2645 * its value from the ARMCPUState structure into the cpreg_values list. 2646 * This is used to copy info from TCG's working data structures into 2647 * KVM or for outbound migration. 2648 * 2649 * @kvm_sync is true if we are doing this in order to sync the 2650 * register state back to KVM. In this case we will only update 2651 * values in the list if the previous list->cpustate sync actually 2652 * successfully wrote the CPU state. Otherwise we will keep the value 2653 * that is in the list. 2654 * 2655 * Returns: true if all register values were read correctly, 2656 * false if some register was unknown or could not be read. 2657 * Note that we do not stop early on failure -- we will attempt 2658 * reading all registers in the list. 2659 */ 2660 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2661 2662 #define ARM_CPUID_TI915T 0x54029152 2663 #define ARM_CPUID_TI925T 0x54029252 2664 2665 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2666 unsigned int target_el) 2667 { 2668 CPUARMState *env = cs->env_ptr; 2669 unsigned int cur_el = arm_current_el(env); 2670 bool secure = arm_is_secure(env); 2671 bool pstate_unmasked; 2672 int8_t unmasked = 0; 2673 uint64_t hcr_el2; 2674 2675 /* Don't take exceptions if they target a lower EL. 2676 * This check should catch any exceptions that would not be taken but left 2677 * pending. 2678 */ 2679 if (cur_el > target_el) { 2680 return false; 2681 } 2682 2683 hcr_el2 = arm_hcr_el2_eff(env); 2684 2685 switch (excp_idx) { 2686 case EXCP_FIQ: 2687 pstate_unmasked = !(env->daif & PSTATE_F); 2688 break; 2689 2690 case EXCP_IRQ: 2691 pstate_unmasked = !(env->daif & PSTATE_I); 2692 break; 2693 2694 case EXCP_VFIQ: 2695 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 2696 /* VFIQs are only taken when hypervized and non-secure. */ 2697 return false; 2698 } 2699 return !(env->daif & PSTATE_F); 2700 case EXCP_VIRQ: 2701 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 2702 /* VIRQs are only taken when hypervized and non-secure. */ 2703 return false; 2704 } 2705 return !(env->daif & PSTATE_I); 2706 default: 2707 g_assert_not_reached(); 2708 } 2709 2710 /* Use the target EL, current execution state and SCR/HCR settings to 2711 * determine whether the corresponding CPSR bit is used to mask the 2712 * interrupt. 2713 */ 2714 if ((target_el > cur_el) && (target_el != 1)) { 2715 /* Exceptions targeting a higher EL may not be maskable */ 2716 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2717 /* 64-bit masking rules are simple: exceptions to EL3 2718 * can't be masked, and exceptions to EL2 can only be 2719 * masked from Secure state. The HCR and SCR settings 2720 * don't affect the masking logic, only the interrupt routing. 2721 */ 2722 if (target_el == 3 || !secure) { 2723 unmasked = 1; 2724 } 2725 } else { 2726 /* The old 32-bit-only environment has a more complicated 2727 * masking setup. HCR and SCR bits not only affect interrupt 2728 * routing but also change the behaviour of masking. 2729 */ 2730 bool hcr, scr; 2731 2732 switch (excp_idx) { 2733 case EXCP_FIQ: 2734 /* If FIQs are routed to EL3 or EL2 then there are cases where 2735 * we override the CPSR.F in determining if the exception is 2736 * masked or not. If neither of these are set then we fall back 2737 * to the CPSR.F setting otherwise we further assess the state 2738 * below. 2739 */ 2740 hcr = hcr_el2 & HCR_FMO; 2741 scr = (env->cp15.scr_el3 & SCR_FIQ); 2742 2743 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2744 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2745 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2746 * when non-secure but only when FIQs are only routed to EL3. 2747 */ 2748 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2749 break; 2750 case EXCP_IRQ: 2751 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2752 * we may override the CPSR.I masking when in non-secure state. 2753 * The SCR.IRQ setting has already been taken into consideration 2754 * when setting the target EL, so it does not have a further 2755 * affect here. 2756 */ 2757 hcr = hcr_el2 & HCR_IMO; 2758 scr = false; 2759 break; 2760 default: 2761 g_assert_not_reached(); 2762 } 2763 2764 if ((scr || hcr) && !secure) { 2765 unmasked = 1; 2766 } 2767 } 2768 } 2769 2770 /* The PSTATE bits only mask the interrupt if we have not overriden the 2771 * ability above. 2772 */ 2773 return unmasked || pstate_unmasked; 2774 } 2775 2776 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2777 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2778 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2779 2780 #define cpu_signal_handler cpu_arm_signal_handler 2781 #define cpu_list arm_cpu_list 2782 2783 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2784 * 2785 * If EL3 is 64-bit: 2786 * + NonSecure EL1 & 0 stage 1 2787 * + NonSecure EL1 & 0 stage 2 2788 * + NonSecure EL2 2789 * + Secure EL1 & EL0 2790 * + Secure EL3 2791 * If EL3 is 32-bit: 2792 * + NonSecure PL1 & 0 stage 1 2793 * + NonSecure PL1 & 0 stage 2 2794 * + NonSecure PL2 2795 * + Secure PL0 & PL1 2796 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2797 * 2798 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2799 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2800 * may differ in access permissions even if the VA->PA map is the same 2801 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2802 * translation, which means that we have one mmu_idx that deals with two 2803 * concatenated translation regimes [this sort of combined s1+2 TLB is 2804 * architecturally permitted] 2805 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2806 * handling via the TLB. The only way to do a stage 1 translation without 2807 * the immediate stage 2 translation is via the ATS or AT system insns, 2808 * which can be slow-pathed and always do a page table walk. 2809 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2810 * translation regimes, because they map reasonably well to each other 2811 * and they can't both be active at the same time. 2812 * This gives us the following list of mmu_idx values: 2813 * 2814 * NS EL0 (aka NS PL0) stage 1+2 2815 * NS EL1 (aka NS PL1) stage 1+2 2816 * NS EL2 (aka NS PL2) 2817 * S EL3 (aka S PL1) 2818 * S EL0 (aka S PL0) 2819 * S EL1 (not used if EL3 is 32 bit) 2820 * NS EL0+1 stage 2 2821 * 2822 * (The last of these is an mmu_idx because we want to be able to use the TLB 2823 * for the accesses done as part of a stage 1 page table walk, rather than 2824 * having to walk the stage 2 page table over and over.) 2825 * 2826 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2827 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2828 * NS EL2 if we ever model a Cortex-R52). 2829 * 2830 * M profile CPUs are rather different as they do not have a true MMU. 2831 * They have the following different MMU indexes: 2832 * User 2833 * Privileged 2834 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2835 * Privileged, execution priority negative (ditto) 2836 * If the CPU supports the v8M Security Extension then there are also: 2837 * Secure User 2838 * Secure Privileged 2839 * Secure User, execution priority negative 2840 * Secure Privileged, execution priority negative 2841 * 2842 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2843 * are not quite the same -- different CPU types (most notably M profile 2844 * vs A/R profile) would like to use MMU indexes with different semantics, 2845 * but since we don't ever need to use all of those in a single CPU we 2846 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2847 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2848 * the same for any particular CPU. 2849 * Variables of type ARMMUIdx are always full values, and the core 2850 * index values are in variables of type 'int'. 2851 * 2852 * Our enumeration includes at the end some entries which are not "true" 2853 * mmu_idx values in that they don't have corresponding TLBs and are only 2854 * valid for doing slow path page table walks. 2855 * 2856 * The constant names here are patterned after the general style of the names 2857 * of the AT/ATS operations. 2858 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2859 * For M profile we arrange them to have a bit for priv, a bit for negpri 2860 * and a bit for secure. 2861 */ 2862 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2863 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2864 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2865 2866 /* meanings of the bits for M profile mmu idx values */ 2867 #define ARM_MMU_IDX_M_PRIV 0x1 2868 #define ARM_MMU_IDX_M_NEGPRI 0x2 2869 #define ARM_MMU_IDX_M_S 0x4 2870 2871 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2872 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2873 2874 typedef enum ARMMMUIdx { 2875 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2876 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2877 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2878 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2879 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2880 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2881 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2882 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2883 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2884 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2885 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2886 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2887 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2888 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2889 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2890 /* Indexes below here don't have TLBs and are used only for AT system 2891 * instructions or for the first stage of an S12 page table walk. 2892 */ 2893 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2894 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2895 } ARMMMUIdx; 2896 2897 /* Bit macros for the core-mmu-index values for each index, 2898 * for use when calling tlb_flush_by_mmuidx() and friends. 2899 */ 2900 typedef enum ARMMMUIdxBit { 2901 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2902 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2903 ARMMMUIdxBit_S1E2 = 1 << 2, 2904 ARMMMUIdxBit_S1E3 = 1 << 3, 2905 ARMMMUIdxBit_S1SE0 = 1 << 4, 2906 ARMMMUIdxBit_S1SE1 = 1 << 5, 2907 ARMMMUIdxBit_S2NS = 1 << 6, 2908 ARMMMUIdxBit_MUser = 1 << 0, 2909 ARMMMUIdxBit_MPriv = 1 << 1, 2910 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2911 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2912 ARMMMUIdxBit_MSUser = 1 << 4, 2913 ARMMMUIdxBit_MSPriv = 1 << 5, 2914 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2915 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2916 } ARMMMUIdxBit; 2917 2918 #define MMU_USER_IDX 0 2919 2920 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2921 { 2922 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2923 } 2924 2925 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2926 { 2927 if (arm_feature(env, ARM_FEATURE_M)) { 2928 return mmu_idx | ARM_MMU_IDX_M; 2929 } else { 2930 return mmu_idx | ARM_MMU_IDX_A; 2931 } 2932 } 2933 2934 /* Return the exception level we're running at if this is our mmu_idx */ 2935 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2936 { 2937 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2938 case ARM_MMU_IDX_A: 2939 return mmu_idx & 3; 2940 case ARM_MMU_IDX_M: 2941 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2942 default: 2943 g_assert_not_reached(); 2944 } 2945 } 2946 2947 /* 2948 * Return the MMU index for a v7M CPU with all relevant information 2949 * manually specified. 2950 */ 2951 ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, 2952 bool secstate, bool priv, bool negpri); 2953 2954 /* Return the MMU index for a v7M CPU in the specified security and 2955 * privilege state. 2956 */ 2957 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2958 bool secstate, bool priv); 2959 2960 /* Return the MMU index for a v7M CPU in the specified security state */ 2961 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); 2962 2963 /** 2964 * cpu_mmu_index: 2965 * @env: The cpu environment 2966 * @ifetch: True for code access, false for data access. 2967 * 2968 * Return the core mmu index for the current translation regime. 2969 * This function is used by generic TCG code paths. 2970 */ 2971 int cpu_mmu_index(CPUARMState *env, bool ifetch); 2972 2973 /* Indexes used when registering address spaces with cpu_address_space_init */ 2974 typedef enum ARMASIdx { 2975 ARMASIdx_NS = 0, 2976 ARMASIdx_S = 1, 2977 } ARMASIdx; 2978 2979 /* Return the Exception Level targeted by debug exceptions. */ 2980 static inline int arm_debug_target_el(CPUARMState *env) 2981 { 2982 bool secure = arm_is_secure(env); 2983 bool route_to_el2 = false; 2984 2985 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2986 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2987 env->cp15.mdcr_el2 & MDCR_TDE; 2988 } 2989 2990 if (route_to_el2) { 2991 return 2; 2992 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2993 !arm_el_is_aa64(env, 3) && secure) { 2994 return 3; 2995 } else { 2996 return 1; 2997 } 2998 } 2999 3000 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3001 { 3002 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3003 * CSSELR is RAZ/WI. 3004 */ 3005 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3006 } 3007 3008 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 3009 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 3010 { 3011 int cur_el = arm_current_el(env); 3012 int debug_el; 3013 3014 if (cur_el == 3) { 3015 return false; 3016 } 3017 3018 /* MDCR_EL3.SDD disables debug events from Secure state */ 3019 if (arm_is_secure_below_el3(env) 3020 && extract32(env->cp15.mdcr_el3, 16, 1)) { 3021 return false; 3022 } 3023 3024 /* 3025 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 3026 * while not masking the (D)ebug bit in DAIF. 3027 */ 3028 debug_el = arm_debug_target_el(env); 3029 3030 if (cur_el == debug_el) { 3031 return extract32(env->cp15.mdscr_el1, 13, 1) 3032 && !(env->daif & PSTATE_D); 3033 } 3034 3035 /* Otherwise the debug target needs to be a higher EL */ 3036 return debug_el > cur_el; 3037 } 3038 3039 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 3040 { 3041 int el = arm_current_el(env); 3042 3043 if (el == 0 && arm_el_is_aa64(env, 1)) { 3044 return aa64_generate_debug_exceptions(env); 3045 } 3046 3047 if (arm_is_secure(env)) { 3048 int spd; 3049 3050 if (el == 0 && (env->cp15.sder & 1)) { 3051 /* SDER.SUIDEN means debug exceptions from Secure EL0 3052 * are always enabled. Otherwise they are controlled by 3053 * SDCR.SPD like those from other Secure ELs. 3054 */ 3055 return true; 3056 } 3057 3058 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3059 switch (spd) { 3060 case 1: 3061 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3062 case 0: 3063 /* For 0b00 we return true if external secure invasive debug 3064 * is enabled. On real hardware this is controlled by external 3065 * signals to the core. QEMU always permits debug, and behaves 3066 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3067 */ 3068 return true; 3069 case 2: 3070 return false; 3071 case 3: 3072 return true; 3073 } 3074 } 3075 3076 return el != 2; 3077 } 3078 3079 /* Return true if debugging exceptions are currently enabled. 3080 * This corresponds to what in ARM ARM pseudocode would be 3081 * if UsingAArch32() then 3082 * return AArch32.GenerateDebugExceptions() 3083 * else 3084 * return AArch64.GenerateDebugExceptions() 3085 * We choose to push the if() down into this function for clarity, 3086 * since the pseudocode has it at all callsites except for the one in 3087 * CheckSoftwareStep(), where it is elided because both branches would 3088 * always return the same value. 3089 */ 3090 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3091 { 3092 if (env->aarch64) { 3093 return aa64_generate_debug_exceptions(env); 3094 } else { 3095 return aa32_generate_debug_exceptions(env); 3096 } 3097 } 3098 3099 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3100 * implicitly means this always returns false in pre-v8 CPUs.) 3101 */ 3102 static inline bool arm_singlestep_active(CPUARMState *env) 3103 { 3104 return extract32(env->cp15.mdscr_el1, 0, 1) 3105 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3106 && arm_generate_debug_exceptions(env); 3107 } 3108 3109 static inline bool arm_sctlr_b(CPUARMState *env) 3110 { 3111 return 3112 /* We need not implement SCTLR.ITD in user-mode emulation, so 3113 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3114 * This lets people run BE32 binaries with "-cpu any". 3115 */ 3116 #ifndef CONFIG_USER_ONLY 3117 !arm_feature(env, ARM_FEATURE_V7) && 3118 #endif 3119 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3120 } 3121 3122 static inline uint64_t arm_sctlr(CPUARMState *env, int el) 3123 { 3124 if (el == 0) { 3125 /* FIXME: ARMv8.1-VHE S2 translation regime. */ 3126 return env->cp15.sctlr_el[1]; 3127 } else { 3128 return env->cp15.sctlr_el[el]; 3129 } 3130 } 3131 3132 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3133 bool sctlr_b) 3134 { 3135 #ifdef CONFIG_USER_ONLY 3136 /* 3137 * In system mode, BE32 is modelled in line with the 3138 * architecture (as word-invariant big-endianness), where loads 3139 * and stores are done little endian but from addresses which 3140 * are adjusted by XORing with the appropriate constant. So the 3141 * endianness to use for the raw data access is not affected by 3142 * SCTLR.B. 3143 * In user mode, however, we model BE32 as byte-invariant 3144 * big-endianness (because user-only code cannot tell the 3145 * difference), and so we need to use a data access endianness 3146 * that depends on SCTLR.B. 3147 */ 3148 if (sctlr_b) { 3149 return true; 3150 } 3151 #endif 3152 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3153 return env->uncached_cpsr & CPSR_E; 3154 } 3155 3156 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3157 { 3158 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3159 } 3160 3161 /* Return true if the processor is in big-endian mode. */ 3162 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3163 { 3164 if (!is_a64(env)) { 3165 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3166 } else { 3167 int cur_el = arm_current_el(env); 3168 uint64_t sctlr = arm_sctlr(env, cur_el); 3169 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3170 } 3171 } 3172 3173 typedef CPUARMState CPUArchState; 3174 typedef ARMCPU ArchCPU; 3175 3176 #include "exec/cpu-all.h" 3177 3178 /* 3179 * Bit usage in the TB flags field: bit 31 indicates whether we are 3180 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 3181 * We put flags which are shared between 32 and 64 bit mode at the top 3182 * of the word, and flags which apply to only one mode at the bottom. 3183 * 3184 * Unless otherwise noted, these bits are cached in env->hflags. 3185 */ 3186 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3187 FIELD(TBFLAG_ANY, MMUIDX, 28, 3) 3188 FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) 3189 FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ 3190 /* Target EL if we take a floating-point-disabled exception */ 3191 FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) 3192 FIELD(TBFLAG_ANY, BE_DATA, 23, 1) 3193 /* 3194 * For A-profile only, target EL for debug exceptions. 3195 * Note that this overlaps with the M-profile-only HANDLER and STACKCHECK bits. 3196 */ 3197 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) 3198 3199 /* Bit usage when in AArch32 state: */ 3200 FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ 3201 FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */ 3202 FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */ 3203 /* 3204 * We store the bottom two bits of the CPAR as TB flags and handle 3205 * checks on the other bits at runtime. This shares the same bits as 3206 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3207 * Not cached, because VECLEN+VECSTRIDE are not cached. 3208 */ 3209 FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) 3210 /* 3211 * Indicates whether cp register reads and writes by guest code should access 3212 * the secure or nonsecure bank of banked registers; note that this is not 3213 * the same thing as the current security state of the processor! 3214 */ 3215 FIELD(TBFLAG_A32, NS, 6, 1) 3216 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3217 FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ 3218 FIELD(TBFLAG_A32, SCTLR_B, 16, 1) 3219 /* For M profile only, set if FPCCR.LSPACT is set */ 3220 FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */ 3221 /* For M profile only, set if we must create a new FP context */ 3222 FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */ 3223 /* For M profile only, set if FPCCR.S does not match current security state */ 3224 FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */ 3225 /* For M profile only, Handler (ie not Thread) mode */ 3226 FIELD(TBFLAG_A32, HANDLER, 21, 1) 3227 /* For M profile only, whether we should generate stack-limit checks */ 3228 FIELD(TBFLAG_A32, STACKCHECK, 22, 1) 3229 3230 /* Bit usage when in AArch64 state */ 3231 FIELD(TBFLAG_A64, TBII, 0, 2) 3232 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3233 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3234 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3235 FIELD(TBFLAG_A64, BT, 9, 1) 3236 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3237 FIELD(TBFLAG_A64, TBID, 12, 2) 3238 3239 static inline bool bswap_code(bool sctlr_b) 3240 { 3241 #ifdef CONFIG_USER_ONLY 3242 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3243 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3244 * would also end up as a mixed-endian mode with BE code, LE data. 3245 */ 3246 return 3247 #ifdef TARGET_WORDS_BIGENDIAN 3248 1 ^ 3249 #endif 3250 sctlr_b; 3251 #else 3252 /* All code access in ARM is little endian, and there are no loaders 3253 * doing swaps that need to be reversed 3254 */ 3255 return 0; 3256 #endif 3257 } 3258 3259 #ifdef CONFIG_USER_ONLY 3260 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3261 { 3262 return 3263 #ifdef TARGET_WORDS_BIGENDIAN 3264 1 ^ 3265 #endif 3266 arm_cpu_data_is_big_endian(env); 3267 } 3268 #endif 3269 3270 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3271 target_ulong *cs_base, uint32_t *flags); 3272 3273 enum { 3274 QEMU_PSCI_CONDUIT_DISABLED = 0, 3275 QEMU_PSCI_CONDUIT_SMC = 1, 3276 QEMU_PSCI_CONDUIT_HVC = 2, 3277 }; 3278 3279 #ifndef CONFIG_USER_ONLY 3280 /* Return the address space index to use for a memory access */ 3281 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3282 { 3283 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3284 } 3285 3286 /* Return the AddressSpace to use for a memory access 3287 * (which depends on whether the access is S or NS, and whether 3288 * the board gave us a separate AddressSpace for S accesses). 3289 */ 3290 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3291 { 3292 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3293 } 3294 #endif 3295 3296 /** 3297 * arm_register_pre_el_change_hook: 3298 * Register a hook function which will be called immediately before this 3299 * CPU changes exception level or mode. The hook function will be 3300 * passed a pointer to the ARMCPU and the opaque data pointer passed 3301 * to this function when the hook was registered. 3302 * 3303 * Note that if a pre-change hook is called, any registered post-change hooks 3304 * are guaranteed to subsequently be called. 3305 */ 3306 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3307 void *opaque); 3308 /** 3309 * arm_register_el_change_hook: 3310 * Register a hook function which will be called immediately after this 3311 * CPU changes exception level or mode. The hook function will be 3312 * passed a pointer to the ARMCPU and the opaque data pointer passed 3313 * to this function when the hook was registered. 3314 * 3315 * Note that any registered hooks registered here are guaranteed to be called 3316 * if pre-change hooks have been. 3317 */ 3318 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3319 *opaque); 3320 3321 /** 3322 * arm_rebuild_hflags: 3323 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3324 */ 3325 void arm_rebuild_hflags(CPUARMState *env); 3326 3327 /** 3328 * aa32_vfp_dreg: 3329 * Return a pointer to the Dn register within env in 32-bit mode. 3330 */ 3331 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3332 { 3333 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3334 } 3335 3336 /** 3337 * aa32_vfp_qreg: 3338 * Return a pointer to the Qn register within env in 32-bit mode. 3339 */ 3340 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3341 { 3342 return &env->vfp.zregs[regno].d[0]; 3343 } 3344 3345 /** 3346 * aa64_vfp_qreg: 3347 * Return a pointer to the Qn register within env in 64-bit mode. 3348 */ 3349 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3350 { 3351 return &env->vfp.zregs[regno].d[0]; 3352 } 3353 3354 /* Shared between translate-sve.c and sve_helper.c. */ 3355 extern const uint64_t pred_esz_masks[4]; 3356 3357 /* 3358 * 32-bit feature tests via id registers. 3359 */ 3360 static inline bool isar_feature_thumb_div(const ARMISARegisters *id) 3361 { 3362 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3363 } 3364 3365 static inline bool isar_feature_arm_div(const ARMISARegisters *id) 3366 { 3367 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3368 } 3369 3370 static inline bool isar_feature_jazelle(const ARMISARegisters *id) 3371 { 3372 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3373 } 3374 3375 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3376 { 3377 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3378 } 3379 3380 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3381 { 3382 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3383 } 3384 3385 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3386 { 3387 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3388 } 3389 3390 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3391 { 3392 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3393 } 3394 3395 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3396 { 3397 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3398 } 3399 3400 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3401 { 3402 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3403 } 3404 3405 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3406 { 3407 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3408 } 3409 3410 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3411 { 3412 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3413 } 3414 3415 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3416 { 3417 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3418 } 3419 3420 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3421 { 3422 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3423 } 3424 3425 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3426 { 3427 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3428 } 3429 3430 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3431 { 3432 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3433 } 3434 3435 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3436 { 3437 /* 3438 * This is a placeholder for use by VCMA until the rest of 3439 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3440 * At which point we can properly set and check MVFR1.FPHP. 3441 */ 3442 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3443 } 3444 3445 static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id) 3446 { 3447 /* Return true if D16-D31 are implemented */ 3448 return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >= 2; 3449 } 3450 3451 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3452 { 3453 return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0; 3454 } 3455 3456 static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) 3457 { 3458 /* Return true if CPU supports double precision floating point */ 3459 return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0; 3460 } 3461 3462 /* 3463 * We always set the FP and SIMD FP16 fields to indicate identical 3464 * levels of support (assuming SIMD is implemented at all), so 3465 * we only need one set of accessors. 3466 */ 3467 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3468 { 3469 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0; 3470 } 3471 3472 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3473 { 3474 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; 3475 } 3476 3477 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3478 { 3479 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1; 3480 } 3481 3482 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3483 { 3484 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2; 3485 } 3486 3487 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3488 { 3489 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3; 3490 } 3491 3492 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3493 { 3494 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; 3495 } 3496 3497 /* 3498 * 64-bit feature tests via id registers. 3499 */ 3500 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3501 { 3502 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3503 } 3504 3505 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3506 { 3507 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3508 } 3509 3510 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3511 { 3512 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3513 } 3514 3515 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3516 { 3517 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3518 } 3519 3520 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3521 { 3522 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3523 } 3524 3525 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3526 { 3527 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3528 } 3529 3530 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3531 { 3532 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3533 } 3534 3535 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3536 { 3537 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3538 } 3539 3540 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3541 { 3542 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3543 } 3544 3545 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3546 { 3547 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3548 } 3549 3550 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3551 { 3552 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3553 } 3554 3555 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3556 { 3557 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3558 } 3559 3560 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3561 { 3562 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3563 } 3564 3565 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3566 { 3567 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3568 } 3569 3570 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3571 { 3572 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3573 } 3574 3575 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3576 { 3577 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3578 } 3579 3580 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3581 { 3582 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3583 } 3584 3585 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3586 { 3587 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3588 } 3589 3590 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3591 { 3592 /* 3593 * Note that while QEMU will only implement the architected algorithm 3594 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation 3595 * defined algorithms, and thus API+GPI, and this predicate controls 3596 * migration of the 128-bit keys. 3597 */ 3598 return (id->id_aa64isar1 & 3599 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3600 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3601 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3602 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3603 } 3604 3605 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3606 { 3607 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3608 } 3609 3610 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3611 { 3612 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3613 } 3614 3615 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3616 { 3617 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3618 } 3619 3620 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3621 { 3622 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3623 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3624 } 3625 3626 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3627 { 3628 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3629 } 3630 3631 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3632 { 3633 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3634 } 3635 3636 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3637 { 3638 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3639 } 3640 3641 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3642 { 3643 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3644 } 3645 3646 /* 3647 * Forward to the above feature tests given an ARMCPU pointer. 3648 */ 3649 #define cpu_isar_feature(name, cpu) \ 3650 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3651 3652 #endif 3653