1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 #include "cpu-qom.h" 26 #include "exec/cpu-defs.h" 27 28 /* ARM processors have a weak memory model */ 29 #define TCG_GUEST_DEFAULT_MO (0) 30 31 #define EXCP_UDEF 1 /* undefined instruction */ 32 #define EXCP_SWI 2 /* software interrupt */ 33 #define EXCP_PREFETCH_ABORT 3 34 #define EXCP_DATA_ABORT 4 35 #define EXCP_IRQ 5 36 #define EXCP_FIQ 6 37 #define EXCP_BKPT 7 38 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 39 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 40 #define EXCP_HVC 11 /* HyperVisor Call */ 41 #define EXCP_HYP_TRAP 12 42 #define EXCP_SMC 13 /* Secure Monitor Call */ 43 #define EXCP_VIRQ 14 44 #define EXCP_VFIQ 15 45 #define EXCP_SEMIHOST 16 /* semihosting call */ 46 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 47 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 48 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 49 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 50 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 51 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 52 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 53 54 #define ARMV7M_EXCP_RESET 1 55 #define ARMV7M_EXCP_NMI 2 56 #define ARMV7M_EXCP_HARD 3 57 #define ARMV7M_EXCP_MEM 4 58 #define ARMV7M_EXCP_BUS 5 59 #define ARMV7M_EXCP_USAGE 6 60 #define ARMV7M_EXCP_SECURE 7 61 #define ARMV7M_EXCP_SVC 11 62 #define ARMV7M_EXCP_DEBUG 12 63 #define ARMV7M_EXCP_PENDSV 14 64 #define ARMV7M_EXCP_SYSTICK 15 65 66 /* For M profile, some registers are banked secure vs non-secure; 67 * these are represented as a 2-element array where the first element 68 * is the non-secure copy and the second is the secure copy. 69 * When the CPU does not have implement the security extension then 70 * only the first element is used. 71 * This means that the copy for the current security state can be 72 * accessed via env->registerfield[env->v7m.secure] (whether the security 73 * extension is implemented or not). 74 */ 75 enum { 76 M_REG_NS = 0, 77 M_REG_S = 1, 78 M_REG_NUM_BANKS = 2, 79 }; 80 81 /* ARM-specific interrupt pending bits. */ 82 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 83 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 84 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 85 86 /* The usual mapping for an AArch64 system register to its AArch32 87 * counterpart is for the 32 bit world to have access to the lower 88 * half only (with writes leaving the upper half untouched). It's 89 * therefore useful to be able to pass TCG the offset of the least 90 * significant half of a uint64_t struct member. 91 */ 92 #ifdef HOST_WORDS_BIGENDIAN 93 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 94 #define offsetofhigh32(S, M) offsetof(S, M) 95 #else 96 #define offsetoflow32(S, M) offsetof(S, M) 97 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 98 #endif 99 100 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 101 #define ARM_CPU_IRQ 0 102 #define ARM_CPU_FIQ 1 103 #define ARM_CPU_VIRQ 2 104 #define ARM_CPU_VFIQ 3 105 106 /* ARM-specific extra insn start words: 107 * 1: Conditional execution bits 108 * 2: Partial exception syndrome for data aborts 109 */ 110 #define TARGET_INSN_START_EXTRA_WORDS 2 111 112 /* The 2nd extra word holding syndrome info for data aborts does not use 113 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 114 * help the sleb128 encoder do a better job. 115 * When restoring the CPU state, we shift it back up. 116 */ 117 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 118 #define ARM_INSN_START_WORD2_SHIFT 14 119 120 /* We currently assume float and double are IEEE single and double 121 precision respectively. 122 Doing runtime conversions is tricky because VFP registers may contain 123 integer values (eg. as the result of a FTOSI instruction). 124 s<2n> maps to the least significant half of d<n> 125 s<2n+1> maps to the most significant half of d<n> 126 */ 127 128 /** 129 * DynamicGDBXMLInfo: 130 * @desc: Contains the XML descriptions. 131 * @num_cpregs: Number of the Coprocessor registers seen by GDB. 132 * @cpregs_keys: Array that contains the corresponding Key of 133 * a given cpreg with the same order of the cpreg in the XML description. 134 */ 135 typedef struct DynamicGDBXMLInfo { 136 char *desc; 137 int num_cpregs; 138 uint32_t *cpregs_keys; 139 } DynamicGDBXMLInfo; 140 141 /* CPU state for each instance of a generic timer (in cp15 c14) */ 142 typedef struct ARMGenericTimer { 143 uint64_t cval; /* Timer CompareValue register */ 144 uint64_t ctl; /* Timer Control register */ 145 } ARMGenericTimer; 146 147 #define GTIMER_PHYS 0 148 #define GTIMER_VIRT 1 149 #define GTIMER_HYP 2 150 #define GTIMER_SEC 3 151 #define NUM_GTIMERS 4 152 153 typedef struct { 154 uint64_t raw_tcr; 155 uint32_t mask; 156 uint32_t base_mask; 157 } TCR; 158 159 /* Define a maximum sized vector register. 160 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 161 * For 64-bit, this is a 2048-bit SVE register. 162 * 163 * Note that the mapping between S, D, and Q views of the register bank 164 * differs between AArch64 and AArch32. 165 * In AArch32: 166 * Qn = regs[n].d[1]:regs[n].d[0] 167 * Dn = regs[n / 2].d[n & 1] 168 * Sn = regs[n / 4].d[n % 4 / 2], 169 * bits 31..0 for even n, and bits 63..32 for odd n 170 * (and regs[16] to regs[31] are inaccessible) 171 * In AArch64: 172 * Zn = regs[n].d[*] 173 * Qn = regs[n].d[1]:regs[n].d[0] 174 * Dn = regs[n].d[0] 175 * Sn = regs[n].d[0] bits 31..0 176 * Hn = regs[n].d[0] bits 15..0 177 * 178 * This corresponds to the architecturally defined mapping between 179 * the two execution states, and means we do not need to explicitly 180 * map these registers when changing states. 181 * 182 * Align the data for use with TCG host vector operations. 183 */ 184 185 #ifdef TARGET_AARCH64 186 # define ARM_MAX_VQ 16 187 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 188 #else 189 # define ARM_MAX_VQ 1 190 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 191 #endif 192 193 typedef struct ARMVectorReg { 194 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 195 } ARMVectorReg; 196 197 #ifdef TARGET_AARCH64 198 /* In AArch32 mode, predicate registers do not exist at all. */ 199 typedef struct ARMPredicateReg { 200 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 201 } ARMPredicateReg; 202 203 /* In AArch32 mode, PAC keys do not exist at all. */ 204 typedef struct ARMPACKey { 205 uint64_t lo, hi; 206 } ARMPACKey; 207 #endif 208 209 210 typedef struct CPUARMState { 211 /* Regs for current mode. */ 212 uint32_t regs[16]; 213 214 /* 32/64 switch only happens when taking and returning from 215 * exceptions so the overlap semantics are taken care of then 216 * instead of having a complicated union. 217 */ 218 /* Regs for A64 mode. */ 219 uint64_t xregs[32]; 220 uint64_t pc; 221 /* PSTATE isn't an architectural register for ARMv8. However, it is 222 * convenient for us to assemble the underlying state into a 32 bit format 223 * identical to the architectural format used for the SPSR. (This is also 224 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 225 * 'pstate' register are.) Of the PSTATE bits: 226 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 227 * semantics as for AArch32, as described in the comments on each field) 228 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 229 * DAIF (exception masks) are kept in env->daif 230 * BTYPE is kept in env->btype 231 * all other bits are stored in their correct places in env->pstate 232 */ 233 uint32_t pstate; 234 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 235 236 /* Cached TBFLAGS state. See below for which bits are included. */ 237 uint32_t hflags; 238 239 /* Frequently accessed CPSR bits are stored separately for efficiency. 240 This contains all the other bits. Use cpsr_{read,write} to access 241 the whole CPSR. */ 242 uint32_t uncached_cpsr; 243 uint32_t spsr; 244 245 /* Banked registers. */ 246 uint64_t banked_spsr[8]; 247 uint32_t banked_r13[8]; 248 uint32_t banked_r14[8]; 249 250 /* These hold r8-r12. */ 251 uint32_t usr_regs[5]; 252 uint32_t fiq_regs[5]; 253 254 /* cpsr flag cache for faster execution */ 255 uint32_t CF; /* 0 or 1 */ 256 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 257 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 258 uint32_t ZF; /* Z set if zero. */ 259 uint32_t QF; /* 0 or 1 */ 260 uint32_t GE; /* cpsr[19:16] */ 261 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 262 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 263 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 264 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 265 266 uint64_t elr_el[4]; /* AArch64 exception link regs */ 267 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 268 269 /* System control coprocessor (cp15) */ 270 struct { 271 uint32_t c0_cpuid; 272 union { /* Cache size selection */ 273 struct { 274 uint64_t _unused_csselr0; 275 uint64_t csselr_ns; 276 uint64_t _unused_csselr1; 277 uint64_t csselr_s; 278 }; 279 uint64_t csselr_el[4]; 280 }; 281 union { /* System control register. */ 282 struct { 283 uint64_t _unused_sctlr; 284 uint64_t sctlr_ns; 285 uint64_t hsctlr; 286 uint64_t sctlr_s; 287 }; 288 uint64_t sctlr_el[4]; 289 }; 290 uint64_t cpacr_el1; /* Architectural feature access control register */ 291 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 292 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 293 uint64_t sder; /* Secure debug enable register. */ 294 uint32_t nsacr; /* Non-secure access control register. */ 295 union { /* MMU translation table base 0. */ 296 struct { 297 uint64_t _unused_ttbr0_0; 298 uint64_t ttbr0_ns; 299 uint64_t _unused_ttbr0_1; 300 uint64_t ttbr0_s; 301 }; 302 uint64_t ttbr0_el[4]; 303 }; 304 union { /* MMU translation table base 1. */ 305 struct { 306 uint64_t _unused_ttbr1_0; 307 uint64_t ttbr1_ns; 308 uint64_t _unused_ttbr1_1; 309 uint64_t ttbr1_s; 310 }; 311 uint64_t ttbr1_el[4]; 312 }; 313 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 314 /* MMU translation table base control. */ 315 TCR tcr_el[4]; 316 TCR vtcr_el2; /* Virtualization Translation Control. */ 317 uint32_t c2_data; /* MPU data cacheable bits. */ 318 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 319 union { /* MMU domain access control register 320 * MPU write buffer control. 321 */ 322 struct { 323 uint64_t dacr_ns; 324 uint64_t dacr_s; 325 }; 326 struct { 327 uint64_t dacr32_el2; 328 }; 329 }; 330 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 331 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 332 uint64_t hcr_el2; /* Hypervisor configuration register */ 333 uint64_t scr_el3; /* Secure configuration register. */ 334 union { /* Fault status registers. */ 335 struct { 336 uint64_t ifsr_ns; 337 uint64_t ifsr_s; 338 }; 339 struct { 340 uint64_t ifsr32_el2; 341 }; 342 }; 343 union { 344 struct { 345 uint64_t _unused_dfsr; 346 uint64_t dfsr_ns; 347 uint64_t hsr; 348 uint64_t dfsr_s; 349 }; 350 uint64_t esr_el[4]; 351 }; 352 uint32_t c6_region[8]; /* MPU base/size registers. */ 353 union { /* Fault address registers. */ 354 struct { 355 uint64_t _unused_far0; 356 #ifdef HOST_WORDS_BIGENDIAN 357 uint32_t ifar_ns; 358 uint32_t dfar_ns; 359 uint32_t ifar_s; 360 uint32_t dfar_s; 361 #else 362 uint32_t dfar_ns; 363 uint32_t ifar_ns; 364 uint32_t dfar_s; 365 uint32_t ifar_s; 366 #endif 367 uint64_t _unused_far3; 368 }; 369 uint64_t far_el[4]; 370 }; 371 uint64_t hpfar_el2; 372 uint64_t hstr_el2; 373 union { /* Translation result. */ 374 struct { 375 uint64_t _unused_par_0; 376 uint64_t par_ns; 377 uint64_t _unused_par_1; 378 uint64_t par_s; 379 }; 380 uint64_t par_el[4]; 381 }; 382 383 uint32_t c9_insn; /* Cache lockdown registers. */ 384 uint32_t c9_data; 385 uint64_t c9_pmcr; /* performance monitor control register */ 386 uint64_t c9_pmcnten; /* perf monitor counter enables */ 387 uint64_t c9_pmovsr; /* perf monitor overflow status */ 388 uint64_t c9_pmuserenr; /* perf monitor user enable */ 389 uint64_t c9_pmselr; /* perf monitor counter selection register */ 390 uint64_t c9_pminten; /* perf monitor interrupt enables */ 391 union { /* Memory attribute redirection */ 392 struct { 393 #ifdef HOST_WORDS_BIGENDIAN 394 uint64_t _unused_mair_0; 395 uint32_t mair1_ns; 396 uint32_t mair0_ns; 397 uint64_t _unused_mair_1; 398 uint32_t mair1_s; 399 uint32_t mair0_s; 400 #else 401 uint64_t _unused_mair_0; 402 uint32_t mair0_ns; 403 uint32_t mair1_ns; 404 uint64_t _unused_mair_1; 405 uint32_t mair0_s; 406 uint32_t mair1_s; 407 #endif 408 }; 409 uint64_t mair_el[4]; 410 }; 411 union { /* vector base address register */ 412 struct { 413 uint64_t _unused_vbar; 414 uint64_t vbar_ns; 415 uint64_t hvbar; 416 uint64_t vbar_s; 417 }; 418 uint64_t vbar_el[4]; 419 }; 420 uint32_t mvbar; /* (monitor) vector base address register */ 421 struct { /* FCSE PID. */ 422 uint32_t fcseidr_ns; 423 uint32_t fcseidr_s; 424 }; 425 union { /* Context ID. */ 426 struct { 427 uint64_t _unused_contextidr_0; 428 uint64_t contextidr_ns; 429 uint64_t _unused_contextidr_1; 430 uint64_t contextidr_s; 431 }; 432 uint64_t contextidr_el[4]; 433 }; 434 union { /* User RW Thread register. */ 435 struct { 436 uint64_t tpidrurw_ns; 437 uint64_t tpidrprw_ns; 438 uint64_t htpidr; 439 uint64_t _tpidr_el3; 440 }; 441 uint64_t tpidr_el[4]; 442 }; 443 /* The secure banks of these registers don't map anywhere */ 444 uint64_t tpidrurw_s; 445 uint64_t tpidrprw_s; 446 uint64_t tpidruro_s; 447 448 union { /* User RO Thread register. */ 449 uint64_t tpidruro_ns; 450 uint64_t tpidrro_el[1]; 451 }; 452 uint64_t c14_cntfrq; /* Counter Frequency register */ 453 uint64_t c14_cntkctl; /* Timer Control register */ 454 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 455 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 456 ARMGenericTimer c14_timer[NUM_GTIMERS]; 457 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 458 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 459 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 460 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 461 uint32_t c15_threadid; /* TI debugger thread-ID. */ 462 uint32_t c15_config_base_address; /* SCU base address. */ 463 uint32_t c15_diagnostic; /* diagnostic register */ 464 uint32_t c15_power_diagnostic; 465 uint32_t c15_power_control; /* power control */ 466 uint64_t dbgbvr[16]; /* breakpoint value registers */ 467 uint64_t dbgbcr[16]; /* breakpoint control registers */ 468 uint64_t dbgwvr[16]; /* watchpoint value registers */ 469 uint64_t dbgwcr[16]; /* watchpoint control registers */ 470 uint64_t mdscr_el1; 471 uint64_t oslsr_el1; /* OS Lock Status */ 472 uint64_t mdcr_el2; 473 uint64_t mdcr_el3; 474 /* Stores the architectural value of the counter *the last time it was 475 * updated* by pmccntr_op_start. Accesses should always be surrounded 476 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 477 * architecturally-correct value is being read/set. 478 */ 479 uint64_t c15_ccnt; 480 /* Stores the delta between the architectural value and the underlying 481 * cycle count during normal operation. It is used to update c15_ccnt 482 * to be the correct architectural value before accesses. During 483 * accesses, c15_ccnt_delta contains the underlying count being used 484 * for the access, after which it reverts to the delta value in 485 * pmccntr_op_finish. 486 */ 487 uint64_t c15_ccnt_delta; 488 uint64_t c14_pmevcntr[31]; 489 uint64_t c14_pmevcntr_delta[31]; 490 uint64_t c14_pmevtyper[31]; 491 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 492 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 493 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 494 } cp15; 495 496 struct { 497 /* M profile has up to 4 stack pointers: 498 * a Main Stack Pointer and a Process Stack Pointer for each 499 * of the Secure and Non-Secure states. (If the CPU doesn't support 500 * the security extension then it has only two SPs.) 501 * In QEMU we always store the currently active SP in regs[13], 502 * and the non-active SP for the current security state in 503 * v7m.other_sp. The stack pointers for the inactive security state 504 * are stored in other_ss_msp and other_ss_psp. 505 * switch_v7m_security_state() is responsible for rearranging them 506 * when we change security state. 507 */ 508 uint32_t other_sp; 509 uint32_t other_ss_msp; 510 uint32_t other_ss_psp; 511 uint32_t vecbase[M_REG_NUM_BANKS]; 512 uint32_t basepri[M_REG_NUM_BANKS]; 513 uint32_t control[M_REG_NUM_BANKS]; 514 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 515 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 516 uint32_t hfsr; /* HardFault Status */ 517 uint32_t dfsr; /* Debug Fault Status Register */ 518 uint32_t sfsr; /* Secure Fault Status Register */ 519 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 520 uint32_t bfar; /* BusFault Address */ 521 uint32_t sfar; /* Secure Fault Address Register */ 522 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 523 int exception; 524 uint32_t primask[M_REG_NUM_BANKS]; 525 uint32_t faultmask[M_REG_NUM_BANKS]; 526 uint32_t aircr; /* only holds r/w state if security extn implemented */ 527 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 528 uint32_t csselr[M_REG_NUM_BANKS]; 529 uint32_t scr[M_REG_NUM_BANKS]; 530 uint32_t msplim[M_REG_NUM_BANKS]; 531 uint32_t psplim[M_REG_NUM_BANKS]; 532 uint32_t fpcar[M_REG_NUM_BANKS]; 533 uint32_t fpccr[M_REG_NUM_BANKS]; 534 uint32_t fpdscr[M_REG_NUM_BANKS]; 535 uint32_t cpacr[M_REG_NUM_BANKS]; 536 uint32_t nsacr; 537 } v7m; 538 539 /* Information associated with an exception about to be taken: 540 * code which raises an exception must set cs->exception_index and 541 * the relevant parts of this structure; the cpu_do_interrupt function 542 * will then set the guest-visible registers as part of the exception 543 * entry process. 544 */ 545 struct { 546 uint32_t syndrome; /* AArch64 format syndrome register */ 547 uint32_t fsr; /* AArch32 format fault status register info */ 548 uint64_t vaddress; /* virtual addr associated with exception, if any */ 549 uint32_t target_el; /* EL the exception should be targeted for */ 550 /* If we implement EL2 we will also need to store information 551 * about the intermediate physical address for stage 2 faults. 552 */ 553 } exception; 554 555 /* Information associated with an SError */ 556 struct { 557 uint8_t pending; 558 uint8_t has_esr; 559 uint64_t esr; 560 } serror; 561 562 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 563 uint32_t irq_line_state; 564 565 /* Thumb-2 EE state. */ 566 uint32_t teecr; 567 uint32_t teehbr; 568 569 /* VFP coprocessor state. */ 570 struct { 571 ARMVectorReg zregs[32]; 572 573 #ifdef TARGET_AARCH64 574 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 575 #define FFR_PRED_NUM 16 576 ARMPredicateReg pregs[17]; 577 /* Scratch space for aa64 sve predicate temporary. */ 578 ARMPredicateReg preg_tmp; 579 #endif 580 581 /* We store these fpcsr fields separately for convenience. */ 582 uint32_t qc[4] QEMU_ALIGNED(16); 583 int vec_len; 584 int vec_stride; 585 586 uint32_t xregs[16]; 587 588 /* Scratch space for aa32 neon expansion. */ 589 uint32_t scratch[8]; 590 591 /* There are a number of distinct float control structures: 592 * 593 * fp_status: is the "normal" fp status. 594 * fp_status_fp16: used for half-precision calculations 595 * standard_fp_status : the ARM "Standard FPSCR Value" 596 * 597 * Half-precision operations are governed by a separate 598 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 599 * status structure to control this. 600 * 601 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 602 * round-to-nearest and is used by any operations (generally 603 * Neon) which the architecture defines as controlled by the 604 * standard FPSCR value rather than the FPSCR. 605 * 606 * To avoid having to transfer exception bits around, we simply 607 * say that the FPSCR cumulative exception flags are the logical 608 * OR of the flags in the three fp statuses. This relies on the 609 * only thing which needs to read the exception flags being 610 * an explicit FPSCR read. 611 */ 612 float_status fp_status; 613 float_status fp_status_f16; 614 float_status standard_fp_status; 615 616 /* ZCR_EL[1-3] */ 617 uint64_t zcr_el[4]; 618 } vfp; 619 uint64_t exclusive_addr; 620 uint64_t exclusive_val; 621 uint64_t exclusive_high; 622 623 /* iwMMXt coprocessor state. */ 624 struct { 625 uint64_t regs[16]; 626 uint64_t val; 627 628 uint32_t cregs[16]; 629 } iwmmxt; 630 631 #ifdef TARGET_AARCH64 632 struct { 633 ARMPACKey apia; 634 ARMPACKey apib; 635 ARMPACKey apda; 636 ARMPACKey apdb; 637 ARMPACKey apga; 638 } keys; 639 #endif 640 641 #if defined(CONFIG_USER_ONLY) 642 /* For usermode syscall translation. */ 643 int eabi; 644 #endif 645 646 struct CPUBreakpoint *cpu_breakpoint[16]; 647 struct CPUWatchpoint *cpu_watchpoint[16]; 648 649 /* Fields up to this point are cleared by a CPU reset */ 650 struct {} end_reset_fields; 651 652 /* Fields after this point are preserved across CPU reset. */ 653 654 /* Internal CPU feature flags. */ 655 uint64_t features; 656 657 /* PMSAv7 MPU */ 658 struct { 659 uint32_t *drbar; 660 uint32_t *drsr; 661 uint32_t *dracr; 662 uint32_t rnr[M_REG_NUM_BANKS]; 663 } pmsav7; 664 665 /* PMSAv8 MPU */ 666 struct { 667 /* The PMSAv8 implementation also shares some PMSAv7 config 668 * and state: 669 * pmsav7.rnr (region number register) 670 * pmsav7_dregion (number of configured regions) 671 */ 672 uint32_t *rbar[M_REG_NUM_BANKS]; 673 uint32_t *rlar[M_REG_NUM_BANKS]; 674 uint32_t mair0[M_REG_NUM_BANKS]; 675 uint32_t mair1[M_REG_NUM_BANKS]; 676 } pmsav8; 677 678 /* v8M SAU */ 679 struct { 680 uint32_t *rbar; 681 uint32_t *rlar; 682 uint32_t rnr; 683 uint32_t ctrl; 684 } sau; 685 686 void *nvic; 687 const struct arm_boot_info *boot_info; 688 /* Store GICv3CPUState to access from this struct */ 689 void *gicv3state; 690 } CPUARMState; 691 692 /** 693 * ARMELChangeHookFn: 694 * type of a function which can be registered via arm_register_el_change_hook() 695 * to get callbacks when the CPU changes its exception level or mode. 696 */ 697 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 698 typedef struct ARMELChangeHook ARMELChangeHook; 699 struct ARMELChangeHook { 700 ARMELChangeHookFn *hook; 701 void *opaque; 702 QLIST_ENTRY(ARMELChangeHook) node; 703 }; 704 705 /* These values map onto the return values for 706 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 707 typedef enum ARMPSCIState { 708 PSCI_ON = 0, 709 PSCI_OFF = 1, 710 PSCI_ON_PENDING = 2 711 } ARMPSCIState; 712 713 typedef struct ARMISARegisters ARMISARegisters; 714 715 /** 716 * ARMCPU: 717 * @env: #CPUARMState 718 * 719 * An ARM CPU core. 720 */ 721 struct ARMCPU { 722 /*< private >*/ 723 CPUState parent_obj; 724 /*< public >*/ 725 726 CPUNegativeOffsetState neg; 727 CPUARMState env; 728 729 /* Coprocessor information */ 730 GHashTable *cp_regs; 731 /* For marshalling (mostly coprocessor) register state between the 732 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 733 * we use these arrays. 734 */ 735 /* List of register indexes managed via these arrays; (full KVM style 736 * 64 bit indexes, not CPRegInfo 32 bit indexes) 737 */ 738 uint64_t *cpreg_indexes; 739 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 740 uint64_t *cpreg_values; 741 /* Length of the indexes, values, reset_values arrays */ 742 int32_t cpreg_array_len; 743 /* These are used only for migration: incoming data arrives in 744 * these fields and is sanity checked in post_load before copying 745 * to the working data structures above. 746 */ 747 uint64_t *cpreg_vmstate_indexes; 748 uint64_t *cpreg_vmstate_values; 749 int32_t cpreg_vmstate_array_len; 750 751 DynamicGDBXMLInfo dyn_xml; 752 753 /* Timers used by the generic (architected) timer */ 754 QEMUTimer *gt_timer[NUM_GTIMERS]; 755 /* 756 * Timer used by the PMU. Its state is restored after migration by 757 * pmu_op_finish() - it does not need other handling during migration 758 */ 759 QEMUTimer *pmu_timer; 760 /* GPIO outputs for generic timer */ 761 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 762 /* GPIO output for GICv3 maintenance interrupt signal */ 763 qemu_irq gicv3_maintenance_interrupt; 764 /* GPIO output for the PMU interrupt */ 765 qemu_irq pmu_interrupt; 766 767 /* MemoryRegion to use for secure physical accesses */ 768 MemoryRegion *secure_memory; 769 770 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 771 Object *idau; 772 773 /* 'compatible' string for this CPU for Linux device trees */ 774 const char *dtb_compatible; 775 776 /* PSCI version for this CPU 777 * Bits[31:16] = Major Version 778 * Bits[15:0] = Minor Version 779 */ 780 uint32_t psci_version; 781 782 /* Should CPU start in PSCI powered-off state? */ 783 bool start_powered_off; 784 785 /* Current power state, access guarded by BQL */ 786 ARMPSCIState power_state; 787 788 /* CPU has virtualization extension */ 789 bool has_el2; 790 /* CPU has security extension */ 791 bool has_el3; 792 /* CPU has PMU (Performance Monitor Unit) */ 793 bool has_pmu; 794 /* CPU has VFP */ 795 bool has_vfp; 796 /* CPU has Neon */ 797 bool has_neon; 798 /* CPU has M-profile DSP extension */ 799 bool has_dsp; 800 801 /* CPU has memory protection unit */ 802 bool has_mpu; 803 /* PMSAv7 MPU number of supported regions */ 804 uint32_t pmsav7_dregion; 805 /* v8M SAU number of supported regions */ 806 uint32_t sau_sregion; 807 808 /* PSCI conduit used to invoke PSCI methods 809 * 0 - disabled, 1 - smc, 2 - hvc 810 */ 811 uint32_t psci_conduit; 812 813 /* For v8M, initial value of the Secure VTOR */ 814 uint32_t init_svtor; 815 816 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 817 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 818 */ 819 uint32_t kvm_target; 820 821 /* KVM init features for this CPU */ 822 uint32_t kvm_init_features[7]; 823 824 /* Uniprocessor system with MP extensions */ 825 bool mp_is_up; 826 827 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 828 * and the probe failed (so we need to report the error in realize) 829 */ 830 bool host_cpu_probe_failed; 831 832 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 833 * register. 834 */ 835 int32_t core_count; 836 837 /* The instance init functions for implementation-specific subclasses 838 * set these fields to specify the implementation-dependent values of 839 * various constant registers and reset values of non-constant 840 * registers. 841 * Some of these might become QOM properties eventually. 842 * Field names match the official register names as defined in the 843 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 844 * is used for reset values of non-constant registers; no reset_ 845 * prefix means a constant register. 846 * Some of these registers are split out into a substructure that 847 * is shared with the translators to control the ISA. 848 */ 849 struct ARMISARegisters { 850 uint32_t id_isar0; 851 uint32_t id_isar1; 852 uint32_t id_isar2; 853 uint32_t id_isar3; 854 uint32_t id_isar4; 855 uint32_t id_isar5; 856 uint32_t id_isar6; 857 uint32_t mvfr0; 858 uint32_t mvfr1; 859 uint32_t mvfr2; 860 uint64_t id_aa64isar0; 861 uint64_t id_aa64isar1; 862 uint64_t id_aa64pfr0; 863 uint64_t id_aa64pfr1; 864 uint64_t id_aa64mmfr0; 865 uint64_t id_aa64mmfr1; 866 } isar; 867 uint32_t midr; 868 uint32_t revidr; 869 uint32_t reset_fpsid; 870 uint32_t ctr; 871 uint32_t reset_sctlr; 872 uint32_t id_pfr0; 873 uint32_t id_pfr1; 874 uint32_t id_dfr0; 875 uint64_t pmceid0; 876 uint64_t pmceid1; 877 uint32_t id_afr0; 878 uint32_t id_mmfr0; 879 uint32_t id_mmfr1; 880 uint32_t id_mmfr2; 881 uint32_t id_mmfr3; 882 uint32_t id_mmfr4; 883 uint64_t id_aa64dfr0; 884 uint64_t id_aa64dfr1; 885 uint64_t id_aa64afr0; 886 uint64_t id_aa64afr1; 887 uint32_t dbgdidr; 888 uint32_t clidr; 889 uint64_t mp_affinity; /* MP ID without feature bits */ 890 /* The elements of this array are the CCSIDR values for each cache, 891 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 892 */ 893 uint32_t ccsidr[16]; 894 uint64_t reset_cbar; 895 uint32_t reset_auxcr; 896 bool reset_hivecs; 897 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 898 uint32_t dcz_blocksize; 899 uint64_t rvbar; 900 901 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 902 int gic_num_lrs; /* number of list registers */ 903 int gic_vpribits; /* number of virtual priority bits */ 904 int gic_vprebits; /* number of virtual preemption bits */ 905 906 /* Whether the cfgend input is high (i.e. this CPU should reset into 907 * big-endian mode). This setting isn't used directly: instead it modifies 908 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 909 * architecture version. 910 */ 911 bool cfgend; 912 913 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 914 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 915 916 int32_t node_id; /* NUMA node this CPU belongs to */ 917 918 /* Used to synchronize KVM and QEMU in-kernel device levels */ 919 uint8_t device_irq_level; 920 921 /* Used to set the maximum vector length the cpu will support. */ 922 uint32_t sve_max_vq; 923 924 /* 925 * In sve_vq_map each set bit is a supported vector length of 926 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 927 * length in quadwords. 928 * 929 * While processing properties during initialization, corresponding 930 * sve_vq_init bits are set for bits in sve_vq_map that have been 931 * set by properties. 932 */ 933 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 934 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 935 }; 936 937 void arm_cpu_post_init(Object *obj); 938 939 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 940 941 #ifndef CONFIG_USER_ONLY 942 extern const VMStateDescription vmstate_arm_cpu; 943 #endif 944 945 void arm_cpu_do_interrupt(CPUState *cpu); 946 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 947 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 948 949 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 950 MemTxAttrs *attrs); 951 952 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 953 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 954 955 /* Dynamically generates for gdb stub an XML description of the sysregs from 956 * the cp_regs hashtable. Returns the registered sysregs number. 957 */ 958 int arm_gen_dynamic_xml(CPUState *cpu); 959 960 /* Returns the dynamically generated XML for the gdb stub. 961 * Returns a pointer to the XML contents for the specified XML file or NULL 962 * if the XML name doesn't match the predefined one. 963 */ 964 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 965 966 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 967 int cpuid, void *opaque); 968 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 969 int cpuid, void *opaque); 970 971 #ifdef TARGET_AARCH64 972 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 973 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 974 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 975 void aarch64_sve_change_el(CPUARMState *env, int old_el, 976 int new_el, bool el0_a64); 977 void aarch64_add_sve_properties(Object *obj); 978 #else 979 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 980 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 981 int n, bool a) 982 { } 983 static inline void aarch64_add_sve_properties(Object *obj) { } 984 #endif 985 986 #if !defined(CONFIG_TCG) 987 static inline target_ulong do_arm_semihosting(CPUARMState *env) 988 { 989 g_assert_not_reached(); 990 } 991 #else 992 target_ulong do_arm_semihosting(CPUARMState *env); 993 #endif 994 void aarch64_sync_32_to_64(CPUARMState *env); 995 void aarch64_sync_64_to_32(CPUARMState *env); 996 997 int fp_exception_el(CPUARMState *env, int cur_el); 998 int sve_exception_el(CPUARMState *env, int cur_el); 999 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1000 1001 static inline bool is_a64(CPUARMState *env) 1002 { 1003 return env->aarch64; 1004 } 1005 1006 /* you can call this signal handler from your SIGBUS and SIGSEGV 1007 signal handlers to inform the virtual CPU of exceptions. non zero 1008 is returned if the signal was handled by the virtual CPU. */ 1009 int cpu_arm_signal_handler(int host_signum, void *pinfo, 1010 void *puc); 1011 1012 /** 1013 * pmu_op_start/finish 1014 * @env: CPUARMState 1015 * 1016 * Convert all PMU counters between their delta form (the typical mode when 1017 * they are enabled) and the guest-visible values. These two calls must 1018 * surround any action which might affect the counters. 1019 */ 1020 void pmu_op_start(CPUARMState *env); 1021 void pmu_op_finish(CPUARMState *env); 1022 1023 /* 1024 * Called when a PMU counter is due to overflow 1025 */ 1026 void arm_pmu_timer_cb(void *opaque); 1027 1028 /** 1029 * Functions to register as EL change hooks for PMU mode filtering 1030 */ 1031 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1032 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1033 1034 /* 1035 * pmu_init 1036 * @cpu: ARMCPU 1037 * 1038 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1039 * for the current configuration 1040 */ 1041 void pmu_init(ARMCPU *cpu); 1042 1043 /* SCTLR bit meanings. Several bits have been reused in newer 1044 * versions of the architecture; in that case we define constants 1045 * for both old and new bit meanings. Code which tests against those 1046 * bits should probably check or otherwise arrange that the CPU 1047 * is the architectural version it expects. 1048 */ 1049 #define SCTLR_M (1U << 0) 1050 #define SCTLR_A (1U << 1) 1051 #define SCTLR_C (1U << 2) 1052 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1053 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1054 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1055 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1056 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1057 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1058 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1059 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1060 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1061 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1062 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1063 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1064 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1065 #define SCTLR_SED (1U << 8) /* v8 onward */ 1066 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1067 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1068 #define SCTLR_F (1U << 10) /* up to v6 */ 1069 #define SCTLR_SW (1U << 10) /* v7 */ 1070 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1071 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1072 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1073 #define SCTLR_I (1U << 12) 1074 #define SCTLR_V (1U << 13) /* AArch32 only */ 1075 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1076 #define SCTLR_RR (1U << 14) /* up to v7 */ 1077 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1078 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1079 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1080 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1081 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1082 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1083 #define SCTLR_BR (1U << 17) /* PMSA only */ 1084 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1085 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1086 #define SCTLR_WXN (1U << 19) 1087 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1088 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1089 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1090 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1091 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1092 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1093 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1094 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1095 #define SCTLR_VE (1U << 24) /* up to v7 */ 1096 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1097 #define SCTLR_EE (1U << 25) 1098 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1099 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1100 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1101 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1102 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1103 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1104 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1105 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1106 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1107 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1108 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1109 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1110 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1111 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1112 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1113 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1114 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1115 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1116 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1117 1118 #define CPTR_TCPAC (1U << 31) 1119 #define CPTR_TTA (1U << 20) 1120 #define CPTR_TFP (1U << 10) 1121 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1122 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1123 1124 #define MDCR_EPMAD (1U << 21) 1125 #define MDCR_EDAD (1U << 20) 1126 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1127 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1128 #define MDCR_SDD (1U << 16) 1129 #define MDCR_SPD (3U << 14) 1130 #define MDCR_TDRA (1U << 11) 1131 #define MDCR_TDOSA (1U << 10) 1132 #define MDCR_TDA (1U << 9) 1133 #define MDCR_TDE (1U << 8) 1134 #define MDCR_HPME (1U << 7) 1135 #define MDCR_TPM (1U << 6) 1136 #define MDCR_TPMCR (1U << 5) 1137 #define MDCR_HPMN (0x1fU) 1138 1139 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1140 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1141 1142 #define CPSR_M (0x1fU) 1143 #define CPSR_T (1U << 5) 1144 #define CPSR_F (1U << 6) 1145 #define CPSR_I (1U << 7) 1146 #define CPSR_A (1U << 8) 1147 #define CPSR_E (1U << 9) 1148 #define CPSR_IT_2_7 (0xfc00U) 1149 #define CPSR_GE (0xfU << 16) 1150 #define CPSR_IL (1U << 20) 1151 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 1152 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 1153 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 1154 * where it is live state but not accessible to the AArch32 code. 1155 */ 1156 #define CPSR_RESERVED (0x7U << 21) 1157 #define CPSR_J (1U << 24) 1158 #define CPSR_IT_0_1 (3U << 25) 1159 #define CPSR_Q (1U << 27) 1160 #define CPSR_V (1U << 28) 1161 #define CPSR_C (1U << 29) 1162 #define CPSR_Z (1U << 30) 1163 #define CPSR_N (1U << 31) 1164 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1165 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1166 1167 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1168 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1169 | CPSR_NZCV) 1170 /* Bits writable in user mode. */ 1171 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1172 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1173 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1174 /* Mask of bits which may be set by exception return copying them from SPSR */ 1175 #define CPSR_ERET_MASK (~CPSR_RESERVED) 1176 1177 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1178 #define XPSR_EXCP 0x1ffU 1179 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1180 #define XPSR_IT_2_7 CPSR_IT_2_7 1181 #define XPSR_GE CPSR_GE 1182 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1183 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1184 #define XPSR_IT_0_1 CPSR_IT_0_1 1185 #define XPSR_Q CPSR_Q 1186 #define XPSR_V CPSR_V 1187 #define XPSR_C CPSR_C 1188 #define XPSR_Z CPSR_Z 1189 #define XPSR_N CPSR_N 1190 #define XPSR_NZCV CPSR_NZCV 1191 #define XPSR_IT CPSR_IT 1192 1193 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1194 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1195 #define TTBCR_PD0 (1U << 4) 1196 #define TTBCR_PD1 (1U << 5) 1197 #define TTBCR_EPD0 (1U << 7) 1198 #define TTBCR_IRGN0 (3U << 8) 1199 #define TTBCR_ORGN0 (3U << 10) 1200 #define TTBCR_SH0 (3U << 12) 1201 #define TTBCR_T1SZ (3U << 16) 1202 #define TTBCR_A1 (1U << 22) 1203 #define TTBCR_EPD1 (1U << 23) 1204 #define TTBCR_IRGN1 (3U << 24) 1205 #define TTBCR_ORGN1 (3U << 26) 1206 #define TTBCR_SH1 (1U << 28) 1207 #define TTBCR_EAE (1U << 31) 1208 1209 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1210 * Only these are valid when in AArch64 mode; in 1211 * AArch32 mode SPSRs are basically CPSR-format. 1212 */ 1213 #define PSTATE_SP (1U) 1214 #define PSTATE_M (0xFU) 1215 #define PSTATE_nRW (1U << 4) 1216 #define PSTATE_F (1U << 6) 1217 #define PSTATE_I (1U << 7) 1218 #define PSTATE_A (1U << 8) 1219 #define PSTATE_D (1U << 9) 1220 #define PSTATE_BTYPE (3U << 10) 1221 #define PSTATE_IL (1U << 20) 1222 #define PSTATE_SS (1U << 21) 1223 #define PSTATE_V (1U << 28) 1224 #define PSTATE_C (1U << 29) 1225 #define PSTATE_Z (1U << 30) 1226 #define PSTATE_N (1U << 31) 1227 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1228 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1229 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1230 /* Mode values for AArch64 */ 1231 #define PSTATE_MODE_EL3h 13 1232 #define PSTATE_MODE_EL3t 12 1233 #define PSTATE_MODE_EL2h 9 1234 #define PSTATE_MODE_EL2t 8 1235 #define PSTATE_MODE_EL1h 5 1236 #define PSTATE_MODE_EL1t 4 1237 #define PSTATE_MODE_EL0t 0 1238 1239 /* Write a new value to v7m.exception, thus transitioning into or out 1240 * of Handler mode; this may result in a change of active stack pointer. 1241 */ 1242 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1243 1244 /* Map EL and handler into a PSTATE_MODE. */ 1245 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1246 { 1247 return (el << 2) | handler; 1248 } 1249 1250 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1251 * interprocessing, so we don't attempt to sync with the cpsr state used by 1252 * the 32 bit decoder. 1253 */ 1254 static inline uint32_t pstate_read(CPUARMState *env) 1255 { 1256 int ZF; 1257 1258 ZF = (env->ZF == 0); 1259 return (env->NF & 0x80000000) | (ZF << 30) 1260 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1261 | env->pstate | env->daif | (env->btype << 10); 1262 } 1263 1264 static inline void pstate_write(CPUARMState *env, uint32_t val) 1265 { 1266 env->ZF = (~val) & PSTATE_Z; 1267 env->NF = val; 1268 env->CF = (val >> 29) & 1; 1269 env->VF = (val << 3) & 0x80000000; 1270 env->daif = val & PSTATE_DAIF; 1271 env->btype = (val >> 10) & 3; 1272 env->pstate = val & ~CACHED_PSTATE_BITS; 1273 } 1274 1275 /* Return the current CPSR value. */ 1276 uint32_t cpsr_read(CPUARMState *env); 1277 1278 typedef enum CPSRWriteType { 1279 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1280 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1281 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1282 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1283 } CPSRWriteType; 1284 1285 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1286 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1287 CPSRWriteType write_type); 1288 1289 /* Return the current xPSR value. */ 1290 static inline uint32_t xpsr_read(CPUARMState *env) 1291 { 1292 int ZF; 1293 ZF = (env->ZF == 0); 1294 return (env->NF & 0x80000000) | (ZF << 30) 1295 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1296 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1297 | ((env->condexec_bits & 0xfc) << 8) 1298 | (env->GE << 16) 1299 | env->v7m.exception; 1300 } 1301 1302 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1303 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1304 { 1305 if (mask & XPSR_NZCV) { 1306 env->ZF = (~val) & XPSR_Z; 1307 env->NF = val; 1308 env->CF = (val >> 29) & 1; 1309 env->VF = (val << 3) & 0x80000000; 1310 } 1311 if (mask & XPSR_Q) { 1312 env->QF = ((val & XPSR_Q) != 0); 1313 } 1314 if (mask & XPSR_GE) { 1315 env->GE = (val & XPSR_GE) >> 16; 1316 } 1317 #ifndef CONFIG_USER_ONLY 1318 if (mask & XPSR_T) { 1319 env->thumb = ((val & XPSR_T) != 0); 1320 } 1321 if (mask & XPSR_IT_0_1) { 1322 env->condexec_bits &= ~3; 1323 env->condexec_bits |= (val >> 25) & 3; 1324 } 1325 if (mask & XPSR_IT_2_7) { 1326 env->condexec_bits &= 3; 1327 env->condexec_bits |= (val >> 8) & 0xfc; 1328 } 1329 if (mask & XPSR_EXCP) { 1330 /* Note that this only happens on exception exit */ 1331 write_v7m_exception(env, val & XPSR_EXCP); 1332 } 1333 #endif 1334 } 1335 1336 #define HCR_VM (1ULL << 0) 1337 #define HCR_SWIO (1ULL << 1) 1338 #define HCR_PTW (1ULL << 2) 1339 #define HCR_FMO (1ULL << 3) 1340 #define HCR_IMO (1ULL << 4) 1341 #define HCR_AMO (1ULL << 5) 1342 #define HCR_VF (1ULL << 6) 1343 #define HCR_VI (1ULL << 7) 1344 #define HCR_VSE (1ULL << 8) 1345 #define HCR_FB (1ULL << 9) 1346 #define HCR_BSU_MASK (3ULL << 10) 1347 #define HCR_DC (1ULL << 12) 1348 #define HCR_TWI (1ULL << 13) 1349 #define HCR_TWE (1ULL << 14) 1350 #define HCR_TID0 (1ULL << 15) 1351 #define HCR_TID1 (1ULL << 16) 1352 #define HCR_TID2 (1ULL << 17) 1353 #define HCR_TID3 (1ULL << 18) 1354 #define HCR_TSC (1ULL << 19) 1355 #define HCR_TIDCP (1ULL << 20) 1356 #define HCR_TACR (1ULL << 21) 1357 #define HCR_TSW (1ULL << 22) 1358 #define HCR_TPCP (1ULL << 23) 1359 #define HCR_TPU (1ULL << 24) 1360 #define HCR_TTLB (1ULL << 25) 1361 #define HCR_TVM (1ULL << 26) 1362 #define HCR_TGE (1ULL << 27) 1363 #define HCR_TDZ (1ULL << 28) 1364 #define HCR_HCD (1ULL << 29) 1365 #define HCR_TRVM (1ULL << 30) 1366 #define HCR_RW (1ULL << 31) 1367 #define HCR_CD (1ULL << 32) 1368 #define HCR_ID (1ULL << 33) 1369 #define HCR_E2H (1ULL << 34) 1370 #define HCR_TLOR (1ULL << 35) 1371 #define HCR_TERR (1ULL << 36) 1372 #define HCR_TEA (1ULL << 37) 1373 #define HCR_MIOCNCE (1ULL << 38) 1374 #define HCR_APK (1ULL << 40) 1375 #define HCR_API (1ULL << 41) 1376 #define HCR_NV (1ULL << 42) 1377 #define HCR_NV1 (1ULL << 43) 1378 #define HCR_AT (1ULL << 44) 1379 #define HCR_NV2 (1ULL << 45) 1380 #define HCR_FWB (1ULL << 46) 1381 #define HCR_FIEN (1ULL << 47) 1382 #define HCR_TID4 (1ULL << 49) 1383 #define HCR_TICAB (1ULL << 50) 1384 #define HCR_TOCU (1ULL << 52) 1385 #define HCR_TTLBIS (1ULL << 54) 1386 #define HCR_TTLBOS (1ULL << 55) 1387 #define HCR_ATA (1ULL << 56) 1388 #define HCR_DCT (1ULL << 57) 1389 1390 /* 1391 * When we actually implement ARMv8.1-VHE we should add HCR_E2H to 1392 * HCR_MASK and then clear it again if the feature bit is not set in 1393 * hcr_write(). 1394 */ 1395 #define HCR_MASK ((1ULL << 34) - 1) 1396 1397 #define SCR_NS (1U << 0) 1398 #define SCR_IRQ (1U << 1) 1399 #define SCR_FIQ (1U << 2) 1400 #define SCR_EA (1U << 3) 1401 #define SCR_FW (1U << 4) 1402 #define SCR_AW (1U << 5) 1403 #define SCR_NET (1U << 6) 1404 #define SCR_SMD (1U << 7) 1405 #define SCR_HCE (1U << 8) 1406 #define SCR_SIF (1U << 9) 1407 #define SCR_RW (1U << 10) 1408 #define SCR_ST (1U << 11) 1409 #define SCR_TWI (1U << 12) 1410 #define SCR_TWE (1U << 13) 1411 #define SCR_TLOR (1U << 14) 1412 #define SCR_TERR (1U << 15) 1413 #define SCR_APK (1U << 16) 1414 #define SCR_API (1U << 17) 1415 #define SCR_EEL2 (1U << 18) 1416 #define SCR_EASE (1U << 19) 1417 #define SCR_NMEA (1U << 20) 1418 #define SCR_FIEN (1U << 21) 1419 #define SCR_ENSCXT (1U << 25) 1420 #define SCR_ATA (1U << 26) 1421 1422 /* Return the current FPSCR value. */ 1423 uint32_t vfp_get_fpscr(CPUARMState *env); 1424 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1425 1426 /* FPCR, Floating Point Control Register 1427 * FPSR, Floating Poiht Status Register 1428 * 1429 * For A64 the FPSCR is split into two logically distinct registers, 1430 * FPCR and FPSR. However since they still use non-overlapping bits 1431 * we store the underlying state in fpscr and just mask on read/write. 1432 */ 1433 #define FPSR_MASK 0xf800009f 1434 #define FPCR_MASK 0x07ff9f00 1435 1436 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1437 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1438 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1439 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1440 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1441 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1442 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1443 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1444 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1445 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1446 1447 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1448 { 1449 return vfp_get_fpscr(env) & FPSR_MASK; 1450 } 1451 1452 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1453 { 1454 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1455 vfp_set_fpscr(env, new_fpscr); 1456 } 1457 1458 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1459 { 1460 return vfp_get_fpscr(env) & FPCR_MASK; 1461 } 1462 1463 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1464 { 1465 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1466 vfp_set_fpscr(env, new_fpscr); 1467 } 1468 1469 enum arm_cpu_mode { 1470 ARM_CPU_MODE_USR = 0x10, 1471 ARM_CPU_MODE_FIQ = 0x11, 1472 ARM_CPU_MODE_IRQ = 0x12, 1473 ARM_CPU_MODE_SVC = 0x13, 1474 ARM_CPU_MODE_MON = 0x16, 1475 ARM_CPU_MODE_ABT = 0x17, 1476 ARM_CPU_MODE_HYP = 0x1a, 1477 ARM_CPU_MODE_UND = 0x1b, 1478 ARM_CPU_MODE_SYS = 0x1f 1479 }; 1480 1481 /* VFP system registers. */ 1482 #define ARM_VFP_FPSID 0 1483 #define ARM_VFP_FPSCR 1 1484 #define ARM_VFP_MVFR2 5 1485 #define ARM_VFP_MVFR1 6 1486 #define ARM_VFP_MVFR0 7 1487 #define ARM_VFP_FPEXC 8 1488 #define ARM_VFP_FPINST 9 1489 #define ARM_VFP_FPINST2 10 1490 1491 /* iwMMXt coprocessor control registers. */ 1492 #define ARM_IWMMXT_wCID 0 1493 #define ARM_IWMMXT_wCon 1 1494 #define ARM_IWMMXT_wCSSF 2 1495 #define ARM_IWMMXT_wCASF 3 1496 #define ARM_IWMMXT_wCGR0 8 1497 #define ARM_IWMMXT_wCGR1 9 1498 #define ARM_IWMMXT_wCGR2 10 1499 #define ARM_IWMMXT_wCGR3 11 1500 1501 /* V7M CCR bits */ 1502 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1503 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1504 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1505 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1506 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1507 FIELD(V7M_CCR, STKALIGN, 9, 1) 1508 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1509 FIELD(V7M_CCR, DC, 16, 1) 1510 FIELD(V7M_CCR, IC, 17, 1) 1511 FIELD(V7M_CCR, BP, 18, 1) 1512 1513 /* V7M SCR bits */ 1514 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1515 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1516 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1517 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1518 1519 /* V7M AIRCR bits */ 1520 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1521 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1522 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1523 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1524 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1525 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1526 FIELD(V7M_AIRCR, PRIS, 14, 1) 1527 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1528 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1529 1530 /* V7M CFSR bits for MMFSR */ 1531 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1532 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1533 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1534 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1535 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1536 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1537 1538 /* V7M CFSR bits for BFSR */ 1539 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1540 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1541 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1542 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1543 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1544 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1545 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1546 1547 /* V7M CFSR bits for UFSR */ 1548 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1549 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1550 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1551 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1552 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1553 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1554 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1555 1556 /* V7M CFSR bit masks covering all of the subregister bits */ 1557 FIELD(V7M_CFSR, MMFSR, 0, 8) 1558 FIELD(V7M_CFSR, BFSR, 8, 8) 1559 FIELD(V7M_CFSR, UFSR, 16, 16) 1560 1561 /* V7M HFSR bits */ 1562 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1563 FIELD(V7M_HFSR, FORCED, 30, 1) 1564 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1565 1566 /* V7M DFSR bits */ 1567 FIELD(V7M_DFSR, HALTED, 0, 1) 1568 FIELD(V7M_DFSR, BKPT, 1, 1) 1569 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1570 FIELD(V7M_DFSR, VCATCH, 3, 1) 1571 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1572 1573 /* V7M SFSR bits */ 1574 FIELD(V7M_SFSR, INVEP, 0, 1) 1575 FIELD(V7M_SFSR, INVIS, 1, 1) 1576 FIELD(V7M_SFSR, INVER, 2, 1) 1577 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1578 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1579 FIELD(V7M_SFSR, LSPERR, 5, 1) 1580 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1581 FIELD(V7M_SFSR, LSERR, 7, 1) 1582 1583 /* v7M MPU_CTRL bits */ 1584 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1585 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1586 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1587 1588 /* v7M CLIDR bits */ 1589 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1590 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1591 FIELD(V7M_CLIDR, LOC, 24, 3) 1592 FIELD(V7M_CLIDR, LOUU, 27, 3) 1593 FIELD(V7M_CLIDR, ICB, 30, 2) 1594 1595 FIELD(V7M_CSSELR, IND, 0, 1) 1596 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1597 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1598 * define a mask for this and check that it doesn't permit running off 1599 * the end of the array. 1600 */ 1601 FIELD(V7M_CSSELR, INDEX, 0, 4) 1602 1603 /* v7M FPCCR bits */ 1604 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1605 FIELD(V7M_FPCCR, USER, 1, 1) 1606 FIELD(V7M_FPCCR, S, 2, 1) 1607 FIELD(V7M_FPCCR, THREAD, 3, 1) 1608 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1609 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1610 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1611 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1612 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1613 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1614 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1615 FIELD(V7M_FPCCR, RES0, 11, 15) 1616 FIELD(V7M_FPCCR, TS, 26, 1) 1617 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1618 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1619 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1620 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1621 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1622 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1623 #define R_V7M_FPCCR_BANKED_MASK \ 1624 (R_V7M_FPCCR_LSPACT_MASK | \ 1625 R_V7M_FPCCR_USER_MASK | \ 1626 R_V7M_FPCCR_THREAD_MASK | \ 1627 R_V7M_FPCCR_MMRDY_MASK | \ 1628 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1629 R_V7M_FPCCR_UFRDY_MASK | \ 1630 R_V7M_FPCCR_ASPEN_MASK) 1631 1632 /* 1633 * System register ID fields. 1634 */ 1635 FIELD(MIDR_EL1, REVISION, 0, 4) 1636 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1637 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1638 FIELD(MIDR_EL1, VARIANT, 20, 4) 1639 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1640 1641 FIELD(ID_ISAR0, SWAP, 0, 4) 1642 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1643 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1644 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1645 FIELD(ID_ISAR0, COPROC, 16, 4) 1646 FIELD(ID_ISAR0, DEBUG, 20, 4) 1647 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1648 1649 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1650 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1651 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1652 FIELD(ID_ISAR1, EXTEND, 12, 4) 1653 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1654 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1655 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1656 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1657 1658 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1659 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1660 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1661 FIELD(ID_ISAR2, MULT, 12, 4) 1662 FIELD(ID_ISAR2, MULTS, 16, 4) 1663 FIELD(ID_ISAR2, MULTU, 20, 4) 1664 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1665 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1666 1667 FIELD(ID_ISAR3, SATURATE, 0, 4) 1668 FIELD(ID_ISAR3, SIMD, 4, 4) 1669 FIELD(ID_ISAR3, SVC, 8, 4) 1670 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1671 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1672 FIELD(ID_ISAR3, T32COPY, 20, 4) 1673 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1674 FIELD(ID_ISAR3, T32EE, 28, 4) 1675 1676 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1677 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1678 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1679 FIELD(ID_ISAR4, SMC, 12, 4) 1680 FIELD(ID_ISAR4, BARRIER, 16, 4) 1681 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1682 FIELD(ID_ISAR4, PSR_M, 24, 4) 1683 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1684 1685 FIELD(ID_ISAR5, SEVL, 0, 4) 1686 FIELD(ID_ISAR5, AES, 4, 4) 1687 FIELD(ID_ISAR5, SHA1, 8, 4) 1688 FIELD(ID_ISAR5, SHA2, 12, 4) 1689 FIELD(ID_ISAR5, CRC32, 16, 4) 1690 FIELD(ID_ISAR5, RDM, 24, 4) 1691 FIELD(ID_ISAR5, VCMA, 28, 4) 1692 1693 FIELD(ID_ISAR6, JSCVT, 0, 4) 1694 FIELD(ID_ISAR6, DP, 4, 4) 1695 FIELD(ID_ISAR6, FHM, 8, 4) 1696 FIELD(ID_ISAR6, SB, 12, 4) 1697 FIELD(ID_ISAR6, SPECRES, 16, 4) 1698 1699 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1700 FIELD(ID_MMFR4, AC2, 4, 4) 1701 FIELD(ID_MMFR4, XNX, 8, 4) 1702 FIELD(ID_MMFR4, CNP, 12, 4) 1703 FIELD(ID_MMFR4, HPDS, 16, 4) 1704 FIELD(ID_MMFR4, LSM, 20, 4) 1705 FIELD(ID_MMFR4, CCIDX, 24, 4) 1706 FIELD(ID_MMFR4, EVT, 28, 4) 1707 1708 FIELD(ID_AA64ISAR0, AES, 4, 4) 1709 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1710 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1711 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1712 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1713 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1714 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1715 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1716 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1717 FIELD(ID_AA64ISAR0, DP, 44, 4) 1718 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1719 FIELD(ID_AA64ISAR0, TS, 52, 4) 1720 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1721 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1722 1723 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1724 FIELD(ID_AA64ISAR1, APA, 4, 4) 1725 FIELD(ID_AA64ISAR1, API, 8, 4) 1726 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1727 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1728 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1729 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1730 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1731 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1732 FIELD(ID_AA64ISAR1, SB, 36, 4) 1733 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1734 1735 FIELD(ID_AA64PFR0, EL0, 0, 4) 1736 FIELD(ID_AA64PFR0, EL1, 4, 4) 1737 FIELD(ID_AA64PFR0, EL2, 8, 4) 1738 FIELD(ID_AA64PFR0, EL3, 12, 4) 1739 FIELD(ID_AA64PFR0, FP, 16, 4) 1740 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1741 FIELD(ID_AA64PFR0, GIC, 24, 4) 1742 FIELD(ID_AA64PFR0, RAS, 28, 4) 1743 FIELD(ID_AA64PFR0, SVE, 32, 4) 1744 1745 FIELD(ID_AA64PFR1, BT, 0, 4) 1746 FIELD(ID_AA64PFR1, SBSS, 4, 4) 1747 FIELD(ID_AA64PFR1, MTE, 8, 4) 1748 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1749 1750 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1751 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1752 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1753 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1754 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1755 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1756 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1757 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1758 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1759 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1760 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1761 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1762 1763 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1764 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1765 FIELD(ID_AA64MMFR1, VH, 8, 4) 1766 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1767 FIELD(ID_AA64MMFR1, LO, 16, 4) 1768 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1769 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1770 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1771 1772 FIELD(ID_DFR0, COPDBG, 0, 4) 1773 FIELD(ID_DFR0, COPSDBG, 4, 4) 1774 FIELD(ID_DFR0, MMAPDBG, 8, 4) 1775 FIELD(ID_DFR0, COPTRC, 12, 4) 1776 FIELD(ID_DFR0, MMAPTRC, 16, 4) 1777 FIELD(ID_DFR0, MPROFDBG, 20, 4) 1778 FIELD(ID_DFR0, PERFMON, 24, 4) 1779 FIELD(ID_DFR0, TRACEFILT, 28, 4) 1780 1781 FIELD(MVFR0, SIMDREG, 0, 4) 1782 FIELD(MVFR0, FPSP, 4, 4) 1783 FIELD(MVFR0, FPDP, 8, 4) 1784 FIELD(MVFR0, FPTRAP, 12, 4) 1785 FIELD(MVFR0, FPDIVIDE, 16, 4) 1786 FIELD(MVFR0, FPSQRT, 20, 4) 1787 FIELD(MVFR0, FPSHVEC, 24, 4) 1788 FIELD(MVFR0, FPROUND, 28, 4) 1789 1790 FIELD(MVFR1, FPFTZ, 0, 4) 1791 FIELD(MVFR1, FPDNAN, 4, 4) 1792 FIELD(MVFR1, SIMDLS, 8, 4) 1793 FIELD(MVFR1, SIMDINT, 12, 4) 1794 FIELD(MVFR1, SIMDSP, 16, 4) 1795 FIELD(MVFR1, SIMDHP, 20, 4) 1796 FIELD(MVFR1, FPHP, 24, 4) 1797 FIELD(MVFR1, SIMDFMAC, 28, 4) 1798 1799 FIELD(MVFR2, SIMDMISC, 0, 4) 1800 FIELD(MVFR2, FPMISC, 4, 4) 1801 1802 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1803 1804 /* If adding a feature bit which corresponds to a Linux ELF 1805 * HWCAP bit, remember to update the feature-bit-to-hwcap 1806 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1807 */ 1808 enum arm_features { 1809 ARM_FEATURE_VFP, 1810 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1811 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1812 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1813 ARM_FEATURE_V6, 1814 ARM_FEATURE_V6K, 1815 ARM_FEATURE_V7, 1816 ARM_FEATURE_THUMB2, 1817 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1818 ARM_FEATURE_VFP3, 1819 ARM_FEATURE_NEON, 1820 ARM_FEATURE_M, /* Microcontroller profile. */ 1821 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1822 ARM_FEATURE_THUMB2EE, 1823 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1824 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1825 ARM_FEATURE_V4T, 1826 ARM_FEATURE_V5, 1827 ARM_FEATURE_STRONGARM, 1828 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1829 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1830 ARM_FEATURE_GENERIC_TIMER, 1831 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1832 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1833 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1834 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1835 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1836 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1837 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1838 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1839 ARM_FEATURE_V8, 1840 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1841 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1842 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1843 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1844 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1845 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1846 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1847 ARM_FEATURE_PMU, /* has PMU support */ 1848 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1849 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1850 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1851 }; 1852 1853 static inline int arm_feature(CPUARMState *env, int feature) 1854 { 1855 return (env->features & (1ULL << feature)) != 0; 1856 } 1857 1858 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 1859 1860 #if !defined(CONFIG_USER_ONLY) 1861 /* Return true if exception levels below EL3 are in secure state, 1862 * or would be following an exception return to that level. 1863 * Unlike arm_is_secure() (which is always a question about the 1864 * _current_ state of the CPU) this doesn't care about the current 1865 * EL or mode. 1866 */ 1867 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1868 { 1869 if (arm_feature(env, ARM_FEATURE_EL3)) { 1870 return !(env->cp15.scr_el3 & SCR_NS); 1871 } else { 1872 /* If EL3 is not supported then the secure state is implementation 1873 * defined, in which case QEMU defaults to non-secure. 1874 */ 1875 return false; 1876 } 1877 } 1878 1879 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1880 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1881 { 1882 if (arm_feature(env, ARM_FEATURE_EL3)) { 1883 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1884 /* CPU currently in AArch64 state and EL3 */ 1885 return true; 1886 } else if (!is_a64(env) && 1887 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1888 /* CPU currently in AArch32 state and monitor mode */ 1889 return true; 1890 } 1891 } 1892 return false; 1893 } 1894 1895 /* Return true if the processor is in secure state */ 1896 static inline bool arm_is_secure(CPUARMState *env) 1897 { 1898 if (arm_is_el3_or_mon(env)) { 1899 return true; 1900 } 1901 return arm_is_secure_below_el3(env); 1902 } 1903 1904 #else 1905 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1906 { 1907 return false; 1908 } 1909 1910 static inline bool arm_is_secure(CPUARMState *env) 1911 { 1912 return false; 1913 } 1914 #endif 1915 1916 /** 1917 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 1918 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 1919 * "for all purposes other than a direct read or write access of HCR_EL2." 1920 * Not included here is HCR_RW. 1921 */ 1922 uint64_t arm_hcr_el2_eff(CPUARMState *env); 1923 1924 /* Return true if the specified exception level is running in AArch64 state. */ 1925 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1926 { 1927 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1928 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1929 */ 1930 assert(el >= 1 && el <= 3); 1931 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1932 1933 /* The highest exception level is always at the maximum supported 1934 * register width, and then lower levels have a register width controlled 1935 * by bits in the SCR or HCR registers. 1936 */ 1937 if (el == 3) { 1938 return aa64; 1939 } 1940 1941 if (arm_feature(env, ARM_FEATURE_EL3)) { 1942 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1943 } 1944 1945 if (el == 2) { 1946 return aa64; 1947 } 1948 1949 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1950 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1951 } 1952 1953 return aa64; 1954 } 1955 1956 /* Function for determing whether guest cp register reads and writes should 1957 * access the secure or non-secure bank of a cp register. When EL3 is 1958 * operating in AArch32 state, the NS-bit determines whether the secure 1959 * instance of a cp register should be used. When EL3 is AArch64 (or if 1960 * it doesn't exist at all) then there is no register banking, and all 1961 * accesses are to the non-secure version. 1962 */ 1963 static inline bool access_secure_reg(CPUARMState *env) 1964 { 1965 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1966 !arm_el_is_aa64(env, 3) && 1967 !(env->cp15.scr_el3 & SCR_NS)); 1968 1969 return ret; 1970 } 1971 1972 /* Macros for accessing a specified CP register bank */ 1973 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1974 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1975 1976 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1977 do { \ 1978 if (_secure) { \ 1979 (_env)->cp15._regname##_s = (_val); \ 1980 } else { \ 1981 (_env)->cp15._regname##_ns = (_val); \ 1982 } \ 1983 } while (0) 1984 1985 /* Macros for automatically accessing a specific CP register bank depending on 1986 * the current secure state of the system. These macros are not intended for 1987 * supporting instruction translation reads/writes as these are dependent 1988 * solely on the SCR.NS bit and not the mode. 1989 */ 1990 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1991 A32_BANKED_REG_GET((_env), _regname, \ 1992 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1993 1994 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1995 A32_BANKED_REG_SET((_env), _regname, \ 1996 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1997 (_val)) 1998 1999 void arm_cpu_list(void); 2000 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2001 uint32_t cur_el, bool secure); 2002 2003 /* Interface between CPU and Interrupt controller. */ 2004 #ifndef CONFIG_USER_ONLY 2005 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2006 #else 2007 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2008 { 2009 return true; 2010 } 2011 #endif 2012 /** 2013 * armv7m_nvic_set_pending: mark the specified exception as pending 2014 * @opaque: the NVIC 2015 * @irq: the exception number to mark pending 2016 * @secure: false for non-banked exceptions or for the nonsecure 2017 * version of a banked exception, true for the secure version of a banked 2018 * exception. 2019 * 2020 * Marks the specified exception as pending. Note that we will assert() 2021 * if @secure is true and @irq does not specify one of the fixed set 2022 * of architecturally banked exceptions. 2023 */ 2024 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2025 /** 2026 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2027 * @opaque: the NVIC 2028 * @irq: the exception number to mark pending 2029 * @secure: false for non-banked exceptions or for the nonsecure 2030 * version of a banked exception, true for the secure version of a banked 2031 * exception. 2032 * 2033 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2034 * exceptions (exceptions generated in the course of trying to take 2035 * a different exception). 2036 */ 2037 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2038 /** 2039 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2040 * @opaque: the NVIC 2041 * @irq: the exception number to mark pending 2042 * @secure: false for non-banked exceptions or for the nonsecure 2043 * version of a banked exception, true for the secure version of a banked 2044 * exception. 2045 * 2046 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2047 * generated in the course of lazy stacking of FP registers. 2048 */ 2049 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2050 /** 2051 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2052 * exception, and whether it targets Secure state 2053 * @opaque: the NVIC 2054 * @pirq: set to pending exception number 2055 * @ptargets_secure: set to whether pending exception targets Secure 2056 * 2057 * This function writes the number of the highest priority pending 2058 * exception (the one which would be made active by 2059 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2060 * to true if the current highest priority pending exception should 2061 * be taken to Secure state, false for NS. 2062 */ 2063 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2064 bool *ptargets_secure); 2065 /** 2066 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2067 * @opaque: the NVIC 2068 * 2069 * Move the current highest priority pending exception from the pending 2070 * state to the active state, and update v7m.exception to indicate that 2071 * it is the exception currently being handled. 2072 */ 2073 void armv7m_nvic_acknowledge_irq(void *opaque); 2074 /** 2075 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2076 * @opaque: the NVIC 2077 * @irq: the exception number to complete 2078 * @secure: true if this exception was secure 2079 * 2080 * Returns: -1 if the irq was not active 2081 * 1 if completing this irq brought us back to base (no active irqs) 2082 * 0 if there is still an irq active after this one was completed 2083 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2084 */ 2085 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2086 /** 2087 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2088 * @opaque: the NVIC 2089 * @irq: the exception number to mark pending 2090 * @secure: false for non-banked exceptions or for the nonsecure 2091 * version of a banked exception, true for the secure version of a banked 2092 * exception. 2093 * 2094 * Return whether an exception is "ready", i.e. whether the exception is 2095 * enabled and is configured at a priority which would allow it to 2096 * interrupt the current execution priority. This controls whether the 2097 * RDY bit for it in the FPCCR is set. 2098 */ 2099 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2100 /** 2101 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2102 * @opaque: the NVIC 2103 * 2104 * Returns: the raw execution priority as defined by the v8M architecture. 2105 * This is the execution priority minus the effects of AIRCR.PRIS, 2106 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2107 * (v8M ARM ARM I_PKLD.) 2108 */ 2109 int armv7m_nvic_raw_execution_priority(void *opaque); 2110 /** 2111 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2112 * priority is negative for the specified security state. 2113 * @opaque: the NVIC 2114 * @secure: the security state to test 2115 * This corresponds to the pseudocode IsReqExecPriNeg(). 2116 */ 2117 #ifndef CONFIG_USER_ONLY 2118 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2119 #else 2120 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2121 { 2122 return false; 2123 } 2124 #endif 2125 2126 /* Interface for defining coprocessor registers. 2127 * Registers are defined in tables of arm_cp_reginfo structs 2128 * which are passed to define_arm_cp_regs(). 2129 */ 2130 2131 /* When looking up a coprocessor register we look for it 2132 * via an integer which encodes all of: 2133 * coprocessor number 2134 * Crn, Crm, opc1, opc2 fields 2135 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2136 * or via MRRC/MCRR?) 2137 * non-secure/secure bank (AArch32 only) 2138 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2139 * (In this case crn and opc2 should be zero.) 2140 * For AArch64, there is no 32/64 bit size distinction; 2141 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2142 * and 4 bit CRn and CRm. The encoding patterns are chosen 2143 * to be easy to convert to and from the KVM encodings, and also 2144 * so that the hashtable can contain both AArch32 and AArch64 2145 * registers (to allow for interprocessing where we might run 2146 * 32 bit code on a 64 bit core). 2147 */ 2148 /* This bit is private to our hashtable cpreg; in KVM register 2149 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2150 * in the upper bits of the 64 bit ID. 2151 */ 2152 #define CP_REG_AA64_SHIFT 28 2153 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2154 2155 /* To enable banking of coprocessor registers depending on ns-bit we 2156 * add a bit to distinguish between secure and non-secure cpregs in the 2157 * hashtable. 2158 */ 2159 #define CP_REG_NS_SHIFT 29 2160 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2161 2162 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2163 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2164 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2165 2166 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2167 (CP_REG_AA64_MASK | \ 2168 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2169 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2170 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2171 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2172 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2173 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2174 2175 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2176 * version used as a key for the coprocessor register hashtable 2177 */ 2178 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2179 { 2180 uint32_t cpregid = kvmid; 2181 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2182 cpregid |= CP_REG_AA64_MASK; 2183 } else { 2184 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2185 cpregid |= (1 << 15); 2186 } 2187 2188 /* KVM is always non-secure so add the NS flag on AArch32 register 2189 * entries. 2190 */ 2191 cpregid |= 1 << CP_REG_NS_SHIFT; 2192 } 2193 return cpregid; 2194 } 2195 2196 /* Convert a truncated 32 bit hashtable key into the full 2197 * 64 bit KVM register ID. 2198 */ 2199 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2200 { 2201 uint64_t kvmid; 2202 2203 if (cpregid & CP_REG_AA64_MASK) { 2204 kvmid = cpregid & ~CP_REG_AA64_MASK; 2205 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2206 } else { 2207 kvmid = cpregid & ~(1 << 15); 2208 if (cpregid & (1 << 15)) { 2209 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2210 } else { 2211 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2212 } 2213 } 2214 return kvmid; 2215 } 2216 2217 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2218 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2219 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2220 * TCG can assume the value to be constant (ie load at translate time) 2221 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2222 * indicates that the TB should not be ended after a write to this register 2223 * (the default is that the TB ends after cp writes). OVERRIDE permits 2224 * a register definition to override a previous definition for the 2225 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2226 * old must have the OVERRIDE bit set. 2227 * ALIAS indicates that this register is an alias view of some underlying 2228 * state which is also visible via another register, and that the other 2229 * register is handling migration and reset; registers marked ALIAS will not be 2230 * migrated but may have their state set by syncing of register state from KVM. 2231 * NO_RAW indicates that this register has no underlying state and does not 2232 * support raw access for state saving/loading; it will not be used for either 2233 * migration or KVM state synchronization. (Typically this is for "registers" 2234 * which are actually used as instructions for cache maintenance and so on.) 2235 * IO indicates that this register does I/O and therefore its accesses 2236 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2237 * registers which implement clocks or timers require this. 2238 * RAISES_EXC is for when the read or write hook might raise an exception; 2239 * the generated code will synchronize the CPU state before calling the hook 2240 * so that it is safe for the hook to call raise_exception(). 2241 */ 2242 #define ARM_CP_SPECIAL 0x0001 2243 #define ARM_CP_CONST 0x0002 2244 #define ARM_CP_64BIT 0x0004 2245 #define ARM_CP_SUPPRESS_TB_END 0x0008 2246 #define ARM_CP_OVERRIDE 0x0010 2247 #define ARM_CP_ALIAS 0x0020 2248 #define ARM_CP_IO 0x0040 2249 #define ARM_CP_NO_RAW 0x0080 2250 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2251 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2252 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2253 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2254 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2255 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2256 #define ARM_CP_FPU 0x1000 2257 #define ARM_CP_SVE 0x2000 2258 #define ARM_CP_NO_GDB 0x4000 2259 #define ARM_CP_RAISES_EXC 0x8000 2260 /* Used only as a terminator for ARMCPRegInfo lists */ 2261 #define ARM_CP_SENTINEL 0xffff 2262 /* Mask of only the flag bits in a type field */ 2263 #define ARM_CP_FLAG_MASK 0xf0ff 2264 2265 /* Valid values for ARMCPRegInfo state field, indicating which of 2266 * the AArch32 and AArch64 execution states this register is visible in. 2267 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2268 * If the reginfo is declared to be visible in both states then a second 2269 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2270 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2271 * Note that we rely on the values of these enums as we iterate through 2272 * the various states in some places. 2273 */ 2274 enum { 2275 ARM_CP_STATE_AA32 = 0, 2276 ARM_CP_STATE_AA64 = 1, 2277 ARM_CP_STATE_BOTH = 2, 2278 }; 2279 2280 /* ARM CP register secure state flags. These flags identify security state 2281 * attributes for a given CP register entry. 2282 * The existence of both or neither secure and non-secure flags indicates that 2283 * the register has both a secure and non-secure hash entry. A single one of 2284 * these flags causes the register to only be hashed for the specified 2285 * security state. 2286 * Although definitions may have any combination of the S/NS bits, each 2287 * registered entry will only have one to identify whether the entry is secure 2288 * or non-secure. 2289 */ 2290 enum { 2291 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2292 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2293 }; 2294 2295 /* Return true if cptype is a valid type field. This is used to try to 2296 * catch errors where the sentinel has been accidentally left off the end 2297 * of a list of registers. 2298 */ 2299 static inline bool cptype_valid(int cptype) 2300 { 2301 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2302 || ((cptype & ARM_CP_SPECIAL) && 2303 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2304 } 2305 2306 /* Access rights: 2307 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2308 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2309 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2310 * (ie any of the privileged modes in Secure state, or Monitor mode). 2311 * If a register is accessible in one privilege level it's always accessible 2312 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2313 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2314 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2315 * terminology a little and call this PL3. 2316 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2317 * with the ELx exception levels. 2318 * 2319 * If access permissions for a register are more complex than can be 2320 * described with these bits, then use a laxer set of restrictions, and 2321 * do the more restrictive/complex check inside a helper function. 2322 */ 2323 #define PL3_R 0x80 2324 #define PL3_W 0x40 2325 #define PL2_R (0x20 | PL3_R) 2326 #define PL2_W (0x10 | PL3_W) 2327 #define PL1_R (0x08 | PL2_R) 2328 #define PL1_W (0x04 | PL2_W) 2329 #define PL0_R (0x02 | PL1_R) 2330 #define PL0_W (0x01 | PL1_W) 2331 2332 /* 2333 * For user-mode some registers are accessible to EL0 via a kernel 2334 * trap-and-emulate ABI. In this case we define the read permissions 2335 * as actually being PL0_R. However some bits of any given register 2336 * may still be masked. 2337 */ 2338 #ifdef CONFIG_USER_ONLY 2339 #define PL0U_R PL0_R 2340 #else 2341 #define PL0U_R PL1_R 2342 #endif 2343 2344 #define PL3_RW (PL3_R | PL3_W) 2345 #define PL2_RW (PL2_R | PL2_W) 2346 #define PL1_RW (PL1_R | PL1_W) 2347 #define PL0_RW (PL0_R | PL0_W) 2348 2349 /* Return the highest implemented Exception Level */ 2350 static inline int arm_highest_el(CPUARMState *env) 2351 { 2352 if (arm_feature(env, ARM_FEATURE_EL3)) { 2353 return 3; 2354 } 2355 if (arm_feature(env, ARM_FEATURE_EL2)) { 2356 return 2; 2357 } 2358 return 1; 2359 } 2360 2361 /* Return true if a v7M CPU is in Handler mode */ 2362 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2363 { 2364 return env->v7m.exception != 0; 2365 } 2366 2367 /* Return the current Exception Level (as per ARMv8; note that this differs 2368 * from the ARMv7 Privilege Level). 2369 */ 2370 static inline int arm_current_el(CPUARMState *env) 2371 { 2372 if (arm_feature(env, ARM_FEATURE_M)) { 2373 return arm_v7m_is_handler_mode(env) || 2374 !(env->v7m.control[env->v7m.secure] & 1); 2375 } 2376 2377 if (is_a64(env)) { 2378 return extract32(env->pstate, 2, 2); 2379 } 2380 2381 switch (env->uncached_cpsr & 0x1f) { 2382 case ARM_CPU_MODE_USR: 2383 return 0; 2384 case ARM_CPU_MODE_HYP: 2385 return 2; 2386 case ARM_CPU_MODE_MON: 2387 return 3; 2388 default: 2389 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2390 /* If EL3 is 32-bit then all secure privileged modes run in 2391 * EL3 2392 */ 2393 return 3; 2394 } 2395 2396 return 1; 2397 } 2398 } 2399 2400 typedef struct ARMCPRegInfo ARMCPRegInfo; 2401 2402 typedef enum CPAccessResult { 2403 /* Access is permitted */ 2404 CP_ACCESS_OK = 0, 2405 /* Access fails due to a configurable trap or enable which would 2406 * result in a categorized exception syndrome giving information about 2407 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2408 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2409 * PL1 if in EL0, otherwise to the current EL). 2410 */ 2411 CP_ACCESS_TRAP = 1, 2412 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2413 * Note that this is not a catch-all case -- the set of cases which may 2414 * result in this failure is specifically defined by the architecture. 2415 */ 2416 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2417 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2418 CP_ACCESS_TRAP_EL2 = 3, 2419 CP_ACCESS_TRAP_EL3 = 4, 2420 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2421 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2422 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2423 /* Access fails and results in an exception syndrome for an FP access, 2424 * trapped directly to EL2 or EL3 2425 */ 2426 CP_ACCESS_TRAP_FP_EL2 = 7, 2427 CP_ACCESS_TRAP_FP_EL3 = 8, 2428 } CPAccessResult; 2429 2430 /* Access functions for coprocessor registers. These cannot fail and 2431 * may not raise exceptions. 2432 */ 2433 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2434 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2435 uint64_t value); 2436 /* Access permission check functions for coprocessor registers. */ 2437 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2438 const ARMCPRegInfo *opaque, 2439 bool isread); 2440 /* Hook function for register reset */ 2441 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2442 2443 #define CP_ANY 0xff 2444 2445 /* Definition of an ARM coprocessor register */ 2446 struct ARMCPRegInfo { 2447 /* Name of register (useful mainly for debugging, need not be unique) */ 2448 const char *name; 2449 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2450 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2451 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2452 * will be decoded to this register. The register read and write 2453 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2454 * used by the program, so it is possible to register a wildcard and 2455 * then behave differently on read/write if necessary. 2456 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2457 * must both be zero. 2458 * For AArch64-visible registers, opc0 is also used. 2459 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2460 * way to distinguish (for KVM's benefit) guest-visible system registers 2461 * from demuxed ones provided to preserve the "no side effects on 2462 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2463 * visible (to match KVM's encoding); cp==0 will be converted to 2464 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2465 */ 2466 uint8_t cp; 2467 uint8_t crn; 2468 uint8_t crm; 2469 uint8_t opc0; 2470 uint8_t opc1; 2471 uint8_t opc2; 2472 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2473 int state; 2474 /* Register type: ARM_CP_* bits/values */ 2475 int type; 2476 /* Access rights: PL*_[RW] */ 2477 int access; 2478 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2479 int secure; 2480 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2481 * this register was defined: can be used to hand data through to the 2482 * register read/write functions, since they are passed the ARMCPRegInfo*. 2483 */ 2484 void *opaque; 2485 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2486 * fieldoffset is non-zero, the reset value of the register. 2487 */ 2488 uint64_t resetvalue; 2489 /* Offset of the field in CPUARMState for this register. 2490 * 2491 * This is not needed if either: 2492 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2493 * 2. both readfn and writefn are specified 2494 */ 2495 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2496 2497 /* Offsets of the secure and non-secure fields in CPUARMState for the 2498 * register if it is banked. These fields are only used during the static 2499 * registration of a register. During hashing the bank associated 2500 * with a given security state is copied to fieldoffset which is used from 2501 * there on out. 2502 * 2503 * It is expected that register definitions use either fieldoffset or 2504 * bank_fieldoffsets in the definition but not both. It is also expected 2505 * that both bank offsets are set when defining a banked register. This 2506 * use indicates that a register is banked. 2507 */ 2508 ptrdiff_t bank_fieldoffsets[2]; 2509 2510 /* Function for making any access checks for this register in addition to 2511 * those specified by the 'access' permissions bits. If NULL, no extra 2512 * checks required. The access check is performed at runtime, not at 2513 * translate time. 2514 */ 2515 CPAccessFn *accessfn; 2516 /* Function for handling reads of this register. If NULL, then reads 2517 * will be done by loading from the offset into CPUARMState specified 2518 * by fieldoffset. 2519 */ 2520 CPReadFn *readfn; 2521 /* Function for handling writes of this register. If NULL, then writes 2522 * will be done by writing to the offset into CPUARMState specified 2523 * by fieldoffset. 2524 */ 2525 CPWriteFn *writefn; 2526 /* Function for doing a "raw" read; used when we need to copy 2527 * coprocessor state to the kernel for KVM or out for 2528 * migration. This only needs to be provided if there is also a 2529 * readfn and it has side effects (for instance clear-on-read bits). 2530 */ 2531 CPReadFn *raw_readfn; 2532 /* Function for doing a "raw" write; used when we need to copy KVM 2533 * kernel coprocessor state into userspace, or for inbound 2534 * migration. This only needs to be provided if there is also a 2535 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2536 * or similar behaviour. 2537 */ 2538 CPWriteFn *raw_writefn; 2539 /* Function for resetting the register. If NULL, then reset will be done 2540 * by writing resetvalue to the field specified in fieldoffset. If 2541 * fieldoffset is 0 then no reset will be done. 2542 */ 2543 CPResetFn *resetfn; 2544 }; 2545 2546 /* Macros which are lvalues for the field in CPUARMState for the 2547 * ARMCPRegInfo *ri. 2548 */ 2549 #define CPREG_FIELD32(env, ri) \ 2550 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2551 #define CPREG_FIELD64(env, ri) \ 2552 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2553 2554 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2555 2556 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2557 const ARMCPRegInfo *regs, void *opaque); 2558 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2559 const ARMCPRegInfo *regs, void *opaque); 2560 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2561 { 2562 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2563 } 2564 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2565 { 2566 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2567 } 2568 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2569 2570 /* 2571 * Definition of an ARM co-processor register as viewed from 2572 * userspace. This is used for presenting sanitised versions of 2573 * registers to userspace when emulating the Linux AArch64 CPU 2574 * ID/feature ABI (advertised as HWCAP_CPUID). 2575 */ 2576 typedef struct ARMCPRegUserSpaceInfo { 2577 /* Name of register */ 2578 const char *name; 2579 2580 /* Is the name actually a glob pattern */ 2581 bool is_glob; 2582 2583 /* Only some bits are exported to user space */ 2584 uint64_t exported_bits; 2585 2586 /* Fixed bits are applied after the mask */ 2587 uint64_t fixed_bits; 2588 } ARMCPRegUserSpaceInfo; 2589 2590 #define REGUSERINFO_SENTINEL { .name = NULL } 2591 2592 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2593 2594 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2595 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2596 uint64_t value); 2597 /* CPReadFn that can be used for read-as-zero behaviour */ 2598 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2599 2600 /* CPResetFn that does nothing, for use if no reset is required even 2601 * if fieldoffset is non zero. 2602 */ 2603 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2604 2605 /* Return true if this reginfo struct's field in the cpu state struct 2606 * is 64 bits wide. 2607 */ 2608 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2609 { 2610 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2611 } 2612 2613 static inline bool cp_access_ok(int current_el, 2614 const ARMCPRegInfo *ri, int isread) 2615 { 2616 return (ri->access >> ((current_el * 2) + isread)) & 1; 2617 } 2618 2619 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2620 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2621 2622 /** 2623 * write_list_to_cpustate 2624 * @cpu: ARMCPU 2625 * 2626 * For each register listed in the ARMCPU cpreg_indexes list, write 2627 * its value from the cpreg_values list into the ARMCPUState structure. 2628 * This updates TCG's working data structures from KVM data or 2629 * from incoming migration state. 2630 * 2631 * Returns: true if all register values were updated correctly, 2632 * false if some register was unknown or could not be written. 2633 * Note that we do not stop early on failure -- we will attempt 2634 * writing all registers in the list. 2635 */ 2636 bool write_list_to_cpustate(ARMCPU *cpu); 2637 2638 /** 2639 * write_cpustate_to_list: 2640 * @cpu: ARMCPU 2641 * @kvm_sync: true if this is for syncing back to KVM 2642 * 2643 * For each register listed in the ARMCPU cpreg_indexes list, write 2644 * its value from the ARMCPUState structure into the cpreg_values list. 2645 * This is used to copy info from TCG's working data structures into 2646 * KVM or for outbound migration. 2647 * 2648 * @kvm_sync is true if we are doing this in order to sync the 2649 * register state back to KVM. In this case we will only update 2650 * values in the list if the previous list->cpustate sync actually 2651 * successfully wrote the CPU state. Otherwise we will keep the value 2652 * that is in the list. 2653 * 2654 * Returns: true if all register values were read correctly, 2655 * false if some register was unknown or could not be read. 2656 * Note that we do not stop early on failure -- we will attempt 2657 * reading all registers in the list. 2658 */ 2659 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2660 2661 #define ARM_CPUID_TI915T 0x54029152 2662 #define ARM_CPUID_TI925T 0x54029252 2663 2664 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2665 unsigned int target_el) 2666 { 2667 CPUARMState *env = cs->env_ptr; 2668 unsigned int cur_el = arm_current_el(env); 2669 bool secure = arm_is_secure(env); 2670 bool pstate_unmasked; 2671 int8_t unmasked = 0; 2672 uint64_t hcr_el2; 2673 2674 /* Don't take exceptions if they target a lower EL. 2675 * This check should catch any exceptions that would not be taken but left 2676 * pending. 2677 */ 2678 if (cur_el > target_el) { 2679 return false; 2680 } 2681 2682 hcr_el2 = arm_hcr_el2_eff(env); 2683 2684 switch (excp_idx) { 2685 case EXCP_FIQ: 2686 pstate_unmasked = !(env->daif & PSTATE_F); 2687 break; 2688 2689 case EXCP_IRQ: 2690 pstate_unmasked = !(env->daif & PSTATE_I); 2691 break; 2692 2693 case EXCP_VFIQ: 2694 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 2695 /* VFIQs are only taken when hypervized and non-secure. */ 2696 return false; 2697 } 2698 return !(env->daif & PSTATE_F); 2699 case EXCP_VIRQ: 2700 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 2701 /* VIRQs are only taken when hypervized and non-secure. */ 2702 return false; 2703 } 2704 return !(env->daif & PSTATE_I); 2705 default: 2706 g_assert_not_reached(); 2707 } 2708 2709 /* Use the target EL, current execution state and SCR/HCR settings to 2710 * determine whether the corresponding CPSR bit is used to mask the 2711 * interrupt. 2712 */ 2713 if ((target_el > cur_el) && (target_el != 1)) { 2714 /* Exceptions targeting a higher EL may not be maskable */ 2715 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2716 /* 64-bit masking rules are simple: exceptions to EL3 2717 * can't be masked, and exceptions to EL2 can only be 2718 * masked from Secure state. The HCR and SCR settings 2719 * don't affect the masking logic, only the interrupt routing. 2720 */ 2721 if (target_el == 3 || !secure) { 2722 unmasked = 1; 2723 } 2724 } else { 2725 /* The old 32-bit-only environment has a more complicated 2726 * masking setup. HCR and SCR bits not only affect interrupt 2727 * routing but also change the behaviour of masking. 2728 */ 2729 bool hcr, scr; 2730 2731 switch (excp_idx) { 2732 case EXCP_FIQ: 2733 /* If FIQs are routed to EL3 or EL2 then there are cases where 2734 * we override the CPSR.F in determining if the exception is 2735 * masked or not. If neither of these are set then we fall back 2736 * to the CPSR.F setting otherwise we further assess the state 2737 * below. 2738 */ 2739 hcr = hcr_el2 & HCR_FMO; 2740 scr = (env->cp15.scr_el3 & SCR_FIQ); 2741 2742 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2743 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2744 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2745 * when non-secure but only when FIQs are only routed to EL3. 2746 */ 2747 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2748 break; 2749 case EXCP_IRQ: 2750 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2751 * we may override the CPSR.I masking when in non-secure state. 2752 * The SCR.IRQ setting has already been taken into consideration 2753 * when setting the target EL, so it does not have a further 2754 * affect here. 2755 */ 2756 hcr = hcr_el2 & HCR_IMO; 2757 scr = false; 2758 break; 2759 default: 2760 g_assert_not_reached(); 2761 } 2762 2763 if ((scr || hcr) && !secure) { 2764 unmasked = 1; 2765 } 2766 } 2767 } 2768 2769 /* The PSTATE bits only mask the interrupt if we have not overriden the 2770 * ability above. 2771 */ 2772 return unmasked || pstate_unmasked; 2773 } 2774 2775 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2776 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2777 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2778 2779 #define cpu_signal_handler cpu_arm_signal_handler 2780 #define cpu_list arm_cpu_list 2781 2782 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2783 * 2784 * If EL3 is 64-bit: 2785 * + NonSecure EL1 & 0 stage 1 2786 * + NonSecure EL1 & 0 stage 2 2787 * + NonSecure EL2 2788 * + Secure EL1 & EL0 2789 * + Secure EL3 2790 * If EL3 is 32-bit: 2791 * + NonSecure PL1 & 0 stage 1 2792 * + NonSecure PL1 & 0 stage 2 2793 * + NonSecure PL2 2794 * + Secure PL0 & PL1 2795 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2796 * 2797 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2798 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2799 * may differ in access permissions even if the VA->PA map is the same 2800 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2801 * translation, which means that we have one mmu_idx that deals with two 2802 * concatenated translation regimes [this sort of combined s1+2 TLB is 2803 * architecturally permitted] 2804 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2805 * handling via the TLB. The only way to do a stage 1 translation without 2806 * the immediate stage 2 translation is via the ATS or AT system insns, 2807 * which can be slow-pathed and always do a page table walk. 2808 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2809 * translation regimes, because they map reasonably well to each other 2810 * and they can't both be active at the same time. 2811 * This gives us the following list of mmu_idx values: 2812 * 2813 * NS EL0 (aka NS PL0) stage 1+2 2814 * NS EL1 (aka NS PL1) stage 1+2 2815 * NS EL2 (aka NS PL2) 2816 * S EL3 (aka S PL1) 2817 * S EL0 (aka S PL0) 2818 * S EL1 (not used if EL3 is 32 bit) 2819 * NS EL0+1 stage 2 2820 * 2821 * (The last of these is an mmu_idx because we want to be able to use the TLB 2822 * for the accesses done as part of a stage 1 page table walk, rather than 2823 * having to walk the stage 2 page table over and over.) 2824 * 2825 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2826 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2827 * NS EL2 if we ever model a Cortex-R52). 2828 * 2829 * M profile CPUs are rather different as they do not have a true MMU. 2830 * They have the following different MMU indexes: 2831 * User 2832 * Privileged 2833 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2834 * Privileged, execution priority negative (ditto) 2835 * If the CPU supports the v8M Security Extension then there are also: 2836 * Secure User 2837 * Secure Privileged 2838 * Secure User, execution priority negative 2839 * Secure Privileged, execution priority negative 2840 * 2841 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2842 * are not quite the same -- different CPU types (most notably M profile 2843 * vs A/R profile) would like to use MMU indexes with different semantics, 2844 * but since we don't ever need to use all of those in a single CPU we 2845 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2846 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2847 * the same for any particular CPU. 2848 * Variables of type ARMMUIdx are always full values, and the core 2849 * index values are in variables of type 'int'. 2850 * 2851 * Our enumeration includes at the end some entries which are not "true" 2852 * mmu_idx values in that they don't have corresponding TLBs and are only 2853 * valid for doing slow path page table walks. 2854 * 2855 * The constant names here are patterned after the general style of the names 2856 * of the AT/ATS operations. 2857 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2858 * For M profile we arrange them to have a bit for priv, a bit for negpri 2859 * and a bit for secure. 2860 */ 2861 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2862 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2863 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2864 2865 /* meanings of the bits for M profile mmu idx values */ 2866 #define ARM_MMU_IDX_M_PRIV 0x1 2867 #define ARM_MMU_IDX_M_NEGPRI 0x2 2868 #define ARM_MMU_IDX_M_S 0x4 2869 2870 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2871 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2872 2873 typedef enum ARMMMUIdx { 2874 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2875 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2876 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2877 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2878 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2879 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2880 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2881 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2882 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2883 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2884 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2885 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2886 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2887 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2888 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2889 /* Indexes below here don't have TLBs and are used only for AT system 2890 * instructions or for the first stage of an S12 page table walk. 2891 */ 2892 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2893 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2894 } ARMMMUIdx; 2895 2896 /* Bit macros for the core-mmu-index values for each index, 2897 * for use when calling tlb_flush_by_mmuidx() and friends. 2898 */ 2899 typedef enum ARMMMUIdxBit { 2900 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2901 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2902 ARMMMUIdxBit_S1E2 = 1 << 2, 2903 ARMMMUIdxBit_S1E3 = 1 << 3, 2904 ARMMMUIdxBit_S1SE0 = 1 << 4, 2905 ARMMMUIdxBit_S1SE1 = 1 << 5, 2906 ARMMMUIdxBit_S2NS = 1 << 6, 2907 ARMMMUIdxBit_MUser = 1 << 0, 2908 ARMMMUIdxBit_MPriv = 1 << 1, 2909 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2910 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2911 ARMMMUIdxBit_MSUser = 1 << 4, 2912 ARMMMUIdxBit_MSPriv = 1 << 5, 2913 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2914 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2915 } ARMMMUIdxBit; 2916 2917 #define MMU_USER_IDX 0 2918 2919 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2920 { 2921 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2922 } 2923 2924 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2925 { 2926 if (arm_feature(env, ARM_FEATURE_M)) { 2927 return mmu_idx | ARM_MMU_IDX_M; 2928 } else { 2929 return mmu_idx | ARM_MMU_IDX_A; 2930 } 2931 } 2932 2933 /* Return the exception level we're running at if this is our mmu_idx */ 2934 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2935 { 2936 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2937 case ARM_MMU_IDX_A: 2938 return mmu_idx & 3; 2939 case ARM_MMU_IDX_M: 2940 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2941 default: 2942 g_assert_not_reached(); 2943 } 2944 } 2945 2946 /* 2947 * Return the MMU index for a v7M CPU with all relevant information 2948 * manually specified. 2949 */ 2950 ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, 2951 bool secstate, bool priv, bool negpri); 2952 2953 /* Return the MMU index for a v7M CPU in the specified security and 2954 * privilege state. 2955 */ 2956 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2957 bool secstate, bool priv); 2958 2959 /* Return the MMU index for a v7M CPU in the specified security state */ 2960 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); 2961 2962 /** 2963 * cpu_mmu_index: 2964 * @env: The cpu environment 2965 * @ifetch: True for code access, false for data access. 2966 * 2967 * Return the core mmu index for the current translation regime. 2968 * This function is used by generic TCG code paths. 2969 */ 2970 int cpu_mmu_index(CPUARMState *env, bool ifetch); 2971 2972 /* Indexes used when registering address spaces with cpu_address_space_init */ 2973 typedef enum ARMASIdx { 2974 ARMASIdx_NS = 0, 2975 ARMASIdx_S = 1, 2976 } ARMASIdx; 2977 2978 /* Return the Exception Level targeted by debug exceptions. */ 2979 static inline int arm_debug_target_el(CPUARMState *env) 2980 { 2981 bool secure = arm_is_secure(env); 2982 bool route_to_el2 = false; 2983 2984 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2985 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2986 env->cp15.mdcr_el2 & MDCR_TDE; 2987 } 2988 2989 if (route_to_el2) { 2990 return 2; 2991 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2992 !arm_el_is_aa64(env, 3) && secure) { 2993 return 3; 2994 } else { 2995 return 1; 2996 } 2997 } 2998 2999 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3000 { 3001 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3002 * CSSELR is RAZ/WI. 3003 */ 3004 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3005 } 3006 3007 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 3008 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 3009 { 3010 int cur_el = arm_current_el(env); 3011 int debug_el; 3012 3013 if (cur_el == 3) { 3014 return false; 3015 } 3016 3017 /* MDCR_EL3.SDD disables debug events from Secure state */ 3018 if (arm_is_secure_below_el3(env) 3019 && extract32(env->cp15.mdcr_el3, 16, 1)) { 3020 return false; 3021 } 3022 3023 /* 3024 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 3025 * while not masking the (D)ebug bit in DAIF. 3026 */ 3027 debug_el = arm_debug_target_el(env); 3028 3029 if (cur_el == debug_el) { 3030 return extract32(env->cp15.mdscr_el1, 13, 1) 3031 && !(env->daif & PSTATE_D); 3032 } 3033 3034 /* Otherwise the debug target needs to be a higher EL */ 3035 return debug_el > cur_el; 3036 } 3037 3038 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 3039 { 3040 int el = arm_current_el(env); 3041 3042 if (el == 0 && arm_el_is_aa64(env, 1)) { 3043 return aa64_generate_debug_exceptions(env); 3044 } 3045 3046 if (arm_is_secure(env)) { 3047 int spd; 3048 3049 if (el == 0 && (env->cp15.sder & 1)) { 3050 /* SDER.SUIDEN means debug exceptions from Secure EL0 3051 * are always enabled. Otherwise they are controlled by 3052 * SDCR.SPD like those from other Secure ELs. 3053 */ 3054 return true; 3055 } 3056 3057 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3058 switch (spd) { 3059 case 1: 3060 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3061 case 0: 3062 /* For 0b00 we return true if external secure invasive debug 3063 * is enabled. On real hardware this is controlled by external 3064 * signals to the core. QEMU always permits debug, and behaves 3065 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3066 */ 3067 return true; 3068 case 2: 3069 return false; 3070 case 3: 3071 return true; 3072 } 3073 } 3074 3075 return el != 2; 3076 } 3077 3078 /* Return true if debugging exceptions are currently enabled. 3079 * This corresponds to what in ARM ARM pseudocode would be 3080 * if UsingAArch32() then 3081 * return AArch32.GenerateDebugExceptions() 3082 * else 3083 * return AArch64.GenerateDebugExceptions() 3084 * We choose to push the if() down into this function for clarity, 3085 * since the pseudocode has it at all callsites except for the one in 3086 * CheckSoftwareStep(), where it is elided because both branches would 3087 * always return the same value. 3088 */ 3089 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3090 { 3091 if (env->aarch64) { 3092 return aa64_generate_debug_exceptions(env); 3093 } else { 3094 return aa32_generate_debug_exceptions(env); 3095 } 3096 } 3097 3098 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3099 * implicitly means this always returns false in pre-v8 CPUs.) 3100 */ 3101 static inline bool arm_singlestep_active(CPUARMState *env) 3102 { 3103 return extract32(env->cp15.mdscr_el1, 0, 1) 3104 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3105 && arm_generate_debug_exceptions(env); 3106 } 3107 3108 static inline bool arm_sctlr_b(CPUARMState *env) 3109 { 3110 return 3111 /* We need not implement SCTLR.ITD in user-mode emulation, so 3112 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3113 * This lets people run BE32 binaries with "-cpu any". 3114 */ 3115 #ifndef CONFIG_USER_ONLY 3116 !arm_feature(env, ARM_FEATURE_V7) && 3117 #endif 3118 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3119 } 3120 3121 static inline uint64_t arm_sctlr(CPUARMState *env, int el) 3122 { 3123 if (el == 0) { 3124 /* FIXME: ARMv8.1-VHE S2 translation regime. */ 3125 return env->cp15.sctlr_el[1]; 3126 } else { 3127 return env->cp15.sctlr_el[el]; 3128 } 3129 } 3130 3131 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3132 bool sctlr_b) 3133 { 3134 #ifdef CONFIG_USER_ONLY 3135 /* 3136 * In system mode, BE32 is modelled in line with the 3137 * architecture (as word-invariant big-endianness), where loads 3138 * and stores are done little endian but from addresses which 3139 * are adjusted by XORing with the appropriate constant. So the 3140 * endianness to use for the raw data access is not affected by 3141 * SCTLR.B. 3142 * In user mode, however, we model BE32 as byte-invariant 3143 * big-endianness (because user-only code cannot tell the 3144 * difference), and so we need to use a data access endianness 3145 * that depends on SCTLR.B. 3146 */ 3147 if (sctlr_b) { 3148 return true; 3149 } 3150 #endif 3151 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3152 return env->uncached_cpsr & CPSR_E; 3153 } 3154 3155 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3156 { 3157 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3158 } 3159 3160 /* Return true if the processor is in big-endian mode. */ 3161 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3162 { 3163 if (!is_a64(env)) { 3164 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3165 } else { 3166 int cur_el = arm_current_el(env); 3167 uint64_t sctlr = arm_sctlr(env, cur_el); 3168 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3169 } 3170 } 3171 3172 typedef CPUARMState CPUArchState; 3173 typedef ARMCPU ArchCPU; 3174 3175 #include "exec/cpu-all.h" 3176 3177 /* 3178 * Bit usage in the TB flags field: bit 31 indicates whether we are 3179 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 3180 * We put flags which are shared between 32 and 64 bit mode at the top 3181 * of the word, and flags which apply to only one mode at the bottom. 3182 * 3183 * Unless otherwise noted, these bits are cached in env->hflags. 3184 */ 3185 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3186 FIELD(TBFLAG_ANY, MMUIDX, 28, 3) 3187 FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) 3188 FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ 3189 /* Target EL if we take a floating-point-disabled exception */ 3190 FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) 3191 FIELD(TBFLAG_ANY, BE_DATA, 23, 1) 3192 /* 3193 * For A-profile only, target EL for debug exceptions. 3194 * Note that this overlaps with the M-profile-only HANDLER and STACKCHECK bits. 3195 */ 3196 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) 3197 3198 /* Bit usage when in AArch32 state: */ 3199 FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ 3200 FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */ 3201 FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */ 3202 /* 3203 * We store the bottom two bits of the CPAR as TB flags and handle 3204 * checks on the other bits at runtime. This shares the same bits as 3205 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3206 * Not cached, because VECLEN+VECSTRIDE are not cached. 3207 */ 3208 FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) 3209 /* 3210 * Indicates whether cp register reads and writes by guest code should access 3211 * the secure or nonsecure bank of banked registers; note that this is not 3212 * the same thing as the current security state of the processor! 3213 */ 3214 FIELD(TBFLAG_A32, NS, 6, 1) 3215 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3216 FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ 3217 FIELD(TBFLAG_A32, SCTLR_B, 16, 1) 3218 FIELD(TBFLAG_A32, HSTR_ACTIVE, 17, 1) 3219 3220 /* For M profile only, set if FPCCR.LSPACT is set */ 3221 FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */ 3222 /* For M profile only, set if we must create a new FP context */ 3223 FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */ 3224 /* For M profile only, set if FPCCR.S does not match current security state */ 3225 FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */ 3226 /* For M profile only, Handler (ie not Thread) mode */ 3227 FIELD(TBFLAG_A32, HANDLER, 21, 1) 3228 /* For M profile only, whether we should generate stack-limit checks */ 3229 FIELD(TBFLAG_A32, STACKCHECK, 22, 1) 3230 3231 /* Bit usage when in AArch64 state */ 3232 FIELD(TBFLAG_A64, TBII, 0, 2) 3233 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3234 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3235 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3236 FIELD(TBFLAG_A64, BT, 9, 1) 3237 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3238 FIELD(TBFLAG_A64, TBID, 12, 2) 3239 3240 static inline bool bswap_code(bool sctlr_b) 3241 { 3242 #ifdef CONFIG_USER_ONLY 3243 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3244 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3245 * would also end up as a mixed-endian mode with BE code, LE data. 3246 */ 3247 return 3248 #ifdef TARGET_WORDS_BIGENDIAN 3249 1 ^ 3250 #endif 3251 sctlr_b; 3252 #else 3253 /* All code access in ARM is little endian, and there are no loaders 3254 * doing swaps that need to be reversed 3255 */ 3256 return 0; 3257 #endif 3258 } 3259 3260 #ifdef CONFIG_USER_ONLY 3261 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3262 { 3263 return 3264 #ifdef TARGET_WORDS_BIGENDIAN 3265 1 ^ 3266 #endif 3267 arm_cpu_data_is_big_endian(env); 3268 } 3269 #endif 3270 3271 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3272 target_ulong *cs_base, uint32_t *flags); 3273 3274 enum { 3275 QEMU_PSCI_CONDUIT_DISABLED = 0, 3276 QEMU_PSCI_CONDUIT_SMC = 1, 3277 QEMU_PSCI_CONDUIT_HVC = 2, 3278 }; 3279 3280 #ifndef CONFIG_USER_ONLY 3281 /* Return the address space index to use for a memory access */ 3282 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3283 { 3284 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3285 } 3286 3287 /* Return the AddressSpace to use for a memory access 3288 * (which depends on whether the access is S or NS, and whether 3289 * the board gave us a separate AddressSpace for S accesses). 3290 */ 3291 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3292 { 3293 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3294 } 3295 #endif 3296 3297 /** 3298 * arm_register_pre_el_change_hook: 3299 * Register a hook function which will be called immediately before this 3300 * CPU changes exception level or mode. The hook function will be 3301 * passed a pointer to the ARMCPU and the opaque data pointer passed 3302 * to this function when the hook was registered. 3303 * 3304 * Note that if a pre-change hook is called, any registered post-change hooks 3305 * are guaranteed to subsequently be called. 3306 */ 3307 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3308 void *opaque); 3309 /** 3310 * arm_register_el_change_hook: 3311 * Register a hook function which will be called immediately after this 3312 * CPU changes exception level or mode. The hook function will be 3313 * passed a pointer to the ARMCPU and the opaque data pointer passed 3314 * to this function when the hook was registered. 3315 * 3316 * Note that any registered hooks registered here are guaranteed to be called 3317 * if pre-change hooks have been. 3318 */ 3319 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3320 *opaque); 3321 3322 /** 3323 * arm_rebuild_hflags: 3324 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3325 */ 3326 void arm_rebuild_hflags(CPUARMState *env); 3327 3328 /** 3329 * aa32_vfp_dreg: 3330 * Return a pointer to the Dn register within env in 32-bit mode. 3331 */ 3332 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3333 { 3334 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3335 } 3336 3337 /** 3338 * aa32_vfp_qreg: 3339 * Return a pointer to the Qn register within env in 32-bit mode. 3340 */ 3341 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3342 { 3343 return &env->vfp.zregs[regno].d[0]; 3344 } 3345 3346 /** 3347 * aa64_vfp_qreg: 3348 * Return a pointer to the Qn register within env in 64-bit mode. 3349 */ 3350 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3351 { 3352 return &env->vfp.zregs[regno].d[0]; 3353 } 3354 3355 /* Shared between translate-sve.c and sve_helper.c. */ 3356 extern const uint64_t pred_esz_masks[4]; 3357 3358 /* 3359 * 32-bit feature tests via id registers. 3360 */ 3361 static inline bool isar_feature_thumb_div(const ARMISARegisters *id) 3362 { 3363 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3364 } 3365 3366 static inline bool isar_feature_arm_div(const ARMISARegisters *id) 3367 { 3368 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3369 } 3370 3371 static inline bool isar_feature_jazelle(const ARMISARegisters *id) 3372 { 3373 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3374 } 3375 3376 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3377 { 3378 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3379 } 3380 3381 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3382 { 3383 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3384 } 3385 3386 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3387 { 3388 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3389 } 3390 3391 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3392 { 3393 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3394 } 3395 3396 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3397 { 3398 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3399 } 3400 3401 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3402 { 3403 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3404 } 3405 3406 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3407 { 3408 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3409 } 3410 3411 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3412 { 3413 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3414 } 3415 3416 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3417 { 3418 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3419 } 3420 3421 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3422 { 3423 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3424 } 3425 3426 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3427 { 3428 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3429 } 3430 3431 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3432 { 3433 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3434 } 3435 3436 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3437 { 3438 /* 3439 * This is a placeholder for use by VCMA until the rest of 3440 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3441 * At which point we can properly set and check MVFR1.FPHP. 3442 */ 3443 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3444 } 3445 3446 static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id) 3447 { 3448 /* Return true if D16-D31 are implemented */ 3449 return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >= 2; 3450 } 3451 3452 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3453 { 3454 return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0; 3455 } 3456 3457 static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) 3458 { 3459 /* Return true if CPU supports double precision floating point */ 3460 return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0; 3461 } 3462 3463 /* 3464 * We always set the FP and SIMD FP16 fields to indicate identical 3465 * levels of support (assuming SIMD is implemented at all), so 3466 * we only need one set of accessors. 3467 */ 3468 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3469 { 3470 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0; 3471 } 3472 3473 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3474 { 3475 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; 3476 } 3477 3478 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3479 { 3480 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1; 3481 } 3482 3483 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3484 { 3485 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2; 3486 } 3487 3488 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3489 { 3490 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3; 3491 } 3492 3493 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3494 { 3495 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; 3496 } 3497 3498 /* 3499 * 64-bit feature tests via id registers. 3500 */ 3501 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3502 { 3503 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3504 } 3505 3506 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3507 { 3508 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3509 } 3510 3511 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3512 { 3513 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3514 } 3515 3516 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3517 { 3518 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3519 } 3520 3521 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3522 { 3523 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3524 } 3525 3526 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3527 { 3528 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3529 } 3530 3531 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3532 { 3533 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3534 } 3535 3536 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3537 { 3538 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3539 } 3540 3541 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3542 { 3543 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3544 } 3545 3546 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3547 { 3548 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3549 } 3550 3551 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3552 { 3553 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3554 } 3555 3556 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3557 { 3558 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3559 } 3560 3561 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3562 { 3563 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3564 } 3565 3566 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3567 { 3568 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3569 } 3570 3571 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3572 { 3573 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3574 } 3575 3576 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3577 { 3578 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3579 } 3580 3581 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3582 { 3583 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3584 } 3585 3586 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3587 { 3588 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3589 } 3590 3591 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3592 { 3593 /* 3594 * Note that while QEMU will only implement the architected algorithm 3595 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation 3596 * defined algorithms, and thus API+GPI, and this predicate controls 3597 * migration of the 128-bit keys. 3598 */ 3599 return (id->id_aa64isar1 & 3600 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3601 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3602 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3603 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3604 } 3605 3606 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3607 { 3608 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3609 } 3610 3611 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3612 { 3613 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3614 } 3615 3616 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3617 { 3618 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3619 } 3620 3621 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3622 { 3623 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3624 } 3625 3626 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3627 { 3628 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3629 } 3630 3631 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3632 { 3633 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3634 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3635 } 3636 3637 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3638 { 3639 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3640 } 3641 3642 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3643 { 3644 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3645 } 3646 3647 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3648 { 3649 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3650 } 3651 3652 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3653 { 3654 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3655 } 3656 3657 /* 3658 * Forward to the above feature tests given an ARMCPU pointer. 3659 */ 3660 #define cpu_isar_feature(name, cpu) \ 3661 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3662 3663 #endif 3664