1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #define EXCP_UDEF 1 /* undefined instruction */ 43 #define EXCP_SWI 2 /* software interrupt */ 44 #define EXCP_PREFETCH_ABORT 3 45 #define EXCP_DATA_ABORT 4 46 #define EXCP_IRQ 5 47 #define EXCP_FIQ 6 48 #define EXCP_BKPT 7 49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 51 #define EXCP_HVC 11 /* HyperVisor Call */ 52 #define EXCP_HYP_TRAP 12 53 #define EXCP_SMC 13 /* Secure Monitor Call */ 54 #define EXCP_VIRQ 14 55 #define EXCP_VFIQ 15 56 #define EXCP_SEMIHOST 16 /* semihosting call */ 57 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 58 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 59 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 60 61 #define ARMV7M_EXCP_RESET 1 62 #define ARMV7M_EXCP_NMI 2 63 #define ARMV7M_EXCP_HARD 3 64 #define ARMV7M_EXCP_MEM 4 65 #define ARMV7M_EXCP_BUS 5 66 #define ARMV7M_EXCP_USAGE 6 67 #define ARMV7M_EXCP_SECURE 7 68 #define ARMV7M_EXCP_SVC 11 69 #define ARMV7M_EXCP_DEBUG 12 70 #define ARMV7M_EXCP_PENDSV 14 71 #define ARMV7M_EXCP_SYSTICK 15 72 73 /* For M profile, some registers are banked secure vs non-secure; 74 * these are represented as a 2-element array where the first element 75 * is the non-secure copy and the second is the secure copy. 76 * When the CPU does not have implement the security extension then 77 * only the first element is used. 78 * This means that the copy for the current security state can be 79 * accessed via env->registerfield[env->v7m.secure] (whether the security 80 * extension is implemented or not). 81 */ 82 enum { 83 M_REG_NS = 0, 84 M_REG_S = 1, 85 M_REG_NUM_BANKS = 2, 86 }; 87 88 /* ARM-specific interrupt pending bits. */ 89 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 90 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 91 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 92 93 /* The usual mapping for an AArch64 system register to its AArch32 94 * counterpart is for the 32 bit world to have access to the lower 95 * half only (with writes leaving the upper half untouched). It's 96 * therefore useful to be able to pass TCG the offset of the least 97 * significant half of a uint64_t struct member. 98 */ 99 #ifdef HOST_WORDS_BIGENDIAN 100 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 101 #define offsetofhigh32(S, M) offsetof(S, M) 102 #else 103 #define offsetoflow32(S, M) offsetof(S, M) 104 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 105 #endif 106 107 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 108 #define ARM_CPU_IRQ 0 109 #define ARM_CPU_FIQ 1 110 #define ARM_CPU_VIRQ 2 111 #define ARM_CPU_VFIQ 3 112 113 #define NB_MMU_MODES 8 114 /* ARM-specific extra insn start words: 115 * 1: Conditional execution bits 116 * 2: Partial exception syndrome for data aborts 117 */ 118 #define TARGET_INSN_START_EXTRA_WORDS 2 119 120 /* The 2nd extra word holding syndrome info for data aborts does not use 121 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 122 * help the sleb128 encoder do a better job. 123 * When restoring the CPU state, we shift it back up. 124 */ 125 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 126 #define ARM_INSN_START_WORD2_SHIFT 14 127 128 /* We currently assume float and double are IEEE single and double 129 precision respectively. 130 Doing runtime conversions is tricky because VFP registers may contain 131 integer values (eg. as the result of a FTOSI instruction). 132 s<2n> maps to the least significant half of d<n> 133 s<2n+1> maps to the most significant half of d<n> 134 */ 135 136 /** 137 * DynamicGDBXMLInfo: 138 * @desc: Contains the XML descriptions. 139 * @num_cpregs: Number of the Coprocessor registers seen by GDB. 140 * @cpregs_keys: Array that contains the corresponding Key of 141 * a given cpreg with the same order of the cpreg in the XML description. 142 */ 143 typedef struct DynamicGDBXMLInfo { 144 char *desc; 145 int num_cpregs; 146 uint32_t *cpregs_keys; 147 } DynamicGDBXMLInfo; 148 149 /* CPU state for each instance of a generic timer (in cp15 c14) */ 150 typedef struct ARMGenericTimer { 151 uint64_t cval; /* Timer CompareValue register */ 152 uint64_t ctl; /* Timer Control register */ 153 } ARMGenericTimer; 154 155 #define GTIMER_PHYS 0 156 #define GTIMER_VIRT 1 157 #define GTIMER_HYP 2 158 #define GTIMER_SEC 3 159 #define NUM_GTIMERS 4 160 161 typedef struct { 162 uint64_t raw_tcr; 163 uint32_t mask; 164 uint32_t base_mask; 165 } TCR; 166 167 /* Define a maximum sized vector register. 168 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 169 * For 64-bit, this is a 2048-bit SVE register. 170 * 171 * Note that the mapping between S, D, and Q views of the register bank 172 * differs between AArch64 and AArch32. 173 * In AArch32: 174 * Qn = regs[n].d[1]:regs[n].d[0] 175 * Dn = regs[n / 2].d[n & 1] 176 * Sn = regs[n / 4].d[n % 4 / 2], 177 * bits 31..0 for even n, and bits 63..32 for odd n 178 * (and regs[16] to regs[31] are inaccessible) 179 * In AArch64: 180 * Zn = regs[n].d[*] 181 * Qn = regs[n].d[1]:regs[n].d[0] 182 * Dn = regs[n].d[0] 183 * Sn = regs[n].d[0] bits 31..0 184 * Hn = regs[n].d[0] bits 15..0 185 * 186 * This corresponds to the architecturally defined mapping between 187 * the two execution states, and means we do not need to explicitly 188 * map these registers when changing states. 189 * 190 * Align the data for use with TCG host vector operations. 191 */ 192 193 #ifdef TARGET_AARCH64 194 # define ARM_MAX_VQ 16 195 #else 196 # define ARM_MAX_VQ 1 197 #endif 198 199 typedef struct ARMVectorReg { 200 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 201 } ARMVectorReg; 202 203 /* In AArch32 mode, predicate registers do not exist at all. */ 204 #ifdef TARGET_AARCH64 205 typedef struct ARMPredicateReg { 206 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); 207 } ARMPredicateReg; 208 #endif 209 210 211 typedef struct CPUARMState { 212 /* Regs for current mode. */ 213 uint32_t regs[16]; 214 215 /* 32/64 switch only happens when taking and returning from 216 * exceptions so the overlap semantics are taken care of then 217 * instead of having a complicated union. 218 */ 219 /* Regs for A64 mode. */ 220 uint64_t xregs[32]; 221 uint64_t pc; 222 /* PSTATE isn't an architectural register for ARMv8. However, it is 223 * convenient for us to assemble the underlying state into a 32 bit format 224 * identical to the architectural format used for the SPSR. (This is also 225 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 226 * 'pstate' register are.) Of the PSTATE bits: 227 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 228 * semantics as for AArch32, as described in the comments on each field) 229 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 230 * DAIF (exception masks) are kept in env->daif 231 * all other bits are stored in their correct places in env->pstate 232 */ 233 uint32_t pstate; 234 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 235 236 /* Frequently accessed CPSR bits are stored separately for efficiency. 237 This contains all the other bits. Use cpsr_{read,write} to access 238 the whole CPSR. */ 239 uint32_t uncached_cpsr; 240 uint32_t spsr; 241 242 /* Banked registers. */ 243 uint64_t banked_spsr[8]; 244 uint32_t banked_r13[8]; 245 uint32_t banked_r14[8]; 246 247 /* These hold r8-r12. */ 248 uint32_t usr_regs[5]; 249 uint32_t fiq_regs[5]; 250 251 /* cpsr flag cache for faster execution */ 252 uint32_t CF; /* 0 or 1 */ 253 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 254 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 255 uint32_t ZF; /* Z set if zero. */ 256 uint32_t QF; /* 0 or 1 */ 257 uint32_t GE; /* cpsr[19:16] */ 258 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 259 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 260 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 261 262 uint64_t elr_el[4]; /* AArch64 exception link regs */ 263 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 264 265 /* System control coprocessor (cp15) */ 266 struct { 267 uint32_t c0_cpuid; 268 union { /* Cache size selection */ 269 struct { 270 uint64_t _unused_csselr0; 271 uint64_t csselr_ns; 272 uint64_t _unused_csselr1; 273 uint64_t csselr_s; 274 }; 275 uint64_t csselr_el[4]; 276 }; 277 union { /* System control register. */ 278 struct { 279 uint64_t _unused_sctlr; 280 uint64_t sctlr_ns; 281 uint64_t hsctlr; 282 uint64_t sctlr_s; 283 }; 284 uint64_t sctlr_el[4]; 285 }; 286 uint64_t cpacr_el1; /* Architectural feature access control register */ 287 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 288 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 289 uint64_t sder; /* Secure debug enable register. */ 290 uint32_t nsacr; /* Non-secure access control register. */ 291 union { /* MMU translation table base 0. */ 292 struct { 293 uint64_t _unused_ttbr0_0; 294 uint64_t ttbr0_ns; 295 uint64_t _unused_ttbr0_1; 296 uint64_t ttbr0_s; 297 }; 298 uint64_t ttbr0_el[4]; 299 }; 300 union { /* MMU translation table base 1. */ 301 struct { 302 uint64_t _unused_ttbr1_0; 303 uint64_t ttbr1_ns; 304 uint64_t _unused_ttbr1_1; 305 uint64_t ttbr1_s; 306 }; 307 uint64_t ttbr1_el[4]; 308 }; 309 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 310 /* MMU translation table base control. */ 311 TCR tcr_el[4]; 312 TCR vtcr_el2; /* Virtualization Translation Control. */ 313 uint32_t c2_data; /* MPU data cacheable bits. */ 314 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 315 union { /* MMU domain access control register 316 * MPU write buffer control. 317 */ 318 struct { 319 uint64_t dacr_ns; 320 uint64_t dacr_s; 321 }; 322 struct { 323 uint64_t dacr32_el2; 324 }; 325 }; 326 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 327 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 328 uint64_t hcr_el2; /* Hypervisor configuration register */ 329 uint64_t scr_el3; /* Secure configuration register. */ 330 union { /* Fault status registers. */ 331 struct { 332 uint64_t ifsr_ns; 333 uint64_t ifsr_s; 334 }; 335 struct { 336 uint64_t ifsr32_el2; 337 }; 338 }; 339 union { 340 struct { 341 uint64_t _unused_dfsr; 342 uint64_t dfsr_ns; 343 uint64_t hsr; 344 uint64_t dfsr_s; 345 }; 346 uint64_t esr_el[4]; 347 }; 348 uint32_t c6_region[8]; /* MPU base/size registers. */ 349 union { /* Fault address registers. */ 350 struct { 351 uint64_t _unused_far0; 352 #ifdef HOST_WORDS_BIGENDIAN 353 uint32_t ifar_ns; 354 uint32_t dfar_ns; 355 uint32_t ifar_s; 356 uint32_t dfar_s; 357 #else 358 uint32_t dfar_ns; 359 uint32_t ifar_ns; 360 uint32_t dfar_s; 361 uint32_t ifar_s; 362 #endif 363 uint64_t _unused_far3; 364 }; 365 uint64_t far_el[4]; 366 }; 367 uint64_t hpfar_el2; 368 uint64_t hstr_el2; 369 union { /* Translation result. */ 370 struct { 371 uint64_t _unused_par_0; 372 uint64_t par_ns; 373 uint64_t _unused_par_1; 374 uint64_t par_s; 375 }; 376 uint64_t par_el[4]; 377 }; 378 379 uint32_t c9_insn; /* Cache lockdown registers. */ 380 uint32_t c9_data; 381 uint64_t c9_pmcr; /* performance monitor control register */ 382 uint64_t c9_pmcnten; /* perf monitor counter enables */ 383 uint64_t c9_pmovsr; /* perf monitor overflow status */ 384 uint64_t c9_pmuserenr; /* perf monitor user enable */ 385 uint64_t c9_pmselr; /* perf monitor counter selection register */ 386 uint64_t c9_pminten; /* perf monitor interrupt enables */ 387 union { /* Memory attribute redirection */ 388 struct { 389 #ifdef HOST_WORDS_BIGENDIAN 390 uint64_t _unused_mair_0; 391 uint32_t mair1_ns; 392 uint32_t mair0_ns; 393 uint64_t _unused_mair_1; 394 uint32_t mair1_s; 395 uint32_t mair0_s; 396 #else 397 uint64_t _unused_mair_0; 398 uint32_t mair0_ns; 399 uint32_t mair1_ns; 400 uint64_t _unused_mair_1; 401 uint32_t mair0_s; 402 uint32_t mair1_s; 403 #endif 404 }; 405 uint64_t mair_el[4]; 406 }; 407 union { /* vector base address register */ 408 struct { 409 uint64_t _unused_vbar; 410 uint64_t vbar_ns; 411 uint64_t hvbar; 412 uint64_t vbar_s; 413 }; 414 uint64_t vbar_el[4]; 415 }; 416 uint32_t mvbar; /* (monitor) vector base address register */ 417 struct { /* FCSE PID. */ 418 uint32_t fcseidr_ns; 419 uint32_t fcseidr_s; 420 }; 421 union { /* Context ID. */ 422 struct { 423 uint64_t _unused_contextidr_0; 424 uint64_t contextidr_ns; 425 uint64_t _unused_contextidr_1; 426 uint64_t contextidr_s; 427 }; 428 uint64_t contextidr_el[4]; 429 }; 430 union { /* User RW Thread register. */ 431 struct { 432 uint64_t tpidrurw_ns; 433 uint64_t tpidrprw_ns; 434 uint64_t htpidr; 435 uint64_t _tpidr_el3; 436 }; 437 uint64_t tpidr_el[4]; 438 }; 439 /* The secure banks of these registers don't map anywhere */ 440 uint64_t tpidrurw_s; 441 uint64_t tpidrprw_s; 442 uint64_t tpidruro_s; 443 444 union { /* User RO Thread register. */ 445 uint64_t tpidruro_ns; 446 uint64_t tpidrro_el[1]; 447 }; 448 uint64_t c14_cntfrq; /* Counter Frequency register */ 449 uint64_t c14_cntkctl; /* Timer Control register */ 450 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 451 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 452 ARMGenericTimer c14_timer[NUM_GTIMERS]; 453 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 454 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 455 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 456 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 457 uint32_t c15_threadid; /* TI debugger thread-ID. */ 458 uint32_t c15_config_base_address; /* SCU base address. */ 459 uint32_t c15_diagnostic; /* diagnostic register */ 460 uint32_t c15_power_diagnostic; 461 uint32_t c15_power_control; /* power control */ 462 uint64_t dbgbvr[16]; /* breakpoint value registers */ 463 uint64_t dbgbcr[16]; /* breakpoint control registers */ 464 uint64_t dbgwvr[16]; /* watchpoint value registers */ 465 uint64_t dbgwcr[16]; /* watchpoint control registers */ 466 uint64_t mdscr_el1; 467 uint64_t oslsr_el1; /* OS Lock Status */ 468 uint64_t mdcr_el2; 469 uint64_t mdcr_el3; 470 /* If the counter is enabled, this stores the last time the counter 471 * was reset. Otherwise it stores the counter value 472 */ 473 uint64_t c15_ccnt; 474 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 475 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 476 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 477 } cp15; 478 479 struct { 480 /* M profile has up to 4 stack pointers: 481 * a Main Stack Pointer and a Process Stack Pointer for each 482 * of the Secure and Non-Secure states. (If the CPU doesn't support 483 * the security extension then it has only two SPs.) 484 * In QEMU we always store the currently active SP in regs[13], 485 * and the non-active SP for the current security state in 486 * v7m.other_sp. The stack pointers for the inactive security state 487 * are stored in other_ss_msp and other_ss_psp. 488 * switch_v7m_security_state() is responsible for rearranging them 489 * when we change security state. 490 */ 491 uint32_t other_sp; 492 uint32_t other_ss_msp; 493 uint32_t other_ss_psp; 494 uint32_t vecbase[M_REG_NUM_BANKS]; 495 uint32_t basepri[M_REG_NUM_BANKS]; 496 uint32_t control[M_REG_NUM_BANKS]; 497 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 498 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 499 uint32_t hfsr; /* HardFault Status */ 500 uint32_t dfsr; /* Debug Fault Status Register */ 501 uint32_t sfsr; /* Secure Fault Status Register */ 502 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 503 uint32_t bfar; /* BusFault Address */ 504 uint32_t sfar; /* Secure Fault Address Register */ 505 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 506 int exception; 507 uint32_t primask[M_REG_NUM_BANKS]; 508 uint32_t faultmask[M_REG_NUM_BANKS]; 509 uint32_t aircr; /* only holds r/w state if security extn implemented */ 510 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 511 uint32_t csselr[M_REG_NUM_BANKS]; 512 uint32_t scr[M_REG_NUM_BANKS]; 513 uint32_t msplim[M_REG_NUM_BANKS]; 514 uint32_t psplim[M_REG_NUM_BANKS]; 515 } v7m; 516 517 /* Information associated with an exception about to be taken: 518 * code which raises an exception must set cs->exception_index and 519 * the relevant parts of this structure; the cpu_do_interrupt function 520 * will then set the guest-visible registers as part of the exception 521 * entry process. 522 */ 523 struct { 524 uint32_t syndrome; /* AArch64 format syndrome register */ 525 uint32_t fsr; /* AArch32 format fault status register info */ 526 uint64_t vaddress; /* virtual addr associated with exception, if any */ 527 uint32_t target_el; /* EL the exception should be targeted for */ 528 /* If we implement EL2 we will also need to store information 529 * about the intermediate physical address for stage 2 faults. 530 */ 531 } exception; 532 533 /* Thumb-2 EE state. */ 534 uint32_t teecr; 535 uint32_t teehbr; 536 537 /* VFP coprocessor state. */ 538 struct { 539 ARMVectorReg zregs[32]; 540 541 #ifdef TARGET_AARCH64 542 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 543 #define FFR_PRED_NUM 16 544 ARMPredicateReg pregs[17]; 545 /* Scratch space for aa64 sve predicate temporary. */ 546 ARMPredicateReg preg_tmp; 547 #endif 548 549 uint32_t xregs[16]; 550 /* We store these fpcsr fields separately for convenience. */ 551 int vec_len; 552 int vec_stride; 553 554 /* Scratch space for aa32 neon expansion. */ 555 uint32_t scratch[8]; 556 557 /* There are a number of distinct float control structures: 558 * 559 * fp_status: is the "normal" fp status. 560 * fp_status_fp16: used for half-precision calculations 561 * standard_fp_status : the ARM "Standard FPSCR Value" 562 * 563 * Half-precision operations are governed by a separate 564 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 565 * status structure to control this. 566 * 567 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 568 * round-to-nearest and is used by any operations (generally 569 * Neon) which the architecture defines as controlled by the 570 * standard FPSCR value rather than the FPSCR. 571 * 572 * To avoid having to transfer exception bits around, we simply 573 * say that the FPSCR cumulative exception flags are the logical 574 * OR of the flags in the three fp statuses. This relies on the 575 * only thing which needs to read the exception flags being 576 * an explicit FPSCR read. 577 */ 578 float_status fp_status; 579 float_status fp_status_f16; 580 float_status standard_fp_status; 581 582 /* ZCR_EL[1-3] */ 583 uint64_t zcr_el[4]; 584 } vfp; 585 uint64_t exclusive_addr; 586 uint64_t exclusive_val; 587 uint64_t exclusive_high; 588 589 /* iwMMXt coprocessor state. */ 590 struct { 591 uint64_t regs[16]; 592 uint64_t val; 593 594 uint32_t cregs[16]; 595 } iwmmxt; 596 597 #if defined(CONFIG_USER_ONLY) 598 /* For usermode syscall translation. */ 599 int eabi; 600 #endif 601 602 struct CPUBreakpoint *cpu_breakpoint[16]; 603 struct CPUWatchpoint *cpu_watchpoint[16]; 604 605 /* Fields up to this point are cleared by a CPU reset */ 606 struct {} end_reset_fields; 607 608 CPU_COMMON 609 610 /* Fields after CPU_COMMON are preserved across CPU reset. */ 611 612 /* Internal CPU feature flags. */ 613 uint64_t features; 614 615 /* PMSAv7 MPU */ 616 struct { 617 uint32_t *drbar; 618 uint32_t *drsr; 619 uint32_t *dracr; 620 uint32_t rnr[M_REG_NUM_BANKS]; 621 } pmsav7; 622 623 /* PMSAv8 MPU */ 624 struct { 625 /* The PMSAv8 implementation also shares some PMSAv7 config 626 * and state: 627 * pmsav7.rnr (region number register) 628 * pmsav7_dregion (number of configured regions) 629 */ 630 uint32_t *rbar[M_REG_NUM_BANKS]; 631 uint32_t *rlar[M_REG_NUM_BANKS]; 632 uint32_t mair0[M_REG_NUM_BANKS]; 633 uint32_t mair1[M_REG_NUM_BANKS]; 634 } pmsav8; 635 636 /* v8M SAU */ 637 struct { 638 uint32_t *rbar; 639 uint32_t *rlar; 640 uint32_t rnr; 641 uint32_t ctrl; 642 } sau; 643 644 void *nvic; 645 const struct arm_boot_info *boot_info; 646 /* Store GICv3CPUState to access from this struct */ 647 void *gicv3state; 648 } CPUARMState; 649 650 /** 651 * ARMELChangeHookFn: 652 * type of a function which can be registered via arm_register_el_change_hook() 653 * to get callbacks when the CPU changes its exception level or mode. 654 */ 655 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 656 typedef struct ARMELChangeHook ARMELChangeHook; 657 struct ARMELChangeHook { 658 ARMELChangeHookFn *hook; 659 void *opaque; 660 QLIST_ENTRY(ARMELChangeHook) node; 661 }; 662 663 /* These values map onto the return values for 664 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 665 typedef enum ARMPSCIState { 666 PSCI_ON = 0, 667 PSCI_OFF = 1, 668 PSCI_ON_PENDING = 2 669 } ARMPSCIState; 670 671 /** 672 * ARMCPU: 673 * @env: #CPUARMState 674 * 675 * An ARM CPU core. 676 */ 677 struct ARMCPU { 678 /*< private >*/ 679 CPUState parent_obj; 680 /*< public >*/ 681 682 CPUARMState env; 683 684 /* Coprocessor information */ 685 GHashTable *cp_regs; 686 /* For marshalling (mostly coprocessor) register state between the 687 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 688 * we use these arrays. 689 */ 690 /* List of register indexes managed via these arrays; (full KVM style 691 * 64 bit indexes, not CPRegInfo 32 bit indexes) 692 */ 693 uint64_t *cpreg_indexes; 694 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 695 uint64_t *cpreg_values; 696 /* Length of the indexes, values, reset_values arrays */ 697 int32_t cpreg_array_len; 698 /* These are used only for migration: incoming data arrives in 699 * these fields and is sanity checked in post_load before copying 700 * to the working data structures above. 701 */ 702 uint64_t *cpreg_vmstate_indexes; 703 uint64_t *cpreg_vmstate_values; 704 int32_t cpreg_vmstate_array_len; 705 706 DynamicGDBXMLInfo dyn_xml; 707 708 /* Timers used by the generic (architected) timer */ 709 QEMUTimer *gt_timer[NUM_GTIMERS]; 710 /* GPIO outputs for generic timer */ 711 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 712 /* GPIO output for GICv3 maintenance interrupt signal */ 713 qemu_irq gicv3_maintenance_interrupt; 714 /* GPIO output for the PMU interrupt */ 715 qemu_irq pmu_interrupt; 716 717 /* MemoryRegion to use for secure physical accesses */ 718 MemoryRegion *secure_memory; 719 720 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 721 Object *idau; 722 723 /* 'compatible' string for this CPU for Linux device trees */ 724 const char *dtb_compatible; 725 726 /* PSCI version for this CPU 727 * Bits[31:16] = Major Version 728 * Bits[15:0] = Minor Version 729 */ 730 uint32_t psci_version; 731 732 /* Should CPU start in PSCI powered-off state? */ 733 bool start_powered_off; 734 735 /* Current power state, access guarded by BQL */ 736 ARMPSCIState power_state; 737 738 /* CPU has virtualization extension */ 739 bool has_el2; 740 /* CPU has security extension */ 741 bool has_el3; 742 /* CPU has PMU (Performance Monitor Unit) */ 743 bool has_pmu; 744 745 /* CPU has memory protection unit */ 746 bool has_mpu; 747 /* PMSAv7 MPU number of supported regions */ 748 uint32_t pmsav7_dregion; 749 /* v8M SAU number of supported regions */ 750 uint32_t sau_sregion; 751 752 /* PSCI conduit used to invoke PSCI methods 753 * 0 - disabled, 1 - smc, 2 - hvc 754 */ 755 uint32_t psci_conduit; 756 757 /* For v8M, initial value of the Secure VTOR */ 758 uint32_t init_svtor; 759 760 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 761 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 762 */ 763 uint32_t kvm_target; 764 765 /* KVM init features for this CPU */ 766 uint32_t kvm_init_features[7]; 767 768 /* Uniprocessor system with MP extensions */ 769 bool mp_is_up; 770 771 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 772 * and the probe failed (so we need to report the error in realize) 773 */ 774 bool host_cpu_probe_failed; 775 776 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 777 * register. 778 */ 779 int32_t core_count; 780 781 /* The instance init functions for implementation-specific subclasses 782 * set these fields to specify the implementation-dependent values of 783 * various constant registers and reset values of non-constant 784 * registers. 785 * Some of these might become QOM properties eventually. 786 * Field names match the official register names as defined in the 787 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 788 * is used for reset values of non-constant registers; no reset_ 789 * prefix means a constant register. 790 */ 791 uint32_t midr; 792 uint32_t revidr; 793 uint32_t reset_fpsid; 794 uint32_t mvfr0; 795 uint32_t mvfr1; 796 uint32_t mvfr2; 797 uint32_t ctr; 798 uint32_t reset_sctlr; 799 uint32_t id_pfr0; 800 uint32_t id_pfr1; 801 uint32_t id_dfr0; 802 uint32_t pmceid0; 803 uint32_t pmceid1; 804 uint32_t id_afr0; 805 uint32_t id_mmfr0; 806 uint32_t id_mmfr1; 807 uint32_t id_mmfr2; 808 uint32_t id_mmfr3; 809 uint32_t id_mmfr4; 810 uint32_t id_isar0; 811 uint32_t id_isar1; 812 uint32_t id_isar2; 813 uint32_t id_isar3; 814 uint32_t id_isar4; 815 uint32_t id_isar5; 816 uint64_t id_aa64pfr0; 817 uint64_t id_aa64pfr1; 818 uint64_t id_aa64dfr0; 819 uint64_t id_aa64dfr1; 820 uint64_t id_aa64afr0; 821 uint64_t id_aa64afr1; 822 uint64_t id_aa64isar0; 823 uint64_t id_aa64isar1; 824 uint64_t id_aa64mmfr0; 825 uint64_t id_aa64mmfr1; 826 uint32_t dbgdidr; 827 uint32_t clidr; 828 uint64_t mp_affinity; /* MP ID without feature bits */ 829 /* The elements of this array are the CCSIDR values for each cache, 830 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 831 */ 832 uint32_t ccsidr[16]; 833 uint64_t reset_cbar; 834 uint32_t reset_auxcr; 835 bool reset_hivecs; 836 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 837 uint32_t dcz_blocksize; 838 uint64_t rvbar; 839 840 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 841 int gic_num_lrs; /* number of list registers */ 842 int gic_vpribits; /* number of virtual priority bits */ 843 int gic_vprebits; /* number of virtual preemption bits */ 844 845 /* Whether the cfgend input is high (i.e. this CPU should reset into 846 * big-endian mode). This setting isn't used directly: instead it modifies 847 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 848 * architecture version. 849 */ 850 bool cfgend; 851 852 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 853 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 854 855 int32_t node_id; /* NUMA node this CPU belongs to */ 856 857 /* Used to synchronize KVM and QEMU in-kernel device levels */ 858 uint8_t device_irq_level; 859 }; 860 861 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 862 { 863 return container_of(env, ARMCPU, env); 864 } 865 866 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 867 868 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 869 870 #define ENV_OFFSET offsetof(ARMCPU, env) 871 872 #ifndef CONFIG_USER_ONLY 873 extern const struct VMStateDescription vmstate_arm_cpu; 874 #endif 875 876 void arm_cpu_do_interrupt(CPUState *cpu); 877 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 878 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 879 880 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 881 int flags); 882 883 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 884 MemTxAttrs *attrs); 885 886 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 887 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 888 889 /* Dynamically generates for gdb stub an XML description of the sysregs from 890 * the cp_regs hashtable. Returns the registered sysregs number. 891 */ 892 int arm_gen_dynamic_xml(CPUState *cpu); 893 894 /* Returns the dynamically generated XML for the gdb stub. 895 * Returns a pointer to the XML contents for the specified XML file or NULL 896 * if the XML name doesn't match the predefined one. 897 */ 898 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 899 900 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 901 int cpuid, void *opaque); 902 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 903 int cpuid, void *opaque); 904 905 #ifdef TARGET_AARCH64 906 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 907 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 908 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 909 #endif 910 911 target_ulong do_arm_semihosting(CPUARMState *env); 912 void aarch64_sync_32_to_64(CPUARMState *env); 913 void aarch64_sync_64_to_32(CPUARMState *env); 914 915 static inline bool is_a64(CPUARMState *env) 916 { 917 return env->aarch64; 918 } 919 920 /* you can call this signal handler from your SIGBUS and SIGSEGV 921 signal handlers to inform the virtual CPU of exceptions. non zero 922 is returned if the signal was handled by the virtual CPU. */ 923 int cpu_arm_signal_handler(int host_signum, void *pinfo, 924 void *puc); 925 926 /** 927 * pmccntr_sync 928 * @env: CPUARMState 929 * 930 * Synchronises the counter in the PMCCNTR. This must always be called twice, 931 * once before any action that might affect the timer and again afterwards. 932 * The function is used to swap the state of the register if required. 933 * This only happens when not in user mode (!CONFIG_USER_ONLY) 934 */ 935 void pmccntr_sync(CPUARMState *env); 936 937 /* SCTLR bit meanings. Several bits have been reused in newer 938 * versions of the architecture; in that case we define constants 939 * for both old and new bit meanings. Code which tests against those 940 * bits should probably check or otherwise arrange that the CPU 941 * is the architectural version it expects. 942 */ 943 #define SCTLR_M (1U << 0) 944 #define SCTLR_A (1U << 1) 945 #define SCTLR_C (1U << 2) 946 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 947 #define SCTLR_SA (1U << 3) 948 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 949 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 950 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 951 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 952 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 953 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 954 #define SCTLR_ITD (1U << 7) /* v8 onward */ 955 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 956 #define SCTLR_SED (1U << 8) /* v8 onward */ 957 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 958 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 959 #define SCTLR_F (1U << 10) /* up to v6 */ 960 #define SCTLR_SW (1U << 10) /* v7 onward */ 961 #define SCTLR_Z (1U << 11) 962 #define SCTLR_I (1U << 12) 963 #define SCTLR_V (1U << 13) 964 #define SCTLR_RR (1U << 14) /* up to v7 */ 965 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 966 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 967 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 968 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 969 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 970 #define SCTLR_HA (1U << 17) 971 #define SCTLR_BR (1U << 17) /* PMSA only */ 972 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 973 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 974 #define SCTLR_WXN (1U << 19) 975 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 976 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 977 #define SCTLR_FI (1U << 21) 978 #define SCTLR_U (1U << 22) 979 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 980 #define SCTLR_VE (1U << 24) /* up to v7 */ 981 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 982 #define SCTLR_EE (1U << 25) 983 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 984 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 985 #define SCTLR_NMFI (1U << 27) 986 #define SCTLR_TRE (1U << 28) 987 #define SCTLR_AFE (1U << 29) 988 #define SCTLR_TE (1U << 30) 989 990 #define CPTR_TCPAC (1U << 31) 991 #define CPTR_TTA (1U << 20) 992 #define CPTR_TFP (1U << 10) 993 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 994 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 995 996 #define MDCR_EPMAD (1U << 21) 997 #define MDCR_EDAD (1U << 20) 998 #define MDCR_SPME (1U << 17) 999 #define MDCR_SDD (1U << 16) 1000 #define MDCR_SPD (3U << 14) 1001 #define MDCR_TDRA (1U << 11) 1002 #define MDCR_TDOSA (1U << 10) 1003 #define MDCR_TDA (1U << 9) 1004 #define MDCR_TDE (1U << 8) 1005 #define MDCR_HPME (1U << 7) 1006 #define MDCR_TPM (1U << 6) 1007 #define MDCR_TPMCR (1U << 5) 1008 1009 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1010 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1011 1012 #define CPSR_M (0x1fU) 1013 #define CPSR_T (1U << 5) 1014 #define CPSR_F (1U << 6) 1015 #define CPSR_I (1U << 7) 1016 #define CPSR_A (1U << 8) 1017 #define CPSR_E (1U << 9) 1018 #define CPSR_IT_2_7 (0xfc00U) 1019 #define CPSR_GE (0xfU << 16) 1020 #define CPSR_IL (1U << 20) 1021 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 1022 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 1023 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 1024 * where it is live state but not accessible to the AArch32 code. 1025 */ 1026 #define CPSR_RESERVED (0x7U << 21) 1027 #define CPSR_J (1U << 24) 1028 #define CPSR_IT_0_1 (3U << 25) 1029 #define CPSR_Q (1U << 27) 1030 #define CPSR_V (1U << 28) 1031 #define CPSR_C (1U << 29) 1032 #define CPSR_Z (1U << 30) 1033 #define CPSR_N (1U << 31) 1034 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1035 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1036 1037 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1038 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1039 | CPSR_NZCV) 1040 /* Bits writable in user mode. */ 1041 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1042 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1043 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1044 /* Mask of bits which may be set by exception return copying them from SPSR */ 1045 #define CPSR_ERET_MASK (~CPSR_RESERVED) 1046 1047 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1048 #define XPSR_EXCP 0x1ffU 1049 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1050 #define XPSR_IT_2_7 CPSR_IT_2_7 1051 #define XPSR_GE CPSR_GE 1052 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1053 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1054 #define XPSR_IT_0_1 CPSR_IT_0_1 1055 #define XPSR_Q CPSR_Q 1056 #define XPSR_V CPSR_V 1057 #define XPSR_C CPSR_C 1058 #define XPSR_Z CPSR_Z 1059 #define XPSR_N CPSR_N 1060 #define XPSR_NZCV CPSR_NZCV 1061 #define XPSR_IT CPSR_IT 1062 1063 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1064 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1065 #define TTBCR_PD0 (1U << 4) 1066 #define TTBCR_PD1 (1U << 5) 1067 #define TTBCR_EPD0 (1U << 7) 1068 #define TTBCR_IRGN0 (3U << 8) 1069 #define TTBCR_ORGN0 (3U << 10) 1070 #define TTBCR_SH0 (3U << 12) 1071 #define TTBCR_T1SZ (3U << 16) 1072 #define TTBCR_A1 (1U << 22) 1073 #define TTBCR_EPD1 (1U << 23) 1074 #define TTBCR_IRGN1 (3U << 24) 1075 #define TTBCR_ORGN1 (3U << 26) 1076 #define TTBCR_SH1 (1U << 28) 1077 #define TTBCR_EAE (1U << 31) 1078 1079 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1080 * Only these are valid when in AArch64 mode; in 1081 * AArch32 mode SPSRs are basically CPSR-format. 1082 */ 1083 #define PSTATE_SP (1U) 1084 #define PSTATE_M (0xFU) 1085 #define PSTATE_nRW (1U << 4) 1086 #define PSTATE_F (1U << 6) 1087 #define PSTATE_I (1U << 7) 1088 #define PSTATE_A (1U << 8) 1089 #define PSTATE_D (1U << 9) 1090 #define PSTATE_IL (1U << 20) 1091 #define PSTATE_SS (1U << 21) 1092 #define PSTATE_V (1U << 28) 1093 #define PSTATE_C (1U << 29) 1094 #define PSTATE_Z (1U << 30) 1095 #define PSTATE_N (1U << 31) 1096 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1097 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1098 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 1099 /* Mode values for AArch64 */ 1100 #define PSTATE_MODE_EL3h 13 1101 #define PSTATE_MODE_EL3t 12 1102 #define PSTATE_MODE_EL2h 9 1103 #define PSTATE_MODE_EL2t 8 1104 #define PSTATE_MODE_EL1h 5 1105 #define PSTATE_MODE_EL1t 4 1106 #define PSTATE_MODE_EL0t 0 1107 1108 /* Write a new value to v7m.exception, thus transitioning into or out 1109 * of Handler mode; this may result in a change of active stack pointer. 1110 */ 1111 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1112 1113 /* Map EL and handler into a PSTATE_MODE. */ 1114 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1115 { 1116 return (el << 2) | handler; 1117 } 1118 1119 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1120 * interprocessing, so we don't attempt to sync with the cpsr state used by 1121 * the 32 bit decoder. 1122 */ 1123 static inline uint32_t pstate_read(CPUARMState *env) 1124 { 1125 int ZF; 1126 1127 ZF = (env->ZF == 0); 1128 return (env->NF & 0x80000000) | (ZF << 30) 1129 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1130 | env->pstate | env->daif; 1131 } 1132 1133 static inline void pstate_write(CPUARMState *env, uint32_t val) 1134 { 1135 env->ZF = (~val) & PSTATE_Z; 1136 env->NF = val; 1137 env->CF = (val >> 29) & 1; 1138 env->VF = (val << 3) & 0x80000000; 1139 env->daif = val & PSTATE_DAIF; 1140 env->pstate = val & ~CACHED_PSTATE_BITS; 1141 } 1142 1143 /* Return the current CPSR value. */ 1144 uint32_t cpsr_read(CPUARMState *env); 1145 1146 typedef enum CPSRWriteType { 1147 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1148 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1149 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1150 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1151 } CPSRWriteType; 1152 1153 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1154 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1155 CPSRWriteType write_type); 1156 1157 /* Return the current xPSR value. */ 1158 static inline uint32_t xpsr_read(CPUARMState *env) 1159 { 1160 int ZF; 1161 ZF = (env->ZF == 0); 1162 return (env->NF & 0x80000000) | (ZF << 30) 1163 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1164 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1165 | ((env->condexec_bits & 0xfc) << 8) 1166 | env->v7m.exception; 1167 } 1168 1169 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1170 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1171 { 1172 if (mask & XPSR_NZCV) { 1173 env->ZF = (~val) & XPSR_Z; 1174 env->NF = val; 1175 env->CF = (val >> 29) & 1; 1176 env->VF = (val << 3) & 0x80000000; 1177 } 1178 if (mask & XPSR_Q) { 1179 env->QF = ((val & XPSR_Q) != 0); 1180 } 1181 if (mask & XPSR_T) { 1182 env->thumb = ((val & XPSR_T) != 0); 1183 } 1184 if (mask & XPSR_IT_0_1) { 1185 env->condexec_bits &= ~3; 1186 env->condexec_bits |= (val >> 25) & 3; 1187 } 1188 if (mask & XPSR_IT_2_7) { 1189 env->condexec_bits &= 3; 1190 env->condexec_bits |= (val >> 8) & 0xfc; 1191 } 1192 if (mask & XPSR_EXCP) { 1193 /* Note that this only happens on exception exit */ 1194 write_v7m_exception(env, val & XPSR_EXCP); 1195 } 1196 } 1197 1198 #define HCR_VM (1ULL << 0) 1199 #define HCR_SWIO (1ULL << 1) 1200 #define HCR_PTW (1ULL << 2) 1201 #define HCR_FMO (1ULL << 3) 1202 #define HCR_IMO (1ULL << 4) 1203 #define HCR_AMO (1ULL << 5) 1204 #define HCR_VF (1ULL << 6) 1205 #define HCR_VI (1ULL << 7) 1206 #define HCR_VSE (1ULL << 8) 1207 #define HCR_FB (1ULL << 9) 1208 #define HCR_BSU_MASK (3ULL << 10) 1209 #define HCR_DC (1ULL << 12) 1210 #define HCR_TWI (1ULL << 13) 1211 #define HCR_TWE (1ULL << 14) 1212 #define HCR_TID0 (1ULL << 15) 1213 #define HCR_TID1 (1ULL << 16) 1214 #define HCR_TID2 (1ULL << 17) 1215 #define HCR_TID3 (1ULL << 18) 1216 #define HCR_TSC (1ULL << 19) 1217 #define HCR_TIDCP (1ULL << 20) 1218 #define HCR_TACR (1ULL << 21) 1219 #define HCR_TSW (1ULL << 22) 1220 #define HCR_TPC (1ULL << 23) 1221 #define HCR_TPU (1ULL << 24) 1222 #define HCR_TTLB (1ULL << 25) 1223 #define HCR_TVM (1ULL << 26) 1224 #define HCR_TGE (1ULL << 27) 1225 #define HCR_TDZ (1ULL << 28) 1226 #define HCR_HCD (1ULL << 29) 1227 #define HCR_TRVM (1ULL << 30) 1228 #define HCR_RW (1ULL << 31) 1229 #define HCR_CD (1ULL << 32) 1230 #define HCR_ID (1ULL << 33) 1231 #define HCR_MASK ((1ULL << 34) - 1) 1232 1233 #define SCR_NS (1U << 0) 1234 #define SCR_IRQ (1U << 1) 1235 #define SCR_FIQ (1U << 2) 1236 #define SCR_EA (1U << 3) 1237 #define SCR_FW (1U << 4) 1238 #define SCR_AW (1U << 5) 1239 #define SCR_NET (1U << 6) 1240 #define SCR_SMD (1U << 7) 1241 #define SCR_HCE (1U << 8) 1242 #define SCR_SIF (1U << 9) 1243 #define SCR_RW (1U << 10) 1244 #define SCR_ST (1U << 11) 1245 #define SCR_TWI (1U << 12) 1246 #define SCR_TWE (1U << 13) 1247 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1248 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1249 1250 /* Return the current FPSCR value. */ 1251 uint32_t vfp_get_fpscr(CPUARMState *env); 1252 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1253 1254 /* FPCR, Floating Point Control Register 1255 * FPSR, Floating Poiht Status Register 1256 * 1257 * For A64 the FPSCR is split into two logically distinct registers, 1258 * FPCR and FPSR. However since they still use non-overlapping bits 1259 * we store the underlying state in fpscr and just mask on read/write. 1260 */ 1261 #define FPSR_MASK 0xf800009f 1262 #define FPCR_MASK 0x07f79f00 1263 1264 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1265 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1266 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1267 1268 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1269 { 1270 return vfp_get_fpscr(env) & FPSR_MASK; 1271 } 1272 1273 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1274 { 1275 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1276 vfp_set_fpscr(env, new_fpscr); 1277 } 1278 1279 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1280 { 1281 return vfp_get_fpscr(env) & FPCR_MASK; 1282 } 1283 1284 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1285 { 1286 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1287 vfp_set_fpscr(env, new_fpscr); 1288 } 1289 1290 enum arm_cpu_mode { 1291 ARM_CPU_MODE_USR = 0x10, 1292 ARM_CPU_MODE_FIQ = 0x11, 1293 ARM_CPU_MODE_IRQ = 0x12, 1294 ARM_CPU_MODE_SVC = 0x13, 1295 ARM_CPU_MODE_MON = 0x16, 1296 ARM_CPU_MODE_ABT = 0x17, 1297 ARM_CPU_MODE_HYP = 0x1a, 1298 ARM_CPU_MODE_UND = 0x1b, 1299 ARM_CPU_MODE_SYS = 0x1f 1300 }; 1301 1302 /* VFP system registers. */ 1303 #define ARM_VFP_FPSID 0 1304 #define ARM_VFP_FPSCR 1 1305 #define ARM_VFP_MVFR2 5 1306 #define ARM_VFP_MVFR1 6 1307 #define ARM_VFP_MVFR0 7 1308 #define ARM_VFP_FPEXC 8 1309 #define ARM_VFP_FPINST 9 1310 #define ARM_VFP_FPINST2 10 1311 1312 /* iwMMXt coprocessor control registers. */ 1313 #define ARM_IWMMXT_wCID 0 1314 #define ARM_IWMMXT_wCon 1 1315 #define ARM_IWMMXT_wCSSF 2 1316 #define ARM_IWMMXT_wCASF 3 1317 #define ARM_IWMMXT_wCGR0 8 1318 #define ARM_IWMMXT_wCGR1 9 1319 #define ARM_IWMMXT_wCGR2 10 1320 #define ARM_IWMMXT_wCGR3 11 1321 1322 /* V7M CCR bits */ 1323 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1324 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1325 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1326 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1327 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1328 FIELD(V7M_CCR, STKALIGN, 9, 1) 1329 FIELD(V7M_CCR, DC, 16, 1) 1330 FIELD(V7M_CCR, IC, 17, 1) 1331 1332 /* V7M SCR bits */ 1333 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1334 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1335 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1336 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1337 1338 /* V7M AIRCR bits */ 1339 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1340 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1341 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1342 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1343 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1344 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1345 FIELD(V7M_AIRCR, PRIS, 14, 1) 1346 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1347 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1348 1349 /* V7M CFSR bits for MMFSR */ 1350 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1351 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1352 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1353 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1354 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1355 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1356 1357 /* V7M CFSR bits for BFSR */ 1358 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1359 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1360 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1361 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1362 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1363 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1364 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1365 1366 /* V7M CFSR bits for UFSR */ 1367 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1368 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1369 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1370 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1371 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1372 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1373 1374 /* V7M CFSR bit masks covering all of the subregister bits */ 1375 FIELD(V7M_CFSR, MMFSR, 0, 8) 1376 FIELD(V7M_CFSR, BFSR, 8, 8) 1377 FIELD(V7M_CFSR, UFSR, 16, 16) 1378 1379 /* V7M HFSR bits */ 1380 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1381 FIELD(V7M_HFSR, FORCED, 30, 1) 1382 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1383 1384 /* V7M DFSR bits */ 1385 FIELD(V7M_DFSR, HALTED, 0, 1) 1386 FIELD(V7M_DFSR, BKPT, 1, 1) 1387 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1388 FIELD(V7M_DFSR, VCATCH, 3, 1) 1389 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1390 1391 /* V7M SFSR bits */ 1392 FIELD(V7M_SFSR, INVEP, 0, 1) 1393 FIELD(V7M_SFSR, INVIS, 1, 1) 1394 FIELD(V7M_SFSR, INVER, 2, 1) 1395 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1396 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1397 FIELD(V7M_SFSR, LSPERR, 5, 1) 1398 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1399 FIELD(V7M_SFSR, LSERR, 7, 1) 1400 1401 /* v7M MPU_CTRL bits */ 1402 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1403 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1404 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1405 1406 /* v7M CLIDR bits */ 1407 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1408 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1409 FIELD(V7M_CLIDR, LOC, 24, 3) 1410 FIELD(V7M_CLIDR, LOUU, 27, 3) 1411 FIELD(V7M_CLIDR, ICB, 30, 2) 1412 1413 FIELD(V7M_CSSELR, IND, 0, 1) 1414 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1415 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1416 * define a mask for this and check that it doesn't permit running off 1417 * the end of the array. 1418 */ 1419 FIELD(V7M_CSSELR, INDEX, 0, 4) 1420 1421 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1422 1423 /* If adding a feature bit which corresponds to a Linux ELF 1424 * HWCAP bit, remember to update the feature-bit-to-hwcap 1425 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1426 */ 1427 enum arm_features { 1428 ARM_FEATURE_VFP, 1429 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1430 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1431 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1432 ARM_FEATURE_V6, 1433 ARM_FEATURE_V6K, 1434 ARM_FEATURE_V7, 1435 ARM_FEATURE_THUMB2, 1436 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1437 ARM_FEATURE_VFP3, 1438 ARM_FEATURE_VFP_FP16, 1439 ARM_FEATURE_NEON, 1440 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1441 ARM_FEATURE_M, /* Microcontroller profile. */ 1442 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1443 ARM_FEATURE_THUMB2EE, 1444 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1445 ARM_FEATURE_V4T, 1446 ARM_FEATURE_V5, 1447 ARM_FEATURE_STRONGARM, 1448 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1449 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1450 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1451 ARM_FEATURE_GENERIC_TIMER, 1452 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1453 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1454 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1455 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1456 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1457 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1458 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1459 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1460 ARM_FEATURE_V8, 1461 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1462 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1463 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1464 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1465 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1466 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1467 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1468 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1469 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1470 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1471 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1472 ARM_FEATURE_PMU, /* has PMU support */ 1473 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1474 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1475 ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ 1476 ARM_FEATURE_SVE, /* has Scalable Vector Extension */ 1477 ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensions */ 1478 ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ 1479 ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ 1480 ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ 1481 ARM_FEATURE_V8_ATOMICS, /* ARMv8.1-Atomics feature */ 1482 ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ 1483 ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ 1484 ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ 1485 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1486 }; 1487 1488 static inline int arm_feature(CPUARMState *env, int feature) 1489 { 1490 return (env->features & (1ULL << feature)) != 0; 1491 } 1492 1493 #if !defined(CONFIG_USER_ONLY) 1494 /* Return true if exception levels below EL3 are in secure state, 1495 * or would be following an exception return to that level. 1496 * Unlike arm_is_secure() (which is always a question about the 1497 * _current_ state of the CPU) this doesn't care about the current 1498 * EL or mode. 1499 */ 1500 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1501 { 1502 if (arm_feature(env, ARM_FEATURE_EL3)) { 1503 return !(env->cp15.scr_el3 & SCR_NS); 1504 } else { 1505 /* If EL3 is not supported then the secure state is implementation 1506 * defined, in which case QEMU defaults to non-secure. 1507 */ 1508 return false; 1509 } 1510 } 1511 1512 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1513 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1514 { 1515 if (arm_feature(env, ARM_FEATURE_EL3)) { 1516 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1517 /* CPU currently in AArch64 state and EL3 */ 1518 return true; 1519 } else if (!is_a64(env) && 1520 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1521 /* CPU currently in AArch32 state and monitor mode */ 1522 return true; 1523 } 1524 } 1525 return false; 1526 } 1527 1528 /* Return true if the processor is in secure state */ 1529 static inline bool arm_is_secure(CPUARMState *env) 1530 { 1531 if (arm_is_el3_or_mon(env)) { 1532 return true; 1533 } 1534 return arm_is_secure_below_el3(env); 1535 } 1536 1537 #else 1538 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1539 { 1540 return false; 1541 } 1542 1543 static inline bool arm_is_secure(CPUARMState *env) 1544 { 1545 return false; 1546 } 1547 #endif 1548 1549 /* Return true if the specified exception level is running in AArch64 state. */ 1550 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1551 { 1552 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1553 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1554 */ 1555 assert(el >= 1 && el <= 3); 1556 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1557 1558 /* The highest exception level is always at the maximum supported 1559 * register width, and then lower levels have a register width controlled 1560 * by bits in the SCR or HCR registers. 1561 */ 1562 if (el == 3) { 1563 return aa64; 1564 } 1565 1566 if (arm_feature(env, ARM_FEATURE_EL3)) { 1567 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1568 } 1569 1570 if (el == 2) { 1571 return aa64; 1572 } 1573 1574 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1575 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1576 } 1577 1578 return aa64; 1579 } 1580 1581 /* Function for determing whether guest cp register reads and writes should 1582 * access the secure or non-secure bank of a cp register. When EL3 is 1583 * operating in AArch32 state, the NS-bit determines whether the secure 1584 * instance of a cp register should be used. When EL3 is AArch64 (or if 1585 * it doesn't exist at all) then there is no register banking, and all 1586 * accesses are to the non-secure version. 1587 */ 1588 static inline bool access_secure_reg(CPUARMState *env) 1589 { 1590 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1591 !arm_el_is_aa64(env, 3) && 1592 !(env->cp15.scr_el3 & SCR_NS)); 1593 1594 return ret; 1595 } 1596 1597 /* Macros for accessing a specified CP register bank */ 1598 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1599 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1600 1601 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1602 do { \ 1603 if (_secure) { \ 1604 (_env)->cp15._regname##_s = (_val); \ 1605 } else { \ 1606 (_env)->cp15._regname##_ns = (_val); \ 1607 } \ 1608 } while (0) 1609 1610 /* Macros for automatically accessing a specific CP register bank depending on 1611 * the current secure state of the system. These macros are not intended for 1612 * supporting instruction translation reads/writes as these are dependent 1613 * solely on the SCR.NS bit and not the mode. 1614 */ 1615 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1616 A32_BANKED_REG_GET((_env), _regname, \ 1617 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1618 1619 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1620 A32_BANKED_REG_SET((_env), _regname, \ 1621 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1622 (_val)) 1623 1624 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1625 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1626 uint32_t cur_el, bool secure); 1627 1628 /* Interface between CPU and Interrupt controller. */ 1629 #ifndef CONFIG_USER_ONLY 1630 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1631 #else 1632 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1633 { 1634 return true; 1635 } 1636 #endif 1637 /** 1638 * armv7m_nvic_set_pending: mark the specified exception as pending 1639 * @opaque: the NVIC 1640 * @irq: the exception number to mark pending 1641 * @secure: false for non-banked exceptions or for the nonsecure 1642 * version of a banked exception, true for the secure version of a banked 1643 * exception. 1644 * 1645 * Marks the specified exception as pending. Note that we will assert() 1646 * if @secure is true and @irq does not specify one of the fixed set 1647 * of architecturally banked exceptions. 1648 */ 1649 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1650 /** 1651 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 1652 * @opaque: the NVIC 1653 * @irq: the exception number to mark pending 1654 * @secure: false for non-banked exceptions or for the nonsecure 1655 * version of a banked exception, true for the secure version of a banked 1656 * exception. 1657 * 1658 * Similar to armv7m_nvic_set_pending(), but specifically for derived 1659 * exceptions (exceptions generated in the course of trying to take 1660 * a different exception). 1661 */ 1662 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 1663 /** 1664 * armv7m_nvic_get_pending_irq_info: return highest priority pending 1665 * exception, and whether it targets Secure state 1666 * @opaque: the NVIC 1667 * @pirq: set to pending exception number 1668 * @ptargets_secure: set to whether pending exception targets Secure 1669 * 1670 * This function writes the number of the highest priority pending 1671 * exception (the one which would be made active by 1672 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 1673 * to true if the current highest priority pending exception should 1674 * be taken to Secure state, false for NS. 1675 */ 1676 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 1677 bool *ptargets_secure); 1678 /** 1679 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 1680 * @opaque: the NVIC 1681 * 1682 * Move the current highest priority pending exception from the pending 1683 * state to the active state, and update v7m.exception to indicate that 1684 * it is the exception currently being handled. 1685 */ 1686 void armv7m_nvic_acknowledge_irq(void *opaque); 1687 /** 1688 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1689 * @opaque: the NVIC 1690 * @irq: the exception number to complete 1691 * @secure: true if this exception was secure 1692 * 1693 * Returns: -1 if the irq was not active 1694 * 1 if completing this irq brought us back to base (no active irqs) 1695 * 0 if there is still an irq active after this one was completed 1696 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1697 */ 1698 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 1699 /** 1700 * armv7m_nvic_raw_execution_priority: return the raw execution priority 1701 * @opaque: the NVIC 1702 * 1703 * Returns: the raw execution priority as defined by the v8M architecture. 1704 * This is the execution priority minus the effects of AIRCR.PRIS, 1705 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 1706 * (v8M ARM ARM I_PKLD.) 1707 */ 1708 int armv7m_nvic_raw_execution_priority(void *opaque); 1709 /** 1710 * armv7m_nvic_neg_prio_requested: return true if the requested execution 1711 * priority is negative for the specified security state. 1712 * @opaque: the NVIC 1713 * @secure: the security state to test 1714 * This corresponds to the pseudocode IsReqExecPriNeg(). 1715 */ 1716 #ifndef CONFIG_USER_ONLY 1717 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 1718 #else 1719 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 1720 { 1721 return false; 1722 } 1723 #endif 1724 1725 /* Interface for defining coprocessor registers. 1726 * Registers are defined in tables of arm_cp_reginfo structs 1727 * which are passed to define_arm_cp_regs(). 1728 */ 1729 1730 /* When looking up a coprocessor register we look for it 1731 * via an integer which encodes all of: 1732 * coprocessor number 1733 * Crn, Crm, opc1, opc2 fields 1734 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1735 * or via MRRC/MCRR?) 1736 * non-secure/secure bank (AArch32 only) 1737 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1738 * (In this case crn and opc2 should be zero.) 1739 * For AArch64, there is no 32/64 bit size distinction; 1740 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1741 * and 4 bit CRn and CRm. The encoding patterns are chosen 1742 * to be easy to convert to and from the KVM encodings, and also 1743 * so that the hashtable can contain both AArch32 and AArch64 1744 * registers (to allow for interprocessing where we might run 1745 * 32 bit code on a 64 bit core). 1746 */ 1747 /* This bit is private to our hashtable cpreg; in KVM register 1748 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1749 * in the upper bits of the 64 bit ID. 1750 */ 1751 #define CP_REG_AA64_SHIFT 28 1752 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1753 1754 /* To enable banking of coprocessor registers depending on ns-bit we 1755 * add a bit to distinguish between secure and non-secure cpregs in the 1756 * hashtable. 1757 */ 1758 #define CP_REG_NS_SHIFT 29 1759 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1760 1761 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1762 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1763 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1764 1765 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1766 (CP_REG_AA64_MASK | \ 1767 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1768 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1769 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1770 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1771 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1772 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1773 1774 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1775 * version used as a key for the coprocessor register hashtable 1776 */ 1777 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1778 { 1779 uint32_t cpregid = kvmid; 1780 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1781 cpregid |= CP_REG_AA64_MASK; 1782 } else { 1783 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1784 cpregid |= (1 << 15); 1785 } 1786 1787 /* KVM is always non-secure so add the NS flag on AArch32 register 1788 * entries. 1789 */ 1790 cpregid |= 1 << CP_REG_NS_SHIFT; 1791 } 1792 return cpregid; 1793 } 1794 1795 /* Convert a truncated 32 bit hashtable key into the full 1796 * 64 bit KVM register ID. 1797 */ 1798 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1799 { 1800 uint64_t kvmid; 1801 1802 if (cpregid & CP_REG_AA64_MASK) { 1803 kvmid = cpregid & ~CP_REG_AA64_MASK; 1804 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1805 } else { 1806 kvmid = cpregid & ~(1 << 15); 1807 if (cpregid & (1 << 15)) { 1808 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1809 } else { 1810 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1811 } 1812 } 1813 return kvmid; 1814 } 1815 1816 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1817 * special-behaviour cp reg and bits [11..8] indicate what behaviour 1818 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1819 * TCG can assume the value to be constant (ie load at translate time) 1820 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1821 * indicates that the TB should not be ended after a write to this register 1822 * (the default is that the TB ends after cp writes). OVERRIDE permits 1823 * a register definition to override a previous definition for the 1824 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1825 * old must have the OVERRIDE bit set. 1826 * ALIAS indicates that this register is an alias view of some underlying 1827 * state which is also visible via another register, and that the other 1828 * register is handling migration and reset; registers marked ALIAS will not be 1829 * migrated but may have their state set by syncing of register state from KVM. 1830 * NO_RAW indicates that this register has no underlying state and does not 1831 * support raw access for state saving/loading; it will not be used for either 1832 * migration or KVM state synchronization. (Typically this is for "registers" 1833 * which are actually used as instructions for cache maintenance and so on.) 1834 * IO indicates that this register does I/O and therefore its accesses 1835 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1836 * registers which implement clocks or timers require this. 1837 */ 1838 #define ARM_CP_SPECIAL 0x0001 1839 #define ARM_CP_CONST 0x0002 1840 #define ARM_CP_64BIT 0x0004 1841 #define ARM_CP_SUPPRESS_TB_END 0x0008 1842 #define ARM_CP_OVERRIDE 0x0010 1843 #define ARM_CP_ALIAS 0x0020 1844 #define ARM_CP_IO 0x0040 1845 #define ARM_CP_NO_RAW 0x0080 1846 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 1847 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 1848 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 1849 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 1850 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 1851 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1852 #define ARM_CP_FPU 0x1000 1853 #define ARM_CP_SVE 0x2000 1854 #define ARM_CP_NO_GDB 0x4000 1855 /* Used only as a terminator for ARMCPRegInfo lists */ 1856 #define ARM_CP_SENTINEL 0xffff 1857 /* Mask of only the flag bits in a type field */ 1858 #define ARM_CP_FLAG_MASK 0x70ff 1859 1860 /* Valid values for ARMCPRegInfo state field, indicating which of 1861 * the AArch32 and AArch64 execution states this register is visible in. 1862 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1863 * If the reginfo is declared to be visible in both states then a second 1864 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1865 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1866 * Note that we rely on the values of these enums as we iterate through 1867 * the various states in some places. 1868 */ 1869 enum { 1870 ARM_CP_STATE_AA32 = 0, 1871 ARM_CP_STATE_AA64 = 1, 1872 ARM_CP_STATE_BOTH = 2, 1873 }; 1874 1875 /* ARM CP register secure state flags. These flags identify security state 1876 * attributes for a given CP register entry. 1877 * The existence of both or neither secure and non-secure flags indicates that 1878 * the register has both a secure and non-secure hash entry. A single one of 1879 * these flags causes the register to only be hashed for the specified 1880 * security state. 1881 * Although definitions may have any combination of the S/NS bits, each 1882 * registered entry will only have one to identify whether the entry is secure 1883 * or non-secure. 1884 */ 1885 enum { 1886 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1887 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1888 }; 1889 1890 /* Return true if cptype is a valid type field. This is used to try to 1891 * catch errors where the sentinel has been accidentally left off the end 1892 * of a list of registers. 1893 */ 1894 static inline bool cptype_valid(int cptype) 1895 { 1896 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1897 || ((cptype & ARM_CP_SPECIAL) && 1898 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1899 } 1900 1901 /* Access rights: 1902 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1903 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1904 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1905 * (ie any of the privileged modes in Secure state, or Monitor mode). 1906 * If a register is accessible in one privilege level it's always accessible 1907 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1908 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1909 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1910 * terminology a little and call this PL3. 1911 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1912 * with the ELx exception levels. 1913 * 1914 * If access permissions for a register are more complex than can be 1915 * described with these bits, then use a laxer set of restrictions, and 1916 * do the more restrictive/complex check inside a helper function. 1917 */ 1918 #define PL3_R 0x80 1919 #define PL3_W 0x40 1920 #define PL2_R (0x20 | PL3_R) 1921 #define PL2_W (0x10 | PL3_W) 1922 #define PL1_R (0x08 | PL2_R) 1923 #define PL1_W (0x04 | PL2_W) 1924 #define PL0_R (0x02 | PL1_R) 1925 #define PL0_W (0x01 | PL1_W) 1926 1927 #define PL3_RW (PL3_R | PL3_W) 1928 #define PL2_RW (PL2_R | PL2_W) 1929 #define PL1_RW (PL1_R | PL1_W) 1930 #define PL0_RW (PL0_R | PL0_W) 1931 1932 /* Return the highest implemented Exception Level */ 1933 static inline int arm_highest_el(CPUARMState *env) 1934 { 1935 if (arm_feature(env, ARM_FEATURE_EL3)) { 1936 return 3; 1937 } 1938 if (arm_feature(env, ARM_FEATURE_EL2)) { 1939 return 2; 1940 } 1941 return 1; 1942 } 1943 1944 /* Return true if a v7M CPU is in Handler mode */ 1945 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 1946 { 1947 return env->v7m.exception != 0; 1948 } 1949 1950 /* Return the current Exception Level (as per ARMv8; note that this differs 1951 * from the ARMv7 Privilege Level). 1952 */ 1953 static inline int arm_current_el(CPUARMState *env) 1954 { 1955 if (arm_feature(env, ARM_FEATURE_M)) { 1956 return arm_v7m_is_handler_mode(env) || 1957 !(env->v7m.control[env->v7m.secure] & 1); 1958 } 1959 1960 if (is_a64(env)) { 1961 return extract32(env->pstate, 2, 2); 1962 } 1963 1964 switch (env->uncached_cpsr & 0x1f) { 1965 case ARM_CPU_MODE_USR: 1966 return 0; 1967 case ARM_CPU_MODE_HYP: 1968 return 2; 1969 case ARM_CPU_MODE_MON: 1970 return 3; 1971 default: 1972 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1973 /* If EL3 is 32-bit then all secure privileged modes run in 1974 * EL3 1975 */ 1976 return 3; 1977 } 1978 1979 return 1; 1980 } 1981 } 1982 1983 typedef struct ARMCPRegInfo ARMCPRegInfo; 1984 1985 typedef enum CPAccessResult { 1986 /* Access is permitted */ 1987 CP_ACCESS_OK = 0, 1988 /* Access fails due to a configurable trap or enable which would 1989 * result in a categorized exception syndrome giving information about 1990 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1991 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1992 * PL1 if in EL0, otherwise to the current EL). 1993 */ 1994 CP_ACCESS_TRAP = 1, 1995 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1996 * Note that this is not a catch-all case -- the set of cases which may 1997 * result in this failure is specifically defined by the architecture. 1998 */ 1999 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2000 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2001 CP_ACCESS_TRAP_EL2 = 3, 2002 CP_ACCESS_TRAP_EL3 = 4, 2003 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2004 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2005 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2006 /* Access fails and results in an exception syndrome for an FP access, 2007 * trapped directly to EL2 or EL3 2008 */ 2009 CP_ACCESS_TRAP_FP_EL2 = 7, 2010 CP_ACCESS_TRAP_FP_EL3 = 8, 2011 } CPAccessResult; 2012 2013 /* Access functions for coprocessor registers. These cannot fail and 2014 * may not raise exceptions. 2015 */ 2016 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2017 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2018 uint64_t value); 2019 /* Access permission check functions for coprocessor registers. */ 2020 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2021 const ARMCPRegInfo *opaque, 2022 bool isread); 2023 /* Hook function for register reset */ 2024 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2025 2026 #define CP_ANY 0xff 2027 2028 /* Definition of an ARM coprocessor register */ 2029 struct ARMCPRegInfo { 2030 /* Name of register (useful mainly for debugging, need not be unique) */ 2031 const char *name; 2032 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2033 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2034 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2035 * will be decoded to this register. The register read and write 2036 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2037 * used by the program, so it is possible to register a wildcard and 2038 * then behave differently on read/write if necessary. 2039 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2040 * must both be zero. 2041 * For AArch64-visible registers, opc0 is also used. 2042 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2043 * way to distinguish (for KVM's benefit) guest-visible system registers 2044 * from demuxed ones provided to preserve the "no side effects on 2045 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2046 * visible (to match KVM's encoding); cp==0 will be converted to 2047 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2048 */ 2049 uint8_t cp; 2050 uint8_t crn; 2051 uint8_t crm; 2052 uint8_t opc0; 2053 uint8_t opc1; 2054 uint8_t opc2; 2055 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2056 int state; 2057 /* Register type: ARM_CP_* bits/values */ 2058 int type; 2059 /* Access rights: PL*_[RW] */ 2060 int access; 2061 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2062 int secure; 2063 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2064 * this register was defined: can be used to hand data through to the 2065 * register read/write functions, since they are passed the ARMCPRegInfo*. 2066 */ 2067 void *opaque; 2068 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2069 * fieldoffset is non-zero, the reset value of the register. 2070 */ 2071 uint64_t resetvalue; 2072 /* Offset of the field in CPUARMState for this register. 2073 * 2074 * This is not needed if either: 2075 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2076 * 2. both readfn and writefn are specified 2077 */ 2078 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2079 2080 /* Offsets of the secure and non-secure fields in CPUARMState for the 2081 * register if it is banked. These fields are only used during the static 2082 * registration of a register. During hashing the bank associated 2083 * with a given security state is copied to fieldoffset which is used from 2084 * there on out. 2085 * 2086 * It is expected that register definitions use either fieldoffset or 2087 * bank_fieldoffsets in the definition but not both. It is also expected 2088 * that both bank offsets are set when defining a banked register. This 2089 * use indicates that a register is banked. 2090 */ 2091 ptrdiff_t bank_fieldoffsets[2]; 2092 2093 /* Function for making any access checks for this register in addition to 2094 * those specified by the 'access' permissions bits. If NULL, no extra 2095 * checks required. The access check is performed at runtime, not at 2096 * translate time. 2097 */ 2098 CPAccessFn *accessfn; 2099 /* Function for handling reads of this register. If NULL, then reads 2100 * will be done by loading from the offset into CPUARMState specified 2101 * by fieldoffset. 2102 */ 2103 CPReadFn *readfn; 2104 /* Function for handling writes of this register. If NULL, then writes 2105 * will be done by writing to the offset into CPUARMState specified 2106 * by fieldoffset. 2107 */ 2108 CPWriteFn *writefn; 2109 /* Function for doing a "raw" read; used when we need to copy 2110 * coprocessor state to the kernel for KVM or out for 2111 * migration. This only needs to be provided if there is also a 2112 * readfn and it has side effects (for instance clear-on-read bits). 2113 */ 2114 CPReadFn *raw_readfn; 2115 /* Function for doing a "raw" write; used when we need to copy KVM 2116 * kernel coprocessor state into userspace, or for inbound 2117 * migration. This only needs to be provided if there is also a 2118 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2119 * or similar behaviour. 2120 */ 2121 CPWriteFn *raw_writefn; 2122 /* Function for resetting the register. If NULL, then reset will be done 2123 * by writing resetvalue to the field specified in fieldoffset. If 2124 * fieldoffset is 0 then no reset will be done. 2125 */ 2126 CPResetFn *resetfn; 2127 }; 2128 2129 /* Macros which are lvalues for the field in CPUARMState for the 2130 * ARMCPRegInfo *ri. 2131 */ 2132 #define CPREG_FIELD32(env, ri) \ 2133 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2134 #define CPREG_FIELD64(env, ri) \ 2135 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2136 2137 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2138 2139 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2140 const ARMCPRegInfo *regs, void *opaque); 2141 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2142 const ARMCPRegInfo *regs, void *opaque); 2143 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2144 { 2145 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2146 } 2147 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2148 { 2149 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2150 } 2151 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2152 2153 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2154 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2155 uint64_t value); 2156 /* CPReadFn that can be used for read-as-zero behaviour */ 2157 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2158 2159 /* CPResetFn that does nothing, for use if no reset is required even 2160 * if fieldoffset is non zero. 2161 */ 2162 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2163 2164 /* Return true if this reginfo struct's field in the cpu state struct 2165 * is 64 bits wide. 2166 */ 2167 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2168 { 2169 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2170 } 2171 2172 static inline bool cp_access_ok(int current_el, 2173 const ARMCPRegInfo *ri, int isread) 2174 { 2175 return (ri->access >> ((current_el * 2) + isread)) & 1; 2176 } 2177 2178 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2179 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2180 2181 /** 2182 * write_list_to_cpustate 2183 * @cpu: ARMCPU 2184 * 2185 * For each register listed in the ARMCPU cpreg_indexes list, write 2186 * its value from the cpreg_values list into the ARMCPUState structure. 2187 * This updates TCG's working data structures from KVM data or 2188 * from incoming migration state. 2189 * 2190 * Returns: true if all register values were updated correctly, 2191 * false if some register was unknown or could not be written. 2192 * Note that we do not stop early on failure -- we will attempt 2193 * writing all registers in the list. 2194 */ 2195 bool write_list_to_cpustate(ARMCPU *cpu); 2196 2197 /** 2198 * write_cpustate_to_list: 2199 * @cpu: ARMCPU 2200 * 2201 * For each register listed in the ARMCPU cpreg_indexes list, write 2202 * its value from the ARMCPUState structure into the cpreg_values list. 2203 * This is used to copy info from TCG's working data structures into 2204 * KVM or for outbound migration. 2205 * 2206 * Returns: true if all register values were read correctly, 2207 * false if some register was unknown or could not be read. 2208 * Note that we do not stop early on failure -- we will attempt 2209 * reading all registers in the list. 2210 */ 2211 bool write_cpustate_to_list(ARMCPU *cpu); 2212 2213 #define ARM_CPUID_TI915T 0x54029152 2214 #define ARM_CPUID_TI925T 0x54029252 2215 2216 #if defined(CONFIG_USER_ONLY) 2217 #define TARGET_PAGE_BITS 12 2218 #else 2219 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2220 * have to support 1K tiny pages. 2221 */ 2222 #define TARGET_PAGE_BITS_VARY 2223 #define TARGET_PAGE_BITS_MIN 10 2224 #endif 2225 2226 #if defined(TARGET_AARCH64) 2227 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2228 # define TARGET_VIRT_ADDR_SPACE_BITS 64 2229 #else 2230 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2231 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2232 #endif 2233 2234 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2235 unsigned int target_el) 2236 { 2237 CPUARMState *env = cs->env_ptr; 2238 unsigned int cur_el = arm_current_el(env); 2239 bool secure = arm_is_secure(env); 2240 bool pstate_unmasked; 2241 int8_t unmasked = 0; 2242 2243 /* Don't take exceptions if they target a lower EL. 2244 * This check should catch any exceptions that would not be taken but left 2245 * pending. 2246 */ 2247 if (cur_el > target_el) { 2248 return false; 2249 } 2250 2251 switch (excp_idx) { 2252 case EXCP_FIQ: 2253 pstate_unmasked = !(env->daif & PSTATE_F); 2254 break; 2255 2256 case EXCP_IRQ: 2257 pstate_unmasked = !(env->daif & PSTATE_I); 2258 break; 2259 2260 case EXCP_VFIQ: 2261 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 2262 /* VFIQs are only taken when hypervized and non-secure. */ 2263 return false; 2264 } 2265 return !(env->daif & PSTATE_F); 2266 case EXCP_VIRQ: 2267 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 2268 /* VIRQs are only taken when hypervized and non-secure. */ 2269 return false; 2270 } 2271 return !(env->daif & PSTATE_I); 2272 default: 2273 g_assert_not_reached(); 2274 } 2275 2276 /* Use the target EL, current execution state and SCR/HCR settings to 2277 * determine whether the corresponding CPSR bit is used to mask the 2278 * interrupt. 2279 */ 2280 if ((target_el > cur_el) && (target_el != 1)) { 2281 /* Exceptions targeting a higher EL may not be maskable */ 2282 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2283 /* 64-bit masking rules are simple: exceptions to EL3 2284 * can't be masked, and exceptions to EL2 can only be 2285 * masked from Secure state. The HCR and SCR settings 2286 * don't affect the masking logic, only the interrupt routing. 2287 */ 2288 if (target_el == 3 || !secure) { 2289 unmasked = 1; 2290 } 2291 } else { 2292 /* The old 32-bit-only environment has a more complicated 2293 * masking setup. HCR and SCR bits not only affect interrupt 2294 * routing but also change the behaviour of masking. 2295 */ 2296 bool hcr, scr; 2297 2298 switch (excp_idx) { 2299 case EXCP_FIQ: 2300 /* If FIQs are routed to EL3 or EL2 then there are cases where 2301 * we override the CPSR.F in determining if the exception is 2302 * masked or not. If neither of these are set then we fall back 2303 * to the CPSR.F setting otherwise we further assess the state 2304 * below. 2305 */ 2306 hcr = (env->cp15.hcr_el2 & HCR_FMO); 2307 scr = (env->cp15.scr_el3 & SCR_FIQ); 2308 2309 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2310 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2311 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2312 * when non-secure but only when FIQs are only routed to EL3. 2313 */ 2314 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2315 break; 2316 case EXCP_IRQ: 2317 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2318 * we may override the CPSR.I masking when in non-secure state. 2319 * The SCR.IRQ setting has already been taken into consideration 2320 * when setting the target EL, so it does not have a further 2321 * affect here. 2322 */ 2323 hcr = (env->cp15.hcr_el2 & HCR_IMO); 2324 scr = false; 2325 break; 2326 default: 2327 g_assert_not_reached(); 2328 } 2329 2330 if ((scr || hcr) && !secure) { 2331 unmasked = 1; 2332 } 2333 } 2334 } 2335 2336 /* The PSTATE bits only mask the interrupt if we have not overriden the 2337 * ability above. 2338 */ 2339 return unmasked || pstate_unmasked; 2340 } 2341 2342 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2343 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2344 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2345 2346 #define cpu_signal_handler cpu_arm_signal_handler 2347 #define cpu_list arm_cpu_list 2348 2349 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2350 * 2351 * If EL3 is 64-bit: 2352 * + NonSecure EL1 & 0 stage 1 2353 * + NonSecure EL1 & 0 stage 2 2354 * + NonSecure EL2 2355 * + Secure EL1 & EL0 2356 * + Secure EL3 2357 * If EL3 is 32-bit: 2358 * + NonSecure PL1 & 0 stage 1 2359 * + NonSecure PL1 & 0 stage 2 2360 * + NonSecure PL2 2361 * + Secure PL0 & PL1 2362 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2363 * 2364 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2365 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2366 * may differ in access permissions even if the VA->PA map is the same 2367 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2368 * translation, which means that we have one mmu_idx that deals with two 2369 * concatenated translation regimes [this sort of combined s1+2 TLB is 2370 * architecturally permitted] 2371 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2372 * handling via the TLB. The only way to do a stage 1 translation without 2373 * the immediate stage 2 translation is via the ATS or AT system insns, 2374 * which can be slow-pathed and always do a page table walk. 2375 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2376 * translation regimes, because they map reasonably well to each other 2377 * and they can't both be active at the same time. 2378 * This gives us the following list of mmu_idx values: 2379 * 2380 * NS EL0 (aka NS PL0) stage 1+2 2381 * NS EL1 (aka NS PL1) stage 1+2 2382 * NS EL2 (aka NS PL2) 2383 * S EL3 (aka S PL1) 2384 * S EL0 (aka S PL0) 2385 * S EL1 (not used if EL3 is 32 bit) 2386 * NS EL0+1 stage 2 2387 * 2388 * (The last of these is an mmu_idx because we want to be able to use the TLB 2389 * for the accesses done as part of a stage 1 page table walk, rather than 2390 * having to walk the stage 2 page table over and over.) 2391 * 2392 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2393 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2394 * NS EL2 if we ever model a Cortex-R52). 2395 * 2396 * M profile CPUs are rather different as they do not have a true MMU. 2397 * They have the following different MMU indexes: 2398 * User 2399 * Privileged 2400 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2401 * Privileged, execution priority negative (ditto) 2402 * If the CPU supports the v8M Security Extension then there are also: 2403 * Secure User 2404 * Secure Privileged 2405 * Secure User, execution priority negative 2406 * Secure Privileged, execution priority negative 2407 * 2408 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2409 * are not quite the same -- different CPU types (most notably M profile 2410 * vs A/R profile) would like to use MMU indexes with different semantics, 2411 * but since we don't ever need to use all of those in a single CPU we 2412 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2413 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2414 * the same for any particular CPU. 2415 * Variables of type ARMMUIdx are always full values, and the core 2416 * index values are in variables of type 'int'. 2417 * 2418 * Our enumeration includes at the end some entries which are not "true" 2419 * mmu_idx values in that they don't have corresponding TLBs and are only 2420 * valid for doing slow path page table walks. 2421 * 2422 * The constant names here are patterned after the general style of the names 2423 * of the AT/ATS operations. 2424 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2425 * For M profile we arrange them to have a bit for priv, a bit for negpri 2426 * and a bit for secure. 2427 */ 2428 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2429 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2430 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2431 2432 /* meanings of the bits for M profile mmu idx values */ 2433 #define ARM_MMU_IDX_M_PRIV 0x1 2434 #define ARM_MMU_IDX_M_NEGPRI 0x2 2435 #define ARM_MMU_IDX_M_S 0x4 2436 2437 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2438 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2439 2440 typedef enum ARMMMUIdx { 2441 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2442 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2443 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2444 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2445 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2446 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2447 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2448 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2449 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2450 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2451 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2452 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2453 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2454 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2455 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2456 /* Indexes below here don't have TLBs and are used only for AT system 2457 * instructions or for the first stage of an S12 page table walk. 2458 */ 2459 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2460 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2461 } ARMMMUIdx; 2462 2463 /* Bit macros for the core-mmu-index values for each index, 2464 * for use when calling tlb_flush_by_mmuidx() and friends. 2465 */ 2466 typedef enum ARMMMUIdxBit { 2467 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2468 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2469 ARMMMUIdxBit_S1E2 = 1 << 2, 2470 ARMMMUIdxBit_S1E3 = 1 << 3, 2471 ARMMMUIdxBit_S1SE0 = 1 << 4, 2472 ARMMMUIdxBit_S1SE1 = 1 << 5, 2473 ARMMMUIdxBit_S2NS = 1 << 6, 2474 ARMMMUIdxBit_MUser = 1 << 0, 2475 ARMMMUIdxBit_MPriv = 1 << 1, 2476 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2477 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2478 ARMMMUIdxBit_MSUser = 1 << 4, 2479 ARMMMUIdxBit_MSPriv = 1 << 5, 2480 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2481 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2482 } ARMMMUIdxBit; 2483 2484 #define MMU_USER_IDX 0 2485 2486 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2487 { 2488 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2489 } 2490 2491 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2492 { 2493 if (arm_feature(env, ARM_FEATURE_M)) { 2494 return mmu_idx | ARM_MMU_IDX_M; 2495 } else { 2496 return mmu_idx | ARM_MMU_IDX_A; 2497 } 2498 } 2499 2500 /* Return the exception level we're running at if this is our mmu_idx */ 2501 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2502 { 2503 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2504 case ARM_MMU_IDX_A: 2505 return mmu_idx & 3; 2506 case ARM_MMU_IDX_M: 2507 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2508 default: 2509 g_assert_not_reached(); 2510 } 2511 } 2512 2513 /* Return the MMU index for a v7M CPU in the specified security and 2514 * privilege state 2515 */ 2516 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2517 bool secstate, 2518 bool priv) 2519 { 2520 ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; 2521 2522 if (priv) { 2523 mmu_idx |= ARM_MMU_IDX_M_PRIV; 2524 } 2525 2526 if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { 2527 mmu_idx |= ARM_MMU_IDX_M_NEGPRI; 2528 } 2529 2530 if (secstate) { 2531 mmu_idx |= ARM_MMU_IDX_M_S; 2532 } 2533 2534 return mmu_idx; 2535 } 2536 2537 /* Return the MMU index for a v7M CPU in the specified security state */ 2538 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, 2539 bool secstate) 2540 { 2541 bool priv = arm_current_el(env) != 0; 2542 2543 return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); 2544 } 2545 2546 /* Determine the current mmu_idx to use for normal loads/stores */ 2547 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2548 { 2549 int el = arm_current_el(env); 2550 2551 if (arm_feature(env, ARM_FEATURE_M)) { 2552 ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); 2553 2554 return arm_to_core_mmu_idx(mmu_idx); 2555 } 2556 2557 if (el < 2 && arm_is_secure_below_el3(env)) { 2558 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); 2559 } 2560 return el; 2561 } 2562 2563 /* Indexes used when registering address spaces with cpu_address_space_init */ 2564 typedef enum ARMASIdx { 2565 ARMASIdx_NS = 0, 2566 ARMASIdx_S = 1, 2567 } ARMASIdx; 2568 2569 /* Return the Exception Level targeted by debug exceptions. */ 2570 static inline int arm_debug_target_el(CPUARMState *env) 2571 { 2572 bool secure = arm_is_secure(env); 2573 bool route_to_el2 = false; 2574 2575 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2576 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2577 env->cp15.mdcr_el2 & (1 << 8); 2578 } 2579 2580 if (route_to_el2) { 2581 return 2; 2582 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2583 !arm_el_is_aa64(env, 3) && secure) { 2584 return 3; 2585 } else { 2586 return 1; 2587 } 2588 } 2589 2590 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2591 { 2592 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2593 * CSSELR is RAZ/WI. 2594 */ 2595 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2596 } 2597 2598 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2599 { 2600 if (arm_is_secure(env)) { 2601 /* MDCR_EL3.SDD disables debug events from Secure state */ 2602 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2603 || arm_current_el(env) == 3) { 2604 return false; 2605 } 2606 } 2607 2608 if (arm_current_el(env) == arm_debug_target_el(env)) { 2609 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2610 || (env->daif & PSTATE_D)) { 2611 return false; 2612 } 2613 } 2614 return true; 2615 } 2616 2617 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2618 { 2619 int el = arm_current_el(env); 2620 2621 if (el == 0 && arm_el_is_aa64(env, 1)) { 2622 return aa64_generate_debug_exceptions(env); 2623 } 2624 2625 if (arm_is_secure(env)) { 2626 int spd; 2627 2628 if (el == 0 && (env->cp15.sder & 1)) { 2629 /* SDER.SUIDEN means debug exceptions from Secure EL0 2630 * are always enabled. Otherwise they are controlled by 2631 * SDCR.SPD like those from other Secure ELs. 2632 */ 2633 return true; 2634 } 2635 2636 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2637 switch (spd) { 2638 case 1: 2639 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2640 case 0: 2641 /* For 0b00 we return true if external secure invasive debug 2642 * is enabled. On real hardware this is controlled by external 2643 * signals to the core. QEMU always permits debug, and behaves 2644 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2645 */ 2646 return true; 2647 case 2: 2648 return false; 2649 case 3: 2650 return true; 2651 } 2652 } 2653 2654 return el != 2; 2655 } 2656 2657 /* Return true if debugging exceptions are currently enabled. 2658 * This corresponds to what in ARM ARM pseudocode would be 2659 * if UsingAArch32() then 2660 * return AArch32.GenerateDebugExceptions() 2661 * else 2662 * return AArch64.GenerateDebugExceptions() 2663 * We choose to push the if() down into this function for clarity, 2664 * since the pseudocode has it at all callsites except for the one in 2665 * CheckSoftwareStep(), where it is elided because both branches would 2666 * always return the same value. 2667 * 2668 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2669 * don't yet implement those exception levels or their associated trap bits. 2670 */ 2671 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2672 { 2673 if (env->aarch64) { 2674 return aa64_generate_debug_exceptions(env); 2675 } else { 2676 return aa32_generate_debug_exceptions(env); 2677 } 2678 } 2679 2680 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2681 * implicitly means this always returns false in pre-v8 CPUs.) 2682 */ 2683 static inline bool arm_singlestep_active(CPUARMState *env) 2684 { 2685 return extract32(env->cp15.mdscr_el1, 0, 1) 2686 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2687 && arm_generate_debug_exceptions(env); 2688 } 2689 2690 static inline bool arm_sctlr_b(CPUARMState *env) 2691 { 2692 return 2693 /* We need not implement SCTLR.ITD in user-mode emulation, so 2694 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2695 * This lets people run BE32 binaries with "-cpu any". 2696 */ 2697 #ifndef CONFIG_USER_ONLY 2698 !arm_feature(env, ARM_FEATURE_V7) && 2699 #endif 2700 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2701 } 2702 2703 /* Return true if the processor is in big-endian mode. */ 2704 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2705 { 2706 int cur_el; 2707 2708 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2709 if (!is_a64(env)) { 2710 return 2711 #ifdef CONFIG_USER_ONLY 2712 /* In system mode, BE32 is modelled in line with the 2713 * architecture (as word-invariant big-endianness), where loads 2714 * and stores are done little endian but from addresses which 2715 * are adjusted by XORing with the appropriate constant. So the 2716 * endianness to use for the raw data access is not affected by 2717 * SCTLR.B. 2718 * In user mode, however, we model BE32 as byte-invariant 2719 * big-endianness (because user-only code cannot tell the 2720 * difference), and so we need to use a data access endianness 2721 * that depends on SCTLR.B. 2722 */ 2723 arm_sctlr_b(env) || 2724 #endif 2725 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2726 } 2727 2728 cur_el = arm_current_el(env); 2729 2730 if (cur_el == 0) { 2731 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2732 } 2733 2734 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2735 } 2736 2737 #include "exec/cpu-all.h" 2738 2739 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2740 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2741 * We put flags which are shared between 32 and 64 bit mode at the top 2742 * of the word, and flags which apply to only one mode at the bottom. 2743 */ 2744 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2745 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2746 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2747 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2748 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2749 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2750 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2751 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2752 /* Target EL if we take a floating-point-disabled exception */ 2753 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2754 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2755 2756 /* Bit usage when in AArch32 state: */ 2757 #define ARM_TBFLAG_THUMB_SHIFT 0 2758 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2759 #define ARM_TBFLAG_VECLEN_SHIFT 1 2760 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2761 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2762 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2763 #define ARM_TBFLAG_VFPEN_SHIFT 7 2764 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2765 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2766 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2767 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2768 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2769 /* We store the bottom two bits of the CPAR as TB flags and handle 2770 * checks on the other bits at runtime 2771 */ 2772 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2773 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2774 /* Indicates whether cp register reads and writes by guest code should access 2775 * the secure or nonsecure bank of banked registers; note that this is not 2776 * the same thing as the current security state of the processor! 2777 */ 2778 #define ARM_TBFLAG_NS_SHIFT 19 2779 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2780 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2781 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2782 /* For M profile only, Handler (ie not Thread) mode */ 2783 #define ARM_TBFLAG_HANDLER_SHIFT 21 2784 #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) 2785 2786 /* Bit usage when in AArch64 state */ 2787 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2788 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2789 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2790 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2791 #define ARM_TBFLAG_SVEEXC_EL_SHIFT 2 2792 #define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT) 2793 #define ARM_TBFLAG_ZCR_LEN_SHIFT 4 2794 #define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT) 2795 2796 /* some convenience accessor macros */ 2797 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2798 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2799 #define ARM_TBFLAG_MMUIDX(F) \ 2800 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2801 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2802 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2803 #define ARM_TBFLAG_PSTATE_SS(F) \ 2804 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2805 #define ARM_TBFLAG_FPEXC_EL(F) \ 2806 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2807 #define ARM_TBFLAG_THUMB(F) \ 2808 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2809 #define ARM_TBFLAG_VECLEN(F) \ 2810 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2811 #define ARM_TBFLAG_VECSTRIDE(F) \ 2812 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2813 #define ARM_TBFLAG_VFPEN(F) \ 2814 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2815 #define ARM_TBFLAG_CONDEXEC(F) \ 2816 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2817 #define ARM_TBFLAG_SCTLR_B(F) \ 2818 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2819 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2820 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2821 #define ARM_TBFLAG_NS(F) \ 2822 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2823 #define ARM_TBFLAG_BE_DATA(F) \ 2824 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2825 #define ARM_TBFLAG_HANDLER(F) \ 2826 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) 2827 #define ARM_TBFLAG_TBI0(F) \ 2828 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2829 #define ARM_TBFLAG_TBI1(F) \ 2830 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2831 #define ARM_TBFLAG_SVEEXC_EL(F) \ 2832 (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT) 2833 #define ARM_TBFLAG_ZCR_LEN(F) \ 2834 (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT) 2835 2836 static inline bool bswap_code(bool sctlr_b) 2837 { 2838 #ifdef CONFIG_USER_ONLY 2839 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2840 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2841 * would also end up as a mixed-endian mode with BE code, LE data. 2842 */ 2843 return 2844 #ifdef TARGET_WORDS_BIGENDIAN 2845 1 ^ 2846 #endif 2847 sctlr_b; 2848 #else 2849 /* All code access in ARM is little endian, and there are no loaders 2850 * doing swaps that need to be reversed 2851 */ 2852 return 0; 2853 #endif 2854 } 2855 2856 #ifdef CONFIG_USER_ONLY 2857 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2858 { 2859 return 2860 #ifdef TARGET_WORDS_BIGENDIAN 2861 1 ^ 2862 #endif 2863 arm_cpu_data_is_big_endian(env); 2864 } 2865 #endif 2866 2867 #ifndef CONFIG_USER_ONLY 2868 /** 2869 * arm_regime_tbi0: 2870 * @env: CPUARMState 2871 * @mmu_idx: MMU index indicating required translation regime 2872 * 2873 * Extracts the TBI0 value from the appropriate TCR for the current EL 2874 * 2875 * Returns: the TBI0 value. 2876 */ 2877 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2878 2879 /** 2880 * arm_regime_tbi1: 2881 * @env: CPUARMState 2882 * @mmu_idx: MMU index indicating required translation regime 2883 * 2884 * Extracts the TBI1 value from the appropriate TCR for the current EL 2885 * 2886 * Returns: the TBI1 value. 2887 */ 2888 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2889 #else 2890 /* We can't handle tagged addresses properly in user-only mode */ 2891 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2892 { 2893 return 0; 2894 } 2895 2896 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2897 { 2898 return 0; 2899 } 2900 #endif 2901 2902 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2903 target_ulong *cs_base, uint32_t *flags); 2904 2905 enum { 2906 QEMU_PSCI_CONDUIT_DISABLED = 0, 2907 QEMU_PSCI_CONDUIT_SMC = 1, 2908 QEMU_PSCI_CONDUIT_HVC = 2, 2909 }; 2910 2911 #ifndef CONFIG_USER_ONLY 2912 /* Return the address space index to use for a memory access */ 2913 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2914 { 2915 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2916 } 2917 2918 /* Return the AddressSpace to use for a memory access 2919 * (which depends on whether the access is S or NS, and whether 2920 * the board gave us a separate AddressSpace for S accesses). 2921 */ 2922 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2923 { 2924 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2925 } 2926 #endif 2927 2928 /** 2929 * arm_register_pre_el_change_hook: 2930 * Register a hook function which will be called immediately before this 2931 * CPU changes exception level or mode. The hook function will be 2932 * passed a pointer to the ARMCPU and the opaque data pointer passed 2933 * to this function when the hook was registered. 2934 * 2935 * Note that if a pre-change hook is called, any registered post-change hooks 2936 * are guaranteed to subsequently be called. 2937 */ 2938 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 2939 void *opaque); 2940 /** 2941 * arm_register_el_change_hook: 2942 * Register a hook function which will be called immediately after this 2943 * CPU changes exception level or mode. The hook function will be 2944 * passed a pointer to the ARMCPU and the opaque data pointer passed 2945 * to this function when the hook was registered. 2946 * 2947 * Note that any registered hooks registered here are guaranteed to be called 2948 * if pre-change hooks have been. 2949 */ 2950 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 2951 *opaque); 2952 2953 /** 2954 * aa32_vfp_dreg: 2955 * Return a pointer to the Dn register within env in 32-bit mode. 2956 */ 2957 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 2958 { 2959 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 2960 } 2961 2962 /** 2963 * aa32_vfp_qreg: 2964 * Return a pointer to the Qn register within env in 32-bit mode. 2965 */ 2966 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 2967 { 2968 return &env->vfp.zregs[regno].d[0]; 2969 } 2970 2971 /** 2972 * aa64_vfp_qreg: 2973 * Return a pointer to the Qn register within env in 64-bit mode. 2974 */ 2975 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 2976 { 2977 return &env->vfp.zregs[regno].d[0]; 2978 } 2979 2980 /* Shared between translate-sve.c and sve_helper.c. */ 2981 extern const uint64_t pred_esz_masks[4]; 2982 2983 #endif 2984