1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 #include "cpu-qom.h" 26 #include "exec/cpu-defs.h" 27 #include "qapi/qapi-types-common.h" 28 29 /* ARM processors have a weak memory model */ 30 #define TCG_GUEST_DEFAULT_MO (0) 31 32 #ifdef TARGET_AARCH64 33 #define KVM_HAVE_MCE_INJECTION 1 34 #endif 35 36 #define EXCP_UDEF 1 /* undefined instruction */ 37 #define EXCP_SWI 2 /* software interrupt */ 38 #define EXCP_PREFETCH_ABORT 3 39 #define EXCP_DATA_ABORT 4 40 #define EXCP_IRQ 5 41 #define EXCP_FIQ 6 42 #define EXCP_BKPT 7 43 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 44 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 45 #define EXCP_HVC 11 /* HyperVisor Call */ 46 #define EXCP_HYP_TRAP 12 47 #define EXCP_SMC 13 /* Secure Monitor Call */ 48 #define EXCP_VIRQ 14 49 #define EXCP_VFIQ 15 50 #define EXCP_SEMIHOST 16 /* semihosting call */ 51 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 52 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 53 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 54 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 55 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 56 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 57 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 58 59 #define ARMV7M_EXCP_RESET 1 60 #define ARMV7M_EXCP_NMI 2 61 #define ARMV7M_EXCP_HARD 3 62 #define ARMV7M_EXCP_MEM 4 63 #define ARMV7M_EXCP_BUS 5 64 #define ARMV7M_EXCP_USAGE 6 65 #define ARMV7M_EXCP_SECURE 7 66 #define ARMV7M_EXCP_SVC 11 67 #define ARMV7M_EXCP_DEBUG 12 68 #define ARMV7M_EXCP_PENDSV 14 69 #define ARMV7M_EXCP_SYSTICK 15 70 71 /* For M profile, some registers are banked secure vs non-secure; 72 * these are represented as a 2-element array where the first element 73 * is the non-secure copy and the second is the secure copy. 74 * When the CPU does not have implement the security extension then 75 * only the first element is used. 76 * This means that the copy for the current security state can be 77 * accessed via env->registerfield[env->v7m.secure] (whether the security 78 * extension is implemented or not). 79 */ 80 enum { 81 M_REG_NS = 0, 82 M_REG_S = 1, 83 M_REG_NUM_BANKS = 2, 84 }; 85 86 /* ARM-specific interrupt pending bits. */ 87 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 88 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 89 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 90 91 /* The usual mapping for an AArch64 system register to its AArch32 92 * counterpart is for the 32 bit world to have access to the lower 93 * half only (with writes leaving the upper half untouched). It's 94 * therefore useful to be able to pass TCG the offset of the least 95 * significant half of a uint64_t struct member. 96 */ 97 #ifdef HOST_WORDS_BIGENDIAN 98 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 99 #define offsetofhigh32(S, M) offsetof(S, M) 100 #else 101 #define offsetoflow32(S, M) offsetof(S, M) 102 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #endif 104 105 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 106 #define ARM_CPU_IRQ 0 107 #define ARM_CPU_FIQ 1 108 #define ARM_CPU_VIRQ 2 109 #define ARM_CPU_VFIQ 3 110 111 /* ARM-specific extra insn start words: 112 * 1: Conditional execution bits 113 * 2: Partial exception syndrome for data aborts 114 */ 115 #define TARGET_INSN_START_EXTRA_WORDS 2 116 117 /* The 2nd extra word holding syndrome info for data aborts does not use 118 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 119 * help the sleb128 encoder do a better job. 120 * When restoring the CPU state, we shift it back up. 121 */ 122 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 123 #define ARM_INSN_START_WORD2_SHIFT 14 124 125 /* We currently assume float and double are IEEE single and double 126 precision respectively. 127 Doing runtime conversions is tricky because VFP registers may contain 128 integer values (eg. as the result of a FTOSI instruction). 129 s<2n> maps to the least significant half of d<n> 130 s<2n+1> maps to the most significant half of d<n> 131 */ 132 133 /** 134 * DynamicGDBXMLInfo: 135 * @desc: Contains the XML descriptions. 136 * @num: Number of the registers in this XML seen by GDB. 137 * @data: A union with data specific to the set of registers 138 * @cpregs_keys: Array that contains the corresponding Key of 139 * a given cpreg with the same order of the cpreg 140 * in the XML description. 141 */ 142 typedef struct DynamicGDBXMLInfo { 143 char *desc; 144 int num; 145 union { 146 struct { 147 uint32_t *keys; 148 } cpregs; 149 } data; 150 } DynamicGDBXMLInfo; 151 152 /* CPU state for each instance of a generic timer (in cp15 c14) */ 153 typedef struct ARMGenericTimer { 154 uint64_t cval; /* Timer CompareValue register */ 155 uint64_t ctl; /* Timer Control register */ 156 } ARMGenericTimer; 157 158 #define GTIMER_PHYS 0 159 #define GTIMER_VIRT 1 160 #define GTIMER_HYP 2 161 #define GTIMER_SEC 3 162 #define GTIMER_HYPVIRT 4 163 #define NUM_GTIMERS 5 164 165 typedef struct { 166 uint64_t raw_tcr; 167 uint32_t mask; 168 uint32_t base_mask; 169 } TCR; 170 171 #define VTCR_NSW (1u << 29) 172 #define VTCR_NSA (1u << 30) 173 #define VSTCR_SW VTCR_NSW 174 #define VSTCR_SA VTCR_NSA 175 176 /* Define a maximum sized vector register. 177 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 178 * For 64-bit, this is a 2048-bit SVE register. 179 * 180 * Note that the mapping between S, D, and Q views of the register bank 181 * differs between AArch64 and AArch32. 182 * In AArch32: 183 * Qn = regs[n].d[1]:regs[n].d[0] 184 * Dn = regs[n / 2].d[n & 1] 185 * Sn = regs[n / 4].d[n % 4 / 2], 186 * bits 31..0 for even n, and bits 63..32 for odd n 187 * (and regs[16] to regs[31] are inaccessible) 188 * In AArch64: 189 * Zn = regs[n].d[*] 190 * Qn = regs[n].d[1]:regs[n].d[0] 191 * Dn = regs[n].d[0] 192 * Sn = regs[n].d[0] bits 31..0 193 * Hn = regs[n].d[0] bits 15..0 194 * 195 * This corresponds to the architecturally defined mapping between 196 * the two execution states, and means we do not need to explicitly 197 * map these registers when changing states. 198 * 199 * Align the data for use with TCG host vector operations. 200 */ 201 202 #ifdef TARGET_AARCH64 203 # define ARM_MAX_VQ 16 204 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 205 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); 206 #else 207 # define ARM_MAX_VQ 1 208 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 209 static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } 210 #endif 211 212 typedef struct ARMVectorReg { 213 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 214 } ARMVectorReg; 215 216 #ifdef TARGET_AARCH64 217 /* In AArch32 mode, predicate registers do not exist at all. */ 218 typedef struct ARMPredicateReg { 219 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 220 } ARMPredicateReg; 221 222 /* In AArch32 mode, PAC keys do not exist at all. */ 223 typedef struct ARMPACKey { 224 uint64_t lo, hi; 225 } ARMPACKey; 226 #endif 227 228 /* See the commentary above the TBFLAG field definitions. */ 229 typedef struct CPUARMTBFlags { 230 uint32_t flags; 231 target_ulong flags2; 232 } CPUARMTBFlags; 233 234 typedef struct CPUARMState { 235 /* Regs for current mode. */ 236 uint32_t regs[16]; 237 238 /* 32/64 switch only happens when taking and returning from 239 * exceptions so the overlap semantics are taken care of then 240 * instead of having a complicated union. 241 */ 242 /* Regs for A64 mode. */ 243 uint64_t xregs[32]; 244 uint64_t pc; 245 /* PSTATE isn't an architectural register for ARMv8. However, it is 246 * convenient for us to assemble the underlying state into a 32 bit format 247 * identical to the architectural format used for the SPSR. (This is also 248 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 249 * 'pstate' register are.) Of the PSTATE bits: 250 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 251 * semantics as for AArch32, as described in the comments on each field) 252 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 253 * DAIF (exception masks) are kept in env->daif 254 * BTYPE is kept in env->btype 255 * all other bits are stored in their correct places in env->pstate 256 */ 257 uint32_t pstate; 258 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 259 260 /* Cached TBFLAGS state. See below for which bits are included. */ 261 CPUARMTBFlags hflags; 262 263 /* Frequently accessed CPSR bits are stored separately for efficiency. 264 This contains all the other bits. Use cpsr_{read,write} to access 265 the whole CPSR. */ 266 uint32_t uncached_cpsr; 267 uint32_t spsr; 268 269 /* Banked registers. */ 270 uint64_t banked_spsr[8]; 271 uint32_t banked_r13[8]; 272 uint32_t banked_r14[8]; 273 274 /* These hold r8-r12. */ 275 uint32_t usr_regs[5]; 276 uint32_t fiq_regs[5]; 277 278 /* cpsr flag cache for faster execution */ 279 uint32_t CF; /* 0 or 1 */ 280 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 281 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 282 uint32_t ZF; /* Z set if zero. */ 283 uint32_t QF; /* 0 or 1 */ 284 uint32_t GE; /* cpsr[19:16] */ 285 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 286 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 287 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 288 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 289 290 uint64_t elr_el[4]; /* AArch64 exception link regs */ 291 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 292 293 /* System control coprocessor (cp15) */ 294 struct { 295 uint32_t c0_cpuid; 296 union { /* Cache size selection */ 297 struct { 298 uint64_t _unused_csselr0; 299 uint64_t csselr_ns; 300 uint64_t _unused_csselr1; 301 uint64_t csselr_s; 302 }; 303 uint64_t csselr_el[4]; 304 }; 305 union { /* System control register. */ 306 struct { 307 uint64_t _unused_sctlr; 308 uint64_t sctlr_ns; 309 uint64_t hsctlr; 310 uint64_t sctlr_s; 311 }; 312 uint64_t sctlr_el[4]; 313 }; 314 uint64_t cpacr_el1; /* Architectural feature access control register */ 315 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 316 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 317 uint64_t sder; /* Secure debug enable register. */ 318 uint32_t nsacr; /* Non-secure access control register. */ 319 union { /* MMU translation table base 0. */ 320 struct { 321 uint64_t _unused_ttbr0_0; 322 uint64_t ttbr0_ns; 323 uint64_t _unused_ttbr0_1; 324 uint64_t ttbr0_s; 325 }; 326 uint64_t ttbr0_el[4]; 327 }; 328 union { /* MMU translation table base 1. */ 329 struct { 330 uint64_t _unused_ttbr1_0; 331 uint64_t ttbr1_ns; 332 uint64_t _unused_ttbr1_1; 333 uint64_t ttbr1_s; 334 }; 335 uint64_t ttbr1_el[4]; 336 }; 337 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 338 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 339 /* MMU translation table base control. */ 340 TCR tcr_el[4]; 341 TCR vtcr_el2; /* Virtualization Translation Control. */ 342 TCR vstcr_el2; /* Secure Virtualization Translation Control. */ 343 uint32_t c2_data; /* MPU data cacheable bits. */ 344 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 345 union { /* MMU domain access control register 346 * MPU write buffer control. 347 */ 348 struct { 349 uint64_t dacr_ns; 350 uint64_t dacr_s; 351 }; 352 struct { 353 uint64_t dacr32_el2; 354 }; 355 }; 356 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 357 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 358 uint64_t hcr_el2; /* Hypervisor configuration register */ 359 uint64_t scr_el3; /* Secure configuration register. */ 360 union { /* Fault status registers. */ 361 struct { 362 uint64_t ifsr_ns; 363 uint64_t ifsr_s; 364 }; 365 struct { 366 uint64_t ifsr32_el2; 367 }; 368 }; 369 union { 370 struct { 371 uint64_t _unused_dfsr; 372 uint64_t dfsr_ns; 373 uint64_t hsr; 374 uint64_t dfsr_s; 375 }; 376 uint64_t esr_el[4]; 377 }; 378 uint32_t c6_region[8]; /* MPU base/size registers. */ 379 union { /* Fault address registers. */ 380 struct { 381 uint64_t _unused_far0; 382 #ifdef HOST_WORDS_BIGENDIAN 383 uint32_t ifar_ns; 384 uint32_t dfar_ns; 385 uint32_t ifar_s; 386 uint32_t dfar_s; 387 #else 388 uint32_t dfar_ns; 389 uint32_t ifar_ns; 390 uint32_t dfar_s; 391 uint32_t ifar_s; 392 #endif 393 uint64_t _unused_far3; 394 }; 395 uint64_t far_el[4]; 396 }; 397 uint64_t hpfar_el2; 398 uint64_t hstr_el2; 399 union { /* Translation result. */ 400 struct { 401 uint64_t _unused_par_0; 402 uint64_t par_ns; 403 uint64_t _unused_par_1; 404 uint64_t par_s; 405 }; 406 uint64_t par_el[4]; 407 }; 408 409 uint32_t c9_insn; /* Cache lockdown registers. */ 410 uint32_t c9_data; 411 uint64_t c9_pmcr; /* performance monitor control register */ 412 uint64_t c9_pmcnten; /* perf monitor counter enables */ 413 uint64_t c9_pmovsr; /* perf monitor overflow status */ 414 uint64_t c9_pmuserenr; /* perf monitor user enable */ 415 uint64_t c9_pmselr; /* perf monitor counter selection register */ 416 uint64_t c9_pminten; /* perf monitor interrupt enables */ 417 union { /* Memory attribute redirection */ 418 struct { 419 #ifdef HOST_WORDS_BIGENDIAN 420 uint64_t _unused_mair_0; 421 uint32_t mair1_ns; 422 uint32_t mair0_ns; 423 uint64_t _unused_mair_1; 424 uint32_t mair1_s; 425 uint32_t mair0_s; 426 #else 427 uint64_t _unused_mair_0; 428 uint32_t mair0_ns; 429 uint32_t mair1_ns; 430 uint64_t _unused_mair_1; 431 uint32_t mair0_s; 432 uint32_t mair1_s; 433 #endif 434 }; 435 uint64_t mair_el[4]; 436 }; 437 union { /* vector base address register */ 438 struct { 439 uint64_t _unused_vbar; 440 uint64_t vbar_ns; 441 uint64_t hvbar; 442 uint64_t vbar_s; 443 }; 444 uint64_t vbar_el[4]; 445 }; 446 uint32_t mvbar; /* (monitor) vector base address register */ 447 struct { /* FCSE PID. */ 448 uint32_t fcseidr_ns; 449 uint32_t fcseidr_s; 450 }; 451 union { /* Context ID. */ 452 struct { 453 uint64_t _unused_contextidr_0; 454 uint64_t contextidr_ns; 455 uint64_t _unused_contextidr_1; 456 uint64_t contextidr_s; 457 }; 458 uint64_t contextidr_el[4]; 459 }; 460 union { /* User RW Thread register. */ 461 struct { 462 uint64_t tpidrurw_ns; 463 uint64_t tpidrprw_ns; 464 uint64_t htpidr; 465 uint64_t _tpidr_el3; 466 }; 467 uint64_t tpidr_el[4]; 468 }; 469 /* The secure banks of these registers don't map anywhere */ 470 uint64_t tpidrurw_s; 471 uint64_t tpidrprw_s; 472 uint64_t tpidruro_s; 473 474 union { /* User RO Thread register. */ 475 uint64_t tpidruro_ns; 476 uint64_t tpidrro_el[1]; 477 }; 478 uint64_t c14_cntfrq; /* Counter Frequency register */ 479 uint64_t c14_cntkctl; /* Timer Control register */ 480 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 481 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 482 ARMGenericTimer c14_timer[NUM_GTIMERS]; 483 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 484 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 485 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 486 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 487 uint32_t c15_threadid; /* TI debugger thread-ID. */ 488 uint32_t c15_config_base_address; /* SCU base address. */ 489 uint32_t c15_diagnostic; /* diagnostic register */ 490 uint32_t c15_power_diagnostic; 491 uint32_t c15_power_control; /* power control */ 492 uint64_t dbgbvr[16]; /* breakpoint value registers */ 493 uint64_t dbgbcr[16]; /* breakpoint control registers */ 494 uint64_t dbgwvr[16]; /* watchpoint value registers */ 495 uint64_t dbgwcr[16]; /* watchpoint control registers */ 496 uint64_t mdscr_el1; 497 uint64_t oslsr_el1; /* OS Lock Status */ 498 uint64_t mdcr_el2; 499 uint64_t mdcr_el3; 500 /* Stores the architectural value of the counter *the last time it was 501 * updated* by pmccntr_op_start. Accesses should always be surrounded 502 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 503 * architecturally-correct value is being read/set. 504 */ 505 uint64_t c15_ccnt; 506 /* Stores the delta between the architectural value and the underlying 507 * cycle count during normal operation. It is used to update c15_ccnt 508 * to be the correct architectural value before accesses. During 509 * accesses, c15_ccnt_delta contains the underlying count being used 510 * for the access, after which it reverts to the delta value in 511 * pmccntr_op_finish. 512 */ 513 uint64_t c15_ccnt_delta; 514 uint64_t c14_pmevcntr[31]; 515 uint64_t c14_pmevcntr_delta[31]; 516 uint64_t c14_pmevtyper[31]; 517 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 518 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 519 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 520 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 521 uint64_t gcr_el1; 522 uint64_t rgsr_el1; 523 } cp15; 524 525 struct { 526 /* M profile has up to 4 stack pointers: 527 * a Main Stack Pointer and a Process Stack Pointer for each 528 * of the Secure and Non-Secure states. (If the CPU doesn't support 529 * the security extension then it has only two SPs.) 530 * In QEMU we always store the currently active SP in regs[13], 531 * and the non-active SP for the current security state in 532 * v7m.other_sp. The stack pointers for the inactive security state 533 * are stored in other_ss_msp and other_ss_psp. 534 * switch_v7m_security_state() is responsible for rearranging them 535 * when we change security state. 536 */ 537 uint32_t other_sp; 538 uint32_t other_ss_msp; 539 uint32_t other_ss_psp; 540 uint32_t vecbase[M_REG_NUM_BANKS]; 541 uint32_t basepri[M_REG_NUM_BANKS]; 542 uint32_t control[M_REG_NUM_BANKS]; 543 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 544 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 545 uint32_t hfsr; /* HardFault Status */ 546 uint32_t dfsr; /* Debug Fault Status Register */ 547 uint32_t sfsr; /* Secure Fault Status Register */ 548 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 549 uint32_t bfar; /* BusFault Address */ 550 uint32_t sfar; /* Secure Fault Address Register */ 551 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 552 int exception; 553 uint32_t primask[M_REG_NUM_BANKS]; 554 uint32_t faultmask[M_REG_NUM_BANKS]; 555 uint32_t aircr; /* only holds r/w state if security extn implemented */ 556 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 557 uint32_t csselr[M_REG_NUM_BANKS]; 558 uint32_t scr[M_REG_NUM_BANKS]; 559 uint32_t msplim[M_REG_NUM_BANKS]; 560 uint32_t psplim[M_REG_NUM_BANKS]; 561 uint32_t fpcar[M_REG_NUM_BANKS]; 562 uint32_t fpccr[M_REG_NUM_BANKS]; 563 uint32_t fpdscr[M_REG_NUM_BANKS]; 564 uint32_t cpacr[M_REG_NUM_BANKS]; 565 uint32_t nsacr; 566 uint32_t ltpsize; 567 uint32_t vpr; 568 } v7m; 569 570 /* Information associated with an exception about to be taken: 571 * code which raises an exception must set cs->exception_index and 572 * the relevant parts of this structure; the cpu_do_interrupt function 573 * will then set the guest-visible registers as part of the exception 574 * entry process. 575 */ 576 struct { 577 uint32_t syndrome; /* AArch64 format syndrome register */ 578 uint32_t fsr; /* AArch32 format fault status register info */ 579 uint64_t vaddress; /* virtual addr associated with exception, if any */ 580 uint32_t target_el; /* EL the exception should be targeted for */ 581 /* If we implement EL2 we will also need to store information 582 * about the intermediate physical address for stage 2 faults. 583 */ 584 } exception; 585 586 /* Information associated with an SError */ 587 struct { 588 uint8_t pending; 589 uint8_t has_esr; 590 uint64_t esr; 591 } serror; 592 593 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 594 595 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 596 uint32_t irq_line_state; 597 598 /* Thumb-2 EE state. */ 599 uint32_t teecr; 600 uint32_t teehbr; 601 602 /* VFP coprocessor state. */ 603 struct { 604 ARMVectorReg zregs[32]; 605 606 #ifdef TARGET_AARCH64 607 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 608 #define FFR_PRED_NUM 16 609 ARMPredicateReg pregs[17]; 610 /* Scratch space for aa64 sve predicate temporary. */ 611 ARMPredicateReg preg_tmp; 612 #endif 613 614 /* We store these fpcsr fields separately for convenience. */ 615 uint32_t qc[4] QEMU_ALIGNED(16); 616 int vec_len; 617 int vec_stride; 618 619 uint32_t xregs[16]; 620 621 /* Scratch space for aa32 neon expansion. */ 622 uint32_t scratch[8]; 623 624 /* There are a number of distinct float control structures: 625 * 626 * fp_status: is the "normal" fp status. 627 * fp_status_fp16: used for half-precision calculations 628 * standard_fp_status : the ARM "Standard FPSCR Value" 629 * standard_fp_status_fp16 : used for half-precision 630 * calculations with the ARM "Standard FPSCR Value" 631 * 632 * Half-precision operations are governed by a separate 633 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 634 * status structure to control this. 635 * 636 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 637 * round-to-nearest and is used by any operations (generally 638 * Neon) which the architecture defines as controlled by the 639 * standard FPSCR value rather than the FPSCR. 640 * 641 * The "standard FPSCR but for fp16 ops" is needed because 642 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 643 * using a fixed value for it. 644 * 645 * To avoid having to transfer exception bits around, we simply 646 * say that the FPSCR cumulative exception flags are the logical 647 * OR of the flags in the four fp statuses. This relies on the 648 * only thing which needs to read the exception flags being 649 * an explicit FPSCR read. 650 */ 651 float_status fp_status; 652 float_status fp_status_f16; 653 float_status standard_fp_status; 654 float_status standard_fp_status_f16; 655 656 /* ZCR_EL[1-3] */ 657 uint64_t zcr_el[4]; 658 } vfp; 659 uint64_t exclusive_addr; 660 uint64_t exclusive_val; 661 uint64_t exclusive_high; 662 663 /* iwMMXt coprocessor state. */ 664 struct { 665 uint64_t regs[16]; 666 uint64_t val; 667 668 uint32_t cregs[16]; 669 } iwmmxt; 670 671 #ifdef TARGET_AARCH64 672 struct { 673 ARMPACKey apia; 674 ARMPACKey apib; 675 ARMPACKey apda; 676 ARMPACKey apdb; 677 ARMPACKey apga; 678 } keys; 679 #endif 680 681 #if defined(CONFIG_USER_ONLY) 682 /* For usermode syscall translation. */ 683 int eabi; 684 #endif 685 686 struct CPUBreakpoint *cpu_breakpoint[16]; 687 struct CPUWatchpoint *cpu_watchpoint[16]; 688 689 /* Fields up to this point are cleared by a CPU reset */ 690 struct {} end_reset_fields; 691 692 /* Fields after this point are preserved across CPU reset. */ 693 694 /* Internal CPU feature flags. */ 695 uint64_t features; 696 697 /* PMSAv7 MPU */ 698 struct { 699 uint32_t *drbar; 700 uint32_t *drsr; 701 uint32_t *dracr; 702 uint32_t rnr[M_REG_NUM_BANKS]; 703 } pmsav7; 704 705 /* PMSAv8 MPU */ 706 struct { 707 /* The PMSAv8 implementation also shares some PMSAv7 config 708 * and state: 709 * pmsav7.rnr (region number register) 710 * pmsav7_dregion (number of configured regions) 711 */ 712 uint32_t *rbar[M_REG_NUM_BANKS]; 713 uint32_t *rlar[M_REG_NUM_BANKS]; 714 uint32_t mair0[M_REG_NUM_BANKS]; 715 uint32_t mair1[M_REG_NUM_BANKS]; 716 } pmsav8; 717 718 /* v8M SAU */ 719 struct { 720 uint32_t *rbar; 721 uint32_t *rlar; 722 uint32_t rnr; 723 uint32_t ctrl; 724 } sau; 725 726 void *nvic; 727 const struct arm_boot_info *boot_info; 728 /* Store GICv3CPUState to access from this struct */ 729 void *gicv3state; 730 731 #ifdef TARGET_TAGGED_ADDRESSES 732 /* Linux syscall tagged address support */ 733 bool tagged_addr_enable; 734 #endif 735 } CPUARMState; 736 737 static inline void set_feature(CPUARMState *env, int feature) 738 { 739 env->features |= 1ULL << feature; 740 } 741 742 static inline void unset_feature(CPUARMState *env, int feature) 743 { 744 env->features &= ~(1ULL << feature); 745 } 746 747 /** 748 * ARMELChangeHookFn: 749 * type of a function which can be registered via arm_register_el_change_hook() 750 * to get callbacks when the CPU changes its exception level or mode. 751 */ 752 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 753 typedef struct ARMELChangeHook ARMELChangeHook; 754 struct ARMELChangeHook { 755 ARMELChangeHookFn *hook; 756 void *opaque; 757 QLIST_ENTRY(ARMELChangeHook) node; 758 }; 759 760 /* These values map onto the return values for 761 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 762 typedef enum ARMPSCIState { 763 PSCI_ON = 0, 764 PSCI_OFF = 1, 765 PSCI_ON_PENDING = 2 766 } ARMPSCIState; 767 768 typedef struct ARMISARegisters ARMISARegisters; 769 770 /** 771 * ARMCPU: 772 * @env: #CPUARMState 773 * 774 * An ARM CPU core. 775 */ 776 struct ARMCPU { 777 /*< private >*/ 778 CPUState parent_obj; 779 /*< public >*/ 780 781 CPUNegativeOffsetState neg; 782 CPUARMState env; 783 784 /* Coprocessor information */ 785 GHashTable *cp_regs; 786 /* For marshalling (mostly coprocessor) register state between the 787 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 788 * we use these arrays. 789 */ 790 /* List of register indexes managed via these arrays; (full KVM style 791 * 64 bit indexes, not CPRegInfo 32 bit indexes) 792 */ 793 uint64_t *cpreg_indexes; 794 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 795 uint64_t *cpreg_values; 796 /* Length of the indexes, values, reset_values arrays */ 797 int32_t cpreg_array_len; 798 /* These are used only for migration: incoming data arrives in 799 * these fields and is sanity checked in post_load before copying 800 * to the working data structures above. 801 */ 802 uint64_t *cpreg_vmstate_indexes; 803 uint64_t *cpreg_vmstate_values; 804 int32_t cpreg_vmstate_array_len; 805 806 DynamicGDBXMLInfo dyn_sysreg_xml; 807 DynamicGDBXMLInfo dyn_svereg_xml; 808 809 /* Timers used by the generic (architected) timer */ 810 QEMUTimer *gt_timer[NUM_GTIMERS]; 811 /* 812 * Timer used by the PMU. Its state is restored after migration by 813 * pmu_op_finish() - it does not need other handling during migration 814 */ 815 QEMUTimer *pmu_timer; 816 /* GPIO outputs for generic timer */ 817 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 818 /* GPIO output for GICv3 maintenance interrupt signal */ 819 qemu_irq gicv3_maintenance_interrupt; 820 /* GPIO output for the PMU interrupt */ 821 qemu_irq pmu_interrupt; 822 823 /* MemoryRegion to use for secure physical accesses */ 824 MemoryRegion *secure_memory; 825 826 /* MemoryRegion to use for allocation tag accesses */ 827 MemoryRegion *tag_memory; 828 MemoryRegion *secure_tag_memory; 829 830 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 831 Object *idau; 832 833 /* 'compatible' string for this CPU for Linux device trees */ 834 const char *dtb_compatible; 835 836 /* PSCI version for this CPU 837 * Bits[31:16] = Major Version 838 * Bits[15:0] = Minor Version 839 */ 840 uint32_t psci_version; 841 842 /* Current power state, access guarded by BQL */ 843 ARMPSCIState power_state; 844 845 /* CPU has virtualization extension */ 846 bool has_el2; 847 /* CPU has security extension */ 848 bool has_el3; 849 /* CPU has PMU (Performance Monitor Unit) */ 850 bool has_pmu; 851 /* CPU has VFP */ 852 bool has_vfp; 853 /* CPU has Neon */ 854 bool has_neon; 855 /* CPU has M-profile DSP extension */ 856 bool has_dsp; 857 858 /* CPU has memory protection unit */ 859 bool has_mpu; 860 /* PMSAv7 MPU number of supported regions */ 861 uint32_t pmsav7_dregion; 862 /* v8M SAU number of supported regions */ 863 uint32_t sau_sregion; 864 865 /* PSCI conduit used to invoke PSCI methods 866 * 0 - disabled, 1 - smc, 2 - hvc 867 */ 868 uint32_t psci_conduit; 869 870 /* For v8M, initial value of the Secure VTOR */ 871 uint32_t init_svtor; 872 /* For v8M, initial value of the Non-secure VTOR */ 873 uint32_t init_nsvtor; 874 875 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 876 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 877 */ 878 uint32_t kvm_target; 879 880 /* KVM init features for this CPU */ 881 uint32_t kvm_init_features[7]; 882 883 /* KVM CPU state */ 884 885 /* KVM virtual time adjustment */ 886 bool kvm_adjvtime; 887 bool kvm_vtime_dirty; 888 uint64_t kvm_vtime; 889 890 /* KVM steal time */ 891 OnOffAuto kvm_steal_time; 892 893 /* Uniprocessor system with MP extensions */ 894 bool mp_is_up; 895 896 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 897 * and the probe failed (so we need to report the error in realize) 898 */ 899 bool host_cpu_probe_failed; 900 901 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 902 * register. 903 */ 904 int32_t core_count; 905 906 /* The instance init functions for implementation-specific subclasses 907 * set these fields to specify the implementation-dependent values of 908 * various constant registers and reset values of non-constant 909 * registers. 910 * Some of these might become QOM properties eventually. 911 * Field names match the official register names as defined in the 912 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 913 * is used for reset values of non-constant registers; no reset_ 914 * prefix means a constant register. 915 * Some of these registers are split out into a substructure that 916 * is shared with the translators to control the ISA. 917 * 918 * Note that if you add an ID register to the ARMISARegisters struct 919 * you need to also update the 32-bit and 64-bit versions of the 920 * kvm_arm_get_host_cpu_features() function to correctly populate the 921 * field by reading the value from the KVM vCPU. 922 */ 923 struct ARMISARegisters { 924 uint32_t id_isar0; 925 uint32_t id_isar1; 926 uint32_t id_isar2; 927 uint32_t id_isar3; 928 uint32_t id_isar4; 929 uint32_t id_isar5; 930 uint32_t id_isar6; 931 uint32_t id_mmfr0; 932 uint32_t id_mmfr1; 933 uint32_t id_mmfr2; 934 uint32_t id_mmfr3; 935 uint32_t id_mmfr4; 936 uint32_t id_pfr0; 937 uint32_t id_pfr1; 938 uint32_t id_pfr2; 939 uint32_t mvfr0; 940 uint32_t mvfr1; 941 uint32_t mvfr2; 942 uint32_t id_dfr0; 943 uint32_t dbgdidr; 944 uint64_t id_aa64isar0; 945 uint64_t id_aa64isar1; 946 uint64_t id_aa64pfr0; 947 uint64_t id_aa64pfr1; 948 uint64_t id_aa64mmfr0; 949 uint64_t id_aa64mmfr1; 950 uint64_t id_aa64mmfr2; 951 uint64_t id_aa64dfr0; 952 uint64_t id_aa64dfr1; 953 uint64_t id_aa64zfr0; 954 } isar; 955 uint64_t midr; 956 uint32_t revidr; 957 uint32_t reset_fpsid; 958 uint64_t ctr; 959 uint32_t reset_sctlr; 960 uint64_t pmceid0; 961 uint64_t pmceid1; 962 uint32_t id_afr0; 963 uint64_t id_aa64afr0; 964 uint64_t id_aa64afr1; 965 uint64_t clidr; 966 uint64_t mp_affinity; /* MP ID without feature bits */ 967 /* The elements of this array are the CCSIDR values for each cache, 968 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 969 */ 970 uint64_t ccsidr[16]; 971 uint64_t reset_cbar; 972 uint32_t reset_auxcr; 973 bool reset_hivecs; 974 975 /* 976 * Intermediate values used during property parsing. 977 * Once finalized, the values should be read from ID_AA64ISAR1. 978 */ 979 bool prop_pauth; 980 bool prop_pauth_impdef; 981 982 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 983 uint32_t dcz_blocksize; 984 uint64_t rvbar; 985 986 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 987 int gic_num_lrs; /* number of list registers */ 988 int gic_vpribits; /* number of virtual priority bits */ 989 int gic_vprebits; /* number of virtual preemption bits */ 990 991 /* Whether the cfgend input is high (i.e. this CPU should reset into 992 * big-endian mode). This setting isn't used directly: instead it modifies 993 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 994 * architecture version. 995 */ 996 bool cfgend; 997 998 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 999 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1000 1001 int32_t node_id; /* NUMA node this CPU belongs to */ 1002 1003 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1004 uint8_t device_irq_level; 1005 1006 /* Used to set the maximum vector length the cpu will support. */ 1007 uint32_t sve_max_vq; 1008 1009 /* 1010 * In sve_vq_map each set bit is a supported vector length of 1011 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 1012 * length in quadwords. 1013 * 1014 * While processing properties during initialization, corresponding 1015 * sve_vq_init bits are set for bits in sve_vq_map that have been 1016 * set by properties. 1017 */ 1018 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 1019 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 1020 1021 /* Generic timer counter frequency, in Hz */ 1022 uint64_t gt_cntfrq_hz; 1023 }; 1024 1025 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1026 1027 void arm_cpu_post_init(Object *obj); 1028 1029 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1030 1031 #ifndef CONFIG_USER_ONLY 1032 extern const VMStateDescription vmstate_arm_cpu; 1033 #endif 1034 1035 void arm_cpu_do_interrupt(CPUState *cpu); 1036 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1037 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 1038 1039 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1040 MemTxAttrs *attrs); 1041 1042 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1043 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1044 1045 /* 1046 * Helpers to dynamically generates XML descriptions of the sysregs 1047 * and SVE registers. Returns the number of registers in each set. 1048 */ 1049 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1050 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1051 1052 /* Returns the dynamically generated XML for the gdb stub. 1053 * Returns a pointer to the XML contents for the specified XML file or NULL 1054 * if the XML name doesn't match the predefined one. 1055 */ 1056 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1057 1058 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1059 int cpuid, void *opaque); 1060 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1061 int cpuid, void *opaque); 1062 1063 #ifdef TARGET_AARCH64 1064 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1065 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1066 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1067 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1068 int new_el, bool el0_a64); 1069 void aarch64_add_sve_properties(Object *obj); 1070 1071 /* 1072 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1073 * The byte at offset i from the start of the in-memory representation contains 1074 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1075 * lowest offsets are stored in the lowest memory addresses, then that nearly 1076 * matches QEMU's representation, which is to use an array of host-endian 1077 * uint64_t's, where the lower offsets are at the lower indices. To complete 1078 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1079 */ 1080 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1081 { 1082 #ifdef HOST_WORDS_BIGENDIAN 1083 int i; 1084 1085 for (i = 0; i < nr; ++i) { 1086 dst[i] = bswap64(src[i]); 1087 } 1088 1089 return dst; 1090 #else 1091 return src; 1092 #endif 1093 } 1094 1095 #else 1096 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1097 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1098 int n, bool a) 1099 { } 1100 static inline void aarch64_add_sve_properties(Object *obj) { } 1101 #endif 1102 1103 void aarch64_sync_32_to_64(CPUARMState *env); 1104 void aarch64_sync_64_to_32(CPUARMState *env); 1105 1106 int fp_exception_el(CPUARMState *env, int cur_el); 1107 int sve_exception_el(CPUARMState *env, int cur_el); 1108 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1109 1110 static inline bool is_a64(CPUARMState *env) 1111 { 1112 return env->aarch64; 1113 } 1114 1115 /* you can call this signal handler from your SIGBUS and SIGSEGV 1116 signal handlers to inform the virtual CPU of exceptions. non zero 1117 is returned if the signal was handled by the virtual CPU. */ 1118 int cpu_arm_signal_handler(int host_signum, void *pinfo, 1119 void *puc); 1120 1121 /** 1122 * pmu_op_start/finish 1123 * @env: CPUARMState 1124 * 1125 * Convert all PMU counters between their delta form (the typical mode when 1126 * they are enabled) and the guest-visible values. These two calls must 1127 * surround any action which might affect the counters. 1128 */ 1129 void pmu_op_start(CPUARMState *env); 1130 void pmu_op_finish(CPUARMState *env); 1131 1132 /* 1133 * Called when a PMU counter is due to overflow 1134 */ 1135 void arm_pmu_timer_cb(void *opaque); 1136 1137 /** 1138 * Functions to register as EL change hooks for PMU mode filtering 1139 */ 1140 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1141 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1142 1143 /* 1144 * pmu_init 1145 * @cpu: ARMCPU 1146 * 1147 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1148 * for the current configuration 1149 */ 1150 void pmu_init(ARMCPU *cpu); 1151 1152 /* SCTLR bit meanings. Several bits have been reused in newer 1153 * versions of the architecture; in that case we define constants 1154 * for both old and new bit meanings. Code which tests against those 1155 * bits should probably check or otherwise arrange that the CPU 1156 * is the architectural version it expects. 1157 */ 1158 #define SCTLR_M (1U << 0) 1159 #define SCTLR_A (1U << 1) 1160 #define SCTLR_C (1U << 2) 1161 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1162 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1163 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1164 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1165 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1166 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1167 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1168 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1169 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1170 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1171 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1172 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1173 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1174 #define SCTLR_SED (1U << 8) /* v8 onward */ 1175 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1176 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1177 #define SCTLR_F (1U << 10) /* up to v6 */ 1178 #define SCTLR_SW (1U << 10) /* v7 */ 1179 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1180 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1181 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1182 #define SCTLR_I (1U << 12) 1183 #define SCTLR_V (1U << 13) /* AArch32 only */ 1184 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1185 #define SCTLR_RR (1U << 14) /* up to v7 */ 1186 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1187 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1188 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1189 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1190 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1191 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1192 #define SCTLR_BR (1U << 17) /* PMSA only */ 1193 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1194 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1195 #define SCTLR_WXN (1U << 19) 1196 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1197 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1198 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1199 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1200 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1201 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1202 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1203 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1204 #define SCTLR_VE (1U << 24) /* up to v7 */ 1205 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1206 #define SCTLR_EE (1U << 25) 1207 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1208 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1209 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1210 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1211 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1212 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1213 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1214 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1215 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1216 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1217 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1218 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1219 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1220 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1221 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1222 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1223 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1224 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1225 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1226 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1227 1228 #define CPTR_TCPAC (1U << 31) 1229 #define CPTR_TTA (1U << 20) 1230 #define CPTR_TFP (1U << 10) 1231 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1232 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1233 1234 #define MDCR_EPMAD (1U << 21) 1235 #define MDCR_EDAD (1U << 20) 1236 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1237 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1238 #define MDCR_SDD (1U << 16) 1239 #define MDCR_SPD (3U << 14) 1240 #define MDCR_TDRA (1U << 11) 1241 #define MDCR_TDOSA (1U << 10) 1242 #define MDCR_TDA (1U << 9) 1243 #define MDCR_TDE (1U << 8) 1244 #define MDCR_HPME (1U << 7) 1245 #define MDCR_TPM (1U << 6) 1246 #define MDCR_TPMCR (1U << 5) 1247 #define MDCR_HPMN (0x1fU) 1248 1249 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1250 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1251 1252 #define CPSR_M (0x1fU) 1253 #define CPSR_T (1U << 5) 1254 #define CPSR_F (1U << 6) 1255 #define CPSR_I (1U << 7) 1256 #define CPSR_A (1U << 8) 1257 #define CPSR_E (1U << 9) 1258 #define CPSR_IT_2_7 (0xfc00U) 1259 #define CPSR_GE (0xfU << 16) 1260 #define CPSR_IL (1U << 20) 1261 #define CPSR_DIT (1U << 21) 1262 #define CPSR_PAN (1U << 22) 1263 #define CPSR_SSBS (1U << 23) 1264 #define CPSR_J (1U << 24) 1265 #define CPSR_IT_0_1 (3U << 25) 1266 #define CPSR_Q (1U << 27) 1267 #define CPSR_V (1U << 28) 1268 #define CPSR_C (1U << 29) 1269 #define CPSR_Z (1U << 30) 1270 #define CPSR_N (1U << 31) 1271 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1272 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1273 1274 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1275 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1276 | CPSR_NZCV) 1277 /* Bits writable in user mode. */ 1278 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1279 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1280 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1281 1282 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1283 #define XPSR_EXCP 0x1ffU 1284 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1285 #define XPSR_IT_2_7 CPSR_IT_2_7 1286 #define XPSR_GE CPSR_GE 1287 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1288 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1289 #define XPSR_IT_0_1 CPSR_IT_0_1 1290 #define XPSR_Q CPSR_Q 1291 #define XPSR_V CPSR_V 1292 #define XPSR_C CPSR_C 1293 #define XPSR_Z CPSR_Z 1294 #define XPSR_N CPSR_N 1295 #define XPSR_NZCV CPSR_NZCV 1296 #define XPSR_IT CPSR_IT 1297 1298 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1299 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1300 #define TTBCR_PD0 (1U << 4) 1301 #define TTBCR_PD1 (1U << 5) 1302 #define TTBCR_EPD0 (1U << 7) 1303 #define TTBCR_IRGN0 (3U << 8) 1304 #define TTBCR_ORGN0 (3U << 10) 1305 #define TTBCR_SH0 (3U << 12) 1306 #define TTBCR_T1SZ (3U << 16) 1307 #define TTBCR_A1 (1U << 22) 1308 #define TTBCR_EPD1 (1U << 23) 1309 #define TTBCR_IRGN1 (3U << 24) 1310 #define TTBCR_ORGN1 (3U << 26) 1311 #define TTBCR_SH1 (1U << 28) 1312 #define TTBCR_EAE (1U << 31) 1313 1314 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1315 * Only these are valid when in AArch64 mode; in 1316 * AArch32 mode SPSRs are basically CPSR-format. 1317 */ 1318 #define PSTATE_SP (1U) 1319 #define PSTATE_M (0xFU) 1320 #define PSTATE_nRW (1U << 4) 1321 #define PSTATE_F (1U << 6) 1322 #define PSTATE_I (1U << 7) 1323 #define PSTATE_A (1U << 8) 1324 #define PSTATE_D (1U << 9) 1325 #define PSTATE_BTYPE (3U << 10) 1326 #define PSTATE_SSBS (1U << 12) 1327 #define PSTATE_IL (1U << 20) 1328 #define PSTATE_SS (1U << 21) 1329 #define PSTATE_PAN (1U << 22) 1330 #define PSTATE_UAO (1U << 23) 1331 #define PSTATE_DIT (1U << 24) 1332 #define PSTATE_TCO (1U << 25) 1333 #define PSTATE_V (1U << 28) 1334 #define PSTATE_C (1U << 29) 1335 #define PSTATE_Z (1U << 30) 1336 #define PSTATE_N (1U << 31) 1337 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1338 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1339 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1340 /* Mode values for AArch64 */ 1341 #define PSTATE_MODE_EL3h 13 1342 #define PSTATE_MODE_EL3t 12 1343 #define PSTATE_MODE_EL2h 9 1344 #define PSTATE_MODE_EL2t 8 1345 #define PSTATE_MODE_EL1h 5 1346 #define PSTATE_MODE_EL1t 4 1347 #define PSTATE_MODE_EL0t 0 1348 1349 /* Write a new value to v7m.exception, thus transitioning into or out 1350 * of Handler mode; this may result in a change of active stack pointer. 1351 */ 1352 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1353 1354 /* Map EL and handler into a PSTATE_MODE. */ 1355 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1356 { 1357 return (el << 2) | handler; 1358 } 1359 1360 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1361 * interprocessing, so we don't attempt to sync with the cpsr state used by 1362 * the 32 bit decoder. 1363 */ 1364 static inline uint32_t pstate_read(CPUARMState *env) 1365 { 1366 int ZF; 1367 1368 ZF = (env->ZF == 0); 1369 return (env->NF & 0x80000000) | (ZF << 30) 1370 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1371 | env->pstate | env->daif | (env->btype << 10); 1372 } 1373 1374 static inline void pstate_write(CPUARMState *env, uint32_t val) 1375 { 1376 env->ZF = (~val) & PSTATE_Z; 1377 env->NF = val; 1378 env->CF = (val >> 29) & 1; 1379 env->VF = (val << 3) & 0x80000000; 1380 env->daif = val & PSTATE_DAIF; 1381 env->btype = (val >> 10) & 3; 1382 env->pstate = val & ~CACHED_PSTATE_BITS; 1383 } 1384 1385 /* Return the current CPSR value. */ 1386 uint32_t cpsr_read(CPUARMState *env); 1387 1388 typedef enum CPSRWriteType { 1389 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1390 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1391 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1392 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1393 } CPSRWriteType; 1394 1395 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1396 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1397 CPSRWriteType write_type); 1398 1399 /* Return the current xPSR value. */ 1400 static inline uint32_t xpsr_read(CPUARMState *env) 1401 { 1402 int ZF; 1403 ZF = (env->ZF == 0); 1404 return (env->NF & 0x80000000) | (ZF << 30) 1405 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1406 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1407 | ((env->condexec_bits & 0xfc) << 8) 1408 | (env->GE << 16) 1409 | env->v7m.exception; 1410 } 1411 1412 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1413 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1414 { 1415 if (mask & XPSR_NZCV) { 1416 env->ZF = (~val) & XPSR_Z; 1417 env->NF = val; 1418 env->CF = (val >> 29) & 1; 1419 env->VF = (val << 3) & 0x80000000; 1420 } 1421 if (mask & XPSR_Q) { 1422 env->QF = ((val & XPSR_Q) != 0); 1423 } 1424 if (mask & XPSR_GE) { 1425 env->GE = (val & XPSR_GE) >> 16; 1426 } 1427 #ifndef CONFIG_USER_ONLY 1428 if (mask & XPSR_T) { 1429 env->thumb = ((val & XPSR_T) != 0); 1430 } 1431 if (mask & XPSR_IT_0_1) { 1432 env->condexec_bits &= ~3; 1433 env->condexec_bits |= (val >> 25) & 3; 1434 } 1435 if (mask & XPSR_IT_2_7) { 1436 env->condexec_bits &= 3; 1437 env->condexec_bits |= (val >> 8) & 0xfc; 1438 } 1439 if (mask & XPSR_EXCP) { 1440 /* Note that this only happens on exception exit */ 1441 write_v7m_exception(env, val & XPSR_EXCP); 1442 } 1443 #endif 1444 } 1445 1446 #define HCR_VM (1ULL << 0) 1447 #define HCR_SWIO (1ULL << 1) 1448 #define HCR_PTW (1ULL << 2) 1449 #define HCR_FMO (1ULL << 3) 1450 #define HCR_IMO (1ULL << 4) 1451 #define HCR_AMO (1ULL << 5) 1452 #define HCR_VF (1ULL << 6) 1453 #define HCR_VI (1ULL << 7) 1454 #define HCR_VSE (1ULL << 8) 1455 #define HCR_FB (1ULL << 9) 1456 #define HCR_BSU_MASK (3ULL << 10) 1457 #define HCR_DC (1ULL << 12) 1458 #define HCR_TWI (1ULL << 13) 1459 #define HCR_TWE (1ULL << 14) 1460 #define HCR_TID0 (1ULL << 15) 1461 #define HCR_TID1 (1ULL << 16) 1462 #define HCR_TID2 (1ULL << 17) 1463 #define HCR_TID3 (1ULL << 18) 1464 #define HCR_TSC (1ULL << 19) 1465 #define HCR_TIDCP (1ULL << 20) 1466 #define HCR_TACR (1ULL << 21) 1467 #define HCR_TSW (1ULL << 22) 1468 #define HCR_TPCP (1ULL << 23) 1469 #define HCR_TPU (1ULL << 24) 1470 #define HCR_TTLB (1ULL << 25) 1471 #define HCR_TVM (1ULL << 26) 1472 #define HCR_TGE (1ULL << 27) 1473 #define HCR_TDZ (1ULL << 28) 1474 #define HCR_HCD (1ULL << 29) 1475 #define HCR_TRVM (1ULL << 30) 1476 #define HCR_RW (1ULL << 31) 1477 #define HCR_CD (1ULL << 32) 1478 #define HCR_ID (1ULL << 33) 1479 #define HCR_E2H (1ULL << 34) 1480 #define HCR_TLOR (1ULL << 35) 1481 #define HCR_TERR (1ULL << 36) 1482 #define HCR_TEA (1ULL << 37) 1483 #define HCR_MIOCNCE (1ULL << 38) 1484 /* RES0 bit 39 */ 1485 #define HCR_APK (1ULL << 40) 1486 #define HCR_API (1ULL << 41) 1487 #define HCR_NV (1ULL << 42) 1488 #define HCR_NV1 (1ULL << 43) 1489 #define HCR_AT (1ULL << 44) 1490 #define HCR_NV2 (1ULL << 45) 1491 #define HCR_FWB (1ULL << 46) 1492 #define HCR_FIEN (1ULL << 47) 1493 /* RES0 bit 48 */ 1494 #define HCR_TID4 (1ULL << 49) 1495 #define HCR_TICAB (1ULL << 50) 1496 #define HCR_AMVOFFEN (1ULL << 51) 1497 #define HCR_TOCU (1ULL << 52) 1498 #define HCR_ENSCXT (1ULL << 53) 1499 #define HCR_TTLBIS (1ULL << 54) 1500 #define HCR_TTLBOS (1ULL << 55) 1501 #define HCR_ATA (1ULL << 56) 1502 #define HCR_DCT (1ULL << 57) 1503 #define HCR_TID5 (1ULL << 58) 1504 #define HCR_TWEDEN (1ULL << 59) 1505 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1506 1507 #define HPFAR_NS (1ULL << 63) 1508 1509 #define SCR_NS (1U << 0) 1510 #define SCR_IRQ (1U << 1) 1511 #define SCR_FIQ (1U << 2) 1512 #define SCR_EA (1U << 3) 1513 #define SCR_FW (1U << 4) 1514 #define SCR_AW (1U << 5) 1515 #define SCR_NET (1U << 6) 1516 #define SCR_SMD (1U << 7) 1517 #define SCR_HCE (1U << 8) 1518 #define SCR_SIF (1U << 9) 1519 #define SCR_RW (1U << 10) 1520 #define SCR_ST (1U << 11) 1521 #define SCR_TWI (1U << 12) 1522 #define SCR_TWE (1U << 13) 1523 #define SCR_TLOR (1U << 14) 1524 #define SCR_TERR (1U << 15) 1525 #define SCR_APK (1U << 16) 1526 #define SCR_API (1U << 17) 1527 #define SCR_EEL2 (1U << 18) 1528 #define SCR_EASE (1U << 19) 1529 #define SCR_NMEA (1U << 20) 1530 #define SCR_FIEN (1U << 21) 1531 #define SCR_ENSCXT (1U << 25) 1532 #define SCR_ATA (1U << 26) 1533 1534 /* Return the current FPSCR value. */ 1535 uint32_t vfp_get_fpscr(CPUARMState *env); 1536 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1537 1538 /* FPCR, Floating Point Control Register 1539 * FPSR, Floating Poiht Status Register 1540 * 1541 * For A64 the FPSCR is split into two logically distinct registers, 1542 * FPCR and FPSR. However since they still use non-overlapping bits 1543 * we store the underlying state in fpscr and just mask on read/write. 1544 */ 1545 #define FPSR_MASK 0xf800009f 1546 #define FPCR_MASK 0x07ff9f00 1547 1548 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1549 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1550 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1551 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1552 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1553 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1554 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1555 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1556 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1557 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1558 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1559 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1560 #define FPCR_V (1 << 28) /* FP overflow flag */ 1561 #define FPCR_C (1 << 29) /* FP carry flag */ 1562 #define FPCR_Z (1 << 30) /* FP zero flag */ 1563 #define FPCR_N (1 << 31) /* FP negative flag */ 1564 1565 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1566 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1567 #define FPCR_LTPSIZE_LENGTH 3 1568 1569 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1570 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1571 1572 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1573 { 1574 return vfp_get_fpscr(env) & FPSR_MASK; 1575 } 1576 1577 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1578 { 1579 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1580 vfp_set_fpscr(env, new_fpscr); 1581 } 1582 1583 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1584 { 1585 return vfp_get_fpscr(env) & FPCR_MASK; 1586 } 1587 1588 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1589 { 1590 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1591 vfp_set_fpscr(env, new_fpscr); 1592 } 1593 1594 enum arm_cpu_mode { 1595 ARM_CPU_MODE_USR = 0x10, 1596 ARM_CPU_MODE_FIQ = 0x11, 1597 ARM_CPU_MODE_IRQ = 0x12, 1598 ARM_CPU_MODE_SVC = 0x13, 1599 ARM_CPU_MODE_MON = 0x16, 1600 ARM_CPU_MODE_ABT = 0x17, 1601 ARM_CPU_MODE_HYP = 0x1a, 1602 ARM_CPU_MODE_UND = 0x1b, 1603 ARM_CPU_MODE_SYS = 0x1f 1604 }; 1605 1606 /* VFP system registers. */ 1607 #define ARM_VFP_FPSID 0 1608 #define ARM_VFP_FPSCR 1 1609 #define ARM_VFP_MVFR2 5 1610 #define ARM_VFP_MVFR1 6 1611 #define ARM_VFP_MVFR0 7 1612 #define ARM_VFP_FPEXC 8 1613 #define ARM_VFP_FPINST 9 1614 #define ARM_VFP_FPINST2 10 1615 /* These ones are M-profile only */ 1616 #define ARM_VFP_FPSCR_NZCVQC 2 1617 #define ARM_VFP_VPR 12 1618 #define ARM_VFP_P0 13 1619 #define ARM_VFP_FPCXT_NS 14 1620 #define ARM_VFP_FPCXT_S 15 1621 1622 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1623 #define QEMU_VFP_FPSCR_NZCV 0xffff 1624 1625 /* iwMMXt coprocessor control registers. */ 1626 #define ARM_IWMMXT_wCID 0 1627 #define ARM_IWMMXT_wCon 1 1628 #define ARM_IWMMXT_wCSSF 2 1629 #define ARM_IWMMXT_wCASF 3 1630 #define ARM_IWMMXT_wCGR0 8 1631 #define ARM_IWMMXT_wCGR1 9 1632 #define ARM_IWMMXT_wCGR2 10 1633 #define ARM_IWMMXT_wCGR3 11 1634 1635 /* V7M CCR bits */ 1636 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1637 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1638 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1639 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1640 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1641 FIELD(V7M_CCR, STKALIGN, 9, 1) 1642 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1643 FIELD(V7M_CCR, DC, 16, 1) 1644 FIELD(V7M_CCR, IC, 17, 1) 1645 FIELD(V7M_CCR, BP, 18, 1) 1646 FIELD(V7M_CCR, LOB, 19, 1) 1647 FIELD(V7M_CCR, TRD, 20, 1) 1648 1649 /* V7M SCR bits */ 1650 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1651 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1652 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1653 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1654 1655 /* V7M AIRCR bits */ 1656 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1657 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1658 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1659 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1660 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1661 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1662 FIELD(V7M_AIRCR, PRIS, 14, 1) 1663 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1664 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1665 1666 /* V7M CFSR bits for MMFSR */ 1667 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1668 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1669 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1670 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1671 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1672 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1673 1674 /* V7M CFSR bits for BFSR */ 1675 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1676 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1677 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1678 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1679 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1680 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1681 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1682 1683 /* V7M CFSR bits for UFSR */ 1684 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1685 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1686 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1687 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1688 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1689 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1690 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1691 1692 /* V7M CFSR bit masks covering all of the subregister bits */ 1693 FIELD(V7M_CFSR, MMFSR, 0, 8) 1694 FIELD(V7M_CFSR, BFSR, 8, 8) 1695 FIELD(V7M_CFSR, UFSR, 16, 16) 1696 1697 /* V7M HFSR bits */ 1698 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1699 FIELD(V7M_HFSR, FORCED, 30, 1) 1700 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1701 1702 /* V7M DFSR bits */ 1703 FIELD(V7M_DFSR, HALTED, 0, 1) 1704 FIELD(V7M_DFSR, BKPT, 1, 1) 1705 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1706 FIELD(V7M_DFSR, VCATCH, 3, 1) 1707 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1708 1709 /* V7M SFSR bits */ 1710 FIELD(V7M_SFSR, INVEP, 0, 1) 1711 FIELD(V7M_SFSR, INVIS, 1, 1) 1712 FIELD(V7M_SFSR, INVER, 2, 1) 1713 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1714 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1715 FIELD(V7M_SFSR, LSPERR, 5, 1) 1716 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1717 FIELD(V7M_SFSR, LSERR, 7, 1) 1718 1719 /* v7M MPU_CTRL bits */ 1720 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1721 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1722 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1723 1724 /* v7M CLIDR bits */ 1725 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1726 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1727 FIELD(V7M_CLIDR, LOC, 24, 3) 1728 FIELD(V7M_CLIDR, LOUU, 27, 3) 1729 FIELD(V7M_CLIDR, ICB, 30, 2) 1730 1731 FIELD(V7M_CSSELR, IND, 0, 1) 1732 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1733 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1734 * define a mask for this and check that it doesn't permit running off 1735 * the end of the array. 1736 */ 1737 FIELD(V7M_CSSELR, INDEX, 0, 4) 1738 1739 /* v7M FPCCR bits */ 1740 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1741 FIELD(V7M_FPCCR, USER, 1, 1) 1742 FIELD(V7M_FPCCR, S, 2, 1) 1743 FIELD(V7M_FPCCR, THREAD, 3, 1) 1744 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1745 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1746 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1747 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1748 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1749 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1750 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1751 FIELD(V7M_FPCCR, RES0, 11, 15) 1752 FIELD(V7M_FPCCR, TS, 26, 1) 1753 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1754 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1755 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1756 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1757 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1758 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1759 #define R_V7M_FPCCR_BANKED_MASK \ 1760 (R_V7M_FPCCR_LSPACT_MASK | \ 1761 R_V7M_FPCCR_USER_MASK | \ 1762 R_V7M_FPCCR_THREAD_MASK | \ 1763 R_V7M_FPCCR_MMRDY_MASK | \ 1764 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1765 R_V7M_FPCCR_UFRDY_MASK | \ 1766 R_V7M_FPCCR_ASPEN_MASK) 1767 1768 /* v7M VPR bits */ 1769 FIELD(V7M_VPR, P0, 0, 16) 1770 FIELD(V7M_VPR, MASK01, 16, 4) 1771 FIELD(V7M_VPR, MASK23, 20, 4) 1772 1773 /* 1774 * System register ID fields. 1775 */ 1776 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1777 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1778 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1779 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1780 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1781 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1782 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1783 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1784 FIELD(CLIDR_EL1, LOC, 24, 3) 1785 FIELD(CLIDR_EL1, LOUU, 27, 3) 1786 FIELD(CLIDR_EL1, ICB, 30, 3) 1787 1788 /* When FEAT_CCIDX is implemented */ 1789 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1790 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1791 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1792 1793 /* When FEAT_CCIDX is not implemented */ 1794 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1795 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1796 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1797 1798 FIELD(CTR_EL0, IMINLINE, 0, 4) 1799 FIELD(CTR_EL0, L1IP, 14, 2) 1800 FIELD(CTR_EL0, DMINLINE, 16, 4) 1801 FIELD(CTR_EL0, ERG, 20, 4) 1802 FIELD(CTR_EL0, CWG, 24, 4) 1803 FIELD(CTR_EL0, IDC, 28, 1) 1804 FIELD(CTR_EL0, DIC, 29, 1) 1805 FIELD(CTR_EL0, TMINLINE, 32, 6) 1806 1807 FIELD(MIDR_EL1, REVISION, 0, 4) 1808 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1809 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1810 FIELD(MIDR_EL1, VARIANT, 20, 4) 1811 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1812 1813 FIELD(ID_ISAR0, SWAP, 0, 4) 1814 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1815 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1816 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1817 FIELD(ID_ISAR0, COPROC, 16, 4) 1818 FIELD(ID_ISAR0, DEBUG, 20, 4) 1819 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1820 1821 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1822 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1823 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1824 FIELD(ID_ISAR1, EXTEND, 12, 4) 1825 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1826 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1827 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1828 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1829 1830 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1831 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1832 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1833 FIELD(ID_ISAR2, MULT, 12, 4) 1834 FIELD(ID_ISAR2, MULTS, 16, 4) 1835 FIELD(ID_ISAR2, MULTU, 20, 4) 1836 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1837 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1838 1839 FIELD(ID_ISAR3, SATURATE, 0, 4) 1840 FIELD(ID_ISAR3, SIMD, 4, 4) 1841 FIELD(ID_ISAR3, SVC, 8, 4) 1842 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1843 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1844 FIELD(ID_ISAR3, T32COPY, 20, 4) 1845 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1846 FIELD(ID_ISAR3, T32EE, 28, 4) 1847 1848 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1849 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1850 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1851 FIELD(ID_ISAR4, SMC, 12, 4) 1852 FIELD(ID_ISAR4, BARRIER, 16, 4) 1853 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1854 FIELD(ID_ISAR4, PSR_M, 24, 4) 1855 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1856 1857 FIELD(ID_ISAR5, SEVL, 0, 4) 1858 FIELD(ID_ISAR5, AES, 4, 4) 1859 FIELD(ID_ISAR5, SHA1, 8, 4) 1860 FIELD(ID_ISAR5, SHA2, 12, 4) 1861 FIELD(ID_ISAR5, CRC32, 16, 4) 1862 FIELD(ID_ISAR5, RDM, 24, 4) 1863 FIELD(ID_ISAR5, VCMA, 28, 4) 1864 1865 FIELD(ID_ISAR6, JSCVT, 0, 4) 1866 FIELD(ID_ISAR6, DP, 4, 4) 1867 FIELD(ID_ISAR6, FHM, 8, 4) 1868 FIELD(ID_ISAR6, SB, 12, 4) 1869 FIELD(ID_ISAR6, SPECRES, 16, 4) 1870 FIELD(ID_ISAR6, BF16, 20, 4) 1871 FIELD(ID_ISAR6, I8MM, 24, 4) 1872 1873 FIELD(ID_MMFR0, VMSA, 0, 4) 1874 FIELD(ID_MMFR0, PMSA, 4, 4) 1875 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 1876 FIELD(ID_MMFR0, SHARELVL, 12, 4) 1877 FIELD(ID_MMFR0, TCM, 16, 4) 1878 FIELD(ID_MMFR0, AUXREG, 20, 4) 1879 FIELD(ID_MMFR0, FCSE, 24, 4) 1880 FIELD(ID_MMFR0, INNERSHR, 28, 4) 1881 1882 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 1883 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 1884 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 1885 FIELD(ID_MMFR1, L1UNISW, 12, 4) 1886 FIELD(ID_MMFR1, L1HVD, 16, 4) 1887 FIELD(ID_MMFR1, L1UNI, 20, 4) 1888 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 1889 FIELD(ID_MMFR1, BPRED, 28, 4) 1890 1891 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 1892 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 1893 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 1894 FIELD(ID_MMFR2, HVDTLB, 12, 4) 1895 FIELD(ID_MMFR2, UNITLB, 16, 4) 1896 FIELD(ID_MMFR2, MEMBARR, 20, 4) 1897 FIELD(ID_MMFR2, WFISTALL, 24, 4) 1898 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 1899 1900 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 1901 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 1902 FIELD(ID_MMFR3, BPMAINT, 8, 4) 1903 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 1904 FIELD(ID_MMFR3, PAN, 16, 4) 1905 FIELD(ID_MMFR3, COHWALK, 20, 4) 1906 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 1907 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 1908 1909 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1910 FIELD(ID_MMFR4, AC2, 4, 4) 1911 FIELD(ID_MMFR4, XNX, 8, 4) 1912 FIELD(ID_MMFR4, CNP, 12, 4) 1913 FIELD(ID_MMFR4, HPDS, 16, 4) 1914 FIELD(ID_MMFR4, LSM, 20, 4) 1915 FIELD(ID_MMFR4, CCIDX, 24, 4) 1916 FIELD(ID_MMFR4, EVT, 28, 4) 1917 1918 FIELD(ID_MMFR5, ETS, 0, 4) 1919 1920 FIELD(ID_PFR0, STATE0, 0, 4) 1921 FIELD(ID_PFR0, STATE1, 4, 4) 1922 FIELD(ID_PFR0, STATE2, 8, 4) 1923 FIELD(ID_PFR0, STATE3, 12, 4) 1924 FIELD(ID_PFR0, CSV2, 16, 4) 1925 FIELD(ID_PFR0, AMU, 20, 4) 1926 FIELD(ID_PFR0, DIT, 24, 4) 1927 FIELD(ID_PFR0, RAS, 28, 4) 1928 1929 FIELD(ID_PFR1, PROGMOD, 0, 4) 1930 FIELD(ID_PFR1, SECURITY, 4, 4) 1931 FIELD(ID_PFR1, MPROGMOD, 8, 4) 1932 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 1933 FIELD(ID_PFR1, GENTIMER, 16, 4) 1934 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 1935 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 1936 FIELD(ID_PFR1, GIC, 28, 4) 1937 1938 FIELD(ID_PFR2, CSV3, 0, 4) 1939 FIELD(ID_PFR2, SSBS, 4, 4) 1940 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 1941 1942 FIELD(ID_AA64ISAR0, AES, 4, 4) 1943 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1944 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1945 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1946 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1947 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1948 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1949 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1950 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1951 FIELD(ID_AA64ISAR0, DP, 44, 4) 1952 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1953 FIELD(ID_AA64ISAR0, TS, 52, 4) 1954 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1955 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1956 1957 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1958 FIELD(ID_AA64ISAR1, APA, 4, 4) 1959 FIELD(ID_AA64ISAR1, API, 8, 4) 1960 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1961 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1962 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1963 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1964 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1965 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1966 FIELD(ID_AA64ISAR1, SB, 36, 4) 1967 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1968 FIELD(ID_AA64ISAR1, BF16, 44, 4) 1969 FIELD(ID_AA64ISAR1, DGH, 48, 4) 1970 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 1971 1972 FIELD(ID_AA64PFR0, EL0, 0, 4) 1973 FIELD(ID_AA64PFR0, EL1, 4, 4) 1974 FIELD(ID_AA64PFR0, EL2, 8, 4) 1975 FIELD(ID_AA64PFR0, EL3, 12, 4) 1976 FIELD(ID_AA64PFR0, FP, 16, 4) 1977 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1978 FIELD(ID_AA64PFR0, GIC, 24, 4) 1979 FIELD(ID_AA64PFR0, RAS, 28, 4) 1980 FIELD(ID_AA64PFR0, SVE, 32, 4) 1981 FIELD(ID_AA64PFR0, SEL2, 36, 4) 1982 FIELD(ID_AA64PFR0, MPAM, 40, 4) 1983 FIELD(ID_AA64PFR0, AMU, 44, 4) 1984 FIELD(ID_AA64PFR0, DIT, 48, 4) 1985 FIELD(ID_AA64PFR0, CSV2, 56, 4) 1986 FIELD(ID_AA64PFR0, CSV3, 60, 4) 1987 1988 FIELD(ID_AA64PFR1, BT, 0, 4) 1989 FIELD(ID_AA64PFR1, SSBS, 4, 4) 1990 FIELD(ID_AA64PFR1, MTE, 8, 4) 1991 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1992 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 1993 1994 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1995 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1996 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1997 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1998 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1999 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2000 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2001 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2002 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2003 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2004 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2005 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2006 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2007 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2008 2009 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2010 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2011 FIELD(ID_AA64MMFR1, VH, 8, 4) 2012 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2013 FIELD(ID_AA64MMFR1, LO, 16, 4) 2014 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2015 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2016 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2017 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2018 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2019 2020 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2021 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2022 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2023 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2024 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2025 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2026 FIELD(ID_AA64MMFR2, NV, 24, 4) 2027 FIELD(ID_AA64MMFR2, ST, 28, 4) 2028 FIELD(ID_AA64MMFR2, AT, 32, 4) 2029 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2030 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2031 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2032 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2033 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2034 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2035 2036 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2037 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2038 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2039 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2040 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2041 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2042 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2043 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2044 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2045 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2046 2047 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2048 FIELD(ID_AA64ZFR0, AES, 4, 4) 2049 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2050 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2051 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2052 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2053 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2054 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2055 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2056 2057 FIELD(ID_DFR0, COPDBG, 0, 4) 2058 FIELD(ID_DFR0, COPSDBG, 4, 4) 2059 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2060 FIELD(ID_DFR0, COPTRC, 12, 4) 2061 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2062 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2063 FIELD(ID_DFR0, PERFMON, 24, 4) 2064 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2065 2066 FIELD(ID_DFR1, MTPMU, 0, 4) 2067 2068 FIELD(DBGDIDR, SE_IMP, 12, 1) 2069 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2070 FIELD(DBGDIDR, VERSION, 16, 4) 2071 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2072 FIELD(DBGDIDR, BRPS, 24, 4) 2073 FIELD(DBGDIDR, WRPS, 28, 4) 2074 2075 FIELD(MVFR0, SIMDREG, 0, 4) 2076 FIELD(MVFR0, FPSP, 4, 4) 2077 FIELD(MVFR0, FPDP, 8, 4) 2078 FIELD(MVFR0, FPTRAP, 12, 4) 2079 FIELD(MVFR0, FPDIVIDE, 16, 4) 2080 FIELD(MVFR0, FPSQRT, 20, 4) 2081 FIELD(MVFR0, FPSHVEC, 24, 4) 2082 FIELD(MVFR0, FPROUND, 28, 4) 2083 2084 FIELD(MVFR1, FPFTZ, 0, 4) 2085 FIELD(MVFR1, FPDNAN, 4, 4) 2086 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2087 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2088 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2089 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2090 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2091 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2092 FIELD(MVFR1, FPHP, 24, 4) 2093 FIELD(MVFR1, SIMDFMAC, 28, 4) 2094 2095 FIELD(MVFR2, SIMDMISC, 0, 4) 2096 FIELD(MVFR2, FPMISC, 4, 4) 2097 2098 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2099 2100 /* If adding a feature bit which corresponds to a Linux ELF 2101 * HWCAP bit, remember to update the feature-bit-to-hwcap 2102 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2103 */ 2104 enum arm_features { 2105 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2106 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2107 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2108 ARM_FEATURE_V6, 2109 ARM_FEATURE_V6K, 2110 ARM_FEATURE_V7, 2111 ARM_FEATURE_THUMB2, 2112 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2113 ARM_FEATURE_NEON, 2114 ARM_FEATURE_M, /* Microcontroller profile. */ 2115 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2116 ARM_FEATURE_THUMB2EE, 2117 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2118 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2119 ARM_FEATURE_V4T, 2120 ARM_FEATURE_V5, 2121 ARM_FEATURE_STRONGARM, 2122 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2123 ARM_FEATURE_GENERIC_TIMER, 2124 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2125 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2126 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2127 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2128 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2129 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2130 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2131 ARM_FEATURE_V8, 2132 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2133 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2134 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2135 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2136 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2137 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2138 ARM_FEATURE_PMU, /* has PMU support */ 2139 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2140 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2141 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2142 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2143 }; 2144 2145 static inline int arm_feature(CPUARMState *env, int feature) 2146 { 2147 return (env->features & (1ULL << feature)) != 0; 2148 } 2149 2150 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2151 2152 #if !defined(CONFIG_USER_ONLY) 2153 /* Return true if exception levels below EL3 are in secure state, 2154 * or would be following an exception return to that level. 2155 * Unlike arm_is_secure() (which is always a question about the 2156 * _current_ state of the CPU) this doesn't care about the current 2157 * EL or mode. 2158 */ 2159 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2160 { 2161 if (arm_feature(env, ARM_FEATURE_EL3)) { 2162 return !(env->cp15.scr_el3 & SCR_NS); 2163 } else { 2164 /* If EL3 is not supported then the secure state is implementation 2165 * defined, in which case QEMU defaults to non-secure. 2166 */ 2167 return false; 2168 } 2169 } 2170 2171 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2172 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2173 { 2174 if (arm_feature(env, ARM_FEATURE_EL3)) { 2175 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2176 /* CPU currently in AArch64 state and EL3 */ 2177 return true; 2178 } else if (!is_a64(env) && 2179 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2180 /* CPU currently in AArch32 state and monitor mode */ 2181 return true; 2182 } 2183 } 2184 return false; 2185 } 2186 2187 /* Return true if the processor is in secure state */ 2188 static inline bool arm_is_secure(CPUARMState *env) 2189 { 2190 if (arm_is_el3_or_mon(env)) { 2191 return true; 2192 } 2193 return arm_is_secure_below_el3(env); 2194 } 2195 2196 /* 2197 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2198 * This corresponds to the pseudocode EL2Enabled() 2199 */ 2200 static inline bool arm_is_el2_enabled(CPUARMState *env) 2201 { 2202 if (arm_feature(env, ARM_FEATURE_EL2)) { 2203 if (arm_is_secure_below_el3(env)) { 2204 return (env->cp15.scr_el3 & SCR_EEL2) != 0; 2205 } 2206 return true; 2207 } 2208 return false; 2209 } 2210 2211 #else 2212 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2213 { 2214 return false; 2215 } 2216 2217 static inline bool arm_is_secure(CPUARMState *env) 2218 { 2219 return false; 2220 } 2221 2222 static inline bool arm_is_el2_enabled(CPUARMState *env) 2223 { 2224 return false; 2225 } 2226 #endif 2227 2228 /** 2229 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2230 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2231 * "for all purposes other than a direct read or write access of HCR_EL2." 2232 * Not included here is HCR_RW. 2233 */ 2234 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2235 2236 /* Return true if the specified exception level is running in AArch64 state. */ 2237 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2238 { 2239 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2240 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2241 */ 2242 assert(el >= 1 && el <= 3); 2243 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2244 2245 /* The highest exception level is always at the maximum supported 2246 * register width, and then lower levels have a register width controlled 2247 * by bits in the SCR or HCR registers. 2248 */ 2249 if (el == 3) { 2250 return aa64; 2251 } 2252 2253 if (arm_feature(env, ARM_FEATURE_EL3) && 2254 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2255 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2256 } 2257 2258 if (el == 2) { 2259 return aa64; 2260 } 2261 2262 if (arm_is_el2_enabled(env)) { 2263 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2264 } 2265 2266 return aa64; 2267 } 2268 2269 /* Function for determing whether guest cp register reads and writes should 2270 * access the secure or non-secure bank of a cp register. When EL3 is 2271 * operating in AArch32 state, the NS-bit determines whether the secure 2272 * instance of a cp register should be used. When EL3 is AArch64 (or if 2273 * it doesn't exist at all) then there is no register banking, and all 2274 * accesses are to the non-secure version. 2275 */ 2276 static inline bool access_secure_reg(CPUARMState *env) 2277 { 2278 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2279 !arm_el_is_aa64(env, 3) && 2280 !(env->cp15.scr_el3 & SCR_NS)); 2281 2282 return ret; 2283 } 2284 2285 /* Macros for accessing a specified CP register bank */ 2286 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2287 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2288 2289 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2290 do { \ 2291 if (_secure) { \ 2292 (_env)->cp15._regname##_s = (_val); \ 2293 } else { \ 2294 (_env)->cp15._regname##_ns = (_val); \ 2295 } \ 2296 } while (0) 2297 2298 /* Macros for automatically accessing a specific CP register bank depending on 2299 * the current secure state of the system. These macros are not intended for 2300 * supporting instruction translation reads/writes as these are dependent 2301 * solely on the SCR.NS bit and not the mode. 2302 */ 2303 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2304 A32_BANKED_REG_GET((_env), _regname, \ 2305 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2306 2307 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2308 A32_BANKED_REG_SET((_env), _regname, \ 2309 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2310 (_val)) 2311 2312 void arm_cpu_list(void); 2313 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2314 uint32_t cur_el, bool secure); 2315 2316 /* Interface between CPU and Interrupt controller. */ 2317 #ifndef CONFIG_USER_ONLY 2318 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2319 #else 2320 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2321 { 2322 return true; 2323 } 2324 #endif 2325 /** 2326 * armv7m_nvic_set_pending: mark the specified exception as pending 2327 * @opaque: the NVIC 2328 * @irq: the exception number to mark pending 2329 * @secure: false for non-banked exceptions or for the nonsecure 2330 * version of a banked exception, true for the secure version of a banked 2331 * exception. 2332 * 2333 * Marks the specified exception as pending. Note that we will assert() 2334 * if @secure is true and @irq does not specify one of the fixed set 2335 * of architecturally banked exceptions. 2336 */ 2337 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2338 /** 2339 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2340 * @opaque: the NVIC 2341 * @irq: the exception number to mark pending 2342 * @secure: false for non-banked exceptions or for the nonsecure 2343 * version of a banked exception, true for the secure version of a banked 2344 * exception. 2345 * 2346 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2347 * exceptions (exceptions generated in the course of trying to take 2348 * a different exception). 2349 */ 2350 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2351 /** 2352 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2353 * @opaque: the NVIC 2354 * @irq: the exception number to mark pending 2355 * @secure: false for non-banked exceptions or for the nonsecure 2356 * version of a banked exception, true for the secure version of a banked 2357 * exception. 2358 * 2359 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2360 * generated in the course of lazy stacking of FP registers. 2361 */ 2362 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2363 /** 2364 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2365 * exception, and whether it targets Secure state 2366 * @opaque: the NVIC 2367 * @pirq: set to pending exception number 2368 * @ptargets_secure: set to whether pending exception targets Secure 2369 * 2370 * This function writes the number of the highest priority pending 2371 * exception (the one which would be made active by 2372 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2373 * to true if the current highest priority pending exception should 2374 * be taken to Secure state, false for NS. 2375 */ 2376 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2377 bool *ptargets_secure); 2378 /** 2379 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2380 * @opaque: the NVIC 2381 * 2382 * Move the current highest priority pending exception from the pending 2383 * state to the active state, and update v7m.exception to indicate that 2384 * it is the exception currently being handled. 2385 */ 2386 void armv7m_nvic_acknowledge_irq(void *opaque); 2387 /** 2388 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2389 * @opaque: the NVIC 2390 * @irq: the exception number to complete 2391 * @secure: true if this exception was secure 2392 * 2393 * Returns: -1 if the irq was not active 2394 * 1 if completing this irq brought us back to base (no active irqs) 2395 * 0 if there is still an irq active after this one was completed 2396 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2397 */ 2398 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2399 /** 2400 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2401 * @opaque: the NVIC 2402 * @irq: the exception number to mark pending 2403 * @secure: false for non-banked exceptions or for the nonsecure 2404 * version of a banked exception, true for the secure version of a banked 2405 * exception. 2406 * 2407 * Return whether an exception is "ready", i.e. whether the exception is 2408 * enabled and is configured at a priority which would allow it to 2409 * interrupt the current execution priority. This controls whether the 2410 * RDY bit for it in the FPCCR is set. 2411 */ 2412 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2413 /** 2414 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2415 * @opaque: the NVIC 2416 * 2417 * Returns: the raw execution priority as defined by the v8M architecture. 2418 * This is the execution priority minus the effects of AIRCR.PRIS, 2419 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2420 * (v8M ARM ARM I_PKLD.) 2421 */ 2422 int armv7m_nvic_raw_execution_priority(void *opaque); 2423 /** 2424 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2425 * priority is negative for the specified security state. 2426 * @opaque: the NVIC 2427 * @secure: the security state to test 2428 * This corresponds to the pseudocode IsReqExecPriNeg(). 2429 */ 2430 #ifndef CONFIG_USER_ONLY 2431 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2432 #else 2433 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2434 { 2435 return false; 2436 } 2437 #endif 2438 2439 /* Interface for defining coprocessor registers. 2440 * Registers are defined in tables of arm_cp_reginfo structs 2441 * which are passed to define_arm_cp_regs(). 2442 */ 2443 2444 /* When looking up a coprocessor register we look for it 2445 * via an integer which encodes all of: 2446 * coprocessor number 2447 * Crn, Crm, opc1, opc2 fields 2448 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2449 * or via MRRC/MCRR?) 2450 * non-secure/secure bank (AArch32 only) 2451 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2452 * (In this case crn and opc2 should be zero.) 2453 * For AArch64, there is no 32/64 bit size distinction; 2454 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2455 * and 4 bit CRn and CRm. The encoding patterns are chosen 2456 * to be easy to convert to and from the KVM encodings, and also 2457 * so that the hashtable can contain both AArch32 and AArch64 2458 * registers (to allow for interprocessing where we might run 2459 * 32 bit code on a 64 bit core). 2460 */ 2461 /* This bit is private to our hashtable cpreg; in KVM register 2462 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2463 * in the upper bits of the 64 bit ID. 2464 */ 2465 #define CP_REG_AA64_SHIFT 28 2466 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2467 2468 /* To enable banking of coprocessor registers depending on ns-bit we 2469 * add a bit to distinguish between secure and non-secure cpregs in the 2470 * hashtable. 2471 */ 2472 #define CP_REG_NS_SHIFT 29 2473 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2474 2475 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2476 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2477 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2478 2479 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2480 (CP_REG_AA64_MASK | \ 2481 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2482 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2483 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2484 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2485 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2486 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2487 2488 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2489 * version used as a key for the coprocessor register hashtable 2490 */ 2491 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2492 { 2493 uint32_t cpregid = kvmid; 2494 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2495 cpregid |= CP_REG_AA64_MASK; 2496 } else { 2497 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2498 cpregid |= (1 << 15); 2499 } 2500 2501 /* KVM is always non-secure so add the NS flag on AArch32 register 2502 * entries. 2503 */ 2504 cpregid |= 1 << CP_REG_NS_SHIFT; 2505 } 2506 return cpregid; 2507 } 2508 2509 /* Convert a truncated 32 bit hashtable key into the full 2510 * 64 bit KVM register ID. 2511 */ 2512 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2513 { 2514 uint64_t kvmid; 2515 2516 if (cpregid & CP_REG_AA64_MASK) { 2517 kvmid = cpregid & ~CP_REG_AA64_MASK; 2518 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2519 } else { 2520 kvmid = cpregid & ~(1 << 15); 2521 if (cpregid & (1 << 15)) { 2522 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2523 } else { 2524 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2525 } 2526 } 2527 return kvmid; 2528 } 2529 2530 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2531 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2532 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2533 * TCG can assume the value to be constant (ie load at translate time) 2534 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2535 * indicates that the TB should not be ended after a write to this register 2536 * (the default is that the TB ends after cp writes). OVERRIDE permits 2537 * a register definition to override a previous definition for the 2538 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2539 * old must have the OVERRIDE bit set. 2540 * ALIAS indicates that this register is an alias view of some underlying 2541 * state which is also visible via another register, and that the other 2542 * register is handling migration and reset; registers marked ALIAS will not be 2543 * migrated but may have their state set by syncing of register state from KVM. 2544 * NO_RAW indicates that this register has no underlying state and does not 2545 * support raw access for state saving/loading; it will not be used for either 2546 * migration or KVM state synchronization. (Typically this is for "registers" 2547 * which are actually used as instructions for cache maintenance and so on.) 2548 * IO indicates that this register does I/O and therefore its accesses 2549 * need to be marked with gen_io_start() and also end the TB. In particular, 2550 * registers which implement clocks or timers require this. 2551 * RAISES_EXC is for when the read or write hook might raise an exception; 2552 * the generated code will synchronize the CPU state before calling the hook 2553 * so that it is safe for the hook to call raise_exception(). 2554 * NEWEL is for writes to registers that might change the exception 2555 * level - typically on older ARM chips. For those cases we need to 2556 * re-read the new el when recomputing the translation flags. 2557 */ 2558 #define ARM_CP_SPECIAL 0x0001 2559 #define ARM_CP_CONST 0x0002 2560 #define ARM_CP_64BIT 0x0004 2561 #define ARM_CP_SUPPRESS_TB_END 0x0008 2562 #define ARM_CP_OVERRIDE 0x0010 2563 #define ARM_CP_ALIAS 0x0020 2564 #define ARM_CP_IO 0x0040 2565 #define ARM_CP_NO_RAW 0x0080 2566 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2567 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2568 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2569 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2570 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2571 #define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) 2572 #define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) 2573 #define ARM_LAST_SPECIAL ARM_CP_DC_GZVA 2574 #define ARM_CP_FPU 0x1000 2575 #define ARM_CP_SVE 0x2000 2576 #define ARM_CP_NO_GDB 0x4000 2577 #define ARM_CP_RAISES_EXC 0x8000 2578 #define ARM_CP_NEWEL 0x10000 2579 /* Used only as a terminator for ARMCPRegInfo lists */ 2580 #define ARM_CP_SENTINEL 0xfffff 2581 /* Mask of only the flag bits in a type field */ 2582 #define ARM_CP_FLAG_MASK 0x1f0ff 2583 2584 /* Valid values for ARMCPRegInfo state field, indicating which of 2585 * the AArch32 and AArch64 execution states this register is visible in. 2586 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2587 * If the reginfo is declared to be visible in both states then a second 2588 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2589 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2590 * Note that we rely on the values of these enums as we iterate through 2591 * the various states in some places. 2592 */ 2593 enum { 2594 ARM_CP_STATE_AA32 = 0, 2595 ARM_CP_STATE_AA64 = 1, 2596 ARM_CP_STATE_BOTH = 2, 2597 }; 2598 2599 /* ARM CP register secure state flags. These flags identify security state 2600 * attributes for a given CP register entry. 2601 * The existence of both or neither secure and non-secure flags indicates that 2602 * the register has both a secure and non-secure hash entry. A single one of 2603 * these flags causes the register to only be hashed for the specified 2604 * security state. 2605 * Although definitions may have any combination of the S/NS bits, each 2606 * registered entry will only have one to identify whether the entry is secure 2607 * or non-secure. 2608 */ 2609 enum { 2610 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2611 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2612 }; 2613 2614 /* Return true if cptype is a valid type field. This is used to try to 2615 * catch errors where the sentinel has been accidentally left off the end 2616 * of a list of registers. 2617 */ 2618 static inline bool cptype_valid(int cptype) 2619 { 2620 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2621 || ((cptype & ARM_CP_SPECIAL) && 2622 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2623 } 2624 2625 /* Access rights: 2626 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2627 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2628 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2629 * (ie any of the privileged modes in Secure state, or Monitor mode). 2630 * If a register is accessible in one privilege level it's always accessible 2631 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2632 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2633 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2634 * terminology a little and call this PL3. 2635 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2636 * with the ELx exception levels. 2637 * 2638 * If access permissions for a register are more complex than can be 2639 * described with these bits, then use a laxer set of restrictions, and 2640 * do the more restrictive/complex check inside a helper function. 2641 */ 2642 #define PL3_R 0x80 2643 #define PL3_W 0x40 2644 #define PL2_R (0x20 | PL3_R) 2645 #define PL2_W (0x10 | PL3_W) 2646 #define PL1_R (0x08 | PL2_R) 2647 #define PL1_W (0x04 | PL2_W) 2648 #define PL0_R (0x02 | PL1_R) 2649 #define PL0_W (0x01 | PL1_W) 2650 2651 /* 2652 * For user-mode some registers are accessible to EL0 via a kernel 2653 * trap-and-emulate ABI. In this case we define the read permissions 2654 * as actually being PL0_R. However some bits of any given register 2655 * may still be masked. 2656 */ 2657 #ifdef CONFIG_USER_ONLY 2658 #define PL0U_R PL0_R 2659 #else 2660 #define PL0U_R PL1_R 2661 #endif 2662 2663 #define PL3_RW (PL3_R | PL3_W) 2664 #define PL2_RW (PL2_R | PL2_W) 2665 #define PL1_RW (PL1_R | PL1_W) 2666 #define PL0_RW (PL0_R | PL0_W) 2667 2668 /* Return the highest implemented Exception Level */ 2669 static inline int arm_highest_el(CPUARMState *env) 2670 { 2671 if (arm_feature(env, ARM_FEATURE_EL3)) { 2672 return 3; 2673 } 2674 if (arm_feature(env, ARM_FEATURE_EL2)) { 2675 return 2; 2676 } 2677 return 1; 2678 } 2679 2680 /* Return true if a v7M CPU is in Handler mode */ 2681 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2682 { 2683 return env->v7m.exception != 0; 2684 } 2685 2686 /* Return the current Exception Level (as per ARMv8; note that this differs 2687 * from the ARMv7 Privilege Level). 2688 */ 2689 static inline int arm_current_el(CPUARMState *env) 2690 { 2691 if (arm_feature(env, ARM_FEATURE_M)) { 2692 return arm_v7m_is_handler_mode(env) || 2693 !(env->v7m.control[env->v7m.secure] & 1); 2694 } 2695 2696 if (is_a64(env)) { 2697 return extract32(env->pstate, 2, 2); 2698 } 2699 2700 switch (env->uncached_cpsr & 0x1f) { 2701 case ARM_CPU_MODE_USR: 2702 return 0; 2703 case ARM_CPU_MODE_HYP: 2704 return 2; 2705 case ARM_CPU_MODE_MON: 2706 return 3; 2707 default: 2708 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2709 /* If EL3 is 32-bit then all secure privileged modes run in 2710 * EL3 2711 */ 2712 return 3; 2713 } 2714 2715 return 1; 2716 } 2717 } 2718 2719 typedef struct ARMCPRegInfo ARMCPRegInfo; 2720 2721 typedef enum CPAccessResult { 2722 /* Access is permitted */ 2723 CP_ACCESS_OK = 0, 2724 /* Access fails due to a configurable trap or enable which would 2725 * result in a categorized exception syndrome giving information about 2726 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2727 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2728 * PL1 if in EL0, otherwise to the current EL). 2729 */ 2730 CP_ACCESS_TRAP = 1, 2731 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2732 * Note that this is not a catch-all case -- the set of cases which may 2733 * result in this failure is specifically defined by the architecture. 2734 */ 2735 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2736 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2737 CP_ACCESS_TRAP_EL2 = 3, 2738 CP_ACCESS_TRAP_EL3 = 4, 2739 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2740 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2741 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2742 /* Access fails and results in an exception syndrome for an FP access, 2743 * trapped directly to EL2 or EL3 2744 */ 2745 CP_ACCESS_TRAP_FP_EL2 = 7, 2746 CP_ACCESS_TRAP_FP_EL3 = 8, 2747 } CPAccessResult; 2748 2749 /* Access functions for coprocessor registers. These cannot fail and 2750 * may not raise exceptions. 2751 */ 2752 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2753 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2754 uint64_t value); 2755 /* Access permission check functions for coprocessor registers. */ 2756 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2757 const ARMCPRegInfo *opaque, 2758 bool isread); 2759 /* Hook function for register reset */ 2760 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2761 2762 #define CP_ANY 0xff 2763 2764 /* Definition of an ARM coprocessor register */ 2765 struct ARMCPRegInfo { 2766 /* Name of register (useful mainly for debugging, need not be unique) */ 2767 const char *name; 2768 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2769 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2770 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2771 * will be decoded to this register. The register read and write 2772 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2773 * used by the program, so it is possible to register a wildcard and 2774 * then behave differently on read/write if necessary. 2775 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2776 * must both be zero. 2777 * For AArch64-visible registers, opc0 is also used. 2778 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2779 * way to distinguish (for KVM's benefit) guest-visible system registers 2780 * from demuxed ones provided to preserve the "no side effects on 2781 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2782 * visible (to match KVM's encoding); cp==0 will be converted to 2783 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2784 */ 2785 uint8_t cp; 2786 uint8_t crn; 2787 uint8_t crm; 2788 uint8_t opc0; 2789 uint8_t opc1; 2790 uint8_t opc2; 2791 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2792 int state; 2793 /* Register type: ARM_CP_* bits/values */ 2794 int type; 2795 /* Access rights: PL*_[RW] */ 2796 int access; 2797 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2798 int secure; 2799 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2800 * this register was defined: can be used to hand data through to the 2801 * register read/write functions, since they are passed the ARMCPRegInfo*. 2802 */ 2803 void *opaque; 2804 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2805 * fieldoffset is non-zero, the reset value of the register. 2806 */ 2807 uint64_t resetvalue; 2808 /* Offset of the field in CPUARMState for this register. 2809 * 2810 * This is not needed if either: 2811 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2812 * 2. both readfn and writefn are specified 2813 */ 2814 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2815 2816 /* Offsets of the secure and non-secure fields in CPUARMState for the 2817 * register if it is banked. These fields are only used during the static 2818 * registration of a register. During hashing the bank associated 2819 * with a given security state is copied to fieldoffset which is used from 2820 * there on out. 2821 * 2822 * It is expected that register definitions use either fieldoffset or 2823 * bank_fieldoffsets in the definition but not both. It is also expected 2824 * that both bank offsets are set when defining a banked register. This 2825 * use indicates that a register is banked. 2826 */ 2827 ptrdiff_t bank_fieldoffsets[2]; 2828 2829 /* Function for making any access checks for this register in addition to 2830 * those specified by the 'access' permissions bits. If NULL, no extra 2831 * checks required. The access check is performed at runtime, not at 2832 * translate time. 2833 */ 2834 CPAccessFn *accessfn; 2835 /* Function for handling reads of this register. If NULL, then reads 2836 * will be done by loading from the offset into CPUARMState specified 2837 * by fieldoffset. 2838 */ 2839 CPReadFn *readfn; 2840 /* Function for handling writes of this register. If NULL, then writes 2841 * will be done by writing to the offset into CPUARMState specified 2842 * by fieldoffset. 2843 */ 2844 CPWriteFn *writefn; 2845 /* Function for doing a "raw" read; used when we need to copy 2846 * coprocessor state to the kernel for KVM or out for 2847 * migration. This only needs to be provided if there is also a 2848 * readfn and it has side effects (for instance clear-on-read bits). 2849 */ 2850 CPReadFn *raw_readfn; 2851 /* Function for doing a "raw" write; used when we need to copy KVM 2852 * kernel coprocessor state into userspace, or for inbound 2853 * migration. This only needs to be provided if there is also a 2854 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2855 * or similar behaviour. 2856 */ 2857 CPWriteFn *raw_writefn; 2858 /* Function for resetting the register. If NULL, then reset will be done 2859 * by writing resetvalue to the field specified in fieldoffset. If 2860 * fieldoffset is 0 then no reset will be done. 2861 */ 2862 CPResetFn *resetfn; 2863 2864 /* 2865 * "Original" writefn and readfn. 2866 * For ARMv8.1-VHE register aliases, we overwrite the read/write 2867 * accessor functions of various EL1/EL0 to perform the runtime 2868 * check for which sysreg should actually be modified, and then 2869 * forwards the operation. Before overwriting the accessors, 2870 * the original function is copied here, so that accesses that 2871 * really do go to the EL1/EL0 version proceed normally. 2872 * (The corresponding EL2 register is linked via opaque.) 2873 */ 2874 CPReadFn *orig_readfn; 2875 CPWriteFn *orig_writefn; 2876 }; 2877 2878 /* Macros which are lvalues for the field in CPUARMState for the 2879 * ARMCPRegInfo *ri. 2880 */ 2881 #define CPREG_FIELD32(env, ri) \ 2882 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2883 #define CPREG_FIELD64(env, ri) \ 2884 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2885 2886 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2887 2888 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2889 const ARMCPRegInfo *regs, void *opaque); 2890 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2891 const ARMCPRegInfo *regs, void *opaque); 2892 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2893 { 2894 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2895 } 2896 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2897 { 2898 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2899 } 2900 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2901 2902 /* 2903 * Definition of an ARM co-processor register as viewed from 2904 * userspace. This is used for presenting sanitised versions of 2905 * registers to userspace when emulating the Linux AArch64 CPU 2906 * ID/feature ABI (advertised as HWCAP_CPUID). 2907 */ 2908 typedef struct ARMCPRegUserSpaceInfo { 2909 /* Name of register */ 2910 const char *name; 2911 2912 /* Is the name actually a glob pattern */ 2913 bool is_glob; 2914 2915 /* Only some bits are exported to user space */ 2916 uint64_t exported_bits; 2917 2918 /* Fixed bits are applied after the mask */ 2919 uint64_t fixed_bits; 2920 } ARMCPRegUserSpaceInfo; 2921 2922 #define REGUSERINFO_SENTINEL { .name = NULL } 2923 2924 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2925 2926 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2927 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2928 uint64_t value); 2929 /* CPReadFn that can be used for read-as-zero behaviour */ 2930 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2931 2932 /* CPResetFn that does nothing, for use if no reset is required even 2933 * if fieldoffset is non zero. 2934 */ 2935 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2936 2937 /* Return true if this reginfo struct's field in the cpu state struct 2938 * is 64 bits wide. 2939 */ 2940 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2941 { 2942 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2943 } 2944 2945 static inline bool cp_access_ok(int current_el, 2946 const ARMCPRegInfo *ri, int isread) 2947 { 2948 return (ri->access >> ((current_el * 2) + isread)) & 1; 2949 } 2950 2951 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2952 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2953 2954 /** 2955 * write_list_to_cpustate 2956 * @cpu: ARMCPU 2957 * 2958 * For each register listed in the ARMCPU cpreg_indexes list, write 2959 * its value from the cpreg_values list into the ARMCPUState structure. 2960 * This updates TCG's working data structures from KVM data or 2961 * from incoming migration state. 2962 * 2963 * Returns: true if all register values were updated correctly, 2964 * false if some register was unknown or could not be written. 2965 * Note that we do not stop early on failure -- we will attempt 2966 * writing all registers in the list. 2967 */ 2968 bool write_list_to_cpustate(ARMCPU *cpu); 2969 2970 /** 2971 * write_cpustate_to_list: 2972 * @cpu: ARMCPU 2973 * @kvm_sync: true if this is for syncing back to KVM 2974 * 2975 * For each register listed in the ARMCPU cpreg_indexes list, write 2976 * its value from the ARMCPUState structure into the cpreg_values list. 2977 * This is used to copy info from TCG's working data structures into 2978 * KVM or for outbound migration. 2979 * 2980 * @kvm_sync is true if we are doing this in order to sync the 2981 * register state back to KVM. In this case we will only update 2982 * values in the list if the previous list->cpustate sync actually 2983 * successfully wrote the CPU state. Otherwise we will keep the value 2984 * that is in the list. 2985 * 2986 * Returns: true if all register values were read correctly, 2987 * false if some register was unknown or could not be read. 2988 * Note that we do not stop early on failure -- we will attempt 2989 * reading all registers in the list. 2990 */ 2991 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2992 2993 #define ARM_CPUID_TI915T 0x54029152 2994 #define ARM_CPUID_TI925T 0x54029252 2995 2996 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2997 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2998 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2999 3000 #define cpu_signal_handler cpu_arm_signal_handler 3001 #define cpu_list arm_cpu_list 3002 3003 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 3004 * 3005 * If EL3 is 64-bit: 3006 * + NonSecure EL1 & 0 stage 1 3007 * + NonSecure EL1 & 0 stage 2 3008 * + NonSecure EL2 3009 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 3010 * + Secure EL1 & 0 3011 * + Secure EL3 3012 * If EL3 is 32-bit: 3013 * + NonSecure PL1 & 0 stage 1 3014 * + NonSecure PL1 & 0 stage 2 3015 * + NonSecure PL2 3016 * + Secure PL0 3017 * + Secure PL1 3018 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 3019 * 3020 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 3021 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 3022 * because they may differ in access permissions even if the VA->PA map is 3023 * the same 3024 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 3025 * translation, which means that we have one mmu_idx that deals with two 3026 * concatenated translation regimes [this sort of combined s1+2 TLB is 3027 * architecturally permitted] 3028 * 3. we don't need to allocate an mmu_idx to translations that we won't be 3029 * handling via the TLB. The only way to do a stage 1 translation without 3030 * the immediate stage 2 translation is via the ATS or AT system insns, 3031 * which can be slow-pathed and always do a page table walk. 3032 * The only use of stage 2 translations is either as part of an s1+2 3033 * lookup or when loading the descriptors during a stage 1 page table walk, 3034 * and in both those cases we don't use the TLB. 3035 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 3036 * translation regimes, because they map reasonably well to each other 3037 * and they can't both be active at the same time. 3038 * 5. we want to be able to use the TLB for accesses done as part of a 3039 * stage1 page table walk, rather than having to walk the stage2 page 3040 * table over and over. 3041 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 3042 * Never (PAN) bit within PSTATE. 3043 * 3044 * This gives us the following list of cases: 3045 * 3046 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 3047 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 3048 * NS EL1 EL1&0 stage 1+2 +PAN 3049 * NS EL0 EL2&0 3050 * NS EL2 EL2&0 3051 * NS EL2 EL2&0 +PAN 3052 * NS EL2 (aka NS PL2) 3053 * S EL0 EL1&0 (aka S PL0) 3054 * S EL1 EL1&0 (not used if EL3 is 32 bit) 3055 * S EL1 EL1&0 +PAN 3056 * S EL3 (aka S PL1) 3057 * 3058 * for a total of 11 different mmu_idx. 3059 * 3060 * R profile CPUs have an MPU, but can use the same set of MMU indexes 3061 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 3062 * NS EL2 if we ever model a Cortex-R52). 3063 * 3064 * M profile CPUs are rather different as they do not have a true MMU. 3065 * They have the following different MMU indexes: 3066 * User 3067 * Privileged 3068 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 3069 * Privileged, execution priority negative (ditto) 3070 * If the CPU supports the v8M Security Extension then there are also: 3071 * Secure User 3072 * Secure Privileged 3073 * Secure User, execution priority negative 3074 * Secure Privileged, execution priority negative 3075 * 3076 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 3077 * are not quite the same -- different CPU types (most notably M profile 3078 * vs A/R profile) would like to use MMU indexes with different semantics, 3079 * but since we don't ever need to use all of those in a single CPU we 3080 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 3081 * modes + total number of M profile MMU modes". The lower bits of 3082 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 3083 * the same for any particular CPU. 3084 * Variables of type ARMMUIdx are always full values, and the core 3085 * index values are in variables of type 'int'. 3086 * 3087 * Our enumeration includes at the end some entries which are not "true" 3088 * mmu_idx values in that they don't have corresponding TLBs and are only 3089 * valid for doing slow path page table walks. 3090 * 3091 * The constant names here are patterned after the general style of the names 3092 * of the AT/ATS operations. 3093 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 3094 * For M profile we arrange them to have a bit for priv, a bit for negpri 3095 * and a bit for secure. 3096 */ 3097 #define ARM_MMU_IDX_A 0x10 /* A profile */ 3098 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 3099 #define ARM_MMU_IDX_M 0x40 /* M profile */ 3100 3101 /* Meanings of the bits for A profile mmu idx values */ 3102 #define ARM_MMU_IDX_A_NS 0x8 3103 3104 /* Meanings of the bits for M profile mmu idx values */ 3105 #define ARM_MMU_IDX_M_PRIV 0x1 3106 #define ARM_MMU_IDX_M_NEGPRI 0x2 3107 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 3108 3109 #define ARM_MMU_IDX_TYPE_MASK \ 3110 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 3111 #define ARM_MMU_IDX_COREIDX_MASK 0xf 3112 3113 typedef enum ARMMMUIdx { 3114 /* 3115 * A-profile. 3116 */ 3117 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, 3118 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, 3119 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, 3120 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, 3121 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, 3122 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, 3123 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, 3124 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, 3125 3126 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, 3127 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, 3128 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, 3129 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, 3130 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, 3131 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, 3132 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, 3133 3134 /* 3135 * These are not allocated TLBs and are used only for AT system 3136 * instructions or for the first stage of an S12 page table walk. 3137 */ 3138 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 3139 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 3140 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 3141 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, 3142 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, 3143 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, 3144 /* 3145 * Not allocated a TLB: used only for second stage of an S12 page 3146 * table walk, or for descriptor loads during first stage of an S1 3147 * page table walk. Note that if we ever want to have a TLB for this 3148 * then various TLB flush insns which currently are no-ops or flush 3149 * only stage 1 MMU indexes will need to change to flush stage 2. 3150 */ 3151 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, 3152 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, 3153 3154 /* 3155 * M-profile. 3156 */ 3157 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 3158 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 3159 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 3160 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 3161 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 3162 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 3163 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 3164 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 3165 } ARMMMUIdx; 3166 3167 /* 3168 * Bit macros for the core-mmu-index values for each index, 3169 * for use when calling tlb_flush_by_mmuidx() and friends. 3170 */ 3171 #define TO_CORE_BIT(NAME) \ 3172 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 3173 3174 typedef enum ARMMMUIdxBit { 3175 TO_CORE_BIT(E10_0), 3176 TO_CORE_BIT(E20_0), 3177 TO_CORE_BIT(E10_1), 3178 TO_CORE_BIT(E10_1_PAN), 3179 TO_CORE_BIT(E2), 3180 TO_CORE_BIT(E20_2), 3181 TO_CORE_BIT(E20_2_PAN), 3182 TO_CORE_BIT(SE10_0), 3183 TO_CORE_BIT(SE20_0), 3184 TO_CORE_BIT(SE10_1), 3185 TO_CORE_BIT(SE20_2), 3186 TO_CORE_BIT(SE10_1_PAN), 3187 TO_CORE_BIT(SE20_2_PAN), 3188 TO_CORE_BIT(SE2), 3189 TO_CORE_BIT(SE3), 3190 3191 TO_CORE_BIT(MUser), 3192 TO_CORE_BIT(MPriv), 3193 TO_CORE_BIT(MUserNegPri), 3194 TO_CORE_BIT(MPrivNegPri), 3195 TO_CORE_BIT(MSUser), 3196 TO_CORE_BIT(MSPriv), 3197 TO_CORE_BIT(MSUserNegPri), 3198 TO_CORE_BIT(MSPrivNegPri), 3199 } ARMMMUIdxBit; 3200 3201 #undef TO_CORE_BIT 3202 3203 #define MMU_USER_IDX 0 3204 3205 /* Indexes used when registering address spaces with cpu_address_space_init */ 3206 typedef enum ARMASIdx { 3207 ARMASIdx_NS = 0, 3208 ARMASIdx_S = 1, 3209 ARMASIdx_TagNS = 2, 3210 ARMASIdx_TagS = 3, 3211 } ARMASIdx; 3212 3213 /* Return the Exception Level targeted by debug exceptions. */ 3214 static inline int arm_debug_target_el(CPUARMState *env) 3215 { 3216 bool secure = arm_is_secure(env); 3217 bool route_to_el2 = false; 3218 3219 if (arm_is_el2_enabled(env)) { 3220 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 3221 env->cp15.mdcr_el2 & MDCR_TDE; 3222 } 3223 3224 if (route_to_el2) { 3225 return 2; 3226 } else if (arm_feature(env, ARM_FEATURE_EL3) && 3227 !arm_el_is_aa64(env, 3) && secure) { 3228 return 3; 3229 } else { 3230 return 1; 3231 } 3232 } 3233 3234 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3235 { 3236 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3237 * CSSELR is RAZ/WI. 3238 */ 3239 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3240 } 3241 3242 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 3243 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 3244 { 3245 int cur_el = arm_current_el(env); 3246 int debug_el; 3247 3248 if (cur_el == 3) { 3249 return false; 3250 } 3251 3252 /* MDCR_EL3.SDD disables debug events from Secure state */ 3253 if (arm_is_secure_below_el3(env) 3254 && extract32(env->cp15.mdcr_el3, 16, 1)) { 3255 return false; 3256 } 3257 3258 /* 3259 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 3260 * while not masking the (D)ebug bit in DAIF. 3261 */ 3262 debug_el = arm_debug_target_el(env); 3263 3264 if (cur_el == debug_el) { 3265 return extract32(env->cp15.mdscr_el1, 13, 1) 3266 && !(env->daif & PSTATE_D); 3267 } 3268 3269 /* Otherwise the debug target needs to be a higher EL */ 3270 return debug_el > cur_el; 3271 } 3272 3273 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 3274 { 3275 int el = arm_current_el(env); 3276 3277 if (el == 0 && arm_el_is_aa64(env, 1)) { 3278 return aa64_generate_debug_exceptions(env); 3279 } 3280 3281 if (arm_is_secure(env)) { 3282 int spd; 3283 3284 if (el == 0 && (env->cp15.sder & 1)) { 3285 /* SDER.SUIDEN means debug exceptions from Secure EL0 3286 * are always enabled. Otherwise they are controlled by 3287 * SDCR.SPD like those from other Secure ELs. 3288 */ 3289 return true; 3290 } 3291 3292 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3293 switch (spd) { 3294 case 1: 3295 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3296 case 0: 3297 /* For 0b00 we return true if external secure invasive debug 3298 * is enabled. On real hardware this is controlled by external 3299 * signals to the core. QEMU always permits debug, and behaves 3300 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3301 */ 3302 return true; 3303 case 2: 3304 return false; 3305 case 3: 3306 return true; 3307 } 3308 } 3309 3310 return el != 2; 3311 } 3312 3313 /* Return true if debugging exceptions are currently enabled. 3314 * This corresponds to what in ARM ARM pseudocode would be 3315 * if UsingAArch32() then 3316 * return AArch32.GenerateDebugExceptions() 3317 * else 3318 * return AArch64.GenerateDebugExceptions() 3319 * We choose to push the if() down into this function for clarity, 3320 * since the pseudocode has it at all callsites except for the one in 3321 * CheckSoftwareStep(), where it is elided because both branches would 3322 * always return the same value. 3323 */ 3324 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3325 { 3326 if (env->aarch64) { 3327 return aa64_generate_debug_exceptions(env); 3328 } else { 3329 return aa32_generate_debug_exceptions(env); 3330 } 3331 } 3332 3333 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3334 * implicitly means this always returns false in pre-v8 CPUs.) 3335 */ 3336 static inline bool arm_singlestep_active(CPUARMState *env) 3337 { 3338 return extract32(env->cp15.mdscr_el1, 0, 1) 3339 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3340 && arm_generate_debug_exceptions(env); 3341 } 3342 3343 static inline bool arm_sctlr_b(CPUARMState *env) 3344 { 3345 return 3346 /* We need not implement SCTLR.ITD in user-mode emulation, so 3347 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3348 * This lets people run BE32 binaries with "-cpu any". 3349 */ 3350 #ifndef CONFIG_USER_ONLY 3351 !arm_feature(env, ARM_FEATURE_V7) && 3352 #endif 3353 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3354 } 3355 3356 uint64_t arm_sctlr(CPUARMState *env, int el); 3357 3358 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3359 bool sctlr_b) 3360 { 3361 #ifdef CONFIG_USER_ONLY 3362 /* 3363 * In system mode, BE32 is modelled in line with the 3364 * architecture (as word-invariant big-endianness), where loads 3365 * and stores are done little endian but from addresses which 3366 * are adjusted by XORing with the appropriate constant. So the 3367 * endianness to use for the raw data access is not affected by 3368 * SCTLR.B. 3369 * In user mode, however, we model BE32 as byte-invariant 3370 * big-endianness (because user-only code cannot tell the 3371 * difference), and so we need to use a data access endianness 3372 * that depends on SCTLR.B. 3373 */ 3374 if (sctlr_b) { 3375 return true; 3376 } 3377 #endif 3378 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3379 return env->uncached_cpsr & CPSR_E; 3380 } 3381 3382 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3383 { 3384 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3385 } 3386 3387 /* Return true if the processor is in big-endian mode. */ 3388 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3389 { 3390 if (!is_a64(env)) { 3391 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3392 } else { 3393 int cur_el = arm_current_el(env); 3394 uint64_t sctlr = arm_sctlr(env, cur_el); 3395 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3396 } 3397 } 3398 3399 typedef CPUARMState CPUArchState; 3400 typedef ARMCPU ArchCPU; 3401 3402 #include "exec/cpu-all.h" 3403 3404 /* 3405 * We have more than 32-bits worth of state per TB, so we split the data 3406 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3407 * We collect these two parts in CPUARMTBFlags where they are named 3408 * flags and flags2 respectively. 3409 * 3410 * The flags that are shared between all execution modes, TBFLAG_ANY, 3411 * are stored in flags. The flags that are specific to a given mode 3412 * are stores in flags2. Since cs_base is sized on the configured 3413 * address size, flags2 always has 64-bits for A64, and a minimum of 3414 * 32-bits for A32 and M32. 3415 * 3416 * The bits for 32-bit A-profile and M-profile partially overlap: 3417 * 3418 * 31 23 11 10 0 3419 * +-------------+----------+----------------+ 3420 * | | | TBFLAG_A32 | 3421 * | TBFLAG_AM32 | +-----+----------+ 3422 * | | |TBFLAG_M32| 3423 * +-------------+----------------+----------+ 3424 * 31 23 5 4 0 3425 * 3426 * Unless otherwise noted, these bits are cached in env->hflags. 3427 */ 3428 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3429 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3430 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3431 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3432 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3433 /* Target EL if we take a floating-point-disabled exception */ 3434 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3435 /* For A-profile only, target EL for debug exceptions. */ 3436 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) 3437 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3438 FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) 3439 3440 /* 3441 * Bit usage when in AArch32 state, both A- and M-profile. 3442 */ 3443 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3444 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3445 3446 /* 3447 * Bit usage when in AArch32 state, for A-profile only. 3448 */ 3449 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3450 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3451 /* 3452 * We store the bottom two bits of the CPAR as TB flags and handle 3453 * checks on the other bits at runtime. This shares the same bits as 3454 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3455 * Not cached, because VECLEN+VECSTRIDE are not cached. 3456 */ 3457 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3458 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3459 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3460 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3461 /* 3462 * Indicates whether cp register reads and writes by guest code should access 3463 * the secure or nonsecure bank of banked registers; note that this is not 3464 * the same thing as the current security state of the processor! 3465 */ 3466 FIELD(TBFLAG_A32, NS, 10, 1) 3467 3468 /* 3469 * Bit usage when in AArch32 state, for M-profile only. 3470 */ 3471 /* Handler (ie not Thread) mode */ 3472 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3473 /* Whether we should generate stack-limit checks */ 3474 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3475 /* Set if FPCCR.LSPACT is set */ 3476 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3477 /* Set if we must create a new FP context */ 3478 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3479 /* Set if FPCCR.S does not match current security state */ 3480 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3481 3482 /* 3483 * Bit usage when in AArch64 state 3484 */ 3485 FIELD(TBFLAG_A64, TBII, 0, 2) 3486 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3487 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3488 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3489 FIELD(TBFLAG_A64, BT, 9, 1) 3490 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3491 FIELD(TBFLAG_A64, TBID, 12, 2) 3492 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3493 FIELD(TBFLAG_A64, ATA, 15, 1) 3494 FIELD(TBFLAG_A64, TCMA, 16, 2) 3495 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3496 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3497 3498 /* 3499 * Helpers for using the above. 3500 */ 3501 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3502 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3503 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3504 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3505 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3506 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3507 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3508 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3509 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3510 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3511 3512 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3513 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3514 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3515 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3516 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3517 3518 /** 3519 * cpu_mmu_index: 3520 * @env: The cpu environment 3521 * @ifetch: True for code access, false for data access. 3522 * 3523 * Return the core mmu index for the current translation regime. 3524 * This function is used by generic TCG code paths. 3525 */ 3526 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3527 { 3528 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3529 } 3530 3531 static inline bool bswap_code(bool sctlr_b) 3532 { 3533 #ifdef CONFIG_USER_ONLY 3534 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3535 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3536 * would also end up as a mixed-endian mode with BE code, LE data. 3537 */ 3538 return 3539 #ifdef TARGET_WORDS_BIGENDIAN 3540 1 ^ 3541 #endif 3542 sctlr_b; 3543 #else 3544 /* All code access in ARM is little endian, and there are no loaders 3545 * doing swaps that need to be reversed 3546 */ 3547 return 0; 3548 #endif 3549 } 3550 3551 #ifdef CONFIG_USER_ONLY 3552 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3553 { 3554 return 3555 #ifdef TARGET_WORDS_BIGENDIAN 3556 1 ^ 3557 #endif 3558 arm_cpu_data_is_big_endian(env); 3559 } 3560 #endif 3561 3562 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3563 target_ulong *cs_base, uint32_t *flags); 3564 3565 enum { 3566 QEMU_PSCI_CONDUIT_DISABLED = 0, 3567 QEMU_PSCI_CONDUIT_SMC = 1, 3568 QEMU_PSCI_CONDUIT_HVC = 2, 3569 }; 3570 3571 #ifndef CONFIG_USER_ONLY 3572 /* Return the address space index to use for a memory access */ 3573 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3574 { 3575 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3576 } 3577 3578 /* Return the AddressSpace to use for a memory access 3579 * (which depends on whether the access is S or NS, and whether 3580 * the board gave us a separate AddressSpace for S accesses). 3581 */ 3582 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3583 { 3584 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3585 } 3586 #endif 3587 3588 /** 3589 * arm_register_pre_el_change_hook: 3590 * Register a hook function which will be called immediately before this 3591 * CPU changes exception level or mode. The hook function will be 3592 * passed a pointer to the ARMCPU and the opaque data pointer passed 3593 * to this function when the hook was registered. 3594 * 3595 * Note that if a pre-change hook is called, any registered post-change hooks 3596 * are guaranteed to subsequently be called. 3597 */ 3598 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3599 void *opaque); 3600 /** 3601 * arm_register_el_change_hook: 3602 * Register a hook function which will be called immediately after this 3603 * CPU changes exception level or mode. The hook function will be 3604 * passed a pointer to the ARMCPU and the opaque data pointer passed 3605 * to this function when the hook was registered. 3606 * 3607 * Note that any registered hooks registered here are guaranteed to be called 3608 * if pre-change hooks have been. 3609 */ 3610 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3611 *opaque); 3612 3613 /** 3614 * arm_rebuild_hflags: 3615 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3616 */ 3617 void arm_rebuild_hflags(CPUARMState *env); 3618 3619 /** 3620 * aa32_vfp_dreg: 3621 * Return a pointer to the Dn register within env in 32-bit mode. 3622 */ 3623 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3624 { 3625 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3626 } 3627 3628 /** 3629 * aa32_vfp_qreg: 3630 * Return a pointer to the Qn register within env in 32-bit mode. 3631 */ 3632 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3633 { 3634 return &env->vfp.zregs[regno].d[0]; 3635 } 3636 3637 /** 3638 * aa64_vfp_qreg: 3639 * Return a pointer to the Qn register within env in 64-bit mode. 3640 */ 3641 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3642 { 3643 return &env->vfp.zregs[regno].d[0]; 3644 } 3645 3646 /* Shared between translate-sve.c and sve_helper.c. */ 3647 extern const uint64_t pred_esz_masks[4]; 3648 3649 /* Helper for the macros below, validating the argument type. */ 3650 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) 3651 { 3652 return x; 3653 } 3654 3655 /* 3656 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. 3657 * Using these should be a bit more self-documenting than using the 3658 * generic target bits directly. 3659 */ 3660 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) 3661 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) 3662 3663 /* 3664 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3665 */ 3666 #define PAGE_BTI PAGE_TARGET_1 3667 #define PAGE_MTE PAGE_TARGET_2 3668 3669 #ifdef TARGET_TAGGED_ADDRESSES 3670 /** 3671 * cpu_untagged_addr: 3672 * @cs: CPU context 3673 * @x: tagged address 3674 * 3675 * Remove any address tag from @x. This is explicitly related to the 3676 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3677 * 3678 * There should be a better place to put this, but we need this in 3679 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3680 */ 3681 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3682 { 3683 ARMCPU *cpu = ARM_CPU(cs); 3684 if (cpu->env.tagged_addr_enable) { 3685 /* 3686 * TBI is enabled for userspace but not kernelspace addresses. 3687 * Only clear the tag if bit 55 is clear. 3688 */ 3689 x &= sextract64(x, 0, 56); 3690 } 3691 return x; 3692 } 3693 #endif 3694 3695 /* 3696 * Naming convention for isar_feature functions: 3697 * Functions which test 32-bit ID registers should have _aa32_ in 3698 * their name. Functions which test 64-bit ID registers should have 3699 * _aa64_ in their name. These must only be used in code where we 3700 * know for certain that the CPU has AArch32 or AArch64 respectively 3701 * or where the correct answer for a CPU which doesn't implement that 3702 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3703 * system registers that are specific to that CPU state, for "should 3704 * we let this system register bit be set" tests where the 32-bit 3705 * flavour of the register doesn't have the bit, and so on). 3706 * Functions which simply ask "does this feature exist at all" have 3707 * _any_ in their name, and always return the logical OR of the _aa64_ 3708 * and the _aa32_ function. 3709 */ 3710 3711 /* 3712 * 32-bit feature tests via id registers. 3713 */ 3714 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3715 { 3716 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3717 } 3718 3719 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3720 { 3721 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3722 } 3723 3724 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3725 { 3726 /* (M-profile) low-overhead loops and branch future */ 3727 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3728 } 3729 3730 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3731 { 3732 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3733 } 3734 3735 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3736 { 3737 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3738 } 3739 3740 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3741 { 3742 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3743 } 3744 3745 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3746 { 3747 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3748 } 3749 3750 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3751 { 3752 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3753 } 3754 3755 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3756 { 3757 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3758 } 3759 3760 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3761 { 3762 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3763 } 3764 3765 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3766 { 3767 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3768 } 3769 3770 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3771 { 3772 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3773 } 3774 3775 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3776 { 3777 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3778 } 3779 3780 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3781 { 3782 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3783 } 3784 3785 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3786 { 3787 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3788 } 3789 3790 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3791 { 3792 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3793 } 3794 3795 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3796 { 3797 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3798 } 3799 3800 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3801 { 3802 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3803 } 3804 3805 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3806 { 3807 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3808 } 3809 3810 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3811 { 3812 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3813 } 3814 3815 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3816 { 3817 /* 3818 * Return true if M-profile state handling insns 3819 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3820 */ 3821 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3822 } 3823 3824 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3825 { 3826 /* Sadly this is encoded differently for A-profile and M-profile */ 3827 if (isar_feature_aa32_mprofile(id)) { 3828 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3829 } else { 3830 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3831 } 3832 } 3833 3834 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3835 { 3836 /* 3837 * Return true if MVE is supported (either integer or floating point). 3838 * We must check for M-profile as the MVFR1 field means something 3839 * else for A-profile. 3840 */ 3841 return isar_feature_aa32_mprofile(id) && 3842 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3843 } 3844 3845 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3846 { 3847 /* 3848 * Return true if MVE is supported (either integer or floating point). 3849 * We must check for M-profile as the MVFR1 field means something 3850 * else for A-profile. 3851 */ 3852 return isar_feature_aa32_mprofile(id) && 3853 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3854 } 3855 3856 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3857 { 3858 /* 3859 * Return true if either VFP or SIMD is implemented. 3860 * In this case, a minimum of VFP w/ D0-D15. 3861 */ 3862 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3863 } 3864 3865 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3866 { 3867 /* Return true if D16-D31 are implemented */ 3868 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3869 } 3870 3871 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3872 { 3873 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3874 } 3875 3876 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3877 { 3878 /* Return true if CPU supports single precision floating point, VFPv2 */ 3879 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3880 } 3881 3882 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3883 { 3884 /* Return true if CPU supports single precision floating point, VFPv3 */ 3885 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3886 } 3887 3888 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3889 { 3890 /* Return true if CPU supports double precision floating point, VFPv2 */ 3891 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3892 } 3893 3894 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3895 { 3896 /* Return true if CPU supports double precision floating point, VFPv3 */ 3897 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3898 } 3899 3900 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3901 { 3902 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3903 } 3904 3905 /* 3906 * We always set the FP and SIMD FP16 fields to indicate identical 3907 * levels of support (assuming SIMD is implemented at all), so 3908 * we only need one set of accessors. 3909 */ 3910 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3911 { 3912 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3913 } 3914 3915 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3916 { 3917 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3918 } 3919 3920 /* 3921 * Note that this ID register field covers both VFP and Neon FMAC, 3922 * so should usually be tested in combination with some other 3923 * check that confirms the presence of whichever of VFP or Neon is 3924 * relevant, to avoid accidentally enabling a Neon feature on 3925 * a VFP-no-Neon core or vice-versa. 3926 */ 3927 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3928 { 3929 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3930 } 3931 3932 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3933 { 3934 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3935 } 3936 3937 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3938 { 3939 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3940 } 3941 3942 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3943 { 3944 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3945 } 3946 3947 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3948 { 3949 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3950 } 3951 3952 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3953 { 3954 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3955 } 3956 3957 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3958 { 3959 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3960 } 3961 3962 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3963 { 3964 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3965 } 3966 3967 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3968 { 3969 /* 0xf means "non-standard IMPDEF PMU" */ 3970 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3971 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3972 } 3973 3974 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3975 { 3976 /* 0xf means "non-standard IMPDEF PMU" */ 3977 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3978 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3979 } 3980 3981 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3982 { 3983 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3984 } 3985 3986 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3987 { 3988 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3989 } 3990 3991 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3992 { 3993 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3994 } 3995 3996 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3997 { 3998 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3999 } 4000 4001 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 4002 { 4003 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 4004 } 4005 4006 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 4007 { 4008 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 4009 } 4010 4011 /* 4012 * 64-bit feature tests via id registers. 4013 */ 4014 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 4015 { 4016 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 4017 } 4018 4019 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 4020 { 4021 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 4022 } 4023 4024 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 4025 { 4026 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 4027 } 4028 4029 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 4030 { 4031 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 4032 } 4033 4034 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 4035 { 4036 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 4037 } 4038 4039 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 4040 { 4041 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 4042 } 4043 4044 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 4045 { 4046 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 4047 } 4048 4049 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 4050 { 4051 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 4052 } 4053 4054 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 4055 { 4056 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 4057 } 4058 4059 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 4060 { 4061 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 4062 } 4063 4064 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 4065 { 4066 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 4067 } 4068 4069 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 4070 { 4071 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 4072 } 4073 4074 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 4075 { 4076 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 4077 } 4078 4079 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 4080 { 4081 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 4082 } 4083 4084 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 4085 { 4086 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 4087 } 4088 4089 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 4090 { 4091 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 4092 } 4093 4094 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 4095 { 4096 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 4097 } 4098 4099 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 4100 { 4101 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 4102 } 4103 4104 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 4105 { 4106 /* 4107 * Return true if any form of pauth is enabled, as this 4108 * predicate controls migration of the 128-bit keys. 4109 */ 4110 return (id->id_aa64isar1 & 4111 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 4112 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 4113 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 4114 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 4115 } 4116 4117 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 4118 { 4119 /* 4120 * Return true if pauth is enabled with the architected QARMA algorithm. 4121 * QEMU will always set APA+GPA to the same value. 4122 */ 4123 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 4124 } 4125 4126 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 4127 { 4128 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 4129 } 4130 4131 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 4132 { 4133 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 4134 } 4135 4136 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 4137 { 4138 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 4139 } 4140 4141 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 4142 { 4143 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 4144 } 4145 4146 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 4147 { 4148 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 4149 } 4150 4151 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 4152 { 4153 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 4154 } 4155 4156 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 4157 { 4158 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 4159 } 4160 4161 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 4162 { 4163 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 4164 } 4165 4166 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 4167 { 4168 /* We always set the AdvSIMD and FP fields identically. */ 4169 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 4170 } 4171 4172 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 4173 { 4174 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 4175 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 4176 } 4177 4178 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 4179 { 4180 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 4181 } 4182 4183 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 4184 { 4185 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 4186 } 4187 4188 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 4189 { 4190 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 4191 } 4192 4193 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 4194 { 4195 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 4196 } 4197 4198 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 4199 { 4200 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 4201 } 4202 4203 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 4204 { 4205 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 4206 } 4207 4208 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 4209 { 4210 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 4211 } 4212 4213 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 4214 { 4215 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 4216 } 4217 4218 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 4219 { 4220 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 4221 } 4222 4223 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 4224 { 4225 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 4226 } 4227 4228 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 4229 { 4230 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 4231 } 4232 4233 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 4234 { 4235 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 4236 } 4237 4238 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 4239 { 4240 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 4241 } 4242 4243 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 4244 { 4245 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 4246 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4247 } 4248 4249 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 4250 { 4251 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 4252 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4253 } 4254 4255 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 4256 { 4257 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 4258 } 4259 4260 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 4261 { 4262 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 4263 } 4264 4265 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 4266 { 4267 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 4268 } 4269 4270 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4271 { 4272 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4273 } 4274 4275 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4276 { 4277 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4278 } 4279 4280 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4281 { 4282 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4283 } 4284 4285 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4286 { 4287 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4288 } 4289 4290 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4291 { 4292 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4293 } 4294 4295 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4296 { 4297 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4298 } 4299 4300 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4301 { 4302 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4303 } 4304 4305 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4306 { 4307 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4308 } 4309 4310 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4311 { 4312 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4313 } 4314 4315 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4316 { 4317 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4318 } 4319 4320 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4321 { 4322 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4323 } 4324 4325 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4326 { 4327 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4328 } 4329 4330 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4331 { 4332 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4333 } 4334 4335 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4336 { 4337 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4338 } 4339 4340 /* 4341 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4342 */ 4343 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4344 { 4345 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4346 } 4347 4348 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4349 { 4350 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4351 } 4352 4353 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 4354 { 4355 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 4356 } 4357 4358 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 4359 { 4360 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 4361 } 4362 4363 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4364 { 4365 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4366 } 4367 4368 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4369 { 4370 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4371 } 4372 4373 /* 4374 * Forward to the above feature tests given an ARMCPU pointer. 4375 */ 4376 #define cpu_isar_feature(name, cpu) \ 4377 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4378 4379 #endif 4380