1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 #define VTCR_NSW (1u << 29) 170 #define VTCR_NSA (1u << 30) 171 #define VSTCR_SW VTCR_NSW 172 #define VSTCR_SA VTCR_NSA 173 174 /* Define a maximum sized vector register. 175 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 176 * For 64-bit, this is a 2048-bit SVE register. 177 * 178 * Note that the mapping between S, D, and Q views of the register bank 179 * differs between AArch64 and AArch32. 180 * In AArch32: 181 * Qn = regs[n].d[1]:regs[n].d[0] 182 * Dn = regs[n / 2].d[n & 1] 183 * Sn = regs[n / 4].d[n % 4 / 2], 184 * bits 31..0 for even n, and bits 63..32 for odd n 185 * (and regs[16] to regs[31] are inaccessible) 186 * In AArch64: 187 * Zn = regs[n].d[*] 188 * Qn = regs[n].d[1]:regs[n].d[0] 189 * Dn = regs[n].d[0] 190 * Sn = regs[n].d[0] bits 31..0 191 * Hn = regs[n].d[0] bits 15..0 192 * 193 * This corresponds to the architecturally defined mapping between 194 * the two execution states, and means we do not need to explicitly 195 * map these registers when changing states. 196 * 197 * Align the data for use with TCG host vector operations. 198 */ 199 200 #ifdef TARGET_AARCH64 201 # define ARM_MAX_VQ 16 202 #else 203 # define ARM_MAX_VQ 1 204 #endif 205 206 typedef struct ARMVectorReg { 207 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 208 } ARMVectorReg; 209 210 #ifdef TARGET_AARCH64 211 /* In AArch32 mode, predicate registers do not exist at all. */ 212 typedef struct ARMPredicateReg { 213 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 214 } ARMPredicateReg; 215 216 /* In AArch32 mode, PAC keys do not exist at all. */ 217 typedef struct ARMPACKey { 218 uint64_t lo, hi; 219 } ARMPACKey; 220 #endif 221 222 /* See the commentary above the TBFLAG field definitions. */ 223 typedef struct CPUARMTBFlags { 224 uint32_t flags; 225 target_ulong flags2; 226 } CPUARMTBFlags; 227 228 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 229 230 typedef struct NVICState NVICState; 231 232 typedef struct CPUArchState { 233 /* Regs for current mode. */ 234 uint32_t regs[16]; 235 236 /* 32/64 switch only happens when taking and returning from 237 * exceptions so the overlap semantics are taken care of then 238 * instead of having a complicated union. 239 */ 240 /* Regs for A64 mode. */ 241 uint64_t xregs[32]; 242 uint64_t pc; 243 /* PSTATE isn't an architectural register for ARMv8. However, it is 244 * convenient for us to assemble the underlying state into a 32 bit format 245 * identical to the architectural format used for the SPSR. (This is also 246 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 247 * 'pstate' register are.) Of the PSTATE bits: 248 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 249 * semantics as for AArch32, as described in the comments on each field) 250 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 251 * DAIF (exception masks) are kept in env->daif 252 * BTYPE is kept in env->btype 253 * SM and ZA are kept in env->svcr 254 * all other bits are stored in their correct places in env->pstate 255 */ 256 uint32_t pstate; 257 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 258 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 259 260 /* Cached TBFLAGS state. See below for which bits are included. */ 261 CPUARMTBFlags hflags; 262 263 /* Frequently accessed CPSR bits are stored separately for efficiency. 264 This contains all the other bits. Use cpsr_{read,write} to access 265 the whole CPSR. */ 266 uint32_t uncached_cpsr; 267 uint32_t spsr; 268 269 /* Banked registers. */ 270 uint64_t banked_spsr[8]; 271 uint32_t banked_r13[8]; 272 uint32_t banked_r14[8]; 273 274 /* These hold r8-r12. */ 275 uint32_t usr_regs[5]; 276 uint32_t fiq_regs[5]; 277 278 /* cpsr flag cache for faster execution */ 279 uint32_t CF; /* 0 or 1 */ 280 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 281 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 282 uint32_t ZF; /* Z set if zero. */ 283 uint32_t QF; /* 0 or 1 */ 284 uint32_t GE; /* cpsr[19:16] */ 285 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 286 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 287 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 288 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 289 290 uint64_t elr_el[4]; /* AArch64 exception link regs */ 291 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 292 293 /* System control coprocessor (cp15) */ 294 struct { 295 uint32_t c0_cpuid; 296 union { /* Cache size selection */ 297 struct { 298 uint64_t _unused_csselr0; 299 uint64_t csselr_ns; 300 uint64_t _unused_csselr1; 301 uint64_t csselr_s; 302 }; 303 uint64_t csselr_el[4]; 304 }; 305 union { /* System control register. */ 306 struct { 307 uint64_t _unused_sctlr; 308 uint64_t sctlr_ns; 309 uint64_t hsctlr; 310 uint64_t sctlr_s; 311 }; 312 uint64_t sctlr_el[4]; 313 }; 314 uint64_t vsctlr; /* Virtualization System control register. */ 315 uint64_t cpacr_el1; /* Architectural feature access control register */ 316 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 317 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 318 uint64_t sder; /* Secure debug enable register. */ 319 uint32_t nsacr; /* Non-secure access control register. */ 320 union { /* MMU translation table base 0. */ 321 struct { 322 uint64_t _unused_ttbr0_0; 323 uint64_t ttbr0_ns; 324 uint64_t _unused_ttbr0_1; 325 uint64_t ttbr0_s; 326 }; 327 uint64_t ttbr0_el[4]; 328 }; 329 union { /* MMU translation table base 1. */ 330 struct { 331 uint64_t _unused_ttbr1_0; 332 uint64_t ttbr1_ns; 333 uint64_t _unused_ttbr1_1; 334 uint64_t ttbr1_s; 335 }; 336 uint64_t ttbr1_el[4]; 337 }; 338 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 339 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 340 /* MMU translation table base control. */ 341 uint64_t tcr_el[4]; 342 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 343 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 344 uint32_t c2_data; /* MPU data cacheable bits. */ 345 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 346 union { /* MMU domain access control register 347 * MPU write buffer control. 348 */ 349 struct { 350 uint64_t dacr_ns; 351 uint64_t dacr_s; 352 }; 353 struct { 354 uint64_t dacr32_el2; 355 }; 356 }; 357 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 358 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 359 uint64_t hcr_el2; /* Hypervisor configuration register */ 360 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 361 uint64_t scr_el3; /* Secure configuration register. */ 362 union { /* Fault status registers. */ 363 struct { 364 uint64_t ifsr_ns; 365 uint64_t ifsr_s; 366 }; 367 struct { 368 uint64_t ifsr32_el2; 369 }; 370 }; 371 union { 372 struct { 373 uint64_t _unused_dfsr; 374 uint64_t dfsr_ns; 375 uint64_t hsr; 376 uint64_t dfsr_s; 377 }; 378 uint64_t esr_el[4]; 379 }; 380 uint32_t c6_region[8]; /* MPU base/size registers. */ 381 union { /* Fault address registers. */ 382 struct { 383 uint64_t _unused_far0; 384 #if HOST_BIG_ENDIAN 385 uint32_t ifar_ns; 386 uint32_t dfar_ns; 387 uint32_t ifar_s; 388 uint32_t dfar_s; 389 #else 390 uint32_t dfar_ns; 391 uint32_t ifar_ns; 392 uint32_t dfar_s; 393 uint32_t ifar_s; 394 #endif 395 uint64_t _unused_far3; 396 }; 397 uint64_t far_el[4]; 398 }; 399 uint64_t hpfar_el2; 400 uint64_t hstr_el2; 401 union { /* Translation result. */ 402 struct { 403 uint64_t _unused_par_0; 404 uint64_t par_ns; 405 uint64_t _unused_par_1; 406 uint64_t par_s; 407 }; 408 uint64_t par_el[4]; 409 }; 410 411 uint32_t c9_insn; /* Cache lockdown registers. */ 412 uint32_t c9_data; 413 uint64_t c9_pmcr; /* performance monitor control register */ 414 uint64_t c9_pmcnten; /* perf monitor counter enables */ 415 uint64_t c9_pmovsr; /* perf monitor overflow status */ 416 uint64_t c9_pmuserenr; /* perf monitor user enable */ 417 uint64_t c9_pmselr; /* perf monitor counter selection register */ 418 uint64_t c9_pminten; /* perf monitor interrupt enables */ 419 union { /* Memory attribute redirection */ 420 struct { 421 #if HOST_BIG_ENDIAN 422 uint64_t _unused_mair_0; 423 uint32_t mair1_ns; 424 uint32_t mair0_ns; 425 uint64_t _unused_mair_1; 426 uint32_t mair1_s; 427 uint32_t mair0_s; 428 #else 429 uint64_t _unused_mair_0; 430 uint32_t mair0_ns; 431 uint32_t mair1_ns; 432 uint64_t _unused_mair_1; 433 uint32_t mair0_s; 434 uint32_t mair1_s; 435 #endif 436 }; 437 uint64_t mair_el[4]; 438 }; 439 union { /* vector base address register */ 440 struct { 441 uint64_t _unused_vbar; 442 uint64_t vbar_ns; 443 uint64_t hvbar; 444 uint64_t vbar_s; 445 }; 446 uint64_t vbar_el[4]; 447 }; 448 uint32_t mvbar; /* (monitor) vector base address register */ 449 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 450 struct { /* FCSE PID. */ 451 uint32_t fcseidr_ns; 452 uint32_t fcseidr_s; 453 }; 454 union { /* Context ID. */ 455 struct { 456 uint64_t _unused_contextidr_0; 457 uint64_t contextidr_ns; 458 uint64_t _unused_contextidr_1; 459 uint64_t contextidr_s; 460 }; 461 uint64_t contextidr_el[4]; 462 }; 463 union { /* User RW Thread register. */ 464 struct { 465 uint64_t tpidrurw_ns; 466 uint64_t tpidrprw_ns; 467 uint64_t htpidr; 468 uint64_t _tpidr_el3; 469 }; 470 uint64_t tpidr_el[4]; 471 }; 472 uint64_t tpidr2_el0; 473 /* The secure banks of these registers don't map anywhere */ 474 uint64_t tpidrurw_s; 475 uint64_t tpidrprw_s; 476 uint64_t tpidruro_s; 477 478 union { /* User RO Thread register. */ 479 uint64_t tpidruro_ns; 480 uint64_t tpidrro_el[1]; 481 }; 482 uint64_t c14_cntfrq; /* Counter Frequency register */ 483 uint64_t c14_cntkctl; /* Timer Control register */ 484 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 485 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 486 ARMGenericTimer c14_timer[NUM_GTIMERS]; 487 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 488 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 489 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 490 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 491 uint32_t c15_threadid; /* TI debugger thread-ID. */ 492 uint32_t c15_config_base_address; /* SCU base address. */ 493 uint32_t c15_diagnostic; /* diagnostic register */ 494 uint32_t c15_power_diagnostic; 495 uint32_t c15_power_control; /* power control */ 496 uint64_t dbgbvr[16]; /* breakpoint value registers */ 497 uint64_t dbgbcr[16]; /* breakpoint control registers */ 498 uint64_t dbgwvr[16]; /* watchpoint value registers */ 499 uint64_t dbgwcr[16]; /* watchpoint control registers */ 500 uint64_t dbgclaim; /* DBGCLAIM bits */ 501 uint64_t mdscr_el1; 502 uint64_t oslsr_el1; /* OS Lock Status */ 503 uint64_t osdlr_el1; /* OS DoubleLock status */ 504 uint64_t mdcr_el2; 505 uint64_t mdcr_el3; 506 /* Stores the architectural value of the counter *the last time it was 507 * updated* by pmccntr_op_start. Accesses should always be surrounded 508 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 509 * architecturally-correct value is being read/set. 510 */ 511 uint64_t c15_ccnt; 512 /* Stores the delta between the architectural value and the underlying 513 * cycle count during normal operation. It is used to update c15_ccnt 514 * to be the correct architectural value before accesses. During 515 * accesses, c15_ccnt_delta contains the underlying count being used 516 * for the access, after which it reverts to the delta value in 517 * pmccntr_op_finish. 518 */ 519 uint64_t c15_ccnt_delta; 520 uint64_t c14_pmevcntr[31]; 521 uint64_t c14_pmevcntr_delta[31]; 522 uint64_t c14_pmevtyper[31]; 523 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 524 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 525 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 526 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 527 uint64_t gcr_el1; 528 uint64_t rgsr_el1; 529 530 /* Minimal RAS registers */ 531 uint64_t disr_el1; 532 uint64_t vdisr_el2; 533 uint64_t vsesr_el2; 534 535 /* 536 * Fine-Grained Trap registers. We store these as arrays so the 537 * access checking code doesn't have to manually select 538 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 539 * FEAT_FGT2 will add more elements to these arrays. 540 */ 541 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 542 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 543 uint64_t fgt_exec[1]; /* HFGITR */ 544 } cp15; 545 546 struct { 547 /* M profile has up to 4 stack pointers: 548 * a Main Stack Pointer and a Process Stack Pointer for each 549 * of the Secure and Non-Secure states. (If the CPU doesn't support 550 * the security extension then it has only two SPs.) 551 * In QEMU we always store the currently active SP in regs[13], 552 * and the non-active SP for the current security state in 553 * v7m.other_sp. The stack pointers for the inactive security state 554 * are stored in other_ss_msp and other_ss_psp. 555 * switch_v7m_security_state() is responsible for rearranging them 556 * when we change security state. 557 */ 558 uint32_t other_sp; 559 uint32_t other_ss_msp; 560 uint32_t other_ss_psp; 561 uint32_t vecbase[M_REG_NUM_BANKS]; 562 uint32_t basepri[M_REG_NUM_BANKS]; 563 uint32_t control[M_REG_NUM_BANKS]; 564 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 565 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 566 uint32_t hfsr; /* HardFault Status */ 567 uint32_t dfsr; /* Debug Fault Status Register */ 568 uint32_t sfsr; /* Secure Fault Status Register */ 569 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 570 uint32_t bfar; /* BusFault Address */ 571 uint32_t sfar; /* Secure Fault Address Register */ 572 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 573 int exception; 574 uint32_t primask[M_REG_NUM_BANKS]; 575 uint32_t faultmask[M_REG_NUM_BANKS]; 576 uint32_t aircr; /* only holds r/w state if security extn implemented */ 577 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 578 uint32_t csselr[M_REG_NUM_BANKS]; 579 uint32_t scr[M_REG_NUM_BANKS]; 580 uint32_t msplim[M_REG_NUM_BANKS]; 581 uint32_t psplim[M_REG_NUM_BANKS]; 582 uint32_t fpcar[M_REG_NUM_BANKS]; 583 uint32_t fpccr[M_REG_NUM_BANKS]; 584 uint32_t fpdscr[M_REG_NUM_BANKS]; 585 uint32_t cpacr[M_REG_NUM_BANKS]; 586 uint32_t nsacr; 587 uint32_t ltpsize; 588 uint32_t vpr; 589 } v7m; 590 591 /* Information associated with an exception about to be taken: 592 * code which raises an exception must set cs->exception_index and 593 * the relevant parts of this structure; the cpu_do_interrupt function 594 * will then set the guest-visible registers as part of the exception 595 * entry process. 596 */ 597 struct { 598 uint32_t syndrome; /* AArch64 format syndrome register */ 599 uint32_t fsr; /* AArch32 format fault status register info */ 600 uint64_t vaddress; /* virtual addr associated with exception, if any */ 601 uint32_t target_el; /* EL the exception should be targeted for */ 602 /* If we implement EL2 we will also need to store information 603 * about the intermediate physical address for stage 2 faults. 604 */ 605 } exception; 606 607 /* Information associated with an SError */ 608 struct { 609 uint8_t pending; 610 uint8_t has_esr; 611 uint64_t esr; 612 } serror; 613 614 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 615 616 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 617 uint32_t irq_line_state; 618 619 /* Thumb-2 EE state. */ 620 uint32_t teecr; 621 uint32_t teehbr; 622 623 /* VFP coprocessor state. */ 624 struct { 625 ARMVectorReg zregs[32]; 626 627 #ifdef TARGET_AARCH64 628 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 629 #define FFR_PRED_NUM 16 630 ARMPredicateReg pregs[17]; 631 /* Scratch space for aa64 sve predicate temporary. */ 632 ARMPredicateReg preg_tmp; 633 #endif 634 635 /* We store these fpcsr fields separately for convenience. */ 636 uint32_t qc[4] QEMU_ALIGNED(16); 637 int vec_len; 638 int vec_stride; 639 640 uint32_t xregs[16]; 641 642 /* Scratch space for aa32 neon expansion. */ 643 uint32_t scratch[8]; 644 645 /* There are a number of distinct float control structures: 646 * 647 * fp_status: is the "normal" fp status. 648 * fp_status_fp16: used for half-precision calculations 649 * standard_fp_status : the ARM "Standard FPSCR Value" 650 * standard_fp_status_fp16 : used for half-precision 651 * calculations with the ARM "Standard FPSCR Value" 652 * 653 * Half-precision operations are governed by a separate 654 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 655 * status structure to control this. 656 * 657 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 658 * round-to-nearest and is used by any operations (generally 659 * Neon) which the architecture defines as controlled by the 660 * standard FPSCR value rather than the FPSCR. 661 * 662 * The "standard FPSCR but for fp16 ops" is needed because 663 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 664 * using a fixed value for it. 665 * 666 * To avoid having to transfer exception bits around, we simply 667 * say that the FPSCR cumulative exception flags are the logical 668 * OR of the flags in the four fp statuses. This relies on the 669 * only thing which needs to read the exception flags being 670 * an explicit FPSCR read. 671 */ 672 float_status fp_status; 673 float_status fp_status_f16; 674 float_status standard_fp_status; 675 float_status standard_fp_status_f16; 676 677 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 678 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 679 } vfp; 680 uint64_t exclusive_addr; 681 uint64_t exclusive_val; 682 uint64_t exclusive_high; 683 684 /* iwMMXt coprocessor state. */ 685 struct { 686 uint64_t regs[16]; 687 uint64_t val; 688 689 uint32_t cregs[16]; 690 } iwmmxt; 691 692 #ifdef TARGET_AARCH64 693 struct { 694 ARMPACKey apia; 695 ARMPACKey apib; 696 ARMPACKey apda; 697 ARMPACKey apdb; 698 ARMPACKey apga; 699 } keys; 700 701 uint64_t scxtnum_el[4]; 702 703 /* 704 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 705 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 706 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 707 * When SVL is less than the architectural maximum, the accessible 708 * storage is restricted, such that if the SVL is X bytes the guest can 709 * see only the bottom X elements of zarray[], and only the least 710 * significant X bytes of each element of the array. (In other words, 711 * the observable part is always square.) 712 * 713 * The ZA storage can also be considered as a set of square tiles of 714 * elements of different sizes. The mapping from tiles to the ZA array 715 * is architecturally defined, such that for tiles of elements of esz 716 * bytes, the Nth row (or "horizontal slice") of tile T is in 717 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 718 * in the ZA storage, because its rows are striped through the ZA array. 719 * 720 * Because this is so large, keep this toward the end of the reset area, 721 * to keep the offsets into the rest of the structure smaller. 722 */ 723 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 724 #endif 725 726 struct CPUBreakpoint *cpu_breakpoint[16]; 727 struct CPUWatchpoint *cpu_watchpoint[16]; 728 729 /* Optional fault info across tlb lookup. */ 730 ARMMMUFaultInfo *tlb_fi; 731 732 /* Fields up to this point are cleared by a CPU reset */ 733 struct {} end_reset_fields; 734 735 /* Fields after this point are preserved across CPU reset. */ 736 737 /* Internal CPU feature flags. */ 738 uint64_t features; 739 740 /* PMSAv7 MPU */ 741 struct { 742 uint32_t *drbar; 743 uint32_t *drsr; 744 uint32_t *dracr; 745 uint32_t rnr[M_REG_NUM_BANKS]; 746 } pmsav7; 747 748 /* PMSAv8 MPU */ 749 struct { 750 /* The PMSAv8 implementation also shares some PMSAv7 config 751 * and state: 752 * pmsav7.rnr (region number register) 753 * pmsav7_dregion (number of configured regions) 754 */ 755 uint32_t *rbar[M_REG_NUM_BANKS]; 756 uint32_t *rlar[M_REG_NUM_BANKS]; 757 uint32_t *hprbar; 758 uint32_t *hprlar; 759 uint32_t mair0[M_REG_NUM_BANKS]; 760 uint32_t mair1[M_REG_NUM_BANKS]; 761 uint32_t hprselr; 762 } pmsav8; 763 764 /* v8M SAU */ 765 struct { 766 uint32_t *rbar; 767 uint32_t *rlar; 768 uint32_t rnr; 769 uint32_t ctrl; 770 } sau; 771 772 #if !defined(CONFIG_USER_ONLY) 773 NVICState *nvic; 774 const struct arm_boot_info *boot_info; 775 /* Store GICv3CPUState to access from this struct */ 776 void *gicv3state; 777 #else /* CONFIG_USER_ONLY */ 778 /* For usermode syscall translation. */ 779 bool eabi; 780 #endif /* CONFIG_USER_ONLY */ 781 782 #ifdef TARGET_TAGGED_ADDRESSES 783 /* Linux syscall tagged address support */ 784 bool tagged_addr_enable; 785 #endif 786 } CPUARMState; 787 788 static inline void set_feature(CPUARMState *env, int feature) 789 { 790 env->features |= 1ULL << feature; 791 } 792 793 static inline void unset_feature(CPUARMState *env, int feature) 794 { 795 env->features &= ~(1ULL << feature); 796 } 797 798 /** 799 * ARMELChangeHookFn: 800 * type of a function which can be registered via arm_register_el_change_hook() 801 * to get callbacks when the CPU changes its exception level or mode. 802 */ 803 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 804 typedef struct ARMELChangeHook ARMELChangeHook; 805 struct ARMELChangeHook { 806 ARMELChangeHookFn *hook; 807 void *opaque; 808 QLIST_ENTRY(ARMELChangeHook) node; 809 }; 810 811 /* These values map onto the return values for 812 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 813 typedef enum ARMPSCIState { 814 PSCI_ON = 0, 815 PSCI_OFF = 1, 816 PSCI_ON_PENDING = 2 817 } ARMPSCIState; 818 819 typedef struct ARMISARegisters ARMISARegisters; 820 821 /* 822 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 823 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 824 * 825 * While processing properties during initialization, corresponding init bits 826 * are set for bits in sve_vq_map that have been set by properties. 827 * 828 * Bits set in supported represent valid vector lengths for the CPU type. 829 */ 830 typedef struct { 831 uint32_t map, init, supported; 832 } ARMVQMap; 833 834 /** 835 * ARMCPU: 836 * @env: #CPUARMState 837 * 838 * An ARM CPU core. 839 */ 840 struct ArchCPU { 841 /*< private >*/ 842 CPUState parent_obj; 843 /*< public >*/ 844 845 CPUNegativeOffsetState neg; 846 CPUARMState env; 847 848 /* Coprocessor information */ 849 GHashTable *cp_regs; 850 /* For marshalling (mostly coprocessor) register state between the 851 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 852 * we use these arrays. 853 */ 854 /* List of register indexes managed via these arrays; (full KVM style 855 * 64 bit indexes, not CPRegInfo 32 bit indexes) 856 */ 857 uint64_t *cpreg_indexes; 858 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 859 uint64_t *cpreg_values; 860 /* Length of the indexes, values, reset_values arrays */ 861 int32_t cpreg_array_len; 862 /* These are used only for migration: incoming data arrives in 863 * these fields and is sanity checked in post_load before copying 864 * to the working data structures above. 865 */ 866 uint64_t *cpreg_vmstate_indexes; 867 uint64_t *cpreg_vmstate_values; 868 int32_t cpreg_vmstate_array_len; 869 870 DynamicGDBXMLInfo dyn_sysreg_xml; 871 DynamicGDBXMLInfo dyn_svereg_xml; 872 873 /* Timers used by the generic (architected) timer */ 874 QEMUTimer *gt_timer[NUM_GTIMERS]; 875 /* 876 * Timer used by the PMU. Its state is restored after migration by 877 * pmu_op_finish() - it does not need other handling during migration 878 */ 879 QEMUTimer *pmu_timer; 880 /* GPIO outputs for generic timer */ 881 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 882 /* GPIO output for GICv3 maintenance interrupt signal */ 883 qemu_irq gicv3_maintenance_interrupt; 884 /* GPIO output for the PMU interrupt */ 885 qemu_irq pmu_interrupt; 886 887 /* MemoryRegion to use for secure physical accesses */ 888 MemoryRegion *secure_memory; 889 890 /* MemoryRegion to use for allocation tag accesses */ 891 MemoryRegion *tag_memory; 892 MemoryRegion *secure_tag_memory; 893 894 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 895 Object *idau; 896 897 /* 'compatible' string for this CPU for Linux device trees */ 898 const char *dtb_compatible; 899 900 /* PSCI version for this CPU 901 * Bits[31:16] = Major Version 902 * Bits[15:0] = Minor Version 903 */ 904 uint32_t psci_version; 905 906 /* Current power state, access guarded by BQL */ 907 ARMPSCIState power_state; 908 909 /* CPU has virtualization extension */ 910 bool has_el2; 911 /* CPU has security extension */ 912 bool has_el3; 913 /* CPU has PMU (Performance Monitor Unit) */ 914 bool has_pmu; 915 /* CPU has VFP */ 916 bool has_vfp; 917 /* CPU has Neon */ 918 bool has_neon; 919 /* CPU has M-profile DSP extension */ 920 bool has_dsp; 921 922 /* CPU has memory protection unit */ 923 bool has_mpu; 924 /* PMSAv7 MPU number of supported regions */ 925 uint32_t pmsav7_dregion; 926 /* PMSAv8 MPU number of supported hyp regions */ 927 uint32_t pmsav8r_hdregion; 928 /* v8M SAU number of supported regions */ 929 uint32_t sau_sregion; 930 931 /* PSCI conduit used to invoke PSCI methods 932 * 0 - disabled, 1 - smc, 2 - hvc 933 */ 934 uint32_t psci_conduit; 935 936 /* For v8M, initial value of the Secure VTOR */ 937 uint32_t init_svtor; 938 /* For v8M, initial value of the Non-secure VTOR */ 939 uint32_t init_nsvtor; 940 941 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 942 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 943 */ 944 uint32_t kvm_target; 945 946 /* KVM init features for this CPU */ 947 uint32_t kvm_init_features[7]; 948 949 /* KVM CPU state */ 950 951 /* KVM virtual time adjustment */ 952 bool kvm_adjvtime; 953 bool kvm_vtime_dirty; 954 uint64_t kvm_vtime; 955 956 /* KVM steal time */ 957 OnOffAuto kvm_steal_time; 958 959 /* Uniprocessor system with MP extensions */ 960 bool mp_is_up; 961 962 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 963 * and the probe failed (so we need to report the error in realize) 964 */ 965 bool host_cpu_probe_failed; 966 967 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 968 * register. 969 */ 970 int32_t core_count; 971 972 /* The instance init functions for implementation-specific subclasses 973 * set these fields to specify the implementation-dependent values of 974 * various constant registers and reset values of non-constant 975 * registers. 976 * Some of these might become QOM properties eventually. 977 * Field names match the official register names as defined in the 978 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 979 * is used for reset values of non-constant registers; no reset_ 980 * prefix means a constant register. 981 * Some of these registers are split out into a substructure that 982 * is shared with the translators to control the ISA. 983 * 984 * Note that if you add an ID register to the ARMISARegisters struct 985 * you need to also update the 32-bit and 64-bit versions of the 986 * kvm_arm_get_host_cpu_features() function to correctly populate the 987 * field by reading the value from the KVM vCPU. 988 */ 989 struct ARMISARegisters { 990 uint32_t id_isar0; 991 uint32_t id_isar1; 992 uint32_t id_isar2; 993 uint32_t id_isar3; 994 uint32_t id_isar4; 995 uint32_t id_isar5; 996 uint32_t id_isar6; 997 uint32_t id_mmfr0; 998 uint32_t id_mmfr1; 999 uint32_t id_mmfr2; 1000 uint32_t id_mmfr3; 1001 uint32_t id_mmfr4; 1002 uint32_t id_mmfr5; 1003 uint32_t id_pfr0; 1004 uint32_t id_pfr1; 1005 uint32_t id_pfr2; 1006 uint32_t mvfr0; 1007 uint32_t mvfr1; 1008 uint32_t mvfr2; 1009 uint32_t id_dfr0; 1010 uint32_t id_dfr1; 1011 uint32_t dbgdidr; 1012 uint32_t dbgdevid; 1013 uint32_t dbgdevid1; 1014 uint64_t id_aa64isar0; 1015 uint64_t id_aa64isar1; 1016 uint64_t id_aa64pfr0; 1017 uint64_t id_aa64pfr1; 1018 uint64_t id_aa64mmfr0; 1019 uint64_t id_aa64mmfr1; 1020 uint64_t id_aa64mmfr2; 1021 uint64_t id_aa64dfr0; 1022 uint64_t id_aa64dfr1; 1023 uint64_t id_aa64zfr0; 1024 uint64_t id_aa64smfr0; 1025 uint64_t reset_pmcr_el0; 1026 } isar; 1027 uint64_t midr; 1028 uint32_t revidr; 1029 uint32_t reset_fpsid; 1030 uint64_t ctr; 1031 uint32_t reset_sctlr; 1032 uint64_t pmceid0; 1033 uint64_t pmceid1; 1034 uint32_t id_afr0; 1035 uint64_t id_aa64afr0; 1036 uint64_t id_aa64afr1; 1037 uint64_t clidr; 1038 uint64_t mp_affinity; /* MP ID without feature bits */ 1039 /* The elements of this array are the CCSIDR values for each cache, 1040 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1041 */ 1042 uint64_t ccsidr[16]; 1043 uint64_t reset_cbar; 1044 uint32_t reset_auxcr; 1045 bool reset_hivecs; 1046 1047 /* 1048 * Intermediate values used during property parsing. 1049 * Once finalized, the values should be read from ID_AA64*. 1050 */ 1051 bool prop_pauth; 1052 bool prop_pauth_impdef; 1053 bool prop_lpa2; 1054 1055 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1056 uint32_t dcz_blocksize; 1057 uint64_t rvbar_prop; /* Property/input signals. */ 1058 1059 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1060 int gic_num_lrs; /* number of list registers */ 1061 int gic_vpribits; /* number of virtual priority bits */ 1062 int gic_vprebits; /* number of virtual preemption bits */ 1063 int gic_pribits; /* number of physical priority bits */ 1064 1065 /* Whether the cfgend input is high (i.e. this CPU should reset into 1066 * big-endian mode). This setting isn't used directly: instead it modifies 1067 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1068 * architecture version. 1069 */ 1070 bool cfgend; 1071 1072 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1073 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1074 1075 int32_t node_id; /* NUMA node this CPU belongs to */ 1076 1077 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1078 uint8_t device_irq_level; 1079 1080 /* Used to set the maximum vector length the cpu will support. */ 1081 uint32_t sve_max_vq; 1082 1083 #ifdef CONFIG_USER_ONLY 1084 /* Used to set the default vector length at process start. */ 1085 uint32_t sve_default_vq; 1086 uint32_t sme_default_vq; 1087 #endif 1088 1089 ARMVQMap sve_vq; 1090 ARMVQMap sme_vq; 1091 1092 /* Generic timer counter frequency, in Hz */ 1093 uint64_t gt_cntfrq_hz; 1094 }; 1095 1096 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1097 1098 void arm_cpu_post_init(Object *obj); 1099 1100 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1101 1102 #ifndef CONFIG_USER_ONLY 1103 extern const VMStateDescription vmstate_arm_cpu; 1104 1105 void arm_cpu_do_interrupt(CPUState *cpu); 1106 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1107 1108 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1109 MemTxAttrs *attrs); 1110 #endif /* !CONFIG_USER_ONLY */ 1111 1112 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1113 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1114 1115 /* Returns the dynamically generated XML for the gdb stub. 1116 * Returns a pointer to the XML contents for the specified XML file or NULL 1117 * if the XML name doesn't match the predefined one. 1118 */ 1119 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1120 1121 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1122 int cpuid, DumpState *s); 1123 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1124 int cpuid, DumpState *s); 1125 1126 #ifdef TARGET_AARCH64 1127 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1128 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1129 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1130 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1131 int new_el, bool el0_a64); 1132 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1133 1134 /* 1135 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1136 * The byte at offset i from the start of the in-memory representation contains 1137 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1138 * lowest offsets are stored in the lowest memory addresses, then that nearly 1139 * matches QEMU's representation, which is to use an array of host-endian 1140 * uint64_t's, where the lower offsets are at the lower indices. To complete 1141 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1142 */ 1143 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1144 { 1145 #if HOST_BIG_ENDIAN 1146 int i; 1147 1148 for (i = 0; i < nr; ++i) { 1149 dst[i] = bswap64(src[i]); 1150 } 1151 1152 return dst; 1153 #else 1154 return src; 1155 #endif 1156 } 1157 1158 #else 1159 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1160 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1161 int n, bool a) 1162 { } 1163 #endif 1164 1165 void aarch64_sync_32_to_64(CPUARMState *env); 1166 void aarch64_sync_64_to_32(CPUARMState *env); 1167 1168 int fp_exception_el(CPUARMState *env, int cur_el); 1169 int sve_exception_el(CPUARMState *env, int cur_el); 1170 int sme_exception_el(CPUARMState *env, int cur_el); 1171 1172 /** 1173 * sve_vqm1_for_el_sm: 1174 * @env: CPUARMState 1175 * @el: exception level 1176 * @sm: streaming mode 1177 * 1178 * Compute the current vector length for @el & @sm, in units of 1179 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1180 * If @sm, compute for SVL, otherwise NVL. 1181 */ 1182 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1183 1184 /* Likewise, but using @sm = PSTATE.SM. */ 1185 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1186 1187 static inline bool is_a64(CPUARMState *env) 1188 { 1189 return env->aarch64; 1190 } 1191 1192 /** 1193 * pmu_op_start/finish 1194 * @env: CPUARMState 1195 * 1196 * Convert all PMU counters between their delta form (the typical mode when 1197 * they are enabled) and the guest-visible values. These two calls must 1198 * surround any action which might affect the counters. 1199 */ 1200 void pmu_op_start(CPUARMState *env); 1201 void pmu_op_finish(CPUARMState *env); 1202 1203 /* 1204 * Called when a PMU counter is due to overflow 1205 */ 1206 void arm_pmu_timer_cb(void *opaque); 1207 1208 /** 1209 * Functions to register as EL change hooks for PMU mode filtering 1210 */ 1211 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1212 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1213 1214 /* 1215 * pmu_init 1216 * @cpu: ARMCPU 1217 * 1218 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1219 * for the current configuration 1220 */ 1221 void pmu_init(ARMCPU *cpu); 1222 1223 /* SCTLR bit meanings. Several bits have been reused in newer 1224 * versions of the architecture; in that case we define constants 1225 * for both old and new bit meanings. Code which tests against those 1226 * bits should probably check or otherwise arrange that the CPU 1227 * is the architectural version it expects. 1228 */ 1229 #define SCTLR_M (1U << 0) 1230 #define SCTLR_A (1U << 1) 1231 #define SCTLR_C (1U << 2) 1232 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1233 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1234 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1235 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1236 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1237 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1238 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1239 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1240 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1241 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1242 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1243 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1244 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1245 #define SCTLR_SED (1U << 8) /* v8 onward */ 1246 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1247 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1248 #define SCTLR_F (1U << 10) /* up to v6 */ 1249 #define SCTLR_SW (1U << 10) /* v7 */ 1250 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1251 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1252 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1253 #define SCTLR_I (1U << 12) 1254 #define SCTLR_V (1U << 13) /* AArch32 only */ 1255 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1256 #define SCTLR_RR (1U << 14) /* up to v7 */ 1257 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1258 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1259 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1260 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1261 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1262 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1263 #define SCTLR_BR (1U << 17) /* PMSA only */ 1264 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1265 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1266 #define SCTLR_WXN (1U << 19) 1267 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1268 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1269 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1270 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1271 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1272 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1273 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1274 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1275 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1276 #define SCTLR_VE (1U << 24) /* up to v7 */ 1277 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1278 #define SCTLR_EE (1U << 25) 1279 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1280 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1281 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1282 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1283 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1284 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1285 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1286 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1287 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1288 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1289 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1290 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1291 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1292 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1293 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1294 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1295 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1296 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1297 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1298 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1299 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1300 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1301 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1302 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1303 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1304 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1305 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1306 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1307 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1308 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1309 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1310 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1311 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1312 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1313 1314 /* Bit definitions for CPACR (AArch32 only) */ 1315 FIELD(CPACR, CP10, 20, 2) 1316 FIELD(CPACR, CP11, 22, 2) 1317 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1318 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1319 FIELD(CPACR, ASEDIS, 31, 1) 1320 1321 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1322 FIELD(CPACR_EL1, ZEN, 16, 2) 1323 FIELD(CPACR_EL1, FPEN, 20, 2) 1324 FIELD(CPACR_EL1, SMEN, 24, 2) 1325 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1326 1327 /* Bit definitions for HCPTR (AArch32 only) */ 1328 FIELD(HCPTR, TCP10, 10, 1) 1329 FIELD(HCPTR, TCP11, 11, 1) 1330 FIELD(HCPTR, TASE, 15, 1) 1331 FIELD(HCPTR, TTA, 20, 1) 1332 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1333 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1334 1335 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1336 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1337 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1338 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1339 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1340 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1341 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1342 FIELD(CPTR_EL2, TTA, 28, 1) 1343 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1344 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1345 1346 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1347 FIELD(CPTR_EL3, EZ, 8, 1) 1348 FIELD(CPTR_EL3, TFP, 10, 1) 1349 FIELD(CPTR_EL3, ESM, 12, 1) 1350 FIELD(CPTR_EL3, TTA, 20, 1) 1351 FIELD(CPTR_EL3, TAM, 30, 1) 1352 FIELD(CPTR_EL3, TCPAC, 31, 1) 1353 1354 #define MDCR_MTPME (1U << 28) 1355 #define MDCR_TDCC (1U << 27) 1356 #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ 1357 #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ 1358 #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ 1359 #define MDCR_EPMAD (1U << 21) 1360 #define MDCR_EDAD (1U << 20) 1361 #define MDCR_TTRF (1U << 19) 1362 #define MDCR_STE (1U << 18) /* MDCR_EL3 */ 1363 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1364 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1365 #define MDCR_SDD (1U << 16) 1366 #define MDCR_SPD (3U << 14) 1367 #define MDCR_TDRA (1U << 11) 1368 #define MDCR_TDOSA (1U << 10) 1369 #define MDCR_TDA (1U << 9) 1370 #define MDCR_TDE (1U << 8) 1371 #define MDCR_HPME (1U << 7) 1372 #define MDCR_TPM (1U << 6) 1373 #define MDCR_TPMCR (1U << 5) 1374 #define MDCR_HPMN (0x1fU) 1375 1376 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1377 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ 1378 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ 1379 MDCR_STE | MDCR_SPME | MDCR_SPD) 1380 1381 #define CPSR_M (0x1fU) 1382 #define CPSR_T (1U << 5) 1383 #define CPSR_F (1U << 6) 1384 #define CPSR_I (1U << 7) 1385 #define CPSR_A (1U << 8) 1386 #define CPSR_E (1U << 9) 1387 #define CPSR_IT_2_7 (0xfc00U) 1388 #define CPSR_GE (0xfU << 16) 1389 #define CPSR_IL (1U << 20) 1390 #define CPSR_DIT (1U << 21) 1391 #define CPSR_PAN (1U << 22) 1392 #define CPSR_SSBS (1U << 23) 1393 #define CPSR_J (1U << 24) 1394 #define CPSR_IT_0_1 (3U << 25) 1395 #define CPSR_Q (1U << 27) 1396 #define CPSR_V (1U << 28) 1397 #define CPSR_C (1U << 29) 1398 #define CPSR_Z (1U << 30) 1399 #define CPSR_N (1U << 31) 1400 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1401 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1402 1403 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1404 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1405 | CPSR_NZCV) 1406 /* Bits writable in user mode. */ 1407 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1408 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1409 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1410 1411 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1412 #define XPSR_EXCP 0x1ffU 1413 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1414 #define XPSR_IT_2_7 CPSR_IT_2_7 1415 #define XPSR_GE CPSR_GE 1416 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1417 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1418 #define XPSR_IT_0_1 CPSR_IT_0_1 1419 #define XPSR_Q CPSR_Q 1420 #define XPSR_V CPSR_V 1421 #define XPSR_C CPSR_C 1422 #define XPSR_Z CPSR_Z 1423 #define XPSR_N CPSR_N 1424 #define XPSR_NZCV CPSR_NZCV 1425 #define XPSR_IT CPSR_IT 1426 1427 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1428 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1429 #define TTBCR_PD0 (1U << 4) 1430 #define TTBCR_PD1 (1U << 5) 1431 #define TTBCR_EPD0 (1U << 7) 1432 #define TTBCR_IRGN0 (3U << 8) 1433 #define TTBCR_ORGN0 (3U << 10) 1434 #define TTBCR_SH0 (3U << 12) 1435 #define TTBCR_T1SZ (3U << 16) 1436 #define TTBCR_A1 (1U << 22) 1437 #define TTBCR_EPD1 (1U << 23) 1438 #define TTBCR_IRGN1 (3U << 24) 1439 #define TTBCR_ORGN1 (3U << 26) 1440 #define TTBCR_SH1 (1U << 28) 1441 #define TTBCR_EAE (1U << 31) 1442 1443 FIELD(VTCR, T0SZ, 0, 6) 1444 FIELD(VTCR, SL0, 6, 2) 1445 FIELD(VTCR, IRGN0, 8, 2) 1446 FIELD(VTCR, ORGN0, 10, 2) 1447 FIELD(VTCR, SH0, 12, 2) 1448 FIELD(VTCR, TG0, 14, 2) 1449 FIELD(VTCR, PS, 16, 3) 1450 FIELD(VTCR, VS, 19, 1) 1451 FIELD(VTCR, HA, 21, 1) 1452 FIELD(VTCR, HD, 22, 1) 1453 FIELD(VTCR, HWU59, 25, 1) 1454 FIELD(VTCR, HWU60, 26, 1) 1455 FIELD(VTCR, HWU61, 27, 1) 1456 FIELD(VTCR, HWU62, 28, 1) 1457 FIELD(VTCR, NSW, 29, 1) 1458 FIELD(VTCR, NSA, 30, 1) 1459 FIELD(VTCR, DS, 32, 1) 1460 FIELD(VTCR, SL2, 33, 1) 1461 1462 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1463 * Only these are valid when in AArch64 mode; in 1464 * AArch32 mode SPSRs are basically CPSR-format. 1465 */ 1466 #define PSTATE_SP (1U) 1467 #define PSTATE_M (0xFU) 1468 #define PSTATE_nRW (1U << 4) 1469 #define PSTATE_F (1U << 6) 1470 #define PSTATE_I (1U << 7) 1471 #define PSTATE_A (1U << 8) 1472 #define PSTATE_D (1U << 9) 1473 #define PSTATE_BTYPE (3U << 10) 1474 #define PSTATE_SSBS (1U << 12) 1475 #define PSTATE_IL (1U << 20) 1476 #define PSTATE_SS (1U << 21) 1477 #define PSTATE_PAN (1U << 22) 1478 #define PSTATE_UAO (1U << 23) 1479 #define PSTATE_DIT (1U << 24) 1480 #define PSTATE_TCO (1U << 25) 1481 #define PSTATE_V (1U << 28) 1482 #define PSTATE_C (1U << 29) 1483 #define PSTATE_Z (1U << 30) 1484 #define PSTATE_N (1U << 31) 1485 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1486 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1487 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1488 /* Mode values for AArch64 */ 1489 #define PSTATE_MODE_EL3h 13 1490 #define PSTATE_MODE_EL3t 12 1491 #define PSTATE_MODE_EL2h 9 1492 #define PSTATE_MODE_EL2t 8 1493 #define PSTATE_MODE_EL1h 5 1494 #define PSTATE_MODE_EL1t 4 1495 #define PSTATE_MODE_EL0t 0 1496 1497 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1498 FIELD(SVCR, SM, 0, 1) 1499 FIELD(SVCR, ZA, 1, 1) 1500 1501 /* Fields for SMCR_ELx. */ 1502 FIELD(SMCR, LEN, 0, 4) 1503 FIELD(SMCR, FA64, 31, 1) 1504 1505 /* Write a new value to v7m.exception, thus transitioning into or out 1506 * of Handler mode; this may result in a change of active stack pointer. 1507 */ 1508 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1509 1510 /* Map EL and handler into a PSTATE_MODE. */ 1511 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1512 { 1513 return (el << 2) | handler; 1514 } 1515 1516 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1517 * interprocessing, so we don't attempt to sync with the cpsr state used by 1518 * the 32 bit decoder. 1519 */ 1520 static inline uint32_t pstate_read(CPUARMState *env) 1521 { 1522 int ZF; 1523 1524 ZF = (env->ZF == 0); 1525 return (env->NF & 0x80000000) | (ZF << 30) 1526 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1527 | env->pstate | env->daif | (env->btype << 10); 1528 } 1529 1530 static inline void pstate_write(CPUARMState *env, uint32_t val) 1531 { 1532 env->ZF = (~val) & PSTATE_Z; 1533 env->NF = val; 1534 env->CF = (val >> 29) & 1; 1535 env->VF = (val << 3) & 0x80000000; 1536 env->daif = val & PSTATE_DAIF; 1537 env->btype = (val >> 10) & 3; 1538 env->pstate = val & ~CACHED_PSTATE_BITS; 1539 } 1540 1541 /* Return the current CPSR value. */ 1542 uint32_t cpsr_read(CPUARMState *env); 1543 1544 typedef enum CPSRWriteType { 1545 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1546 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1547 CPSRWriteRaw = 2, 1548 /* trust values, no reg bank switch, no hflags rebuild */ 1549 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1550 } CPSRWriteType; 1551 1552 /* 1553 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1554 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1555 * correspond to TB flags bits cached in the hflags, unless @write_type 1556 * is CPSRWriteRaw. 1557 */ 1558 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1559 CPSRWriteType write_type); 1560 1561 /* Return the current xPSR value. */ 1562 static inline uint32_t xpsr_read(CPUARMState *env) 1563 { 1564 int ZF; 1565 ZF = (env->ZF == 0); 1566 return (env->NF & 0x80000000) | (ZF << 30) 1567 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1568 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1569 | ((env->condexec_bits & 0xfc) << 8) 1570 | (env->GE << 16) 1571 | env->v7m.exception; 1572 } 1573 1574 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1575 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1576 { 1577 if (mask & XPSR_NZCV) { 1578 env->ZF = (~val) & XPSR_Z; 1579 env->NF = val; 1580 env->CF = (val >> 29) & 1; 1581 env->VF = (val << 3) & 0x80000000; 1582 } 1583 if (mask & XPSR_Q) { 1584 env->QF = ((val & XPSR_Q) != 0); 1585 } 1586 if (mask & XPSR_GE) { 1587 env->GE = (val & XPSR_GE) >> 16; 1588 } 1589 #ifndef CONFIG_USER_ONLY 1590 if (mask & XPSR_T) { 1591 env->thumb = ((val & XPSR_T) != 0); 1592 } 1593 if (mask & XPSR_IT_0_1) { 1594 env->condexec_bits &= ~3; 1595 env->condexec_bits |= (val >> 25) & 3; 1596 } 1597 if (mask & XPSR_IT_2_7) { 1598 env->condexec_bits &= 3; 1599 env->condexec_bits |= (val >> 8) & 0xfc; 1600 } 1601 if (mask & XPSR_EXCP) { 1602 /* Note that this only happens on exception exit */ 1603 write_v7m_exception(env, val & XPSR_EXCP); 1604 } 1605 #endif 1606 } 1607 1608 #define HCR_VM (1ULL << 0) 1609 #define HCR_SWIO (1ULL << 1) 1610 #define HCR_PTW (1ULL << 2) 1611 #define HCR_FMO (1ULL << 3) 1612 #define HCR_IMO (1ULL << 4) 1613 #define HCR_AMO (1ULL << 5) 1614 #define HCR_VF (1ULL << 6) 1615 #define HCR_VI (1ULL << 7) 1616 #define HCR_VSE (1ULL << 8) 1617 #define HCR_FB (1ULL << 9) 1618 #define HCR_BSU_MASK (3ULL << 10) 1619 #define HCR_DC (1ULL << 12) 1620 #define HCR_TWI (1ULL << 13) 1621 #define HCR_TWE (1ULL << 14) 1622 #define HCR_TID0 (1ULL << 15) 1623 #define HCR_TID1 (1ULL << 16) 1624 #define HCR_TID2 (1ULL << 17) 1625 #define HCR_TID3 (1ULL << 18) 1626 #define HCR_TSC (1ULL << 19) 1627 #define HCR_TIDCP (1ULL << 20) 1628 #define HCR_TACR (1ULL << 21) 1629 #define HCR_TSW (1ULL << 22) 1630 #define HCR_TPCP (1ULL << 23) 1631 #define HCR_TPU (1ULL << 24) 1632 #define HCR_TTLB (1ULL << 25) 1633 #define HCR_TVM (1ULL << 26) 1634 #define HCR_TGE (1ULL << 27) 1635 #define HCR_TDZ (1ULL << 28) 1636 #define HCR_HCD (1ULL << 29) 1637 #define HCR_TRVM (1ULL << 30) 1638 #define HCR_RW (1ULL << 31) 1639 #define HCR_CD (1ULL << 32) 1640 #define HCR_ID (1ULL << 33) 1641 #define HCR_E2H (1ULL << 34) 1642 #define HCR_TLOR (1ULL << 35) 1643 #define HCR_TERR (1ULL << 36) 1644 #define HCR_TEA (1ULL << 37) 1645 #define HCR_MIOCNCE (1ULL << 38) 1646 /* RES0 bit 39 */ 1647 #define HCR_APK (1ULL << 40) 1648 #define HCR_API (1ULL << 41) 1649 #define HCR_NV (1ULL << 42) 1650 #define HCR_NV1 (1ULL << 43) 1651 #define HCR_AT (1ULL << 44) 1652 #define HCR_NV2 (1ULL << 45) 1653 #define HCR_FWB (1ULL << 46) 1654 #define HCR_FIEN (1ULL << 47) 1655 /* RES0 bit 48 */ 1656 #define HCR_TID4 (1ULL << 49) 1657 #define HCR_TICAB (1ULL << 50) 1658 #define HCR_AMVOFFEN (1ULL << 51) 1659 #define HCR_TOCU (1ULL << 52) 1660 #define HCR_ENSCXT (1ULL << 53) 1661 #define HCR_TTLBIS (1ULL << 54) 1662 #define HCR_TTLBOS (1ULL << 55) 1663 #define HCR_ATA (1ULL << 56) 1664 #define HCR_DCT (1ULL << 57) 1665 #define HCR_TID5 (1ULL << 58) 1666 #define HCR_TWEDEN (1ULL << 59) 1667 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1668 1669 #define HCRX_ENAS0 (1ULL << 0) 1670 #define HCRX_ENALS (1ULL << 1) 1671 #define HCRX_ENASR (1ULL << 2) 1672 #define HCRX_FNXS (1ULL << 3) 1673 #define HCRX_FGTNXS (1ULL << 4) 1674 #define HCRX_SMPME (1ULL << 5) 1675 #define HCRX_TALLINT (1ULL << 6) 1676 #define HCRX_VINMI (1ULL << 7) 1677 #define HCRX_VFNMI (1ULL << 8) 1678 #define HCRX_CMOW (1ULL << 9) 1679 #define HCRX_MCE2 (1ULL << 10) 1680 #define HCRX_MSCEN (1ULL << 11) 1681 1682 #define HPFAR_NS (1ULL << 63) 1683 1684 #define SCR_NS (1ULL << 0) 1685 #define SCR_IRQ (1ULL << 1) 1686 #define SCR_FIQ (1ULL << 2) 1687 #define SCR_EA (1ULL << 3) 1688 #define SCR_FW (1ULL << 4) 1689 #define SCR_AW (1ULL << 5) 1690 #define SCR_NET (1ULL << 6) 1691 #define SCR_SMD (1ULL << 7) 1692 #define SCR_HCE (1ULL << 8) 1693 #define SCR_SIF (1ULL << 9) 1694 #define SCR_RW (1ULL << 10) 1695 #define SCR_ST (1ULL << 11) 1696 #define SCR_TWI (1ULL << 12) 1697 #define SCR_TWE (1ULL << 13) 1698 #define SCR_TLOR (1ULL << 14) 1699 #define SCR_TERR (1ULL << 15) 1700 #define SCR_APK (1ULL << 16) 1701 #define SCR_API (1ULL << 17) 1702 #define SCR_EEL2 (1ULL << 18) 1703 #define SCR_EASE (1ULL << 19) 1704 #define SCR_NMEA (1ULL << 20) 1705 #define SCR_FIEN (1ULL << 21) 1706 #define SCR_ENSCXT (1ULL << 25) 1707 #define SCR_ATA (1ULL << 26) 1708 #define SCR_FGTEN (1ULL << 27) 1709 #define SCR_ECVEN (1ULL << 28) 1710 #define SCR_TWEDEN (1ULL << 29) 1711 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1712 #define SCR_TME (1ULL << 34) 1713 #define SCR_AMVOFFEN (1ULL << 35) 1714 #define SCR_ENAS0 (1ULL << 36) 1715 #define SCR_ADEN (1ULL << 37) 1716 #define SCR_HXEN (1ULL << 38) 1717 #define SCR_TRNDR (1ULL << 40) 1718 #define SCR_ENTP2 (1ULL << 41) 1719 #define SCR_GPF (1ULL << 48) 1720 1721 #define HSTR_TTEE (1 << 16) 1722 #define HSTR_TJDBX (1 << 17) 1723 1724 /* Return the current FPSCR value. */ 1725 uint32_t vfp_get_fpscr(CPUARMState *env); 1726 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1727 1728 /* FPCR, Floating Point Control Register 1729 * FPSR, Floating Poiht Status Register 1730 * 1731 * For A64 the FPSCR is split into two logically distinct registers, 1732 * FPCR and FPSR. However since they still use non-overlapping bits 1733 * we store the underlying state in fpscr and just mask on read/write. 1734 */ 1735 #define FPSR_MASK 0xf800009f 1736 #define FPCR_MASK 0x07ff9f00 1737 1738 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1739 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1740 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1741 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1742 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1743 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1744 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1745 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1746 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1747 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1748 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1749 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1750 #define FPCR_V (1 << 28) /* FP overflow flag */ 1751 #define FPCR_C (1 << 29) /* FP carry flag */ 1752 #define FPCR_Z (1 << 30) /* FP zero flag */ 1753 #define FPCR_N (1 << 31) /* FP negative flag */ 1754 1755 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1756 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1757 #define FPCR_LTPSIZE_LENGTH 3 1758 1759 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1760 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1761 1762 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1763 { 1764 return vfp_get_fpscr(env) & FPSR_MASK; 1765 } 1766 1767 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1768 { 1769 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1770 vfp_set_fpscr(env, new_fpscr); 1771 } 1772 1773 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1774 { 1775 return vfp_get_fpscr(env) & FPCR_MASK; 1776 } 1777 1778 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1779 { 1780 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1781 vfp_set_fpscr(env, new_fpscr); 1782 } 1783 1784 enum arm_cpu_mode { 1785 ARM_CPU_MODE_USR = 0x10, 1786 ARM_CPU_MODE_FIQ = 0x11, 1787 ARM_CPU_MODE_IRQ = 0x12, 1788 ARM_CPU_MODE_SVC = 0x13, 1789 ARM_CPU_MODE_MON = 0x16, 1790 ARM_CPU_MODE_ABT = 0x17, 1791 ARM_CPU_MODE_HYP = 0x1a, 1792 ARM_CPU_MODE_UND = 0x1b, 1793 ARM_CPU_MODE_SYS = 0x1f 1794 }; 1795 1796 /* VFP system registers. */ 1797 #define ARM_VFP_FPSID 0 1798 #define ARM_VFP_FPSCR 1 1799 #define ARM_VFP_MVFR2 5 1800 #define ARM_VFP_MVFR1 6 1801 #define ARM_VFP_MVFR0 7 1802 #define ARM_VFP_FPEXC 8 1803 #define ARM_VFP_FPINST 9 1804 #define ARM_VFP_FPINST2 10 1805 /* These ones are M-profile only */ 1806 #define ARM_VFP_FPSCR_NZCVQC 2 1807 #define ARM_VFP_VPR 12 1808 #define ARM_VFP_P0 13 1809 #define ARM_VFP_FPCXT_NS 14 1810 #define ARM_VFP_FPCXT_S 15 1811 1812 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1813 #define QEMU_VFP_FPSCR_NZCV 0xffff 1814 1815 /* iwMMXt coprocessor control registers. */ 1816 #define ARM_IWMMXT_wCID 0 1817 #define ARM_IWMMXT_wCon 1 1818 #define ARM_IWMMXT_wCSSF 2 1819 #define ARM_IWMMXT_wCASF 3 1820 #define ARM_IWMMXT_wCGR0 8 1821 #define ARM_IWMMXT_wCGR1 9 1822 #define ARM_IWMMXT_wCGR2 10 1823 #define ARM_IWMMXT_wCGR3 11 1824 1825 /* V7M CCR bits */ 1826 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1827 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1828 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1829 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1830 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1831 FIELD(V7M_CCR, STKALIGN, 9, 1) 1832 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1833 FIELD(V7M_CCR, DC, 16, 1) 1834 FIELD(V7M_CCR, IC, 17, 1) 1835 FIELD(V7M_CCR, BP, 18, 1) 1836 FIELD(V7M_CCR, LOB, 19, 1) 1837 FIELD(V7M_CCR, TRD, 20, 1) 1838 1839 /* V7M SCR bits */ 1840 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1841 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1842 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1843 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1844 1845 /* V7M AIRCR bits */ 1846 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1847 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1848 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1849 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1850 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1851 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1852 FIELD(V7M_AIRCR, PRIS, 14, 1) 1853 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1854 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1855 1856 /* V7M CFSR bits for MMFSR */ 1857 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1858 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1859 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1860 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1861 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1862 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1863 1864 /* V7M CFSR bits for BFSR */ 1865 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1866 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1867 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1868 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1869 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1870 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1871 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1872 1873 /* V7M CFSR bits for UFSR */ 1874 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1875 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1876 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1877 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1878 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1879 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1880 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1881 1882 /* V7M CFSR bit masks covering all of the subregister bits */ 1883 FIELD(V7M_CFSR, MMFSR, 0, 8) 1884 FIELD(V7M_CFSR, BFSR, 8, 8) 1885 FIELD(V7M_CFSR, UFSR, 16, 16) 1886 1887 /* V7M HFSR bits */ 1888 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1889 FIELD(V7M_HFSR, FORCED, 30, 1) 1890 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1891 1892 /* V7M DFSR bits */ 1893 FIELD(V7M_DFSR, HALTED, 0, 1) 1894 FIELD(V7M_DFSR, BKPT, 1, 1) 1895 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1896 FIELD(V7M_DFSR, VCATCH, 3, 1) 1897 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1898 1899 /* V7M SFSR bits */ 1900 FIELD(V7M_SFSR, INVEP, 0, 1) 1901 FIELD(V7M_SFSR, INVIS, 1, 1) 1902 FIELD(V7M_SFSR, INVER, 2, 1) 1903 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1904 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1905 FIELD(V7M_SFSR, LSPERR, 5, 1) 1906 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1907 FIELD(V7M_SFSR, LSERR, 7, 1) 1908 1909 /* v7M MPU_CTRL bits */ 1910 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1911 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1912 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1913 1914 /* v7M CLIDR bits */ 1915 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1916 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1917 FIELD(V7M_CLIDR, LOC, 24, 3) 1918 FIELD(V7M_CLIDR, LOUU, 27, 3) 1919 FIELD(V7M_CLIDR, ICB, 30, 2) 1920 1921 FIELD(V7M_CSSELR, IND, 0, 1) 1922 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1923 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1924 * define a mask for this and check that it doesn't permit running off 1925 * the end of the array. 1926 */ 1927 FIELD(V7M_CSSELR, INDEX, 0, 4) 1928 1929 /* v7M FPCCR bits */ 1930 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1931 FIELD(V7M_FPCCR, USER, 1, 1) 1932 FIELD(V7M_FPCCR, S, 2, 1) 1933 FIELD(V7M_FPCCR, THREAD, 3, 1) 1934 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1935 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1936 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1937 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1938 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1939 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1940 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1941 FIELD(V7M_FPCCR, RES0, 11, 15) 1942 FIELD(V7M_FPCCR, TS, 26, 1) 1943 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1944 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1945 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1946 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1947 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1948 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1949 #define R_V7M_FPCCR_BANKED_MASK \ 1950 (R_V7M_FPCCR_LSPACT_MASK | \ 1951 R_V7M_FPCCR_USER_MASK | \ 1952 R_V7M_FPCCR_THREAD_MASK | \ 1953 R_V7M_FPCCR_MMRDY_MASK | \ 1954 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1955 R_V7M_FPCCR_UFRDY_MASK | \ 1956 R_V7M_FPCCR_ASPEN_MASK) 1957 1958 /* v7M VPR bits */ 1959 FIELD(V7M_VPR, P0, 0, 16) 1960 FIELD(V7M_VPR, MASK01, 16, 4) 1961 FIELD(V7M_VPR, MASK23, 20, 4) 1962 1963 /* 1964 * System register ID fields. 1965 */ 1966 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1967 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1968 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1969 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1970 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1971 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1972 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1973 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1974 FIELD(CLIDR_EL1, LOC, 24, 3) 1975 FIELD(CLIDR_EL1, LOUU, 27, 3) 1976 FIELD(CLIDR_EL1, ICB, 30, 3) 1977 1978 /* When FEAT_CCIDX is implemented */ 1979 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1980 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1981 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1982 1983 /* When FEAT_CCIDX is not implemented */ 1984 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1985 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1986 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1987 1988 FIELD(CTR_EL0, IMINLINE, 0, 4) 1989 FIELD(CTR_EL0, L1IP, 14, 2) 1990 FIELD(CTR_EL0, DMINLINE, 16, 4) 1991 FIELD(CTR_EL0, ERG, 20, 4) 1992 FIELD(CTR_EL0, CWG, 24, 4) 1993 FIELD(CTR_EL0, IDC, 28, 1) 1994 FIELD(CTR_EL0, DIC, 29, 1) 1995 FIELD(CTR_EL0, TMINLINE, 32, 6) 1996 1997 FIELD(MIDR_EL1, REVISION, 0, 4) 1998 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1999 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2000 FIELD(MIDR_EL1, VARIANT, 20, 4) 2001 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2002 2003 FIELD(ID_ISAR0, SWAP, 0, 4) 2004 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2005 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2006 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2007 FIELD(ID_ISAR0, COPROC, 16, 4) 2008 FIELD(ID_ISAR0, DEBUG, 20, 4) 2009 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2010 2011 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2012 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2013 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2014 FIELD(ID_ISAR1, EXTEND, 12, 4) 2015 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2016 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2017 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2018 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2019 2020 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2021 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2022 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2023 FIELD(ID_ISAR2, MULT, 12, 4) 2024 FIELD(ID_ISAR2, MULTS, 16, 4) 2025 FIELD(ID_ISAR2, MULTU, 20, 4) 2026 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2027 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2028 2029 FIELD(ID_ISAR3, SATURATE, 0, 4) 2030 FIELD(ID_ISAR3, SIMD, 4, 4) 2031 FIELD(ID_ISAR3, SVC, 8, 4) 2032 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2033 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2034 FIELD(ID_ISAR3, T32COPY, 20, 4) 2035 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2036 FIELD(ID_ISAR3, T32EE, 28, 4) 2037 2038 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2039 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2040 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2041 FIELD(ID_ISAR4, SMC, 12, 4) 2042 FIELD(ID_ISAR4, BARRIER, 16, 4) 2043 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2044 FIELD(ID_ISAR4, PSR_M, 24, 4) 2045 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2046 2047 FIELD(ID_ISAR5, SEVL, 0, 4) 2048 FIELD(ID_ISAR5, AES, 4, 4) 2049 FIELD(ID_ISAR5, SHA1, 8, 4) 2050 FIELD(ID_ISAR5, SHA2, 12, 4) 2051 FIELD(ID_ISAR5, CRC32, 16, 4) 2052 FIELD(ID_ISAR5, RDM, 24, 4) 2053 FIELD(ID_ISAR5, VCMA, 28, 4) 2054 2055 FIELD(ID_ISAR6, JSCVT, 0, 4) 2056 FIELD(ID_ISAR6, DP, 4, 4) 2057 FIELD(ID_ISAR6, FHM, 8, 4) 2058 FIELD(ID_ISAR6, SB, 12, 4) 2059 FIELD(ID_ISAR6, SPECRES, 16, 4) 2060 FIELD(ID_ISAR6, BF16, 20, 4) 2061 FIELD(ID_ISAR6, I8MM, 24, 4) 2062 2063 FIELD(ID_MMFR0, VMSA, 0, 4) 2064 FIELD(ID_MMFR0, PMSA, 4, 4) 2065 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2066 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2067 FIELD(ID_MMFR0, TCM, 16, 4) 2068 FIELD(ID_MMFR0, AUXREG, 20, 4) 2069 FIELD(ID_MMFR0, FCSE, 24, 4) 2070 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2071 2072 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2073 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2074 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2075 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2076 FIELD(ID_MMFR1, L1HVD, 16, 4) 2077 FIELD(ID_MMFR1, L1UNI, 20, 4) 2078 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2079 FIELD(ID_MMFR1, BPRED, 28, 4) 2080 2081 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2082 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2083 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2084 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2085 FIELD(ID_MMFR2, UNITLB, 16, 4) 2086 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2087 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2088 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2089 2090 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2091 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2092 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2093 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2094 FIELD(ID_MMFR3, PAN, 16, 4) 2095 FIELD(ID_MMFR3, COHWALK, 20, 4) 2096 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2097 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2098 2099 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2100 FIELD(ID_MMFR4, AC2, 4, 4) 2101 FIELD(ID_MMFR4, XNX, 8, 4) 2102 FIELD(ID_MMFR4, CNP, 12, 4) 2103 FIELD(ID_MMFR4, HPDS, 16, 4) 2104 FIELD(ID_MMFR4, LSM, 20, 4) 2105 FIELD(ID_MMFR4, CCIDX, 24, 4) 2106 FIELD(ID_MMFR4, EVT, 28, 4) 2107 2108 FIELD(ID_MMFR5, ETS, 0, 4) 2109 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2110 2111 FIELD(ID_PFR0, STATE0, 0, 4) 2112 FIELD(ID_PFR0, STATE1, 4, 4) 2113 FIELD(ID_PFR0, STATE2, 8, 4) 2114 FIELD(ID_PFR0, STATE3, 12, 4) 2115 FIELD(ID_PFR0, CSV2, 16, 4) 2116 FIELD(ID_PFR0, AMU, 20, 4) 2117 FIELD(ID_PFR0, DIT, 24, 4) 2118 FIELD(ID_PFR0, RAS, 28, 4) 2119 2120 FIELD(ID_PFR1, PROGMOD, 0, 4) 2121 FIELD(ID_PFR1, SECURITY, 4, 4) 2122 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2123 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2124 FIELD(ID_PFR1, GENTIMER, 16, 4) 2125 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2126 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2127 FIELD(ID_PFR1, GIC, 28, 4) 2128 2129 FIELD(ID_PFR2, CSV3, 0, 4) 2130 FIELD(ID_PFR2, SSBS, 4, 4) 2131 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2132 2133 FIELD(ID_AA64ISAR0, AES, 4, 4) 2134 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2135 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2136 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2137 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2138 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2139 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2140 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2141 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2142 FIELD(ID_AA64ISAR0, DP, 44, 4) 2143 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2144 FIELD(ID_AA64ISAR0, TS, 52, 4) 2145 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2146 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2147 2148 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2149 FIELD(ID_AA64ISAR1, APA, 4, 4) 2150 FIELD(ID_AA64ISAR1, API, 8, 4) 2151 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2152 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2153 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2154 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2155 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2156 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2157 FIELD(ID_AA64ISAR1, SB, 36, 4) 2158 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2159 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2160 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2161 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2162 FIELD(ID_AA64ISAR1, XS, 56, 4) 2163 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2164 2165 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2166 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2167 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2168 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2169 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2170 FIELD(ID_AA64ISAR2, BC, 20, 4) 2171 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2172 2173 FIELD(ID_AA64PFR0, EL0, 0, 4) 2174 FIELD(ID_AA64PFR0, EL1, 4, 4) 2175 FIELD(ID_AA64PFR0, EL2, 8, 4) 2176 FIELD(ID_AA64PFR0, EL3, 12, 4) 2177 FIELD(ID_AA64PFR0, FP, 16, 4) 2178 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2179 FIELD(ID_AA64PFR0, GIC, 24, 4) 2180 FIELD(ID_AA64PFR0, RAS, 28, 4) 2181 FIELD(ID_AA64PFR0, SVE, 32, 4) 2182 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2183 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2184 FIELD(ID_AA64PFR0, AMU, 44, 4) 2185 FIELD(ID_AA64PFR0, DIT, 48, 4) 2186 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2187 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2188 2189 FIELD(ID_AA64PFR1, BT, 0, 4) 2190 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2191 FIELD(ID_AA64PFR1, MTE, 8, 4) 2192 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2193 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2194 FIELD(ID_AA64PFR1, SME, 24, 4) 2195 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2196 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2197 FIELD(ID_AA64PFR1, NMI, 36, 4) 2198 2199 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2200 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2201 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2202 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2203 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2204 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2205 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2206 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2207 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2208 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2209 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2210 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2211 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2212 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2213 2214 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2215 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2216 FIELD(ID_AA64MMFR1, VH, 8, 4) 2217 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2218 FIELD(ID_AA64MMFR1, LO, 16, 4) 2219 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2220 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2221 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2222 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2223 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2224 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2225 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2226 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2227 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2228 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2229 2230 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2231 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2232 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2233 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2234 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2235 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2236 FIELD(ID_AA64MMFR2, NV, 24, 4) 2237 FIELD(ID_AA64MMFR2, ST, 28, 4) 2238 FIELD(ID_AA64MMFR2, AT, 32, 4) 2239 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2240 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2241 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2242 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2243 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2244 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2245 2246 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2247 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2248 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2249 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2250 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2251 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2252 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2253 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2254 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2255 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2256 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2257 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2258 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2259 2260 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2261 FIELD(ID_AA64ZFR0, AES, 4, 4) 2262 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2263 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2264 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2265 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2266 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2267 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2268 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2269 2270 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2271 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2272 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2273 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2274 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2275 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2276 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2277 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2278 2279 FIELD(ID_DFR0, COPDBG, 0, 4) 2280 FIELD(ID_DFR0, COPSDBG, 4, 4) 2281 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2282 FIELD(ID_DFR0, COPTRC, 12, 4) 2283 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2284 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2285 FIELD(ID_DFR0, PERFMON, 24, 4) 2286 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2287 2288 FIELD(ID_DFR1, MTPMU, 0, 4) 2289 FIELD(ID_DFR1, HPMN0, 4, 4) 2290 2291 FIELD(DBGDIDR, SE_IMP, 12, 1) 2292 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2293 FIELD(DBGDIDR, VERSION, 16, 4) 2294 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2295 FIELD(DBGDIDR, BRPS, 24, 4) 2296 FIELD(DBGDIDR, WRPS, 28, 4) 2297 2298 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2299 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2300 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2301 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2302 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2303 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2304 FIELD(DBGDEVID, AUXREGS, 24, 4) 2305 FIELD(DBGDEVID, CIDMASK, 28, 4) 2306 2307 FIELD(MVFR0, SIMDREG, 0, 4) 2308 FIELD(MVFR0, FPSP, 4, 4) 2309 FIELD(MVFR0, FPDP, 8, 4) 2310 FIELD(MVFR0, FPTRAP, 12, 4) 2311 FIELD(MVFR0, FPDIVIDE, 16, 4) 2312 FIELD(MVFR0, FPSQRT, 20, 4) 2313 FIELD(MVFR0, FPSHVEC, 24, 4) 2314 FIELD(MVFR0, FPROUND, 28, 4) 2315 2316 FIELD(MVFR1, FPFTZ, 0, 4) 2317 FIELD(MVFR1, FPDNAN, 4, 4) 2318 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2319 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2320 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2321 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2322 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2323 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2324 FIELD(MVFR1, FPHP, 24, 4) 2325 FIELD(MVFR1, SIMDFMAC, 28, 4) 2326 2327 FIELD(MVFR2, SIMDMISC, 0, 4) 2328 FIELD(MVFR2, FPMISC, 4, 4) 2329 2330 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2331 2332 /* If adding a feature bit which corresponds to a Linux ELF 2333 * HWCAP bit, remember to update the feature-bit-to-hwcap 2334 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2335 */ 2336 enum arm_features { 2337 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2338 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2339 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2340 ARM_FEATURE_V6, 2341 ARM_FEATURE_V6K, 2342 ARM_FEATURE_V7, 2343 ARM_FEATURE_THUMB2, 2344 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2345 ARM_FEATURE_NEON, 2346 ARM_FEATURE_M, /* Microcontroller profile. */ 2347 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2348 ARM_FEATURE_THUMB2EE, 2349 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2350 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2351 ARM_FEATURE_V4T, 2352 ARM_FEATURE_V5, 2353 ARM_FEATURE_STRONGARM, 2354 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2355 ARM_FEATURE_GENERIC_TIMER, 2356 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2357 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2358 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2359 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2360 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2361 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2362 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2363 ARM_FEATURE_V8, 2364 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2365 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2366 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2367 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2368 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2369 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2370 ARM_FEATURE_PMU, /* has PMU support */ 2371 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2372 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2373 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2374 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2375 }; 2376 2377 static inline int arm_feature(CPUARMState *env, int feature) 2378 { 2379 return (env->features & (1ULL << feature)) != 0; 2380 } 2381 2382 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2383 2384 #if !defined(CONFIG_USER_ONLY) 2385 /* Return true if exception levels below EL3 are in secure state, 2386 * or would be following an exception return to that level. 2387 * Unlike arm_is_secure() (which is always a question about the 2388 * _current_ state of the CPU) this doesn't care about the current 2389 * EL or mode. 2390 */ 2391 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2392 { 2393 if (arm_feature(env, ARM_FEATURE_EL3)) { 2394 return !(env->cp15.scr_el3 & SCR_NS); 2395 } else { 2396 /* If EL3 is not supported then the secure state is implementation 2397 * defined, in which case QEMU defaults to non-secure. 2398 */ 2399 return false; 2400 } 2401 } 2402 2403 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2404 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2405 { 2406 if (arm_feature(env, ARM_FEATURE_EL3)) { 2407 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2408 /* CPU currently in AArch64 state and EL3 */ 2409 return true; 2410 } else if (!is_a64(env) && 2411 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2412 /* CPU currently in AArch32 state and monitor mode */ 2413 return true; 2414 } 2415 } 2416 return false; 2417 } 2418 2419 /* Return true if the processor is in secure state */ 2420 static inline bool arm_is_secure(CPUARMState *env) 2421 { 2422 if (arm_is_el3_or_mon(env)) { 2423 return true; 2424 } 2425 return arm_is_secure_below_el3(env); 2426 } 2427 2428 /* 2429 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2430 * This corresponds to the pseudocode EL2Enabled() 2431 */ 2432 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2433 { 2434 return arm_feature(env, ARM_FEATURE_EL2) 2435 && (!secure || (env->cp15.scr_el3 & SCR_EEL2)); 2436 } 2437 2438 static inline bool arm_is_el2_enabled(CPUARMState *env) 2439 { 2440 return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env)); 2441 } 2442 2443 #else 2444 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2445 { 2446 return false; 2447 } 2448 2449 static inline bool arm_is_secure(CPUARMState *env) 2450 { 2451 return false; 2452 } 2453 2454 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2455 { 2456 return false; 2457 } 2458 2459 static inline bool arm_is_el2_enabled(CPUARMState *env) 2460 { 2461 return false; 2462 } 2463 #endif 2464 2465 /** 2466 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2467 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2468 * "for all purposes other than a direct read or write access of HCR_EL2." 2469 * Not included here is HCR_RW. 2470 */ 2471 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); 2472 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2473 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2474 2475 /* Return true if the specified exception level is running in AArch64 state. */ 2476 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2477 { 2478 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2479 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2480 */ 2481 assert(el >= 1 && el <= 3); 2482 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2483 2484 /* The highest exception level is always at the maximum supported 2485 * register width, and then lower levels have a register width controlled 2486 * by bits in the SCR or HCR registers. 2487 */ 2488 if (el == 3) { 2489 return aa64; 2490 } 2491 2492 if (arm_feature(env, ARM_FEATURE_EL3) && 2493 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2494 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2495 } 2496 2497 if (el == 2) { 2498 return aa64; 2499 } 2500 2501 if (arm_is_el2_enabled(env)) { 2502 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2503 } 2504 2505 return aa64; 2506 } 2507 2508 /* Function for determing whether guest cp register reads and writes should 2509 * access the secure or non-secure bank of a cp register. When EL3 is 2510 * operating in AArch32 state, the NS-bit determines whether the secure 2511 * instance of a cp register should be used. When EL3 is AArch64 (or if 2512 * it doesn't exist at all) then there is no register banking, and all 2513 * accesses are to the non-secure version. 2514 */ 2515 static inline bool access_secure_reg(CPUARMState *env) 2516 { 2517 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2518 !arm_el_is_aa64(env, 3) && 2519 !(env->cp15.scr_el3 & SCR_NS)); 2520 2521 return ret; 2522 } 2523 2524 /* Macros for accessing a specified CP register bank */ 2525 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2526 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2527 2528 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2529 do { \ 2530 if (_secure) { \ 2531 (_env)->cp15._regname##_s = (_val); \ 2532 } else { \ 2533 (_env)->cp15._regname##_ns = (_val); \ 2534 } \ 2535 } while (0) 2536 2537 /* Macros for automatically accessing a specific CP register bank depending on 2538 * the current secure state of the system. These macros are not intended for 2539 * supporting instruction translation reads/writes as these are dependent 2540 * solely on the SCR.NS bit and not the mode. 2541 */ 2542 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2543 A32_BANKED_REG_GET((_env), _regname, \ 2544 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2545 2546 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2547 A32_BANKED_REG_SET((_env), _regname, \ 2548 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2549 (_val)) 2550 2551 void arm_cpu_list(void); 2552 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2553 uint32_t cur_el, bool secure); 2554 2555 /* Return the highest implemented Exception Level */ 2556 static inline int arm_highest_el(CPUARMState *env) 2557 { 2558 if (arm_feature(env, ARM_FEATURE_EL3)) { 2559 return 3; 2560 } 2561 if (arm_feature(env, ARM_FEATURE_EL2)) { 2562 return 2; 2563 } 2564 return 1; 2565 } 2566 2567 /* Return true if a v7M CPU is in Handler mode */ 2568 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2569 { 2570 return env->v7m.exception != 0; 2571 } 2572 2573 /* Return the current Exception Level (as per ARMv8; note that this differs 2574 * from the ARMv7 Privilege Level). 2575 */ 2576 static inline int arm_current_el(CPUARMState *env) 2577 { 2578 if (arm_feature(env, ARM_FEATURE_M)) { 2579 return arm_v7m_is_handler_mode(env) || 2580 !(env->v7m.control[env->v7m.secure] & 1); 2581 } 2582 2583 if (is_a64(env)) { 2584 return extract32(env->pstate, 2, 2); 2585 } 2586 2587 switch (env->uncached_cpsr & 0x1f) { 2588 case ARM_CPU_MODE_USR: 2589 return 0; 2590 case ARM_CPU_MODE_HYP: 2591 return 2; 2592 case ARM_CPU_MODE_MON: 2593 return 3; 2594 default: 2595 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2596 /* If EL3 is 32-bit then all secure privileged modes run in 2597 * EL3 2598 */ 2599 return 3; 2600 } 2601 2602 return 1; 2603 } 2604 } 2605 2606 /** 2607 * write_list_to_cpustate 2608 * @cpu: ARMCPU 2609 * 2610 * For each register listed in the ARMCPU cpreg_indexes list, write 2611 * its value from the cpreg_values list into the ARMCPUState structure. 2612 * This updates TCG's working data structures from KVM data or 2613 * from incoming migration state. 2614 * 2615 * Returns: true if all register values were updated correctly, 2616 * false if some register was unknown or could not be written. 2617 * Note that we do not stop early on failure -- we will attempt 2618 * writing all registers in the list. 2619 */ 2620 bool write_list_to_cpustate(ARMCPU *cpu); 2621 2622 /** 2623 * write_cpustate_to_list: 2624 * @cpu: ARMCPU 2625 * @kvm_sync: true if this is for syncing back to KVM 2626 * 2627 * For each register listed in the ARMCPU cpreg_indexes list, write 2628 * its value from the ARMCPUState structure into the cpreg_values list. 2629 * This is used to copy info from TCG's working data structures into 2630 * KVM or for outbound migration. 2631 * 2632 * @kvm_sync is true if we are doing this in order to sync the 2633 * register state back to KVM. In this case we will only update 2634 * values in the list if the previous list->cpustate sync actually 2635 * successfully wrote the CPU state. Otherwise we will keep the value 2636 * that is in the list. 2637 * 2638 * Returns: true if all register values were read correctly, 2639 * false if some register was unknown or could not be read. 2640 * Note that we do not stop early on failure -- we will attempt 2641 * reading all registers in the list. 2642 */ 2643 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2644 2645 #define ARM_CPUID_TI915T 0x54029152 2646 #define ARM_CPUID_TI925T 0x54029252 2647 2648 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2649 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2650 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2651 2652 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2653 2654 #define cpu_list arm_cpu_list 2655 2656 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2657 * 2658 * If EL3 is 64-bit: 2659 * + NonSecure EL1 & 0 stage 1 2660 * + NonSecure EL1 & 0 stage 2 2661 * + NonSecure EL2 2662 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2663 * + Secure EL1 & 0 2664 * + Secure EL3 2665 * If EL3 is 32-bit: 2666 * + NonSecure PL1 & 0 stage 1 2667 * + NonSecure PL1 & 0 stage 2 2668 * + NonSecure PL2 2669 * + Secure PL0 2670 * + Secure PL1 2671 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2672 * 2673 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2674 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2675 * because they may differ in access permissions even if the VA->PA map is 2676 * the same 2677 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2678 * translation, which means that we have one mmu_idx that deals with two 2679 * concatenated translation regimes [this sort of combined s1+2 TLB is 2680 * architecturally permitted] 2681 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2682 * handling via the TLB. The only way to do a stage 1 translation without 2683 * the immediate stage 2 translation is via the ATS or AT system insns, 2684 * which can be slow-pathed and always do a page table walk. 2685 * The only use of stage 2 translations is either as part of an s1+2 2686 * lookup or when loading the descriptors during a stage 1 page table walk, 2687 * and in both those cases we don't use the TLB. 2688 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2689 * translation regimes, because they map reasonably well to each other 2690 * and they can't both be active at the same time. 2691 * 5. we want to be able to use the TLB for accesses done as part of a 2692 * stage1 page table walk, rather than having to walk the stage2 page 2693 * table over and over. 2694 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2695 * Never (PAN) bit within PSTATE. 2696 * 7. we fold together the secure and non-secure regimes for A-profile, 2697 * because there are no banked system registers for aarch64, so the 2698 * process of switching between secure and non-secure is 2699 * already heavyweight. 2700 * 2701 * This gives us the following list of cases: 2702 * 2703 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2704 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2705 * EL1 EL1&0 stage 1+2 +PAN 2706 * EL0 EL2&0 2707 * EL2 EL2&0 2708 * EL2 EL2&0 +PAN 2709 * EL2 (aka NS PL2) 2710 * EL3 (aka S PL1) 2711 * Physical (NS & S) 2712 * Stage2 (NS & S) 2713 * 2714 * for a total of 12 different mmu_idx. 2715 * 2716 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2717 * as A profile. They only need to distinguish EL0 and EL1 (and 2718 * EL2 if we ever model a Cortex-R52). 2719 * 2720 * M profile CPUs are rather different as they do not have a true MMU. 2721 * They have the following different MMU indexes: 2722 * User 2723 * Privileged 2724 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2725 * Privileged, execution priority negative (ditto) 2726 * If the CPU supports the v8M Security Extension then there are also: 2727 * Secure User 2728 * Secure Privileged 2729 * Secure User, execution priority negative 2730 * Secure Privileged, execution priority negative 2731 * 2732 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2733 * are not quite the same -- different CPU types (most notably M profile 2734 * vs A/R profile) would like to use MMU indexes with different semantics, 2735 * but since we don't ever need to use all of those in a single CPU we 2736 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2737 * modes + total number of M profile MMU modes". The lower bits of 2738 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2739 * the same for any particular CPU. 2740 * Variables of type ARMMUIdx are always full values, and the core 2741 * index values are in variables of type 'int'. 2742 * 2743 * Our enumeration includes at the end some entries which are not "true" 2744 * mmu_idx values in that they don't have corresponding TLBs and are only 2745 * valid for doing slow path page table walks. 2746 * 2747 * The constant names here are patterned after the general style of the names 2748 * of the AT/ATS operations. 2749 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2750 * For M profile we arrange them to have a bit for priv, a bit for negpri 2751 * and a bit for secure. 2752 */ 2753 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2754 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2755 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2756 2757 /* Meanings of the bits for M profile mmu idx values */ 2758 #define ARM_MMU_IDX_M_PRIV 0x1 2759 #define ARM_MMU_IDX_M_NEGPRI 0x2 2760 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2761 2762 #define ARM_MMU_IDX_TYPE_MASK \ 2763 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2764 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2765 2766 typedef enum ARMMMUIdx { 2767 /* 2768 * A-profile. 2769 */ 2770 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2771 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2772 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2773 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2774 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2775 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2776 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2777 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2778 2779 /* TLBs with 1-1 mapping to the physical address spaces. */ 2780 ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A, 2781 ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A, 2782 2783 /* 2784 * Used for second stage of an S12 page table walk, or for descriptor 2785 * loads during first stage of an S1 page table walk. Note that both 2786 * are in use simultaneously for SecureEL2: the security state for 2787 * the S2 ptw is selected by the NS bit from the S1 ptw. 2788 */ 2789 ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A, 2790 ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A, 2791 2792 /* 2793 * These are not allocated TLBs and are used only for AT system 2794 * instructions or for the first stage of an S12 page table walk. 2795 */ 2796 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2797 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2798 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2799 2800 /* 2801 * M-profile. 2802 */ 2803 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2804 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2805 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2806 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2807 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2808 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2809 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2810 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2811 } ARMMMUIdx; 2812 2813 /* 2814 * Bit macros for the core-mmu-index values for each index, 2815 * for use when calling tlb_flush_by_mmuidx() and friends. 2816 */ 2817 #define TO_CORE_BIT(NAME) \ 2818 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2819 2820 typedef enum ARMMMUIdxBit { 2821 TO_CORE_BIT(E10_0), 2822 TO_CORE_BIT(E20_0), 2823 TO_CORE_BIT(E10_1), 2824 TO_CORE_BIT(E10_1_PAN), 2825 TO_CORE_BIT(E2), 2826 TO_CORE_BIT(E20_2), 2827 TO_CORE_BIT(E20_2_PAN), 2828 TO_CORE_BIT(E3), 2829 TO_CORE_BIT(Stage2), 2830 TO_CORE_BIT(Stage2_S), 2831 2832 TO_CORE_BIT(MUser), 2833 TO_CORE_BIT(MPriv), 2834 TO_CORE_BIT(MUserNegPri), 2835 TO_CORE_BIT(MPrivNegPri), 2836 TO_CORE_BIT(MSUser), 2837 TO_CORE_BIT(MSPriv), 2838 TO_CORE_BIT(MSUserNegPri), 2839 TO_CORE_BIT(MSPrivNegPri), 2840 } ARMMMUIdxBit; 2841 2842 #undef TO_CORE_BIT 2843 2844 #define MMU_USER_IDX 0 2845 2846 /* Indexes used when registering address spaces with cpu_address_space_init */ 2847 typedef enum ARMASIdx { 2848 ARMASIdx_NS = 0, 2849 ARMASIdx_S = 1, 2850 ARMASIdx_TagNS = 2, 2851 ARMASIdx_TagS = 3, 2852 } ARMASIdx; 2853 2854 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2855 { 2856 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2857 * CSSELR is RAZ/WI. 2858 */ 2859 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2860 } 2861 2862 static inline bool arm_sctlr_b(CPUARMState *env) 2863 { 2864 return 2865 /* We need not implement SCTLR.ITD in user-mode emulation, so 2866 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2867 * This lets people run BE32 binaries with "-cpu any". 2868 */ 2869 #ifndef CONFIG_USER_ONLY 2870 !arm_feature(env, ARM_FEATURE_V7) && 2871 #endif 2872 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2873 } 2874 2875 uint64_t arm_sctlr(CPUARMState *env, int el); 2876 2877 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 2878 bool sctlr_b) 2879 { 2880 #ifdef CONFIG_USER_ONLY 2881 /* 2882 * In system mode, BE32 is modelled in line with the 2883 * architecture (as word-invariant big-endianness), where loads 2884 * and stores are done little endian but from addresses which 2885 * are adjusted by XORing with the appropriate constant. So the 2886 * endianness to use for the raw data access is not affected by 2887 * SCTLR.B. 2888 * In user mode, however, we model BE32 as byte-invariant 2889 * big-endianness (because user-only code cannot tell the 2890 * difference), and so we need to use a data access endianness 2891 * that depends on SCTLR.B. 2892 */ 2893 if (sctlr_b) { 2894 return true; 2895 } 2896 #endif 2897 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2898 return env->uncached_cpsr & CPSR_E; 2899 } 2900 2901 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 2902 { 2903 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 2904 } 2905 2906 /* Return true if the processor is in big-endian mode. */ 2907 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2908 { 2909 if (!is_a64(env)) { 2910 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 2911 } else { 2912 int cur_el = arm_current_el(env); 2913 uint64_t sctlr = arm_sctlr(env, cur_el); 2914 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 2915 } 2916 } 2917 2918 #include "exec/cpu-all.h" 2919 2920 /* 2921 * We have more than 32-bits worth of state per TB, so we split the data 2922 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 2923 * We collect these two parts in CPUARMTBFlags where they are named 2924 * flags and flags2 respectively. 2925 * 2926 * The flags that are shared between all execution modes, TBFLAG_ANY, 2927 * are stored in flags. The flags that are specific to a given mode 2928 * are stores in flags2. Since cs_base is sized on the configured 2929 * address size, flags2 always has 64-bits for A64, and a minimum of 2930 * 32-bits for A32 and M32. 2931 * 2932 * The bits for 32-bit A-profile and M-profile partially overlap: 2933 * 2934 * 31 23 11 10 0 2935 * +-------------+----------+----------------+ 2936 * | | | TBFLAG_A32 | 2937 * | TBFLAG_AM32 | +-----+----------+ 2938 * | | |TBFLAG_M32| 2939 * +-------------+----------------+----------+ 2940 * 31 23 6 5 0 2941 * 2942 * Unless otherwise noted, these bits are cached in env->hflags. 2943 */ 2944 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 2945 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 2946 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 2947 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 2948 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 2949 /* Target EL if we take a floating-point-disabled exception */ 2950 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 2951 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 2952 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 2953 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 2954 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 2955 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 2956 2957 /* 2958 * Bit usage when in AArch32 state, both A- and M-profile. 2959 */ 2960 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 2961 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 2962 2963 /* 2964 * Bit usage when in AArch32 state, for A-profile only. 2965 */ 2966 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 2967 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 2968 /* 2969 * We store the bottom two bits of the CPAR as TB flags and handle 2970 * checks on the other bits at runtime. This shares the same bits as 2971 * VECSTRIDE, which is OK as no XScale CPU has VFP. 2972 * Not cached, because VECLEN+VECSTRIDE are not cached. 2973 */ 2974 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 2975 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 2976 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 2977 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 2978 /* 2979 * Indicates whether cp register reads and writes by guest code should access 2980 * the secure or nonsecure bank of banked registers; note that this is not 2981 * the same thing as the current security state of the processor! 2982 */ 2983 FIELD(TBFLAG_A32, NS, 10, 1) 2984 /* 2985 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 2986 * This requires an SME trap from AArch32 mode when using NEON. 2987 */ 2988 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 2989 2990 /* 2991 * Bit usage when in AArch32 state, for M-profile only. 2992 */ 2993 /* Handler (ie not Thread) mode */ 2994 FIELD(TBFLAG_M32, HANDLER, 0, 1) 2995 /* Whether we should generate stack-limit checks */ 2996 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 2997 /* Set if FPCCR.LSPACT is set */ 2998 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 2999 /* Set if we must create a new FP context */ 3000 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3001 /* Set if FPCCR.S does not match current security state */ 3002 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3003 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3004 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3005 /* Set if in secure mode */ 3006 FIELD(TBFLAG_M32, SECURE, 6, 1) 3007 3008 /* 3009 * Bit usage when in AArch64 state 3010 */ 3011 FIELD(TBFLAG_A64, TBII, 0, 2) 3012 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3013 /* The current vector length, either NVL or SVL. */ 3014 FIELD(TBFLAG_A64, VL, 4, 4) 3015 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3016 FIELD(TBFLAG_A64, BT, 9, 1) 3017 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3018 FIELD(TBFLAG_A64, TBID, 12, 2) 3019 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3020 FIELD(TBFLAG_A64, ATA, 15, 1) 3021 FIELD(TBFLAG_A64, TCMA, 16, 2) 3022 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3023 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3024 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3025 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3026 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3027 FIELD(TBFLAG_A64, SVL, 24, 4) 3028 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3029 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3030 FIELD(TBFLAG_A64, FGT_ERET, 29, 1) 3031 3032 /* 3033 * Helpers for using the above. 3034 */ 3035 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3036 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3037 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3038 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3039 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3040 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3041 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3042 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3043 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3044 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3045 3046 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3047 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3048 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3049 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3050 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3051 3052 /** 3053 * cpu_mmu_index: 3054 * @env: The cpu environment 3055 * @ifetch: True for code access, false for data access. 3056 * 3057 * Return the core mmu index for the current translation regime. 3058 * This function is used by generic TCG code paths. 3059 */ 3060 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3061 { 3062 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3063 } 3064 3065 /** 3066 * sve_vq 3067 * @env: the cpu context 3068 * 3069 * Return the VL cached within env->hflags, in units of quadwords. 3070 */ 3071 static inline int sve_vq(CPUARMState *env) 3072 { 3073 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3074 } 3075 3076 /** 3077 * sme_vq 3078 * @env: the cpu context 3079 * 3080 * Return the SVL cached within env->hflags, in units of quadwords. 3081 */ 3082 static inline int sme_vq(CPUARMState *env) 3083 { 3084 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3085 } 3086 3087 static inline bool bswap_code(bool sctlr_b) 3088 { 3089 #ifdef CONFIG_USER_ONLY 3090 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3091 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3092 * would also end up as a mixed-endian mode with BE code, LE data. 3093 */ 3094 return 3095 #if TARGET_BIG_ENDIAN 3096 1 ^ 3097 #endif 3098 sctlr_b; 3099 #else 3100 /* All code access in ARM is little endian, and there are no loaders 3101 * doing swaps that need to be reversed 3102 */ 3103 return 0; 3104 #endif 3105 } 3106 3107 #ifdef CONFIG_USER_ONLY 3108 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3109 { 3110 return 3111 #if TARGET_BIG_ENDIAN 3112 1 ^ 3113 #endif 3114 arm_cpu_data_is_big_endian(env); 3115 } 3116 #endif 3117 3118 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3119 target_ulong *cs_base, uint32_t *flags); 3120 3121 enum { 3122 QEMU_PSCI_CONDUIT_DISABLED = 0, 3123 QEMU_PSCI_CONDUIT_SMC = 1, 3124 QEMU_PSCI_CONDUIT_HVC = 2, 3125 }; 3126 3127 #ifndef CONFIG_USER_ONLY 3128 /* Return the address space index to use for a memory access */ 3129 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3130 { 3131 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3132 } 3133 3134 /* Return the AddressSpace to use for a memory access 3135 * (which depends on whether the access is S or NS, and whether 3136 * the board gave us a separate AddressSpace for S accesses). 3137 */ 3138 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3139 { 3140 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3141 } 3142 #endif 3143 3144 /** 3145 * arm_register_pre_el_change_hook: 3146 * Register a hook function which will be called immediately before this 3147 * CPU changes exception level or mode. The hook function will be 3148 * passed a pointer to the ARMCPU and the opaque data pointer passed 3149 * to this function when the hook was registered. 3150 * 3151 * Note that if a pre-change hook is called, any registered post-change hooks 3152 * are guaranteed to subsequently be called. 3153 */ 3154 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3155 void *opaque); 3156 /** 3157 * arm_register_el_change_hook: 3158 * Register a hook function which will be called immediately after this 3159 * CPU changes exception level or mode. The hook function will be 3160 * passed a pointer to the ARMCPU and the opaque data pointer passed 3161 * to this function when the hook was registered. 3162 * 3163 * Note that any registered hooks registered here are guaranteed to be called 3164 * if pre-change hooks have been. 3165 */ 3166 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3167 *opaque); 3168 3169 /** 3170 * arm_rebuild_hflags: 3171 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3172 */ 3173 void arm_rebuild_hflags(CPUARMState *env); 3174 3175 /** 3176 * aa32_vfp_dreg: 3177 * Return a pointer to the Dn register within env in 32-bit mode. 3178 */ 3179 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3180 { 3181 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3182 } 3183 3184 /** 3185 * aa32_vfp_qreg: 3186 * Return a pointer to the Qn register within env in 32-bit mode. 3187 */ 3188 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3189 { 3190 return &env->vfp.zregs[regno].d[0]; 3191 } 3192 3193 /** 3194 * aa64_vfp_qreg: 3195 * Return a pointer to the Qn register within env in 64-bit mode. 3196 */ 3197 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3198 { 3199 return &env->vfp.zregs[regno].d[0]; 3200 } 3201 3202 /* Shared between translate-sve.c and sve_helper.c. */ 3203 extern const uint64_t pred_esz_masks[5]; 3204 3205 /* 3206 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3207 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3208 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3209 */ 3210 #define PAGE_BTI PAGE_TARGET_1 3211 #define PAGE_MTE PAGE_TARGET_2 3212 #define PAGE_TARGET_STICKY PAGE_MTE 3213 3214 /* We associate one allocation tag per 16 bytes, the minimum. */ 3215 #define LOG2_TAG_GRANULE 4 3216 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3217 3218 #ifdef CONFIG_USER_ONLY 3219 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3220 #endif 3221 3222 #ifdef TARGET_TAGGED_ADDRESSES 3223 /** 3224 * cpu_untagged_addr: 3225 * @cs: CPU context 3226 * @x: tagged address 3227 * 3228 * Remove any address tag from @x. This is explicitly related to the 3229 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3230 * 3231 * There should be a better place to put this, but we need this in 3232 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3233 */ 3234 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3235 { 3236 ARMCPU *cpu = ARM_CPU(cs); 3237 if (cpu->env.tagged_addr_enable) { 3238 /* 3239 * TBI is enabled for userspace but not kernelspace addresses. 3240 * Only clear the tag if bit 55 is clear. 3241 */ 3242 x &= sextract64(x, 0, 56); 3243 } 3244 return x; 3245 } 3246 #endif 3247 3248 /* 3249 * Naming convention for isar_feature functions: 3250 * Functions which test 32-bit ID registers should have _aa32_ in 3251 * their name. Functions which test 64-bit ID registers should have 3252 * _aa64_ in their name. These must only be used in code where we 3253 * know for certain that the CPU has AArch32 or AArch64 respectively 3254 * or where the correct answer for a CPU which doesn't implement that 3255 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3256 * system registers that are specific to that CPU state, for "should 3257 * we let this system register bit be set" tests where the 32-bit 3258 * flavour of the register doesn't have the bit, and so on). 3259 * Functions which simply ask "does this feature exist at all" have 3260 * _any_ in their name, and always return the logical OR of the _aa64_ 3261 * and the _aa32_ function. 3262 */ 3263 3264 /* 3265 * 32-bit feature tests via id registers. 3266 */ 3267 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3268 { 3269 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3270 } 3271 3272 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3273 { 3274 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3275 } 3276 3277 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3278 { 3279 /* (M-profile) low-overhead loops and branch future */ 3280 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3281 } 3282 3283 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3284 { 3285 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3286 } 3287 3288 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3289 { 3290 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3291 } 3292 3293 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3294 { 3295 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3296 } 3297 3298 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3299 { 3300 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3301 } 3302 3303 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3304 { 3305 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3306 } 3307 3308 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3309 { 3310 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3311 } 3312 3313 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3314 { 3315 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3316 } 3317 3318 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3319 { 3320 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3321 } 3322 3323 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3324 { 3325 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3326 } 3327 3328 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3329 { 3330 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3331 } 3332 3333 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3334 { 3335 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3336 } 3337 3338 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3339 { 3340 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3341 } 3342 3343 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3344 { 3345 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3346 } 3347 3348 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3349 { 3350 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3351 } 3352 3353 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3354 { 3355 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3356 } 3357 3358 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3359 { 3360 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3361 } 3362 3363 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3364 { 3365 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3366 } 3367 3368 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3369 { 3370 /* 3371 * Return true if M-profile state handling insns 3372 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3373 */ 3374 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3375 } 3376 3377 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3378 { 3379 /* Sadly this is encoded differently for A-profile and M-profile */ 3380 if (isar_feature_aa32_mprofile(id)) { 3381 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3382 } else { 3383 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3384 } 3385 } 3386 3387 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3388 { 3389 /* 3390 * Return true if MVE is supported (either integer or floating point). 3391 * We must check for M-profile as the MVFR1 field means something 3392 * else for A-profile. 3393 */ 3394 return isar_feature_aa32_mprofile(id) && 3395 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3396 } 3397 3398 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3399 { 3400 /* 3401 * Return true if MVE is supported (either integer or floating point). 3402 * We must check for M-profile as the MVFR1 field means something 3403 * else for A-profile. 3404 */ 3405 return isar_feature_aa32_mprofile(id) && 3406 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3407 } 3408 3409 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3410 { 3411 /* 3412 * Return true if either VFP or SIMD is implemented. 3413 * In this case, a minimum of VFP w/ D0-D15. 3414 */ 3415 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3416 } 3417 3418 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3419 { 3420 /* Return true if D16-D31 are implemented */ 3421 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3422 } 3423 3424 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3425 { 3426 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3427 } 3428 3429 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3430 { 3431 /* Return true if CPU supports single precision floating point, VFPv2 */ 3432 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3433 } 3434 3435 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3436 { 3437 /* Return true if CPU supports single precision floating point, VFPv3 */ 3438 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3439 } 3440 3441 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3442 { 3443 /* Return true if CPU supports double precision floating point, VFPv2 */ 3444 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3445 } 3446 3447 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3448 { 3449 /* Return true if CPU supports double precision floating point, VFPv3 */ 3450 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3451 } 3452 3453 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3454 { 3455 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3456 } 3457 3458 /* 3459 * We always set the FP and SIMD FP16 fields to indicate identical 3460 * levels of support (assuming SIMD is implemented at all), so 3461 * we only need one set of accessors. 3462 */ 3463 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3464 { 3465 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3466 } 3467 3468 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3469 { 3470 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3471 } 3472 3473 /* 3474 * Note that this ID register field covers both VFP and Neon FMAC, 3475 * so should usually be tested in combination with some other 3476 * check that confirms the presence of whichever of VFP or Neon is 3477 * relevant, to avoid accidentally enabling a Neon feature on 3478 * a VFP-no-Neon core or vice-versa. 3479 */ 3480 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3481 { 3482 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3483 } 3484 3485 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3486 { 3487 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3488 } 3489 3490 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3491 { 3492 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3493 } 3494 3495 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3496 { 3497 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3498 } 3499 3500 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3501 { 3502 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3503 } 3504 3505 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3506 { 3507 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3508 } 3509 3510 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3511 { 3512 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3513 } 3514 3515 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3516 { 3517 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3518 } 3519 3520 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) 3521 { 3522 /* 0xf means "non-standard IMPDEF PMU" */ 3523 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3524 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3525 } 3526 3527 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) 3528 { 3529 /* 0xf means "non-standard IMPDEF PMU" */ 3530 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3531 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3532 } 3533 3534 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) 3535 { 3536 /* 0xf means "non-standard IMPDEF PMU" */ 3537 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 && 3538 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3539 } 3540 3541 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3542 { 3543 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3544 } 3545 3546 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3547 { 3548 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3549 } 3550 3551 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3552 { 3553 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3554 } 3555 3556 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3557 { 3558 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3559 } 3560 3561 static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) 3562 { 3563 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1; 3564 } 3565 3566 static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) 3567 { 3568 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2; 3569 } 3570 3571 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3572 { 3573 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3574 } 3575 3576 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3577 { 3578 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3579 } 3580 3581 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) 3582 { 3583 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5; 3584 } 3585 3586 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3587 { 3588 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3589 } 3590 3591 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) 3592 { 3593 return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0; 3594 } 3595 3596 /* 3597 * 64-bit feature tests via id registers. 3598 */ 3599 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3600 { 3601 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3602 } 3603 3604 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3605 { 3606 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3607 } 3608 3609 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3610 { 3611 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3612 } 3613 3614 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3615 { 3616 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3617 } 3618 3619 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3620 { 3621 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3622 } 3623 3624 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3625 { 3626 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3627 } 3628 3629 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3630 { 3631 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3632 } 3633 3634 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3635 { 3636 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3637 } 3638 3639 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3640 { 3641 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3642 } 3643 3644 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3645 { 3646 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3647 } 3648 3649 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3650 { 3651 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3652 } 3653 3654 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3655 { 3656 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3657 } 3658 3659 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3660 { 3661 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3662 } 3663 3664 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3665 { 3666 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3667 } 3668 3669 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3670 { 3671 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3672 } 3673 3674 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3675 { 3676 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3677 } 3678 3679 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3680 { 3681 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3682 } 3683 3684 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3685 { 3686 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3687 } 3688 3689 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3690 { 3691 /* 3692 * Return true if any form of pauth is enabled, as this 3693 * predicate controls migration of the 128-bit keys. 3694 */ 3695 return (id->id_aa64isar1 & 3696 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3697 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3698 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3699 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3700 } 3701 3702 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3703 { 3704 /* 3705 * Return true if pauth is enabled with the architected QARMA algorithm. 3706 * QEMU will always set APA+GPA to the same value. 3707 */ 3708 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3709 } 3710 3711 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3712 { 3713 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3714 } 3715 3716 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3717 { 3718 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3719 } 3720 3721 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3722 { 3723 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3724 } 3725 3726 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3727 { 3728 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3729 } 3730 3731 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3732 { 3733 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3734 } 3735 3736 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3737 { 3738 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3739 } 3740 3741 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3742 { 3743 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3744 } 3745 3746 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3747 { 3748 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3749 } 3750 3751 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3752 { 3753 /* We always set the AdvSIMD and FP fields identically. */ 3754 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3755 } 3756 3757 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3758 { 3759 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3760 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3761 } 3762 3763 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3764 { 3765 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3766 } 3767 3768 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3769 { 3770 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3771 } 3772 3773 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) 3774 { 3775 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; 3776 } 3777 3778 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3779 { 3780 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 3781 } 3782 3783 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) 3784 { 3785 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2; 3786 } 3787 3788 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3789 { 3790 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3791 } 3792 3793 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 3794 { 3795 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 3796 } 3797 3798 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3799 { 3800 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3801 } 3802 3803 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3804 { 3805 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3806 } 3807 3808 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3809 { 3810 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3811 } 3812 3813 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3814 { 3815 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3816 } 3817 3818 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) 3819 { 3820 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; 3821 } 3822 3823 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 3824 { 3825 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 3826 } 3827 3828 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 3829 { 3830 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 3831 } 3832 3833 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) 3834 { 3835 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; 3836 } 3837 3838 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) 3839 { 3840 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; 3841 } 3842 3843 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) 3844 { 3845 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1; 3846 } 3847 3848 static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) 3849 { 3850 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2; 3851 } 3852 3853 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3854 { 3855 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3856 } 3857 3858 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 3859 { 3860 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 3861 } 3862 3863 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 3864 { 3865 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 3866 } 3867 3868 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) 3869 { 3870 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; 3871 } 3872 3873 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) 3874 { 3875 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 3876 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3877 } 3878 3879 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) 3880 { 3881 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 3882 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3883 } 3884 3885 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) 3886 { 3887 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 && 3888 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3889 } 3890 3891 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 3892 { 3893 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 3894 } 3895 3896 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 3897 { 3898 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 3899 } 3900 3901 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 3902 { 3903 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 3904 } 3905 3906 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 3907 { 3908 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 3909 } 3910 3911 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 3912 { 3913 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 3914 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 3915 } 3916 3917 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 3918 { 3919 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 3920 } 3921 3922 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 3923 { 3924 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 3925 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 3926 } 3927 3928 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) 3929 { 3930 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0; 3931 } 3932 3933 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) 3934 { 3935 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1; 3936 } 3937 3938 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) 3939 { 3940 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0; 3941 } 3942 3943 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) 3944 { 3945 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 3946 return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id)); 3947 } 3948 3949 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) 3950 { 3951 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 3952 return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id)); 3953 } 3954 3955 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) 3956 { 3957 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); 3958 return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); 3959 } 3960 3961 static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) 3962 { 3963 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0; 3964 } 3965 3966 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 3967 { 3968 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 3969 } 3970 3971 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 3972 { 3973 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 3974 } 3975 3976 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) 3977 { 3978 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; 3979 } 3980 3981 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) 3982 { 3983 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0; 3984 } 3985 3986 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) 3987 { 3988 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2; 3989 } 3990 3991 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 3992 { 3993 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 3994 } 3995 3996 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 3997 { 3998 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 3999 } 4000 4001 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 4002 { 4003 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); 4004 if (key >= 2) { 4005 return true; /* FEAT_CSV2_2 */ 4006 } 4007 if (key == 1) { 4008 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); 4009 return key >= 2; /* FEAT_CSV2_1p2 */ 4010 } 4011 return false; 4012 } 4013 4014 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4015 { 4016 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4017 } 4018 4019 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4020 { 4021 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4022 } 4023 4024 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4025 { 4026 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4027 } 4028 4029 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4030 { 4031 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4032 } 4033 4034 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4035 { 4036 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4037 } 4038 4039 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4040 { 4041 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4042 } 4043 4044 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4045 { 4046 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4047 } 4048 4049 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4050 { 4051 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4052 } 4053 4054 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4055 { 4056 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4057 } 4058 4059 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4060 { 4061 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4062 } 4063 4064 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4065 { 4066 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4067 } 4068 4069 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4070 { 4071 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4072 } 4073 4074 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) 4075 { 4076 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); 4077 } 4078 4079 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) 4080 { 4081 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; 4082 } 4083 4084 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) 4085 { 4086 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); 4087 } 4088 4089 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) 4090 { 4091 return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; 4092 } 4093 4094 /* 4095 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4096 */ 4097 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4098 { 4099 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4100 } 4101 4102 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4103 { 4104 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4105 } 4106 4107 static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id) 4108 { 4109 return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id); 4110 } 4111 4112 static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) 4113 { 4114 return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); 4115 } 4116 4117 static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) 4118 { 4119 return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); 4120 } 4121 4122 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4123 { 4124 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4125 } 4126 4127 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4128 { 4129 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4130 } 4131 4132 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4133 { 4134 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4135 } 4136 4137 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4138 { 4139 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4140 } 4141 4142 static inline bool isar_feature_any_half_evt(const ARMISARegisters *id) 4143 { 4144 return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id); 4145 } 4146 4147 static inline bool isar_feature_any_evt(const ARMISARegisters *id) 4148 { 4149 return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); 4150 } 4151 4152 /* 4153 * Forward to the above feature tests given an ARMCPU pointer. 4154 */ 4155 #define cpu_isar_feature(name, cpu) \ 4156 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4157 4158 #endif 4159