1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 typedef struct { 170 uint64_t raw_tcr; 171 uint32_t mask; 172 uint32_t base_mask; 173 } TCR; 174 175 #define VTCR_NSW (1u << 29) 176 #define VTCR_NSA (1u << 30) 177 #define VSTCR_SW VTCR_NSW 178 #define VSTCR_SA VTCR_NSA 179 180 /* Define a maximum sized vector register. 181 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 182 * For 64-bit, this is a 2048-bit SVE register. 183 * 184 * Note that the mapping between S, D, and Q views of the register bank 185 * differs between AArch64 and AArch32. 186 * In AArch32: 187 * Qn = regs[n].d[1]:regs[n].d[0] 188 * Dn = regs[n / 2].d[n & 1] 189 * Sn = regs[n / 4].d[n % 4 / 2], 190 * bits 31..0 for even n, and bits 63..32 for odd n 191 * (and regs[16] to regs[31] are inaccessible) 192 * In AArch64: 193 * Zn = regs[n].d[*] 194 * Qn = regs[n].d[1]:regs[n].d[0] 195 * Dn = regs[n].d[0] 196 * Sn = regs[n].d[0] bits 31..0 197 * Hn = regs[n].d[0] bits 15..0 198 * 199 * This corresponds to the architecturally defined mapping between 200 * the two execution states, and means we do not need to explicitly 201 * map these registers when changing states. 202 * 203 * Align the data for use with TCG host vector operations. 204 */ 205 206 #ifdef TARGET_AARCH64 207 # define ARM_MAX_VQ 16 208 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 209 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); 210 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); 211 #else 212 # define ARM_MAX_VQ 1 213 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 214 static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } 215 static inline void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { } 216 #endif 217 218 typedef struct ARMVectorReg { 219 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 220 } ARMVectorReg; 221 222 #ifdef TARGET_AARCH64 223 /* In AArch32 mode, predicate registers do not exist at all. */ 224 typedef struct ARMPredicateReg { 225 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 226 } ARMPredicateReg; 227 228 /* In AArch32 mode, PAC keys do not exist at all. */ 229 typedef struct ARMPACKey { 230 uint64_t lo, hi; 231 } ARMPACKey; 232 #endif 233 234 /* See the commentary above the TBFLAG field definitions. */ 235 typedef struct CPUARMTBFlags { 236 uint32_t flags; 237 target_ulong flags2; 238 } CPUARMTBFlags; 239 240 typedef struct CPUArchState { 241 /* Regs for current mode. */ 242 uint32_t regs[16]; 243 244 /* 32/64 switch only happens when taking and returning from 245 * exceptions so the overlap semantics are taken care of then 246 * instead of having a complicated union. 247 */ 248 /* Regs for A64 mode. */ 249 uint64_t xregs[32]; 250 uint64_t pc; 251 /* PSTATE isn't an architectural register for ARMv8. However, it is 252 * convenient for us to assemble the underlying state into a 32 bit format 253 * identical to the architectural format used for the SPSR. (This is also 254 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 255 * 'pstate' register are.) Of the PSTATE bits: 256 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 257 * semantics as for AArch32, as described in the comments on each field) 258 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 259 * DAIF (exception masks) are kept in env->daif 260 * BTYPE is kept in env->btype 261 * all other bits are stored in their correct places in env->pstate 262 */ 263 uint32_t pstate; 264 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 265 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 266 267 /* Cached TBFLAGS state. See below for which bits are included. */ 268 CPUARMTBFlags hflags; 269 270 /* Frequently accessed CPSR bits are stored separately for efficiency. 271 This contains all the other bits. Use cpsr_{read,write} to access 272 the whole CPSR. */ 273 uint32_t uncached_cpsr; 274 uint32_t spsr; 275 276 /* Banked registers. */ 277 uint64_t banked_spsr[8]; 278 uint32_t banked_r13[8]; 279 uint32_t banked_r14[8]; 280 281 /* These hold r8-r12. */ 282 uint32_t usr_regs[5]; 283 uint32_t fiq_regs[5]; 284 285 /* cpsr flag cache for faster execution */ 286 uint32_t CF; /* 0 or 1 */ 287 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 288 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 289 uint32_t ZF; /* Z set if zero. */ 290 uint32_t QF; /* 0 or 1 */ 291 uint32_t GE; /* cpsr[19:16] */ 292 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 293 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 294 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 295 296 uint64_t elr_el[4]; /* AArch64 exception link regs */ 297 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 298 299 /* System control coprocessor (cp15) */ 300 struct { 301 uint32_t c0_cpuid; 302 union { /* Cache size selection */ 303 struct { 304 uint64_t _unused_csselr0; 305 uint64_t csselr_ns; 306 uint64_t _unused_csselr1; 307 uint64_t csselr_s; 308 }; 309 uint64_t csselr_el[4]; 310 }; 311 union { /* System control register. */ 312 struct { 313 uint64_t _unused_sctlr; 314 uint64_t sctlr_ns; 315 uint64_t hsctlr; 316 uint64_t sctlr_s; 317 }; 318 uint64_t sctlr_el[4]; 319 }; 320 uint64_t cpacr_el1; /* Architectural feature access control register */ 321 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 322 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 323 uint64_t sder; /* Secure debug enable register. */ 324 uint32_t nsacr; /* Non-secure access control register. */ 325 union { /* MMU translation table base 0. */ 326 struct { 327 uint64_t _unused_ttbr0_0; 328 uint64_t ttbr0_ns; 329 uint64_t _unused_ttbr0_1; 330 uint64_t ttbr0_s; 331 }; 332 uint64_t ttbr0_el[4]; 333 }; 334 union { /* MMU translation table base 1. */ 335 struct { 336 uint64_t _unused_ttbr1_0; 337 uint64_t ttbr1_ns; 338 uint64_t _unused_ttbr1_1; 339 uint64_t ttbr1_s; 340 }; 341 uint64_t ttbr1_el[4]; 342 }; 343 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 344 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 345 /* MMU translation table base control. */ 346 TCR tcr_el[4]; 347 TCR vtcr_el2; /* Virtualization Translation Control. */ 348 TCR vstcr_el2; /* Secure Virtualization Translation Control. */ 349 uint32_t c2_data; /* MPU data cacheable bits. */ 350 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 351 union { /* MMU domain access control register 352 * MPU write buffer control. 353 */ 354 struct { 355 uint64_t dacr_ns; 356 uint64_t dacr_s; 357 }; 358 struct { 359 uint64_t dacr32_el2; 360 }; 361 }; 362 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 363 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 364 uint64_t hcr_el2; /* Hypervisor configuration register */ 365 uint64_t scr_el3; /* Secure configuration register. */ 366 union { /* Fault status registers. */ 367 struct { 368 uint64_t ifsr_ns; 369 uint64_t ifsr_s; 370 }; 371 struct { 372 uint64_t ifsr32_el2; 373 }; 374 }; 375 union { 376 struct { 377 uint64_t _unused_dfsr; 378 uint64_t dfsr_ns; 379 uint64_t hsr; 380 uint64_t dfsr_s; 381 }; 382 uint64_t esr_el[4]; 383 }; 384 uint32_t c6_region[8]; /* MPU base/size registers. */ 385 union { /* Fault address registers. */ 386 struct { 387 uint64_t _unused_far0; 388 #if HOST_BIG_ENDIAN 389 uint32_t ifar_ns; 390 uint32_t dfar_ns; 391 uint32_t ifar_s; 392 uint32_t dfar_s; 393 #else 394 uint32_t dfar_ns; 395 uint32_t ifar_ns; 396 uint32_t dfar_s; 397 uint32_t ifar_s; 398 #endif 399 uint64_t _unused_far3; 400 }; 401 uint64_t far_el[4]; 402 }; 403 uint64_t hpfar_el2; 404 uint64_t hstr_el2; 405 union { /* Translation result. */ 406 struct { 407 uint64_t _unused_par_0; 408 uint64_t par_ns; 409 uint64_t _unused_par_1; 410 uint64_t par_s; 411 }; 412 uint64_t par_el[4]; 413 }; 414 415 uint32_t c9_insn; /* Cache lockdown registers. */ 416 uint32_t c9_data; 417 uint64_t c9_pmcr; /* performance monitor control register */ 418 uint64_t c9_pmcnten; /* perf monitor counter enables */ 419 uint64_t c9_pmovsr; /* perf monitor overflow status */ 420 uint64_t c9_pmuserenr; /* perf monitor user enable */ 421 uint64_t c9_pmselr; /* perf monitor counter selection register */ 422 uint64_t c9_pminten; /* perf monitor interrupt enables */ 423 union { /* Memory attribute redirection */ 424 struct { 425 #if HOST_BIG_ENDIAN 426 uint64_t _unused_mair_0; 427 uint32_t mair1_ns; 428 uint32_t mair0_ns; 429 uint64_t _unused_mair_1; 430 uint32_t mair1_s; 431 uint32_t mair0_s; 432 #else 433 uint64_t _unused_mair_0; 434 uint32_t mair0_ns; 435 uint32_t mair1_ns; 436 uint64_t _unused_mair_1; 437 uint32_t mair0_s; 438 uint32_t mair1_s; 439 #endif 440 }; 441 uint64_t mair_el[4]; 442 }; 443 union { /* vector base address register */ 444 struct { 445 uint64_t _unused_vbar; 446 uint64_t vbar_ns; 447 uint64_t hvbar; 448 uint64_t vbar_s; 449 }; 450 uint64_t vbar_el[4]; 451 }; 452 uint32_t mvbar; /* (monitor) vector base address register */ 453 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 454 struct { /* FCSE PID. */ 455 uint32_t fcseidr_ns; 456 uint32_t fcseidr_s; 457 }; 458 union { /* Context ID. */ 459 struct { 460 uint64_t _unused_contextidr_0; 461 uint64_t contextidr_ns; 462 uint64_t _unused_contextidr_1; 463 uint64_t contextidr_s; 464 }; 465 uint64_t contextidr_el[4]; 466 }; 467 union { /* User RW Thread register. */ 468 struct { 469 uint64_t tpidrurw_ns; 470 uint64_t tpidrprw_ns; 471 uint64_t htpidr; 472 uint64_t _tpidr_el3; 473 }; 474 uint64_t tpidr_el[4]; 475 }; 476 /* The secure banks of these registers don't map anywhere */ 477 uint64_t tpidrurw_s; 478 uint64_t tpidrprw_s; 479 uint64_t tpidruro_s; 480 481 union { /* User RO Thread register. */ 482 uint64_t tpidruro_ns; 483 uint64_t tpidrro_el[1]; 484 }; 485 uint64_t c14_cntfrq; /* Counter Frequency register */ 486 uint64_t c14_cntkctl; /* Timer Control register */ 487 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 488 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 489 ARMGenericTimer c14_timer[NUM_GTIMERS]; 490 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 491 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 492 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 493 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 494 uint32_t c15_threadid; /* TI debugger thread-ID. */ 495 uint32_t c15_config_base_address; /* SCU base address. */ 496 uint32_t c15_diagnostic; /* diagnostic register */ 497 uint32_t c15_power_diagnostic; 498 uint32_t c15_power_control; /* power control */ 499 uint64_t dbgbvr[16]; /* breakpoint value registers */ 500 uint64_t dbgbcr[16]; /* breakpoint control registers */ 501 uint64_t dbgwvr[16]; /* watchpoint value registers */ 502 uint64_t dbgwcr[16]; /* watchpoint control registers */ 503 uint64_t mdscr_el1; 504 uint64_t oslsr_el1; /* OS Lock Status */ 505 uint64_t mdcr_el2; 506 uint64_t mdcr_el3; 507 /* Stores the architectural value of the counter *the last time it was 508 * updated* by pmccntr_op_start. Accesses should always be surrounded 509 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 510 * architecturally-correct value is being read/set. 511 */ 512 uint64_t c15_ccnt; 513 /* Stores the delta between the architectural value and the underlying 514 * cycle count during normal operation. It is used to update c15_ccnt 515 * to be the correct architectural value before accesses. During 516 * accesses, c15_ccnt_delta contains the underlying count being used 517 * for the access, after which it reverts to the delta value in 518 * pmccntr_op_finish. 519 */ 520 uint64_t c15_ccnt_delta; 521 uint64_t c14_pmevcntr[31]; 522 uint64_t c14_pmevcntr_delta[31]; 523 uint64_t c14_pmevtyper[31]; 524 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 525 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 526 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 527 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 528 uint64_t gcr_el1; 529 uint64_t rgsr_el1; 530 531 /* Minimal RAS registers */ 532 uint64_t disr_el1; 533 uint64_t vdisr_el2; 534 uint64_t vsesr_el2; 535 } cp15; 536 537 struct { 538 /* M profile has up to 4 stack pointers: 539 * a Main Stack Pointer and a Process Stack Pointer for each 540 * of the Secure and Non-Secure states. (If the CPU doesn't support 541 * the security extension then it has only two SPs.) 542 * In QEMU we always store the currently active SP in regs[13], 543 * and the non-active SP for the current security state in 544 * v7m.other_sp. The stack pointers for the inactive security state 545 * are stored in other_ss_msp and other_ss_psp. 546 * switch_v7m_security_state() is responsible for rearranging them 547 * when we change security state. 548 */ 549 uint32_t other_sp; 550 uint32_t other_ss_msp; 551 uint32_t other_ss_psp; 552 uint32_t vecbase[M_REG_NUM_BANKS]; 553 uint32_t basepri[M_REG_NUM_BANKS]; 554 uint32_t control[M_REG_NUM_BANKS]; 555 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 556 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 557 uint32_t hfsr; /* HardFault Status */ 558 uint32_t dfsr; /* Debug Fault Status Register */ 559 uint32_t sfsr; /* Secure Fault Status Register */ 560 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 561 uint32_t bfar; /* BusFault Address */ 562 uint32_t sfar; /* Secure Fault Address Register */ 563 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 564 int exception; 565 uint32_t primask[M_REG_NUM_BANKS]; 566 uint32_t faultmask[M_REG_NUM_BANKS]; 567 uint32_t aircr; /* only holds r/w state if security extn implemented */ 568 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 569 uint32_t csselr[M_REG_NUM_BANKS]; 570 uint32_t scr[M_REG_NUM_BANKS]; 571 uint32_t msplim[M_REG_NUM_BANKS]; 572 uint32_t psplim[M_REG_NUM_BANKS]; 573 uint32_t fpcar[M_REG_NUM_BANKS]; 574 uint32_t fpccr[M_REG_NUM_BANKS]; 575 uint32_t fpdscr[M_REG_NUM_BANKS]; 576 uint32_t cpacr[M_REG_NUM_BANKS]; 577 uint32_t nsacr; 578 uint32_t ltpsize; 579 uint32_t vpr; 580 } v7m; 581 582 /* Information associated with an exception about to be taken: 583 * code which raises an exception must set cs->exception_index and 584 * the relevant parts of this structure; the cpu_do_interrupt function 585 * will then set the guest-visible registers as part of the exception 586 * entry process. 587 */ 588 struct { 589 uint32_t syndrome; /* AArch64 format syndrome register */ 590 uint32_t fsr; /* AArch32 format fault status register info */ 591 uint64_t vaddress; /* virtual addr associated with exception, if any */ 592 uint32_t target_el; /* EL the exception should be targeted for */ 593 /* If we implement EL2 we will also need to store information 594 * about the intermediate physical address for stage 2 faults. 595 */ 596 } exception; 597 598 /* Information associated with an SError */ 599 struct { 600 uint8_t pending; 601 uint8_t has_esr; 602 uint64_t esr; 603 } serror; 604 605 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 606 607 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 608 uint32_t irq_line_state; 609 610 /* Thumb-2 EE state. */ 611 uint32_t teecr; 612 uint32_t teehbr; 613 614 /* VFP coprocessor state. */ 615 struct { 616 ARMVectorReg zregs[32]; 617 618 #ifdef TARGET_AARCH64 619 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 620 #define FFR_PRED_NUM 16 621 ARMPredicateReg pregs[17]; 622 /* Scratch space for aa64 sve predicate temporary. */ 623 ARMPredicateReg preg_tmp; 624 #endif 625 626 /* We store these fpcsr fields separately for convenience. */ 627 uint32_t qc[4] QEMU_ALIGNED(16); 628 int vec_len; 629 int vec_stride; 630 631 uint32_t xregs[16]; 632 633 /* Scratch space for aa32 neon expansion. */ 634 uint32_t scratch[8]; 635 636 /* There are a number of distinct float control structures: 637 * 638 * fp_status: is the "normal" fp status. 639 * fp_status_fp16: used for half-precision calculations 640 * standard_fp_status : the ARM "Standard FPSCR Value" 641 * standard_fp_status_fp16 : used for half-precision 642 * calculations with the ARM "Standard FPSCR Value" 643 * 644 * Half-precision operations are governed by a separate 645 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 646 * status structure to control this. 647 * 648 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 649 * round-to-nearest and is used by any operations (generally 650 * Neon) which the architecture defines as controlled by the 651 * standard FPSCR value rather than the FPSCR. 652 * 653 * The "standard FPSCR but for fp16 ops" is needed because 654 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 655 * using a fixed value for it. 656 * 657 * To avoid having to transfer exception bits around, we simply 658 * say that the FPSCR cumulative exception flags are the logical 659 * OR of the flags in the four fp statuses. This relies on the 660 * only thing which needs to read the exception flags being 661 * an explicit FPSCR read. 662 */ 663 float_status fp_status; 664 float_status fp_status_f16; 665 float_status standard_fp_status; 666 float_status standard_fp_status_f16; 667 668 /* ZCR_EL[1-3] */ 669 uint64_t zcr_el[4]; 670 } vfp; 671 uint64_t exclusive_addr; 672 uint64_t exclusive_val; 673 uint64_t exclusive_high; 674 675 /* iwMMXt coprocessor state. */ 676 struct { 677 uint64_t regs[16]; 678 uint64_t val; 679 680 uint32_t cregs[16]; 681 } iwmmxt; 682 683 #ifdef TARGET_AARCH64 684 struct { 685 ARMPACKey apia; 686 ARMPACKey apib; 687 ARMPACKey apda; 688 ARMPACKey apdb; 689 ARMPACKey apga; 690 } keys; 691 #endif 692 693 #if defined(CONFIG_USER_ONLY) 694 /* For usermode syscall translation. */ 695 int eabi; 696 #endif 697 698 struct CPUBreakpoint *cpu_breakpoint[16]; 699 struct CPUWatchpoint *cpu_watchpoint[16]; 700 701 /* Fields up to this point are cleared by a CPU reset */ 702 struct {} end_reset_fields; 703 704 /* Fields after this point are preserved across CPU reset. */ 705 706 /* Internal CPU feature flags. */ 707 uint64_t features; 708 709 /* PMSAv7 MPU */ 710 struct { 711 uint32_t *drbar; 712 uint32_t *drsr; 713 uint32_t *dracr; 714 uint32_t rnr[M_REG_NUM_BANKS]; 715 } pmsav7; 716 717 /* PMSAv8 MPU */ 718 struct { 719 /* The PMSAv8 implementation also shares some PMSAv7 config 720 * and state: 721 * pmsav7.rnr (region number register) 722 * pmsav7_dregion (number of configured regions) 723 */ 724 uint32_t *rbar[M_REG_NUM_BANKS]; 725 uint32_t *rlar[M_REG_NUM_BANKS]; 726 uint32_t mair0[M_REG_NUM_BANKS]; 727 uint32_t mair1[M_REG_NUM_BANKS]; 728 } pmsav8; 729 730 /* v8M SAU */ 731 struct { 732 uint32_t *rbar; 733 uint32_t *rlar; 734 uint32_t rnr; 735 uint32_t ctrl; 736 } sau; 737 738 void *nvic; 739 const struct arm_boot_info *boot_info; 740 /* Store GICv3CPUState to access from this struct */ 741 void *gicv3state; 742 743 #ifdef TARGET_TAGGED_ADDRESSES 744 /* Linux syscall tagged address support */ 745 bool tagged_addr_enable; 746 #endif 747 } CPUARMState; 748 749 static inline void set_feature(CPUARMState *env, int feature) 750 { 751 env->features |= 1ULL << feature; 752 } 753 754 static inline void unset_feature(CPUARMState *env, int feature) 755 { 756 env->features &= ~(1ULL << feature); 757 } 758 759 /** 760 * ARMELChangeHookFn: 761 * type of a function which can be registered via arm_register_el_change_hook() 762 * to get callbacks when the CPU changes its exception level or mode. 763 */ 764 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 765 typedef struct ARMELChangeHook ARMELChangeHook; 766 struct ARMELChangeHook { 767 ARMELChangeHookFn *hook; 768 void *opaque; 769 QLIST_ENTRY(ARMELChangeHook) node; 770 }; 771 772 /* These values map onto the return values for 773 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 774 typedef enum ARMPSCIState { 775 PSCI_ON = 0, 776 PSCI_OFF = 1, 777 PSCI_ON_PENDING = 2 778 } ARMPSCIState; 779 780 typedef struct ARMISARegisters ARMISARegisters; 781 782 /** 783 * ARMCPU: 784 * @env: #CPUARMState 785 * 786 * An ARM CPU core. 787 */ 788 struct ArchCPU { 789 /*< private >*/ 790 CPUState parent_obj; 791 /*< public >*/ 792 793 CPUNegativeOffsetState neg; 794 CPUARMState env; 795 796 /* Coprocessor information */ 797 GHashTable *cp_regs; 798 /* For marshalling (mostly coprocessor) register state between the 799 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 800 * we use these arrays. 801 */ 802 /* List of register indexes managed via these arrays; (full KVM style 803 * 64 bit indexes, not CPRegInfo 32 bit indexes) 804 */ 805 uint64_t *cpreg_indexes; 806 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 807 uint64_t *cpreg_values; 808 /* Length of the indexes, values, reset_values arrays */ 809 int32_t cpreg_array_len; 810 /* These are used only for migration: incoming data arrives in 811 * these fields and is sanity checked in post_load before copying 812 * to the working data structures above. 813 */ 814 uint64_t *cpreg_vmstate_indexes; 815 uint64_t *cpreg_vmstate_values; 816 int32_t cpreg_vmstate_array_len; 817 818 DynamicGDBXMLInfo dyn_sysreg_xml; 819 DynamicGDBXMLInfo dyn_svereg_xml; 820 821 /* Timers used by the generic (architected) timer */ 822 QEMUTimer *gt_timer[NUM_GTIMERS]; 823 /* 824 * Timer used by the PMU. Its state is restored after migration by 825 * pmu_op_finish() - it does not need other handling during migration 826 */ 827 QEMUTimer *pmu_timer; 828 /* GPIO outputs for generic timer */ 829 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 830 /* GPIO output for GICv3 maintenance interrupt signal */ 831 qemu_irq gicv3_maintenance_interrupt; 832 /* GPIO output for the PMU interrupt */ 833 qemu_irq pmu_interrupt; 834 835 /* MemoryRegion to use for secure physical accesses */ 836 MemoryRegion *secure_memory; 837 838 /* MemoryRegion to use for allocation tag accesses */ 839 MemoryRegion *tag_memory; 840 MemoryRegion *secure_tag_memory; 841 842 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 843 Object *idau; 844 845 /* 'compatible' string for this CPU for Linux device trees */ 846 const char *dtb_compatible; 847 848 /* PSCI version for this CPU 849 * Bits[31:16] = Major Version 850 * Bits[15:0] = Minor Version 851 */ 852 uint32_t psci_version; 853 854 /* Current power state, access guarded by BQL */ 855 ARMPSCIState power_state; 856 857 /* CPU has virtualization extension */ 858 bool has_el2; 859 /* CPU has security extension */ 860 bool has_el3; 861 /* CPU has PMU (Performance Monitor Unit) */ 862 bool has_pmu; 863 /* CPU has VFP */ 864 bool has_vfp; 865 /* CPU has Neon */ 866 bool has_neon; 867 /* CPU has M-profile DSP extension */ 868 bool has_dsp; 869 870 /* CPU has memory protection unit */ 871 bool has_mpu; 872 /* PMSAv7 MPU number of supported regions */ 873 uint32_t pmsav7_dregion; 874 /* v8M SAU number of supported regions */ 875 uint32_t sau_sregion; 876 877 /* PSCI conduit used to invoke PSCI methods 878 * 0 - disabled, 1 - smc, 2 - hvc 879 */ 880 uint32_t psci_conduit; 881 882 /* For v8M, initial value of the Secure VTOR */ 883 uint32_t init_svtor; 884 /* For v8M, initial value of the Non-secure VTOR */ 885 uint32_t init_nsvtor; 886 887 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 888 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 889 */ 890 uint32_t kvm_target; 891 892 /* KVM init features for this CPU */ 893 uint32_t kvm_init_features[7]; 894 895 /* KVM CPU state */ 896 897 /* KVM virtual time adjustment */ 898 bool kvm_adjvtime; 899 bool kvm_vtime_dirty; 900 uint64_t kvm_vtime; 901 902 /* KVM steal time */ 903 OnOffAuto kvm_steal_time; 904 905 /* Uniprocessor system with MP extensions */ 906 bool mp_is_up; 907 908 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 909 * and the probe failed (so we need to report the error in realize) 910 */ 911 bool host_cpu_probe_failed; 912 913 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 914 * register. 915 */ 916 int32_t core_count; 917 918 /* The instance init functions for implementation-specific subclasses 919 * set these fields to specify the implementation-dependent values of 920 * various constant registers and reset values of non-constant 921 * registers. 922 * Some of these might become QOM properties eventually. 923 * Field names match the official register names as defined in the 924 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 925 * is used for reset values of non-constant registers; no reset_ 926 * prefix means a constant register. 927 * Some of these registers are split out into a substructure that 928 * is shared with the translators to control the ISA. 929 * 930 * Note that if you add an ID register to the ARMISARegisters struct 931 * you need to also update the 32-bit and 64-bit versions of the 932 * kvm_arm_get_host_cpu_features() function to correctly populate the 933 * field by reading the value from the KVM vCPU. 934 */ 935 struct ARMISARegisters { 936 uint32_t id_isar0; 937 uint32_t id_isar1; 938 uint32_t id_isar2; 939 uint32_t id_isar3; 940 uint32_t id_isar4; 941 uint32_t id_isar5; 942 uint32_t id_isar6; 943 uint32_t id_mmfr0; 944 uint32_t id_mmfr1; 945 uint32_t id_mmfr2; 946 uint32_t id_mmfr3; 947 uint32_t id_mmfr4; 948 uint32_t id_pfr0; 949 uint32_t id_pfr1; 950 uint32_t id_pfr2; 951 uint32_t mvfr0; 952 uint32_t mvfr1; 953 uint32_t mvfr2; 954 uint32_t id_dfr0; 955 uint32_t dbgdidr; 956 uint64_t id_aa64isar0; 957 uint64_t id_aa64isar1; 958 uint64_t id_aa64pfr0; 959 uint64_t id_aa64pfr1; 960 uint64_t id_aa64mmfr0; 961 uint64_t id_aa64mmfr1; 962 uint64_t id_aa64mmfr2; 963 uint64_t id_aa64dfr0; 964 uint64_t id_aa64dfr1; 965 uint64_t id_aa64zfr0; 966 } isar; 967 uint64_t midr; 968 uint32_t revidr; 969 uint32_t reset_fpsid; 970 uint64_t ctr; 971 uint32_t reset_sctlr; 972 uint64_t pmceid0; 973 uint64_t pmceid1; 974 uint32_t id_afr0; 975 uint64_t id_aa64afr0; 976 uint64_t id_aa64afr1; 977 uint64_t clidr; 978 uint64_t mp_affinity; /* MP ID without feature bits */ 979 /* The elements of this array are the CCSIDR values for each cache, 980 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 981 */ 982 uint64_t ccsidr[16]; 983 uint64_t reset_cbar; 984 uint32_t reset_auxcr; 985 bool reset_hivecs; 986 987 /* 988 * Intermediate values used during property parsing. 989 * Once finalized, the values should be read from ID_AA64*. 990 */ 991 bool prop_pauth; 992 bool prop_pauth_impdef; 993 bool prop_lpa2; 994 995 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 996 uint32_t dcz_blocksize; 997 uint64_t rvbar_prop; /* Property/input signals. */ 998 999 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1000 int gic_num_lrs; /* number of list registers */ 1001 int gic_vpribits; /* number of virtual priority bits */ 1002 int gic_vprebits; /* number of virtual preemption bits */ 1003 1004 /* Whether the cfgend input is high (i.e. this CPU should reset into 1005 * big-endian mode). This setting isn't used directly: instead it modifies 1006 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1007 * architecture version. 1008 */ 1009 bool cfgend; 1010 1011 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1012 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1013 1014 int32_t node_id; /* NUMA node this CPU belongs to */ 1015 1016 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1017 uint8_t device_irq_level; 1018 1019 /* Used to set the maximum vector length the cpu will support. */ 1020 uint32_t sve_max_vq; 1021 1022 #ifdef CONFIG_USER_ONLY 1023 /* Used to set the default vector length at process start. */ 1024 uint32_t sve_default_vq; 1025 #endif 1026 1027 /* 1028 * In sve_vq_map each set bit is a supported vector length of 1029 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 1030 * length in quadwords. 1031 * 1032 * While processing properties during initialization, corresponding 1033 * sve_vq_init bits are set for bits in sve_vq_map that have been 1034 * set by properties. 1035 * 1036 * Bits set in sve_vq_supported represent valid vector lengths for 1037 * the CPU type. 1038 */ 1039 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 1040 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 1041 DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ); 1042 1043 /* Generic timer counter frequency, in Hz */ 1044 uint64_t gt_cntfrq_hz; 1045 }; 1046 1047 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1048 1049 void arm_cpu_post_init(Object *obj); 1050 1051 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1052 1053 #ifndef CONFIG_USER_ONLY 1054 extern const VMStateDescription vmstate_arm_cpu; 1055 1056 void arm_cpu_do_interrupt(CPUState *cpu); 1057 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1058 #endif /* !CONFIG_USER_ONLY */ 1059 1060 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1061 MemTxAttrs *attrs); 1062 1063 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1064 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1065 1066 /* 1067 * Helpers to dynamically generates XML descriptions of the sysregs 1068 * and SVE registers. Returns the number of registers in each set. 1069 */ 1070 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1071 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1072 1073 /* Returns the dynamically generated XML for the gdb stub. 1074 * Returns a pointer to the XML contents for the specified XML file or NULL 1075 * if the XML name doesn't match the predefined one. 1076 */ 1077 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1078 1079 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1080 int cpuid, void *opaque); 1081 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1082 int cpuid, void *opaque); 1083 1084 #ifdef TARGET_AARCH64 1085 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1086 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1087 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1088 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1089 int new_el, bool el0_a64); 1090 void aarch64_add_sve_properties(Object *obj); 1091 void aarch64_add_pauth_properties(Object *obj); 1092 1093 /* 1094 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1095 * The byte at offset i from the start of the in-memory representation contains 1096 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1097 * lowest offsets are stored in the lowest memory addresses, then that nearly 1098 * matches QEMU's representation, which is to use an array of host-endian 1099 * uint64_t's, where the lower offsets are at the lower indices. To complete 1100 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1101 */ 1102 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1103 { 1104 #if HOST_BIG_ENDIAN 1105 int i; 1106 1107 for (i = 0; i < nr; ++i) { 1108 dst[i] = bswap64(src[i]); 1109 } 1110 1111 return dst; 1112 #else 1113 return src; 1114 #endif 1115 } 1116 1117 #else 1118 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1119 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1120 int n, bool a) 1121 { } 1122 static inline void aarch64_add_sve_properties(Object *obj) { } 1123 #endif 1124 1125 void aarch64_sync_32_to_64(CPUARMState *env); 1126 void aarch64_sync_64_to_32(CPUARMState *env); 1127 1128 int fp_exception_el(CPUARMState *env, int cur_el); 1129 int sve_exception_el(CPUARMState *env, int cur_el); 1130 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1131 1132 static inline bool is_a64(CPUARMState *env) 1133 { 1134 return env->aarch64; 1135 } 1136 1137 /** 1138 * pmu_op_start/finish 1139 * @env: CPUARMState 1140 * 1141 * Convert all PMU counters between their delta form (the typical mode when 1142 * they are enabled) and the guest-visible values. These two calls must 1143 * surround any action which might affect the counters. 1144 */ 1145 void pmu_op_start(CPUARMState *env); 1146 void pmu_op_finish(CPUARMState *env); 1147 1148 /* 1149 * Called when a PMU counter is due to overflow 1150 */ 1151 void arm_pmu_timer_cb(void *opaque); 1152 1153 /** 1154 * Functions to register as EL change hooks for PMU mode filtering 1155 */ 1156 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1157 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1158 1159 /* 1160 * pmu_init 1161 * @cpu: ARMCPU 1162 * 1163 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1164 * for the current configuration 1165 */ 1166 void pmu_init(ARMCPU *cpu); 1167 1168 /* SCTLR bit meanings. Several bits have been reused in newer 1169 * versions of the architecture; in that case we define constants 1170 * for both old and new bit meanings. Code which tests against those 1171 * bits should probably check or otherwise arrange that the CPU 1172 * is the architectural version it expects. 1173 */ 1174 #define SCTLR_M (1U << 0) 1175 #define SCTLR_A (1U << 1) 1176 #define SCTLR_C (1U << 2) 1177 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1178 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1179 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1180 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1181 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1182 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1183 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1184 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1185 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1186 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1187 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1188 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1189 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1190 #define SCTLR_SED (1U << 8) /* v8 onward */ 1191 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1192 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1193 #define SCTLR_F (1U << 10) /* up to v6 */ 1194 #define SCTLR_SW (1U << 10) /* v7 */ 1195 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1196 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1197 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1198 #define SCTLR_I (1U << 12) 1199 #define SCTLR_V (1U << 13) /* AArch32 only */ 1200 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1201 #define SCTLR_RR (1U << 14) /* up to v7 */ 1202 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1203 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1204 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1205 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1206 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1207 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1208 #define SCTLR_BR (1U << 17) /* PMSA only */ 1209 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1210 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1211 #define SCTLR_WXN (1U << 19) 1212 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1213 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1214 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1215 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1216 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1217 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1218 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1219 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1220 #define SCTLR_VE (1U << 24) /* up to v7 */ 1221 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1222 #define SCTLR_EE (1U << 25) 1223 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1224 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1225 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1226 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1227 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1228 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1229 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1230 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1231 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1232 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1233 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1234 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1235 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1236 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1237 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1238 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1239 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1240 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1241 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1242 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1243 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1244 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1245 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1246 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1247 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1248 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1249 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1250 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1251 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1252 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1253 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1254 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1255 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1256 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1257 1258 #define CPTR_TCPAC (1U << 31) 1259 #define CPTR_TTA (1U << 20) 1260 #define CPTR_TFP (1U << 10) 1261 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1262 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1263 1264 #define MDCR_EPMAD (1U << 21) 1265 #define MDCR_EDAD (1U << 20) 1266 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1267 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1268 #define MDCR_SDD (1U << 16) 1269 #define MDCR_SPD (3U << 14) 1270 #define MDCR_TDRA (1U << 11) 1271 #define MDCR_TDOSA (1U << 10) 1272 #define MDCR_TDA (1U << 9) 1273 #define MDCR_TDE (1U << 8) 1274 #define MDCR_HPME (1U << 7) 1275 #define MDCR_TPM (1U << 6) 1276 #define MDCR_TPMCR (1U << 5) 1277 #define MDCR_HPMN (0x1fU) 1278 1279 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1280 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1281 1282 #define CPSR_M (0x1fU) 1283 #define CPSR_T (1U << 5) 1284 #define CPSR_F (1U << 6) 1285 #define CPSR_I (1U << 7) 1286 #define CPSR_A (1U << 8) 1287 #define CPSR_E (1U << 9) 1288 #define CPSR_IT_2_7 (0xfc00U) 1289 #define CPSR_GE (0xfU << 16) 1290 #define CPSR_IL (1U << 20) 1291 #define CPSR_DIT (1U << 21) 1292 #define CPSR_PAN (1U << 22) 1293 #define CPSR_SSBS (1U << 23) 1294 #define CPSR_J (1U << 24) 1295 #define CPSR_IT_0_1 (3U << 25) 1296 #define CPSR_Q (1U << 27) 1297 #define CPSR_V (1U << 28) 1298 #define CPSR_C (1U << 29) 1299 #define CPSR_Z (1U << 30) 1300 #define CPSR_N (1U << 31) 1301 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1302 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1303 1304 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1305 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1306 | CPSR_NZCV) 1307 /* Bits writable in user mode. */ 1308 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1309 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1310 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1311 1312 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1313 #define XPSR_EXCP 0x1ffU 1314 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1315 #define XPSR_IT_2_7 CPSR_IT_2_7 1316 #define XPSR_GE CPSR_GE 1317 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1318 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1319 #define XPSR_IT_0_1 CPSR_IT_0_1 1320 #define XPSR_Q CPSR_Q 1321 #define XPSR_V CPSR_V 1322 #define XPSR_C CPSR_C 1323 #define XPSR_Z CPSR_Z 1324 #define XPSR_N CPSR_N 1325 #define XPSR_NZCV CPSR_NZCV 1326 #define XPSR_IT CPSR_IT 1327 1328 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1329 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1330 #define TTBCR_PD0 (1U << 4) 1331 #define TTBCR_PD1 (1U << 5) 1332 #define TTBCR_EPD0 (1U << 7) 1333 #define TTBCR_IRGN0 (3U << 8) 1334 #define TTBCR_ORGN0 (3U << 10) 1335 #define TTBCR_SH0 (3U << 12) 1336 #define TTBCR_T1SZ (3U << 16) 1337 #define TTBCR_A1 (1U << 22) 1338 #define TTBCR_EPD1 (1U << 23) 1339 #define TTBCR_IRGN1 (3U << 24) 1340 #define TTBCR_ORGN1 (3U << 26) 1341 #define TTBCR_SH1 (1U << 28) 1342 #define TTBCR_EAE (1U << 31) 1343 1344 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1345 * Only these are valid when in AArch64 mode; in 1346 * AArch32 mode SPSRs are basically CPSR-format. 1347 */ 1348 #define PSTATE_SP (1U) 1349 #define PSTATE_M (0xFU) 1350 #define PSTATE_nRW (1U << 4) 1351 #define PSTATE_F (1U << 6) 1352 #define PSTATE_I (1U << 7) 1353 #define PSTATE_A (1U << 8) 1354 #define PSTATE_D (1U << 9) 1355 #define PSTATE_BTYPE (3U << 10) 1356 #define PSTATE_SSBS (1U << 12) 1357 #define PSTATE_IL (1U << 20) 1358 #define PSTATE_SS (1U << 21) 1359 #define PSTATE_PAN (1U << 22) 1360 #define PSTATE_UAO (1U << 23) 1361 #define PSTATE_DIT (1U << 24) 1362 #define PSTATE_TCO (1U << 25) 1363 #define PSTATE_V (1U << 28) 1364 #define PSTATE_C (1U << 29) 1365 #define PSTATE_Z (1U << 30) 1366 #define PSTATE_N (1U << 31) 1367 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1368 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1369 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1370 /* Mode values for AArch64 */ 1371 #define PSTATE_MODE_EL3h 13 1372 #define PSTATE_MODE_EL3t 12 1373 #define PSTATE_MODE_EL2h 9 1374 #define PSTATE_MODE_EL2t 8 1375 #define PSTATE_MODE_EL1h 5 1376 #define PSTATE_MODE_EL1t 4 1377 #define PSTATE_MODE_EL0t 0 1378 1379 /* Write a new value to v7m.exception, thus transitioning into or out 1380 * of Handler mode; this may result in a change of active stack pointer. 1381 */ 1382 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1383 1384 /* Map EL and handler into a PSTATE_MODE. */ 1385 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1386 { 1387 return (el << 2) | handler; 1388 } 1389 1390 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1391 * interprocessing, so we don't attempt to sync with the cpsr state used by 1392 * the 32 bit decoder. 1393 */ 1394 static inline uint32_t pstate_read(CPUARMState *env) 1395 { 1396 int ZF; 1397 1398 ZF = (env->ZF == 0); 1399 return (env->NF & 0x80000000) | (ZF << 30) 1400 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1401 | env->pstate | env->daif | (env->btype << 10); 1402 } 1403 1404 static inline void pstate_write(CPUARMState *env, uint32_t val) 1405 { 1406 env->ZF = (~val) & PSTATE_Z; 1407 env->NF = val; 1408 env->CF = (val >> 29) & 1; 1409 env->VF = (val << 3) & 0x80000000; 1410 env->daif = val & PSTATE_DAIF; 1411 env->btype = (val >> 10) & 3; 1412 env->pstate = val & ~CACHED_PSTATE_BITS; 1413 } 1414 1415 /* Return the current CPSR value. */ 1416 uint32_t cpsr_read(CPUARMState *env); 1417 1418 typedef enum CPSRWriteType { 1419 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1420 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1421 CPSRWriteRaw = 2, 1422 /* trust values, no reg bank switch, no hflags rebuild */ 1423 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1424 } CPSRWriteType; 1425 1426 /* 1427 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1428 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1429 * correspond to TB flags bits cached in the hflags, unless @write_type 1430 * is CPSRWriteRaw. 1431 */ 1432 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1433 CPSRWriteType write_type); 1434 1435 /* Return the current xPSR value. */ 1436 static inline uint32_t xpsr_read(CPUARMState *env) 1437 { 1438 int ZF; 1439 ZF = (env->ZF == 0); 1440 return (env->NF & 0x80000000) | (ZF << 30) 1441 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1442 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1443 | ((env->condexec_bits & 0xfc) << 8) 1444 | (env->GE << 16) 1445 | env->v7m.exception; 1446 } 1447 1448 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1449 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1450 { 1451 if (mask & XPSR_NZCV) { 1452 env->ZF = (~val) & XPSR_Z; 1453 env->NF = val; 1454 env->CF = (val >> 29) & 1; 1455 env->VF = (val << 3) & 0x80000000; 1456 } 1457 if (mask & XPSR_Q) { 1458 env->QF = ((val & XPSR_Q) != 0); 1459 } 1460 if (mask & XPSR_GE) { 1461 env->GE = (val & XPSR_GE) >> 16; 1462 } 1463 #ifndef CONFIG_USER_ONLY 1464 if (mask & XPSR_T) { 1465 env->thumb = ((val & XPSR_T) != 0); 1466 } 1467 if (mask & XPSR_IT_0_1) { 1468 env->condexec_bits &= ~3; 1469 env->condexec_bits |= (val >> 25) & 3; 1470 } 1471 if (mask & XPSR_IT_2_7) { 1472 env->condexec_bits &= 3; 1473 env->condexec_bits |= (val >> 8) & 0xfc; 1474 } 1475 if (mask & XPSR_EXCP) { 1476 /* Note that this only happens on exception exit */ 1477 write_v7m_exception(env, val & XPSR_EXCP); 1478 } 1479 #endif 1480 } 1481 1482 #define HCR_VM (1ULL << 0) 1483 #define HCR_SWIO (1ULL << 1) 1484 #define HCR_PTW (1ULL << 2) 1485 #define HCR_FMO (1ULL << 3) 1486 #define HCR_IMO (1ULL << 4) 1487 #define HCR_AMO (1ULL << 5) 1488 #define HCR_VF (1ULL << 6) 1489 #define HCR_VI (1ULL << 7) 1490 #define HCR_VSE (1ULL << 8) 1491 #define HCR_FB (1ULL << 9) 1492 #define HCR_BSU_MASK (3ULL << 10) 1493 #define HCR_DC (1ULL << 12) 1494 #define HCR_TWI (1ULL << 13) 1495 #define HCR_TWE (1ULL << 14) 1496 #define HCR_TID0 (1ULL << 15) 1497 #define HCR_TID1 (1ULL << 16) 1498 #define HCR_TID2 (1ULL << 17) 1499 #define HCR_TID3 (1ULL << 18) 1500 #define HCR_TSC (1ULL << 19) 1501 #define HCR_TIDCP (1ULL << 20) 1502 #define HCR_TACR (1ULL << 21) 1503 #define HCR_TSW (1ULL << 22) 1504 #define HCR_TPCP (1ULL << 23) 1505 #define HCR_TPU (1ULL << 24) 1506 #define HCR_TTLB (1ULL << 25) 1507 #define HCR_TVM (1ULL << 26) 1508 #define HCR_TGE (1ULL << 27) 1509 #define HCR_TDZ (1ULL << 28) 1510 #define HCR_HCD (1ULL << 29) 1511 #define HCR_TRVM (1ULL << 30) 1512 #define HCR_RW (1ULL << 31) 1513 #define HCR_CD (1ULL << 32) 1514 #define HCR_ID (1ULL << 33) 1515 #define HCR_E2H (1ULL << 34) 1516 #define HCR_TLOR (1ULL << 35) 1517 #define HCR_TERR (1ULL << 36) 1518 #define HCR_TEA (1ULL << 37) 1519 #define HCR_MIOCNCE (1ULL << 38) 1520 /* RES0 bit 39 */ 1521 #define HCR_APK (1ULL << 40) 1522 #define HCR_API (1ULL << 41) 1523 #define HCR_NV (1ULL << 42) 1524 #define HCR_NV1 (1ULL << 43) 1525 #define HCR_AT (1ULL << 44) 1526 #define HCR_NV2 (1ULL << 45) 1527 #define HCR_FWB (1ULL << 46) 1528 #define HCR_FIEN (1ULL << 47) 1529 /* RES0 bit 48 */ 1530 #define HCR_TID4 (1ULL << 49) 1531 #define HCR_TICAB (1ULL << 50) 1532 #define HCR_AMVOFFEN (1ULL << 51) 1533 #define HCR_TOCU (1ULL << 52) 1534 #define HCR_ENSCXT (1ULL << 53) 1535 #define HCR_TTLBIS (1ULL << 54) 1536 #define HCR_TTLBOS (1ULL << 55) 1537 #define HCR_ATA (1ULL << 56) 1538 #define HCR_DCT (1ULL << 57) 1539 #define HCR_TID5 (1ULL << 58) 1540 #define HCR_TWEDEN (1ULL << 59) 1541 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1542 1543 #define HPFAR_NS (1ULL << 63) 1544 1545 #define SCR_NS (1U << 0) 1546 #define SCR_IRQ (1U << 1) 1547 #define SCR_FIQ (1U << 2) 1548 #define SCR_EA (1U << 3) 1549 #define SCR_FW (1U << 4) 1550 #define SCR_AW (1U << 5) 1551 #define SCR_NET (1U << 6) 1552 #define SCR_SMD (1U << 7) 1553 #define SCR_HCE (1U << 8) 1554 #define SCR_SIF (1U << 9) 1555 #define SCR_RW (1U << 10) 1556 #define SCR_ST (1U << 11) 1557 #define SCR_TWI (1U << 12) 1558 #define SCR_TWE (1U << 13) 1559 #define SCR_TLOR (1U << 14) 1560 #define SCR_TERR (1U << 15) 1561 #define SCR_APK (1U << 16) 1562 #define SCR_API (1U << 17) 1563 #define SCR_EEL2 (1U << 18) 1564 #define SCR_EASE (1U << 19) 1565 #define SCR_NMEA (1U << 20) 1566 #define SCR_FIEN (1U << 21) 1567 #define SCR_ENSCXT (1U << 25) 1568 #define SCR_ATA (1U << 26) 1569 #define SCR_FGTEN (1U << 27) 1570 #define SCR_ECVEN (1U << 28) 1571 #define SCR_TWEDEN (1U << 29) 1572 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1573 #define SCR_TME (1ULL << 34) 1574 #define SCR_AMVOFFEN (1ULL << 35) 1575 #define SCR_ENAS0 (1ULL << 36) 1576 #define SCR_ADEN (1ULL << 37) 1577 #define SCR_HXEN (1ULL << 38) 1578 #define SCR_TRNDR (1ULL << 40) 1579 #define SCR_ENTP2 (1ULL << 41) 1580 #define SCR_GPF (1ULL << 48) 1581 1582 #define HSTR_TTEE (1 << 16) 1583 #define HSTR_TJDBX (1 << 17) 1584 1585 /* Return the current FPSCR value. */ 1586 uint32_t vfp_get_fpscr(CPUARMState *env); 1587 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1588 1589 /* FPCR, Floating Point Control Register 1590 * FPSR, Floating Poiht Status Register 1591 * 1592 * For A64 the FPSCR is split into two logically distinct registers, 1593 * FPCR and FPSR. However since they still use non-overlapping bits 1594 * we store the underlying state in fpscr and just mask on read/write. 1595 */ 1596 #define FPSR_MASK 0xf800009f 1597 #define FPCR_MASK 0x07ff9f00 1598 1599 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1600 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1601 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1602 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1603 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1604 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1605 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1606 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1607 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1608 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1609 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1610 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1611 #define FPCR_V (1 << 28) /* FP overflow flag */ 1612 #define FPCR_C (1 << 29) /* FP carry flag */ 1613 #define FPCR_Z (1 << 30) /* FP zero flag */ 1614 #define FPCR_N (1 << 31) /* FP negative flag */ 1615 1616 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1617 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1618 #define FPCR_LTPSIZE_LENGTH 3 1619 1620 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1621 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1622 1623 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1624 { 1625 return vfp_get_fpscr(env) & FPSR_MASK; 1626 } 1627 1628 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1629 { 1630 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1631 vfp_set_fpscr(env, new_fpscr); 1632 } 1633 1634 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1635 { 1636 return vfp_get_fpscr(env) & FPCR_MASK; 1637 } 1638 1639 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1640 { 1641 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1642 vfp_set_fpscr(env, new_fpscr); 1643 } 1644 1645 enum arm_cpu_mode { 1646 ARM_CPU_MODE_USR = 0x10, 1647 ARM_CPU_MODE_FIQ = 0x11, 1648 ARM_CPU_MODE_IRQ = 0x12, 1649 ARM_CPU_MODE_SVC = 0x13, 1650 ARM_CPU_MODE_MON = 0x16, 1651 ARM_CPU_MODE_ABT = 0x17, 1652 ARM_CPU_MODE_HYP = 0x1a, 1653 ARM_CPU_MODE_UND = 0x1b, 1654 ARM_CPU_MODE_SYS = 0x1f 1655 }; 1656 1657 /* VFP system registers. */ 1658 #define ARM_VFP_FPSID 0 1659 #define ARM_VFP_FPSCR 1 1660 #define ARM_VFP_MVFR2 5 1661 #define ARM_VFP_MVFR1 6 1662 #define ARM_VFP_MVFR0 7 1663 #define ARM_VFP_FPEXC 8 1664 #define ARM_VFP_FPINST 9 1665 #define ARM_VFP_FPINST2 10 1666 /* These ones are M-profile only */ 1667 #define ARM_VFP_FPSCR_NZCVQC 2 1668 #define ARM_VFP_VPR 12 1669 #define ARM_VFP_P0 13 1670 #define ARM_VFP_FPCXT_NS 14 1671 #define ARM_VFP_FPCXT_S 15 1672 1673 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1674 #define QEMU_VFP_FPSCR_NZCV 0xffff 1675 1676 /* iwMMXt coprocessor control registers. */ 1677 #define ARM_IWMMXT_wCID 0 1678 #define ARM_IWMMXT_wCon 1 1679 #define ARM_IWMMXT_wCSSF 2 1680 #define ARM_IWMMXT_wCASF 3 1681 #define ARM_IWMMXT_wCGR0 8 1682 #define ARM_IWMMXT_wCGR1 9 1683 #define ARM_IWMMXT_wCGR2 10 1684 #define ARM_IWMMXT_wCGR3 11 1685 1686 /* V7M CCR bits */ 1687 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1688 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1689 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1690 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1691 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1692 FIELD(V7M_CCR, STKALIGN, 9, 1) 1693 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1694 FIELD(V7M_CCR, DC, 16, 1) 1695 FIELD(V7M_CCR, IC, 17, 1) 1696 FIELD(V7M_CCR, BP, 18, 1) 1697 FIELD(V7M_CCR, LOB, 19, 1) 1698 FIELD(V7M_CCR, TRD, 20, 1) 1699 1700 /* V7M SCR bits */ 1701 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1702 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1703 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1704 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1705 1706 /* V7M AIRCR bits */ 1707 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1708 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1709 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1710 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1711 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1712 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1713 FIELD(V7M_AIRCR, PRIS, 14, 1) 1714 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1715 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1716 1717 /* V7M CFSR bits for MMFSR */ 1718 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1719 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1720 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1721 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1722 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1723 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1724 1725 /* V7M CFSR bits for BFSR */ 1726 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1727 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1728 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1729 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1730 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1731 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1732 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1733 1734 /* V7M CFSR bits for UFSR */ 1735 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1736 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1737 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1738 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1739 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1740 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1741 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1742 1743 /* V7M CFSR bit masks covering all of the subregister bits */ 1744 FIELD(V7M_CFSR, MMFSR, 0, 8) 1745 FIELD(V7M_CFSR, BFSR, 8, 8) 1746 FIELD(V7M_CFSR, UFSR, 16, 16) 1747 1748 /* V7M HFSR bits */ 1749 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1750 FIELD(V7M_HFSR, FORCED, 30, 1) 1751 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1752 1753 /* V7M DFSR bits */ 1754 FIELD(V7M_DFSR, HALTED, 0, 1) 1755 FIELD(V7M_DFSR, BKPT, 1, 1) 1756 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1757 FIELD(V7M_DFSR, VCATCH, 3, 1) 1758 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1759 1760 /* V7M SFSR bits */ 1761 FIELD(V7M_SFSR, INVEP, 0, 1) 1762 FIELD(V7M_SFSR, INVIS, 1, 1) 1763 FIELD(V7M_SFSR, INVER, 2, 1) 1764 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1765 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1766 FIELD(V7M_SFSR, LSPERR, 5, 1) 1767 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1768 FIELD(V7M_SFSR, LSERR, 7, 1) 1769 1770 /* v7M MPU_CTRL bits */ 1771 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1772 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1773 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1774 1775 /* v7M CLIDR bits */ 1776 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1777 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1778 FIELD(V7M_CLIDR, LOC, 24, 3) 1779 FIELD(V7M_CLIDR, LOUU, 27, 3) 1780 FIELD(V7M_CLIDR, ICB, 30, 2) 1781 1782 FIELD(V7M_CSSELR, IND, 0, 1) 1783 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1784 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1785 * define a mask for this and check that it doesn't permit running off 1786 * the end of the array. 1787 */ 1788 FIELD(V7M_CSSELR, INDEX, 0, 4) 1789 1790 /* v7M FPCCR bits */ 1791 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1792 FIELD(V7M_FPCCR, USER, 1, 1) 1793 FIELD(V7M_FPCCR, S, 2, 1) 1794 FIELD(V7M_FPCCR, THREAD, 3, 1) 1795 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1796 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1797 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1798 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1799 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1800 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1801 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1802 FIELD(V7M_FPCCR, RES0, 11, 15) 1803 FIELD(V7M_FPCCR, TS, 26, 1) 1804 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1805 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1806 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1807 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1808 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1809 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1810 #define R_V7M_FPCCR_BANKED_MASK \ 1811 (R_V7M_FPCCR_LSPACT_MASK | \ 1812 R_V7M_FPCCR_USER_MASK | \ 1813 R_V7M_FPCCR_THREAD_MASK | \ 1814 R_V7M_FPCCR_MMRDY_MASK | \ 1815 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1816 R_V7M_FPCCR_UFRDY_MASK | \ 1817 R_V7M_FPCCR_ASPEN_MASK) 1818 1819 /* v7M VPR bits */ 1820 FIELD(V7M_VPR, P0, 0, 16) 1821 FIELD(V7M_VPR, MASK01, 16, 4) 1822 FIELD(V7M_VPR, MASK23, 20, 4) 1823 1824 /* 1825 * System register ID fields. 1826 */ 1827 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1828 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1829 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1830 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1831 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1832 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1833 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1834 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1835 FIELD(CLIDR_EL1, LOC, 24, 3) 1836 FIELD(CLIDR_EL1, LOUU, 27, 3) 1837 FIELD(CLIDR_EL1, ICB, 30, 3) 1838 1839 /* When FEAT_CCIDX is implemented */ 1840 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1841 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1842 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1843 1844 /* When FEAT_CCIDX is not implemented */ 1845 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1846 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1847 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1848 1849 FIELD(CTR_EL0, IMINLINE, 0, 4) 1850 FIELD(CTR_EL0, L1IP, 14, 2) 1851 FIELD(CTR_EL0, DMINLINE, 16, 4) 1852 FIELD(CTR_EL0, ERG, 20, 4) 1853 FIELD(CTR_EL0, CWG, 24, 4) 1854 FIELD(CTR_EL0, IDC, 28, 1) 1855 FIELD(CTR_EL0, DIC, 29, 1) 1856 FIELD(CTR_EL0, TMINLINE, 32, 6) 1857 1858 FIELD(MIDR_EL1, REVISION, 0, 4) 1859 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1860 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1861 FIELD(MIDR_EL1, VARIANT, 20, 4) 1862 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1863 1864 FIELD(ID_ISAR0, SWAP, 0, 4) 1865 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1866 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1867 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1868 FIELD(ID_ISAR0, COPROC, 16, 4) 1869 FIELD(ID_ISAR0, DEBUG, 20, 4) 1870 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1871 1872 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1873 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1874 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1875 FIELD(ID_ISAR1, EXTEND, 12, 4) 1876 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1877 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1878 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1879 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1880 1881 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1882 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1883 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1884 FIELD(ID_ISAR2, MULT, 12, 4) 1885 FIELD(ID_ISAR2, MULTS, 16, 4) 1886 FIELD(ID_ISAR2, MULTU, 20, 4) 1887 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1888 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1889 1890 FIELD(ID_ISAR3, SATURATE, 0, 4) 1891 FIELD(ID_ISAR3, SIMD, 4, 4) 1892 FIELD(ID_ISAR3, SVC, 8, 4) 1893 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1894 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1895 FIELD(ID_ISAR3, T32COPY, 20, 4) 1896 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1897 FIELD(ID_ISAR3, T32EE, 28, 4) 1898 1899 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1900 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1901 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1902 FIELD(ID_ISAR4, SMC, 12, 4) 1903 FIELD(ID_ISAR4, BARRIER, 16, 4) 1904 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1905 FIELD(ID_ISAR4, PSR_M, 24, 4) 1906 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1907 1908 FIELD(ID_ISAR5, SEVL, 0, 4) 1909 FIELD(ID_ISAR5, AES, 4, 4) 1910 FIELD(ID_ISAR5, SHA1, 8, 4) 1911 FIELD(ID_ISAR5, SHA2, 12, 4) 1912 FIELD(ID_ISAR5, CRC32, 16, 4) 1913 FIELD(ID_ISAR5, RDM, 24, 4) 1914 FIELD(ID_ISAR5, VCMA, 28, 4) 1915 1916 FIELD(ID_ISAR6, JSCVT, 0, 4) 1917 FIELD(ID_ISAR6, DP, 4, 4) 1918 FIELD(ID_ISAR6, FHM, 8, 4) 1919 FIELD(ID_ISAR6, SB, 12, 4) 1920 FIELD(ID_ISAR6, SPECRES, 16, 4) 1921 FIELD(ID_ISAR6, BF16, 20, 4) 1922 FIELD(ID_ISAR6, I8MM, 24, 4) 1923 1924 FIELD(ID_MMFR0, VMSA, 0, 4) 1925 FIELD(ID_MMFR0, PMSA, 4, 4) 1926 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 1927 FIELD(ID_MMFR0, SHARELVL, 12, 4) 1928 FIELD(ID_MMFR0, TCM, 16, 4) 1929 FIELD(ID_MMFR0, AUXREG, 20, 4) 1930 FIELD(ID_MMFR0, FCSE, 24, 4) 1931 FIELD(ID_MMFR0, INNERSHR, 28, 4) 1932 1933 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 1934 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 1935 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 1936 FIELD(ID_MMFR1, L1UNISW, 12, 4) 1937 FIELD(ID_MMFR1, L1HVD, 16, 4) 1938 FIELD(ID_MMFR1, L1UNI, 20, 4) 1939 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 1940 FIELD(ID_MMFR1, BPRED, 28, 4) 1941 1942 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 1943 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 1944 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 1945 FIELD(ID_MMFR2, HVDTLB, 12, 4) 1946 FIELD(ID_MMFR2, UNITLB, 16, 4) 1947 FIELD(ID_MMFR2, MEMBARR, 20, 4) 1948 FIELD(ID_MMFR2, WFISTALL, 24, 4) 1949 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 1950 1951 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 1952 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 1953 FIELD(ID_MMFR3, BPMAINT, 8, 4) 1954 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 1955 FIELD(ID_MMFR3, PAN, 16, 4) 1956 FIELD(ID_MMFR3, COHWALK, 20, 4) 1957 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 1958 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 1959 1960 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1961 FIELD(ID_MMFR4, AC2, 4, 4) 1962 FIELD(ID_MMFR4, XNX, 8, 4) 1963 FIELD(ID_MMFR4, CNP, 12, 4) 1964 FIELD(ID_MMFR4, HPDS, 16, 4) 1965 FIELD(ID_MMFR4, LSM, 20, 4) 1966 FIELD(ID_MMFR4, CCIDX, 24, 4) 1967 FIELD(ID_MMFR4, EVT, 28, 4) 1968 1969 FIELD(ID_MMFR5, ETS, 0, 4) 1970 FIELD(ID_MMFR5, NTLBPA, 4, 4) 1971 1972 FIELD(ID_PFR0, STATE0, 0, 4) 1973 FIELD(ID_PFR0, STATE1, 4, 4) 1974 FIELD(ID_PFR0, STATE2, 8, 4) 1975 FIELD(ID_PFR0, STATE3, 12, 4) 1976 FIELD(ID_PFR0, CSV2, 16, 4) 1977 FIELD(ID_PFR0, AMU, 20, 4) 1978 FIELD(ID_PFR0, DIT, 24, 4) 1979 FIELD(ID_PFR0, RAS, 28, 4) 1980 1981 FIELD(ID_PFR1, PROGMOD, 0, 4) 1982 FIELD(ID_PFR1, SECURITY, 4, 4) 1983 FIELD(ID_PFR1, MPROGMOD, 8, 4) 1984 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 1985 FIELD(ID_PFR1, GENTIMER, 16, 4) 1986 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 1987 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 1988 FIELD(ID_PFR1, GIC, 28, 4) 1989 1990 FIELD(ID_PFR2, CSV3, 0, 4) 1991 FIELD(ID_PFR2, SSBS, 4, 4) 1992 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 1993 1994 FIELD(ID_AA64ISAR0, AES, 4, 4) 1995 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1996 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1997 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1998 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1999 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2000 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2001 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2002 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2003 FIELD(ID_AA64ISAR0, DP, 44, 4) 2004 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2005 FIELD(ID_AA64ISAR0, TS, 52, 4) 2006 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2007 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2008 2009 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2010 FIELD(ID_AA64ISAR1, APA, 4, 4) 2011 FIELD(ID_AA64ISAR1, API, 8, 4) 2012 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2013 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2014 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2015 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2016 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2017 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2018 FIELD(ID_AA64ISAR1, SB, 36, 4) 2019 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2020 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2021 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2022 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2023 FIELD(ID_AA64ISAR1, XS, 56, 4) 2024 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2025 2026 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2027 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2028 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2029 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2030 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2031 FIELD(ID_AA64ISAR2, BC, 20, 4) 2032 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2033 2034 FIELD(ID_AA64PFR0, EL0, 0, 4) 2035 FIELD(ID_AA64PFR0, EL1, 4, 4) 2036 FIELD(ID_AA64PFR0, EL2, 8, 4) 2037 FIELD(ID_AA64PFR0, EL3, 12, 4) 2038 FIELD(ID_AA64PFR0, FP, 16, 4) 2039 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2040 FIELD(ID_AA64PFR0, GIC, 24, 4) 2041 FIELD(ID_AA64PFR0, RAS, 28, 4) 2042 FIELD(ID_AA64PFR0, SVE, 32, 4) 2043 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2044 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2045 FIELD(ID_AA64PFR0, AMU, 44, 4) 2046 FIELD(ID_AA64PFR0, DIT, 48, 4) 2047 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2048 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2049 2050 FIELD(ID_AA64PFR1, BT, 0, 4) 2051 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2052 FIELD(ID_AA64PFR1, MTE, 8, 4) 2053 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2054 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2055 FIELD(ID_AA64PFR1, SME, 24, 4) 2056 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2057 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2058 FIELD(ID_AA64PFR1, NMI, 36, 4) 2059 2060 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2061 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2062 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2063 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2064 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2065 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2066 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2067 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2068 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2069 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2070 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2071 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2072 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2073 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2074 2075 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2076 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2077 FIELD(ID_AA64MMFR1, VH, 8, 4) 2078 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2079 FIELD(ID_AA64MMFR1, LO, 16, 4) 2080 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2081 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2082 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2083 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2084 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2085 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2086 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2087 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2088 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2089 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2090 2091 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2092 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2093 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2094 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2095 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2096 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2097 FIELD(ID_AA64MMFR2, NV, 24, 4) 2098 FIELD(ID_AA64MMFR2, ST, 28, 4) 2099 FIELD(ID_AA64MMFR2, AT, 32, 4) 2100 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2101 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2102 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2103 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2104 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2105 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2106 2107 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2108 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2109 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2110 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2111 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2112 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2113 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2114 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2115 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2116 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2117 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2118 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2119 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2120 2121 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2122 FIELD(ID_AA64ZFR0, AES, 4, 4) 2123 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2124 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2125 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2126 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2127 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2128 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2129 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2130 2131 FIELD(ID_DFR0, COPDBG, 0, 4) 2132 FIELD(ID_DFR0, COPSDBG, 4, 4) 2133 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2134 FIELD(ID_DFR0, COPTRC, 12, 4) 2135 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2136 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2137 FIELD(ID_DFR0, PERFMON, 24, 4) 2138 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2139 2140 FIELD(ID_DFR1, MTPMU, 0, 4) 2141 FIELD(ID_DFR1, HPMN0, 4, 4) 2142 2143 FIELD(DBGDIDR, SE_IMP, 12, 1) 2144 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2145 FIELD(DBGDIDR, VERSION, 16, 4) 2146 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2147 FIELD(DBGDIDR, BRPS, 24, 4) 2148 FIELD(DBGDIDR, WRPS, 28, 4) 2149 2150 FIELD(MVFR0, SIMDREG, 0, 4) 2151 FIELD(MVFR0, FPSP, 4, 4) 2152 FIELD(MVFR0, FPDP, 8, 4) 2153 FIELD(MVFR0, FPTRAP, 12, 4) 2154 FIELD(MVFR0, FPDIVIDE, 16, 4) 2155 FIELD(MVFR0, FPSQRT, 20, 4) 2156 FIELD(MVFR0, FPSHVEC, 24, 4) 2157 FIELD(MVFR0, FPROUND, 28, 4) 2158 2159 FIELD(MVFR1, FPFTZ, 0, 4) 2160 FIELD(MVFR1, FPDNAN, 4, 4) 2161 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2162 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2163 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2164 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2165 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2166 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2167 FIELD(MVFR1, FPHP, 24, 4) 2168 FIELD(MVFR1, SIMDFMAC, 28, 4) 2169 2170 FIELD(MVFR2, SIMDMISC, 0, 4) 2171 FIELD(MVFR2, FPMISC, 4, 4) 2172 2173 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2174 2175 /* If adding a feature bit which corresponds to a Linux ELF 2176 * HWCAP bit, remember to update the feature-bit-to-hwcap 2177 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2178 */ 2179 enum arm_features { 2180 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2181 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2182 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2183 ARM_FEATURE_V6, 2184 ARM_FEATURE_V6K, 2185 ARM_FEATURE_V7, 2186 ARM_FEATURE_THUMB2, 2187 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2188 ARM_FEATURE_NEON, 2189 ARM_FEATURE_M, /* Microcontroller profile. */ 2190 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2191 ARM_FEATURE_THUMB2EE, 2192 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2193 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2194 ARM_FEATURE_V4T, 2195 ARM_FEATURE_V5, 2196 ARM_FEATURE_STRONGARM, 2197 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2198 ARM_FEATURE_GENERIC_TIMER, 2199 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2200 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2201 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2202 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2203 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2204 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2205 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2206 ARM_FEATURE_V8, 2207 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2208 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2209 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2210 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2211 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2212 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2213 ARM_FEATURE_PMU, /* has PMU support */ 2214 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2215 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2216 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2217 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2218 }; 2219 2220 static inline int arm_feature(CPUARMState *env, int feature) 2221 { 2222 return (env->features & (1ULL << feature)) != 0; 2223 } 2224 2225 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2226 2227 #if !defined(CONFIG_USER_ONLY) 2228 /* Return true if exception levels below EL3 are in secure state, 2229 * or would be following an exception return to that level. 2230 * Unlike arm_is_secure() (which is always a question about the 2231 * _current_ state of the CPU) this doesn't care about the current 2232 * EL or mode. 2233 */ 2234 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2235 { 2236 if (arm_feature(env, ARM_FEATURE_EL3)) { 2237 return !(env->cp15.scr_el3 & SCR_NS); 2238 } else { 2239 /* If EL3 is not supported then the secure state is implementation 2240 * defined, in which case QEMU defaults to non-secure. 2241 */ 2242 return false; 2243 } 2244 } 2245 2246 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2247 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2248 { 2249 if (arm_feature(env, ARM_FEATURE_EL3)) { 2250 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2251 /* CPU currently in AArch64 state and EL3 */ 2252 return true; 2253 } else if (!is_a64(env) && 2254 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2255 /* CPU currently in AArch32 state and monitor mode */ 2256 return true; 2257 } 2258 } 2259 return false; 2260 } 2261 2262 /* Return true if the processor is in secure state */ 2263 static inline bool arm_is_secure(CPUARMState *env) 2264 { 2265 if (arm_is_el3_or_mon(env)) { 2266 return true; 2267 } 2268 return arm_is_secure_below_el3(env); 2269 } 2270 2271 /* 2272 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2273 * This corresponds to the pseudocode EL2Enabled() 2274 */ 2275 static inline bool arm_is_el2_enabled(CPUARMState *env) 2276 { 2277 if (arm_feature(env, ARM_FEATURE_EL2)) { 2278 if (arm_is_secure_below_el3(env)) { 2279 return (env->cp15.scr_el3 & SCR_EEL2) != 0; 2280 } 2281 return true; 2282 } 2283 return false; 2284 } 2285 2286 #else 2287 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2288 { 2289 return false; 2290 } 2291 2292 static inline bool arm_is_secure(CPUARMState *env) 2293 { 2294 return false; 2295 } 2296 2297 static inline bool arm_is_el2_enabled(CPUARMState *env) 2298 { 2299 return false; 2300 } 2301 #endif 2302 2303 /** 2304 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2305 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2306 * "for all purposes other than a direct read or write access of HCR_EL2." 2307 * Not included here is HCR_RW. 2308 */ 2309 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2310 2311 /* Return true if the specified exception level is running in AArch64 state. */ 2312 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2313 { 2314 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2315 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2316 */ 2317 assert(el >= 1 && el <= 3); 2318 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2319 2320 /* The highest exception level is always at the maximum supported 2321 * register width, and then lower levels have a register width controlled 2322 * by bits in the SCR or HCR registers. 2323 */ 2324 if (el == 3) { 2325 return aa64; 2326 } 2327 2328 if (arm_feature(env, ARM_FEATURE_EL3) && 2329 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2330 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2331 } 2332 2333 if (el == 2) { 2334 return aa64; 2335 } 2336 2337 if (arm_is_el2_enabled(env)) { 2338 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2339 } 2340 2341 return aa64; 2342 } 2343 2344 /* Function for determing whether guest cp register reads and writes should 2345 * access the secure or non-secure bank of a cp register. When EL3 is 2346 * operating in AArch32 state, the NS-bit determines whether the secure 2347 * instance of a cp register should be used. When EL3 is AArch64 (or if 2348 * it doesn't exist at all) then there is no register banking, and all 2349 * accesses are to the non-secure version. 2350 */ 2351 static inline bool access_secure_reg(CPUARMState *env) 2352 { 2353 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2354 !arm_el_is_aa64(env, 3) && 2355 !(env->cp15.scr_el3 & SCR_NS)); 2356 2357 return ret; 2358 } 2359 2360 /* Macros for accessing a specified CP register bank */ 2361 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2362 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2363 2364 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2365 do { \ 2366 if (_secure) { \ 2367 (_env)->cp15._regname##_s = (_val); \ 2368 } else { \ 2369 (_env)->cp15._regname##_ns = (_val); \ 2370 } \ 2371 } while (0) 2372 2373 /* Macros for automatically accessing a specific CP register bank depending on 2374 * the current secure state of the system. These macros are not intended for 2375 * supporting instruction translation reads/writes as these are dependent 2376 * solely on the SCR.NS bit and not the mode. 2377 */ 2378 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2379 A32_BANKED_REG_GET((_env), _regname, \ 2380 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2381 2382 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2383 A32_BANKED_REG_SET((_env), _regname, \ 2384 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2385 (_val)) 2386 2387 void arm_cpu_list(void); 2388 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2389 uint32_t cur_el, bool secure); 2390 2391 /* Interface between CPU and Interrupt controller. */ 2392 #ifndef CONFIG_USER_ONLY 2393 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2394 #else 2395 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2396 { 2397 return true; 2398 } 2399 #endif 2400 /** 2401 * armv7m_nvic_set_pending: mark the specified exception as pending 2402 * @opaque: the NVIC 2403 * @irq: the exception number to mark pending 2404 * @secure: false for non-banked exceptions or for the nonsecure 2405 * version of a banked exception, true for the secure version of a banked 2406 * exception. 2407 * 2408 * Marks the specified exception as pending. Note that we will assert() 2409 * if @secure is true and @irq does not specify one of the fixed set 2410 * of architecturally banked exceptions. 2411 */ 2412 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2413 /** 2414 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2415 * @opaque: the NVIC 2416 * @irq: the exception number to mark pending 2417 * @secure: false for non-banked exceptions or for the nonsecure 2418 * version of a banked exception, true for the secure version of a banked 2419 * exception. 2420 * 2421 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2422 * exceptions (exceptions generated in the course of trying to take 2423 * a different exception). 2424 */ 2425 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2426 /** 2427 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2428 * @opaque: the NVIC 2429 * @irq: the exception number to mark pending 2430 * @secure: false for non-banked exceptions or for the nonsecure 2431 * version of a banked exception, true for the secure version of a banked 2432 * exception. 2433 * 2434 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2435 * generated in the course of lazy stacking of FP registers. 2436 */ 2437 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2438 /** 2439 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2440 * exception, and whether it targets Secure state 2441 * @opaque: the NVIC 2442 * @pirq: set to pending exception number 2443 * @ptargets_secure: set to whether pending exception targets Secure 2444 * 2445 * This function writes the number of the highest priority pending 2446 * exception (the one which would be made active by 2447 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2448 * to true if the current highest priority pending exception should 2449 * be taken to Secure state, false for NS. 2450 */ 2451 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2452 bool *ptargets_secure); 2453 /** 2454 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2455 * @opaque: the NVIC 2456 * 2457 * Move the current highest priority pending exception from the pending 2458 * state to the active state, and update v7m.exception to indicate that 2459 * it is the exception currently being handled. 2460 */ 2461 void armv7m_nvic_acknowledge_irq(void *opaque); 2462 /** 2463 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2464 * @opaque: the NVIC 2465 * @irq: the exception number to complete 2466 * @secure: true if this exception was secure 2467 * 2468 * Returns: -1 if the irq was not active 2469 * 1 if completing this irq brought us back to base (no active irqs) 2470 * 0 if there is still an irq active after this one was completed 2471 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2472 */ 2473 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2474 /** 2475 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2476 * @opaque: the NVIC 2477 * @irq: the exception number to mark pending 2478 * @secure: false for non-banked exceptions or for the nonsecure 2479 * version of a banked exception, true for the secure version of a banked 2480 * exception. 2481 * 2482 * Return whether an exception is "ready", i.e. whether the exception is 2483 * enabled and is configured at a priority which would allow it to 2484 * interrupt the current execution priority. This controls whether the 2485 * RDY bit for it in the FPCCR is set. 2486 */ 2487 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2488 /** 2489 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2490 * @opaque: the NVIC 2491 * 2492 * Returns: the raw execution priority as defined by the v8M architecture. 2493 * This is the execution priority minus the effects of AIRCR.PRIS, 2494 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2495 * (v8M ARM ARM I_PKLD.) 2496 */ 2497 int armv7m_nvic_raw_execution_priority(void *opaque); 2498 /** 2499 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2500 * priority is negative for the specified security state. 2501 * @opaque: the NVIC 2502 * @secure: the security state to test 2503 * This corresponds to the pseudocode IsReqExecPriNeg(). 2504 */ 2505 #ifndef CONFIG_USER_ONLY 2506 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2507 #else 2508 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2509 { 2510 return false; 2511 } 2512 #endif 2513 2514 /* Interface for defining coprocessor registers. 2515 * Registers are defined in tables of arm_cp_reginfo structs 2516 * which are passed to define_arm_cp_regs(). 2517 */ 2518 2519 /* When looking up a coprocessor register we look for it 2520 * via an integer which encodes all of: 2521 * coprocessor number 2522 * Crn, Crm, opc1, opc2 fields 2523 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2524 * or via MRRC/MCRR?) 2525 * non-secure/secure bank (AArch32 only) 2526 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2527 * (In this case crn and opc2 should be zero.) 2528 * For AArch64, there is no 32/64 bit size distinction; 2529 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2530 * and 4 bit CRn and CRm. The encoding patterns are chosen 2531 * to be easy to convert to and from the KVM encodings, and also 2532 * so that the hashtable can contain both AArch32 and AArch64 2533 * registers (to allow for interprocessing where we might run 2534 * 32 bit code on a 64 bit core). 2535 */ 2536 /* This bit is private to our hashtable cpreg; in KVM register 2537 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2538 * in the upper bits of the 64 bit ID. 2539 */ 2540 #define CP_REG_AA64_SHIFT 28 2541 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2542 2543 /* To enable banking of coprocessor registers depending on ns-bit we 2544 * add a bit to distinguish between secure and non-secure cpregs in the 2545 * hashtable. 2546 */ 2547 #define CP_REG_NS_SHIFT 29 2548 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2549 2550 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2551 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2552 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2553 2554 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2555 (CP_REG_AA64_MASK | \ 2556 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2557 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2558 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2559 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2560 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2561 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2562 2563 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2564 * version used as a key for the coprocessor register hashtable 2565 */ 2566 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2567 { 2568 uint32_t cpregid = kvmid; 2569 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2570 cpregid |= CP_REG_AA64_MASK; 2571 } else { 2572 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2573 cpregid |= (1 << 15); 2574 } 2575 2576 /* KVM is always non-secure so add the NS flag on AArch32 register 2577 * entries. 2578 */ 2579 cpregid |= 1 << CP_REG_NS_SHIFT; 2580 } 2581 return cpregid; 2582 } 2583 2584 /* Convert a truncated 32 bit hashtable key into the full 2585 * 64 bit KVM register ID. 2586 */ 2587 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2588 { 2589 uint64_t kvmid; 2590 2591 if (cpregid & CP_REG_AA64_MASK) { 2592 kvmid = cpregid & ~CP_REG_AA64_MASK; 2593 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2594 } else { 2595 kvmid = cpregid & ~(1 << 15); 2596 if (cpregid & (1 << 15)) { 2597 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2598 } else { 2599 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2600 } 2601 } 2602 return kvmid; 2603 } 2604 2605 /* Return the highest implemented Exception Level */ 2606 static inline int arm_highest_el(CPUARMState *env) 2607 { 2608 if (arm_feature(env, ARM_FEATURE_EL3)) { 2609 return 3; 2610 } 2611 if (arm_feature(env, ARM_FEATURE_EL2)) { 2612 return 2; 2613 } 2614 return 1; 2615 } 2616 2617 /* Return true if a v7M CPU is in Handler mode */ 2618 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2619 { 2620 return env->v7m.exception != 0; 2621 } 2622 2623 /* Return the current Exception Level (as per ARMv8; note that this differs 2624 * from the ARMv7 Privilege Level). 2625 */ 2626 static inline int arm_current_el(CPUARMState *env) 2627 { 2628 if (arm_feature(env, ARM_FEATURE_M)) { 2629 return arm_v7m_is_handler_mode(env) || 2630 !(env->v7m.control[env->v7m.secure] & 1); 2631 } 2632 2633 if (is_a64(env)) { 2634 return extract32(env->pstate, 2, 2); 2635 } 2636 2637 switch (env->uncached_cpsr & 0x1f) { 2638 case ARM_CPU_MODE_USR: 2639 return 0; 2640 case ARM_CPU_MODE_HYP: 2641 return 2; 2642 case ARM_CPU_MODE_MON: 2643 return 3; 2644 default: 2645 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2646 /* If EL3 is 32-bit then all secure privileged modes run in 2647 * EL3 2648 */ 2649 return 3; 2650 } 2651 2652 return 1; 2653 } 2654 } 2655 2656 /** 2657 * write_list_to_cpustate 2658 * @cpu: ARMCPU 2659 * 2660 * For each register listed in the ARMCPU cpreg_indexes list, write 2661 * its value from the cpreg_values list into the ARMCPUState structure. 2662 * This updates TCG's working data structures from KVM data or 2663 * from incoming migration state. 2664 * 2665 * Returns: true if all register values were updated correctly, 2666 * false if some register was unknown or could not be written. 2667 * Note that we do not stop early on failure -- we will attempt 2668 * writing all registers in the list. 2669 */ 2670 bool write_list_to_cpustate(ARMCPU *cpu); 2671 2672 /** 2673 * write_cpustate_to_list: 2674 * @cpu: ARMCPU 2675 * @kvm_sync: true if this is for syncing back to KVM 2676 * 2677 * For each register listed in the ARMCPU cpreg_indexes list, write 2678 * its value from the ARMCPUState structure into the cpreg_values list. 2679 * This is used to copy info from TCG's working data structures into 2680 * KVM or for outbound migration. 2681 * 2682 * @kvm_sync is true if we are doing this in order to sync the 2683 * register state back to KVM. In this case we will only update 2684 * values in the list if the previous list->cpustate sync actually 2685 * successfully wrote the CPU state. Otherwise we will keep the value 2686 * that is in the list. 2687 * 2688 * Returns: true if all register values were read correctly, 2689 * false if some register was unknown or could not be read. 2690 * Note that we do not stop early on failure -- we will attempt 2691 * reading all registers in the list. 2692 */ 2693 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2694 2695 #define ARM_CPUID_TI915T 0x54029152 2696 #define ARM_CPUID_TI925T 0x54029252 2697 2698 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2699 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2700 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2701 2702 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2703 2704 #define cpu_list arm_cpu_list 2705 2706 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2707 * 2708 * If EL3 is 64-bit: 2709 * + NonSecure EL1 & 0 stage 1 2710 * + NonSecure EL1 & 0 stage 2 2711 * + NonSecure EL2 2712 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2713 * + Secure EL1 & 0 2714 * + Secure EL3 2715 * If EL3 is 32-bit: 2716 * + NonSecure PL1 & 0 stage 1 2717 * + NonSecure PL1 & 0 stage 2 2718 * + NonSecure PL2 2719 * + Secure PL0 2720 * + Secure PL1 2721 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2722 * 2723 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2724 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2725 * because they may differ in access permissions even if the VA->PA map is 2726 * the same 2727 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2728 * translation, which means that we have one mmu_idx that deals with two 2729 * concatenated translation regimes [this sort of combined s1+2 TLB is 2730 * architecturally permitted] 2731 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2732 * handling via the TLB. The only way to do a stage 1 translation without 2733 * the immediate stage 2 translation is via the ATS or AT system insns, 2734 * which can be slow-pathed and always do a page table walk. 2735 * The only use of stage 2 translations is either as part of an s1+2 2736 * lookup or when loading the descriptors during a stage 1 page table walk, 2737 * and in both those cases we don't use the TLB. 2738 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2739 * translation regimes, because they map reasonably well to each other 2740 * and they can't both be active at the same time. 2741 * 5. we want to be able to use the TLB for accesses done as part of a 2742 * stage1 page table walk, rather than having to walk the stage2 page 2743 * table over and over. 2744 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2745 * Never (PAN) bit within PSTATE. 2746 * 2747 * This gives us the following list of cases: 2748 * 2749 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 2750 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 2751 * NS EL1 EL1&0 stage 1+2 +PAN 2752 * NS EL0 EL2&0 2753 * NS EL2 EL2&0 2754 * NS EL2 EL2&0 +PAN 2755 * NS EL2 (aka NS PL2) 2756 * S EL0 EL1&0 (aka S PL0) 2757 * S EL1 EL1&0 (not used if EL3 is 32 bit) 2758 * S EL1 EL1&0 +PAN 2759 * S EL3 (aka S PL1) 2760 * 2761 * for a total of 11 different mmu_idx. 2762 * 2763 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2764 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2765 * NS EL2 if we ever model a Cortex-R52). 2766 * 2767 * M profile CPUs are rather different as they do not have a true MMU. 2768 * They have the following different MMU indexes: 2769 * User 2770 * Privileged 2771 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2772 * Privileged, execution priority negative (ditto) 2773 * If the CPU supports the v8M Security Extension then there are also: 2774 * Secure User 2775 * Secure Privileged 2776 * Secure User, execution priority negative 2777 * Secure Privileged, execution priority negative 2778 * 2779 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2780 * are not quite the same -- different CPU types (most notably M profile 2781 * vs A/R profile) would like to use MMU indexes with different semantics, 2782 * but since we don't ever need to use all of those in a single CPU we 2783 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2784 * modes + total number of M profile MMU modes". The lower bits of 2785 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2786 * the same for any particular CPU. 2787 * Variables of type ARMMUIdx are always full values, and the core 2788 * index values are in variables of type 'int'. 2789 * 2790 * Our enumeration includes at the end some entries which are not "true" 2791 * mmu_idx values in that they don't have corresponding TLBs and are only 2792 * valid for doing slow path page table walks. 2793 * 2794 * The constant names here are patterned after the general style of the names 2795 * of the AT/ATS operations. 2796 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2797 * For M profile we arrange them to have a bit for priv, a bit for negpri 2798 * and a bit for secure. 2799 */ 2800 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2801 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2802 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2803 2804 /* Meanings of the bits for A profile mmu idx values */ 2805 #define ARM_MMU_IDX_A_NS 0x8 2806 2807 /* Meanings of the bits for M profile mmu idx values */ 2808 #define ARM_MMU_IDX_M_PRIV 0x1 2809 #define ARM_MMU_IDX_M_NEGPRI 0x2 2810 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2811 2812 #define ARM_MMU_IDX_TYPE_MASK \ 2813 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2814 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2815 2816 typedef enum ARMMMUIdx { 2817 /* 2818 * A-profile. 2819 */ 2820 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, 2821 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, 2822 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, 2823 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, 2824 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, 2825 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, 2826 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, 2827 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, 2828 2829 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, 2830 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, 2831 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, 2832 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, 2833 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, 2834 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, 2835 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, 2836 2837 /* 2838 * These are not allocated TLBs and are used only for AT system 2839 * instructions or for the first stage of an S12 page table walk. 2840 */ 2841 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2842 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2843 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2844 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, 2845 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, 2846 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, 2847 /* 2848 * Not allocated a TLB: used only for second stage of an S12 page 2849 * table walk, or for descriptor loads during first stage of an S1 2850 * page table walk. Note that if we ever want to have a TLB for this 2851 * then various TLB flush insns which currently are no-ops or flush 2852 * only stage 1 MMU indexes will need to change to flush stage 2. 2853 */ 2854 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, 2855 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, 2856 2857 /* 2858 * M-profile. 2859 */ 2860 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2861 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2862 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2863 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2864 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2865 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2866 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2867 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2868 } ARMMMUIdx; 2869 2870 /* 2871 * Bit macros for the core-mmu-index values for each index, 2872 * for use when calling tlb_flush_by_mmuidx() and friends. 2873 */ 2874 #define TO_CORE_BIT(NAME) \ 2875 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2876 2877 typedef enum ARMMMUIdxBit { 2878 TO_CORE_BIT(E10_0), 2879 TO_CORE_BIT(E20_0), 2880 TO_CORE_BIT(E10_1), 2881 TO_CORE_BIT(E10_1_PAN), 2882 TO_CORE_BIT(E2), 2883 TO_CORE_BIT(E20_2), 2884 TO_CORE_BIT(E20_2_PAN), 2885 TO_CORE_BIT(SE10_0), 2886 TO_CORE_BIT(SE20_0), 2887 TO_CORE_BIT(SE10_1), 2888 TO_CORE_BIT(SE20_2), 2889 TO_CORE_BIT(SE10_1_PAN), 2890 TO_CORE_BIT(SE20_2_PAN), 2891 TO_CORE_BIT(SE2), 2892 TO_CORE_BIT(SE3), 2893 2894 TO_CORE_BIT(MUser), 2895 TO_CORE_BIT(MPriv), 2896 TO_CORE_BIT(MUserNegPri), 2897 TO_CORE_BIT(MPrivNegPri), 2898 TO_CORE_BIT(MSUser), 2899 TO_CORE_BIT(MSPriv), 2900 TO_CORE_BIT(MSUserNegPri), 2901 TO_CORE_BIT(MSPrivNegPri), 2902 } ARMMMUIdxBit; 2903 2904 #undef TO_CORE_BIT 2905 2906 #define MMU_USER_IDX 0 2907 2908 /* Indexes used when registering address spaces with cpu_address_space_init */ 2909 typedef enum ARMASIdx { 2910 ARMASIdx_NS = 0, 2911 ARMASIdx_S = 1, 2912 ARMASIdx_TagNS = 2, 2913 ARMASIdx_TagS = 3, 2914 } ARMASIdx; 2915 2916 /* Return the Exception Level targeted by debug exceptions. */ 2917 static inline int arm_debug_target_el(CPUARMState *env) 2918 { 2919 bool secure = arm_is_secure(env); 2920 bool route_to_el2 = false; 2921 2922 if (arm_is_el2_enabled(env)) { 2923 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2924 env->cp15.mdcr_el2 & MDCR_TDE; 2925 } 2926 2927 if (route_to_el2) { 2928 return 2; 2929 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2930 !arm_el_is_aa64(env, 3) && secure) { 2931 return 3; 2932 } else { 2933 return 1; 2934 } 2935 } 2936 2937 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2938 { 2939 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2940 * CSSELR is RAZ/WI. 2941 */ 2942 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2943 } 2944 2945 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 2946 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2947 { 2948 int cur_el = arm_current_el(env); 2949 int debug_el; 2950 2951 if (cur_el == 3) { 2952 return false; 2953 } 2954 2955 /* MDCR_EL3.SDD disables debug events from Secure state */ 2956 if (arm_is_secure_below_el3(env) 2957 && extract32(env->cp15.mdcr_el3, 16, 1)) { 2958 return false; 2959 } 2960 2961 /* 2962 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 2963 * while not masking the (D)ebug bit in DAIF. 2964 */ 2965 debug_el = arm_debug_target_el(env); 2966 2967 if (cur_el == debug_el) { 2968 return extract32(env->cp15.mdscr_el1, 13, 1) 2969 && !(env->daif & PSTATE_D); 2970 } 2971 2972 /* Otherwise the debug target needs to be a higher EL */ 2973 return debug_el > cur_el; 2974 } 2975 2976 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2977 { 2978 int el = arm_current_el(env); 2979 2980 if (el == 0 && arm_el_is_aa64(env, 1)) { 2981 return aa64_generate_debug_exceptions(env); 2982 } 2983 2984 if (arm_is_secure(env)) { 2985 int spd; 2986 2987 if (el == 0 && (env->cp15.sder & 1)) { 2988 /* SDER.SUIDEN means debug exceptions from Secure EL0 2989 * are always enabled. Otherwise they are controlled by 2990 * SDCR.SPD like those from other Secure ELs. 2991 */ 2992 return true; 2993 } 2994 2995 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2996 switch (spd) { 2997 case 1: 2998 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2999 case 0: 3000 /* For 0b00 we return true if external secure invasive debug 3001 * is enabled. On real hardware this is controlled by external 3002 * signals to the core. QEMU always permits debug, and behaves 3003 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3004 */ 3005 return true; 3006 case 2: 3007 return false; 3008 case 3: 3009 return true; 3010 } 3011 } 3012 3013 return el != 2; 3014 } 3015 3016 /* Return true if debugging exceptions are currently enabled. 3017 * This corresponds to what in ARM ARM pseudocode would be 3018 * if UsingAArch32() then 3019 * return AArch32.GenerateDebugExceptions() 3020 * else 3021 * return AArch64.GenerateDebugExceptions() 3022 * We choose to push the if() down into this function for clarity, 3023 * since the pseudocode has it at all callsites except for the one in 3024 * CheckSoftwareStep(), where it is elided because both branches would 3025 * always return the same value. 3026 */ 3027 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3028 { 3029 if (env->aarch64) { 3030 return aa64_generate_debug_exceptions(env); 3031 } else { 3032 return aa32_generate_debug_exceptions(env); 3033 } 3034 } 3035 3036 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3037 * implicitly means this always returns false in pre-v8 CPUs.) 3038 */ 3039 static inline bool arm_singlestep_active(CPUARMState *env) 3040 { 3041 return extract32(env->cp15.mdscr_el1, 0, 1) 3042 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3043 && arm_generate_debug_exceptions(env); 3044 } 3045 3046 static inline bool arm_sctlr_b(CPUARMState *env) 3047 { 3048 return 3049 /* We need not implement SCTLR.ITD in user-mode emulation, so 3050 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3051 * This lets people run BE32 binaries with "-cpu any". 3052 */ 3053 #ifndef CONFIG_USER_ONLY 3054 !arm_feature(env, ARM_FEATURE_V7) && 3055 #endif 3056 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3057 } 3058 3059 uint64_t arm_sctlr(CPUARMState *env, int el); 3060 3061 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3062 bool sctlr_b) 3063 { 3064 #ifdef CONFIG_USER_ONLY 3065 /* 3066 * In system mode, BE32 is modelled in line with the 3067 * architecture (as word-invariant big-endianness), where loads 3068 * and stores are done little endian but from addresses which 3069 * are adjusted by XORing with the appropriate constant. So the 3070 * endianness to use for the raw data access is not affected by 3071 * SCTLR.B. 3072 * In user mode, however, we model BE32 as byte-invariant 3073 * big-endianness (because user-only code cannot tell the 3074 * difference), and so we need to use a data access endianness 3075 * that depends on SCTLR.B. 3076 */ 3077 if (sctlr_b) { 3078 return true; 3079 } 3080 #endif 3081 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3082 return env->uncached_cpsr & CPSR_E; 3083 } 3084 3085 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3086 { 3087 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3088 } 3089 3090 /* Return true if the processor is in big-endian mode. */ 3091 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3092 { 3093 if (!is_a64(env)) { 3094 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3095 } else { 3096 int cur_el = arm_current_el(env); 3097 uint64_t sctlr = arm_sctlr(env, cur_el); 3098 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3099 } 3100 } 3101 3102 #include "exec/cpu-all.h" 3103 3104 /* 3105 * We have more than 32-bits worth of state per TB, so we split the data 3106 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3107 * We collect these two parts in CPUARMTBFlags where they are named 3108 * flags and flags2 respectively. 3109 * 3110 * The flags that are shared between all execution modes, TBFLAG_ANY, 3111 * are stored in flags. The flags that are specific to a given mode 3112 * are stores in flags2. Since cs_base is sized on the configured 3113 * address size, flags2 always has 64-bits for A64, and a minimum of 3114 * 32-bits for A32 and M32. 3115 * 3116 * The bits for 32-bit A-profile and M-profile partially overlap: 3117 * 3118 * 31 23 11 10 0 3119 * +-------------+----------+----------------+ 3120 * | | | TBFLAG_A32 | 3121 * | TBFLAG_AM32 | +-----+----------+ 3122 * | | |TBFLAG_M32| 3123 * +-------------+----------------+----------+ 3124 * 31 23 6 5 0 3125 * 3126 * Unless otherwise noted, these bits are cached in env->hflags. 3127 */ 3128 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3129 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3130 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3131 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3132 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3133 /* Target EL if we take a floating-point-disabled exception */ 3134 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3135 /* For A-profile only, target EL for debug exceptions. */ 3136 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) 3137 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3138 FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) 3139 FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1) 3140 3141 /* 3142 * Bit usage when in AArch32 state, both A- and M-profile. 3143 */ 3144 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3145 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3146 3147 /* 3148 * Bit usage when in AArch32 state, for A-profile only. 3149 */ 3150 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3151 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3152 /* 3153 * We store the bottom two bits of the CPAR as TB flags and handle 3154 * checks on the other bits at runtime. This shares the same bits as 3155 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3156 * Not cached, because VECLEN+VECSTRIDE are not cached. 3157 */ 3158 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3159 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3160 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3161 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3162 /* 3163 * Indicates whether cp register reads and writes by guest code should access 3164 * the secure or nonsecure bank of banked registers; note that this is not 3165 * the same thing as the current security state of the processor! 3166 */ 3167 FIELD(TBFLAG_A32, NS, 10, 1) 3168 3169 /* 3170 * Bit usage when in AArch32 state, for M-profile only. 3171 */ 3172 /* Handler (ie not Thread) mode */ 3173 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3174 /* Whether we should generate stack-limit checks */ 3175 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3176 /* Set if FPCCR.LSPACT is set */ 3177 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3178 /* Set if we must create a new FP context */ 3179 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3180 /* Set if FPCCR.S does not match current security state */ 3181 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3182 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3183 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3184 3185 /* 3186 * Bit usage when in AArch64 state 3187 */ 3188 FIELD(TBFLAG_A64, TBII, 0, 2) 3189 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3190 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3191 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3192 FIELD(TBFLAG_A64, BT, 9, 1) 3193 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3194 FIELD(TBFLAG_A64, TBID, 12, 2) 3195 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3196 FIELD(TBFLAG_A64, ATA, 15, 1) 3197 FIELD(TBFLAG_A64, TCMA, 16, 2) 3198 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3199 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3200 3201 /* 3202 * Helpers for using the above. 3203 */ 3204 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3205 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3206 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3207 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3208 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3209 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3210 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3211 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3212 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3213 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3214 3215 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3216 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3217 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3218 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3219 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3220 3221 /** 3222 * cpu_mmu_index: 3223 * @env: The cpu environment 3224 * @ifetch: True for code access, false for data access. 3225 * 3226 * Return the core mmu index for the current translation regime. 3227 * This function is used by generic TCG code paths. 3228 */ 3229 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3230 { 3231 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3232 } 3233 3234 static inline bool bswap_code(bool sctlr_b) 3235 { 3236 #ifdef CONFIG_USER_ONLY 3237 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3238 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3239 * would also end up as a mixed-endian mode with BE code, LE data. 3240 */ 3241 return 3242 #if TARGET_BIG_ENDIAN 3243 1 ^ 3244 #endif 3245 sctlr_b; 3246 #else 3247 /* All code access in ARM is little endian, and there are no loaders 3248 * doing swaps that need to be reversed 3249 */ 3250 return 0; 3251 #endif 3252 } 3253 3254 #ifdef CONFIG_USER_ONLY 3255 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3256 { 3257 return 3258 #if TARGET_BIG_ENDIAN 3259 1 ^ 3260 #endif 3261 arm_cpu_data_is_big_endian(env); 3262 } 3263 #endif 3264 3265 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3266 target_ulong *cs_base, uint32_t *flags); 3267 3268 enum { 3269 QEMU_PSCI_CONDUIT_DISABLED = 0, 3270 QEMU_PSCI_CONDUIT_SMC = 1, 3271 QEMU_PSCI_CONDUIT_HVC = 2, 3272 }; 3273 3274 #ifndef CONFIG_USER_ONLY 3275 /* Return the address space index to use for a memory access */ 3276 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3277 { 3278 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3279 } 3280 3281 /* Return the AddressSpace to use for a memory access 3282 * (which depends on whether the access is S or NS, and whether 3283 * the board gave us a separate AddressSpace for S accesses). 3284 */ 3285 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3286 { 3287 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3288 } 3289 #endif 3290 3291 /** 3292 * arm_register_pre_el_change_hook: 3293 * Register a hook function which will be called immediately before this 3294 * CPU changes exception level or mode. The hook function will be 3295 * passed a pointer to the ARMCPU and the opaque data pointer passed 3296 * to this function when the hook was registered. 3297 * 3298 * Note that if a pre-change hook is called, any registered post-change hooks 3299 * are guaranteed to subsequently be called. 3300 */ 3301 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3302 void *opaque); 3303 /** 3304 * arm_register_el_change_hook: 3305 * Register a hook function which will be called immediately after this 3306 * CPU changes exception level or mode. The hook function will be 3307 * passed a pointer to the ARMCPU and the opaque data pointer passed 3308 * to this function when the hook was registered. 3309 * 3310 * Note that any registered hooks registered here are guaranteed to be called 3311 * if pre-change hooks have been. 3312 */ 3313 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3314 *opaque); 3315 3316 /** 3317 * arm_rebuild_hflags: 3318 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3319 */ 3320 void arm_rebuild_hflags(CPUARMState *env); 3321 3322 /** 3323 * aa32_vfp_dreg: 3324 * Return a pointer to the Dn register within env in 32-bit mode. 3325 */ 3326 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3327 { 3328 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3329 } 3330 3331 /** 3332 * aa32_vfp_qreg: 3333 * Return a pointer to the Qn register within env in 32-bit mode. 3334 */ 3335 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3336 { 3337 return &env->vfp.zregs[regno].d[0]; 3338 } 3339 3340 /** 3341 * aa64_vfp_qreg: 3342 * Return a pointer to the Qn register within env in 64-bit mode. 3343 */ 3344 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3345 { 3346 return &env->vfp.zregs[regno].d[0]; 3347 } 3348 3349 /* Shared between translate-sve.c and sve_helper.c. */ 3350 extern const uint64_t pred_esz_masks[4]; 3351 3352 /* Helper for the macros below, validating the argument type. */ 3353 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) 3354 { 3355 return x; 3356 } 3357 3358 /* 3359 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. 3360 * Using these should be a bit more self-documenting than using the 3361 * generic target bits directly. 3362 */ 3363 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) 3364 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) 3365 3366 /* 3367 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3368 */ 3369 #define PAGE_BTI PAGE_TARGET_1 3370 #define PAGE_MTE PAGE_TARGET_2 3371 3372 #ifdef TARGET_TAGGED_ADDRESSES 3373 /** 3374 * cpu_untagged_addr: 3375 * @cs: CPU context 3376 * @x: tagged address 3377 * 3378 * Remove any address tag from @x. This is explicitly related to the 3379 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3380 * 3381 * There should be a better place to put this, but we need this in 3382 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3383 */ 3384 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3385 { 3386 ARMCPU *cpu = ARM_CPU(cs); 3387 if (cpu->env.tagged_addr_enable) { 3388 /* 3389 * TBI is enabled for userspace but not kernelspace addresses. 3390 * Only clear the tag if bit 55 is clear. 3391 */ 3392 x &= sextract64(x, 0, 56); 3393 } 3394 return x; 3395 } 3396 #endif 3397 3398 /* 3399 * Naming convention for isar_feature functions: 3400 * Functions which test 32-bit ID registers should have _aa32_ in 3401 * their name. Functions which test 64-bit ID registers should have 3402 * _aa64_ in their name. These must only be used in code where we 3403 * know for certain that the CPU has AArch32 or AArch64 respectively 3404 * or where the correct answer for a CPU which doesn't implement that 3405 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3406 * system registers that are specific to that CPU state, for "should 3407 * we let this system register bit be set" tests where the 32-bit 3408 * flavour of the register doesn't have the bit, and so on). 3409 * Functions which simply ask "does this feature exist at all" have 3410 * _any_ in their name, and always return the logical OR of the _aa64_ 3411 * and the _aa32_ function. 3412 */ 3413 3414 /* 3415 * 32-bit feature tests via id registers. 3416 */ 3417 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3418 { 3419 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3420 } 3421 3422 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3423 { 3424 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3425 } 3426 3427 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3428 { 3429 /* (M-profile) low-overhead loops and branch future */ 3430 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3431 } 3432 3433 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3434 { 3435 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3436 } 3437 3438 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3439 { 3440 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3441 } 3442 3443 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3444 { 3445 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3446 } 3447 3448 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3449 { 3450 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3451 } 3452 3453 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3454 { 3455 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3456 } 3457 3458 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3459 { 3460 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3461 } 3462 3463 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3464 { 3465 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3466 } 3467 3468 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3469 { 3470 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3471 } 3472 3473 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3474 { 3475 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3476 } 3477 3478 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3479 { 3480 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3481 } 3482 3483 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3484 { 3485 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3486 } 3487 3488 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3489 { 3490 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3491 } 3492 3493 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3494 { 3495 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3496 } 3497 3498 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3499 { 3500 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3501 } 3502 3503 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3504 { 3505 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3506 } 3507 3508 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3509 { 3510 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3511 } 3512 3513 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3514 { 3515 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3516 } 3517 3518 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3519 { 3520 /* 3521 * Return true if M-profile state handling insns 3522 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3523 */ 3524 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3525 } 3526 3527 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3528 { 3529 /* Sadly this is encoded differently for A-profile and M-profile */ 3530 if (isar_feature_aa32_mprofile(id)) { 3531 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3532 } else { 3533 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3534 } 3535 } 3536 3537 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3538 { 3539 /* 3540 * Return true if MVE is supported (either integer or floating point). 3541 * We must check for M-profile as the MVFR1 field means something 3542 * else for A-profile. 3543 */ 3544 return isar_feature_aa32_mprofile(id) && 3545 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3546 } 3547 3548 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3549 { 3550 /* 3551 * Return true if MVE is supported (either integer or floating point). 3552 * We must check for M-profile as the MVFR1 field means something 3553 * else for A-profile. 3554 */ 3555 return isar_feature_aa32_mprofile(id) && 3556 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3557 } 3558 3559 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3560 { 3561 /* 3562 * Return true if either VFP or SIMD is implemented. 3563 * In this case, a minimum of VFP w/ D0-D15. 3564 */ 3565 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3566 } 3567 3568 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3569 { 3570 /* Return true if D16-D31 are implemented */ 3571 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3572 } 3573 3574 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3575 { 3576 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3577 } 3578 3579 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3580 { 3581 /* Return true if CPU supports single precision floating point, VFPv2 */ 3582 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3583 } 3584 3585 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3586 { 3587 /* Return true if CPU supports single precision floating point, VFPv3 */ 3588 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3589 } 3590 3591 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3592 { 3593 /* Return true if CPU supports double precision floating point, VFPv2 */ 3594 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3595 } 3596 3597 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3598 { 3599 /* Return true if CPU supports double precision floating point, VFPv3 */ 3600 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3601 } 3602 3603 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3604 { 3605 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3606 } 3607 3608 /* 3609 * We always set the FP and SIMD FP16 fields to indicate identical 3610 * levels of support (assuming SIMD is implemented at all), so 3611 * we only need one set of accessors. 3612 */ 3613 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3614 { 3615 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3616 } 3617 3618 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3619 { 3620 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3621 } 3622 3623 /* 3624 * Note that this ID register field covers both VFP and Neon FMAC, 3625 * so should usually be tested in combination with some other 3626 * check that confirms the presence of whichever of VFP or Neon is 3627 * relevant, to avoid accidentally enabling a Neon feature on 3628 * a VFP-no-Neon core or vice-versa. 3629 */ 3630 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3631 { 3632 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3633 } 3634 3635 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3636 { 3637 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3638 } 3639 3640 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3641 { 3642 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3643 } 3644 3645 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3646 { 3647 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3648 } 3649 3650 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3651 { 3652 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3653 } 3654 3655 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3656 { 3657 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3658 } 3659 3660 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3661 { 3662 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3663 } 3664 3665 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3666 { 3667 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3668 } 3669 3670 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3671 { 3672 /* 0xf means "non-standard IMPDEF PMU" */ 3673 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3674 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3675 } 3676 3677 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3678 { 3679 /* 0xf means "non-standard IMPDEF PMU" */ 3680 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3681 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3682 } 3683 3684 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3685 { 3686 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3687 } 3688 3689 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3690 { 3691 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3692 } 3693 3694 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3695 { 3696 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3697 } 3698 3699 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3700 { 3701 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3702 } 3703 3704 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3705 { 3706 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3707 } 3708 3709 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3710 { 3711 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3712 } 3713 3714 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3715 { 3716 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3717 } 3718 3719 /* 3720 * 64-bit feature tests via id registers. 3721 */ 3722 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3723 { 3724 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3725 } 3726 3727 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3728 { 3729 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3730 } 3731 3732 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3733 { 3734 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3735 } 3736 3737 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3738 { 3739 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3740 } 3741 3742 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3743 { 3744 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3745 } 3746 3747 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3748 { 3749 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3750 } 3751 3752 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3753 { 3754 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3755 } 3756 3757 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3758 { 3759 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3760 } 3761 3762 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3763 { 3764 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3765 } 3766 3767 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3768 { 3769 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3770 } 3771 3772 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3773 { 3774 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3775 } 3776 3777 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3778 { 3779 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3780 } 3781 3782 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3783 { 3784 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3785 } 3786 3787 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3788 { 3789 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3790 } 3791 3792 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3793 { 3794 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3795 } 3796 3797 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3798 { 3799 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3800 } 3801 3802 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3803 { 3804 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3805 } 3806 3807 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3808 { 3809 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3810 } 3811 3812 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3813 { 3814 /* 3815 * Return true if any form of pauth is enabled, as this 3816 * predicate controls migration of the 128-bit keys. 3817 */ 3818 return (id->id_aa64isar1 & 3819 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3820 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3821 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3822 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3823 } 3824 3825 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3826 { 3827 /* 3828 * Return true if pauth is enabled with the architected QARMA algorithm. 3829 * QEMU will always set APA+GPA to the same value. 3830 */ 3831 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3832 } 3833 3834 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3835 { 3836 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3837 } 3838 3839 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3840 { 3841 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3842 } 3843 3844 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3845 { 3846 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3847 } 3848 3849 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3850 { 3851 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3852 } 3853 3854 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3855 { 3856 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3857 } 3858 3859 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3860 { 3861 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3862 } 3863 3864 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3865 { 3866 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3867 } 3868 3869 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3870 { 3871 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3872 } 3873 3874 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3875 { 3876 /* We always set the AdvSIMD and FP fields identically. */ 3877 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3878 } 3879 3880 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3881 { 3882 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3883 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3884 } 3885 3886 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3887 { 3888 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3889 } 3890 3891 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3892 { 3893 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3894 } 3895 3896 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3897 { 3898 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 3899 } 3900 3901 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3902 { 3903 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3904 } 3905 3906 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 3907 { 3908 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 3909 } 3910 3911 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3912 { 3913 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3914 } 3915 3916 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3917 { 3918 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3919 } 3920 3921 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3922 { 3923 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3924 } 3925 3926 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3927 { 3928 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3929 } 3930 3931 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 3932 { 3933 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 3934 } 3935 3936 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 3937 { 3938 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 3939 } 3940 3941 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3942 { 3943 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3944 } 3945 3946 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 3947 { 3948 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 3949 } 3950 3951 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 3952 { 3953 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 3954 } 3955 3956 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 3957 { 3958 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 3959 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3960 } 3961 3962 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 3963 { 3964 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 3965 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3966 } 3967 3968 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 3969 { 3970 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 3971 } 3972 3973 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 3974 { 3975 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 3976 } 3977 3978 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 3979 { 3980 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 3981 } 3982 3983 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 3984 { 3985 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 3986 } 3987 3988 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 3989 { 3990 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 3991 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 3992 } 3993 3994 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 3995 { 3996 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 3997 } 3998 3999 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 4000 { 4001 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4002 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 4003 } 4004 4005 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4006 { 4007 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4008 } 4009 4010 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4011 { 4012 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4013 } 4014 4015 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4016 { 4017 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4018 } 4019 4020 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4021 { 4022 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4023 } 4024 4025 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4026 { 4027 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4028 } 4029 4030 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4031 { 4032 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4033 } 4034 4035 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4036 { 4037 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4038 } 4039 4040 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4041 { 4042 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4043 } 4044 4045 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4046 { 4047 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4048 } 4049 4050 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4051 { 4052 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4053 } 4054 4055 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4056 { 4057 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4058 } 4059 4060 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4061 { 4062 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4063 } 4064 4065 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4066 { 4067 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4068 } 4069 4070 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4071 { 4072 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4073 } 4074 4075 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4076 { 4077 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4078 } 4079 4080 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4081 { 4082 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4083 } 4084 4085 /* 4086 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4087 */ 4088 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4089 { 4090 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4091 } 4092 4093 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4094 { 4095 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4096 } 4097 4098 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 4099 { 4100 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 4101 } 4102 4103 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 4104 { 4105 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 4106 } 4107 4108 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4109 { 4110 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4111 } 4112 4113 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4114 { 4115 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4116 } 4117 4118 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4119 { 4120 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4121 } 4122 4123 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4124 { 4125 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4126 } 4127 4128 /* 4129 * Forward to the above feature tests given an ARMCPU pointer. 4130 */ 4131 #define cpu_isar_feature(name, cpu) \ 4132 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4133 4134 #endif 4135