1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 #include "target/arm/multiprocessing.h" 30 31 /* ARM processors have a weak memory model */ 32 #define TCG_GUEST_DEFAULT_MO (0) 33 34 #ifdef TARGET_AARCH64 35 #define KVM_HAVE_MCE_INJECTION 1 36 #endif 37 38 #define EXCP_UDEF 1 /* undefined instruction */ 39 #define EXCP_SWI 2 /* software interrupt */ 40 #define EXCP_PREFETCH_ABORT 3 41 #define EXCP_DATA_ABORT 4 42 #define EXCP_IRQ 5 43 #define EXCP_FIQ 6 44 #define EXCP_BKPT 7 45 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 46 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 47 #define EXCP_HVC 11 /* HyperVisor Call */ 48 #define EXCP_HYP_TRAP 12 49 #define EXCP_SMC 13 /* Secure Monitor Call */ 50 #define EXCP_VIRQ 14 51 #define EXCP_VFIQ 15 52 #define EXCP_SEMIHOST 16 /* semihosting call */ 53 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 54 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 55 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 56 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 57 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 58 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 59 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 60 #define EXCP_VSERR 24 61 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 62 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 63 64 #define ARMV7M_EXCP_RESET 1 65 #define ARMV7M_EXCP_NMI 2 66 #define ARMV7M_EXCP_HARD 3 67 #define ARMV7M_EXCP_MEM 4 68 #define ARMV7M_EXCP_BUS 5 69 #define ARMV7M_EXCP_USAGE 6 70 #define ARMV7M_EXCP_SECURE 7 71 #define ARMV7M_EXCP_SVC 11 72 #define ARMV7M_EXCP_DEBUG 12 73 #define ARMV7M_EXCP_PENDSV 14 74 #define ARMV7M_EXCP_SYSTICK 15 75 76 /* For M profile, some registers are banked secure vs non-secure; 77 * these are represented as a 2-element array where the first element 78 * is the non-secure copy and the second is the secure copy. 79 * When the CPU does not have implement the security extension then 80 * only the first element is used. 81 * This means that the copy for the current security state can be 82 * accessed via env->registerfield[env->v7m.secure] (whether the security 83 * extension is implemented or not). 84 */ 85 enum { 86 M_REG_NS = 0, 87 M_REG_S = 1, 88 M_REG_NUM_BANKS = 2, 89 }; 90 91 /* ARM-specific interrupt pending bits. */ 92 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 93 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 94 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 95 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 96 97 /* The usual mapping for an AArch64 system register to its AArch32 98 * counterpart is for the 32 bit world to have access to the lower 99 * half only (with writes leaving the upper half untouched). It's 100 * therefore useful to be able to pass TCG the offset of the least 101 * significant half of a uint64_t struct member. 102 */ 103 #if HOST_BIG_ENDIAN 104 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 105 #define offsetofhigh32(S, M) offsetof(S, M) 106 #else 107 #define offsetoflow32(S, M) offsetof(S, M) 108 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 109 #endif 110 111 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 112 #define ARM_CPU_IRQ 0 113 #define ARM_CPU_FIQ 1 114 #define ARM_CPU_VIRQ 2 115 #define ARM_CPU_VFIQ 3 116 117 /* ARM-specific extra insn start words: 118 * 1: Conditional execution bits 119 * 2: Partial exception syndrome for data aborts 120 */ 121 #define TARGET_INSN_START_EXTRA_WORDS 2 122 123 /* The 2nd extra word holding syndrome info for data aborts does not use 124 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 125 * help the sleb128 encoder do a better job. 126 * When restoring the CPU state, we shift it back up. 127 */ 128 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 129 #define ARM_INSN_START_WORD2_SHIFT 13 130 131 /* We currently assume float and double are IEEE single and double 132 precision respectively. 133 Doing runtime conversions is tricky because VFP registers may contain 134 integer values (eg. as the result of a FTOSI instruction). 135 s<2n> maps to the least significant half of d<n> 136 s<2n+1> maps to the most significant half of d<n> 137 */ 138 139 /** 140 * DynamicGDBXMLInfo: 141 * @desc: Contains the XML descriptions. 142 * @num: Number of the registers in this XML seen by GDB. 143 * @data: A union with data specific to the set of registers 144 * @cpregs_keys: Array that contains the corresponding Key of 145 * a given cpreg with the same order of the cpreg 146 * in the XML description. 147 */ 148 typedef struct DynamicGDBXMLInfo { 149 char *desc; 150 int num; 151 union { 152 struct { 153 uint32_t *keys; 154 } cpregs; 155 } data; 156 } DynamicGDBXMLInfo; 157 158 /* CPU state for each instance of a generic timer (in cp15 c14) */ 159 typedef struct ARMGenericTimer { 160 uint64_t cval; /* Timer CompareValue register */ 161 uint64_t ctl; /* Timer Control register */ 162 } ARMGenericTimer; 163 164 #define GTIMER_PHYS 0 165 #define GTIMER_VIRT 1 166 #define GTIMER_HYP 2 167 #define GTIMER_SEC 3 168 #define GTIMER_HYPVIRT 4 169 #define NUM_GTIMERS 5 170 171 #define VTCR_NSW (1u << 29) 172 #define VTCR_NSA (1u << 30) 173 #define VSTCR_SW VTCR_NSW 174 #define VSTCR_SA VTCR_NSA 175 176 /* Define a maximum sized vector register. 177 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 178 * For 64-bit, this is a 2048-bit SVE register. 179 * 180 * Note that the mapping between S, D, and Q views of the register bank 181 * differs between AArch64 and AArch32. 182 * In AArch32: 183 * Qn = regs[n].d[1]:regs[n].d[0] 184 * Dn = regs[n / 2].d[n & 1] 185 * Sn = regs[n / 4].d[n % 4 / 2], 186 * bits 31..0 for even n, and bits 63..32 for odd n 187 * (and regs[16] to regs[31] are inaccessible) 188 * In AArch64: 189 * Zn = regs[n].d[*] 190 * Qn = regs[n].d[1]:regs[n].d[0] 191 * Dn = regs[n].d[0] 192 * Sn = regs[n].d[0] bits 31..0 193 * Hn = regs[n].d[0] bits 15..0 194 * 195 * This corresponds to the architecturally defined mapping between 196 * the two execution states, and means we do not need to explicitly 197 * map these registers when changing states. 198 * 199 * Align the data for use with TCG host vector operations. 200 */ 201 202 #ifdef TARGET_AARCH64 203 # define ARM_MAX_VQ 16 204 #else 205 # define ARM_MAX_VQ 1 206 #endif 207 208 typedef struct ARMVectorReg { 209 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 210 } ARMVectorReg; 211 212 #ifdef TARGET_AARCH64 213 /* In AArch32 mode, predicate registers do not exist at all. */ 214 typedef struct ARMPredicateReg { 215 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 216 } ARMPredicateReg; 217 218 /* In AArch32 mode, PAC keys do not exist at all. */ 219 typedef struct ARMPACKey { 220 uint64_t lo, hi; 221 } ARMPACKey; 222 #endif 223 224 /* See the commentary above the TBFLAG field definitions. */ 225 typedef struct CPUARMTBFlags { 226 uint32_t flags; 227 target_ulong flags2; 228 } CPUARMTBFlags; 229 230 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 231 232 typedef struct NVICState NVICState; 233 234 typedef struct CPUArchState { 235 /* Regs for current mode. */ 236 uint32_t regs[16]; 237 238 /* 32/64 switch only happens when taking and returning from 239 * exceptions so the overlap semantics are taken care of then 240 * instead of having a complicated union. 241 */ 242 /* Regs for A64 mode. */ 243 uint64_t xregs[32]; 244 uint64_t pc; 245 /* PSTATE isn't an architectural register for ARMv8. However, it is 246 * convenient for us to assemble the underlying state into a 32 bit format 247 * identical to the architectural format used for the SPSR. (This is also 248 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 249 * 'pstate' register are.) Of the PSTATE bits: 250 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 251 * semantics as for AArch32, as described in the comments on each field) 252 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 253 * DAIF (exception masks) are kept in env->daif 254 * BTYPE is kept in env->btype 255 * SM and ZA are kept in env->svcr 256 * all other bits are stored in their correct places in env->pstate 257 */ 258 uint32_t pstate; 259 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 260 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 261 262 /* Cached TBFLAGS state. See below for which bits are included. */ 263 CPUARMTBFlags hflags; 264 265 /* Frequently accessed CPSR bits are stored separately for efficiency. 266 This contains all the other bits. Use cpsr_{read,write} to access 267 the whole CPSR. */ 268 uint32_t uncached_cpsr; 269 uint32_t spsr; 270 271 /* Banked registers. */ 272 uint64_t banked_spsr[8]; 273 uint32_t banked_r13[8]; 274 uint32_t banked_r14[8]; 275 276 /* These hold r8-r12. */ 277 uint32_t usr_regs[5]; 278 uint32_t fiq_regs[5]; 279 280 /* cpsr flag cache for faster execution */ 281 uint32_t CF; /* 0 or 1 */ 282 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 283 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 284 uint32_t ZF; /* Z set if zero. */ 285 uint32_t QF; /* 0 or 1 */ 286 uint32_t GE; /* cpsr[19:16] */ 287 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 288 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 289 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 290 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 291 292 uint64_t elr_el[4]; /* AArch64 exception link regs */ 293 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 294 295 /* System control coprocessor (cp15) */ 296 struct { 297 uint32_t c0_cpuid; 298 union { /* Cache size selection */ 299 struct { 300 uint64_t _unused_csselr0; 301 uint64_t csselr_ns; 302 uint64_t _unused_csselr1; 303 uint64_t csselr_s; 304 }; 305 uint64_t csselr_el[4]; 306 }; 307 union { /* System control register. */ 308 struct { 309 uint64_t _unused_sctlr; 310 uint64_t sctlr_ns; 311 uint64_t hsctlr; 312 uint64_t sctlr_s; 313 }; 314 uint64_t sctlr_el[4]; 315 }; 316 uint64_t vsctlr; /* Virtualization System control register. */ 317 uint64_t cpacr_el1; /* Architectural feature access control register */ 318 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 319 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 320 uint64_t sder; /* Secure debug enable register. */ 321 uint32_t nsacr; /* Non-secure access control register. */ 322 union { /* MMU translation table base 0. */ 323 struct { 324 uint64_t _unused_ttbr0_0; 325 uint64_t ttbr0_ns; 326 uint64_t _unused_ttbr0_1; 327 uint64_t ttbr0_s; 328 }; 329 uint64_t ttbr0_el[4]; 330 }; 331 union { /* MMU translation table base 1. */ 332 struct { 333 uint64_t _unused_ttbr1_0; 334 uint64_t ttbr1_ns; 335 uint64_t _unused_ttbr1_1; 336 uint64_t ttbr1_s; 337 }; 338 uint64_t ttbr1_el[4]; 339 }; 340 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 341 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 342 /* MMU translation table base control. */ 343 uint64_t tcr_el[4]; 344 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 345 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 346 uint32_t c2_data; /* MPU data cacheable bits. */ 347 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 348 union { /* MMU domain access control register 349 * MPU write buffer control. 350 */ 351 struct { 352 uint64_t dacr_ns; 353 uint64_t dacr_s; 354 }; 355 struct { 356 uint64_t dacr32_el2; 357 }; 358 }; 359 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 360 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 361 uint64_t hcr_el2; /* Hypervisor configuration register */ 362 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 363 uint64_t scr_el3; /* Secure configuration register. */ 364 union { /* Fault status registers. */ 365 struct { 366 uint64_t ifsr_ns; 367 uint64_t ifsr_s; 368 }; 369 struct { 370 uint64_t ifsr32_el2; 371 }; 372 }; 373 union { 374 struct { 375 uint64_t _unused_dfsr; 376 uint64_t dfsr_ns; 377 uint64_t hsr; 378 uint64_t dfsr_s; 379 }; 380 uint64_t esr_el[4]; 381 }; 382 uint32_t c6_region[8]; /* MPU base/size registers. */ 383 union { /* Fault address registers. */ 384 struct { 385 uint64_t _unused_far0; 386 #if HOST_BIG_ENDIAN 387 uint32_t ifar_ns; 388 uint32_t dfar_ns; 389 uint32_t ifar_s; 390 uint32_t dfar_s; 391 #else 392 uint32_t dfar_ns; 393 uint32_t ifar_ns; 394 uint32_t dfar_s; 395 uint32_t ifar_s; 396 #endif 397 uint64_t _unused_far3; 398 }; 399 uint64_t far_el[4]; 400 }; 401 uint64_t hpfar_el2; 402 uint64_t hstr_el2; 403 union { /* Translation result. */ 404 struct { 405 uint64_t _unused_par_0; 406 uint64_t par_ns; 407 uint64_t _unused_par_1; 408 uint64_t par_s; 409 }; 410 uint64_t par_el[4]; 411 }; 412 413 uint32_t c9_insn; /* Cache lockdown registers. */ 414 uint32_t c9_data; 415 uint64_t c9_pmcr; /* performance monitor control register */ 416 uint64_t c9_pmcnten; /* perf monitor counter enables */ 417 uint64_t c9_pmovsr; /* perf monitor overflow status */ 418 uint64_t c9_pmuserenr; /* perf monitor user enable */ 419 uint64_t c9_pmselr; /* perf monitor counter selection register */ 420 uint64_t c9_pminten; /* perf monitor interrupt enables */ 421 union { /* Memory attribute redirection */ 422 struct { 423 #if HOST_BIG_ENDIAN 424 uint64_t _unused_mair_0; 425 uint32_t mair1_ns; 426 uint32_t mair0_ns; 427 uint64_t _unused_mair_1; 428 uint32_t mair1_s; 429 uint32_t mair0_s; 430 #else 431 uint64_t _unused_mair_0; 432 uint32_t mair0_ns; 433 uint32_t mair1_ns; 434 uint64_t _unused_mair_1; 435 uint32_t mair0_s; 436 uint32_t mair1_s; 437 #endif 438 }; 439 uint64_t mair_el[4]; 440 }; 441 union { /* vector base address register */ 442 struct { 443 uint64_t _unused_vbar; 444 uint64_t vbar_ns; 445 uint64_t hvbar; 446 uint64_t vbar_s; 447 }; 448 uint64_t vbar_el[4]; 449 }; 450 uint32_t mvbar; /* (monitor) vector base address register */ 451 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 452 struct { /* FCSE PID. */ 453 uint32_t fcseidr_ns; 454 uint32_t fcseidr_s; 455 }; 456 union { /* Context ID. */ 457 struct { 458 uint64_t _unused_contextidr_0; 459 uint64_t contextidr_ns; 460 uint64_t _unused_contextidr_1; 461 uint64_t contextidr_s; 462 }; 463 uint64_t contextidr_el[4]; 464 }; 465 union { /* User RW Thread register. */ 466 struct { 467 uint64_t tpidrurw_ns; 468 uint64_t tpidrprw_ns; 469 uint64_t htpidr; 470 uint64_t _tpidr_el3; 471 }; 472 uint64_t tpidr_el[4]; 473 }; 474 uint64_t tpidr2_el0; 475 /* The secure banks of these registers don't map anywhere */ 476 uint64_t tpidrurw_s; 477 uint64_t tpidrprw_s; 478 uint64_t tpidruro_s; 479 480 union { /* User RO Thread register. */ 481 uint64_t tpidruro_ns; 482 uint64_t tpidrro_el[1]; 483 }; 484 uint64_t c14_cntfrq; /* Counter Frequency register */ 485 uint64_t c14_cntkctl; /* Timer Control register */ 486 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 487 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 488 ARMGenericTimer c14_timer[NUM_GTIMERS]; 489 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 490 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 491 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 492 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 493 uint32_t c15_threadid; /* TI debugger thread-ID. */ 494 uint32_t c15_config_base_address; /* SCU base address. */ 495 uint32_t c15_diagnostic; /* diagnostic register */ 496 uint32_t c15_power_diagnostic; 497 uint32_t c15_power_control; /* power control */ 498 uint64_t dbgbvr[16]; /* breakpoint value registers */ 499 uint64_t dbgbcr[16]; /* breakpoint control registers */ 500 uint64_t dbgwvr[16]; /* watchpoint value registers */ 501 uint64_t dbgwcr[16]; /* watchpoint control registers */ 502 uint64_t dbgclaim; /* DBGCLAIM bits */ 503 uint64_t mdscr_el1; 504 uint64_t oslsr_el1; /* OS Lock Status */ 505 uint64_t osdlr_el1; /* OS DoubleLock status */ 506 uint64_t mdcr_el2; 507 uint64_t mdcr_el3; 508 /* Stores the architectural value of the counter *the last time it was 509 * updated* by pmccntr_op_start. Accesses should always be surrounded 510 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 511 * architecturally-correct value is being read/set. 512 */ 513 uint64_t c15_ccnt; 514 /* Stores the delta between the architectural value and the underlying 515 * cycle count during normal operation. It is used to update c15_ccnt 516 * to be the correct architectural value before accesses. During 517 * accesses, c15_ccnt_delta contains the underlying count being used 518 * for the access, after which it reverts to the delta value in 519 * pmccntr_op_finish. 520 */ 521 uint64_t c15_ccnt_delta; 522 uint64_t c14_pmevcntr[31]; 523 uint64_t c14_pmevcntr_delta[31]; 524 uint64_t c14_pmevtyper[31]; 525 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 526 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 527 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 528 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 529 uint64_t gcr_el1; 530 uint64_t rgsr_el1; 531 532 /* Minimal RAS registers */ 533 uint64_t disr_el1; 534 uint64_t vdisr_el2; 535 uint64_t vsesr_el2; 536 537 /* 538 * Fine-Grained Trap registers. We store these as arrays so the 539 * access checking code doesn't have to manually select 540 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 541 * FEAT_FGT2 will add more elements to these arrays. 542 */ 543 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 544 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 545 uint64_t fgt_exec[1]; /* HFGITR */ 546 547 /* RME registers */ 548 uint64_t gpccr_el3; 549 uint64_t gptbr_el3; 550 uint64_t mfar_el3; 551 552 /* NV2 register */ 553 uint64_t vncr_el2; 554 } cp15; 555 556 struct { 557 /* M profile has up to 4 stack pointers: 558 * a Main Stack Pointer and a Process Stack Pointer for each 559 * of the Secure and Non-Secure states. (If the CPU doesn't support 560 * the security extension then it has only two SPs.) 561 * In QEMU we always store the currently active SP in regs[13], 562 * and the non-active SP for the current security state in 563 * v7m.other_sp. The stack pointers for the inactive security state 564 * are stored in other_ss_msp and other_ss_psp. 565 * switch_v7m_security_state() is responsible for rearranging them 566 * when we change security state. 567 */ 568 uint32_t other_sp; 569 uint32_t other_ss_msp; 570 uint32_t other_ss_psp; 571 uint32_t vecbase[M_REG_NUM_BANKS]; 572 uint32_t basepri[M_REG_NUM_BANKS]; 573 uint32_t control[M_REG_NUM_BANKS]; 574 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 575 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 576 uint32_t hfsr; /* HardFault Status */ 577 uint32_t dfsr; /* Debug Fault Status Register */ 578 uint32_t sfsr; /* Secure Fault Status Register */ 579 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 580 uint32_t bfar; /* BusFault Address */ 581 uint32_t sfar; /* Secure Fault Address Register */ 582 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 583 int exception; 584 uint32_t primask[M_REG_NUM_BANKS]; 585 uint32_t faultmask[M_REG_NUM_BANKS]; 586 uint32_t aircr; /* only holds r/w state if security extn implemented */ 587 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 588 uint32_t csselr[M_REG_NUM_BANKS]; 589 uint32_t scr[M_REG_NUM_BANKS]; 590 uint32_t msplim[M_REG_NUM_BANKS]; 591 uint32_t psplim[M_REG_NUM_BANKS]; 592 uint32_t fpcar[M_REG_NUM_BANKS]; 593 uint32_t fpccr[M_REG_NUM_BANKS]; 594 uint32_t fpdscr[M_REG_NUM_BANKS]; 595 uint32_t cpacr[M_REG_NUM_BANKS]; 596 uint32_t nsacr; 597 uint32_t ltpsize; 598 uint32_t vpr; 599 } v7m; 600 601 /* Information associated with an exception about to be taken: 602 * code which raises an exception must set cs->exception_index and 603 * the relevant parts of this structure; the cpu_do_interrupt function 604 * will then set the guest-visible registers as part of the exception 605 * entry process. 606 */ 607 struct { 608 uint32_t syndrome; /* AArch64 format syndrome register */ 609 uint32_t fsr; /* AArch32 format fault status register info */ 610 uint64_t vaddress; /* virtual addr associated with exception, if any */ 611 uint32_t target_el; /* EL the exception should be targeted for */ 612 /* If we implement EL2 we will also need to store information 613 * about the intermediate physical address for stage 2 faults. 614 */ 615 } exception; 616 617 /* Information associated with an SError */ 618 struct { 619 uint8_t pending; 620 uint8_t has_esr; 621 uint64_t esr; 622 } serror; 623 624 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 625 626 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 627 uint32_t irq_line_state; 628 629 /* Thumb-2 EE state. */ 630 uint32_t teecr; 631 uint32_t teehbr; 632 633 /* VFP coprocessor state. */ 634 struct { 635 ARMVectorReg zregs[32]; 636 637 #ifdef TARGET_AARCH64 638 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 639 #define FFR_PRED_NUM 16 640 ARMPredicateReg pregs[17]; 641 /* Scratch space for aa64 sve predicate temporary. */ 642 ARMPredicateReg preg_tmp; 643 #endif 644 645 /* We store these fpcsr fields separately for convenience. */ 646 uint32_t qc[4] QEMU_ALIGNED(16); 647 int vec_len; 648 int vec_stride; 649 650 uint32_t xregs[16]; 651 652 /* Scratch space for aa32 neon expansion. */ 653 uint32_t scratch[8]; 654 655 /* There are a number of distinct float control structures: 656 * 657 * fp_status: is the "normal" fp status. 658 * fp_status_fp16: used for half-precision calculations 659 * standard_fp_status : the ARM "Standard FPSCR Value" 660 * standard_fp_status_fp16 : used for half-precision 661 * calculations with the ARM "Standard FPSCR Value" 662 * 663 * Half-precision operations are governed by a separate 664 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 665 * status structure to control this. 666 * 667 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 668 * round-to-nearest and is used by any operations (generally 669 * Neon) which the architecture defines as controlled by the 670 * standard FPSCR value rather than the FPSCR. 671 * 672 * The "standard FPSCR but for fp16 ops" is needed because 673 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 674 * using a fixed value for it. 675 * 676 * To avoid having to transfer exception bits around, we simply 677 * say that the FPSCR cumulative exception flags are the logical 678 * OR of the flags in the four fp statuses. This relies on the 679 * only thing which needs to read the exception flags being 680 * an explicit FPSCR read. 681 */ 682 float_status fp_status; 683 float_status fp_status_f16; 684 float_status standard_fp_status; 685 float_status standard_fp_status_f16; 686 687 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 688 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 689 } vfp; 690 691 uint64_t exclusive_addr; 692 uint64_t exclusive_val; 693 /* 694 * Contains the 'val' for the second 64-bit register of LDXP, which comes 695 * from the higher address, not the high part of a complete 128-bit value. 696 * In some ways it might be more convenient to record the exclusive value 697 * as the low and high halves of a 128 bit data value, but the current 698 * semantics of these fields are baked into the migration format. 699 */ 700 uint64_t exclusive_high; 701 702 /* iwMMXt coprocessor state. */ 703 struct { 704 uint64_t regs[16]; 705 uint64_t val; 706 707 uint32_t cregs[16]; 708 } iwmmxt; 709 710 #ifdef TARGET_AARCH64 711 struct { 712 ARMPACKey apia; 713 ARMPACKey apib; 714 ARMPACKey apda; 715 ARMPACKey apdb; 716 ARMPACKey apga; 717 } keys; 718 719 uint64_t scxtnum_el[4]; 720 721 /* 722 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 723 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 724 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 725 * When SVL is less than the architectural maximum, the accessible 726 * storage is restricted, such that if the SVL is X bytes the guest can 727 * see only the bottom X elements of zarray[], and only the least 728 * significant X bytes of each element of the array. (In other words, 729 * the observable part is always square.) 730 * 731 * The ZA storage can also be considered as a set of square tiles of 732 * elements of different sizes. The mapping from tiles to the ZA array 733 * is architecturally defined, such that for tiles of elements of esz 734 * bytes, the Nth row (or "horizontal slice") of tile T is in 735 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 736 * in the ZA storage, because its rows are striped through the ZA array. 737 * 738 * Because this is so large, keep this toward the end of the reset area, 739 * to keep the offsets into the rest of the structure smaller. 740 */ 741 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 742 #endif 743 744 struct CPUBreakpoint *cpu_breakpoint[16]; 745 struct CPUWatchpoint *cpu_watchpoint[16]; 746 747 /* Optional fault info across tlb lookup. */ 748 ARMMMUFaultInfo *tlb_fi; 749 750 /* Fields up to this point are cleared by a CPU reset */ 751 struct {} end_reset_fields; 752 753 /* Fields after this point are preserved across CPU reset. */ 754 755 /* Internal CPU feature flags. */ 756 uint64_t features; 757 758 /* PMSAv7 MPU */ 759 struct { 760 uint32_t *drbar; 761 uint32_t *drsr; 762 uint32_t *dracr; 763 uint32_t rnr[M_REG_NUM_BANKS]; 764 } pmsav7; 765 766 /* PMSAv8 MPU */ 767 struct { 768 /* The PMSAv8 implementation also shares some PMSAv7 config 769 * and state: 770 * pmsav7.rnr (region number register) 771 * pmsav7_dregion (number of configured regions) 772 */ 773 uint32_t *rbar[M_REG_NUM_BANKS]; 774 uint32_t *rlar[M_REG_NUM_BANKS]; 775 uint32_t *hprbar; 776 uint32_t *hprlar; 777 uint32_t mair0[M_REG_NUM_BANKS]; 778 uint32_t mair1[M_REG_NUM_BANKS]; 779 uint32_t hprselr; 780 } pmsav8; 781 782 /* v8M SAU */ 783 struct { 784 uint32_t *rbar; 785 uint32_t *rlar; 786 uint32_t rnr; 787 uint32_t ctrl; 788 } sau; 789 790 #if !defined(CONFIG_USER_ONLY) 791 NVICState *nvic; 792 const struct arm_boot_info *boot_info; 793 /* Store GICv3CPUState to access from this struct */ 794 void *gicv3state; 795 #else /* CONFIG_USER_ONLY */ 796 /* For usermode syscall translation. */ 797 bool eabi; 798 #endif /* CONFIG_USER_ONLY */ 799 800 #ifdef TARGET_TAGGED_ADDRESSES 801 /* Linux syscall tagged address support */ 802 bool tagged_addr_enable; 803 #endif 804 } CPUARMState; 805 806 static inline void set_feature(CPUARMState *env, int feature) 807 { 808 env->features |= 1ULL << feature; 809 } 810 811 static inline void unset_feature(CPUARMState *env, int feature) 812 { 813 env->features &= ~(1ULL << feature); 814 } 815 816 /** 817 * ARMELChangeHookFn: 818 * type of a function which can be registered via arm_register_el_change_hook() 819 * to get callbacks when the CPU changes its exception level or mode. 820 */ 821 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 822 typedef struct ARMELChangeHook ARMELChangeHook; 823 struct ARMELChangeHook { 824 ARMELChangeHookFn *hook; 825 void *opaque; 826 QLIST_ENTRY(ARMELChangeHook) node; 827 }; 828 829 /* These values map onto the return values for 830 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 831 typedef enum ARMPSCIState { 832 PSCI_ON = 0, 833 PSCI_OFF = 1, 834 PSCI_ON_PENDING = 2 835 } ARMPSCIState; 836 837 typedef struct ARMISARegisters ARMISARegisters; 838 839 /* 840 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 841 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 842 * 843 * While processing properties during initialization, corresponding init bits 844 * are set for bits in sve_vq_map that have been set by properties. 845 * 846 * Bits set in supported represent valid vector lengths for the CPU type. 847 */ 848 typedef struct { 849 uint32_t map, init, supported; 850 } ARMVQMap; 851 852 /** 853 * ARMCPU: 854 * @env: #CPUARMState 855 * 856 * An ARM CPU core. 857 */ 858 struct ArchCPU { 859 CPUState parent_obj; 860 861 CPUARMState env; 862 863 /* Coprocessor information */ 864 GHashTable *cp_regs; 865 /* For marshalling (mostly coprocessor) register state between the 866 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 867 * we use these arrays. 868 */ 869 /* List of register indexes managed via these arrays; (full KVM style 870 * 64 bit indexes, not CPRegInfo 32 bit indexes) 871 */ 872 uint64_t *cpreg_indexes; 873 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 874 uint64_t *cpreg_values; 875 /* Length of the indexes, values, reset_values arrays */ 876 int32_t cpreg_array_len; 877 /* These are used only for migration: incoming data arrives in 878 * these fields and is sanity checked in post_load before copying 879 * to the working data structures above. 880 */ 881 uint64_t *cpreg_vmstate_indexes; 882 uint64_t *cpreg_vmstate_values; 883 int32_t cpreg_vmstate_array_len; 884 885 DynamicGDBXMLInfo dyn_sysreg_xml; 886 DynamicGDBXMLInfo dyn_svereg_xml; 887 DynamicGDBXMLInfo dyn_m_systemreg_xml; 888 DynamicGDBXMLInfo dyn_m_secextreg_xml; 889 890 /* Timers used by the generic (architected) timer */ 891 QEMUTimer *gt_timer[NUM_GTIMERS]; 892 /* 893 * Timer used by the PMU. Its state is restored after migration by 894 * pmu_op_finish() - it does not need other handling during migration 895 */ 896 QEMUTimer *pmu_timer; 897 /* GPIO outputs for generic timer */ 898 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 899 /* GPIO output for GICv3 maintenance interrupt signal */ 900 qemu_irq gicv3_maintenance_interrupt; 901 /* GPIO output for the PMU interrupt */ 902 qemu_irq pmu_interrupt; 903 904 /* MemoryRegion to use for secure physical accesses */ 905 MemoryRegion *secure_memory; 906 907 /* MemoryRegion to use for allocation tag accesses */ 908 MemoryRegion *tag_memory; 909 MemoryRegion *secure_tag_memory; 910 911 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 912 Object *idau; 913 914 /* 'compatible' string for this CPU for Linux device trees */ 915 const char *dtb_compatible; 916 917 /* PSCI version for this CPU 918 * Bits[31:16] = Major Version 919 * Bits[15:0] = Minor Version 920 */ 921 uint32_t psci_version; 922 923 /* Current power state, access guarded by BQL */ 924 ARMPSCIState power_state; 925 926 /* CPU has virtualization extension */ 927 bool has_el2; 928 /* CPU has security extension */ 929 bool has_el3; 930 /* CPU has PMU (Performance Monitor Unit) */ 931 bool has_pmu; 932 /* CPU has VFP */ 933 bool has_vfp; 934 /* CPU has 32 VFP registers */ 935 bool has_vfp_d32; 936 /* CPU has Neon */ 937 bool has_neon; 938 /* CPU has M-profile DSP extension */ 939 bool has_dsp; 940 941 /* CPU has memory protection unit */ 942 bool has_mpu; 943 /* PMSAv7 MPU number of supported regions */ 944 uint32_t pmsav7_dregion; 945 /* PMSAv8 MPU number of supported hyp regions */ 946 uint32_t pmsav8r_hdregion; 947 /* v8M SAU number of supported regions */ 948 uint32_t sau_sregion; 949 950 /* PSCI conduit used to invoke PSCI methods 951 * 0 - disabled, 1 - smc, 2 - hvc 952 */ 953 uint32_t psci_conduit; 954 955 /* For v8M, initial value of the Secure VTOR */ 956 uint32_t init_svtor; 957 /* For v8M, initial value of the Non-secure VTOR */ 958 uint32_t init_nsvtor; 959 960 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 961 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 962 */ 963 uint32_t kvm_target; 964 965 #ifdef CONFIG_KVM 966 /* KVM init features for this CPU */ 967 uint32_t kvm_init_features[7]; 968 969 /* KVM CPU state */ 970 971 /* KVM virtual time adjustment */ 972 bool kvm_adjvtime; 973 bool kvm_vtime_dirty; 974 uint64_t kvm_vtime; 975 976 /* KVM steal time */ 977 OnOffAuto kvm_steal_time; 978 #endif /* CONFIG_KVM */ 979 980 /* Uniprocessor system with MP extensions */ 981 bool mp_is_up; 982 983 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 984 * and the probe failed (so we need to report the error in realize) 985 */ 986 bool host_cpu_probe_failed; 987 988 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 989 * register. 990 */ 991 int32_t core_count; 992 993 /* The instance init functions for implementation-specific subclasses 994 * set these fields to specify the implementation-dependent values of 995 * various constant registers and reset values of non-constant 996 * registers. 997 * Some of these might become QOM properties eventually. 998 * Field names match the official register names as defined in the 999 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 1000 * is used for reset values of non-constant registers; no reset_ 1001 * prefix means a constant register. 1002 * Some of these registers are split out into a substructure that 1003 * is shared with the translators to control the ISA. 1004 * 1005 * Note that if you add an ID register to the ARMISARegisters struct 1006 * you need to also update the 32-bit and 64-bit versions of the 1007 * kvm_arm_get_host_cpu_features() function to correctly populate the 1008 * field by reading the value from the KVM vCPU. 1009 */ 1010 struct ARMISARegisters { 1011 uint32_t id_isar0; 1012 uint32_t id_isar1; 1013 uint32_t id_isar2; 1014 uint32_t id_isar3; 1015 uint32_t id_isar4; 1016 uint32_t id_isar5; 1017 uint32_t id_isar6; 1018 uint32_t id_mmfr0; 1019 uint32_t id_mmfr1; 1020 uint32_t id_mmfr2; 1021 uint32_t id_mmfr3; 1022 uint32_t id_mmfr4; 1023 uint32_t id_mmfr5; 1024 uint32_t id_pfr0; 1025 uint32_t id_pfr1; 1026 uint32_t id_pfr2; 1027 uint32_t mvfr0; 1028 uint32_t mvfr1; 1029 uint32_t mvfr2; 1030 uint32_t id_dfr0; 1031 uint32_t id_dfr1; 1032 uint32_t dbgdidr; 1033 uint32_t dbgdevid; 1034 uint32_t dbgdevid1; 1035 uint64_t id_aa64isar0; 1036 uint64_t id_aa64isar1; 1037 uint64_t id_aa64isar2; 1038 uint64_t id_aa64pfr0; 1039 uint64_t id_aa64pfr1; 1040 uint64_t id_aa64mmfr0; 1041 uint64_t id_aa64mmfr1; 1042 uint64_t id_aa64mmfr2; 1043 uint64_t id_aa64dfr0; 1044 uint64_t id_aa64dfr1; 1045 uint64_t id_aa64zfr0; 1046 uint64_t id_aa64smfr0; 1047 uint64_t reset_pmcr_el0; 1048 } isar; 1049 uint64_t midr; 1050 uint32_t revidr; 1051 uint32_t reset_fpsid; 1052 uint64_t ctr; 1053 uint32_t reset_sctlr; 1054 uint64_t pmceid0; 1055 uint64_t pmceid1; 1056 uint32_t id_afr0; 1057 uint64_t id_aa64afr0; 1058 uint64_t id_aa64afr1; 1059 uint64_t clidr; 1060 uint64_t mp_affinity; /* MP ID without feature bits */ 1061 /* The elements of this array are the CCSIDR values for each cache, 1062 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1063 */ 1064 uint64_t ccsidr[16]; 1065 uint64_t reset_cbar; 1066 uint32_t reset_auxcr; 1067 bool reset_hivecs; 1068 uint8_t reset_l0gptsz; 1069 1070 /* 1071 * Intermediate values used during property parsing. 1072 * Once finalized, the values should be read from ID_AA64*. 1073 */ 1074 bool prop_pauth; 1075 bool prop_pauth_impdef; 1076 bool prop_pauth_qarma3; 1077 bool prop_lpa2; 1078 1079 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1080 uint8_t dcz_blocksize; 1081 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1082 uint8_t gm_blocksize; 1083 1084 uint64_t rvbar_prop; /* Property/input signals. */ 1085 1086 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1087 int gic_num_lrs; /* number of list registers */ 1088 int gic_vpribits; /* number of virtual priority bits */ 1089 int gic_vprebits; /* number of virtual preemption bits */ 1090 int gic_pribits; /* number of physical priority bits */ 1091 1092 /* Whether the cfgend input is high (i.e. this CPU should reset into 1093 * big-endian mode). This setting isn't used directly: instead it modifies 1094 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1095 * architecture version. 1096 */ 1097 bool cfgend; 1098 1099 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1100 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1101 1102 int32_t node_id; /* NUMA node this CPU belongs to */ 1103 1104 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1105 uint8_t device_irq_level; 1106 1107 /* Used to set the maximum vector length the cpu will support. */ 1108 uint32_t sve_max_vq; 1109 1110 #ifdef CONFIG_USER_ONLY 1111 /* Used to set the default vector length at process start. */ 1112 uint32_t sve_default_vq; 1113 uint32_t sme_default_vq; 1114 #endif 1115 1116 ARMVQMap sve_vq; 1117 ARMVQMap sme_vq; 1118 1119 /* Generic timer counter frequency, in Hz */ 1120 uint64_t gt_cntfrq_hz; 1121 }; 1122 1123 typedef struct ARMCPUInfo { 1124 const char *name; 1125 void (*initfn)(Object *obj); 1126 void (*class_init)(ObjectClass *oc, void *data); 1127 } ARMCPUInfo; 1128 1129 /** 1130 * ARMCPUClass: 1131 * @parent_realize: The parent class' realize handler. 1132 * @parent_phases: The parent class' reset phase handlers. 1133 * 1134 * An ARM CPU model. 1135 */ 1136 struct ARMCPUClass { 1137 CPUClass parent_class; 1138 1139 const ARMCPUInfo *info; 1140 DeviceRealize parent_realize; 1141 ResettablePhases parent_phases; 1142 }; 1143 1144 struct AArch64CPUClass { 1145 ARMCPUClass parent_class; 1146 }; 1147 1148 /* Callback functions for the generic timer's timers. */ 1149 void arm_gt_ptimer_cb(void *opaque); 1150 void arm_gt_vtimer_cb(void *opaque); 1151 void arm_gt_htimer_cb(void *opaque); 1152 void arm_gt_stimer_cb(void *opaque); 1153 void arm_gt_hvtimer_cb(void *opaque); 1154 1155 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1156 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1157 1158 void arm_cpu_post_init(Object *obj); 1159 1160 #define ARM_AFF0_SHIFT 0 1161 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1162 #define ARM_AFF1_SHIFT 8 1163 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1164 #define ARM_AFF2_SHIFT 16 1165 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1166 #define ARM_AFF3_SHIFT 32 1167 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1168 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1169 1170 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1171 #define ARM64_AFFINITY_MASK \ 1172 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1173 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1174 1175 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1176 1177 #ifndef CONFIG_USER_ONLY 1178 extern const VMStateDescription vmstate_arm_cpu; 1179 1180 void arm_cpu_do_interrupt(CPUState *cpu); 1181 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1182 1183 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1184 MemTxAttrs *attrs); 1185 #endif /* !CONFIG_USER_ONLY */ 1186 1187 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1188 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1189 1190 /* Returns the dynamically generated XML for the gdb stub. 1191 * Returns a pointer to the XML contents for the specified XML file or NULL 1192 * if the XML name doesn't match the predefined one. 1193 */ 1194 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1195 1196 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1197 int cpuid, DumpState *s); 1198 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1199 int cpuid, DumpState *s); 1200 1201 /** 1202 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1203 * @cpu: CPU (which must have been freshly reset) 1204 * @target_el: exception level to put the CPU into 1205 * @secure: whether to put the CPU in secure state 1206 * 1207 * When QEMU is directly running a guest kernel at a lower level than 1208 * EL3 it implicitly emulates some aspects of the guest firmware. 1209 * This includes that on reset we need to configure the parts of the 1210 * CPU corresponding to EL3 so that the real guest code can run at its 1211 * lower exception level. This function does that post-reset CPU setup, 1212 * for when we do direct boot of a guest kernel, and for when we 1213 * emulate PSCI and similar firmware interfaces starting a CPU at a 1214 * lower exception level. 1215 * 1216 * @target_el must be an EL implemented by the CPU between 1 and 3. 1217 * We do not support dropping into a Secure EL other than 3. 1218 * 1219 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1220 */ 1221 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1222 1223 #ifdef TARGET_AARCH64 1224 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1225 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1226 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1227 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1228 int new_el, bool el0_a64); 1229 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1230 1231 /* 1232 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1233 * The byte at offset i from the start of the in-memory representation contains 1234 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1235 * lowest offsets are stored in the lowest memory addresses, then that nearly 1236 * matches QEMU's representation, which is to use an array of host-endian 1237 * uint64_t's, where the lower offsets are at the lower indices. To complete 1238 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1239 */ 1240 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1241 { 1242 #if HOST_BIG_ENDIAN 1243 int i; 1244 1245 for (i = 0; i < nr; ++i) { 1246 dst[i] = bswap64(src[i]); 1247 } 1248 1249 return dst; 1250 #else 1251 return src; 1252 #endif 1253 } 1254 1255 #else 1256 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1257 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1258 int n, bool a) 1259 { } 1260 #endif 1261 1262 void aarch64_sync_32_to_64(CPUARMState *env); 1263 void aarch64_sync_64_to_32(CPUARMState *env); 1264 1265 int fp_exception_el(CPUARMState *env, int cur_el); 1266 int sve_exception_el(CPUARMState *env, int cur_el); 1267 int sme_exception_el(CPUARMState *env, int cur_el); 1268 1269 /** 1270 * sve_vqm1_for_el_sm: 1271 * @env: CPUARMState 1272 * @el: exception level 1273 * @sm: streaming mode 1274 * 1275 * Compute the current vector length for @el & @sm, in units of 1276 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1277 * If @sm, compute for SVL, otherwise NVL. 1278 */ 1279 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1280 1281 /* Likewise, but using @sm = PSTATE.SM. */ 1282 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1283 1284 static inline bool is_a64(CPUARMState *env) 1285 { 1286 return env->aarch64; 1287 } 1288 1289 /** 1290 * pmu_op_start/finish 1291 * @env: CPUARMState 1292 * 1293 * Convert all PMU counters between their delta form (the typical mode when 1294 * they are enabled) and the guest-visible values. These two calls must 1295 * surround any action which might affect the counters. 1296 */ 1297 void pmu_op_start(CPUARMState *env); 1298 void pmu_op_finish(CPUARMState *env); 1299 1300 /* 1301 * Called when a PMU counter is due to overflow 1302 */ 1303 void arm_pmu_timer_cb(void *opaque); 1304 1305 /** 1306 * Functions to register as EL change hooks for PMU mode filtering 1307 */ 1308 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1309 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1310 1311 /* 1312 * pmu_init 1313 * @cpu: ARMCPU 1314 * 1315 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1316 * for the current configuration 1317 */ 1318 void pmu_init(ARMCPU *cpu); 1319 1320 /* SCTLR bit meanings. Several bits have been reused in newer 1321 * versions of the architecture; in that case we define constants 1322 * for both old and new bit meanings. Code which tests against those 1323 * bits should probably check or otherwise arrange that the CPU 1324 * is the architectural version it expects. 1325 */ 1326 #define SCTLR_M (1U << 0) 1327 #define SCTLR_A (1U << 1) 1328 #define SCTLR_C (1U << 2) 1329 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1330 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1331 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1332 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1333 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1334 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1335 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1336 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1337 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1338 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1339 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1340 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1341 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1342 #define SCTLR_SED (1U << 8) /* v8 onward */ 1343 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1344 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1345 #define SCTLR_F (1U << 10) /* up to v6 */ 1346 #define SCTLR_SW (1U << 10) /* v7 */ 1347 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1348 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1349 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1350 #define SCTLR_I (1U << 12) 1351 #define SCTLR_V (1U << 13) /* AArch32 only */ 1352 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1353 #define SCTLR_RR (1U << 14) /* up to v7 */ 1354 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1355 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1356 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1357 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1358 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1359 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1360 #define SCTLR_BR (1U << 17) /* PMSA only */ 1361 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1362 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1363 #define SCTLR_WXN (1U << 19) 1364 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1365 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1366 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1367 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1368 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1369 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1370 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1371 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1372 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1373 #define SCTLR_VE (1U << 24) /* up to v7 */ 1374 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1375 #define SCTLR_EE (1U << 25) 1376 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1377 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1378 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1379 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1380 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1381 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1382 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1383 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1384 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1385 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1386 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1387 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1388 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1389 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1390 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1391 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1392 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1393 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1394 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1395 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1396 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1397 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1398 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1399 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1400 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1401 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1402 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1403 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1404 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1405 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1406 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1407 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1408 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1409 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1410 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1411 1412 /* Bit definitions for CPACR (AArch32 only) */ 1413 FIELD(CPACR, CP10, 20, 2) 1414 FIELD(CPACR, CP11, 22, 2) 1415 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1416 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1417 FIELD(CPACR, ASEDIS, 31, 1) 1418 1419 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1420 FIELD(CPACR_EL1, ZEN, 16, 2) 1421 FIELD(CPACR_EL1, FPEN, 20, 2) 1422 FIELD(CPACR_EL1, SMEN, 24, 2) 1423 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1424 1425 /* Bit definitions for HCPTR (AArch32 only) */ 1426 FIELD(HCPTR, TCP10, 10, 1) 1427 FIELD(HCPTR, TCP11, 11, 1) 1428 FIELD(HCPTR, TASE, 15, 1) 1429 FIELD(HCPTR, TTA, 20, 1) 1430 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1431 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1432 1433 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1434 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1435 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1436 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1437 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1438 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1439 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1440 FIELD(CPTR_EL2, TTA, 28, 1) 1441 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1442 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1443 1444 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1445 FIELD(CPTR_EL3, EZ, 8, 1) 1446 FIELD(CPTR_EL3, TFP, 10, 1) 1447 FIELD(CPTR_EL3, ESM, 12, 1) 1448 FIELD(CPTR_EL3, TTA, 20, 1) 1449 FIELD(CPTR_EL3, TAM, 30, 1) 1450 FIELD(CPTR_EL3, TCPAC, 31, 1) 1451 1452 #define MDCR_MTPME (1U << 28) 1453 #define MDCR_TDCC (1U << 27) 1454 #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ 1455 #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ 1456 #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ 1457 #define MDCR_EPMAD (1U << 21) 1458 #define MDCR_EDAD (1U << 20) 1459 #define MDCR_TTRF (1U << 19) 1460 #define MDCR_STE (1U << 18) /* MDCR_EL3 */ 1461 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1462 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1463 #define MDCR_SDD (1U << 16) 1464 #define MDCR_SPD (3U << 14) 1465 #define MDCR_TDRA (1U << 11) 1466 #define MDCR_TDOSA (1U << 10) 1467 #define MDCR_TDA (1U << 9) 1468 #define MDCR_TDE (1U << 8) 1469 #define MDCR_HPME (1U << 7) 1470 #define MDCR_TPM (1U << 6) 1471 #define MDCR_TPMCR (1U << 5) 1472 #define MDCR_HPMN (0x1fU) 1473 1474 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1475 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ 1476 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ 1477 MDCR_STE | MDCR_SPME | MDCR_SPD) 1478 1479 #define CPSR_M (0x1fU) 1480 #define CPSR_T (1U << 5) 1481 #define CPSR_F (1U << 6) 1482 #define CPSR_I (1U << 7) 1483 #define CPSR_A (1U << 8) 1484 #define CPSR_E (1U << 9) 1485 #define CPSR_IT_2_7 (0xfc00U) 1486 #define CPSR_GE (0xfU << 16) 1487 #define CPSR_IL (1U << 20) 1488 #define CPSR_DIT (1U << 21) 1489 #define CPSR_PAN (1U << 22) 1490 #define CPSR_SSBS (1U << 23) 1491 #define CPSR_J (1U << 24) 1492 #define CPSR_IT_0_1 (3U << 25) 1493 #define CPSR_Q (1U << 27) 1494 #define CPSR_V (1U << 28) 1495 #define CPSR_C (1U << 29) 1496 #define CPSR_Z (1U << 30) 1497 #define CPSR_N (1U << 31) 1498 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1499 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1500 1501 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1502 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1503 | CPSR_NZCV) 1504 /* Bits writable in user mode. */ 1505 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1506 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1507 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1508 1509 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1510 #define XPSR_EXCP 0x1ffU 1511 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1512 #define XPSR_IT_2_7 CPSR_IT_2_7 1513 #define XPSR_GE CPSR_GE 1514 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1515 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1516 #define XPSR_IT_0_1 CPSR_IT_0_1 1517 #define XPSR_Q CPSR_Q 1518 #define XPSR_V CPSR_V 1519 #define XPSR_C CPSR_C 1520 #define XPSR_Z CPSR_Z 1521 #define XPSR_N CPSR_N 1522 #define XPSR_NZCV CPSR_NZCV 1523 #define XPSR_IT CPSR_IT 1524 1525 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1526 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1527 #define TTBCR_PD0 (1U << 4) 1528 #define TTBCR_PD1 (1U << 5) 1529 #define TTBCR_EPD0 (1U << 7) 1530 #define TTBCR_IRGN0 (3U << 8) 1531 #define TTBCR_ORGN0 (3U << 10) 1532 #define TTBCR_SH0 (3U << 12) 1533 #define TTBCR_T1SZ (3U << 16) 1534 #define TTBCR_A1 (1U << 22) 1535 #define TTBCR_EPD1 (1U << 23) 1536 #define TTBCR_IRGN1 (3U << 24) 1537 #define TTBCR_ORGN1 (3U << 26) 1538 #define TTBCR_SH1 (1U << 28) 1539 #define TTBCR_EAE (1U << 31) 1540 1541 FIELD(VTCR, T0SZ, 0, 6) 1542 FIELD(VTCR, SL0, 6, 2) 1543 FIELD(VTCR, IRGN0, 8, 2) 1544 FIELD(VTCR, ORGN0, 10, 2) 1545 FIELD(VTCR, SH0, 12, 2) 1546 FIELD(VTCR, TG0, 14, 2) 1547 FIELD(VTCR, PS, 16, 3) 1548 FIELD(VTCR, VS, 19, 1) 1549 FIELD(VTCR, HA, 21, 1) 1550 FIELD(VTCR, HD, 22, 1) 1551 FIELD(VTCR, HWU59, 25, 1) 1552 FIELD(VTCR, HWU60, 26, 1) 1553 FIELD(VTCR, HWU61, 27, 1) 1554 FIELD(VTCR, HWU62, 28, 1) 1555 FIELD(VTCR, NSW, 29, 1) 1556 FIELD(VTCR, NSA, 30, 1) 1557 FIELD(VTCR, DS, 32, 1) 1558 FIELD(VTCR, SL2, 33, 1) 1559 1560 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1561 * Only these are valid when in AArch64 mode; in 1562 * AArch32 mode SPSRs are basically CPSR-format. 1563 */ 1564 #define PSTATE_SP (1U) 1565 #define PSTATE_M (0xFU) 1566 #define PSTATE_nRW (1U << 4) 1567 #define PSTATE_F (1U << 6) 1568 #define PSTATE_I (1U << 7) 1569 #define PSTATE_A (1U << 8) 1570 #define PSTATE_D (1U << 9) 1571 #define PSTATE_BTYPE (3U << 10) 1572 #define PSTATE_SSBS (1U << 12) 1573 #define PSTATE_IL (1U << 20) 1574 #define PSTATE_SS (1U << 21) 1575 #define PSTATE_PAN (1U << 22) 1576 #define PSTATE_UAO (1U << 23) 1577 #define PSTATE_DIT (1U << 24) 1578 #define PSTATE_TCO (1U << 25) 1579 #define PSTATE_V (1U << 28) 1580 #define PSTATE_C (1U << 29) 1581 #define PSTATE_Z (1U << 30) 1582 #define PSTATE_N (1U << 31) 1583 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1584 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1585 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1586 /* Mode values for AArch64 */ 1587 #define PSTATE_MODE_EL3h 13 1588 #define PSTATE_MODE_EL3t 12 1589 #define PSTATE_MODE_EL2h 9 1590 #define PSTATE_MODE_EL2t 8 1591 #define PSTATE_MODE_EL1h 5 1592 #define PSTATE_MODE_EL1t 4 1593 #define PSTATE_MODE_EL0t 0 1594 1595 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1596 FIELD(SVCR, SM, 0, 1) 1597 FIELD(SVCR, ZA, 1, 1) 1598 1599 /* Fields for SMCR_ELx. */ 1600 FIELD(SMCR, LEN, 0, 4) 1601 FIELD(SMCR, FA64, 31, 1) 1602 1603 /* Write a new value to v7m.exception, thus transitioning into or out 1604 * of Handler mode; this may result in a change of active stack pointer. 1605 */ 1606 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1607 1608 /* Map EL and handler into a PSTATE_MODE. */ 1609 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1610 { 1611 return (el << 2) | handler; 1612 } 1613 1614 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1615 * interprocessing, so we don't attempt to sync with the cpsr state used by 1616 * the 32 bit decoder. 1617 */ 1618 static inline uint32_t pstate_read(CPUARMState *env) 1619 { 1620 int ZF; 1621 1622 ZF = (env->ZF == 0); 1623 return (env->NF & 0x80000000) | (ZF << 30) 1624 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1625 | env->pstate | env->daif | (env->btype << 10); 1626 } 1627 1628 static inline void pstate_write(CPUARMState *env, uint32_t val) 1629 { 1630 env->ZF = (~val) & PSTATE_Z; 1631 env->NF = val; 1632 env->CF = (val >> 29) & 1; 1633 env->VF = (val << 3) & 0x80000000; 1634 env->daif = val & PSTATE_DAIF; 1635 env->btype = (val >> 10) & 3; 1636 env->pstate = val & ~CACHED_PSTATE_BITS; 1637 } 1638 1639 /* Return the current CPSR value. */ 1640 uint32_t cpsr_read(CPUARMState *env); 1641 1642 typedef enum CPSRWriteType { 1643 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1644 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1645 CPSRWriteRaw = 2, 1646 /* trust values, no reg bank switch, no hflags rebuild */ 1647 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1648 } CPSRWriteType; 1649 1650 /* 1651 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1652 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1653 * correspond to TB flags bits cached in the hflags, unless @write_type 1654 * is CPSRWriteRaw. 1655 */ 1656 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1657 CPSRWriteType write_type); 1658 1659 /* Return the current xPSR value. */ 1660 static inline uint32_t xpsr_read(CPUARMState *env) 1661 { 1662 int ZF; 1663 ZF = (env->ZF == 0); 1664 return (env->NF & 0x80000000) | (ZF << 30) 1665 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1666 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1667 | ((env->condexec_bits & 0xfc) << 8) 1668 | (env->GE << 16) 1669 | env->v7m.exception; 1670 } 1671 1672 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1673 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1674 { 1675 if (mask & XPSR_NZCV) { 1676 env->ZF = (~val) & XPSR_Z; 1677 env->NF = val; 1678 env->CF = (val >> 29) & 1; 1679 env->VF = (val << 3) & 0x80000000; 1680 } 1681 if (mask & XPSR_Q) { 1682 env->QF = ((val & XPSR_Q) != 0); 1683 } 1684 if (mask & XPSR_GE) { 1685 env->GE = (val & XPSR_GE) >> 16; 1686 } 1687 #ifndef CONFIG_USER_ONLY 1688 if (mask & XPSR_T) { 1689 env->thumb = ((val & XPSR_T) != 0); 1690 } 1691 if (mask & XPSR_IT_0_1) { 1692 env->condexec_bits &= ~3; 1693 env->condexec_bits |= (val >> 25) & 3; 1694 } 1695 if (mask & XPSR_IT_2_7) { 1696 env->condexec_bits &= 3; 1697 env->condexec_bits |= (val >> 8) & 0xfc; 1698 } 1699 if (mask & XPSR_EXCP) { 1700 /* Note that this only happens on exception exit */ 1701 write_v7m_exception(env, val & XPSR_EXCP); 1702 } 1703 #endif 1704 } 1705 1706 #define HCR_VM (1ULL << 0) 1707 #define HCR_SWIO (1ULL << 1) 1708 #define HCR_PTW (1ULL << 2) 1709 #define HCR_FMO (1ULL << 3) 1710 #define HCR_IMO (1ULL << 4) 1711 #define HCR_AMO (1ULL << 5) 1712 #define HCR_VF (1ULL << 6) 1713 #define HCR_VI (1ULL << 7) 1714 #define HCR_VSE (1ULL << 8) 1715 #define HCR_FB (1ULL << 9) 1716 #define HCR_BSU_MASK (3ULL << 10) 1717 #define HCR_DC (1ULL << 12) 1718 #define HCR_TWI (1ULL << 13) 1719 #define HCR_TWE (1ULL << 14) 1720 #define HCR_TID0 (1ULL << 15) 1721 #define HCR_TID1 (1ULL << 16) 1722 #define HCR_TID2 (1ULL << 17) 1723 #define HCR_TID3 (1ULL << 18) 1724 #define HCR_TSC (1ULL << 19) 1725 #define HCR_TIDCP (1ULL << 20) 1726 #define HCR_TACR (1ULL << 21) 1727 #define HCR_TSW (1ULL << 22) 1728 #define HCR_TPCP (1ULL << 23) 1729 #define HCR_TPU (1ULL << 24) 1730 #define HCR_TTLB (1ULL << 25) 1731 #define HCR_TVM (1ULL << 26) 1732 #define HCR_TGE (1ULL << 27) 1733 #define HCR_TDZ (1ULL << 28) 1734 #define HCR_HCD (1ULL << 29) 1735 #define HCR_TRVM (1ULL << 30) 1736 #define HCR_RW (1ULL << 31) 1737 #define HCR_CD (1ULL << 32) 1738 #define HCR_ID (1ULL << 33) 1739 #define HCR_E2H (1ULL << 34) 1740 #define HCR_TLOR (1ULL << 35) 1741 #define HCR_TERR (1ULL << 36) 1742 #define HCR_TEA (1ULL << 37) 1743 #define HCR_MIOCNCE (1ULL << 38) 1744 #define HCR_TME (1ULL << 39) 1745 #define HCR_APK (1ULL << 40) 1746 #define HCR_API (1ULL << 41) 1747 #define HCR_NV (1ULL << 42) 1748 #define HCR_NV1 (1ULL << 43) 1749 #define HCR_AT (1ULL << 44) 1750 #define HCR_NV2 (1ULL << 45) 1751 #define HCR_FWB (1ULL << 46) 1752 #define HCR_FIEN (1ULL << 47) 1753 #define HCR_GPF (1ULL << 48) 1754 #define HCR_TID4 (1ULL << 49) 1755 #define HCR_TICAB (1ULL << 50) 1756 #define HCR_AMVOFFEN (1ULL << 51) 1757 #define HCR_TOCU (1ULL << 52) 1758 #define HCR_ENSCXT (1ULL << 53) 1759 #define HCR_TTLBIS (1ULL << 54) 1760 #define HCR_TTLBOS (1ULL << 55) 1761 #define HCR_ATA (1ULL << 56) 1762 #define HCR_DCT (1ULL << 57) 1763 #define HCR_TID5 (1ULL << 58) 1764 #define HCR_TWEDEN (1ULL << 59) 1765 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1766 1767 #define HCRX_ENAS0 (1ULL << 0) 1768 #define HCRX_ENALS (1ULL << 1) 1769 #define HCRX_ENASR (1ULL << 2) 1770 #define HCRX_FNXS (1ULL << 3) 1771 #define HCRX_FGTNXS (1ULL << 4) 1772 #define HCRX_SMPME (1ULL << 5) 1773 #define HCRX_TALLINT (1ULL << 6) 1774 #define HCRX_VINMI (1ULL << 7) 1775 #define HCRX_VFNMI (1ULL << 8) 1776 #define HCRX_CMOW (1ULL << 9) 1777 #define HCRX_MCE2 (1ULL << 10) 1778 #define HCRX_MSCEN (1ULL << 11) 1779 1780 #define HPFAR_NS (1ULL << 63) 1781 1782 #define SCR_NS (1ULL << 0) 1783 #define SCR_IRQ (1ULL << 1) 1784 #define SCR_FIQ (1ULL << 2) 1785 #define SCR_EA (1ULL << 3) 1786 #define SCR_FW (1ULL << 4) 1787 #define SCR_AW (1ULL << 5) 1788 #define SCR_NET (1ULL << 6) 1789 #define SCR_SMD (1ULL << 7) 1790 #define SCR_HCE (1ULL << 8) 1791 #define SCR_SIF (1ULL << 9) 1792 #define SCR_RW (1ULL << 10) 1793 #define SCR_ST (1ULL << 11) 1794 #define SCR_TWI (1ULL << 12) 1795 #define SCR_TWE (1ULL << 13) 1796 #define SCR_TLOR (1ULL << 14) 1797 #define SCR_TERR (1ULL << 15) 1798 #define SCR_APK (1ULL << 16) 1799 #define SCR_API (1ULL << 17) 1800 #define SCR_EEL2 (1ULL << 18) 1801 #define SCR_EASE (1ULL << 19) 1802 #define SCR_NMEA (1ULL << 20) 1803 #define SCR_FIEN (1ULL << 21) 1804 #define SCR_ENSCXT (1ULL << 25) 1805 #define SCR_ATA (1ULL << 26) 1806 #define SCR_FGTEN (1ULL << 27) 1807 #define SCR_ECVEN (1ULL << 28) 1808 #define SCR_TWEDEN (1ULL << 29) 1809 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1810 #define SCR_TME (1ULL << 34) 1811 #define SCR_AMVOFFEN (1ULL << 35) 1812 #define SCR_ENAS0 (1ULL << 36) 1813 #define SCR_ADEN (1ULL << 37) 1814 #define SCR_HXEN (1ULL << 38) 1815 #define SCR_TRNDR (1ULL << 40) 1816 #define SCR_ENTP2 (1ULL << 41) 1817 #define SCR_GPF (1ULL << 48) 1818 #define SCR_NSE (1ULL << 62) 1819 1820 #define HSTR_TTEE (1 << 16) 1821 #define HSTR_TJDBX (1 << 17) 1822 1823 #define CNTHCTL_CNTVMASK (1 << 18) 1824 #define CNTHCTL_CNTPMASK (1 << 19) 1825 1826 /* Return the current FPSCR value. */ 1827 uint32_t vfp_get_fpscr(CPUARMState *env); 1828 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1829 1830 /* FPCR, Floating Point Control Register 1831 * FPSR, Floating Poiht Status Register 1832 * 1833 * For A64 the FPSCR is split into two logically distinct registers, 1834 * FPCR and FPSR. However since they still use non-overlapping bits 1835 * we store the underlying state in fpscr and just mask on read/write. 1836 */ 1837 #define FPSR_MASK 0xf800009f 1838 #define FPCR_MASK 0x07ff9f00 1839 1840 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1841 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1842 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1843 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1844 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1845 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1846 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1847 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1848 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1849 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1850 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1851 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1852 #define FPCR_V (1 << 28) /* FP overflow flag */ 1853 #define FPCR_C (1 << 29) /* FP carry flag */ 1854 #define FPCR_Z (1 << 30) /* FP zero flag */ 1855 #define FPCR_N (1 << 31) /* FP negative flag */ 1856 1857 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1858 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1859 #define FPCR_LTPSIZE_LENGTH 3 1860 1861 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1862 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1863 1864 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1865 { 1866 return vfp_get_fpscr(env) & FPSR_MASK; 1867 } 1868 1869 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1870 { 1871 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1872 vfp_set_fpscr(env, new_fpscr); 1873 } 1874 1875 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1876 { 1877 return vfp_get_fpscr(env) & FPCR_MASK; 1878 } 1879 1880 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1881 { 1882 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1883 vfp_set_fpscr(env, new_fpscr); 1884 } 1885 1886 enum arm_cpu_mode { 1887 ARM_CPU_MODE_USR = 0x10, 1888 ARM_CPU_MODE_FIQ = 0x11, 1889 ARM_CPU_MODE_IRQ = 0x12, 1890 ARM_CPU_MODE_SVC = 0x13, 1891 ARM_CPU_MODE_MON = 0x16, 1892 ARM_CPU_MODE_ABT = 0x17, 1893 ARM_CPU_MODE_HYP = 0x1a, 1894 ARM_CPU_MODE_UND = 0x1b, 1895 ARM_CPU_MODE_SYS = 0x1f 1896 }; 1897 1898 /* VFP system registers. */ 1899 #define ARM_VFP_FPSID 0 1900 #define ARM_VFP_FPSCR 1 1901 #define ARM_VFP_MVFR2 5 1902 #define ARM_VFP_MVFR1 6 1903 #define ARM_VFP_MVFR0 7 1904 #define ARM_VFP_FPEXC 8 1905 #define ARM_VFP_FPINST 9 1906 #define ARM_VFP_FPINST2 10 1907 /* These ones are M-profile only */ 1908 #define ARM_VFP_FPSCR_NZCVQC 2 1909 #define ARM_VFP_VPR 12 1910 #define ARM_VFP_P0 13 1911 #define ARM_VFP_FPCXT_NS 14 1912 #define ARM_VFP_FPCXT_S 15 1913 1914 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1915 #define QEMU_VFP_FPSCR_NZCV 0xffff 1916 1917 /* iwMMXt coprocessor control registers. */ 1918 #define ARM_IWMMXT_wCID 0 1919 #define ARM_IWMMXT_wCon 1 1920 #define ARM_IWMMXT_wCSSF 2 1921 #define ARM_IWMMXT_wCASF 3 1922 #define ARM_IWMMXT_wCGR0 8 1923 #define ARM_IWMMXT_wCGR1 9 1924 #define ARM_IWMMXT_wCGR2 10 1925 #define ARM_IWMMXT_wCGR3 11 1926 1927 /* V7M CCR bits */ 1928 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1929 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1930 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1931 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1932 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1933 FIELD(V7M_CCR, STKALIGN, 9, 1) 1934 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1935 FIELD(V7M_CCR, DC, 16, 1) 1936 FIELD(V7M_CCR, IC, 17, 1) 1937 FIELD(V7M_CCR, BP, 18, 1) 1938 FIELD(V7M_CCR, LOB, 19, 1) 1939 FIELD(V7M_CCR, TRD, 20, 1) 1940 1941 /* V7M SCR bits */ 1942 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1943 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1944 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1945 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1946 1947 /* V7M AIRCR bits */ 1948 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1949 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1950 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1951 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1952 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1953 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1954 FIELD(V7M_AIRCR, PRIS, 14, 1) 1955 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1956 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1957 1958 /* V7M CFSR bits for MMFSR */ 1959 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1960 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1961 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1962 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1963 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1964 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1965 1966 /* V7M CFSR bits for BFSR */ 1967 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1968 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1969 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1970 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1971 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1972 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1973 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1974 1975 /* V7M CFSR bits for UFSR */ 1976 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1977 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1978 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1979 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1980 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1981 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1982 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1983 1984 /* V7M CFSR bit masks covering all of the subregister bits */ 1985 FIELD(V7M_CFSR, MMFSR, 0, 8) 1986 FIELD(V7M_CFSR, BFSR, 8, 8) 1987 FIELD(V7M_CFSR, UFSR, 16, 16) 1988 1989 /* V7M HFSR bits */ 1990 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1991 FIELD(V7M_HFSR, FORCED, 30, 1) 1992 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1993 1994 /* V7M DFSR bits */ 1995 FIELD(V7M_DFSR, HALTED, 0, 1) 1996 FIELD(V7M_DFSR, BKPT, 1, 1) 1997 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1998 FIELD(V7M_DFSR, VCATCH, 3, 1) 1999 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 2000 2001 /* V7M SFSR bits */ 2002 FIELD(V7M_SFSR, INVEP, 0, 1) 2003 FIELD(V7M_SFSR, INVIS, 1, 1) 2004 FIELD(V7M_SFSR, INVER, 2, 1) 2005 FIELD(V7M_SFSR, AUVIOL, 3, 1) 2006 FIELD(V7M_SFSR, INVTRAN, 4, 1) 2007 FIELD(V7M_SFSR, LSPERR, 5, 1) 2008 FIELD(V7M_SFSR, SFARVALID, 6, 1) 2009 FIELD(V7M_SFSR, LSERR, 7, 1) 2010 2011 /* v7M MPU_CTRL bits */ 2012 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 2013 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 2014 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 2015 2016 /* v7M CLIDR bits */ 2017 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 2018 FIELD(V7M_CLIDR, LOUIS, 21, 3) 2019 FIELD(V7M_CLIDR, LOC, 24, 3) 2020 FIELD(V7M_CLIDR, LOUU, 27, 3) 2021 FIELD(V7M_CLIDR, ICB, 30, 2) 2022 2023 FIELD(V7M_CSSELR, IND, 0, 1) 2024 FIELD(V7M_CSSELR, LEVEL, 1, 3) 2025 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 2026 * define a mask for this and check that it doesn't permit running off 2027 * the end of the array. 2028 */ 2029 FIELD(V7M_CSSELR, INDEX, 0, 4) 2030 2031 /* v7M FPCCR bits */ 2032 FIELD(V7M_FPCCR, LSPACT, 0, 1) 2033 FIELD(V7M_FPCCR, USER, 1, 1) 2034 FIELD(V7M_FPCCR, S, 2, 1) 2035 FIELD(V7M_FPCCR, THREAD, 3, 1) 2036 FIELD(V7M_FPCCR, HFRDY, 4, 1) 2037 FIELD(V7M_FPCCR, MMRDY, 5, 1) 2038 FIELD(V7M_FPCCR, BFRDY, 6, 1) 2039 FIELD(V7M_FPCCR, SFRDY, 7, 1) 2040 FIELD(V7M_FPCCR, MONRDY, 8, 1) 2041 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 2042 FIELD(V7M_FPCCR, UFRDY, 10, 1) 2043 FIELD(V7M_FPCCR, RES0, 11, 15) 2044 FIELD(V7M_FPCCR, TS, 26, 1) 2045 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 2046 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 2047 FIELD(V7M_FPCCR, LSPENS, 29, 1) 2048 FIELD(V7M_FPCCR, LSPEN, 30, 1) 2049 FIELD(V7M_FPCCR, ASPEN, 31, 1) 2050 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 2051 #define R_V7M_FPCCR_BANKED_MASK \ 2052 (R_V7M_FPCCR_LSPACT_MASK | \ 2053 R_V7M_FPCCR_USER_MASK | \ 2054 R_V7M_FPCCR_THREAD_MASK | \ 2055 R_V7M_FPCCR_MMRDY_MASK | \ 2056 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 2057 R_V7M_FPCCR_UFRDY_MASK | \ 2058 R_V7M_FPCCR_ASPEN_MASK) 2059 2060 /* v7M VPR bits */ 2061 FIELD(V7M_VPR, P0, 0, 16) 2062 FIELD(V7M_VPR, MASK01, 16, 4) 2063 FIELD(V7M_VPR, MASK23, 20, 4) 2064 2065 /* 2066 * System register ID fields. 2067 */ 2068 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 2069 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 2070 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 2071 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 2072 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 2073 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 2074 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 2075 FIELD(CLIDR_EL1, LOUIS, 21, 3) 2076 FIELD(CLIDR_EL1, LOC, 24, 3) 2077 FIELD(CLIDR_EL1, LOUU, 27, 3) 2078 FIELD(CLIDR_EL1, ICB, 30, 3) 2079 2080 /* When FEAT_CCIDX is implemented */ 2081 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 2082 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 2083 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 2084 2085 /* When FEAT_CCIDX is not implemented */ 2086 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 2087 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 2088 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 2089 2090 FIELD(CTR_EL0, IMINLINE, 0, 4) 2091 FIELD(CTR_EL0, L1IP, 14, 2) 2092 FIELD(CTR_EL0, DMINLINE, 16, 4) 2093 FIELD(CTR_EL0, ERG, 20, 4) 2094 FIELD(CTR_EL0, CWG, 24, 4) 2095 FIELD(CTR_EL0, IDC, 28, 1) 2096 FIELD(CTR_EL0, DIC, 29, 1) 2097 FIELD(CTR_EL0, TMINLINE, 32, 6) 2098 2099 FIELD(MIDR_EL1, REVISION, 0, 4) 2100 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2101 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2102 FIELD(MIDR_EL1, VARIANT, 20, 4) 2103 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2104 2105 FIELD(ID_ISAR0, SWAP, 0, 4) 2106 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2107 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2108 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2109 FIELD(ID_ISAR0, COPROC, 16, 4) 2110 FIELD(ID_ISAR0, DEBUG, 20, 4) 2111 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2112 2113 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2114 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2115 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2116 FIELD(ID_ISAR1, EXTEND, 12, 4) 2117 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2118 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2119 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2120 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2121 2122 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2123 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2124 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2125 FIELD(ID_ISAR2, MULT, 12, 4) 2126 FIELD(ID_ISAR2, MULTS, 16, 4) 2127 FIELD(ID_ISAR2, MULTU, 20, 4) 2128 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2129 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2130 2131 FIELD(ID_ISAR3, SATURATE, 0, 4) 2132 FIELD(ID_ISAR3, SIMD, 4, 4) 2133 FIELD(ID_ISAR3, SVC, 8, 4) 2134 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2135 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2136 FIELD(ID_ISAR3, T32COPY, 20, 4) 2137 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2138 FIELD(ID_ISAR3, T32EE, 28, 4) 2139 2140 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2141 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2142 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2143 FIELD(ID_ISAR4, SMC, 12, 4) 2144 FIELD(ID_ISAR4, BARRIER, 16, 4) 2145 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2146 FIELD(ID_ISAR4, PSR_M, 24, 4) 2147 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2148 2149 FIELD(ID_ISAR5, SEVL, 0, 4) 2150 FIELD(ID_ISAR5, AES, 4, 4) 2151 FIELD(ID_ISAR5, SHA1, 8, 4) 2152 FIELD(ID_ISAR5, SHA2, 12, 4) 2153 FIELD(ID_ISAR5, CRC32, 16, 4) 2154 FIELD(ID_ISAR5, RDM, 24, 4) 2155 FIELD(ID_ISAR5, VCMA, 28, 4) 2156 2157 FIELD(ID_ISAR6, JSCVT, 0, 4) 2158 FIELD(ID_ISAR6, DP, 4, 4) 2159 FIELD(ID_ISAR6, FHM, 8, 4) 2160 FIELD(ID_ISAR6, SB, 12, 4) 2161 FIELD(ID_ISAR6, SPECRES, 16, 4) 2162 FIELD(ID_ISAR6, BF16, 20, 4) 2163 FIELD(ID_ISAR6, I8MM, 24, 4) 2164 2165 FIELD(ID_MMFR0, VMSA, 0, 4) 2166 FIELD(ID_MMFR0, PMSA, 4, 4) 2167 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2168 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2169 FIELD(ID_MMFR0, TCM, 16, 4) 2170 FIELD(ID_MMFR0, AUXREG, 20, 4) 2171 FIELD(ID_MMFR0, FCSE, 24, 4) 2172 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2173 2174 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2175 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2176 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2177 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2178 FIELD(ID_MMFR1, L1HVD, 16, 4) 2179 FIELD(ID_MMFR1, L1UNI, 20, 4) 2180 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2181 FIELD(ID_MMFR1, BPRED, 28, 4) 2182 2183 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2184 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2185 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2186 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2187 FIELD(ID_MMFR2, UNITLB, 16, 4) 2188 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2189 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2190 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2191 2192 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2193 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2194 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2195 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2196 FIELD(ID_MMFR3, PAN, 16, 4) 2197 FIELD(ID_MMFR3, COHWALK, 20, 4) 2198 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2199 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2200 2201 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2202 FIELD(ID_MMFR4, AC2, 4, 4) 2203 FIELD(ID_MMFR4, XNX, 8, 4) 2204 FIELD(ID_MMFR4, CNP, 12, 4) 2205 FIELD(ID_MMFR4, HPDS, 16, 4) 2206 FIELD(ID_MMFR4, LSM, 20, 4) 2207 FIELD(ID_MMFR4, CCIDX, 24, 4) 2208 FIELD(ID_MMFR4, EVT, 28, 4) 2209 2210 FIELD(ID_MMFR5, ETS, 0, 4) 2211 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2212 2213 FIELD(ID_PFR0, STATE0, 0, 4) 2214 FIELD(ID_PFR0, STATE1, 4, 4) 2215 FIELD(ID_PFR0, STATE2, 8, 4) 2216 FIELD(ID_PFR0, STATE3, 12, 4) 2217 FIELD(ID_PFR0, CSV2, 16, 4) 2218 FIELD(ID_PFR0, AMU, 20, 4) 2219 FIELD(ID_PFR0, DIT, 24, 4) 2220 FIELD(ID_PFR0, RAS, 28, 4) 2221 2222 FIELD(ID_PFR1, PROGMOD, 0, 4) 2223 FIELD(ID_PFR1, SECURITY, 4, 4) 2224 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2225 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2226 FIELD(ID_PFR1, GENTIMER, 16, 4) 2227 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2228 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2229 FIELD(ID_PFR1, GIC, 28, 4) 2230 2231 FIELD(ID_PFR2, CSV3, 0, 4) 2232 FIELD(ID_PFR2, SSBS, 4, 4) 2233 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2234 2235 FIELD(ID_AA64ISAR0, AES, 4, 4) 2236 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2237 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2238 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2239 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2240 FIELD(ID_AA64ISAR0, TME, 24, 4) 2241 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2242 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2243 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2244 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2245 FIELD(ID_AA64ISAR0, DP, 44, 4) 2246 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2247 FIELD(ID_AA64ISAR0, TS, 52, 4) 2248 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2249 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2250 2251 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2252 FIELD(ID_AA64ISAR1, APA, 4, 4) 2253 FIELD(ID_AA64ISAR1, API, 8, 4) 2254 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2255 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2256 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2257 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2258 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2259 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2260 FIELD(ID_AA64ISAR1, SB, 36, 4) 2261 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2262 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2263 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2264 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2265 FIELD(ID_AA64ISAR1, XS, 56, 4) 2266 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2267 2268 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2269 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2270 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2271 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2272 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2273 FIELD(ID_AA64ISAR2, BC, 20, 4) 2274 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2275 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2276 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2277 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2278 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2279 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2280 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2281 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2282 2283 FIELD(ID_AA64PFR0, EL0, 0, 4) 2284 FIELD(ID_AA64PFR0, EL1, 4, 4) 2285 FIELD(ID_AA64PFR0, EL2, 8, 4) 2286 FIELD(ID_AA64PFR0, EL3, 12, 4) 2287 FIELD(ID_AA64PFR0, FP, 16, 4) 2288 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2289 FIELD(ID_AA64PFR0, GIC, 24, 4) 2290 FIELD(ID_AA64PFR0, RAS, 28, 4) 2291 FIELD(ID_AA64PFR0, SVE, 32, 4) 2292 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2293 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2294 FIELD(ID_AA64PFR0, AMU, 44, 4) 2295 FIELD(ID_AA64PFR0, DIT, 48, 4) 2296 FIELD(ID_AA64PFR0, RME, 52, 4) 2297 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2298 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2299 2300 FIELD(ID_AA64PFR1, BT, 0, 4) 2301 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2302 FIELD(ID_AA64PFR1, MTE, 8, 4) 2303 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2304 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2305 FIELD(ID_AA64PFR1, SME, 24, 4) 2306 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2307 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2308 FIELD(ID_AA64PFR1, NMI, 36, 4) 2309 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2310 FIELD(ID_AA64PFR1, GCS, 44, 4) 2311 FIELD(ID_AA64PFR1, THE, 48, 4) 2312 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2313 FIELD(ID_AA64PFR1, DF2, 56, 4) 2314 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2315 2316 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2317 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2318 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2319 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2320 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2321 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2322 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2323 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2324 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2325 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2326 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2327 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2328 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2329 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2330 2331 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2332 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2333 FIELD(ID_AA64MMFR1, VH, 8, 4) 2334 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2335 FIELD(ID_AA64MMFR1, LO, 16, 4) 2336 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2337 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2338 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2339 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2340 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2341 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2342 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2343 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2344 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2345 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2346 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2347 2348 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2349 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2350 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2351 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2352 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2353 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2354 FIELD(ID_AA64MMFR2, NV, 24, 4) 2355 FIELD(ID_AA64MMFR2, ST, 28, 4) 2356 FIELD(ID_AA64MMFR2, AT, 32, 4) 2357 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2358 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2359 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2360 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2361 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2362 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2363 2364 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2365 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2366 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2367 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2368 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2369 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2370 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2371 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2372 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2373 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2374 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2375 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2376 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2377 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2378 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2379 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2380 2381 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2382 FIELD(ID_AA64ZFR0, AES, 4, 4) 2383 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2384 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2385 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2386 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2387 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2388 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2389 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2390 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2391 2392 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2393 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2394 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2395 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2396 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2397 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2398 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2399 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2400 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2401 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2402 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2403 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2404 2405 FIELD(ID_DFR0, COPDBG, 0, 4) 2406 FIELD(ID_DFR0, COPSDBG, 4, 4) 2407 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2408 FIELD(ID_DFR0, COPTRC, 12, 4) 2409 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2410 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2411 FIELD(ID_DFR0, PERFMON, 24, 4) 2412 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2413 2414 FIELD(ID_DFR1, MTPMU, 0, 4) 2415 FIELD(ID_DFR1, HPMN0, 4, 4) 2416 2417 FIELD(DBGDIDR, SE_IMP, 12, 1) 2418 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2419 FIELD(DBGDIDR, VERSION, 16, 4) 2420 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2421 FIELD(DBGDIDR, BRPS, 24, 4) 2422 FIELD(DBGDIDR, WRPS, 28, 4) 2423 2424 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2425 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2426 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2427 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2428 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2429 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2430 FIELD(DBGDEVID, AUXREGS, 24, 4) 2431 FIELD(DBGDEVID, CIDMASK, 28, 4) 2432 2433 FIELD(MVFR0, SIMDREG, 0, 4) 2434 FIELD(MVFR0, FPSP, 4, 4) 2435 FIELD(MVFR0, FPDP, 8, 4) 2436 FIELD(MVFR0, FPTRAP, 12, 4) 2437 FIELD(MVFR0, FPDIVIDE, 16, 4) 2438 FIELD(MVFR0, FPSQRT, 20, 4) 2439 FIELD(MVFR0, FPSHVEC, 24, 4) 2440 FIELD(MVFR0, FPROUND, 28, 4) 2441 2442 FIELD(MVFR1, FPFTZ, 0, 4) 2443 FIELD(MVFR1, FPDNAN, 4, 4) 2444 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2445 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2446 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2447 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2448 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2449 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2450 FIELD(MVFR1, FPHP, 24, 4) 2451 FIELD(MVFR1, SIMDFMAC, 28, 4) 2452 2453 FIELD(MVFR2, SIMDMISC, 0, 4) 2454 FIELD(MVFR2, FPMISC, 4, 4) 2455 2456 FIELD(GPCCR, PPS, 0, 3) 2457 FIELD(GPCCR, IRGN, 8, 2) 2458 FIELD(GPCCR, ORGN, 10, 2) 2459 FIELD(GPCCR, SH, 12, 2) 2460 FIELD(GPCCR, PGS, 14, 2) 2461 FIELD(GPCCR, GPC, 16, 1) 2462 FIELD(GPCCR, GPCP, 17, 1) 2463 FIELD(GPCCR, L0GPTSZ, 20, 4) 2464 2465 FIELD(MFAR, FPA, 12, 40) 2466 FIELD(MFAR, NSE, 62, 1) 2467 FIELD(MFAR, NS, 63, 1) 2468 2469 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2470 2471 /* If adding a feature bit which corresponds to a Linux ELF 2472 * HWCAP bit, remember to update the feature-bit-to-hwcap 2473 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2474 */ 2475 enum arm_features { 2476 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2477 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2478 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2479 ARM_FEATURE_V6, 2480 ARM_FEATURE_V6K, 2481 ARM_FEATURE_V7, 2482 ARM_FEATURE_THUMB2, 2483 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2484 ARM_FEATURE_NEON, 2485 ARM_FEATURE_M, /* Microcontroller profile. */ 2486 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2487 ARM_FEATURE_THUMB2EE, 2488 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2489 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2490 ARM_FEATURE_V4T, 2491 ARM_FEATURE_V5, 2492 ARM_FEATURE_STRONGARM, 2493 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2494 ARM_FEATURE_GENERIC_TIMER, 2495 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2496 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2497 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2498 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2499 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2500 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2501 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2502 ARM_FEATURE_V8, 2503 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2504 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2505 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2506 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2507 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2508 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2509 ARM_FEATURE_PMU, /* has PMU support */ 2510 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2511 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2512 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2513 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2514 }; 2515 2516 static inline int arm_feature(CPUARMState *env, int feature) 2517 { 2518 return (env->features & (1ULL << feature)) != 0; 2519 } 2520 2521 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2522 2523 /* 2524 * ARM v9 security states. 2525 * The ordering of the enumeration corresponds to the low 2 bits 2526 * of the GPI value, and (except for Root) the concat of NSE:NS. 2527 */ 2528 2529 typedef enum ARMSecuritySpace { 2530 ARMSS_Secure = 0, 2531 ARMSS_NonSecure = 1, 2532 ARMSS_Root = 2, 2533 ARMSS_Realm = 3, 2534 } ARMSecuritySpace; 2535 2536 /* Return true if @space is secure, in the pre-v9 sense. */ 2537 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2538 { 2539 return space == ARMSS_Secure || space == ARMSS_Root; 2540 } 2541 2542 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2543 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2544 { 2545 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2546 } 2547 2548 #if !defined(CONFIG_USER_ONLY) 2549 /** 2550 * arm_security_space_below_el3: 2551 * @env: cpu context 2552 * 2553 * Return the security space of exception levels below EL3, following 2554 * an exception return to those levels. Unlike arm_security_space, 2555 * this doesn't care about the current EL. 2556 */ 2557 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2558 2559 /** 2560 * arm_is_secure_below_el3: 2561 * @env: cpu context 2562 * 2563 * Return true if exception levels below EL3 are in secure state, 2564 * or would be following an exception return to those levels. 2565 */ 2566 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2567 { 2568 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2569 return ss == ARMSS_Secure; 2570 } 2571 2572 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2573 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2574 { 2575 assert(!arm_feature(env, ARM_FEATURE_M)); 2576 if (arm_feature(env, ARM_FEATURE_EL3)) { 2577 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2578 /* CPU currently in AArch64 state and EL3 */ 2579 return true; 2580 } else if (!is_a64(env) && 2581 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2582 /* CPU currently in AArch32 state and monitor mode */ 2583 return true; 2584 } 2585 } 2586 return false; 2587 } 2588 2589 /** 2590 * arm_security_space: 2591 * @env: cpu context 2592 * 2593 * Return the current security space of the cpu. 2594 */ 2595 ARMSecuritySpace arm_security_space(CPUARMState *env); 2596 2597 /** 2598 * arm_is_secure: 2599 * @env: cpu context 2600 * 2601 * Return true if the processor is in secure state. 2602 */ 2603 static inline bool arm_is_secure(CPUARMState *env) 2604 { 2605 return arm_space_is_secure(arm_security_space(env)); 2606 } 2607 2608 /* 2609 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2610 * This corresponds to the pseudocode EL2Enabled(). 2611 */ 2612 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2613 ARMSecuritySpace space) 2614 { 2615 assert(space != ARMSS_Root); 2616 return arm_feature(env, ARM_FEATURE_EL2) 2617 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2618 } 2619 2620 static inline bool arm_is_el2_enabled(CPUARMState *env) 2621 { 2622 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2623 } 2624 2625 #else 2626 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2627 { 2628 return ARMSS_NonSecure; 2629 } 2630 2631 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2632 { 2633 return false; 2634 } 2635 2636 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2637 { 2638 return ARMSS_NonSecure; 2639 } 2640 2641 static inline bool arm_is_secure(CPUARMState *env) 2642 { 2643 return false; 2644 } 2645 2646 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2647 ARMSecuritySpace space) 2648 { 2649 return false; 2650 } 2651 2652 static inline bool arm_is_el2_enabled(CPUARMState *env) 2653 { 2654 return false; 2655 } 2656 #endif 2657 2658 /** 2659 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2660 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2661 * "for all purposes other than a direct read or write access of HCR_EL2." 2662 * Not included here is HCR_RW. 2663 */ 2664 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2665 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2666 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2667 2668 /* Return true if the specified exception level is running in AArch64 state. */ 2669 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2670 { 2671 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2672 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2673 */ 2674 assert(el >= 1 && el <= 3); 2675 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2676 2677 /* The highest exception level is always at the maximum supported 2678 * register width, and then lower levels have a register width controlled 2679 * by bits in the SCR or HCR registers. 2680 */ 2681 if (el == 3) { 2682 return aa64; 2683 } 2684 2685 if (arm_feature(env, ARM_FEATURE_EL3) && 2686 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2687 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2688 } 2689 2690 if (el == 2) { 2691 return aa64; 2692 } 2693 2694 if (arm_is_el2_enabled(env)) { 2695 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2696 } 2697 2698 return aa64; 2699 } 2700 2701 /* Function for determining whether guest cp register reads and writes should 2702 * access the secure or non-secure bank of a cp register. When EL3 is 2703 * operating in AArch32 state, the NS-bit determines whether the secure 2704 * instance of a cp register should be used. When EL3 is AArch64 (or if 2705 * it doesn't exist at all) then there is no register banking, and all 2706 * accesses are to the non-secure version. 2707 */ 2708 static inline bool access_secure_reg(CPUARMState *env) 2709 { 2710 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2711 !arm_el_is_aa64(env, 3) && 2712 !(env->cp15.scr_el3 & SCR_NS)); 2713 2714 return ret; 2715 } 2716 2717 /* Macros for accessing a specified CP register bank */ 2718 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2719 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2720 2721 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2722 do { \ 2723 if (_secure) { \ 2724 (_env)->cp15._regname##_s = (_val); \ 2725 } else { \ 2726 (_env)->cp15._regname##_ns = (_val); \ 2727 } \ 2728 } while (0) 2729 2730 /* Macros for automatically accessing a specific CP register bank depending on 2731 * the current secure state of the system. These macros are not intended for 2732 * supporting instruction translation reads/writes as these are dependent 2733 * solely on the SCR.NS bit and not the mode. 2734 */ 2735 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2736 A32_BANKED_REG_GET((_env), _regname, \ 2737 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2738 2739 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2740 A32_BANKED_REG_SET((_env), _regname, \ 2741 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2742 (_val)) 2743 2744 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2745 uint32_t cur_el, bool secure); 2746 2747 /* Return the highest implemented Exception Level */ 2748 static inline int arm_highest_el(CPUARMState *env) 2749 { 2750 if (arm_feature(env, ARM_FEATURE_EL3)) { 2751 return 3; 2752 } 2753 if (arm_feature(env, ARM_FEATURE_EL2)) { 2754 return 2; 2755 } 2756 return 1; 2757 } 2758 2759 /* Return true if a v7M CPU is in Handler mode */ 2760 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2761 { 2762 return env->v7m.exception != 0; 2763 } 2764 2765 /* Return the current Exception Level (as per ARMv8; note that this differs 2766 * from the ARMv7 Privilege Level). 2767 */ 2768 static inline int arm_current_el(CPUARMState *env) 2769 { 2770 if (arm_feature(env, ARM_FEATURE_M)) { 2771 return arm_v7m_is_handler_mode(env) || 2772 !(env->v7m.control[env->v7m.secure] & 1); 2773 } 2774 2775 if (is_a64(env)) { 2776 return extract32(env->pstate, 2, 2); 2777 } 2778 2779 switch (env->uncached_cpsr & 0x1f) { 2780 case ARM_CPU_MODE_USR: 2781 return 0; 2782 case ARM_CPU_MODE_HYP: 2783 return 2; 2784 case ARM_CPU_MODE_MON: 2785 return 3; 2786 default: 2787 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2788 /* If EL3 is 32-bit then all secure privileged modes run in 2789 * EL3 2790 */ 2791 return 3; 2792 } 2793 2794 return 1; 2795 } 2796 } 2797 2798 /** 2799 * write_list_to_cpustate 2800 * @cpu: ARMCPU 2801 * 2802 * For each register listed in the ARMCPU cpreg_indexes list, write 2803 * its value from the cpreg_values list into the ARMCPUState structure. 2804 * This updates TCG's working data structures from KVM data or 2805 * from incoming migration state. 2806 * 2807 * Returns: true if all register values were updated correctly, 2808 * false if some register was unknown or could not be written. 2809 * Note that we do not stop early on failure -- we will attempt 2810 * writing all registers in the list. 2811 */ 2812 bool write_list_to_cpustate(ARMCPU *cpu); 2813 2814 /** 2815 * write_cpustate_to_list: 2816 * @cpu: ARMCPU 2817 * @kvm_sync: true if this is for syncing back to KVM 2818 * 2819 * For each register listed in the ARMCPU cpreg_indexes list, write 2820 * its value from the ARMCPUState structure into the cpreg_values list. 2821 * This is used to copy info from TCG's working data structures into 2822 * KVM or for outbound migration. 2823 * 2824 * @kvm_sync is true if we are doing this in order to sync the 2825 * register state back to KVM. In this case we will only update 2826 * values in the list if the previous list->cpustate sync actually 2827 * successfully wrote the CPU state. Otherwise we will keep the value 2828 * that is in the list. 2829 * 2830 * Returns: true if all register values were read correctly, 2831 * false if some register was unknown or could not be read. 2832 * Note that we do not stop early on failure -- we will attempt 2833 * reading all registers in the list. 2834 */ 2835 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2836 2837 #define ARM_CPUID_TI915T 0x54029152 2838 #define ARM_CPUID_TI925T 0x54029252 2839 2840 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2841 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2842 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2843 2844 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2845 2846 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2847 * 2848 * If EL3 is 64-bit: 2849 * + NonSecure EL1 & 0 stage 1 2850 * + NonSecure EL1 & 0 stage 2 2851 * + NonSecure EL2 2852 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2853 * + Secure EL1 & 0 2854 * + Secure EL3 2855 * If EL3 is 32-bit: 2856 * + NonSecure PL1 & 0 stage 1 2857 * + NonSecure PL1 & 0 stage 2 2858 * + NonSecure PL2 2859 * + Secure PL0 2860 * + Secure PL1 2861 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2862 * 2863 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2864 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2865 * because they may differ in access permissions even if the VA->PA map is 2866 * the same 2867 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2868 * translation, which means that we have one mmu_idx that deals with two 2869 * concatenated translation regimes [this sort of combined s1+2 TLB is 2870 * architecturally permitted] 2871 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2872 * handling via the TLB. The only way to do a stage 1 translation without 2873 * the immediate stage 2 translation is via the ATS or AT system insns, 2874 * which can be slow-pathed and always do a page table walk. 2875 * The only use of stage 2 translations is either as part of an s1+2 2876 * lookup or when loading the descriptors during a stage 1 page table walk, 2877 * and in both those cases we don't use the TLB. 2878 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2879 * translation regimes, because they map reasonably well to each other 2880 * and they can't both be active at the same time. 2881 * 5. we want to be able to use the TLB for accesses done as part of a 2882 * stage1 page table walk, rather than having to walk the stage2 page 2883 * table over and over. 2884 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2885 * Never (PAN) bit within PSTATE. 2886 * 7. we fold together the secure and non-secure regimes for A-profile, 2887 * because there are no banked system registers for aarch64, so the 2888 * process of switching between secure and non-secure is 2889 * already heavyweight. 2890 * 2891 * This gives us the following list of cases: 2892 * 2893 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2894 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2895 * EL1 EL1&0 stage 1+2 +PAN 2896 * EL0 EL2&0 2897 * EL2 EL2&0 2898 * EL2 EL2&0 +PAN 2899 * EL2 (aka NS PL2) 2900 * EL3 (aka S PL1) 2901 * Physical (NS & S) 2902 * Stage2 (NS & S) 2903 * 2904 * for a total of 12 different mmu_idx. 2905 * 2906 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2907 * as A profile. They only need to distinguish EL0 and EL1 (and 2908 * EL2 if we ever model a Cortex-R52). 2909 * 2910 * M profile CPUs are rather different as they do not have a true MMU. 2911 * They have the following different MMU indexes: 2912 * User 2913 * Privileged 2914 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2915 * Privileged, execution priority negative (ditto) 2916 * If the CPU supports the v8M Security Extension then there are also: 2917 * Secure User 2918 * Secure Privileged 2919 * Secure User, execution priority negative 2920 * Secure Privileged, execution priority negative 2921 * 2922 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2923 * are not quite the same -- different CPU types (most notably M profile 2924 * vs A/R profile) would like to use MMU indexes with different semantics, 2925 * but since we don't ever need to use all of those in a single CPU we 2926 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2927 * modes + total number of M profile MMU modes". The lower bits of 2928 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2929 * the same for any particular CPU. 2930 * Variables of type ARMMUIdx are always full values, and the core 2931 * index values are in variables of type 'int'. 2932 * 2933 * Our enumeration includes at the end some entries which are not "true" 2934 * mmu_idx values in that they don't have corresponding TLBs and are only 2935 * valid for doing slow path page table walks. 2936 * 2937 * The constant names here are patterned after the general style of the names 2938 * of the AT/ATS operations. 2939 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2940 * For M profile we arrange them to have a bit for priv, a bit for negpri 2941 * and a bit for secure. 2942 */ 2943 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2944 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2945 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2946 2947 /* Meanings of the bits for M profile mmu idx values */ 2948 #define ARM_MMU_IDX_M_PRIV 0x1 2949 #define ARM_MMU_IDX_M_NEGPRI 0x2 2950 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2951 2952 #define ARM_MMU_IDX_TYPE_MASK \ 2953 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2954 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2955 2956 typedef enum ARMMMUIdx { 2957 /* 2958 * A-profile. 2959 */ 2960 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2961 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2962 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2963 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2964 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2965 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2966 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2967 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2968 2969 /* 2970 * Used for second stage of an S12 page table walk, or for descriptor 2971 * loads during first stage of an S1 page table walk. Note that both 2972 * are in use simultaneously for SecureEL2: the security state for 2973 * the S2 ptw is selected by the NS bit from the S1 ptw. 2974 */ 2975 ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A, 2976 ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, 2977 2978 /* TLBs with 1-1 mapping to the physical address spaces. */ 2979 ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, 2980 ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, 2981 ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, 2982 ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, 2983 2984 /* 2985 * These are not allocated TLBs and are used only for AT system 2986 * instructions or for the first stage of an S12 page table walk. 2987 */ 2988 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2989 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2990 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2991 2992 /* 2993 * M-profile. 2994 */ 2995 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2996 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2997 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2998 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2999 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 3000 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 3001 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 3002 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 3003 } ARMMMUIdx; 3004 3005 /* 3006 * Bit macros for the core-mmu-index values for each index, 3007 * for use when calling tlb_flush_by_mmuidx() and friends. 3008 */ 3009 #define TO_CORE_BIT(NAME) \ 3010 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 3011 3012 typedef enum ARMMMUIdxBit { 3013 TO_CORE_BIT(E10_0), 3014 TO_CORE_BIT(E20_0), 3015 TO_CORE_BIT(E10_1), 3016 TO_CORE_BIT(E10_1_PAN), 3017 TO_CORE_BIT(E2), 3018 TO_CORE_BIT(E20_2), 3019 TO_CORE_BIT(E20_2_PAN), 3020 TO_CORE_BIT(E3), 3021 TO_CORE_BIT(Stage2), 3022 TO_CORE_BIT(Stage2_S), 3023 3024 TO_CORE_BIT(MUser), 3025 TO_CORE_BIT(MPriv), 3026 TO_CORE_BIT(MUserNegPri), 3027 TO_CORE_BIT(MPrivNegPri), 3028 TO_CORE_BIT(MSUser), 3029 TO_CORE_BIT(MSPriv), 3030 TO_CORE_BIT(MSUserNegPri), 3031 TO_CORE_BIT(MSPrivNegPri), 3032 } ARMMMUIdxBit; 3033 3034 #undef TO_CORE_BIT 3035 3036 #define MMU_USER_IDX 0 3037 3038 /* Indexes used when registering address spaces with cpu_address_space_init */ 3039 typedef enum ARMASIdx { 3040 ARMASIdx_NS = 0, 3041 ARMASIdx_S = 1, 3042 ARMASIdx_TagNS = 2, 3043 ARMASIdx_TagS = 3, 3044 } ARMASIdx; 3045 3046 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 3047 { 3048 /* Assert the relative order of the physical mmu indexes. */ 3049 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 3050 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 3051 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 3052 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 3053 3054 return ARMMMUIdx_Phys_S + space; 3055 } 3056 3057 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 3058 { 3059 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 3060 return idx - ARMMMUIdx_Phys_S; 3061 } 3062 3063 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3064 { 3065 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3066 * CSSELR is RAZ/WI. 3067 */ 3068 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3069 } 3070 3071 static inline bool arm_sctlr_b(CPUARMState *env) 3072 { 3073 return 3074 /* We need not implement SCTLR.ITD in user-mode emulation, so 3075 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3076 * This lets people run BE32 binaries with "-cpu any". 3077 */ 3078 #ifndef CONFIG_USER_ONLY 3079 !arm_feature(env, ARM_FEATURE_V7) && 3080 #endif 3081 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3082 } 3083 3084 uint64_t arm_sctlr(CPUARMState *env, int el); 3085 3086 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3087 bool sctlr_b) 3088 { 3089 #ifdef CONFIG_USER_ONLY 3090 /* 3091 * In system mode, BE32 is modelled in line with the 3092 * architecture (as word-invariant big-endianness), where loads 3093 * and stores are done little endian but from addresses which 3094 * are adjusted by XORing with the appropriate constant. So the 3095 * endianness to use for the raw data access is not affected by 3096 * SCTLR.B. 3097 * In user mode, however, we model BE32 as byte-invariant 3098 * big-endianness (because user-only code cannot tell the 3099 * difference), and so we need to use a data access endianness 3100 * that depends on SCTLR.B. 3101 */ 3102 if (sctlr_b) { 3103 return true; 3104 } 3105 #endif 3106 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3107 return env->uncached_cpsr & CPSR_E; 3108 } 3109 3110 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3111 { 3112 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3113 } 3114 3115 /* Return true if the processor is in big-endian mode. */ 3116 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3117 { 3118 if (!is_a64(env)) { 3119 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3120 } else { 3121 int cur_el = arm_current_el(env); 3122 uint64_t sctlr = arm_sctlr(env, cur_el); 3123 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3124 } 3125 } 3126 3127 #include "exec/cpu-all.h" 3128 3129 /* 3130 * We have more than 32-bits worth of state per TB, so we split the data 3131 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3132 * We collect these two parts in CPUARMTBFlags where they are named 3133 * flags and flags2 respectively. 3134 * 3135 * The flags that are shared between all execution modes, TBFLAG_ANY, 3136 * are stored in flags. The flags that are specific to a given mode 3137 * are stores in flags2. Since cs_base is sized on the configured 3138 * address size, flags2 always has 64-bits for A64, and a minimum of 3139 * 32-bits for A32 and M32. 3140 * 3141 * The bits for 32-bit A-profile and M-profile partially overlap: 3142 * 3143 * 31 23 11 10 0 3144 * +-------------+----------+----------------+ 3145 * | | | TBFLAG_A32 | 3146 * | TBFLAG_AM32 | +-----+----------+ 3147 * | | |TBFLAG_M32| 3148 * +-------------+----------------+----------+ 3149 * 31 23 6 5 0 3150 * 3151 * Unless otherwise noted, these bits are cached in env->hflags. 3152 */ 3153 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3154 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3155 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3156 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3157 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3158 /* Target EL if we take a floating-point-disabled exception */ 3159 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3160 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3161 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3162 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3163 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3164 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3165 3166 /* 3167 * Bit usage when in AArch32 state, both A- and M-profile. 3168 */ 3169 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3170 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3171 3172 /* 3173 * Bit usage when in AArch32 state, for A-profile only. 3174 */ 3175 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3176 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3177 /* 3178 * We store the bottom two bits of the CPAR as TB flags and handle 3179 * checks on the other bits at runtime. This shares the same bits as 3180 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3181 * Not cached, because VECLEN+VECSTRIDE are not cached. 3182 */ 3183 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3184 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3185 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3186 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3187 /* 3188 * Indicates whether cp register reads and writes by guest code should access 3189 * the secure or nonsecure bank of banked registers; note that this is not 3190 * the same thing as the current security state of the processor! 3191 */ 3192 FIELD(TBFLAG_A32, NS, 10, 1) 3193 /* 3194 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3195 * This requires an SME trap from AArch32 mode when using NEON. 3196 */ 3197 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3198 3199 /* 3200 * Bit usage when in AArch32 state, for M-profile only. 3201 */ 3202 /* Handler (ie not Thread) mode */ 3203 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3204 /* Whether we should generate stack-limit checks */ 3205 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3206 /* Set if FPCCR.LSPACT is set */ 3207 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3208 /* Set if we must create a new FP context */ 3209 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3210 /* Set if FPCCR.S does not match current security state */ 3211 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3212 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3213 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3214 /* Set if in secure mode */ 3215 FIELD(TBFLAG_M32, SECURE, 6, 1) 3216 3217 /* 3218 * Bit usage when in AArch64 state 3219 */ 3220 FIELD(TBFLAG_A64, TBII, 0, 2) 3221 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3222 /* The current vector length, either NVL or SVL. */ 3223 FIELD(TBFLAG_A64, VL, 4, 4) 3224 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3225 FIELD(TBFLAG_A64, BT, 9, 1) 3226 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3227 FIELD(TBFLAG_A64, TBID, 12, 2) 3228 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3229 FIELD(TBFLAG_A64, ATA, 15, 1) 3230 FIELD(TBFLAG_A64, TCMA, 16, 2) 3231 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3232 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3233 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3234 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3235 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3236 FIELD(TBFLAG_A64, SVL, 24, 4) 3237 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3238 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3239 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 3240 FIELD(TBFLAG_A64, NAA, 30, 1) 3241 FIELD(TBFLAG_A64, ATA0, 31, 1) 3242 FIELD(TBFLAG_A64, NV, 32, 1) 3243 FIELD(TBFLAG_A64, NV1, 33, 1) 3244 FIELD(TBFLAG_A64, NV2, 34, 1) 3245 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ 3246 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) 3247 /* Set if FEAT_NV2 RAM accesses are big-endian */ 3248 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 3249 3250 /* 3251 * Helpers for using the above. Note that only the A64 accessors use 3252 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 3253 * word either is or might be 32 bits only. 3254 */ 3255 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3256 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3257 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3258 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3259 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3260 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3261 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3262 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3263 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3264 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3265 3266 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3267 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 3268 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3269 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3270 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3271 3272 /** 3273 * cpu_mmu_index: 3274 * @env: The cpu environment 3275 * @ifetch: True for code access, false for data access. 3276 * 3277 * Return the core mmu index for the current translation regime. 3278 * This function is used by generic TCG code paths. 3279 */ 3280 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3281 { 3282 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3283 } 3284 3285 /** 3286 * sve_vq 3287 * @env: the cpu context 3288 * 3289 * Return the VL cached within env->hflags, in units of quadwords. 3290 */ 3291 static inline int sve_vq(CPUARMState *env) 3292 { 3293 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3294 } 3295 3296 /** 3297 * sme_vq 3298 * @env: the cpu context 3299 * 3300 * Return the SVL cached within env->hflags, in units of quadwords. 3301 */ 3302 static inline int sme_vq(CPUARMState *env) 3303 { 3304 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3305 } 3306 3307 static inline bool bswap_code(bool sctlr_b) 3308 { 3309 #ifdef CONFIG_USER_ONLY 3310 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3311 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3312 * would also end up as a mixed-endian mode with BE code, LE data. 3313 */ 3314 return TARGET_BIG_ENDIAN ^ sctlr_b; 3315 #else 3316 /* All code access in ARM is little endian, and there are no loaders 3317 * doing swaps that need to be reversed 3318 */ 3319 return 0; 3320 #endif 3321 } 3322 3323 #ifdef CONFIG_USER_ONLY 3324 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3325 { 3326 return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); 3327 } 3328 #endif 3329 3330 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, 3331 uint64_t *cs_base, uint32_t *flags); 3332 3333 enum { 3334 QEMU_PSCI_CONDUIT_DISABLED = 0, 3335 QEMU_PSCI_CONDUIT_SMC = 1, 3336 QEMU_PSCI_CONDUIT_HVC = 2, 3337 }; 3338 3339 #ifndef CONFIG_USER_ONLY 3340 /* Return the address space index to use for a memory access */ 3341 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3342 { 3343 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3344 } 3345 3346 /* Return the AddressSpace to use for a memory access 3347 * (which depends on whether the access is S or NS, and whether 3348 * the board gave us a separate AddressSpace for S accesses). 3349 */ 3350 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3351 { 3352 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3353 } 3354 #endif 3355 3356 /** 3357 * arm_register_pre_el_change_hook: 3358 * Register a hook function which will be called immediately before this 3359 * CPU changes exception level or mode. The hook function will be 3360 * passed a pointer to the ARMCPU and the opaque data pointer passed 3361 * to this function when the hook was registered. 3362 * 3363 * Note that if a pre-change hook is called, any registered post-change hooks 3364 * are guaranteed to subsequently be called. 3365 */ 3366 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3367 void *opaque); 3368 /** 3369 * arm_register_el_change_hook: 3370 * Register a hook function which will be called immediately after this 3371 * CPU changes exception level or mode. The hook function will be 3372 * passed a pointer to the ARMCPU and the opaque data pointer passed 3373 * to this function when the hook was registered. 3374 * 3375 * Note that any registered hooks registered here are guaranteed to be called 3376 * if pre-change hooks have been. 3377 */ 3378 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3379 *opaque); 3380 3381 /** 3382 * arm_rebuild_hflags: 3383 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3384 */ 3385 void arm_rebuild_hflags(CPUARMState *env); 3386 3387 /** 3388 * aa32_vfp_dreg: 3389 * Return a pointer to the Dn register within env in 32-bit mode. 3390 */ 3391 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3392 { 3393 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3394 } 3395 3396 /** 3397 * aa32_vfp_qreg: 3398 * Return a pointer to the Qn register within env in 32-bit mode. 3399 */ 3400 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3401 { 3402 return &env->vfp.zregs[regno].d[0]; 3403 } 3404 3405 /** 3406 * aa64_vfp_qreg: 3407 * Return a pointer to the Qn register within env in 64-bit mode. 3408 */ 3409 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3410 { 3411 return &env->vfp.zregs[regno].d[0]; 3412 } 3413 3414 /* Shared between translate-sve.c and sve_helper.c. */ 3415 extern const uint64_t pred_esz_masks[5]; 3416 3417 /* 3418 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3419 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3420 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3421 */ 3422 #define PAGE_BTI PAGE_TARGET_1 3423 #define PAGE_MTE PAGE_TARGET_2 3424 #define PAGE_TARGET_STICKY PAGE_MTE 3425 3426 /* We associate one allocation tag per 16 bytes, the minimum. */ 3427 #define LOG2_TAG_GRANULE 4 3428 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3429 3430 #ifdef CONFIG_USER_ONLY 3431 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3432 #endif 3433 3434 #ifdef TARGET_TAGGED_ADDRESSES 3435 /** 3436 * cpu_untagged_addr: 3437 * @cs: CPU context 3438 * @x: tagged address 3439 * 3440 * Remove any address tag from @x. This is explicitly related to the 3441 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3442 * 3443 * There should be a better place to put this, but we need this in 3444 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3445 */ 3446 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3447 { 3448 ARMCPU *cpu = ARM_CPU(cs); 3449 if (cpu->env.tagged_addr_enable) { 3450 /* 3451 * TBI is enabled for userspace but not kernelspace addresses. 3452 * Only clear the tag if bit 55 is clear. 3453 */ 3454 x &= sextract64(x, 0, 56); 3455 } 3456 return x; 3457 } 3458 #endif 3459 3460 #endif 3461