xref: /openbmc/qemu/target/arm/cpu.h (revision e0091133)
1 /*
2  * ARM virtual CPU header
3  *
4  *  Copyright (c) 2003 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef ARM_CPU_H
21 #define ARM_CPU_H
22 
23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
25 #include "hw/registerfields.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-defs.h"
28 #include "qapi/qapi-types-common.h"
29 
30 /* ARM processors have a weak memory model */
31 #define TCG_GUEST_DEFAULT_MO      (0)
32 
33 #ifdef TARGET_AARCH64
34 #define KVM_HAVE_MCE_INJECTION 1
35 #endif
36 
37 #define EXCP_UDEF            1   /* undefined instruction */
38 #define EXCP_SWI             2   /* software interrupt */
39 #define EXCP_PREFETCH_ABORT  3
40 #define EXCP_DATA_ABORT      4
41 #define EXCP_IRQ             5
42 #define EXCP_FIQ             6
43 #define EXCP_BKPT            7
44 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
45 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
46 #define EXCP_HVC            11   /* HyperVisor Call */
47 #define EXCP_HYP_TRAP       12
48 #define EXCP_SMC            13   /* Secure Monitor Call */
49 #define EXCP_VIRQ           14
50 #define EXCP_VFIQ           15
51 #define EXCP_SEMIHOST       16   /* semihosting call */
52 #define EXCP_NOCP           17   /* v7M NOCP UsageFault */
53 #define EXCP_INVSTATE       18   /* v7M INVSTATE UsageFault */
54 #define EXCP_STKOF          19   /* v8M STKOF UsageFault */
55 #define EXCP_LAZYFP         20   /* v7M fault during lazy FP stacking */
56 #define EXCP_LSERR          21   /* v8M LSERR SecureFault */
57 #define EXCP_UNALIGNED      22   /* v7M UNALIGNED UsageFault */
58 #define EXCP_DIVBYZERO      23   /* v7M DIVBYZERO UsageFault */
59 #define EXCP_VSERR          24
60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
61 
62 #define ARMV7M_EXCP_RESET   1
63 #define ARMV7M_EXCP_NMI     2
64 #define ARMV7M_EXCP_HARD    3
65 #define ARMV7M_EXCP_MEM     4
66 #define ARMV7M_EXCP_BUS     5
67 #define ARMV7M_EXCP_USAGE   6
68 #define ARMV7M_EXCP_SECURE  7
69 #define ARMV7M_EXCP_SVC     11
70 #define ARMV7M_EXCP_DEBUG   12
71 #define ARMV7M_EXCP_PENDSV  14
72 #define ARMV7M_EXCP_SYSTICK 15
73 
74 /* For M profile, some registers are banked secure vs non-secure;
75  * these are represented as a 2-element array where the first element
76  * is the non-secure copy and the second is the secure copy.
77  * When the CPU does not have implement the security extension then
78  * only the first element is used.
79  * This means that the copy for the current security state can be
80  * accessed via env->registerfield[env->v7m.secure] (whether the security
81  * extension is implemented or not).
82  */
83 enum {
84     M_REG_NS = 0,
85     M_REG_S = 1,
86     M_REG_NUM_BANKS = 2,
87 };
88 
89 /* ARM-specific interrupt pending bits.  */
90 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
91 #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
92 #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
94 
95 /* The usual mapping for an AArch64 system register to its AArch32
96  * counterpart is for the 32 bit world to have access to the lower
97  * half only (with writes leaving the upper half untouched). It's
98  * therefore useful to be able to pass TCG the offset of the least
99  * significant half of a uint64_t struct member.
100  */
101 #if HOST_BIG_ENDIAN
102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
103 #define offsetofhigh32(S, M) offsetof(S, M)
104 #else
105 #define offsetoflow32(S, M) offsetof(S, M)
106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
107 #endif
108 
109 /* Meanings of the ARMCPU object's four inbound GPIO lines */
110 #define ARM_CPU_IRQ 0
111 #define ARM_CPU_FIQ 1
112 #define ARM_CPU_VIRQ 2
113 #define ARM_CPU_VFIQ 3
114 
115 /* ARM-specific extra insn start words:
116  * 1: Conditional execution bits
117  * 2: Partial exception syndrome for data aborts
118  */
119 #define TARGET_INSN_START_EXTRA_WORDS 2
120 
121 /* The 2nd extra word holding syndrome info for data aborts does not use
122  * the upper 6 bits nor the lower 14 bits. We mask and shift it down to
123  * help the sleb128 encoder do a better job.
124  * When restoring the CPU state, we shift it back up.
125  */
126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
127 #define ARM_INSN_START_WORD2_SHIFT 14
128 
129 /* We currently assume float and double are IEEE single and double
130    precision respectively.
131    Doing runtime conversions is tricky because VFP registers may contain
132    integer values (eg. as the result of a FTOSI instruction).
133    s<2n> maps to the least significant half of d<n>
134    s<2n+1> maps to the most significant half of d<n>
135  */
136 
137 /**
138  * DynamicGDBXMLInfo:
139  * @desc: Contains the XML descriptions.
140  * @num: Number of the registers in this XML seen by GDB.
141  * @data: A union with data specific to the set of registers
142  *    @cpregs_keys: Array that contains the corresponding Key of
143  *                  a given cpreg with the same order of the cpreg
144  *                  in the XML description.
145  */
146 typedef struct DynamicGDBXMLInfo {
147     char *desc;
148     int num;
149     union {
150         struct {
151             uint32_t *keys;
152         } cpregs;
153     } data;
154 } DynamicGDBXMLInfo;
155 
156 /* CPU state for each instance of a generic timer (in cp15 c14) */
157 typedef struct ARMGenericTimer {
158     uint64_t cval; /* Timer CompareValue register */
159     uint64_t ctl; /* Timer Control register */
160 } ARMGenericTimer;
161 
162 #define GTIMER_PHYS     0
163 #define GTIMER_VIRT     1
164 #define GTIMER_HYP      2
165 #define GTIMER_SEC      3
166 #define GTIMER_HYPVIRT  4
167 #define NUM_GTIMERS     5
168 
169 #define VTCR_NSW (1u << 29)
170 #define VTCR_NSA (1u << 30)
171 #define VSTCR_SW VTCR_NSW
172 #define VSTCR_SA VTCR_NSA
173 
174 /* Define a maximum sized vector register.
175  * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
176  * For 64-bit, this is a 2048-bit SVE register.
177  *
178  * Note that the mapping between S, D, and Q views of the register bank
179  * differs between AArch64 and AArch32.
180  * In AArch32:
181  *  Qn = regs[n].d[1]:regs[n].d[0]
182  *  Dn = regs[n / 2].d[n & 1]
183  *  Sn = regs[n / 4].d[n % 4 / 2],
184  *       bits 31..0 for even n, and bits 63..32 for odd n
185  *       (and regs[16] to regs[31] are inaccessible)
186  * In AArch64:
187  *  Zn = regs[n].d[*]
188  *  Qn = regs[n].d[1]:regs[n].d[0]
189  *  Dn = regs[n].d[0]
190  *  Sn = regs[n].d[0] bits 31..0
191  *  Hn = regs[n].d[0] bits 15..0
192  *
193  * This corresponds to the architecturally defined mapping between
194  * the two execution states, and means we do not need to explicitly
195  * map these registers when changing states.
196  *
197  * Align the data for use with TCG host vector operations.
198  */
199 
200 #ifdef TARGET_AARCH64
201 # define ARM_MAX_VQ    16
202 #else
203 # define ARM_MAX_VQ    1
204 #endif
205 
206 typedef struct ARMVectorReg {
207     uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
208 } ARMVectorReg;
209 
210 #ifdef TARGET_AARCH64
211 /* In AArch32 mode, predicate registers do not exist at all.  */
212 typedef struct ARMPredicateReg {
213     uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
214 } ARMPredicateReg;
215 
216 /* In AArch32 mode, PAC keys do not exist at all.  */
217 typedef struct ARMPACKey {
218     uint64_t lo, hi;
219 } ARMPACKey;
220 #endif
221 
222 /* See the commentary above the TBFLAG field definitions.  */
223 typedef struct CPUARMTBFlags {
224     uint32_t flags;
225     target_ulong flags2;
226 } CPUARMTBFlags;
227 
228 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
229 
230 typedef struct CPUArchState {
231     /* Regs for current mode.  */
232     uint32_t regs[16];
233 
234     /* 32/64 switch only happens when taking and returning from
235      * exceptions so the overlap semantics are taken care of then
236      * instead of having a complicated union.
237      */
238     /* Regs for A64 mode.  */
239     uint64_t xregs[32];
240     uint64_t pc;
241     /* PSTATE isn't an architectural register for ARMv8. However, it is
242      * convenient for us to assemble the underlying state into a 32 bit format
243      * identical to the architectural format used for the SPSR. (This is also
244      * what the Linux kernel's 'pstate' field in signal handlers and KVM's
245      * 'pstate' register are.) Of the PSTATE bits:
246      *  NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
247      *    semantics as for AArch32, as described in the comments on each field)
248      *  nRW (also known as M[4]) is kept, inverted, in env->aarch64
249      *  DAIF (exception masks) are kept in env->daif
250      *  BTYPE is kept in env->btype
251      *  SM and ZA are kept in env->svcr
252      *  all other bits are stored in their correct places in env->pstate
253      */
254     uint32_t pstate;
255     bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */
256     bool thumb;   /* True if CPU is in thumb mode; cpsr[5] */
257 
258     /* Cached TBFLAGS state.  See below for which bits are included.  */
259     CPUARMTBFlags hflags;
260 
261     /* Frequently accessed CPSR bits are stored separately for efficiency.
262        This contains all the other bits.  Use cpsr_{read,write} to access
263        the whole CPSR.  */
264     uint32_t uncached_cpsr;
265     uint32_t spsr;
266 
267     /* Banked registers.  */
268     uint64_t banked_spsr[8];
269     uint32_t banked_r13[8];
270     uint32_t banked_r14[8];
271 
272     /* These hold r8-r12.  */
273     uint32_t usr_regs[5];
274     uint32_t fiq_regs[5];
275 
276     /* cpsr flag cache for faster execution */
277     uint32_t CF; /* 0 or 1 */
278     uint32_t VF; /* V is the bit 31. All other bits are undefined */
279     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
280     uint32_t ZF; /* Z set if zero.  */
281     uint32_t QF; /* 0 or 1 */
282     uint32_t GE; /* cpsr[19:16] */
283     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
284     uint32_t btype;  /* BTI branch type.  spsr[11:10].  */
285     uint64_t daif; /* exception masks, in the bits they are in PSTATE */
286     uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */
287 
288     uint64_t elr_el[4]; /* AArch64 exception link regs  */
289     uint64_t sp_el[4]; /* AArch64 banked stack pointers */
290 
291     /* System control coprocessor (cp15) */
292     struct {
293         uint32_t c0_cpuid;
294         union { /* Cache size selection */
295             struct {
296                 uint64_t _unused_csselr0;
297                 uint64_t csselr_ns;
298                 uint64_t _unused_csselr1;
299                 uint64_t csselr_s;
300             };
301             uint64_t csselr_el[4];
302         };
303         union { /* System control register. */
304             struct {
305                 uint64_t _unused_sctlr;
306                 uint64_t sctlr_ns;
307                 uint64_t hsctlr;
308                 uint64_t sctlr_s;
309             };
310             uint64_t sctlr_el[4];
311         };
312         uint64_t cpacr_el1; /* Architectural feature access control register */
313         uint64_t cptr_el[4];  /* ARMv8 feature trap registers */
314         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
315         uint64_t sder; /* Secure debug enable register. */
316         uint32_t nsacr; /* Non-secure access control register. */
317         union { /* MMU translation table base 0. */
318             struct {
319                 uint64_t _unused_ttbr0_0;
320                 uint64_t ttbr0_ns;
321                 uint64_t _unused_ttbr0_1;
322                 uint64_t ttbr0_s;
323             };
324             uint64_t ttbr0_el[4];
325         };
326         union { /* MMU translation table base 1. */
327             struct {
328                 uint64_t _unused_ttbr1_0;
329                 uint64_t ttbr1_ns;
330                 uint64_t _unused_ttbr1_1;
331                 uint64_t ttbr1_s;
332             };
333             uint64_t ttbr1_el[4];
334         };
335         uint64_t vttbr_el2; /* Virtualization Translation Table Base.  */
336         uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */
337         /* MMU translation table base control. */
338         uint64_t tcr_el[4];
339         uint64_t vtcr_el2; /* Virtualization Translation Control.  */
340         uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */
341         uint32_t c2_data; /* MPU data cacheable bits.  */
342         uint32_t c2_insn; /* MPU instruction cacheable bits.  */
343         union { /* MMU domain access control register
344                  * MPU write buffer control.
345                  */
346             struct {
347                 uint64_t dacr_ns;
348                 uint64_t dacr_s;
349             };
350             struct {
351                 uint64_t dacr32_el2;
352             };
353         };
354         uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
355         uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
356         uint64_t hcr_el2; /* Hypervisor configuration register */
357         uint64_t hcrx_el2; /* Extended Hypervisor configuration register */
358         uint64_t scr_el3; /* Secure configuration register.  */
359         union { /* Fault status registers.  */
360             struct {
361                 uint64_t ifsr_ns;
362                 uint64_t ifsr_s;
363             };
364             struct {
365                 uint64_t ifsr32_el2;
366             };
367         };
368         union {
369             struct {
370                 uint64_t _unused_dfsr;
371                 uint64_t dfsr_ns;
372                 uint64_t hsr;
373                 uint64_t dfsr_s;
374             };
375             uint64_t esr_el[4];
376         };
377         uint32_t c6_region[8]; /* MPU base/size registers.  */
378         union { /* Fault address registers. */
379             struct {
380                 uint64_t _unused_far0;
381 #if HOST_BIG_ENDIAN
382                 uint32_t ifar_ns;
383                 uint32_t dfar_ns;
384                 uint32_t ifar_s;
385                 uint32_t dfar_s;
386 #else
387                 uint32_t dfar_ns;
388                 uint32_t ifar_ns;
389                 uint32_t dfar_s;
390                 uint32_t ifar_s;
391 #endif
392                 uint64_t _unused_far3;
393             };
394             uint64_t far_el[4];
395         };
396         uint64_t hpfar_el2;
397         uint64_t hstr_el2;
398         union { /* Translation result. */
399             struct {
400                 uint64_t _unused_par_0;
401                 uint64_t par_ns;
402                 uint64_t _unused_par_1;
403                 uint64_t par_s;
404             };
405             uint64_t par_el[4];
406         };
407 
408         uint32_t c9_insn; /* Cache lockdown registers.  */
409         uint32_t c9_data;
410         uint64_t c9_pmcr; /* performance monitor control register */
411         uint64_t c9_pmcnten; /* perf monitor counter enables */
412         uint64_t c9_pmovsr; /* perf monitor overflow status */
413         uint64_t c9_pmuserenr; /* perf monitor user enable */
414         uint64_t c9_pmselr; /* perf monitor counter selection register */
415         uint64_t c9_pminten; /* perf monitor interrupt enables */
416         union { /* Memory attribute redirection */
417             struct {
418 #if HOST_BIG_ENDIAN
419                 uint64_t _unused_mair_0;
420                 uint32_t mair1_ns;
421                 uint32_t mair0_ns;
422                 uint64_t _unused_mair_1;
423                 uint32_t mair1_s;
424                 uint32_t mair0_s;
425 #else
426                 uint64_t _unused_mair_0;
427                 uint32_t mair0_ns;
428                 uint32_t mair1_ns;
429                 uint64_t _unused_mair_1;
430                 uint32_t mair0_s;
431                 uint32_t mair1_s;
432 #endif
433             };
434             uint64_t mair_el[4];
435         };
436         union { /* vector base address register */
437             struct {
438                 uint64_t _unused_vbar;
439                 uint64_t vbar_ns;
440                 uint64_t hvbar;
441                 uint64_t vbar_s;
442             };
443             uint64_t vbar_el[4];
444         };
445         uint32_t mvbar; /* (monitor) vector base address register */
446         uint64_t rvbar; /* rvbar sampled from rvbar property at reset */
447         struct { /* FCSE PID. */
448             uint32_t fcseidr_ns;
449             uint32_t fcseidr_s;
450         };
451         union { /* Context ID. */
452             struct {
453                 uint64_t _unused_contextidr_0;
454                 uint64_t contextidr_ns;
455                 uint64_t _unused_contextidr_1;
456                 uint64_t contextidr_s;
457             };
458             uint64_t contextidr_el[4];
459         };
460         union { /* User RW Thread register. */
461             struct {
462                 uint64_t tpidrurw_ns;
463                 uint64_t tpidrprw_ns;
464                 uint64_t htpidr;
465                 uint64_t _tpidr_el3;
466             };
467             uint64_t tpidr_el[4];
468         };
469         uint64_t tpidr2_el0;
470         /* The secure banks of these registers don't map anywhere */
471         uint64_t tpidrurw_s;
472         uint64_t tpidrprw_s;
473         uint64_t tpidruro_s;
474 
475         union { /* User RO Thread register. */
476             uint64_t tpidruro_ns;
477             uint64_t tpidrro_el[1];
478         };
479         uint64_t c14_cntfrq; /* Counter Frequency register */
480         uint64_t c14_cntkctl; /* Timer Control register */
481         uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
482         uint64_t cntvoff_el2; /* Counter Virtual Offset register */
483         ARMGenericTimer c14_timer[NUM_GTIMERS];
484         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
485         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
486         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
487         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
488         uint32_t c15_threadid; /* TI debugger thread-ID.  */
489         uint32_t c15_config_base_address; /* SCU base address.  */
490         uint32_t c15_diagnostic; /* diagnostic register */
491         uint32_t c15_power_diagnostic;
492         uint32_t c15_power_control; /* power control */
493         uint64_t dbgbvr[16]; /* breakpoint value registers */
494         uint64_t dbgbcr[16]; /* breakpoint control registers */
495         uint64_t dbgwvr[16]; /* watchpoint value registers */
496         uint64_t dbgwcr[16]; /* watchpoint control registers */
497         uint64_t mdscr_el1;
498         uint64_t oslsr_el1; /* OS Lock Status */
499         uint64_t osdlr_el1; /* OS DoubleLock status */
500         uint64_t mdcr_el2;
501         uint64_t mdcr_el3;
502         /* Stores the architectural value of the counter *the last time it was
503          * updated* by pmccntr_op_start. Accesses should always be surrounded
504          * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
505          * architecturally-correct value is being read/set.
506          */
507         uint64_t c15_ccnt;
508         /* Stores the delta between the architectural value and the underlying
509          * cycle count during normal operation. It is used to update c15_ccnt
510          * to be the correct architectural value before accesses. During
511          * accesses, c15_ccnt_delta contains the underlying count being used
512          * for the access, after which it reverts to the delta value in
513          * pmccntr_op_finish.
514          */
515         uint64_t c15_ccnt_delta;
516         uint64_t c14_pmevcntr[31];
517         uint64_t c14_pmevcntr_delta[31];
518         uint64_t c14_pmevtyper[31];
519         uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
520         uint64_t vpidr_el2; /* Virtualization Processor ID Register */
521         uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
522         uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0.  */
523         uint64_t gcr_el1;
524         uint64_t rgsr_el1;
525 
526         /* Minimal RAS registers */
527         uint64_t disr_el1;
528         uint64_t vdisr_el2;
529         uint64_t vsesr_el2;
530     } cp15;
531 
532     struct {
533         /* M profile has up to 4 stack pointers:
534          * a Main Stack Pointer and a Process Stack Pointer for each
535          * of the Secure and Non-Secure states. (If the CPU doesn't support
536          * the security extension then it has only two SPs.)
537          * In QEMU we always store the currently active SP in regs[13],
538          * and the non-active SP for the current security state in
539          * v7m.other_sp. The stack pointers for the inactive security state
540          * are stored in other_ss_msp and other_ss_psp.
541          * switch_v7m_security_state() is responsible for rearranging them
542          * when we change security state.
543          */
544         uint32_t other_sp;
545         uint32_t other_ss_msp;
546         uint32_t other_ss_psp;
547         uint32_t vecbase[M_REG_NUM_BANKS];
548         uint32_t basepri[M_REG_NUM_BANKS];
549         uint32_t control[M_REG_NUM_BANKS];
550         uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
551         uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
552         uint32_t hfsr; /* HardFault Status */
553         uint32_t dfsr; /* Debug Fault Status Register */
554         uint32_t sfsr; /* Secure Fault Status Register */
555         uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
556         uint32_t bfar; /* BusFault Address */
557         uint32_t sfar; /* Secure Fault Address Register */
558         unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
559         int exception;
560         uint32_t primask[M_REG_NUM_BANKS];
561         uint32_t faultmask[M_REG_NUM_BANKS];
562         uint32_t aircr; /* only holds r/w state if security extn implemented */
563         uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
564         uint32_t csselr[M_REG_NUM_BANKS];
565         uint32_t scr[M_REG_NUM_BANKS];
566         uint32_t msplim[M_REG_NUM_BANKS];
567         uint32_t psplim[M_REG_NUM_BANKS];
568         uint32_t fpcar[M_REG_NUM_BANKS];
569         uint32_t fpccr[M_REG_NUM_BANKS];
570         uint32_t fpdscr[M_REG_NUM_BANKS];
571         uint32_t cpacr[M_REG_NUM_BANKS];
572         uint32_t nsacr;
573         uint32_t ltpsize;
574         uint32_t vpr;
575     } v7m;
576 
577     /* Information associated with an exception about to be taken:
578      * code which raises an exception must set cs->exception_index and
579      * the relevant parts of this structure; the cpu_do_interrupt function
580      * will then set the guest-visible registers as part of the exception
581      * entry process.
582      */
583     struct {
584         uint32_t syndrome; /* AArch64 format syndrome register */
585         uint32_t fsr; /* AArch32 format fault status register info */
586         uint64_t vaddress; /* virtual addr associated with exception, if any */
587         uint32_t target_el; /* EL the exception should be targeted for */
588         /* If we implement EL2 we will also need to store information
589          * about the intermediate physical address for stage 2 faults.
590          */
591     } exception;
592 
593     /* Information associated with an SError */
594     struct {
595         uint8_t pending;
596         uint8_t has_esr;
597         uint64_t esr;
598     } serror;
599 
600     uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
601 
602     /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
603     uint32_t irq_line_state;
604 
605     /* Thumb-2 EE state.  */
606     uint32_t teecr;
607     uint32_t teehbr;
608 
609     /* VFP coprocessor state.  */
610     struct {
611         ARMVectorReg zregs[32];
612 
613 #ifdef TARGET_AARCH64
614         /* Store FFR as pregs[16] to make it easier to treat as any other.  */
615 #define FFR_PRED_NUM 16
616         ARMPredicateReg pregs[17];
617         /* Scratch space for aa64 sve predicate temporary.  */
618         ARMPredicateReg preg_tmp;
619 #endif
620 
621         /* We store these fpcsr fields separately for convenience.  */
622         uint32_t qc[4] QEMU_ALIGNED(16);
623         int vec_len;
624         int vec_stride;
625 
626         uint32_t xregs[16];
627 
628         /* Scratch space for aa32 neon expansion.  */
629         uint32_t scratch[8];
630 
631         /* There are a number of distinct float control structures:
632          *
633          *  fp_status: is the "normal" fp status.
634          *  fp_status_fp16: used for half-precision calculations
635          *  standard_fp_status : the ARM "Standard FPSCR Value"
636          *  standard_fp_status_fp16 : used for half-precision
637          *       calculations with the ARM "Standard FPSCR Value"
638          *
639          * Half-precision operations are governed by a separate
640          * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
641          * status structure to control this.
642          *
643          * The "Standard FPSCR", ie default-NaN, flush-to-zero,
644          * round-to-nearest and is used by any operations (generally
645          * Neon) which the architecture defines as controlled by the
646          * standard FPSCR value rather than the FPSCR.
647          *
648          * The "standard FPSCR but for fp16 ops" is needed because
649          * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than
650          * using a fixed value for it.
651          *
652          * To avoid having to transfer exception bits around, we simply
653          * say that the FPSCR cumulative exception flags are the logical
654          * OR of the flags in the four fp statuses. This relies on the
655          * only thing which needs to read the exception flags being
656          * an explicit FPSCR read.
657          */
658         float_status fp_status;
659         float_status fp_status_f16;
660         float_status standard_fp_status;
661         float_status standard_fp_status_f16;
662 
663         uint64_t zcr_el[4];   /* ZCR_EL[1-3] */
664         uint64_t smcr_el[4];  /* SMCR_EL[1-3] */
665     } vfp;
666     uint64_t exclusive_addr;
667     uint64_t exclusive_val;
668     uint64_t exclusive_high;
669 
670     /* iwMMXt coprocessor state.  */
671     struct {
672         uint64_t regs[16];
673         uint64_t val;
674 
675         uint32_t cregs[16];
676     } iwmmxt;
677 
678 #ifdef TARGET_AARCH64
679     struct {
680         ARMPACKey apia;
681         ARMPACKey apib;
682         ARMPACKey apda;
683         ARMPACKey apdb;
684         ARMPACKey apga;
685     } keys;
686 
687     uint64_t scxtnum_el[4];
688 
689     /*
690      * SME ZA storage -- 256 x 256 byte array, with bytes in host word order,
691      * as we do with vfp.zregs[].  This corresponds to the architectural ZA
692      * array, where ZA[N] is in the least-significant bytes of env->zarray[N].
693      * When SVL is less than the architectural maximum, the accessible
694      * storage is restricted, such that if the SVL is X bytes the guest can
695      * see only the bottom X elements of zarray[], and only the least
696      * significant X bytes of each element of the array. (In other words,
697      * the observable part is always square.)
698      *
699      * The ZA storage can also be considered as a set of square tiles of
700      * elements of different sizes. The mapping from tiles to the ZA array
701      * is architecturally defined, such that for tiles of elements of esz
702      * bytes, the Nth row (or "horizontal slice") of tile T is in
703      * ZA[T + N * esz]. Note that this means that each tile is not contiguous
704      * in the ZA storage, because its rows are striped through the ZA array.
705      *
706      * Because this is so large, keep this toward the end of the reset area,
707      * to keep the offsets into the rest of the structure smaller.
708      */
709     ARMVectorReg zarray[ARM_MAX_VQ * 16];
710 #endif
711 
712 #if defined(CONFIG_USER_ONLY)
713     /* For usermode syscall translation.  */
714     int eabi;
715 #endif
716 
717     struct CPUBreakpoint *cpu_breakpoint[16];
718     struct CPUWatchpoint *cpu_watchpoint[16];
719 
720     /* Optional fault info across tlb lookup. */
721     ARMMMUFaultInfo *tlb_fi;
722 
723     /* Fields up to this point are cleared by a CPU reset */
724     struct {} end_reset_fields;
725 
726     /* Fields after this point are preserved across CPU reset. */
727 
728     /* Internal CPU feature flags.  */
729     uint64_t features;
730 
731     /* PMSAv7 MPU */
732     struct {
733         uint32_t *drbar;
734         uint32_t *drsr;
735         uint32_t *dracr;
736         uint32_t rnr[M_REG_NUM_BANKS];
737     } pmsav7;
738 
739     /* PMSAv8 MPU */
740     struct {
741         /* The PMSAv8 implementation also shares some PMSAv7 config
742          * and state:
743          *  pmsav7.rnr (region number register)
744          *  pmsav7_dregion (number of configured regions)
745          */
746         uint32_t *rbar[M_REG_NUM_BANKS];
747         uint32_t *rlar[M_REG_NUM_BANKS];
748         uint32_t mair0[M_REG_NUM_BANKS];
749         uint32_t mair1[M_REG_NUM_BANKS];
750     } pmsav8;
751 
752     /* v8M SAU */
753     struct {
754         uint32_t *rbar;
755         uint32_t *rlar;
756         uint32_t rnr;
757         uint32_t ctrl;
758     } sau;
759 
760     void *nvic;
761     const struct arm_boot_info *boot_info;
762     /* Store GICv3CPUState to access from this struct */
763     void *gicv3state;
764 
765 #ifdef TARGET_TAGGED_ADDRESSES
766     /* Linux syscall tagged address support */
767     bool tagged_addr_enable;
768 #endif
769 } CPUARMState;
770 
771 static inline void set_feature(CPUARMState *env, int feature)
772 {
773     env->features |= 1ULL << feature;
774 }
775 
776 static inline void unset_feature(CPUARMState *env, int feature)
777 {
778     env->features &= ~(1ULL << feature);
779 }
780 
781 /**
782  * ARMELChangeHookFn:
783  * type of a function which can be registered via arm_register_el_change_hook()
784  * to get callbacks when the CPU changes its exception level or mode.
785  */
786 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
787 typedef struct ARMELChangeHook ARMELChangeHook;
788 struct ARMELChangeHook {
789     ARMELChangeHookFn *hook;
790     void *opaque;
791     QLIST_ENTRY(ARMELChangeHook) node;
792 };
793 
794 /* These values map onto the return values for
795  * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
796 typedef enum ARMPSCIState {
797     PSCI_ON = 0,
798     PSCI_OFF = 1,
799     PSCI_ON_PENDING = 2
800 } ARMPSCIState;
801 
802 typedef struct ARMISARegisters ARMISARegisters;
803 
804 /*
805  * In map, each set bit is a supported vector length of (bit-number + 1) * 16
806  * bytes, i.e. each bit number + 1 is the vector length in quadwords.
807  *
808  * While processing properties during initialization, corresponding init bits
809  * are set for bits in sve_vq_map that have been set by properties.
810  *
811  * Bits set in supported represent valid vector lengths for the CPU type.
812  */
813 typedef struct {
814     uint32_t map, init, supported;
815 } ARMVQMap;
816 
817 /**
818  * ARMCPU:
819  * @env: #CPUARMState
820  *
821  * An ARM CPU core.
822  */
823 struct ArchCPU {
824     /*< private >*/
825     CPUState parent_obj;
826     /*< public >*/
827 
828     CPUNegativeOffsetState neg;
829     CPUARMState env;
830 
831     /* Coprocessor information */
832     GHashTable *cp_regs;
833     /* For marshalling (mostly coprocessor) register state between the
834      * kernel and QEMU (for KVM) and between two QEMUs (for migration),
835      * we use these arrays.
836      */
837     /* List of register indexes managed via these arrays; (full KVM style
838      * 64 bit indexes, not CPRegInfo 32 bit indexes)
839      */
840     uint64_t *cpreg_indexes;
841     /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
842     uint64_t *cpreg_values;
843     /* Length of the indexes, values, reset_values arrays */
844     int32_t cpreg_array_len;
845     /* These are used only for migration: incoming data arrives in
846      * these fields and is sanity checked in post_load before copying
847      * to the working data structures above.
848      */
849     uint64_t *cpreg_vmstate_indexes;
850     uint64_t *cpreg_vmstate_values;
851     int32_t cpreg_vmstate_array_len;
852 
853     DynamicGDBXMLInfo dyn_sysreg_xml;
854     DynamicGDBXMLInfo dyn_svereg_xml;
855 
856     /* Timers used by the generic (architected) timer */
857     QEMUTimer *gt_timer[NUM_GTIMERS];
858     /*
859      * Timer used by the PMU. Its state is restored after migration by
860      * pmu_op_finish() - it does not need other handling during migration
861      */
862     QEMUTimer *pmu_timer;
863     /* GPIO outputs for generic timer */
864     qemu_irq gt_timer_outputs[NUM_GTIMERS];
865     /* GPIO output for GICv3 maintenance interrupt signal */
866     qemu_irq gicv3_maintenance_interrupt;
867     /* GPIO output for the PMU interrupt */
868     qemu_irq pmu_interrupt;
869 
870     /* MemoryRegion to use for secure physical accesses */
871     MemoryRegion *secure_memory;
872 
873     /* MemoryRegion to use for allocation tag accesses */
874     MemoryRegion *tag_memory;
875     MemoryRegion *secure_tag_memory;
876 
877     /* For v8M, pointer to the IDAU interface provided by board/SoC */
878     Object *idau;
879 
880     /* 'compatible' string for this CPU for Linux device trees */
881     const char *dtb_compatible;
882 
883     /* PSCI version for this CPU
884      * Bits[31:16] = Major Version
885      * Bits[15:0] = Minor Version
886      */
887     uint32_t psci_version;
888 
889     /* Current power state, access guarded by BQL */
890     ARMPSCIState power_state;
891 
892     /* CPU has virtualization extension */
893     bool has_el2;
894     /* CPU has security extension */
895     bool has_el3;
896     /* CPU has PMU (Performance Monitor Unit) */
897     bool has_pmu;
898     /* CPU has VFP */
899     bool has_vfp;
900     /* CPU has Neon */
901     bool has_neon;
902     /* CPU has M-profile DSP extension */
903     bool has_dsp;
904 
905     /* CPU has memory protection unit */
906     bool has_mpu;
907     /* PMSAv7 MPU number of supported regions */
908     uint32_t pmsav7_dregion;
909     /* v8M SAU number of supported regions */
910     uint32_t sau_sregion;
911 
912     /* PSCI conduit used to invoke PSCI methods
913      * 0 - disabled, 1 - smc, 2 - hvc
914      */
915     uint32_t psci_conduit;
916 
917     /* For v8M, initial value of the Secure VTOR */
918     uint32_t init_svtor;
919     /* For v8M, initial value of the Non-secure VTOR */
920     uint32_t init_nsvtor;
921 
922     /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
923      * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
924      */
925     uint32_t kvm_target;
926 
927     /* KVM init features for this CPU */
928     uint32_t kvm_init_features[7];
929 
930     /* KVM CPU state */
931 
932     /* KVM virtual time adjustment */
933     bool kvm_adjvtime;
934     bool kvm_vtime_dirty;
935     uint64_t kvm_vtime;
936 
937     /* KVM steal time */
938     OnOffAuto kvm_steal_time;
939 
940     /* Uniprocessor system with MP extensions */
941     bool mp_is_up;
942 
943     /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init
944      * and the probe failed (so we need to report the error in realize)
945      */
946     bool host_cpu_probe_failed;
947 
948     /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
949      * register.
950      */
951     int32_t core_count;
952 
953     /* The instance init functions for implementation-specific subclasses
954      * set these fields to specify the implementation-dependent values of
955      * various constant registers and reset values of non-constant
956      * registers.
957      * Some of these might become QOM properties eventually.
958      * Field names match the official register names as defined in the
959      * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
960      * is used for reset values of non-constant registers; no reset_
961      * prefix means a constant register.
962      * Some of these registers are split out into a substructure that
963      * is shared with the translators to control the ISA.
964      *
965      * Note that if you add an ID register to the ARMISARegisters struct
966      * you need to also update the 32-bit and 64-bit versions of the
967      * kvm_arm_get_host_cpu_features() function to correctly populate the
968      * field by reading the value from the KVM vCPU.
969      */
970     struct ARMISARegisters {
971         uint32_t id_isar0;
972         uint32_t id_isar1;
973         uint32_t id_isar2;
974         uint32_t id_isar3;
975         uint32_t id_isar4;
976         uint32_t id_isar5;
977         uint32_t id_isar6;
978         uint32_t id_mmfr0;
979         uint32_t id_mmfr1;
980         uint32_t id_mmfr2;
981         uint32_t id_mmfr3;
982         uint32_t id_mmfr4;
983         uint32_t id_mmfr5;
984         uint32_t id_pfr0;
985         uint32_t id_pfr1;
986         uint32_t id_pfr2;
987         uint32_t mvfr0;
988         uint32_t mvfr1;
989         uint32_t mvfr2;
990         uint32_t id_dfr0;
991         uint32_t id_dfr1;
992         uint32_t dbgdidr;
993         uint32_t dbgdevid;
994         uint32_t dbgdevid1;
995         uint64_t id_aa64isar0;
996         uint64_t id_aa64isar1;
997         uint64_t id_aa64pfr0;
998         uint64_t id_aa64pfr1;
999         uint64_t id_aa64mmfr0;
1000         uint64_t id_aa64mmfr1;
1001         uint64_t id_aa64mmfr2;
1002         uint64_t id_aa64dfr0;
1003         uint64_t id_aa64dfr1;
1004         uint64_t id_aa64zfr0;
1005         uint64_t id_aa64smfr0;
1006         uint64_t reset_pmcr_el0;
1007     } isar;
1008     uint64_t midr;
1009     uint32_t revidr;
1010     uint32_t reset_fpsid;
1011     uint64_t ctr;
1012     uint32_t reset_sctlr;
1013     uint64_t pmceid0;
1014     uint64_t pmceid1;
1015     uint32_t id_afr0;
1016     uint64_t id_aa64afr0;
1017     uint64_t id_aa64afr1;
1018     uint64_t clidr;
1019     uint64_t mp_affinity; /* MP ID without feature bits */
1020     /* The elements of this array are the CCSIDR values for each cache,
1021      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
1022      */
1023     uint64_t ccsidr[16];
1024     uint64_t reset_cbar;
1025     uint32_t reset_auxcr;
1026     bool reset_hivecs;
1027 
1028     /*
1029      * Intermediate values used during property parsing.
1030      * Once finalized, the values should be read from ID_AA64*.
1031      */
1032     bool prop_pauth;
1033     bool prop_pauth_impdef;
1034     bool prop_lpa2;
1035 
1036     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
1037     uint32_t dcz_blocksize;
1038     uint64_t rvbar_prop; /* Property/input signals.  */
1039 
1040     /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
1041     int gic_num_lrs; /* number of list registers */
1042     int gic_vpribits; /* number of virtual priority bits */
1043     int gic_vprebits; /* number of virtual preemption bits */
1044     int gic_pribits; /* number of physical priority bits */
1045 
1046     /* Whether the cfgend input is high (i.e. this CPU should reset into
1047      * big-endian mode).  This setting isn't used directly: instead it modifies
1048      * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
1049      * architecture version.
1050      */
1051     bool cfgend;
1052 
1053     QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
1054     QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
1055 
1056     int32_t node_id; /* NUMA node this CPU belongs to */
1057 
1058     /* Used to synchronize KVM and QEMU in-kernel device levels */
1059     uint8_t device_irq_level;
1060 
1061     /* Used to set the maximum vector length the cpu will support.  */
1062     uint32_t sve_max_vq;
1063 
1064 #ifdef CONFIG_USER_ONLY
1065     /* Used to set the default vector length at process start. */
1066     uint32_t sve_default_vq;
1067     uint32_t sme_default_vq;
1068 #endif
1069 
1070     ARMVQMap sve_vq;
1071     ARMVQMap sme_vq;
1072 
1073     /* Generic timer counter frequency, in Hz */
1074     uint64_t gt_cntfrq_hz;
1075 };
1076 
1077 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
1078 
1079 void arm_cpu_post_init(Object *obj);
1080 
1081 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
1082 
1083 #ifndef CONFIG_USER_ONLY
1084 extern const VMStateDescription vmstate_arm_cpu;
1085 
1086 void arm_cpu_do_interrupt(CPUState *cpu);
1087 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1088 #endif /* !CONFIG_USER_ONLY */
1089 
1090 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1091                                          MemTxAttrs *attrs);
1092 
1093 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1094 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1095 
1096 /*
1097  * Helpers to dynamically generates XML descriptions of the sysregs
1098  * and SVE registers. Returns the number of registers in each set.
1099  */
1100 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
1101 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
1102 
1103 /* Returns the dynamically generated XML for the gdb stub.
1104  * Returns a pointer to the XML contents for the specified XML file or NULL
1105  * if the XML name doesn't match the predefined one.
1106  */
1107 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1108 
1109 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1110                              int cpuid, DumpState *s);
1111 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1112                              int cpuid, DumpState *s);
1113 
1114 #ifdef TARGET_AARCH64
1115 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1116 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1117 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1118 void aarch64_sve_change_el(CPUARMState *env, int old_el,
1119                            int new_el, bool el0_a64);
1120 void arm_reset_sve_state(CPUARMState *env);
1121 
1122 /*
1123  * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1124  * The byte at offset i from the start of the in-memory representation contains
1125  * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
1126  * lowest offsets are stored in the lowest memory addresses, then that nearly
1127  * matches QEMU's representation, which is to use an array of host-endian
1128  * uint64_t's, where the lower offsets are at the lower indices. To complete
1129  * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1130  */
1131 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1132 {
1133 #if HOST_BIG_ENDIAN
1134     int i;
1135 
1136     for (i = 0; i < nr; ++i) {
1137         dst[i] = bswap64(src[i]);
1138     }
1139 
1140     return dst;
1141 #else
1142     return src;
1143 #endif
1144 }
1145 
1146 #else
1147 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1148 static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1149                                          int n, bool a)
1150 { }
1151 #endif
1152 
1153 void aarch64_sync_32_to_64(CPUARMState *env);
1154 void aarch64_sync_64_to_32(CPUARMState *env);
1155 
1156 int fp_exception_el(CPUARMState *env, int cur_el);
1157 int sve_exception_el(CPUARMState *env, int cur_el);
1158 int sme_exception_el(CPUARMState *env, int cur_el);
1159 
1160 /**
1161  * sve_vqm1_for_el_sm:
1162  * @env: CPUARMState
1163  * @el: exception level
1164  * @sm: streaming mode
1165  *
1166  * Compute the current vector length for @el & @sm, in units of
1167  * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
1168  * If @sm, compute for SVL, otherwise NVL.
1169  */
1170 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm);
1171 
1172 /* Likewise, but using @sm = PSTATE.SM. */
1173 uint32_t sve_vqm1_for_el(CPUARMState *env, int el);
1174 
1175 static inline bool is_a64(CPUARMState *env)
1176 {
1177     return env->aarch64;
1178 }
1179 
1180 /**
1181  * pmu_op_start/finish
1182  * @env: CPUARMState
1183  *
1184  * Convert all PMU counters between their delta form (the typical mode when
1185  * they are enabled) and the guest-visible values. These two calls must
1186  * surround any action which might affect the counters.
1187  */
1188 void pmu_op_start(CPUARMState *env);
1189 void pmu_op_finish(CPUARMState *env);
1190 
1191 /*
1192  * Called when a PMU counter is due to overflow
1193  */
1194 void arm_pmu_timer_cb(void *opaque);
1195 
1196 /**
1197  * Functions to register as EL change hooks for PMU mode filtering
1198  */
1199 void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1200 void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1201 
1202 /*
1203  * pmu_init
1204  * @cpu: ARMCPU
1205  *
1206  * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state
1207  * for the current configuration
1208  */
1209 void pmu_init(ARMCPU *cpu);
1210 
1211 /* SCTLR bit meanings. Several bits have been reused in newer
1212  * versions of the architecture; in that case we define constants
1213  * for both old and new bit meanings. Code which tests against those
1214  * bits should probably check or otherwise arrange that the CPU
1215  * is the architectural version it expects.
1216  */
1217 #define SCTLR_M       (1U << 0)
1218 #define SCTLR_A       (1U << 1)
1219 #define SCTLR_C       (1U << 2)
1220 #define SCTLR_W       (1U << 3) /* up to v6; RAO in v7 */
1221 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1222 #define SCTLR_SA      (1U << 3) /* AArch64 only */
1223 #define SCTLR_P       (1U << 4) /* up to v5; RAO in v6 and v7 */
1224 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1225 #define SCTLR_SA0     (1U << 4) /* v8 onward, AArch64 only */
1226 #define SCTLR_D       (1U << 5) /* up to v5; RAO in v6 */
1227 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1228 #define SCTLR_L       (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1229 #define SCTLR_nAA     (1U << 6) /* when v8.4-LSE is implemented */
1230 #define SCTLR_B       (1U << 7) /* up to v6; RAZ in v7 */
1231 #define SCTLR_ITD     (1U << 7) /* v8 onward */
1232 #define SCTLR_S       (1U << 8) /* up to v6; RAZ in v7 */
1233 #define SCTLR_SED     (1U << 8) /* v8 onward */
1234 #define SCTLR_R       (1U << 9) /* up to v6; RAZ in v7 */
1235 #define SCTLR_UMA     (1U << 9) /* v8 onward, AArch64 only */
1236 #define SCTLR_F       (1U << 10) /* up to v6 */
1237 #define SCTLR_SW      (1U << 10) /* v7 */
1238 #define SCTLR_EnRCTX  (1U << 10) /* in v8.0-PredInv */
1239 #define SCTLR_Z       (1U << 11) /* in v7, RES1 in v8 */
1240 #define SCTLR_EOS     (1U << 11) /* v8.5-ExS */
1241 #define SCTLR_I       (1U << 12)
1242 #define SCTLR_V       (1U << 13) /* AArch32 only */
1243 #define SCTLR_EnDB    (1U << 13) /* v8.3, AArch64 only */
1244 #define SCTLR_RR      (1U << 14) /* up to v7 */
1245 #define SCTLR_DZE     (1U << 14) /* v8 onward, AArch64 only */
1246 #define SCTLR_L4      (1U << 15) /* up to v6; RAZ in v7 */
1247 #define SCTLR_UCT     (1U << 15) /* v8 onward, AArch64 only */
1248 #define SCTLR_DT      (1U << 16) /* up to ??, RAO in v6 and v7 */
1249 #define SCTLR_nTWI    (1U << 16) /* v8 onward */
1250 #define SCTLR_HA      (1U << 17) /* up to v7, RES0 in v8 */
1251 #define SCTLR_BR      (1U << 17) /* PMSA only */
1252 #define SCTLR_IT      (1U << 18) /* up to ??, RAO in v6 and v7 */
1253 #define SCTLR_nTWE    (1U << 18) /* v8 onward */
1254 #define SCTLR_WXN     (1U << 19)
1255 #define SCTLR_ST      (1U << 20) /* up to ??, RAZ in v6 */
1256 #define SCTLR_UWXN    (1U << 20) /* v7 onward, AArch32 only */
1257 #define SCTLR_TSCXT   (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
1258 #define SCTLR_FI      (1U << 21) /* up to v7, v8 RES0 */
1259 #define SCTLR_IESB    (1U << 21) /* v8.2-IESB, AArch64 only */
1260 #define SCTLR_U       (1U << 22) /* up to v6, RAO in v7 */
1261 #define SCTLR_EIS     (1U << 22) /* v8.5-ExS */
1262 #define SCTLR_XP      (1U << 23) /* up to v6; v7 onward RAO */
1263 #define SCTLR_SPAN    (1U << 23) /* v8.1-PAN */
1264 #define SCTLR_VE      (1U << 24) /* up to v7 */
1265 #define SCTLR_E0E     (1U << 24) /* v8 onward, AArch64 only */
1266 #define SCTLR_EE      (1U << 25)
1267 #define SCTLR_L2      (1U << 26) /* up to v6, RAZ in v7 */
1268 #define SCTLR_UCI     (1U << 26) /* v8 onward, AArch64 only */
1269 #define SCTLR_NMFI    (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1270 #define SCTLR_EnDA    (1U << 27) /* v8.3, AArch64 only */
1271 #define SCTLR_TRE     (1U << 28) /* AArch32 only */
1272 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1273 #define SCTLR_AFE     (1U << 29) /* AArch32 only */
1274 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1275 #define SCTLR_TE      (1U << 30) /* AArch32 only */
1276 #define SCTLR_EnIB    (1U << 30) /* v8.3, AArch64 only */
1277 #define SCTLR_EnIA    (1U << 31) /* v8.3, AArch64 only */
1278 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
1279 #define SCTLR_BT0     (1ULL << 35) /* v8.5-BTI */
1280 #define SCTLR_BT1     (1ULL << 36) /* v8.5-BTI */
1281 #define SCTLR_ITFSB   (1ULL << 37) /* v8.5-MemTag */
1282 #define SCTLR_TCF0    (3ULL << 38) /* v8.5-MemTag */
1283 #define SCTLR_TCF     (3ULL << 40) /* v8.5-MemTag */
1284 #define SCTLR_ATA0    (1ULL << 42) /* v8.5-MemTag */
1285 #define SCTLR_ATA     (1ULL << 43) /* v8.5-MemTag */
1286 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
1287 #define SCTLR_TWEDEn  (1ULL << 45)  /* FEAT_TWED */
1288 #define SCTLR_TWEDEL  MAKE_64_MASK(46, 4)  /* FEAT_TWED */
1289 #define SCTLR_TMT0    (1ULL << 50) /* FEAT_TME */
1290 #define SCTLR_TMT     (1ULL << 51) /* FEAT_TME */
1291 #define SCTLR_TME0    (1ULL << 52) /* FEAT_TME */
1292 #define SCTLR_TME     (1ULL << 53) /* FEAT_TME */
1293 #define SCTLR_EnASR   (1ULL << 54) /* FEAT_LS64_V */
1294 #define SCTLR_EnAS0   (1ULL << 55) /* FEAT_LS64_ACCDATA */
1295 #define SCTLR_EnALS   (1ULL << 56) /* FEAT_LS64 */
1296 #define SCTLR_EPAN    (1ULL << 57) /* FEAT_PAN3 */
1297 #define SCTLR_EnTP2   (1ULL << 60) /* FEAT_SME */
1298 #define SCTLR_NMI     (1ULL << 61) /* FEAT_NMI */
1299 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
1300 #define SCTLR_TIDCP   (1ULL << 63) /* FEAT_TIDCP1 */
1301 
1302 /* Bit definitions for CPACR (AArch32 only) */
1303 FIELD(CPACR, CP10, 20, 2)
1304 FIELD(CPACR, CP11, 22, 2)
1305 FIELD(CPACR, TRCDIS, 28, 1)    /* matches CPACR_EL1.TTA */
1306 FIELD(CPACR, D32DIS, 30, 1)    /* up to v7; RAZ in v8 */
1307 FIELD(CPACR, ASEDIS, 31, 1)
1308 
1309 /* Bit definitions for CPACR_EL1 (AArch64 only) */
1310 FIELD(CPACR_EL1, ZEN, 16, 2)
1311 FIELD(CPACR_EL1, FPEN, 20, 2)
1312 FIELD(CPACR_EL1, SMEN, 24, 2)
1313 FIELD(CPACR_EL1, TTA, 28, 1)   /* matches CPACR.TRCDIS */
1314 
1315 /* Bit definitions for HCPTR (AArch32 only) */
1316 FIELD(HCPTR, TCP10, 10, 1)
1317 FIELD(HCPTR, TCP11, 11, 1)
1318 FIELD(HCPTR, TASE, 15, 1)
1319 FIELD(HCPTR, TTA, 20, 1)
1320 FIELD(HCPTR, TAM, 30, 1)       /* matches CPTR_EL2.TAM */
1321 FIELD(HCPTR, TCPAC, 31, 1)     /* matches CPTR_EL2.TCPAC */
1322 
1323 /* Bit definitions for CPTR_EL2 (AArch64 only) */
1324 FIELD(CPTR_EL2, TZ, 8, 1)      /* !E2H */
1325 FIELD(CPTR_EL2, TFP, 10, 1)    /* !E2H, matches HCPTR.TCP10 */
1326 FIELD(CPTR_EL2, TSM, 12, 1)    /* !E2H */
1327 FIELD(CPTR_EL2, ZEN, 16, 2)    /* E2H */
1328 FIELD(CPTR_EL2, FPEN, 20, 2)   /* E2H */
1329 FIELD(CPTR_EL2, SMEN, 24, 2)   /* E2H */
1330 FIELD(CPTR_EL2, TTA, 28, 1)
1331 FIELD(CPTR_EL2, TAM, 30, 1)    /* matches HCPTR.TAM */
1332 FIELD(CPTR_EL2, TCPAC, 31, 1)  /* matches HCPTR.TCPAC */
1333 
1334 /* Bit definitions for CPTR_EL3 (AArch64 only) */
1335 FIELD(CPTR_EL3, EZ, 8, 1)
1336 FIELD(CPTR_EL3, TFP, 10, 1)
1337 FIELD(CPTR_EL3, ESM, 12, 1)
1338 FIELD(CPTR_EL3, TTA, 20, 1)
1339 FIELD(CPTR_EL3, TAM, 30, 1)
1340 FIELD(CPTR_EL3, TCPAC, 31, 1)
1341 
1342 #define MDCR_MTPME    (1U << 28)
1343 #define MDCR_TDCC     (1U << 27)
1344 #define MDCR_HLP      (1U << 26)  /* MDCR_EL2 */
1345 #define MDCR_SCCD     (1U << 23)  /* MDCR_EL3 */
1346 #define MDCR_HCCD     (1U << 23)  /* MDCR_EL2 */
1347 #define MDCR_EPMAD    (1U << 21)
1348 #define MDCR_EDAD     (1U << 20)
1349 #define MDCR_TTRF     (1U << 19)
1350 #define MDCR_STE      (1U << 18)  /* MDCR_EL3 */
1351 #define MDCR_SPME     (1U << 17)  /* MDCR_EL3 */
1352 #define MDCR_HPMD     (1U << 17)  /* MDCR_EL2 */
1353 #define MDCR_SDD      (1U << 16)
1354 #define MDCR_SPD      (3U << 14)
1355 #define MDCR_TDRA     (1U << 11)
1356 #define MDCR_TDOSA    (1U << 10)
1357 #define MDCR_TDA      (1U << 9)
1358 #define MDCR_TDE      (1U << 8)
1359 #define MDCR_HPME     (1U << 7)
1360 #define MDCR_TPM      (1U << 6)
1361 #define MDCR_TPMCR    (1U << 5)
1362 #define MDCR_HPMN     (0x1fU)
1363 
1364 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
1365 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
1366                          MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
1367                          MDCR_STE | MDCR_SPME | MDCR_SPD)
1368 
1369 #define CPSR_M (0x1fU)
1370 #define CPSR_T (1U << 5)
1371 #define CPSR_F (1U << 6)
1372 #define CPSR_I (1U << 7)
1373 #define CPSR_A (1U << 8)
1374 #define CPSR_E (1U << 9)
1375 #define CPSR_IT_2_7 (0xfc00U)
1376 #define CPSR_GE (0xfU << 16)
1377 #define CPSR_IL (1U << 20)
1378 #define CPSR_DIT (1U << 21)
1379 #define CPSR_PAN (1U << 22)
1380 #define CPSR_SSBS (1U << 23)
1381 #define CPSR_J (1U << 24)
1382 #define CPSR_IT_0_1 (3U << 25)
1383 #define CPSR_Q (1U << 27)
1384 #define CPSR_V (1U << 28)
1385 #define CPSR_C (1U << 29)
1386 #define CPSR_Z (1U << 30)
1387 #define CPSR_N (1U << 31)
1388 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1389 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1390 
1391 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1392 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1393     | CPSR_NZCV)
1394 /* Bits writable in user mode.  */
1395 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1396 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
1397 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1398 
1399 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1400 #define XPSR_EXCP 0x1ffU
1401 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1402 #define XPSR_IT_2_7 CPSR_IT_2_7
1403 #define XPSR_GE CPSR_GE
1404 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1405 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1406 #define XPSR_IT_0_1 CPSR_IT_0_1
1407 #define XPSR_Q CPSR_Q
1408 #define XPSR_V CPSR_V
1409 #define XPSR_C CPSR_C
1410 #define XPSR_Z CPSR_Z
1411 #define XPSR_N CPSR_N
1412 #define XPSR_NZCV CPSR_NZCV
1413 #define XPSR_IT CPSR_IT
1414 
1415 #define TTBCR_N      (7U << 0) /* TTBCR.EAE==0 */
1416 #define TTBCR_T0SZ   (7U << 0) /* TTBCR.EAE==1 */
1417 #define TTBCR_PD0    (1U << 4)
1418 #define TTBCR_PD1    (1U << 5)
1419 #define TTBCR_EPD0   (1U << 7)
1420 #define TTBCR_IRGN0  (3U << 8)
1421 #define TTBCR_ORGN0  (3U << 10)
1422 #define TTBCR_SH0    (3U << 12)
1423 #define TTBCR_T1SZ   (3U << 16)
1424 #define TTBCR_A1     (1U << 22)
1425 #define TTBCR_EPD1   (1U << 23)
1426 #define TTBCR_IRGN1  (3U << 24)
1427 #define TTBCR_ORGN1  (3U << 26)
1428 #define TTBCR_SH1    (1U << 28)
1429 #define TTBCR_EAE    (1U << 31)
1430 
1431 FIELD(VTCR, T0SZ, 0, 6)
1432 FIELD(VTCR, SL0, 6, 2)
1433 FIELD(VTCR, IRGN0, 8, 2)
1434 FIELD(VTCR, ORGN0, 10, 2)
1435 FIELD(VTCR, SH0, 12, 2)
1436 FIELD(VTCR, TG0, 14, 2)
1437 FIELD(VTCR, PS, 16, 3)
1438 FIELD(VTCR, VS, 19, 1)
1439 FIELD(VTCR, HA, 21, 1)
1440 FIELD(VTCR, HD, 22, 1)
1441 FIELD(VTCR, HWU59, 25, 1)
1442 FIELD(VTCR, HWU60, 26, 1)
1443 FIELD(VTCR, HWU61, 27, 1)
1444 FIELD(VTCR, HWU62, 28, 1)
1445 FIELD(VTCR, NSW, 29, 1)
1446 FIELD(VTCR, NSA, 30, 1)
1447 FIELD(VTCR, DS, 32, 1)
1448 FIELD(VTCR, SL2, 33, 1)
1449 
1450 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1451  * Only these are valid when in AArch64 mode; in
1452  * AArch32 mode SPSRs are basically CPSR-format.
1453  */
1454 #define PSTATE_SP (1U)
1455 #define PSTATE_M (0xFU)
1456 #define PSTATE_nRW (1U << 4)
1457 #define PSTATE_F (1U << 6)
1458 #define PSTATE_I (1U << 7)
1459 #define PSTATE_A (1U << 8)
1460 #define PSTATE_D (1U << 9)
1461 #define PSTATE_BTYPE (3U << 10)
1462 #define PSTATE_SSBS (1U << 12)
1463 #define PSTATE_IL (1U << 20)
1464 #define PSTATE_SS (1U << 21)
1465 #define PSTATE_PAN (1U << 22)
1466 #define PSTATE_UAO (1U << 23)
1467 #define PSTATE_DIT (1U << 24)
1468 #define PSTATE_TCO (1U << 25)
1469 #define PSTATE_V (1U << 28)
1470 #define PSTATE_C (1U << 29)
1471 #define PSTATE_Z (1U << 30)
1472 #define PSTATE_N (1U << 31)
1473 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1474 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1475 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1476 /* Mode values for AArch64 */
1477 #define PSTATE_MODE_EL3h 13
1478 #define PSTATE_MODE_EL3t 12
1479 #define PSTATE_MODE_EL2h 9
1480 #define PSTATE_MODE_EL2t 8
1481 #define PSTATE_MODE_EL1h 5
1482 #define PSTATE_MODE_EL1t 4
1483 #define PSTATE_MODE_EL0t 0
1484 
1485 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */
1486 FIELD(SVCR, SM, 0, 1)
1487 FIELD(SVCR, ZA, 1, 1)
1488 
1489 /* Fields for SMCR_ELx. */
1490 FIELD(SMCR, LEN, 0, 4)
1491 FIELD(SMCR, FA64, 31, 1)
1492 
1493 /* Write a new value to v7m.exception, thus transitioning into or out
1494  * of Handler mode; this may result in a change of active stack pointer.
1495  */
1496 void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1497 
1498 /* Map EL and handler into a PSTATE_MODE.  */
1499 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1500 {
1501     return (el << 2) | handler;
1502 }
1503 
1504 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1505  * interprocessing, so we don't attempt to sync with the cpsr state used by
1506  * the 32 bit decoder.
1507  */
1508 static inline uint32_t pstate_read(CPUARMState *env)
1509 {
1510     int ZF;
1511 
1512     ZF = (env->ZF == 0);
1513     return (env->NF & 0x80000000) | (ZF << 30)
1514         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1515         | env->pstate | env->daif | (env->btype << 10);
1516 }
1517 
1518 static inline void pstate_write(CPUARMState *env, uint32_t val)
1519 {
1520     env->ZF = (~val) & PSTATE_Z;
1521     env->NF = val;
1522     env->CF = (val >> 29) & 1;
1523     env->VF = (val << 3) & 0x80000000;
1524     env->daif = val & PSTATE_DAIF;
1525     env->btype = (val >> 10) & 3;
1526     env->pstate = val & ~CACHED_PSTATE_BITS;
1527 }
1528 
1529 /* Return the current CPSR value.  */
1530 uint32_t cpsr_read(CPUARMState *env);
1531 
1532 typedef enum CPSRWriteType {
1533     CPSRWriteByInstr = 0,         /* from guest MSR or CPS */
1534     CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1535     CPSRWriteRaw = 2,
1536         /* trust values, no reg bank switch, no hflags rebuild */
1537     CPSRWriteByGDBStub = 3,       /* from the GDB stub */
1538 } CPSRWriteType;
1539 
1540 /*
1541  * Set the CPSR.  Note that some bits of mask must be all-set or all-clear.
1542  * This will do an arm_rebuild_hflags() if any of the bits in @mask
1543  * correspond to TB flags bits cached in the hflags, unless @write_type
1544  * is CPSRWriteRaw.
1545  */
1546 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1547                 CPSRWriteType write_type);
1548 
1549 /* Return the current xPSR value.  */
1550 static inline uint32_t xpsr_read(CPUARMState *env)
1551 {
1552     int ZF;
1553     ZF = (env->ZF == 0);
1554     return (env->NF & 0x80000000) | (ZF << 30)
1555         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1556         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1557         | ((env->condexec_bits & 0xfc) << 8)
1558         | (env->GE << 16)
1559         | env->v7m.exception;
1560 }
1561 
1562 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
1563 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1564 {
1565     if (mask & XPSR_NZCV) {
1566         env->ZF = (~val) & XPSR_Z;
1567         env->NF = val;
1568         env->CF = (val >> 29) & 1;
1569         env->VF = (val << 3) & 0x80000000;
1570     }
1571     if (mask & XPSR_Q) {
1572         env->QF = ((val & XPSR_Q) != 0);
1573     }
1574     if (mask & XPSR_GE) {
1575         env->GE = (val & XPSR_GE) >> 16;
1576     }
1577 #ifndef CONFIG_USER_ONLY
1578     if (mask & XPSR_T) {
1579         env->thumb = ((val & XPSR_T) != 0);
1580     }
1581     if (mask & XPSR_IT_0_1) {
1582         env->condexec_bits &= ~3;
1583         env->condexec_bits |= (val >> 25) & 3;
1584     }
1585     if (mask & XPSR_IT_2_7) {
1586         env->condexec_bits &= 3;
1587         env->condexec_bits |= (val >> 8) & 0xfc;
1588     }
1589     if (mask & XPSR_EXCP) {
1590         /* Note that this only happens on exception exit */
1591         write_v7m_exception(env, val & XPSR_EXCP);
1592     }
1593 #endif
1594 }
1595 
1596 #define HCR_VM        (1ULL << 0)
1597 #define HCR_SWIO      (1ULL << 1)
1598 #define HCR_PTW       (1ULL << 2)
1599 #define HCR_FMO       (1ULL << 3)
1600 #define HCR_IMO       (1ULL << 4)
1601 #define HCR_AMO       (1ULL << 5)
1602 #define HCR_VF        (1ULL << 6)
1603 #define HCR_VI        (1ULL << 7)
1604 #define HCR_VSE       (1ULL << 8)
1605 #define HCR_FB        (1ULL << 9)
1606 #define HCR_BSU_MASK  (3ULL << 10)
1607 #define HCR_DC        (1ULL << 12)
1608 #define HCR_TWI       (1ULL << 13)
1609 #define HCR_TWE       (1ULL << 14)
1610 #define HCR_TID0      (1ULL << 15)
1611 #define HCR_TID1      (1ULL << 16)
1612 #define HCR_TID2      (1ULL << 17)
1613 #define HCR_TID3      (1ULL << 18)
1614 #define HCR_TSC       (1ULL << 19)
1615 #define HCR_TIDCP     (1ULL << 20)
1616 #define HCR_TACR      (1ULL << 21)
1617 #define HCR_TSW       (1ULL << 22)
1618 #define HCR_TPCP      (1ULL << 23)
1619 #define HCR_TPU       (1ULL << 24)
1620 #define HCR_TTLB      (1ULL << 25)
1621 #define HCR_TVM       (1ULL << 26)
1622 #define HCR_TGE       (1ULL << 27)
1623 #define HCR_TDZ       (1ULL << 28)
1624 #define HCR_HCD       (1ULL << 29)
1625 #define HCR_TRVM      (1ULL << 30)
1626 #define HCR_RW        (1ULL << 31)
1627 #define HCR_CD        (1ULL << 32)
1628 #define HCR_ID        (1ULL << 33)
1629 #define HCR_E2H       (1ULL << 34)
1630 #define HCR_TLOR      (1ULL << 35)
1631 #define HCR_TERR      (1ULL << 36)
1632 #define HCR_TEA       (1ULL << 37)
1633 #define HCR_MIOCNCE   (1ULL << 38)
1634 /* RES0 bit 39 */
1635 #define HCR_APK       (1ULL << 40)
1636 #define HCR_API       (1ULL << 41)
1637 #define HCR_NV        (1ULL << 42)
1638 #define HCR_NV1       (1ULL << 43)
1639 #define HCR_AT        (1ULL << 44)
1640 #define HCR_NV2       (1ULL << 45)
1641 #define HCR_FWB       (1ULL << 46)
1642 #define HCR_FIEN      (1ULL << 47)
1643 /* RES0 bit 48 */
1644 #define HCR_TID4      (1ULL << 49)
1645 #define HCR_TICAB     (1ULL << 50)
1646 #define HCR_AMVOFFEN  (1ULL << 51)
1647 #define HCR_TOCU      (1ULL << 52)
1648 #define HCR_ENSCXT    (1ULL << 53)
1649 #define HCR_TTLBIS    (1ULL << 54)
1650 #define HCR_TTLBOS    (1ULL << 55)
1651 #define HCR_ATA       (1ULL << 56)
1652 #define HCR_DCT       (1ULL << 57)
1653 #define HCR_TID5      (1ULL << 58)
1654 #define HCR_TWEDEN    (1ULL << 59)
1655 #define HCR_TWEDEL    MAKE_64BIT_MASK(60, 4)
1656 
1657 #define HCRX_ENAS0    (1ULL << 0)
1658 #define HCRX_ENALS    (1ULL << 1)
1659 #define HCRX_ENASR    (1ULL << 2)
1660 #define HCRX_FNXS     (1ULL << 3)
1661 #define HCRX_FGTNXS   (1ULL << 4)
1662 #define HCRX_SMPME    (1ULL << 5)
1663 #define HCRX_TALLINT  (1ULL << 6)
1664 #define HCRX_VINMI    (1ULL << 7)
1665 #define HCRX_VFNMI    (1ULL << 8)
1666 #define HCRX_CMOW     (1ULL << 9)
1667 #define HCRX_MCE2     (1ULL << 10)
1668 #define HCRX_MSCEN    (1ULL << 11)
1669 
1670 #define HPFAR_NS      (1ULL << 63)
1671 
1672 #define SCR_NS                (1ULL << 0)
1673 #define SCR_IRQ               (1ULL << 1)
1674 #define SCR_FIQ               (1ULL << 2)
1675 #define SCR_EA                (1ULL << 3)
1676 #define SCR_FW                (1ULL << 4)
1677 #define SCR_AW                (1ULL << 5)
1678 #define SCR_NET               (1ULL << 6)
1679 #define SCR_SMD               (1ULL << 7)
1680 #define SCR_HCE               (1ULL << 8)
1681 #define SCR_SIF               (1ULL << 9)
1682 #define SCR_RW                (1ULL << 10)
1683 #define SCR_ST                (1ULL << 11)
1684 #define SCR_TWI               (1ULL << 12)
1685 #define SCR_TWE               (1ULL << 13)
1686 #define SCR_TLOR              (1ULL << 14)
1687 #define SCR_TERR              (1ULL << 15)
1688 #define SCR_APK               (1ULL << 16)
1689 #define SCR_API               (1ULL << 17)
1690 #define SCR_EEL2              (1ULL << 18)
1691 #define SCR_EASE              (1ULL << 19)
1692 #define SCR_NMEA              (1ULL << 20)
1693 #define SCR_FIEN              (1ULL << 21)
1694 #define SCR_ENSCXT            (1ULL << 25)
1695 #define SCR_ATA               (1ULL << 26)
1696 #define SCR_FGTEN             (1ULL << 27)
1697 #define SCR_ECVEN             (1ULL << 28)
1698 #define SCR_TWEDEN            (1ULL << 29)
1699 #define SCR_TWEDEL            MAKE_64BIT_MASK(30, 4)
1700 #define SCR_TME               (1ULL << 34)
1701 #define SCR_AMVOFFEN          (1ULL << 35)
1702 #define SCR_ENAS0             (1ULL << 36)
1703 #define SCR_ADEN              (1ULL << 37)
1704 #define SCR_HXEN              (1ULL << 38)
1705 #define SCR_TRNDR             (1ULL << 40)
1706 #define SCR_ENTP2             (1ULL << 41)
1707 #define SCR_GPF               (1ULL << 48)
1708 
1709 #define HSTR_TTEE (1 << 16)
1710 #define HSTR_TJDBX (1 << 17)
1711 
1712 /* Return the current FPSCR value.  */
1713 uint32_t vfp_get_fpscr(CPUARMState *env);
1714 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1715 
1716 /* FPCR, Floating Point Control Register
1717  * FPSR, Floating Poiht Status Register
1718  *
1719  * For A64 the FPSCR is split into two logically distinct registers,
1720  * FPCR and FPSR. However since they still use non-overlapping bits
1721  * we store the underlying state in fpscr and just mask on read/write.
1722  */
1723 #define FPSR_MASK 0xf800009f
1724 #define FPCR_MASK 0x07ff9f00
1725 
1726 #define FPCR_IOE    (1 << 8)    /* Invalid Operation exception trap enable */
1727 #define FPCR_DZE    (1 << 9)    /* Divide by Zero exception trap enable */
1728 #define FPCR_OFE    (1 << 10)   /* Overflow exception trap enable */
1729 #define FPCR_UFE    (1 << 11)   /* Underflow exception trap enable */
1730 #define FPCR_IXE    (1 << 12)   /* Inexact exception trap enable */
1731 #define FPCR_IDE    (1 << 15)   /* Input Denormal exception trap enable */
1732 #define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
1733 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
1734 #define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
1735 #define FPCR_DN     (1 << 25)   /* Default NaN enable bit */
1736 #define FPCR_AHP    (1 << 26)   /* Alternative half-precision */
1737 #define FPCR_QC     (1 << 27)   /* Cumulative saturation bit */
1738 #define FPCR_V      (1 << 28)   /* FP overflow flag */
1739 #define FPCR_C      (1 << 29)   /* FP carry flag */
1740 #define FPCR_Z      (1 << 30)   /* FP zero flag */
1741 #define FPCR_N      (1 << 31)   /* FP negative flag */
1742 
1743 #define FPCR_LTPSIZE_SHIFT 16   /* LTPSIZE, M-profile only */
1744 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
1745 #define FPCR_LTPSIZE_LENGTH 3
1746 
1747 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
1748 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
1749 
1750 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1751 {
1752     return vfp_get_fpscr(env) & FPSR_MASK;
1753 }
1754 
1755 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1756 {
1757     uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1758     vfp_set_fpscr(env, new_fpscr);
1759 }
1760 
1761 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1762 {
1763     return vfp_get_fpscr(env) & FPCR_MASK;
1764 }
1765 
1766 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1767 {
1768     uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1769     vfp_set_fpscr(env, new_fpscr);
1770 }
1771 
1772 enum arm_cpu_mode {
1773   ARM_CPU_MODE_USR = 0x10,
1774   ARM_CPU_MODE_FIQ = 0x11,
1775   ARM_CPU_MODE_IRQ = 0x12,
1776   ARM_CPU_MODE_SVC = 0x13,
1777   ARM_CPU_MODE_MON = 0x16,
1778   ARM_CPU_MODE_ABT = 0x17,
1779   ARM_CPU_MODE_HYP = 0x1a,
1780   ARM_CPU_MODE_UND = 0x1b,
1781   ARM_CPU_MODE_SYS = 0x1f
1782 };
1783 
1784 /* VFP system registers.  */
1785 #define ARM_VFP_FPSID   0
1786 #define ARM_VFP_FPSCR   1
1787 #define ARM_VFP_MVFR2   5
1788 #define ARM_VFP_MVFR1   6
1789 #define ARM_VFP_MVFR0   7
1790 #define ARM_VFP_FPEXC   8
1791 #define ARM_VFP_FPINST  9
1792 #define ARM_VFP_FPINST2 10
1793 /* These ones are M-profile only */
1794 #define ARM_VFP_FPSCR_NZCVQC 2
1795 #define ARM_VFP_VPR 12
1796 #define ARM_VFP_P0 13
1797 #define ARM_VFP_FPCXT_NS 14
1798 #define ARM_VFP_FPCXT_S 15
1799 
1800 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
1801 #define QEMU_VFP_FPSCR_NZCV 0xffff
1802 
1803 /* iwMMXt coprocessor control registers.  */
1804 #define ARM_IWMMXT_wCID  0
1805 #define ARM_IWMMXT_wCon  1
1806 #define ARM_IWMMXT_wCSSF 2
1807 #define ARM_IWMMXT_wCASF 3
1808 #define ARM_IWMMXT_wCGR0 8
1809 #define ARM_IWMMXT_wCGR1 9
1810 #define ARM_IWMMXT_wCGR2 10
1811 #define ARM_IWMMXT_wCGR3 11
1812 
1813 /* V7M CCR bits */
1814 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1815 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1816 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1817 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1818 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1819 FIELD(V7M_CCR, STKALIGN, 9, 1)
1820 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1821 FIELD(V7M_CCR, DC, 16, 1)
1822 FIELD(V7M_CCR, IC, 17, 1)
1823 FIELD(V7M_CCR, BP, 18, 1)
1824 FIELD(V7M_CCR, LOB, 19, 1)
1825 FIELD(V7M_CCR, TRD, 20, 1)
1826 
1827 /* V7M SCR bits */
1828 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1829 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1830 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1831 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1832 
1833 /* V7M AIRCR bits */
1834 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1835 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1836 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1837 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1838 FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1839 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1840 FIELD(V7M_AIRCR, PRIS, 14, 1)
1841 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1842 FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1843 
1844 /* V7M CFSR bits for MMFSR */
1845 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1846 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1847 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1848 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1849 FIELD(V7M_CFSR, MLSPERR, 5, 1)
1850 FIELD(V7M_CFSR, MMARVALID, 7, 1)
1851 
1852 /* V7M CFSR bits for BFSR */
1853 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1854 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1855 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1856 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1857 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1858 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1859 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1860 
1861 /* V7M CFSR bits for UFSR */
1862 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1863 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1864 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1865 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1866 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1867 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1868 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1869 
1870 /* V7M CFSR bit masks covering all of the subregister bits */
1871 FIELD(V7M_CFSR, MMFSR, 0, 8)
1872 FIELD(V7M_CFSR, BFSR, 8, 8)
1873 FIELD(V7M_CFSR, UFSR, 16, 16)
1874 
1875 /* V7M HFSR bits */
1876 FIELD(V7M_HFSR, VECTTBL, 1, 1)
1877 FIELD(V7M_HFSR, FORCED, 30, 1)
1878 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1879 
1880 /* V7M DFSR bits */
1881 FIELD(V7M_DFSR, HALTED, 0, 1)
1882 FIELD(V7M_DFSR, BKPT, 1, 1)
1883 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1884 FIELD(V7M_DFSR, VCATCH, 3, 1)
1885 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1886 
1887 /* V7M SFSR bits */
1888 FIELD(V7M_SFSR, INVEP, 0, 1)
1889 FIELD(V7M_SFSR, INVIS, 1, 1)
1890 FIELD(V7M_SFSR, INVER, 2, 1)
1891 FIELD(V7M_SFSR, AUVIOL, 3, 1)
1892 FIELD(V7M_SFSR, INVTRAN, 4, 1)
1893 FIELD(V7M_SFSR, LSPERR, 5, 1)
1894 FIELD(V7M_SFSR, SFARVALID, 6, 1)
1895 FIELD(V7M_SFSR, LSERR, 7, 1)
1896 
1897 /* v7M MPU_CTRL bits */
1898 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1899 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1900 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1901 
1902 /* v7M CLIDR bits */
1903 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1904 FIELD(V7M_CLIDR, LOUIS, 21, 3)
1905 FIELD(V7M_CLIDR, LOC, 24, 3)
1906 FIELD(V7M_CLIDR, LOUU, 27, 3)
1907 FIELD(V7M_CLIDR, ICB, 30, 2)
1908 
1909 FIELD(V7M_CSSELR, IND, 0, 1)
1910 FIELD(V7M_CSSELR, LEVEL, 1, 3)
1911 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1912  * define a mask for this and check that it doesn't permit running off
1913  * the end of the array.
1914  */
1915 FIELD(V7M_CSSELR, INDEX, 0, 4)
1916 
1917 /* v7M FPCCR bits */
1918 FIELD(V7M_FPCCR, LSPACT, 0, 1)
1919 FIELD(V7M_FPCCR, USER, 1, 1)
1920 FIELD(V7M_FPCCR, S, 2, 1)
1921 FIELD(V7M_FPCCR, THREAD, 3, 1)
1922 FIELD(V7M_FPCCR, HFRDY, 4, 1)
1923 FIELD(V7M_FPCCR, MMRDY, 5, 1)
1924 FIELD(V7M_FPCCR, BFRDY, 6, 1)
1925 FIELD(V7M_FPCCR, SFRDY, 7, 1)
1926 FIELD(V7M_FPCCR, MONRDY, 8, 1)
1927 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1928 FIELD(V7M_FPCCR, UFRDY, 10, 1)
1929 FIELD(V7M_FPCCR, RES0, 11, 15)
1930 FIELD(V7M_FPCCR, TS, 26, 1)
1931 FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1932 FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1933 FIELD(V7M_FPCCR, LSPENS, 29, 1)
1934 FIELD(V7M_FPCCR, LSPEN, 30, 1)
1935 FIELD(V7M_FPCCR, ASPEN, 31, 1)
1936 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
1937 #define R_V7M_FPCCR_BANKED_MASK                 \
1938     (R_V7M_FPCCR_LSPACT_MASK |                  \
1939      R_V7M_FPCCR_USER_MASK |                    \
1940      R_V7M_FPCCR_THREAD_MASK |                  \
1941      R_V7M_FPCCR_MMRDY_MASK |                   \
1942      R_V7M_FPCCR_SPLIMVIOL_MASK |               \
1943      R_V7M_FPCCR_UFRDY_MASK |                   \
1944      R_V7M_FPCCR_ASPEN_MASK)
1945 
1946 /* v7M VPR bits */
1947 FIELD(V7M_VPR, P0, 0, 16)
1948 FIELD(V7M_VPR, MASK01, 16, 4)
1949 FIELD(V7M_VPR, MASK23, 20, 4)
1950 
1951 /*
1952  * System register ID fields.
1953  */
1954 FIELD(CLIDR_EL1, CTYPE1, 0, 3)
1955 FIELD(CLIDR_EL1, CTYPE2, 3, 3)
1956 FIELD(CLIDR_EL1, CTYPE3, 6, 3)
1957 FIELD(CLIDR_EL1, CTYPE4, 9, 3)
1958 FIELD(CLIDR_EL1, CTYPE5, 12, 3)
1959 FIELD(CLIDR_EL1, CTYPE6, 15, 3)
1960 FIELD(CLIDR_EL1, CTYPE7, 18, 3)
1961 FIELD(CLIDR_EL1, LOUIS, 21, 3)
1962 FIELD(CLIDR_EL1, LOC, 24, 3)
1963 FIELD(CLIDR_EL1, LOUU, 27, 3)
1964 FIELD(CLIDR_EL1, ICB, 30, 3)
1965 
1966 /* When FEAT_CCIDX is implemented */
1967 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
1968 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
1969 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
1970 
1971 /* When FEAT_CCIDX is not implemented */
1972 FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
1973 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
1974 FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
1975 
1976 FIELD(CTR_EL0,  IMINLINE, 0, 4)
1977 FIELD(CTR_EL0,  L1IP, 14, 2)
1978 FIELD(CTR_EL0,  DMINLINE, 16, 4)
1979 FIELD(CTR_EL0,  ERG, 20, 4)
1980 FIELD(CTR_EL0,  CWG, 24, 4)
1981 FIELD(CTR_EL0,  IDC, 28, 1)
1982 FIELD(CTR_EL0,  DIC, 29, 1)
1983 FIELD(CTR_EL0,  TMINLINE, 32, 6)
1984 
1985 FIELD(MIDR_EL1, REVISION, 0, 4)
1986 FIELD(MIDR_EL1, PARTNUM, 4, 12)
1987 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
1988 FIELD(MIDR_EL1, VARIANT, 20, 4)
1989 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
1990 
1991 FIELD(ID_ISAR0, SWAP, 0, 4)
1992 FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1993 FIELD(ID_ISAR0, BITFIELD, 8, 4)
1994 FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1995 FIELD(ID_ISAR0, COPROC, 16, 4)
1996 FIELD(ID_ISAR0, DEBUG, 20, 4)
1997 FIELD(ID_ISAR0, DIVIDE, 24, 4)
1998 
1999 FIELD(ID_ISAR1, ENDIAN, 0, 4)
2000 FIELD(ID_ISAR1, EXCEPT, 4, 4)
2001 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
2002 FIELD(ID_ISAR1, EXTEND, 12, 4)
2003 FIELD(ID_ISAR1, IFTHEN, 16, 4)
2004 FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
2005 FIELD(ID_ISAR1, INTERWORK, 24, 4)
2006 FIELD(ID_ISAR1, JAZELLE, 28, 4)
2007 
2008 FIELD(ID_ISAR2, LOADSTORE, 0, 4)
2009 FIELD(ID_ISAR2, MEMHINT, 4, 4)
2010 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
2011 FIELD(ID_ISAR2, MULT, 12, 4)
2012 FIELD(ID_ISAR2, MULTS, 16, 4)
2013 FIELD(ID_ISAR2, MULTU, 20, 4)
2014 FIELD(ID_ISAR2, PSR_AR, 24, 4)
2015 FIELD(ID_ISAR2, REVERSAL, 28, 4)
2016 
2017 FIELD(ID_ISAR3, SATURATE, 0, 4)
2018 FIELD(ID_ISAR3, SIMD, 4, 4)
2019 FIELD(ID_ISAR3, SVC, 8, 4)
2020 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
2021 FIELD(ID_ISAR3, TABBRANCH, 16, 4)
2022 FIELD(ID_ISAR3, T32COPY, 20, 4)
2023 FIELD(ID_ISAR3, TRUENOP, 24, 4)
2024 FIELD(ID_ISAR3, T32EE, 28, 4)
2025 
2026 FIELD(ID_ISAR4, UNPRIV, 0, 4)
2027 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
2028 FIELD(ID_ISAR4, WRITEBACK, 8, 4)
2029 FIELD(ID_ISAR4, SMC, 12, 4)
2030 FIELD(ID_ISAR4, BARRIER, 16, 4)
2031 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
2032 FIELD(ID_ISAR4, PSR_M, 24, 4)
2033 FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
2034 
2035 FIELD(ID_ISAR5, SEVL, 0, 4)
2036 FIELD(ID_ISAR5, AES, 4, 4)
2037 FIELD(ID_ISAR5, SHA1, 8, 4)
2038 FIELD(ID_ISAR5, SHA2, 12, 4)
2039 FIELD(ID_ISAR5, CRC32, 16, 4)
2040 FIELD(ID_ISAR5, RDM, 24, 4)
2041 FIELD(ID_ISAR5, VCMA, 28, 4)
2042 
2043 FIELD(ID_ISAR6, JSCVT, 0, 4)
2044 FIELD(ID_ISAR6, DP, 4, 4)
2045 FIELD(ID_ISAR6, FHM, 8, 4)
2046 FIELD(ID_ISAR6, SB, 12, 4)
2047 FIELD(ID_ISAR6, SPECRES, 16, 4)
2048 FIELD(ID_ISAR6, BF16, 20, 4)
2049 FIELD(ID_ISAR6, I8MM, 24, 4)
2050 
2051 FIELD(ID_MMFR0, VMSA, 0, 4)
2052 FIELD(ID_MMFR0, PMSA, 4, 4)
2053 FIELD(ID_MMFR0, OUTERSHR, 8, 4)
2054 FIELD(ID_MMFR0, SHARELVL, 12, 4)
2055 FIELD(ID_MMFR0, TCM, 16, 4)
2056 FIELD(ID_MMFR0, AUXREG, 20, 4)
2057 FIELD(ID_MMFR0, FCSE, 24, 4)
2058 FIELD(ID_MMFR0, INNERSHR, 28, 4)
2059 
2060 FIELD(ID_MMFR1, L1HVDVA, 0, 4)
2061 FIELD(ID_MMFR1, L1UNIVA, 4, 4)
2062 FIELD(ID_MMFR1, L1HVDSW, 8, 4)
2063 FIELD(ID_MMFR1, L1UNISW, 12, 4)
2064 FIELD(ID_MMFR1, L1HVD, 16, 4)
2065 FIELD(ID_MMFR1, L1UNI, 20, 4)
2066 FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
2067 FIELD(ID_MMFR1, BPRED, 28, 4)
2068 
2069 FIELD(ID_MMFR2, L1HVDFG, 0, 4)
2070 FIELD(ID_MMFR2, L1HVDBG, 4, 4)
2071 FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
2072 FIELD(ID_MMFR2, HVDTLB, 12, 4)
2073 FIELD(ID_MMFR2, UNITLB, 16, 4)
2074 FIELD(ID_MMFR2, MEMBARR, 20, 4)
2075 FIELD(ID_MMFR2, WFISTALL, 24, 4)
2076 FIELD(ID_MMFR2, HWACCFLG, 28, 4)
2077 
2078 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
2079 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
2080 FIELD(ID_MMFR3, BPMAINT, 8, 4)
2081 FIELD(ID_MMFR3, MAINTBCST, 12, 4)
2082 FIELD(ID_MMFR3, PAN, 16, 4)
2083 FIELD(ID_MMFR3, COHWALK, 20, 4)
2084 FIELD(ID_MMFR3, CMEMSZ, 24, 4)
2085 FIELD(ID_MMFR3, SUPERSEC, 28, 4)
2086 
2087 FIELD(ID_MMFR4, SPECSEI, 0, 4)
2088 FIELD(ID_MMFR4, AC2, 4, 4)
2089 FIELD(ID_MMFR4, XNX, 8, 4)
2090 FIELD(ID_MMFR4, CNP, 12, 4)
2091 FIELD(ID_MMFR4, HPDS, 16, 4)
2092 FIELD(ID_MMFR4, LSM, 20, 4)
2093 FIELD(ID_MMFR4, CCIDX, 24, 4)
2094 FIELD(ID_MMFR4, EVT, 28, 4)
2095 
2096 FIELD(ID_MMFR5, ETS, 0, 4)
2097 FIELD(ID_MMFR5, NTLBPA, 4, 4)
2098 
2099 FIELD(ID_PFR0, STATE0, 0, 4)
2100 FIELD(ID_PFR0, STATE1, 4, 4)
2101 FIELD(ID_PFR0, STATE2, 8, 4)
2102 FIELD(ID_PFR0, STATE3, 12, 4)
2103 FIELD(ID_PFR0, CSV2, 16, 4)
2104 FIELD(ID_PFR0, AMU, 20, 4)
2105 FIELD(ID_PFR0, DIT, 24, 4)
2106 FIELD(ID_PFR0, RAS, 28, 4)
2107 
2108 FIELD(ID_PFR1, PROGMOD, 0, 4)
2109 FIELD(ID_PFR1, SECURITY, 4, 4)
2110 FIELD(ID_PFR1, MPROGMOD, 8, 4)
2111 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
2112 FIELD(ID_PFR1, GENTIMER, 16, 4)
2113 FIELD(ID_PFR1, SEC_FRAC, 20, 4)
2114 FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
2115 FIELD(ID_PFR1, GIC, 28, 4)
2116 
2117 FIELD(ID_PFR2, CSV3, 0, 4)
2118 FIELD(ID_PFR2, SSBS, 4, 4)
2119 FIELD(ID_PFR2, RAS_FRAC, 8, 4)
2120 
2121 FIELD(ID_AA64ISAR0, AES, 4, 4)
2122 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
2123 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
2124 FIELD(ID_AA64ISAR0, CRC32, 16, 4)
2125 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
2126 FIELD(ID_AA64ISAR0, RDM, 28, 4)
2127 FIELD(ID_AA64ISAR0, SHA3, 32, 4)
2128 FIELD(ID_AA64ISAR0, SM3, 36, 4)
2129 FIELD(ID_AA64ISAR0, SM4, 40, 4)
2130 FIELD(ID_AA64ISAR0, DP, 44, 4)
2131 FIELD(ID_AA64ISAR0, FHM, 48, 4)
2132 FIELD(ID_AA64ISAR0, TS, 52, 4)
2133 FIELD(ID_AA64ISAR0, TLB, 56, 4)
2134 FIELD(ID_AA64ISAR0, RNDR, 60, 4)
2135 
2136 FIELD(ID_AA64ISAR1, DPB, 0, 4)
2137 FIELD(ID_AA64ISAR1, APA, 4, 4)
2138 FIELD(ID_AA64ISAR1, API, 8, 4)
2139 FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
2140 FIELD(ID_AA64ISAR1, FCMA, 16, 4)
2141 FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
2142 FIELD(ID_AA64ISAR1, GPA, 24, 4)
2143 FIELD(ID_AA64ISAR1, GPI, 28, 4)
2144 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
2145 FIELD(ID_AA64ISAR1, SB, 36, 4)
2146 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
2147 FIELD(ID_AA64ISAR1, BF16, 44, 4)
2148 FIELD(ID_AA64ISAR1, DGH, 48, 4)
2149 FIELD(ID_AA64ISAR1, I8MM, 52, 4)
2150 FIELD(ID_AA64ISAR1, XS, 56, 4)
2151 FIELD(ID_AA64ISAR1, LS64, 60, 4)
2152 
2153 FIELD(ID_AA64ISAR2, WFXT, 0, 4)
2154 FIELD(ID_AA64ISAR2, RPRES, 4, 4)
2155 FIELD(ID_AA64ISAR2, GPA3, 8, 4)
2156 FIELD(ID_AA64ISAR2, APA3, 12, 4)
2157 FIELD(ID_AA64ISAR2, MOPS, 16, 4)
2158 FIELD(ID_AA64ISAR2, BC, 20, 4)
2159 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4)
2160 
2161 FIELD(ID_AA64PFR0, EL0, 0, 4)
2162 FIELD(ID_AA64PFR0, EL1, 4, 4)
2163 FIELD(ID_AA64PFR0, EL2, 8, 4)
2164 FIELD(ID_AA64PFR0, EL3, 12, 4)
2165 FIELD(ID_AA64PFR0, FP, 16, 4)
2166 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
2167 FIELD(ID_AA64PFR0, GIC, 24, 4)
2168 FIELD(ID_AA64PFR0, RAS, 28, 4)
2169 FIELD(ID_AA64PFR0, SVE, 32, 4)
2170 FIELD(ID_AA64PFR0, SEL2, 36, 4)
2171 FIELD(ID_AA64PFR0, MPAM, 40, 4)
2172 FIELD(ID_AA64PFR0, AMU, 44, 4)
2173 FIELD(ID_AA64PFR0, DIT, 48, 4)
2174 FIELD(ID_AA64PFR0, CSV2, 56, 4)
2175 FIELD(ID_AA64PFR0, CSV3, 60, 4)
2176 
2177 FIELD(ID_AA64PFR1, BT, 0, 4)
2178 FIELD(ID_AA64PFR1, SSBS, 4, 4)
2179 FIELD(ID_AA64PFR1, MTE, 8, 4)
2180 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
2181 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
2182 FIELD(ID_AA64PFR1, SME, 24, 4)
2183 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4)
2184 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4)
2185 FIELD(ID_AA64PFR1, NMI, 36, 4)
2186 
2187 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
2188 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
2189 FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
2190 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
2191 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
2192 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
2193 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
2194 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
2195 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
2196 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
2197 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
2198 FIELD(ID_AA64MMFR0, EXS, 44, 4)
2199 FIELD(ID_AA64MMFR0, FGT, 56, 4)
2200 FIELD(ID_AA64MMFR0, ECV, 60, 4)
2201 
2202 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
2203 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
2204 FIELD(ID_AA64MMFR1, VH, 8, 4)
2205 FIELD(ID_AA64MMFR1, HPDS, 12, 4)
2206 FIELD(ID_AA64MMFR1, LO, 16, 4)
2207 FIELD(ID_AA64MMFR1, PAN, 20, 4)
2208 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
2209 FIELD(ID_AA64MMFR1, XNX, 28, 4)
2210 FIELD(ID_AA64MMFR1, TWED, 32, 4)
2211 FIELD(ID_AA64MMFR1, ETS, 36, 4)
2212 FIELD(ID_AA64MMFR1, HCX, 40, 4)
2213 FIELD(ID_AA64MMFR1, AFP, 44, 4)
2214 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4)
2215 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4)
2216 FIELD(ID_AA64MMFR1, CMOW, 56, 4)
2217 
2218 FIELD(ID_AA64MMFR2, CNP, 0, 4)
2219 FIELD(ID_AA64MMFR2, UAO, 4, 4)
2220 FIELD(ID_AA64MMFR2, LSM, 8, 4)
2221 FIELD(ID_AA64MMFR2, IESB, 12, 4)
2222 FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
2223 FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
2224 FIELD(ID_AA64MMFR2, NV, 24, 4)
2225 FIELD(ID_AA64MMFR2, ST, 28, 4)
2226 FIELD(ID_AA64MMFR2, AT, 32, 4)
2227 FIELD(ID_AA64MMFR2, IDS, 36, 4)
2228 FIELD(ID_AA64MMFR2, FWB, 40, 4)
2229 FIELD(ID_AA64MMFR2, TTL, 48, 4)
2230 FIELD(ID_AA64MMFR2, BBM, 52, 4)
2231 FIELD(ID_AA64MMFR2, EVT, 56, 4)
2232 FIELD(ID_AA64MMFR2, E0PD, 60, 4)
2233 
2234 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
2235 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
2236 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
2237 FIELD(ID_AA64DFR0, BRPS, 12, 4)
2238 FIELD(ID_AA64DFR0, WRPS, 20, 4)
2239 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
2240 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
2241 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
2242 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
2243 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4)
2244 FIELD(ID_AA64DFR0, MTPMU, 48, 4)
2245 FIELD(ID_AA64DFR0, BRBE, 52, 4)
2246 FIELD(ID_AA64DFR0, HPMN0, 60, 4)
2247 
2248 FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
2249 FIELD(ID_AA64ZFR0, AES, 4, 4)
2250 FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
2251 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
2252 FIELD(ID_AA64ZFR0, SHA3, 32, 4)
2253 FIELD(ID_AA64ZFR0, SM4, 40, 4)
2254 FIELD(ID_AA64ZFR0, I8MM, 44, 4)
2255 FIELD(ID_AA64ZFR0, F32MM, 52, 4)
2256 FIELD(ID_AA64ZFR0, F64MM, 56, 4)
2257 
2258 FIELD(ID_AA64SMFR0, F32F32, 32, 1)
2259 FIELD(ID_AA64SMFR0, B16F32, 34, 1)
2260 FIELD(ID_AA64SMFR0, F16F32, 35, 1)
2261 FIELD(ID_AA64SMFR0, I8I32, 36, 4)
2262 FIELD(ID_AA64SMFR0, F64F64, 48, 1)
2263 FIELD(ID_AA64SMFR0, I16I64, 52, 4)
2264 FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
2265 FIELD(ID_AA64SMFR0, FA64, 63, 1)
2266 
2267 FIELD(ID_DFR0, COPDBG, 0, 4)
2268 FIELD(ID_DFR0, COPSDBG, 4, 4)
2269 FIELD(ID_DFR0, MMAPDBG, 8, 4)
2270 FIELD(ID_DFR0, COPTRC, 12, 4)
2271 FIELD(ID_DFR0, MMAPTRC, 16, 4)
2272 FIELD(ID_DFR0, MPROFDBG, 20, 4)
2273 FIELD(ID_DFR0, PERFMON, 24, 4)
2274 FIELD(ID_DFR0, TRACEFILT, 28, 4)
2275 
2276 FIELD(ID_DFR1, MTPMU, 0, 4)
2277 FIELD(ID_DFR1, HPMN0, 4, 4)
2278 
2279 FIELD(DBGDIDR, SE_IMP, 12, 1)
2280 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
2281 FIELD(DBGDIDR, VERSION, 16, 4)
2282 FIELD(DBGDIDR, CTX_CMPS, 20, 4)
2283 FIELD(DBGDIDR, BRPS, 24, 4)
2284 FIELD(DBGDIDR, WRPS, 28, 4)
2285 
2286 FIELD(DBGDEVID, PCSAMPLE, 0, 4)
2287 FIELD(DBGDEVID, WPADDRMASK, 4, 4)
2288 FIELD(DBGDEVID, BPADDRMASK, 8, 4)
2289 FIELD(DBGDEVID, VECTORCATCH, 12, 4)
2290 FIELD(DBGDEVID, VIRTEXTNS, 16, 4)
2291 FIELD(DBGDEVID, DOUBLELOCK, 20, 4)
2292 FIELD(DBGDEVID, AUXREGS, 24, 4)
2293 FIELD(DBGDEVID, CIDMASK, 28, 4)
2294 
2295 FIELD(MVFR0, SIMDREG, 0, 4)
2296 FIELD(MVFR0, FPSP, 4, 4)
2297 FIELD(MVFR0, FPDP, 8, 4)
2298 FIELD(MVFR0, FPTRAP, 12, 4)
2299 FIELD(MVFR0, FPDIVIDE, 16, 4)
2300 FIELD(MVFR0, FPSQRT, 20, 4)
2301 FIELD(MVFR0, FPSHVEC, 24, 4)
2302 FIELD(MVFR0, FPROUND, 28, 4)
2303 
2304 FIELD(MVFR1, FPFTZ, 0, 4)
2305 FIELD(MVFR1, FPDNAN, 4, 4)
2306 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
2307 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
2308 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
2309 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
2310 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
2311 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
2312 FIELD(MVFR1, FPHP, 24, 4)
2313 FIELD(MVFR1, SIMDFMAC, 28, 4)
2314 
2315 FIELD(MVFR2, SIMDMISC, 0, 4)
2316 FIELD(MVFR2, FPMISC, 4, 4)
2317 
2318 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2319 
2320 /* If adding a feature bit which corresponds to a Linux ELF
2321  * HWCAP bit, remember to update the feature-bit-to-hwcap
2322  * mapping in linux-user/elfload.c:get_elf_hwcap().
2323  */
2324 enum arm_features {
2325     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
2326     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
2327     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
2328     ARM_FEATURE_V6,
2329     ARM_FEATURE_V6K,
2330     ARM_FEATURE_V7,
2331     ARM_FEATURE_THUMB2,
2332     ARM_FEATURE_PMSA,   /* no MMU; may have Memory Protection Unit */
2333     ARM_FEATURE_NEON,
2334     ARM_FEATURE_M, /* Microcontroller profile.  */
2335     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
2336     ARM_FEATURE_THUMB2EE,
2337     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
2338     ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
2339     ARM_FEATURE_V4T,
2340     ARM_FEATURE_V5,
2341     ARM_FEATURE_STRONGARM,
2342     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
2343     ARM_FEATURE_GENERIC_TIMER,
2344     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
2345     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
2346     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
2347     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
2348     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
2349     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
2350     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
2351     ARM_FEATURE_V8,
2352     ARM_FEATURE_AARCH64, /* supports 64 bit mode */
2353     ARM_FEATURE_CBAR, /* has cp15 CBAR */
2354     ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
2355     ARM_FEATURE_EL2, /* has EL2 Virtualization support */
2356     ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
2357     ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
2358     ARM_FEATURE_PMU, /* has PMU support */
2359     ARM_FEATURE_VBAR, /* has cp15 VBAR */
2360     ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
2361     ARM_FEATURE_M_MAIN, /* M profile Main Extension */
2362     ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
2363 };
2364 
2365 static inline int arm_feature(CPUARMState *env, int feature)
2366 {
2367     return (env->features & (1ULL << feature)) != 0;
2368 }
2369 
2370 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
2371 
2372 #if !defined(CONFIG_USER_ONLY)
2373 /* Return true if exception levels below EL3 are in secure state,
2374  * or would be following an exception return to that level.
2375  * Unlike arm_is_secure() (which is always a question about the
2376  * _current_ state of the CPU) this doesn't care about the current
2377  * EL or mode.
2378  */
2379 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2380 {
2381     if (arm_feature(env, ARM_FEATURE_EL3)) {
2382         return !(env->cp15.scr_el3 & SCR_NS);
2383     } else {
2384         /* If EL3 is not supported then the secure state is implementation
2385          * defined, in which case QEMU defaults to non-secure.
2386          */
2387         return false;
2388     }
2389 }
2390 
2391 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
2392 static inline bool arm_is_el3_or_mon(CPUARMState *env)
2393 {
2394     if (arm_feature(env, ARM_FEATURE_EL3)) {
2395         if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2396             /* CPU currently in AArch64 state and EL3 */
2397             return true;
2398         } else if (!is_a64(env) &&
2399                 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2400             /* CPU currently in AArch32 state and monitor mode */
2401             return true;
2402         }
2403     }
2404     return false;
2405 }
2406 
2407 /* Return true if the processor is in secure state */
2408 static inline bool arm_is_secure(CPUARMState *env)
2409 {
2410     if (arm_is_el3_or_mon(env)) {
2411         return true;
2412     }
2413     return arm_is_secure_below_el3(env);
2414 }
2415 
2416 /*
2417  * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
2418  * This corresponds to the pseudocode EL2Enabled()
2419  */
2420 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
2421 {
2422     return arm_feature(env, ARM_FEATURE_EL2)
2423            && (!secure || (env->cp15.scr_el3 & SCR_EEL2));
2424 }
2425 
2426 static inline bool arm_is_el2_enabled(CPUARMState *env)
2427 {
2428     return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env));
2429 }
2430 
2431 #else
2432 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2433 {
2434     return false;
2435 }
2436 
2437 static inline bool arm_is_secure(CPUARMState *env)
2438 {
2439     return false;
2440 }
2441 
2442 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
2443 {
2444     return false;
2445 }
2446 
2447 static inline bool arm_is_el2_enabled(CPUARMState *env)
2448 {
2449     return false;
2450 }
2451 #endif
2452 
2453 /**
2454  * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
2455  * E.g. when in secure state, fields in HCR_EL2 are suppressed,
2456  * "for all purposes other than a direct read or write access of HCR_EL2."
2457  * Not included here is HCR_RW.
2458  */
2459 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure);
2460 uint64_t arm_hcr_el2_eff(CPUARMState *env);
2461 uint64_t arm_hcrx_el2_eff(CPUARMState *env);
2462 
2463 /* Return true if the specified exception level is running in AArch64 state. */
2464 static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2465 {
2466     /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
2467      * and if we're not in EL0 then the state of EL0 isn't well defined.)
2468      */
2469     assert(el >= 1 && el <= 3);
2470     bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2471 
2472     /* The highest exception level is always at the maximum supported
2473      * register width, and then lower levels have a register width controlled
2474      * by bits in the SCR or HCR registers.
2475      */
2476     if (el == 3) {
2477         return aa64;
2478     }
2479 
2480     if (arm_feature(env, ARM_FEATURE_EL3) &&
2481         ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
2482         aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2483     }
2484 
2485     if (el == 2) {
2486         return aa64;
2487     }
2488 
2489     if (arm_is_el2_enabled(env)) {
2490         aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2491     }
2492 
2493     return aa64;
2494 }
2495 
2496 /* Function for determing whether guest cp register reads and writes should
2497  * access the secure or non-secure bank of a cp register.  When EL3 is
2498  * operating in AArch32 state, the NS-bit determines whether the secure
2499  * instance of a cp register should be used. When EL3 is AArch64 (or if
2500  * it doesn't exist at all) then there is no register banking, and all
2501  * accesses are to the non-secure version.
2502  */
2503 static inline bool access_secure_reg(CPUARMState *env)
2504 {
2505     bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2506                 !arm_el_is_aa64(env, 3) &&
2507                 !(env->cp15.scr_el3 & SCR_NS));
2508 
2509     return ret;
2510 }
2511 
2512 /* Macros for accessing a specified CP register bank */
2513 #define A32_BANKED_REG_GET(_env, _regname, _secure)    \
2514     ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2515 
2516 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val)   \
2517     do {                                                \
2518         if (_secure) {                                   \
2519             (_env)->cp15._regname##_s = (_val);            \
2520         } else {                                        \
2521             (_env)->cp15._regname##_ns = (_val);           \
2522         }                                               \
2523     } while (0)
2524 
2525 /* Macros for automatically accessing a specific CP register bank depending on
2526  * the current secure state of the system.  These macros are not intended for
2527  * supporting instruction translation reads/writes as these are dependent
2528  * solely on the SCR.NS bit and not the mode.
2529  */
2530 #define A32_BANKED_CURRENT_REG_GET(_env, _regname)        \
2531     A32_BANKED_REG_GET((_env), _regname,                \
2532                        (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2533 
2534 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val)                       \
2535     A32_BANKED_REG_SET((_env), _regname,                                    \
2536                        (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2537                        (_val))
2538 
2539 void arm_cpu_list(void);
2540 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2541                                  uint32_t cur_el, bool secure);
2542 
2543 /* Interface between CPU and Interrupt controller.  */
2544 #ifndef CONFIG_USER_ONLY
2545 bool armv7m_nvic_can_take_pending_exception(void *opaque);
2546 #else
2547 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
2548 {
2549     return true;
2550 }
2551 #endif
2552 /**
2553  * armv7m_nvic_set_pending: mark the specified exception as pending
2554  * @opaque: the NVIC
2555  * @irq: the exception number to mark pending
2556  * @secure: false for non-banked exceptions or for the nonsecure
2557  * version of a banked exception, true for the secure version of a banked
2558  * exception.
2559  *
2560  * Marks the specified exception as pending. Note that we will assert()
2561  * if @secure is true and @irq does not specify one of the fixed set
2562  * of architecturally banked exceptions.
2563  */
2564 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
2565 /**
2566  * armv7m_nvic_set_pending_derived: mark this derived exception as pending
2567  * @opaque: the NVIC
2568  * @irq: the exception number to mark pending
2569  * @secure: false for non-banked exceptions or for the nonsecure
2570  * version of a banked exception, true for the secure version of a banked
2571  * exception.
2572  *
2573  * Similar to armv7m_nvic_set_pending(), but specifically for derived
2574  * exceptions (exceptions generated in the course of trying to take
2575  * a different exception).
2576  */
2577 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
2578 /**
2579  * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
2580  * @opaque: the NVIC
2581  * @irq: the exception number to mark pending
2582  * @secure: false for non-banked exceptions or for the nonsecure
2583  * version of a banked exception, true for the secure version of a banked
2584  * exception.
2585  *
2586  * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
2587  * generated in the course of lazy stacking of FP registers.
2588  */
2589 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
2590 /**
2591  * armv7m_nvic_get_pending_irq_info: return highest priority pending
2592  *    exception, and whether it targets Secure state
2593  * @opaque: the NVIC
2594  * @pirq: set to pending exception number
2595  * @ptargets_secure: set to whether pending exception targets Secure
2596  *
2597  * This function writes the number of the highest priority pending
2598  * exception (the one which would be made active by
2599  * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
2600  * to true if the current highest priority pending exception should
2601  * be taken to Secure state, false for NS.
2602  */
2603 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
2604                                       bool *ptargets_secure);
2605 /**
2606  * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
2607  * @opaque: the NVIC
2608  *
2609  * Move the current highest priority pending exception from the pending
2610  * state to the active state, and update v7m.exception to indicate that
2611  * it is the exception currently being handled.
2612  */
2613 void armv7m_nvic_acknowledge_irq(void *opaque);
2614 /**
2615  * armv7m_nvic_complete_irq: complete specified interrupt or exception
2616  * @opaque: the NVIC
2617  * @irq: the exception number to complete
2618  * @secure: true if this exception was secure
2619  *
2620  * Returns: -1 if the irq was not active
2621  *           1 if completing this irq brought us back to base (no active irqs)
2622  *           0 if there is still an irq active after this one was completed
2623  * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
2624  */
2625 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2626 /**
2627  * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
2628  * @opaque: the NVIC
2629  * @irq: the exception number to mark pending
2630  * @secure: false for non-banked exceptions or for the nonsecure
2631  * version of a banked exception, true for the secure version of a banked
2632  * exception.
2633  *
2634  * Return whether an exception is "ready", i.e. whether the exception is
2635  * enabled and is configured at a priority which would allow it to
2636  * interrupt the current execution priority. This controls whether the
2637  * RDY bit for it in the FPCCR is set.
2638  */
2639 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
2640 /**
2641  * armv7m_nvic_raw_execution_priority: return the raw execution priority
2642  * @opaque: the NVIC
2643  *
2644  * Returns: the raw execution priority as defined by the v8M architecture.
2645  * This is the execution priority minus the effects of AIRCR.PRIS,
2646  * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
2647  * (v8M ARM ARM I_PKLD.)
2648  */
2649 int armv7m_nvic_raw_execution_priority(void *opaque);
2650 /**
2651  * armv7m_nvic_neg_prio_requested: return true if the requested execution
2652  * priority is negative for the specified security state.
2653  * @opaque: the NVIC
2654  * @secure: the security state to test
2655  * This corresponds to the pseudocode IsReqExecPriNeg().
2656  */
2657 #ifndef CONFIG_USER_ONLY
2658 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2659 #else
2660 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2661 {
2662     return false;
2663 }
2664 #endif
2665 
2666 /* Interface for defining coprocessor registers.
2667  * Registers are defined in tables of arm_cp_reginfo structs
2668  * which are passed to define_arm_cp_regs().
2669  */
2670 
2671 /* When looking up a coprocessor register we look for it
2672  * via an integer which encodes all of:
2673  *  coprocessor number
2674  *  Crn, Crm, opc1, opc2 fields
2675  *  32 or 64 bit register (ie is it accessed via MRC/MCR
2676  *    or via MRRC/MCRR?)
2677  *  non-secure/secure bank (AArch32 only)
2678  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
2679  * (In this case crn and opc2 should be zero.)
2680  * For AArch64, there is no 32/64 bit size distinction;
2681  * instead all registers have a 2 bit op0, 3 bit op1 and op2,
2682  * and 4 bit CRn and CRm. The encoding patterns are chosen
2683  * to be easy to convert to and from the KVM encodings, and also
2684  * so that the hashtable can contain both AArch32 and AArch64
2685  * registers (to allow for interprocessing where we might run
2686  * 32 bit code on a 64 bit core).
2687  */
2688 /* This bit is private to our hashtable cpreg; in KVM register
2689  * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
2690  * in the upper bits of the 64 bit ID.
2691  */
2692 #define CP_REG_AA64_SHIFT 28
2693 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2694 
2695 /* To enable banking of coprocessor registers depending on ns-bit we
2696  * add a bit to distinguish between secure and non-secure cpregs in the
2697  * hashtable.
2698  */
2699 #define CP_REG_NS_SHIFT 29
2700 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2701 
2702 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
2703     ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
2704      ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2705 
2706 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2707     (CP_REG_AA64_MASK |                                 \
2708      ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
2709      ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
2710      ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
2711      ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
2712      ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
2713      ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2714 
2715 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
2716  * version used as a key for the coprocessor register hashtable
2717  */
2718 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2719 {
2720     uint32_t cpregid = kvmid;
2721     if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2722         cpregid |= CP_REG_AA64_MASK;
2723     } else {
2724         if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2725             cpregid |= (1 << 15);
2726         }
2727 
2728         /* KVM is always non-secure so add the NS flag on AArch32 register
2729          * entries.
2730          */
2731          cpregid |= 1 << CP_REG_NS_SHIFT;
2732     }
2733     return cpregid;
2734 }
2735 
2736 /* Convert a truncated 32 bit hashtable key into the full
2737  * 64 bit KVM register ID.
2738  */
2739 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2740 {
2741     uint64_t kvmid;
2742 
2743     if (cpregid & CP_REG_AA64_MASK) {
2744         kvmid = cpregid & ~CP_REG_AA64_MASK;
2745         kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2746     } else {
2747         kvmid = cpregid & ~(1 << 15);
2748         if (cpregid & (1 << 15)) {
2749             kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2750         } else {
2751             kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2752         }
2753     }
2754     return kvmid;
2755 }
2756 
2757 /* Return the highest implemented Exception Level */
2758 static inline int arm_highest_el(CPUARMState *env)
2759 {
2760     if (arm_feature(env, ARM_FEATURE_EL3)) {
2761         return 3;
2762     }
2763     if (arm_feature(env, ARM_FEATURE_EL2)) {
2764         return 2;
2765     }
2766     return 1;
2767 }
2768 
2769 /* Return true if a v7M CPU is in Handler mode */
2770 static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2771 {
2772     return env->v7m.exception != 0;
2773 }
2774 
2775 /* Return the current Exception Level (as per ARMv8; note that this differs
2776  * from the ARMv7 Privilege Level).
2777  */
2778 static inline int arm_current_el(CPUARMState *env)
2779 {
2780     if (arm_feature(env, ARM_FEATURE_M)) {
2781         return arm_v7m_is_handler_mode(env) ||
2782             !(env->v7m.control[env->v7m.secure] & 1);
2783     }
2784 
2785     if (is_a64(env)) {
2786         return extract32(env->pstate, 2, 2);
2787     }
2788 
2789     switch (env->uncached_cpsr & 0x1f) {
2790     case ARM_CPU_MODE_USR:
2791         return 0;
2792     case ARM_CPU_MODE_HYP:
2793         return 2;
2794     case ARM_CPU_MODE_MON:
2795         return 3;
2796     default:
2797         if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2798             /* If EL3 is 32-bit then all secure privileged modes run in
2799              * EL3
2800              */
2801             return 3;
2802         }
2803 
2804         return 1;
2805     }
2806 }
2807 
2808 /**
2809  * write_list_to_cpustate
2810  * @cpu: ARMCPU
2811  *
2812  * For each register listed in the ARMCPU cpreg_indexes list, write
2813  * its value from the cpreg_values list into the ARMCPUState structure.
2814  * This updates TCG's working data structures from KVM data or
2815  * from incoming migration state.
2816  *
2817  * Returns: true if all register values were updated correctly,
2818  * false if some register was unknown or could not be written.
2819  * Note that we do not stop early on failure -- we will attempt
2820  * writing all registers in the list.
2821  */
2822 bool write_list_to_cpustate(ARMCPU *cpu);
2823 
2824 /**
2825  * write_cpustate_to_list:
2826  * @cpu: ARMCPU
2827  * @kvm_sync: true if this is for syncing back to KVM
2828  *
2829  * For each register listed in the ARMCPU cpreg_indexes list, write
2830  * its value from the ARMCPUState structure into the cpreg_values list.
2831  * This is used to copy info from TCG's working data structures into
2832  * KVM or for outbound migration.
2833  *
2834  * @kvm_sync is true if we are doing this in order to sync the
2835  * register state back to KVM. In this case we will only update
2836  * values in the list if the previous list->cpustate sync actually
2837  * successfully wrote the CPU state. Otherwise we will keep the value
2838  * that is in the list.
2839  *
2840  * Returns: true if all register values were read correctly,
2841  * false if some register was unknown or could not be read.
2842  * Note that we do not stop early on failure -- we will attempt
2843  * reading all registers in the list.
2844  */
2845 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2846 
2847 #define ARM_CPUID_TI915T      0x54029152
2848 #define ARM_CPUID_TI925T      0x54029252
2849 
2850 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2851 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2852 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2853 
2854 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
2855 
2856 #define cpu_list arm_cpu_list
2857 
2858 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
2859  *
2860  * If EL3 is 64-bit:
2861  *  + NonSecure EL1 & 0 stage 1
2862  *  + NonSecure EL1 & 0 stage 2
2863  *  + NonSecure EL2
2864  *  + NonSecure EL2 & 0   (ARMv8.1-VHE)
2865  *  + Secure EL1 & 0
2866  *  + Secure EL3
2867  * If EL3 is 32-bit:
2868  *  + NonSecure PL1 & 0 stage 1
2869  *  + NonSecure PL1 & 0 stage 2
2870  *  + NonSecure PL2
2871  *  + Secure PL0
2872  *  + Secure PL1
2873  * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2874  *
2875  * For QEMU, an mmu_idx is not quite the same as a translation regime because:
2876  *  1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
2877  *     because they may differ in access permissions even if the VA->PA map is
2878  *     the same
2879  *  2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2880  *     translation, which means that we have one mmu_idx that deals with two
2881  *     concatenated translation regimes [this sort of combined s1+2 TLB is
2882  *     architecturally permitted]
2883  *  3. we don't need to allocate an mmu_idx to translations that we won't be
2884  *     handling via the TLB. The only way to do a stage 1 translation without
2885  *     the immediate stage 2 translation is via the ATS or AT system insns,
2886  *     which can be slow-pathed and always do a page table walk.
2887  *     The only use of stage 2 translations is either as part of an s1+2
2888  *     lookup or when loading the descriptors during a stage 1 page table walk,
2889  *     and in both those cases we don't use the TLB.
2890  *  4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2891  *     translation regimes, because they map reasonably well to each other
2892  *     and they can't both be active at the same time.
2893  *  5. we want to be able to use the TLB for accesses done as part of a
2894  *     stage1 page table walk, rather than having to walk the stage2 page
2895  *     table over and over.
2896  *  6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
2897  *     Never (PAN) bit within PSTATE.
2898  *  7. we fold together the secure and non-secure regimes for A-profile,
2899  *     because there are no banked system registers for aarch64, so the
2900  *     process of switching between secure and non-secure is
2901  *     already heavyweight.
2902  *
2903  * This gives us the following list of cases:
2904  *
2905  * EL0 EL1&0 stage 1+2 (aka NS PL0)
2906  * EL1 EL1&0 stage 1+2 (aka NS PL1)
2907  * EL1 EL1&0 stage 1+2 +PAN
2908  * EL0 EL2&0
2909  * EL2 EL2&0
2910  * EL2 EL2&0 +PAN
2911  * EL2 (aka NS PL2)
2912  * EL3 (aka S PL1)
2913  * Physical (NS & S)
2914  * Stage2 (NS & S)
2915  *
2916  * for a total of 12 different mmu_idx.
2917  *
2918  * R profile CPUs have an MPU, but can use the same set of MMU indexes
2919  * as A profile. They only need to distinguish EL0 and EL1 (and
2920  * EL2 if we ever model a Cortex-R52).
2921  *
2922  * M profile CPUs are rather different as they do not have a true MMU.
2923  * They have the following different MMU indexes:
2924  *  User
2925  *  Privileged
2926  *  User, execution priority negative (ie the MPU HFNMIENA bit may apply)
2927  *  Privileged, execution priority negative (ditto)
2928  * If the CPU supports the v8M Security Extension then there are also:
2929  *  Secure User
2930  *  Secure Privileged
2931  *  Secure User, execution priority negative
2932  *  Secure Privileged, execution priority negative
2933  *
2934  * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
2935  * are not quite the same -- different CPU types (most notably M profile
2936  * vs A/R profile) would like to use MMU indexes with different semantics,
2937  * but since we don't ever need to use all of those in a single CPU we
2938  * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
2939  * modes + total number of M profile MMU modes". The lower bits of
2940  * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
2941  * the same for any particular CPU.
2942  * Variables of type ARMMUIdx are always full values, and the core
2943  * index values are in variables of type 'int'.
2944  *
2945  * Our enumeration includes at the end some entries which are not "true"
2946  * mmu_idx values in that they don't have corresponding TLBs and are only
2947  * valid for doing slow path page table walks.
2948  *
2949  * The constant names here are patterned after the general style of the names
2950  * of the AT/ATS operations.
2951  * The values used are carefully arranged to make mmu_idx => EL lookup easy.
2952  * For M profile we arrange them to have a bit for priv, a bit for negpri
2953  * and a bit for secure.
2954  */
2955 #define ARM_MMU_IDX_A     0x10  /* A profile */
2956 #define ARM_MMU_IDX_NOTLB 0x20  /* does not have a TLB */
2957 #define ARM_MMU_IDX_M     0x40  /* M profile */
2958 
2959 /* Meanings of the bits for M profile mmu idx values */
2960 #define ARM_MMU_IDX_M_PRIV   0x1
2961 #define ARM_MMU_IDX_M_NEGPRI 0x2
2962 #define ARM_MMU_IDX_M_S      0x4  /* Secure */
2963 
2964 #define ARM_MMU_IDX_TYPE_MASK \
2965     (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
2966 #define ARM_MMU_IDX_COREIDX_MASK 0xf
2967 
2968 typedef enum ARMMMUIdx {
2969     /*
2970      * A-profile.
2971      */
2972     ARMMMUIdx_E10_0     = 0 | ARM_MMU_IDX_A,
2973     ARMMMUIdx_E20_0     = 1 | ARM_MMU_IDX_A,
2974     ARMMMUIdx_E10_1     = 2 | ARM_MMU_IDX_A,
2975     ARMMMUIdx_E20_2     = 3 | ARM_MMU_IDX_A,
2976     ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A,
2977     ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A,
2978     ARMMMUIdx_E2        = 6 | ARM_MMU_IDX_A,
2979     ARMMMUIdx_E3        = 7 | ARM_MMU_IDX_A,
2980 
2981     /* TLBs with 1-1 mapping to the physical address spaces. */
2982     ARMMMUIdx_Phys_NS   = 8 | ARM_MMU_IDX_A,
2983     ARMMMUIdx_Phys_S    = 9 | ARM_MMU_IDX_A,
2984 
2985     /*
2986      * Used for second stage of an S12 page table walk, or for descriptor
2987      * loads during first stage of an S1 page table walk.  Note that both
2988      * are in use simultaneously for SecureEL2: the security state for
2989      * the S2 ptw is selected by the NS bit from the S1 ptw.
2990      */
2991     ARMMMUIdx_Stage2    = 10 | ARM_MMU_IDX_A,
2992     ARMMMUIdx_Stage2_S  = 11 | ARM_MMU_IDX_A,
2993 
2994     /*
2995      * These are not allocated TLBs and are used only for AT system
2996      * instructions or for the first stage of an S12 page table walk.
2997      */
2998     ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
2999     ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
3000     ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
3001 
3002     /*
3003      * M-profile.
3004      */
3005     ARMMMUIdx_MUser = ARM_MMU_IDX_M,
3006     ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
3007     ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
3008     ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
3009     ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
3010     ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
3011     ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
3012     ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
3013 } ARMMMUIdx;
3014 
3015 /*
3016  * Bit macros for the core-mmu-index values for each index,
3017  * for use when calling tlb_flush_by_mmuidx() and friends.
3018  */
3019 #define TO_CORE_BIT(NAME) \
3020     ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
3021 
3022 typedef enum ARMMMUIdxBit {
3023     TO_CORE_BIT(E10_0),
3024     TO_CORE_BIT(E20_0),
3025     TO_CORE_BIT(E10_1),
3026     TO_CORE_BIT(E10_1_PAN),
3027     TO_CORE_BIT(E2),
3028     TO_CORE_BIT(E20_2),
3029     TO_CORE_BIT(E20_2_PAN),
3030     TO_CORE_BIT(E3),
3031     TO_CORE_BIT(Stage2),
3032     TO_CORE_BIT(Stage2_S),
3033 
3034     TO_CORE_BIT(MUser),
3035     TO_CORE_BIT(MPriv),
3036     TO_CORE_BIT(MUserNegPri),
3037     TO_CORE_BIT(MPrivNegPri),
3038     TO_CORE_BIT(MSUser),
3039     TO_CORE_BIT(MSPriv),
3040     TO_CORE_BIT(MSUserNegPri),
3041     TO_CORE_BIT(MSPrivNegPri),
3042 } ARMMMUIdxBit;
3043 
3044 #undef TO_CORE_BIT
3045 
3046 #define MMU_USER_IDX 0
3047 
3048 /* Indexes used when registering address spaces with cpu_address_space_init */
3049 typedef enum ARMASIdx {
3050     ARMASIdx_NS = 0,
3051     ARMASIdx_S = 1,
3052     ARMASIdx_TagNS = 2,
3053     ARMASIdx_TagS = 3,
3054 } ARMASIdx;
3055 
3056 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
3057 {
3058     /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
3059      * CSSELR is RAZ/WI.
3060      */
3061     return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
3062 }
3063 
3064 static inline bool arm_sctlr_b(CPUARMState *env)
3065 {
3066     return
3067         /* We need not implement SCTLR.ITD in user-mode emulation, so
3068          * let linux-user ignore the fact that it conflicts with SCTLR_B.
3069          * This lets people run BE32 binaries with "-cpu any".
3070          */
3071 #ifndef CONFIG_USER_ONLY
3072         !arm_feature(env, ARM_FEATURE_V7) &&
3073 #endif
3074         (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3075 }
3076 
3077 uint64_t arm_sctlr(CPUARMState *env, int el);
3078 
3079 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
3080                                                   bool sctlr_b)
3081 {
3082 #ifdef CONFIG_USER_ONLY
3083     /*
3084      * In system mode, BE32 is modelled in line with the
3085      * architecture (as word-invariant big-endianness), where loads
3086      * and stores are done little endian but from addresses which
3087      * are adjusted by XORing with the appropriate constant. So the
3088      * endianness to use for the raw data access is not affected by
3089      * SCTLR.B.
3090      * In user mode, however, we model BE32 as byte-invariant
3091      * big-endianness (because user-only code cannot tell the
3092      * difference), and so we need to use a data access endianness
3093      * that depends on SCTLR.B.
3094      */
3095     if (sctlr_b) {
3096         return true;
3097     }
3098 #endif
3099     /* In 32bit endianness is determined by looking at CPSR's E bit */
3100     return env->uncached_cpsr & CPSR_E;
3101 }
3102 
3103 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3104 {
3105     return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3106 }
3107 
3108 /* Return true if the processor is in big-endian mode. */
3109 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3110 {
3111     if (!is_a64(env)) {
3112         return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3113     } else {
3114         int cur_el = arm_current_el(env);
3115         uint64_t sctlr = arm_sctlr(env, cur_el);
3116         return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3117     }
3118 }
3119 
3120 #include "exec/cpu-all.h"
3121 
3122 /*
3123  * We have more than 32-bits worth of state per TB, so we split the data
3124  * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
3125  * We collect these two parts in CPUARMTBFlags where they are named
3126  * flags and flags2 respectively.
3127  *
3128  * The flags that are shared between all execution modes, TBFLAG_ANY,
3129  * are stored in flags.  The flags that are specific to a given mode
3130  * are stores in flags2.  Since cs_base is sized on the configured
3131  * address size, flags2 always has 64-bits for A64, and a minimum of
3132  * 32-bits for A32 and M32.
3133  *
3134  * The bits for 32-bit A-profile and M-profile partially overlap:
3135  *
3136  *  31         23         11 10             0
3137  * +-------------+----------+----------------+
3138  * |             |          |   TBFLAG_A32   |
3139  * | TBFLAG_AM32 |          +-----+----------+
3140  * |             |                |TBFLAG_M32|
3141  * +-------------+----------------+----------+
3142  *  31         23                6 5        0
3143  *
3144  * Unless otherwise noted, these bits are cached in env->hflags.
3145  */
3146 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
3147 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
3148 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1)      /* Not cached. */
3149 FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
3150 FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
3151 /* Target EL if we take a floating-point-disabled exception */
3152 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
3153 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
3154 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
3155 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
3156 
3157 /*
3158  * Bit usage when in AArch32 state, both A- and M-profile.
3159  */
3160 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8)      /* Not cached. */
3161 FIELD(TBFLAG_AM32, THUMB, 23, 1)         /* Not cached. */
3162 
3163 /*
3164  * Bit usage when in AArch32 state, for A-profile only.
3165  */
3166 FIELD(TBFLAG_A32, VECLEN, 0, 3)         /* Not cached. */
3167 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2)     /* Not cached. */
3168 /*
3169  * We store the bottom two bits of the CPAR as TB flags and handle
3170  * checks on the other bits at runtime. This shares the same bits as
3171  * VECSTRIDE, which is OK as no XScale CPU has VFP.
3172  * Not cached, because VECLEN+VECSTRIDE are not cached.
3173  */
3174 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2)
3175 FIELD(TBFLAG_A32, VFPEN, 7, 1)         /* Partially cached, minus FPEXC. */
3176 FIELD(TBFLAG_A32, SCTLR__B, 8, 1)      /* Cannot overlap with SCTLR_B */
3177 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
3178 /*
3179  * Indicates whether cp register reads and writes by guest code should access
3180  * the secure or nonsecure bank of banked registers; note that this is not
3181  * the same thing as the current security state of the processor!
3182  */
3183 FIELD(TBFLAG_A32, NS, 10, 1)
3184 /*
3185  * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not.
3186  * This requires an SME trap from AArch32 mode when using NEON.
3187  */
3188 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
3189 
3190 /*
3191  * Bit usage when in AArch32 state, for M-profile only.
3192  */
3193 /* Handler (ie not Thread) mode */
3194 FIELD(TBFLAG_M32, HANDLER, 0, 1)
3195 /* Whether we should generate stack-limit checks */
3196 FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
3197 /* Set if FPCCR.LSPACT is set */
3198 FIELD(TBFLAG_M32, LSPACT, 2, 1)                 /* Not cached. */
3199 /* Set if we must create a new FP context */
3200 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1)     /* Not cached. */
3201 /* Set if FPCCR.S does not match current security state */
3202 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1)          /* Not cached. */
3203 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */
3204 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1)            /* Not cached. */
3205 /* Set if in secure mode */
3206 FIELD(TBFLAG_M32, SECURE, 6, 1)
3207 
3208 /*
3209  * Bit usage when in AArch64 state
3210  */
3211 FIELD(TBFLAG_A64, TBII, 0, 2)
3212 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3213 /* The current vector length, either NVL or SVL. */
3214 FIELD(TBFLAG_A64, VL, 4, 4)
3215 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3216 FIELD(TBFLAG_A64, BT, 9, 1)
3217 FIELD(TBFLAG_A64, BTYPE, 10, 2)         /* Not cached. */
3218 FIELD(TBFLAG_A64, TBID, 12, 2)
3219 FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3220 FIELD(TBFLAG_A64, ATA, 15, 1)
3221 FIELD(TBFLAG_A64, TCMA, 16, 2)
3222 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3223 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3224 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
3225 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
3226 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
3227 FIELD(TBFLAG_A64, SVL, 24, 4)
3228 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
3229 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
3230 
3231 /*
3232  * Helpers for using the above.
3233  */
3234 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \
3235     (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
3236 #define DP_TBFLAG_A64(DST, WHICH, VAL) \
3237     (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL))
3238 #define DP_TBFLAG_A32(DST, WHICH, VAL) \
3239     (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
3240 #define DP_TBFLAG_M32(DST, WHICH, VAL) \
3241     (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
3242 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \
3243     (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
3244 
3245 #define EX_TBFLAG_ANY(IN, WHICH)   FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
3246 #define EX_TBFLAG_A64(IN, WHICH)   FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH)
3247 #define EX_TBFLAG_A32(IN, WHICH)   FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
3248 #define EX_TBFLAG_M32(IN, WHICH)   FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
3249 #define EX_TBFLAG_AM32(IN, WHICH)  FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
3250 
3251 /**
3252  * cpu_mmu_index:
3253  * @env: The cpu environment
3254  * @ifetch: True for code access, false for data access.
3255  *
3256  * Return the core mmu index for the current translation regime.
3257  * This function is used by generic TCG code paths.
3258  */
3259 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3260 {
3261     return EX_TBFLAG_ANY(env->hflags, MMUIDX);
3262 }
3263 
3264 /**
3265  * sve_vq
3266  * @env: the cpu context
3267  *
3268  * Return the VL cached within env->hflags, in units of quadwords.
3269  */
3270 static inline int sve_vq(CPUARMState *env)
3271 {
3272     return EX_TBFLAG_A64(env->hflags, VL) + 1;
3273 }
3274 
3275 /**
3276  * sme_vq
3277  * @env: the cpu context
3278  *
3279  * Return the SVL cached within env->hflags, in units of quadwords.
3280  */
3281 static inline int sme_vq(CPUARMState *env)
3282 {
3283     return EX_TBFLAG_A64(env->hflags, SVL) + 1;
3284 }
3285 
3286 static inline bool bswap_code(bool sctlr_b)
3287 {
3288 #ifdef CONFIG_USER_ONLY
3289     /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian.
3290      * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0
3291      * would also end up as a mixed-endian mode with BE code, LE data.
3292      */
3293     return
3294 #if TARGET_BIG_ENDIAN
3295         1 ^
3296 #endif
3297         sctlr_b;
3298 #else
3299     /* All code access in ARM is little endian, and there are no loaders
3300      * doing swaps that need to be reversed
3301      */
3302     return 0;
3303 #endif
3304 }
3305 
3306 #ifdef CONFIG_USER_ONLY
3307 static inline bool arm_cpu_bswap_data(CPUARMState *env)
3308 {
3309     return
3310 #if TARGET_BIG_ENDIAN
3311        1 ^
3312 #endif
3313        arm_cpu_data_is_big_endian(env);
3314 }
3315 #endif
3316 
3317 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3318                           target_ulong *cs_base, uint32_t *flags);
3319 
3320 enum {
3321     QEMU_PSCI_CONDUIT_DISABLED = 0,
3322     QEMU_PSCI_CONDUIT_SMC = 1,
3323     QEMU_PSCI_CONDUIT_HVC = 2,
3324 };
3325 
3326 #ifndef CONFIG_USER_ONLY
3327 /* Return the address space index to use for a memory access */
3328 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3329 {
3330     return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3331 }
3332 
3333 /* Return the AddressSpace to use for a memory access
3334  * (which depends on whether the access is S or NS, and whether
3335  * the board gave us a separate AddressSpace for S accesses).
3336  */
3337 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3338 {
3339     return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3340 }
3341 #endif
3342 
3343 /**
3344  * arm_register_pre_el_change_hook:
3345  * Register a hook function which will be called immediately before this
3346  * CPU changes exception level or mode. The hook function will be
3347  * passed a pointer to the ARMCPU and the opaque data pointer passed
3348  * to this function when the hook was registered.
3349  *
3350  * Note that if a pre-change hook is called, any registered post-change hooks
3351  * are guaranteed to subsequently be called.
3352  */
3353 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3354                                  void *opaque);
3355 /**
3356  * arm_register_el_change_hook:
3357  * Register a hook function which will be called immediately after this
3358  * CPU changes exception level or mode. The hook function will be
3359  * passed a pointer to the ARMCPU and the opaque data pointer passed
3360  * to this function when the hook was registered.
3361  *
3362  * Note that any registered hooks registered here are guaranteed to be called
3363  * if pre-change hooks have been.
3364  */
3365 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3366         *opaque);
3367 
3368 /**
3369  * arm_rebuild_hflags:
3370  * Rebuild the cached TBFLAGS for arbitrary changed processor state.
3371  */
3372 void arm_rebuild_hflags(CPUARMState *env);
3373 
3374 /**
3375  * aa32_vfp_dreg:
3376  * Return a pointer to the Dn register within env in 32-bit mode.
3377  */
3378 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3379 {
3380     return &env->vfp.zregs[regno >> 1].d[regno & 1];
3381 }
3382 
3383 /**
3384  * aa32_vfp_qreg:
3385  * Return a pointer to the Qn register within env in 32-bit mode.
3386  */
3387 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3388 {
3389     return &env->vfp.zregs[regno].d[0];
3390 }
3391 
3392 /**
3393  * aa64_vfp_qreg:
3394  * Return a pointer to the Qn register within env in 64-bit mode.
3395  */
3396 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3397 {
3398     return &env->vfp.zregs[regno].d[0];
3399 }
3400 
3401 /* Shared between translate-sve.c and sve_helper.c.  */
3402 extern const uint64_t pred_esz_masks[5];
3403 
3404 /*
3405  * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
3406  * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect
3407  * mprotect but PROT_BTI may be cleared.  C.f. the kernel's VM_ARCH_CLEAR.
3408  */
3409 #define PAGE_BTI            PAGE_TARGET_1
3410 #define PAGE_MTE            PAGE_TARGET_2
3411 #define PAGE_TARGET_STICKY  PAGE_MTE
3412 
3413 /* We associate one allocation tag per 16 bytes, the minimum.  */
3414 #define LOG2_TAG_GRANULE 4
3415 #define TAG_GRANULE      (1 << LOG2_TAG_GRANULE)
3416 
3417 #ifdef CONFIG_USER_ONLY
3418 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1))
3419 #endif
3420 
3421 #ifdef TARGET_TAGGED_ADDRESSES
3422 /**
3423  * cpu_untagged_addr:
3424  * @cs: CPU context
3425  * @x: tagged address
3426  *
3427  * Remove any address tag from @x.  This is explicitly related to the
3428  * linux syscall TIF_TAGGED_ADDR setting, not TBI in general.
3429  *
3430  * There should be a better place to put this, but we need this in
3431  * include/exec/cpu_ldst.h, and not some place linux-user specific.
3432  */
3433 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x)
3434 {
3435     ARMCPU *cpu = ARM_CPU(cs);
3436     if (cpu->env.tagged_addr_enable) {
3437         /*
3438          * TBI is enabled for userspace but not kernelspace addresses.
3439          * Only clear the tag if bit 55 is clear.
3440          */
3441         x &= sextract64(x, 0, 56);
3442     }
3443     return x;
3444 }
3445 #endif
3446 
3447 /*
3448  * Naming convention for isar_feature functions:
3449  * Functions which test 32-bit ID registers should have _aa32_ in
3450  * their name. Functions which test 64-bit ID registers should have
3451  * _aa64_ in their name. These must only be used in code where we
3452  * know for certain that the CPU has AArch32 or AArch64 respectively
3453  * or where the correct answer for a CPU which doesn't implement that
3454  * CPU state is "false" (eg when generating A32 or A64 code, if adding
3455  * system registers that are specific to that CPU state, for "should
3456  * we let this system register bit be set" tests where the 32-bit
3457  * flavour of the register doesn't have the bit, and so on).
3458  * Functions which simply ask "does this feature exist at all" have
3459  * _any_ in their name, and always return the logical OR of the _aa64_
3460  * and the _aa32_ function.
3461  */
3462 
3463 /*
3464  * 32-bit feature tests via id registers.
3465  */
3466 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
3467 {
3468     return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3469 }
3470 
3471 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
3472 {
3473     return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3474 }
3475 
3476 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
3477 {
3478     /* (M-profile) low-overhead loops and branch future */
3479     return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
3480 }
3481 
3482 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
3483 {
3484     return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3485 }
3486 
3487 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3488 {
3489     return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3490 }
3491 
3492 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3493 {
3494     return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3495 }
3496 
3497 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3498 {
3499     return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3500 }
3501 
3502 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3503 {
3504     return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3505 }
3506 
3507 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3508 {
3509     return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3510 }
3511 
3512 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3513 {
3514     return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3515 }
3516 
3517 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3518 {
3519     return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3520 }
3521 
3522 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
3523 {
3524     return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
3525 }
3526 
3527 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3528 {
3529     return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3530 }
3531 
3532 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
3533 {
3534     return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
3535 }
3536 
3537 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
3538 {
3539     return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
3540 }
3541 
3542 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
3543 {
3544     return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
3545 }
3546 
3547 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id)
3548 {
3549     return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0;
3550 }
3551 
3552 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
3553 {
3554     return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
3555 }
3556 
3557 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
3558 {
3559     return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
3560 }
3561 
3562 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
3563 {
3564     return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
3565 }
3566 
3567 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
3568 {
3569     /*
3570      * Return true if M-profile state handling insns
3571      * (VSCCLRM, CLRM, FPCTX access insns) are implemented
3572      */
3573     return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
3574 }
3575 
3576 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
3577 {
3578     /* Sadly this is encoded differently for A-profile and M-profile */
3579     if (isar_feature_aa32_mprofile(id)) {
3580         return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
3581     } else {
3582         return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
3583     }
3584 }
3585 
3586 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id)
3587 {
3588     /*
3589      * Return true if MVE is supported (either integer or floating point).
3590      * We must check for M-profile as the MVFR1 field means something
3591      * else for A-profile.
3592      */
3593     return isar_feature_aa32_mprofile(id) &&
3594         FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0;
3595 }
3596 
3597 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id)
3598 {
3599     /*
3600      * Return true if MVE is supported (either integer or floating point).
3601      * We must check for M-profile as the MVFR1 field means something
3602      * else for A-profile.
3603      */
3604     return isar_feature_aa32_mprofile(id) &&
3605         FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2;
3606 }
3607 
3608 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
3609 {
3610     /*
3611      * Return true if either VFP or SIMD is implemented.
3612      * In this case, a minimum of VFP w/ D0-D15.
3613      */
3614     return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
3615 }
3616 
3617 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
3618 {
3619     /* Return true if D16-D31 are implemented */
3620     return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
3621 }
3622 
3623 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3624 {
3625     return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
3626 }
3627 
3628 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
3629 {
3630     /* Return true if CPU supports single precision floating point, VFPv2 */
3631     return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
3632 }
3633 
3634 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
3635 {
3636     /* Return true if CPU supports single precision floating point, VFPv3 */
3637     return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
3638 }
3639 
3640 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
3641 {
3642     /* Return true if CPU supports double precision floating point, VFPv2 */
3643     return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
3644 }
3645 
3646 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
3647 {
3648     /* Return true if CPU supports double precision floating point, VFPv3 */
3649     return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
3650 }
3651 
3652 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
3653 {
3654     return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
3655 }
3656 
3657 /*
3658  * We always set the FP and SIMD FP16 fields to indicate identical
3659  * levels of support (assuming SIMD is implemented at all), so
3660  * we only need one set of accessors.
3661  */
3662 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
3663 {
3664     return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
3665 }
3666 
3667 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
3668 {
3669     return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
3670 }
3671 
3672 /*
3673  * Note that this ID register field covers both VFP and Neon FMAC,
3674  * so should usually be tested in combination with some other
3675  * check that confirms the presence of whichever of VFP or Neon is
3676  * relevant, to avoid accidentally enabling a Neon feature on
3677  * a VFP-no-Neon core or vice-versa.
3678  */
3679 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
3680 {
3681     return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
3682 }
3683 
3684 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
3685 {
3686     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
3687 }
3688 
3689 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
3690 {
3691     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
3692 }
3693 
3694 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
3695 {
3696     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
3697 }
3698 
3699 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
3700 {
3701     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
3702 }
3703 
3704 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
3705 {
3706     return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
3707 }
3708 
3709 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
3710 {
3711     return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
3712 }
3713 
3714 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
3715 {
3716     return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
3717 }
3718 
3719 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id)
3720 {
3721     /* 0xf means "non-standard IMPDEF PMU" */
3722     return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
3723         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3724 }
3725 
3726 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id)
3727 {
3728     /* 0xf means "non-standard IMPDEF PMU" */
3729     return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
3730         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3731 }
3732 
3733 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id)
3734 {
3735     /* 0xf means "non-standard IMPDEF PMU" */
3736     return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 &&
3737         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3738 }
3739 
3740 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
3741 {
3742     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
3743 }
3744 
3745 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
3746 {
3747     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
3748 }
3749 
3750 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
3751 {
3752     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
3753 }
3754 
3755 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
3756 {
3757     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
3758 }
3759 
3760 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
3761 {
3762     return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
3763 }
3764 
3765 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
3766 {
3767     return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
3768 }
3769 
3770 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id)
3771 {
3772     return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5;
3773 }
3774 
3775 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
3776 {
3777     return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
3778 }
3779 
3780 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id)
3781 {
3782     return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0;
3783 }
3784 
3785 /*
3786  * 64-bit feature tests via id registers.
3787  */
3788 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
3789 {
3790     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
3791 }
3792 
3793 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
3794 {
3795     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
3796 }
3797 
3798 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
3799 {
3800     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
3801 }
3802 
3803 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
3804 {
3805     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
3806 }
3807 
3808 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
3809 {
3810     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
3811 }
3812 
3813 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
3814 {
3815     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
3816 }
3817 
3818 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
3819 {
3820     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
3821 }
3822 
3823 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
3824 {
3825     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
3826 }
3827 
3828 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
3829 {
3830     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
3831 }
3832 
3833 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
3834 {
3835     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
3836 }
3837 
3838 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
3839 {
3840     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
3841 }
3842 
3843 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
3844 {
3845     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
3846 }
3847 
3848 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
3849 {
3850     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
3851 }
3852 
3853 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
3854 {
3855     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
3856 }
3857 
3858 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
3859 {
3860     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
3861 }
3862 
3863 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
3864 {
3865     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
3866 }
3867 
3868 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
3869 {
3870     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
3871 }
3872 
3873 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
3874 {
3875     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
3876 }
3877 
3878 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
3879 {
3880     /*
3881      * Return true if any form of pauth is enabled, as this
3882      * predicate controls migration of the 128-bit keys.
3883      */
3884     return (id->id_aa64isar1 &
3885             (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
3886              FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
3887              FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
3888              FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
3889 }
3890 
3891 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
3892 {
3893     /*
3894      * Return true if pauth is enabled with the architected QARMA algorithm.
3895      * QEMU will always set APA+GPA to the same value.
3896      */
3897     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
3898 }
3899 
3900 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
3901 {
3902     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
3903 }
3904 
3905 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
3906 {
3907     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
3908 }
3909 
3910 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
3911 {
3912     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
3913 }
3914 
3915 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
3916 {
3917     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
3918 }
3919 
3920 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
3921 {
3922     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
3923 }
3924 
3925 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
3926 {
3927     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
3928 }
3929 
3930 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
3931 {
3932     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
3933 }
3934 
3935 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
3936 {
3937     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
3938 }
3939 
3940 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
3941 {
3942     /* We always set the AdvSIMD and FP fields identically.  */
3943     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
3944 }
3945 
3946 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
3947 {
3948     /* We always set the AdvSIMD and FP fields identically wrt FP16.  */
3949     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3950 }
3951 
3952 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
3953 {
3954     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
3955 }
3956 
3957 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
3958 {
3959     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
3960 }
3961 
3962 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
3963 {
3964     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
3965 }
3966 
3967 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
3968 {
3969     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
3970 }
3971 
3972 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id)
3973 {
3974     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2;
3975 }
3976 
3977 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
3978 {
3979     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
3980 }
3981 
3982 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
3983 {
3984     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
3985 }
3986 
3987 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
3988 {
3989     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
3990 }
3991 
3992 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
3993 {
3994     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
3995 }
3996 
3997 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
3998 {
3999     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
4000 }
4001 
4002 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
4003 {
4004     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
4005 }
4006 
4007 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
4008 {
4009     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
4010 }
4011 
4012 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
4013 {
4014     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
4015 }
4016 
4017 static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
4018 {
4019     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
4020 }
4021 
4022 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
4023 {
4024     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
4025 }
4026 
4027 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
4028 {
4029     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
4030 }
4031 
4032 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
4033 {
4034     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
4035 }
4036 
4037 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
4038 {
4039     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
4040 }
4041 
4042 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
4043 {
4044     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
4045 }
4046 
4047 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
4048 {
4049     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
4050 }
4051 
4052 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
4053 {
4054     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
4055         FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4056 }
4057 
4058 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id)
4059 {
4060     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
4061         FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4062 }
4063 
4064 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
4065 {
4066     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 &&
4067         FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4068 }
4069 
4070 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
4071 {
4072     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
4073 }
4074 
4075 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
4076 {
4077     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
4078 }
4079 
4080 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
4081 {
4082     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
4083 }
4084 
4085 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
4086 {
4087     return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
4088 }
4089 
4090 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
4091 {
4092     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
4093     return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
4094 }
4095 
4096 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
4097 {
4098     return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
4099 }
4100 
4101 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
4102 {
4103     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
4104     return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
4105 }
4106 
4107 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
4108 {
4109     return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
4110 }
4111 
4112 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
4113 {
4114     return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
4115 }
4116 
4117 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
4118 {
4119     return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
4120 }
4121 
4122 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
4123 {
4124     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
4125     return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
4126 }
4127 
4128 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
4129 {
4130     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
4131     return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
4132 }
4133 
4134 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
4135 {
4136     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
4137     return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
4138 }
4139 
4140 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
4141 {
4142     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
4143 }
4144 
4145 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
4146 {
4147     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
4148 }
4149 
4150 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
4151 {
4152     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
4153 }
4154 
4155 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
4156 {
4157     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
4158 }
4159 
4160 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
4161 {
4162     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
4163 }
4164 
4165 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
4166 {
4167     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
4168 }
4169 
4170 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
4171 {
4172     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
4173 }
4174 
4175 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
4176 {
4177     int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
4178     if (key >= 2) {
4179         return true;      /* FEAT_CSV2_2 */
4180     }
4181     if (key == 1) {
4182         key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
4183         return key >= 2;  /* FEAT_CSV2_1p2 */
4184     }
4185     return false;
4186 }
4187 
4188 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
4189 {
4190     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
4191 }
4192 
4193 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
4194 {
4195     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
4196 }
4197 
4198 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
4199 {
4200     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
4201 }
4202 
4203 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
4204 {
4205     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
4206 }
4207 
4208 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
4209 {
4210     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
4211 }
4212 
4213 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
4214 {
4215     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
4216 }
4217 
4218 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
4219 {
4220     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0;
4221 }
4222 
4223 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
4224 {
4225     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
4226 }
4227 
4228 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
4229 {
4230     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
4231 }
4232 
4233 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
4234 {
4235     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
4236 }
4237 
4238 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
4239 {
4240     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
4241 }
4242 
4243 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
4244 {
4245     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
4246 }
4247 
4248 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
4249 {
4250     return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64);
4251 }
4252 
4253 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id)
4254 {
4255     return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf;
4256 }
4257 
4258 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
4259 {
4260     return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
4261 }
4262 
4263 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
4264 {
4265     return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
4266 }
4267 
4268 /*
4269  * Feature tests for "does this exist in either 32-bit or 64-bit?"
4270  */
4271 static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
4272 {
4273     return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
4274 }
4275 
4276 static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
4277 {
4278     return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
4279 }
4280 
4281 static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id)
4282 {
4283     return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id);
4284 }
4285 
4286 static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id)
4287 {
4288     return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id);
4289 }
4290 
4291 static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id)
4292 {
4293     return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id);
4294 }
4295 
4296 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
4297 {
4298     return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
4299 }
4300 
4301 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
4302 {
4303     return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
4304 }
4305 
4306 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
4307 {
4308     return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
4309 }
4310 
4311 static inline bool isar_feature_any_ras(const ARMISARegisters *id)
4312 {
4313     return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
4314 }
4315 
4316 /*
4317  * Forward to the above feature tests given an ARMCPU pointer.
4318  */
4319 #define cpu_isar_feature(name, cpu) \
4320     ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
4321 
4322 #endif
4323