xref: /openbmc/qemu/target/arm/cpu.h (revision c63ca4ff)
1 /*
2  * ARM virtual CPU header
3  *
4  *  Copyright (c) 2003 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef ARM_CPU_H
21 #define ARM_CPU_H
22 
23 #include "kvm-consts.h"
24 #include "hw/registerfields.h"
25 #include "cpu-qom.h"
26 #include "exec/cpu-defs.h"
27 #include "qapi/qapi-types-common.h"
28 
29 /* ARM processors have a weak memory model */
30 #define TCG_GUEST_DEFAULT_MO      (0)
31 
32 #ifdef TARGET_AARCH64
33 #define KVM_HAVE_MCE_INJECTION 1
34 #endif
35 
36 #define EXCP_UDEF            1   /* undefined instruction */
37 #define EXCP_SWI             2   /* software interrupt */
38 #define EXCP_PREFETCH_ABORT  3
39 #define EXCP_DATA_ABORT      4
40 #define EXCP_IRQ             5
41 #define EXCP_FIQ             6
42 #define EXCP_BKPT            7
43 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
44 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
45 #define EXCP_HVC            11   /* HyperVisor Call */
46 #define EXCP_HYP_TRAP       12
47 #define EXCP_SMC            13   /* Secure Monitor Call */
48 #define EXCP_VIRQ           14
49 #define EXCP_VFIQ           15
50 #define EXCP_SEMIHOST       16   /* semihosting call */
51 #define EXCP_NOCP           17   /* v7M NOCP UsageFault */
52 #define EXCP_INVSTATE       18   /* v7M INVSTATE UsageFault */
53 #define EXCP_STKOF          19   /* v8M STKOF UsageFault */
54 #define EXCP_LAZYFP         20   /* v7M fault during lazy FP stacking */
55 #define EXCP_LSERR          21   /* v8M LSERR SecureFault */
56 #define EXCP_UNALIGNED      22   /* v7M UNALIGNED UsageFault */
57 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
58 
59 #define ARMV7M_EXCP_RESET   1
60 #define ARMV7M_EXCP_NMI     2
61 #define ARMV7M_EXCP_HARD    3
62 #define ARMV7M_EXCP_MEM     4
63 #define ARMV7M_EXCP_BUS     5
64 #define ARMV7M_EXCP_USAGE   6
65 #define ARMV7M_EXCP_SECURE  7
66 #define ARMV7M_EXCP_SVC     11
67 #define ARMV7M_EXCP_DEBUG   12
68 #define ARMV7M_EXCP_PENDSV  14
69 #define ARMV7M_EXCP_SYSTICK 15
70 
71 /* For M profile, some registers are banked secure vs non-secure;
72  * these are represented as a 2-element array where the first element
73  * is the non-secure copy and the second is the secure copy.
74  * When the CPU does not have implement the security extension then
75  * only the first element is used.
76  * This means that the copy for the current security state can be
77  * accessed via env->registerfield[env->v7m.secure] (whether the security
78  * extension is implemented or not).
79  */
80 enum {
81     M_REG_NS = 0,
82     M_REG_S = 1,
83     M_REG_NUM_BANKS = 2,
84 };
85 
86 /* ARM-specific interrupt pending bits.  */
87 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
88 #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
89 #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
90 
91 /* The usual mapping for an AArch64 system register to its AArch32
92  * counterpart is for the 32 bit world to have access to the lower
93  * half only (with writes leaving the upper half untouched). It's
94  * therefore useful to be able to pass TCG the offset of the least
95  * significant half of a uint64_t struct member.
96  */
97 #ifdef HOST_WORDS_BIGENDIAN
98 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
99 #define offsetofhigh32(S, M) offsetof(S, M)
100 #else
101 #define offsetoflow32(S, M) offsetof(S, M)
102 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
103 #endif
104 
105 /* Meanings of the ARMCPU object's four inbound GPIO lines */
106 #define ARM_CPU_IRQ 0
107 #define ARM_CPU_FIQ 1
108 #define ARM_CPU_VIRQ 2
109 #define ARM_CPU_VFIQ 3
110 
111 /* ARM-specific extra insn start words:
112  * 1: Conditional execution bits
113  * 2: Partial exception syndrome for data aborts
114  */
115 #define TARGET_INSN_START_EXTRA_WORDS 2
116 
117 /* The 2nd extra word holding syndrome info for data aborts does not use
118  * the upper 6 bits nor the lower 14 bits. We mask and shift it down to
119  * help the sleb128 encoder do a better job.
120  * When restoring the CPU state, we shift it back up.
121  */
122 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
123 #define ARM_INSN_START_WORD2_SHIFT 14
124 
125 /* We currently assume float and double are IEEE single and double
126    precision respectively.
127    Doing runtime conversions is tricky because VFP registers may contain
128    integer values (eg. as the result of a FTOSI instruction).
129    s<2n> maps to the least significant half of d<n>
130    s<2n+1> maps to the most significant half of d<n>
131  */
132 
133 /**
134  * DynamicGDBXMLInfo:
135  * @desc: Contains the XML descriptions.
136  * @num: Number of the registers in this XML seen by GDB.
137  * @data: A union with data specific to the set of registers
138  *    @cpregs_keys: Array that contains the corresponding Key of
139  *                  a given cpreg with the same order of the cpreg
140  *                  in the XML description.
141  */
142 typedef struct DynamicGDBXMLInfo {
143     char *desc;
144     int num;
145     union {
146         struct {
147             uint32_t *keys;
148         } cpregs;
149     } data;
150 } DynamicGDBXMLInfo;
151 
152 /* CPU state for each instance of a generic timer (in cp15 c14) */
153 typedef struct ARMGenericTimer {
154     uint64_t cval; /* Timer CompareValue register */
155     uint64_t ctl; /* Timer Control register */
156 } ARMGenericTimer;
157 
158 #define GTIMER_PHYS     0
159 #define GTIMER_VIRT     1
160 #define GTIMER_HYP      2
161 #define GTIMER_SEC      3
162 #define GTIMER_HYPVIRT  4
163 #define NUM_GTIMERS     5
164 
165 typedef struct {
166     uint64_t raw_tcr;
167     uint32_t mask;
168     uint32_t base_mask;
169 } TCR;
170 
171 /* Define a maximum sized vector register.
172  * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
173  * For 64-bit, this is a 2048-bit SVE register.
174  *
175  * Note that the mapping between S, D, and Q views of the register bank
176  * differs between AArch64 and AArch32.
177  * In AArch32:
178  *  Qn = regs[n].d[1]:regs[n].d[0]
179  *  Dn = regs[n / 2].d[n & 1]
180  *  Sn = regs[n / 4].d[n % 4 / 2],
181  *       bits 31..0 for even n, and bits 63..32 for odd n
182  *       (and regs[16] to regs[31] are inaccessible)
183  * In AArch64:
184  *  Zn = regs[n].d[*]
185  *  Qn = regs[n].d[1]:regs[n].d[0]
186  *  Dn = regs[n].d[0]
187  *  Sn = regs[n].d[0] bits 31..0
188  *  Hn = regs[n].d[0] bits 15..0
189  *
190  * This corresponds to the architecturally defined mapping between
191  * the two execution states, and means we do not need to explicitly
192  * map these registers when changing states.
193  *
194  * Align the data for use with TCG host vector operations.
195  */
196 
197 #ifdef TARGET_AARCH64
198 # define ARM_MAX_VQ    16
199 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
200 #else
201 # define ARM_MAX_VQ    1
202 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
203 #endif
204 
205 typedef struct ARMVectorReg {
206     uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
207 } ARMVectorReg;
208 
209 #ifdef TARGET_AARCH64
210 /* In AArch32 mode, predicate registers do not exist at all.  */
211 typedef struct ARMPredicateReg {
212     uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
213 } ARMPredicateReg;
214 
215 /* In AArch32 mode, PAC keys do not exist at all.  */
216 typedef struct ARMPACKey {
217     uint64_t lo, hi;
218 } ARMPACKey;
219 #endif
220 
221 
222 typedef struct CPUARMState {
223     /* Regs for current mode.  */
224     uint32_t regs[16];
225 
226     /* 32/64 switch only happens when taking and returning from
227      * exceptions so the overlap semantics are taken care of then
228      * instead of having a complicated union.
229      */
230     /* Regs for A64 mode.  */
231     uint64_t xregs[32];
232     uint64_t pc;
233     /* PSTATE isn't an architectural register for ARMv8. However, it is
234      * convenient for us to assemble the underlying state into a 32 bit format
235      * identical to the architectural format used for the SPSR. (This is also
236      * what the Linux kernel's 'pstate' field in signal handlers and KVM's
237      * 'pstate' register are.) Of the PSTATE bits:
238      *  NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
239      *    semantics as for AArch32, as described in the comments on each field)
240      *  nRW (also known as M[4]) is kept, inverted, in env->aarch64
241      *  DAIF (exception masks) are kept in env->daif
242      *  BTYPE is kept in env->btype
243      *  all other bits are stored in their correct places in env->pstate
244      */
245     uint32_t pstate;
246     uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
247 
248     /* Cached TBFLAGS state.  See below for which bits are included.  */
249     uint32_t hflags;
250 
251     /* Frequently accessed CPSR bits are stored separately for efficiency.
252        This contains all the other bits.  Use cpsr_{read,write} to access
253        the whole CPSR.  */
254     uint32_t uncached_cpsr;
255     uint32_t spsr;
256 
257     /* Banked registers.  */
258     uint64_t banked_spsr[8];
259     uint32_t banked_r13[8];
260     uint32_t banked_r14[8];
261 
262     /* These hold r8-r12.  */
263     uint32_t usr_regs[5];
264     uint32_t fiq_regs[5];
265 
266     /* cpsr flag cache for faster execution */
267     uint32_t CF; /* 0 or 1 */
268     uint32_t VF; /* V is the bit 31. All other bits are undefined */
269     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
270     uint32_t ZF; /* Z set if zero.  */
271     uint32_t QF; /* 0 or 1 */
272     uint32_t GE; /* cpsr[19:16] */
273     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
274     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
275     uint32_t btype;  /* BTI branch type.  spsr[11:10].  */
276     uint64_t daif; /* exception masks, in the bits they are in PSTATE */
277 
278     uint64_t elr_el[4]; /* AArch64 exception link regs  */
279     uint64_t sp_el[4]; /* AArch64 banked stack pointers */
280 
281     /* System control coprocessor (cp15) */
282     struct {
283         uint32_t c0_cpuid;
284         union { /* Cache size selection */
285             struct {
286                 uint64_t _unused_csselr0;
287                 uint64_t csselr_ns;
288                 uint64_t _unused_csselr1;
289                 uint64_t csselr_s;
290             };
291             uint64_t csselr_el[4];
292         };
293         union { /* System control register. */
294             struct {
295                 uint64_t _unused_sctlr;
296                 uint64_t sctlr_ns;
297                 uint64_t hsctlr;
298                 uint64_t sctlr_s;
299             };
300             uint64_t sctlr_el[4];
301         };
302         uint64_t cpacr_el1; /* Architectural feature access control register */
303         uint64_t cptr_el[4];  /* ARMv8 feature trap registers */
304         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
305         uint64_t sder; /* Secure debug enable register. */
306         uint32_t nsacr; /* Non-secure access control register. */
307         union { /* MMU translation table base 0. */
308             struct {
309                 uint64_t _unused_ttbr0_0;
310                 uint64_t ttbr0_ns;
311                 uint64_t _unused_ttbr0_1;
312                 uint64_t ttbr0_s;
313             };
314             uint64_t ttbr0_el[4];
315         };
316         union { /* MMU translation table base 1. */
317             struct {
318                 uint64_t _unused_ttbr1_0;
319                 uint64_t ttbr1_ns;
320                 uint64_t _unused_ttbr1_1;
321                 uint64_t ttbr1_s;
322             };
323             uint64_t ttbr1_el[4];
324         };
325         uint64_t vttbr_el2; /* Virtualization Translation Table Base.  */
326         /* MMU translation table base control. */
327         TCR tcr_el[4];
328         TCR vtcr_el2; /* Virtualization Translation Control.  */
329         uint32_t c2_data; /* MPU data cacheable bits.  */
330         uint32_t c2_insn; /* MPU instruction cacheable bits.  */
331         union { /* MMU domain access control register
332                  * MPU write buffer control.
333                  */
334             struct {
335                 uint64_t dacr_ns;
336                 uint64_t dacr_s;
337             };
338             struct {
339                 uint64_t dacr32_el2;
340             };
341         };
342         uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
343         uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
344         uint64_t hcr_el2; /* Hypervisor configuration register */
345         uint64_t scr_el3; /* Secure configuration register.  */
346         union { /* Fault status registers.  */
347             struct {
348                 uint64_t ifsr_ns;
349                 uint64_t ifsr_s;
350             };
351             struct {
352                 uint64_t ifsr32_el2;
353             };
354         };
355         union {
356             struct {
357                 uint64_t _unused_dfsr;
358                 uint64_t dfsr_ns;
359                 uint64_t hsr;
360                 uint64_t dfsr_s;
361             };
362             uint64_t esr_el[4];
363         };
364         uint32_t c6_region[8]; /* MPU base/size registers.  */
365         union { /* Fault address registers. */
366             struct {
367                 uint64_t _unused_far0;
368 #ifdef HOST_WORDS_BIGENDIAN
369                 uint32_t ifar_ns;
370                 uint32_t dfar_ns;
371                 uint32_t ifar_s;
372                 uint32_t dfar_s;
373 #else
374                 uint32_t dfar_ns;
375                 uint32_t ifar_ns;
376                 uint32_t dfar_s;
377                 uint32_t ifar_s;
378 #endif
379                 uint64_t _unused_far3;
380             };
381             uint64_t far_el[4];
382         };
383         uint64_t hpfar_el2;
384         uint64_t hstr_el2;
385         union { /* Translation result. */
386             struct {
387                 uint64_t _unused_par_0;
388                 uint64_t par_ns;
389                 uint64_t _unused_par_1;
390                 uint64_t par_s;
391             };
392             uint64_t par_el[4];
393         };
394 
395         uint32_t c9_insn; /* Cache lockdown registers.  */
396         uint32_t c9_data;
397         uint64_t c9_pmcr; /* performance monitor control register */
398         uint64_t c9_pmcnten; /* perf monitor counter enables */
399         uint64_t c9_pmovsr; /* perf monitor overflow status */
400         uint64_t c9_pmuserenr; /* perf monitor user enable */
401         uint64_t c9_pmselr; /* perf monitor counter selection register */
402         uint64_t c9_pminten; /* perf monitor interrupt enables */
403         union { /* Memory attribute redirection */
404             struct {
405 #ifdef HOST_WORDS_BIGENDIAN
406                 uint64_t _unused_mair_0;
407                 uint32_t mair1_ns;
408                 uint32_t mair0_ns;
409                 uint64_t _unused_mair_1;
410                 uint32_t mair1_s;
411                 uint32_t mair0_s;
412 #else
413                 uint64_t _unused_mair_0;
414                 uint32_t mair0_ns;
415                 uint32_t mair1_ns;
416                 uint64_t _unused_mair_1;
417                 uint32_t mair0_s;
418                 uint32_t mair1_s;
419 #endif
420             };
421             uint64_t mair_el[4];
422         };
423         union { /* vector base address register */
424             struct {
425                 uint64_t _unused_vbar;
426                 uint64_t vbar_ns;
427                 uint64_t hvbar;
428                 uint64_t vbar_s;
429             };
430             uint64_t vbar_el[4];
431         };
432         uint32_t mvbar; /* (monitor) vector base address register */
433         struct { /* FCSE PID. */
434             uint32_t fcseidr_ns;
435             uint32_t fcseidr_s;
436         };
437         union { /* Context ID. */
438             struct {
439                 uint64_t _unused_contextidr_0;
440                 uint64_t contextidr_ns;
441                 uint64_t _unused_contextidr_1;
442                 uint64_t contextidr_s;
443             };
444             uint64_t contextidr_el[4];
445         };
446         union { /* User RW Thread register. */
447             struct {
448                 uint64_t tpidrurw_ns;
449                 uint64_t tpidrprw_ns;
450                 uint64_t htpidr;
451                 uint64_t _tpidr_el3;
452             };
453             uint64_t tpidr_el[4];
454         };
455         /* The secure banks of these registers don't map anywhere */
456         uint64_t tpidrurw_s;
457         uint64_t tpidrprw_s;
458         uint64_t tpidruro_s;
459 
460         union { /* User RO Thread register. */
461             uint64_t tpidruro_ns;
462             uint64_t tpidrro_el[1];
463         };
464         uint64_t c14_cntfrq; /* Counter Frequency register */
465         uint64_t c14_cntkctl; /* Timer Control register */
466         uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
467         uint64_t cntvoff_el2; /* Counter Virtual Offset register */
468         ARMGenericTimer c14_timer[NUM_GTIMERS];
469         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
470         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
471         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
472         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
473         uint32_t c15_threadid; /* TI debugger thread-ID.  */
474         uint32_t c15_config_base_address; /* SCU base address.  */
475         uint32_t c15_diagnostic; /* diagnostic register */
476         uint32_t c15_power_diagnostic;
477         uint32_t c15_power_control; /* power control */
478         uint64_t dbgbvr[16]; /* breakpoint value registers */
479         uint64_t dbgbcr[16]; /* breakpoint control registers */
480         uint64_t dbgwvr[16]; /* watchpoint value registers */
481         uint64_t dbgwcr[16]; /* watchpoint control registers */
482         uint64_t mdscr_el1;
483         uint64_t oslsr_el1; /* OS Lock Status */
484         uint64_t mdcr_el2;
485         uint64_t mdcr_el3;
486         /* Stores the architectural value of the counter *the last time it was
487          * updated* by pmccntr_op_start. Accesses should always be surrounded
488          * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
489          * architecturally-correct value is being read/set.
490          */
491         uint64_t c15_ccnt;
492         /* Stores the delta between the architectural value and the underlying
493          * cycle count during normal operation. It is used to update c15_ccnt
494          * to be the correct architectural value before accesses. During
495          * accesses, c15_ccnt_delta contains the underlying count being used
496          * for the access, after which it reverts to the delta value in
497          * pmccntr_op_finish.
498          */
499         uint64_t c15_ccnt_delta;
500         uint64_t c14_pmevcntr[31];
501         uint64_t c14_pmevcntr_delta[31];
502         uint64_t c14_pmevtyper[31];
503         uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
504         uint64_t vpidr_el2; /* Virtualization Processor ID Register */
505         uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
506         uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0.  */
507         uint64_t gcr_el1;
508         uint64_t rgsr_el1;
509     } cp15;
510 
511     struct {
512         /* M profile has up to 4 stack pointers:
513          * a Main Stack Pointer and a Process Stack Pointer for each
514          * of the Secure and Non-Secure states. (If the CPU doesn't support
515          * the security extension then it has only two SPs.)
516          * In QEMU we always store the currently active SP in regs[13],
517          * and the non-active SP for the current security state in
518          * v7m.other_sp. The stack pointers for the inactive security state
519          * are stored in other_ss_msp and other_ss_psp.
520          * switch_v7m_security_state() is responsible for rearranging them
521          * when we change security state.
522          */
523         uint32_t other_sp;
524         uint32_t other_ss_msp;
525         uint32_t other_ss_psp;
526         uint32_t vecbase[M_REG_NUM_BANKS];
527         uint32_t basepri[M_REG_NUM_BANKS];
528         uint32_t control[M_REG_NUM_BANKS];
529         uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
530         uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
531         uint32_t hfsr; /* HardFault Status */
532         uint32_t dfsr; /* Debug Fault Status Register */
533         uint32_t sfsr; /* Secure Fault Status Register */
534         uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
535         uint32_t bfar; /* BusFault Address */
536         uint32_t sfar; /* Secure Fault Address Register */
537         unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
538         int exception;
539         uint32_t primask[M_REG_NUM_BANKS];
540         uint32_t faultmask[M_REG_NUM_BANKS];
541         uint32_t aircr; /* only holds r/w state if security extn implemented */
542         uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
543         uint32_t csselr[M_REG_NUM_BANKS];
544         uint32_t scr[M_REG_NUM_BANKS];
545         uint32_t msplim[M_REG_NUM_BANKS];
546         uint32_t psplim[M_REG_NUM_BANKS];
547         uint32_t fpcar[M_REG_NUM_BANKS];
548         uint32_t fpccr[M_REG_NUM_BANKS];
549         uint32_t fpdscr[M_REG_NUM_BANKS];
550         uint32_t cpacr[M_REG_NUM_BANKS];
551         uint32_t nsacr;
552         int ltpsize;
553     } v7m;
554 
555     /* Information associated with an exception about to be taken:
556      * code which raises an exception must set cs->exception_index and
557      * the relevant parts of this structure; the cpu_do_interrupt function
558      * will then set the guest-visible registers as part of the exception
559      * entry process.
560      */
561     struct {
562         uint32_t syndrome; /* AArch64 format syndrome register */
563         uint32_t fsr; /* AArch32 format fault status register info */
564         uint64_t vaddress; /* virtual addr associated with exception, if any */
565         uint32_t target_el; /* EL the exception should be targeted for */
566         /* If we implement EL2 we will also need to store information
567          * about the intermediate physical address for stage 2 faults.
568          */
569     } exception;
570 
571     /* Information associated with an SError */
572     struct {
573         uint8_t pending;
574         uint8_t has_esr;
575         uint64_t esr;
576     } serror;
577 
578     uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
579 
580     /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
581     uint32_t irq_line_state;
582 
583     /* Thumb-2 EE state.  */
584     uint32_t teecr;
585     uint32_t teehbr;
586 
587     /* VFP coprocessor state.  */
588     struct {
589         ARMVectorReg zregs[32];
590 
591 #ifdef TARGET_AARCH64
592         /* Store FFR as pregs[16] to make it easier to treat as any other.  */
593 #define FFR_PRED_NUM 16
594         ARMPredicateReg pregs[17];
595         /* Scratch space for aa64 sve predicate temporary.  */
596         ARMPredicateReg preg_tmp;
597 #endif
598 
599         /* We store these fpcsr fields separately for convenience.  */
600         uint32_t qc[4] QEMU_ALIGNED(16);
601         int vec_len;
602         int vec_stride;
603 
604         uint32_t xregs[16];
605 
606         /* Scratch space for aa32 neon expansion.  */
607         uint32_t scratch[8];
608 
609         /* There are a number of distinct float control structures:
610          *
611          *  fp_status: is the "normal" fp status.
612          *  fp_status_fp16: used for half-precision calculations
613          *  standard_fp_status : the ARM "Standard FPSCR Value"
614          *  standard_fp_status_fp16 : used for half-precision
615          *       calculations with the ARM "Standard FPSCR Value"
616          *
617          * Half-precision operations are governed by a separate
618          * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
619          * status structure to control this.
620          *
621          * The "Standard FPSCR", ie default-NaN, flush-to-zero,
622          * round-to-nearest and is used by any operations (generally
623          * Neon) which the architecture defines as controlled by the
624          * standard FPSCR value rather than the FPSCR.
625          *
626          * The "standard FPSCR but for fp16 ops" is needed because
627          * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than
628          * using a fixed value for it.
629          *
630          * To avoid having to transfer exception bits around, we simply
631          * say that the FPSCR cumulative exception flags are the logical
632          * OR of the flags in the four fp statuses. This relies on the
633          * only thing which needs to read the exception flags being
634          * an explicit FPSCR read.
635          */
636         float_status fp_status;
637         float_status fp_status_f16;
638         float_status standard_fp_status;
639         float_status standard_fp_status_f16;
640 
641         /* ZCR_EL[1-3] */
642         uint64_t zcr_el[4];
643     } vfp;
644     uint64_t exclusive_addr;
645     uint64_t exclusive_val;
646     uint64_t exclusive_high;
647 
648     /* iwMMXt coprocessor state.  */
649     struct {
650         uint64_t regs[16];
651         uint64_t val;
652 
653         uint32_t cregs[16];
654     } iwmmxt;
655 
656 #ifdef TARGET_AARCH64
657     struct {
658         ARMPACKey apia;
659         ARMPACKey apib;
660         ARMPACKey apda;
661         ARMPACKey apdb;
662         ARMPACKey apga;
663     } keys;
664 #endif
665 
666 #if defined(CONFIG_USER_ONLY)
667     /* For usermode syscall translation.  */
668     int eabi;
669 #endif
670 
671     struct CPUBreakpoint *cpu_breakpoint[16];
672     struct CPUWatchpoint *cpu_watchpoint[16];
673 
674     /* Fields up to this point are cleared by a CPU reset */
675     struct {} end_reset_fields;
676 
677     /* Fields after this point are preserved across CPU reset. */
678 
679     /* Internal CPU feature flags.  */
680     uint64_t features;
681 
682     /* PMSAv7 MPU */
683     struct {
684         uint32_t *drbar;
685         uint32_t *drsr;
686         uint32_t *dracr;
687         uint32_t rnr[M_REG_NUM_BANKS];
688     } pmsav7;
689 
690     /* PMSAv8 MPU */
691     struct {
692         /* The PMSAv8 implementation also shares some PMSAv7 config
693          * and state:
694          *  pmsav7.rnr (region number register)
695          *  pmsav7_dregion (number of configured regions)
696          */
697         uint32_t *rbar[M_REG_NUM_BANKS];
698         uint32_t *rlar[M_REG_NUM_BANKS];
699         uint32_t mair0[M_REG_NUM_BANKS];
700         uint32_t mair1[M_REG_NUM_BANKS];
701     } pmsav8;
702 
703     /* v8M SAU */
704     struct {
705         uint32_t *rbar;
706         uint32_t *rlar;
707         uint32_t rnr;
708         uint32_t ctrl;
709     } sau;
710 
711     void *nvic;
712     const struct arm_boot_info *boot_info;
713     /* Store GICv3CPUState to access from this struct */
714     void *gicv3state;
715 } CPUARMState;
716 
717 static inline void set_feature(CPUARMState *env, int feature)
718 {
719     env->features |= 1ULL << feature;
720 }
721 
722 static inline void unset_feature(CPUARMState *env, int feature)
723 {
724     env->features &= ~(1ULL << feature);
725 }
726 
727 /**
728  * ARMELChangeHookFn:
729  * type of a function which can be registered via arm_register_el_change_hook()
730  * to get callbacks when the CPU changes its exception level or mode.
731  */
732 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
733 typedef struct ARMELChangeHook ARMELChangeHook;
734 struct ARMELChangeHook {
735     ARMELChangeHookFn *hook;
736     void *opaque;
737     QLIST_ENTRY(ARMELChangeHook) node;
738 };
739 
740 /* These values map onto the return values for
741  * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
742 typedef enum ARMPSCIState {
743     PSCI_ON = 0,
744     PSCI_OFF = 1,
745     PSCI_ON_PENDING = 2
746 } ARMPSCIState;
747 
748 typedef struct ARMISARegisters ARMISARegisters;
749 
750 /**
751  * ARMCPU:
752  * @env: #CPUARMState
753  *
754  * An ARM CPU core.
755  */
756 struct ARMCPU {
757     /*< private >*/
758     CPUState parent_obj;
759     /*< public >*/
760 
761     CPUNegativeOffsetState neg;
762     CPUARMState env;
763 
764     /* Coprocessor information */
765     GHashTable *cp_regs;
766     /* For marshalling (mostly coprocessor) register state between the
767      * kernel and QEMU (for KVM) and between two QEMUs (for migration),
768      * we use these arrays.
769      */
770     /* List of register indexes managed via these arrays; (full KVM style
771      * 64 bit indexes, not CPRegInfo 32 bit indexes)
772      */
773     uint64_t *cpreg_indexes;
774     /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
775     uint64_t *cpreg_values;
776     /* Length of the indexes, values, reset_values arrays */
777     int32_t cpreg_array_len;
778     /* These are used only for migration: incoming data arrives in
779      * these fields and is sanity checked in post_load before copying
780      * to the working data structures above.
781      */
782     uint64_t *cpreg_vmstate_indexes;
783     uint64_t *cpreg_vmstate_values;
784     int32_t cpreg_vmstate_array_len;
785 
786     DynamicGDBXMLInfo dyn_sysreg_xml;
787     DynamicGDBXMLInfo dyn_svereg_xml;
788 
789     /* Timers used by the generic (architected) timer */
790     QEMUTimer *gt_timer[NUM_GTIMERS];
791     /*
792      * Timer used by the PMU. Its state is restored after migration by
793      * pmu_op_finish() - it does not need other handling during migration
794      */
795     QEMUTimer *pmu_timer;
796     /* GPIO outputs for generic timer */
797     qemu_irq gt_timer_outputs[NUM_GTIMERS];
798     /* GPIO output for GICv3 maintenance interrupt signal */
799     qemu_irq gicv3_maintenance_interrupt;
800     /* GPIO output for the PMU interrupt */
801     qemu_irq pmu_interrupt;
802 
803     /* MemoryRegion to use for secure physical accesses */
804     MemoryRegion *secure_memory;
805 
806     /* MemoryRegion to use for allocation tag accesses */
807     MemoryRegion *tag_memory;
808     MemoryRegion *secure_tag_memory;
809 
810     /* For v8M, pointer to the IDAU interface provided by board/SoC */
811     Object *idau;
812 
813     /* 'compatible' string for this CPU for Linux device trees */
814     const char *dtb_compatible;
815 
816     /* PSCI version for this CPU
817      * Bits[31:16] = Major Version
818      * Bits[15:0] = Minor Version
819      */
820     uint32_t psci_version;
821 
822     /* Current power state, access guarded by BQL */
823     ARMPSCIState power_state;
824 
825     /* CPU has virtualization extension */
826     bool has_el2;
827     /* CPU has security extension */
828     bool has_el3;
829     /* CPU has PMU (Performance Monitor Unit) */
830     bool has_pmu;
831     /* CPU has VFP */
832     bool has_vfp;
833     /* CPU has Neon */
834     bool has_neon;
835     /* CPU has M-profile DSP extension */
836     bool has_dsp;
837 
838     /* CPU has memory protection unit */
839     bool has_mpu;
840     /* PMSAv7 MPU number of supported regions */
841     uint32_t pmsav7_dregion;
842     /* v8M SAU number of supported regions */
843     uint32_t sau_sregion;
844 
845     /* PSCI conduit used to invoke PSCI methods
846      * 0 - disabled, 1 - smc, 2 - hvc
847      */
848     uint32_t psci_conduit;
849 
850     /* For v8M, initial value of the Secure VTOR */
851     uint32_t init_svtor;
852 
853     /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
854      * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
855      */
856     uint32_t kvm_target;
857 
858     /* KVM init features for this CPU */
859     uint32_t kvm_init_features[7];
860 
861     /* KVM CPU state */
862 
863     /* KVM virtual time adjustment */
864     bool kvm_adjvtime;
865     bool kvm_vtime_dirty;
866     uint64_t kvm_vtime;
867 
868     /* KVM steal time */
869     OnOffAuto kvm_steal_time;
870 
871     /* Uniprocessor system with MP extensions */
872     bool mp_is_up;
873 
874     /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init
875      * and the probe failed (so we need to report the error in realize)
876      */
877     bool host_cpu_probe_failed;
878 
879     /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
880      * register.
881      */
882     int32_t core_count;
883 
884     /* The instance init functions for implementation-specific subclasses
885      * set these fields to specify the implementation-dependent values of
886      * various constant registers and reset values of non-constant
887      * registers.
888      * Some of these might become QOM properties eventually.
889      * Field names match the official register names as defined in the
890      * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
891      * is used for reset values of non-constant registers; no reset_
892      * prefix means a constant register.
893      * Some of these registers are split out into a substructure that
894      * is shared with the translators to control the ISA.
895      *
896      * Note that if you add an ID register to the ARMISARegisters struct
897      * you need to also update the 32-bit and 64-bit versions of the
898      * kvm_arm_get_host_cpu_features() function to correctly populate the
899      * field by reading the value from the KVM vCPU.
900      */
901     struct ARMISARegisters {
902         uint32_t id_isar0;
903         uint32_t id_isar1;
904         uint32_t id_isar2;
905         uint32_t id_isar3;
906         uint32_t id_isar4;
907         uint32_t id_isar5;
908         uint32_t id_isar6;
909         uint32_t id_mmfr0;
910         uint32_t id_mmfr1;
911         uint32_t id_mmfr2;
912         uint32_t id_mmfr3;
913         uint32_t id_mmfr4;
914         uint32_t id_pfr0;
915         uint32_t id_pfr1;
916         uint32_t mvfr0;
917         uint32_t mvfr1;
918         uint32_t mvfr2;
919         uint32_t id_dfr0;
920         uint32_t dbgdidr;
921         uint64_t id_aa64isar0;
922         uint64_t id_aa64isar1;
923         uint64_t id_aa64pfr0;
924         uint64_t id_aa64pfr1;
925         uint64_t id_aa64mmfr0;
926         uint64_t id_aa64mmfr1;
927         uint64_t id_aa64mmfr2;
928         uint64_t id_aa64dfr0;
929         uint64_t id_aa64dfr1;
930     } isar;
931     uint64_t midr;
932     uint32_t revidr;
933     uint32_t reset_fpsid;
934     uint32_t ctr;
935     uint32_t reset_sctlr;
936     uint64_t pmceid0;
937     uint64_t pmceid1;
938     uint32_t id_afr0;
939     uint64_t id_aa64afr0;
940     uint64_t id_aa64afr1;
941     uint32_t clidr;
942     uint64_t mp_affinity; /* MP ID without feature bits */
943     /* The elements of this array are the CCSIDR values for each cache,
944      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
945      */
946     uint64_t ccsidr[16];
947     uint64_t reset_cbar;
948     uint32_t reset_auxcr;
949     bool reset_hivecs;
950     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
951     uint32_t dcz_blocksize;
952     uint64_t rvbar;
953 
954     /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
955     int gic_num_lrs; /* number of list registers */
956     int gic_vpribits; /* number of virtual priority bits */
957     int gic_vprebits; /* number of virtual preemption bits */
958 
959     /* Whether the cfgend input is high (i.e. this CPU should reset into
960      * big-endian mode).  This setting isn't used directly: instead it modifies
961      * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
962      * architecture version.
963      */
964     bool cfgend;
965 
966     QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
967     QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
968 
969     int32_t node_id; /* NUMA node this CPU belongs to */
970 
971     /* Used to synchronize KVM and QEMU in-kernel device levels */
972     uint8_t device_irq_level;
973 
974     /* Used to set the maximum vector length the cpu will support.  */
975     uint32_t sve_max_vq;
976 
977     /*
978      * In sve_vq_map each set bit is a supported vector length of
979      * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
980      * length in quadwords.
981      *
982      * While processing properties during initialization, corresponding
983      * sve_vq_init bits are set for bits in sve_vq_map that have been
984      * set by properties.
985      */
986     DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
987     DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
988 
989     /* Generic timer counter frequency, in Hz */
990     uint64_t gt_cntfrq_hz;
991 };
992 
993 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
994 
995 void arm_cpu_post_init(Object *obj);
996 
997 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
998 
999 #ifndef CONFIG_USER_ONLY
1000 extern const VMStateDescription vmstate_arm_cpu;
1001 #endif
1002 
1003 void arm_cpu_do_interrupt(CPUState *cpu);
1004 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1005 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
1006 
1007 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1008                                          MemTxAttrs *attrs);
1009 
1010 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1011 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1012 
1013 /*
1014  * Helpers to dynamically generates XML descriptions of the sysregs
1015  * and SVE registers. Returns the number of registers in each set.
1016  */
1017 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
1018 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
1019 
1020 /* Returns the dynamically generated XML for the gdb stub.
1021  * Returns a pointer to the XML contents for the specified XML file or NULL
1022  * if the XML name doesn't match the predefined one.
1023  */
1024 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1025 
1026 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1027                              int cpuid, void *opaque);
1028 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1029                              int cpuid, void *opaque);
1030 
1031 #ifdef TARGET_AARCH64
1032 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1033 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1034 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1035 void aarch64_sve_change_el(CPUARMState *env, int old_el,
1036                            int new_el, bool el0_a64);
1037 void aarch64_add_sve_properties(Object *obj);
1038 
1039 /*
1040  * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1041  * The byte at offset i from the start of the in-memory representation contains
1042  * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
1043  * lowest offsets are stored in the lowest memory addresses, then that nearly
1044  * matches QEMU's representation, which is to use an array of host-endian
1045  * uint64_t's, where the lower offsets are at the lower indices. To complete
1046  * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1047  */
1048 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1049 {
1050 #ifdef HOST_WORDS_BIGENDIAN
1051     int i;
1052 
1053     for (i = 0; i < nr; ++i) {
1054         dst[i] = bswap64(src[i]);
1055     }
1056 
1057     return dst;
1058 #else
1059     return src;
1060 #endif
1061 }
1062 
1063 #else
1064 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1065 static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1066                                          int n, bool a)
1067 { }
1068 static inline void aarch64_add_sve_properties(Object *obj) { }
1069 #endif
1070 
1071 #if !defined(CONFIG_TCG)
1072 static inline target_ulong do_arm_semihosting(CPUARMState *env)
1073 {
1074     g_assert_not_reached();
1075 }
1076 #else
1077 target_ulong do_arm_semihosting(CPUARMState *env);
1078 #endif
1079 void aarch64_sync_32_to_64(CPUARMState *env);
1080 void aarch64_sync_64_to_32(CPUARMState *env);
1081 
1082 int fp_exception_el(CPUARMState *env, int cur_el);
1083 int sve_exception_el(CPUARMState *env, int cur_el);
1084 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
1085 
1086 static inline bool is_a64(CPUARMState *env)
1087 {
1088     return env->aarch64;
1089 }
1090 
1091 /* you can call this signal handler from your SIGBUS and SIGSEGV
1092    signal handlers to inform the virtual CPU of exceptions. non zero
1093    is returned if the signal was handled by the virtual CPU.  */
1094 int cpu_arm_signal_handler(int host_signum, void *pinfo,
1095                            void *puc);
1096 
1097 /**
1098  * pmu_op_start/finish
1099  * @env: CPUARMState
1100  *
1101  * Convert all PMU counters between their delta form (the typical mode when
1102  * they are enabled) and the guest-visible values. These two calls must
1103  * surround any action which might affect the counters.
1104  */
1105 void pmu_op_start(CPUARMState *env);
1106 void pmu_op_finish(CPUARMState *env);
1107 
1108 /*
1109  * Called when a PMU counter is due to overflow
1110  */
1111 void arm_pmu_timer_cb(void *opaque);
1112 
1113 /**
1114  * Functions to register as EL change hooks for PMU mode filtering
1115  */
1116 void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1117 void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1118 
1119 /*
1120  * pmu_init
1121  * @cpu: ARMCPU
1122  *
1123  * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state
1124  * for the current configuration
1125  */
1126 void pmu_init(ARMCPU *cpu);
1127 
1128 /* SCTLR bit meanings. Several bits have been reused in newer
1129  * versions of the architecture; in that case we define constants
1130  * for both old and new bit meanings. Code which tests against those
1131  * bits should probably check or otherwise arrange that the CPU
1132  * is the architectural version it expects.
1133  */
1134 #define SCTLR_M       (1U << 0)
1135 #define SCTLR_A       (1U << 1)
1136 #define SCTLR_C       (1U << 2)
1137 #define SCTLR_W       (1U << 3) /* up to v6; RAO in v7 */
1138 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1139 #define SCTLR_SA      (1U << 3) /* AArch64 only */
1140 #define SCTLR_P       (1U << 4) /* up to v5; RAO in v6 and v7 */
1141 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1142 #define SCTLR_SA0     (1U << 4) /* v8 onward, AArch64 only */
1143 #define SCTLR_D       (1U << 5) /* up to v5; RAO in v6 */
1144 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1145 #define SCTLR_L       (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1146 #define SCTLR_nAA     (1U << 6) /* when v8.4-LSE is implemented */
1147 #define SCTLR_B       (1U << 7) /* up to v6; RAZ in v7 */
1148 #define SCTLR_ITD     (1U << 7) /* v8 onward */
1149 #define SCTLR_S       (1U << 8) /* up to v6; RAZ in v7 */
1150 #define SCTLR_SED     (1U << 8) /* v8 onward */
1151 #define SCTLR_R       (1U << 9) /* up to v6; RAZ in v7 */
1152 #define SCTLR_UMA     (1U << 9) /* v8 onward, AArch64 only */
1153 #define SCTLR_F       (1U << 10) /* up to v6 */
1154 #define SCTLR_SW      (1U << 10) /* v7 */
1155 #define SCTLR_EnRCTX  (1U << 10) /* in v8.0-PredInv */
1156 #define SCTLR_Z       (1U << 11) /* in v7, RES1 in v8 */
1157 #define SCTLR_EOS     (1U << 11) /* v8.5-ExS */
1158 #define SCTLR_I       (1U << 12)
1159 #define SCTLR_V       (1U << 13) /* AArch32 only */
1160 #define SCTLR_EnDB    (1U << 13) /* v8.3, AArch64 only */
1161 #define SCTLR_RR      (1U << 14) /* up to v7 */
1162 #define SCTLR_DZE     (1U << 14) /* v8 onward, AArch64 only */
1163 #define SCTLR_L4      (1U << 15) /* up to v6; RAZ in v7 */
1164 #define SCTLR_UCT     (1U << 15) /* v8 onward, AArch64 only */
1165 #define SCTLR_DT      (1U << 16) /* up to ??, RAO in v6 and v7 */
1166 #define SCTLR_nTWI    (1U << 16) /* v8 onward */
1167 #define SCTLR_HA      (1U << 17) /* up to v7, RES0 in v8 */
1168 #define SCTLR_BR      (1U << 17) /* PMSA only */
1169 #define SCTLR_IT      (1U << 18) /* up to ??, RAO in v6 and v7 */
1170 #define SCTLR_nTWE    (1U << 18) /* v8 onward */
1171 #define SCTLR_WXN     (1U << 19)
1172 #define SCTLR_ST      (1U << 20) /* up to ??, RAZ in v6 */
1173 #define SCTLR_UWXN    (1U << 20) /* v7 onward, AArch32 only */
1174 #define SCTLR_FI      (1U << 21) /* up to v7, v8 RES0 */
1175 #define SCTLR_IESB    (1U << 21) /* v8.2-IESB, AArch64 only */
1176 #define SCTLR_U       (1U << 22) /* up to v6, RAO in v7 */
1177 #define SCTLR_EIS     (1U << 22) /* v8.5-ExS */
1178 #define SCTLR_XP      (1U << 23) /* up to v6; v7 onward RAO */
1179 #define SCTLR_SPAN    (1U << 23) /* v8.1-PAN */
1180 #define SCTLR_VE      (1U << 24) /* up to v7 */
1181 #define SCTLR_E0E     (1U << 24) /* v8 onward, AArch64 only */
1182 #define SCTLR_EE      (1U << 25)
1183 #define SCTLR_L2      (1U << 26) /* up to v6, RAZ in v7 */
1184 #define SCTLR_UCI     (1U << 26) /* v8 onward, AArch64 only */
1185 #define SCTLR_NMFI    (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1186 #define SCTLR_EnDA    (1U << 27) /* v8.3, AArch64 only */
1187 #define SCTLR_TRE     (1U << 28) /* AArch32 only */
1188 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1189 #define SCTLR_AFE     (1U << 29) /* AArch32 only */
1190 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1191 #define SCTLR_TE      (1U << 30) /* AArch32 only */
1192 #define SCTLR_EnIB    (1U << 30) /* v8.3, AArch64 only */
1193 #define SCTLR_EnIA    (1U << 31) /* v8.3, AArch64 only */
1194 #define SCTLR_BT0     (1ULL << 35) /* v8.5-BTI */
1195 #define SCTLR_BT1     (1ULL << 36) /* v8.5-BTI */
1196 #define SCTLR_ITFSB   (1ULL << 37) /* v8.5-MemTag */
1197 #define SCTLR_TCF0    (3ULL << 38) /* v8.5-MemTag */
1198 #define SCTLR_TCF     (3ULL << 40) /* v8.5-MemTag */
1199 #define SCTLR_ATA0    (1ULL << 42) /* v8.5-MemTag */
1200 #define SCTLR_ATA     (1ULL << 43) /* v8.5-MemTag */
1201 #define SCTLR_DSSBS   (1ULL << 44) /* v8.5 */
1202 
1203 #define CPTR_TCPAC    (1U << 31)
1204 #define CPTR_TTA      (1U << 20)
1205 #define CPTR_TFP      (1U << 10)
1206 #define CPTR_TZ       (1U << 8)   /* CPTR_EL2 */
1207 #define CPTR_EZ       (1U << 8)   /* CPTR_EL3 */
1208 
1209 #define MDCR_EPMAD    (1U << 21)
1210 #define MDCR_EDAD     (1U << 20)
1211 #define MDCR_SPME     (1U << 17)  /* MDCR_EL3 */
1212 #define MDCR_HPMD     (1U << 17)  /* MDCR_EL2 */
1213 #define MDCR_SDD      (1U << 16)
1214 #define MDCR_SPD      (3U << 14)
1215 #define MDCR_TDRA     (1U << 11)
1216 #define MDCR_TDOSA    (1U << 10)
1217 #define MDCR_TDA      (1U << 9)
1218 #define MDCR_TDE      (1U << 8)
1219 #define MDCR_HPME     (1U << 7)
1220 #define MDCR_TPM      (1U << 6)
1221 #define MDCR_TPMCR    (1U << 5)
1222 #define MDCR_HPMN     (0x1fU)
1223 
1224 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
1225 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1226 
1227 #define CPSR_M (0x1fU)
1228 #define CPSR_T (1U << 5)
1229 #define CPSR_F (1U << 6)
1230 #define CPSR_I (1U << 7)
1231 #define CPSR_A (1U << 8)
1232 #define CPSR_E (1U << 9)
1233 #define CPSR_IT_2_7 (0xfc00U)
1234 #define CPSR_GE (0xfU << 16)
1235 #define CPSR_IL (1U << 20)
1236 #define CPSR_PAN (1U << 22)
1237 #define CPSR_J (1U << 24)
1238 #define CPSR_IT_0_1 (3U << 25)
1239 #define CPSR_Q (1U << 27)
1240 #define CPSR_V (1U << 28)
1241 #define CPSR_C (1U << 29)
1242 #define CPSR_Z (1U << 30)
1243 #define CPSR_N (1U << 31)
1244 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1245 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1246 
1247 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1248 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1249     | CPSR_NZCV)
1250 /* Bits writable in user mode.  */
1251 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1252 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
1253 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1254 
1255 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1256 #define XPSR_EXCP 0x1ffU
1257 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1258 #define XPSR_IT_2_7 CPSR_IT_2_7
1259 #define XPSR_GE CPSR_GE
1260 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1261 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1262 #define XPSR_IT_0_1 CPSR_IT_0_1
1263 #define XPSR_Q CPSR_Q
1264 #define XPSR_V CPSR_V
1265 #define XPSR_C CPSR_C
1266 #define XPSR_Z CPSR_Z
1267 #define XPSR_N CPSR_N
1268 #define XPSR_NZCV CPSR_NZCV
1269 #define XPSR_IT CPSR_IT
1270 
1271 #define TTBCR_N      (7U << 0) /* TTBCR.EAE==0 */
1272 #define TTBCR_T0SZ   (7U << 0) /* TTBCR.EAE==1 */
1273 #define TTBCR_PD0    (1U << 4)
1274 #define TTBCR_PD1    (1U << 5)
1275 #define TTBCR_EPD0   (1U << 7)
1276 #define TTBCR_IRGN0  (3U << 8)
1277 #define TTBCR_ORGN0  (3U << 10)
1278 #define TTBCR_SH0    (3U << 12)
1279 #define TTBCR_T1SZ   (3U << 16)
1280 #define TTBCR_A1     (1U << 22)
1281 #define TTBCR_EPD1   (1U << 23)
1282 #define TTBCR_IRGN1  (3U << 24)
1283 #define TTBCR_ORGN1  (3U << 26)
1284 #define TTBCR_SH1    (1U << 28)
1285 #define TTBCR_EAE    (1U << 31)
1286 
1287 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1288  * Only these are valid when in AArch64 mode; in
1289  * AArch32 mode SPSRs are basically CPSR-format.
1290  */
1291 #define PSTATE_SP (1U)
1292 #define PSTATE_M (0xFU)
1293 #define PSTATE_nRW (1U << 4)
1294 #define PSTATE_F (1U << 6)
1295 #define PSTATE_I (1U << 7)
1296 #define PSTATE_A (1U << 8)
1297 #define PSTATE_D (1U << 9)
1298 #define PSTATE_BTYPE (3U << 10)
1299 #define PSTATE_IL (1U << 20)
1300 #define PSTATE_SS (1U << 21)
1301 #define PSTATE_PAN (1U << 22)
1302 #define PSTATE_UAO (1U << 23)
1303 #define PSTATE_TCO (1U << 25)
1304 #define PSTATE_V (1U << 28)
1305 #define PSTATE_C (1U << 29)
1306 #define PSTATE_Z (1U << 30)
1307 #define PSTATE_N (1U << 31)
1308 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1309 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1310 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1311 /* Mode values for AArch64 */
1312 #define PSTATE_MODE_EL3h 13
1313 #define PSTATE_MODE_EL3t 12
1314 #define PSTATE_MODE_EL2h 9
1315 #define PSTATE_MODE_EL2t 8
1316 #define PSTATE_MODE_EL1h 5
1317 #define PSTATE_MODE_EL1t 4
1318 #define PSTATE_MODE_EL0t 0
1319 
1320 /* Write a new value to v7m.exception, thus transitioning into or out
1321  * of Handler mode; this may result in a change of active stack pointer.
1322  */
1323 void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1324 
1325 /* Map EL and handler into a PSTATE_MODE.  */
1326 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1327 {
1328     return (el << 2) | handler;
1329 }
1330 
1331 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1332  * interprocessing, so we don't attempt to sync with the cpsr state used by
1333  * the 32 bit decoder.
1334  */
1335 static inline uint32_t pstate_read(CPUARMState *env)
1336 {
1337     int ZF;
1338 
1339     ZF = (env->ZF == 0);
1340     return (env->NF & 0x80000000) | (ZF << 30)
1341         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1342         | env->pstate | env->daif | (env->btype << 10);
1343 }
1344 
1345 static inline void pstate_write(CPUARMState *env, uint32_t val)
1346 {
1347     env->ZF = (~val) & PSTATE_Z;
1348     env->NF = val;
1349     env->CF = (val >> 29) & 1;
1350     env->VF = (val << 3) & 0x80000000;
1351     env->daif = val & PSTATE_DAIF;
1352     env->btype = (val >> 10) & 3;
1353     env->pstate = val & ~CACHED_PSTATE_BITS;
1354 }
1355 
1356 /* Return the current CPSR value.  */
1357 uint32_t cpsr_read(CPUARMState *env);
1358 
1359 typedef enum CPSRWriteType {
1360     CPSRWriteByInstr = 0,         /* from guest MSR or CPS */
1361     CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1362     CPSRWriteRaw = 2,             /* trust values, do not switch reg banks */
1363     CPSRWriteByGDBStub = 3,       /* from the GDB stub */
1364 } CPSRWriteType;
1365 
1366 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.*/
1367 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1368                 CPSRWriteType write_type);
1369 
1370 /* Return the current xPSR value.  */
1371 static inline uint32_t xpsr_read(CPUARMState *env)
1372 {
1373     int ZF;
1374     ZF = (env->ZF == 0);
1375     return (env->NF & 0x80000000) | (ZF << 30)
1376         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1377         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1378         | ((env->condexec_bits & 0xfc) << 8)
1379         | (env->GE << 16)
1380         | env->v7m.exception;
1381 }
1382 
1383 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
1384 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1385 {
1386     if (mask & XPSR_NZCV) {
1387         env->ZF = (~val) & XPSR_Z;
1388         env->NF = val;
1389         env->CF = (val >> 29) & 1;
1390         env->VF = (val << 3) & 0x80000000;
1391     }
1392     if (mask & XPSR_Q) {
1393         env->QF = ((val & XPSR_Q) != 0);
1394     }
1395     if (mask & XPSR_GE) {
1396         env->GE = (val & XPSR_GE) >> 16;
1397     }
1398 #ifndef CONFIG_USER_ONLY
1399     if (mask & XPSR_T) {
1400         env->thumb = ((val & XPSR_T) != 0);
1401     }
1402     if (mask & XPSR_IT_0_1) {
1403         env->condexec_bits &= ~3;
1404         env->condexec_bits |= (val >> 25) & 3;
1405     }
1406     if (mask & XPSR_IT_2_7) {
1407         env->condexec_bits &= 3;
1408         env->condexec_bits |= (val >> 8) & 0xfc;
1409     }
1410     if (mask & XPSR_EXCP) {
1411         /* Note that this only happens on exception exit */
1412         write_v7m_exception(env, val & XPSR_EXCP);
1413     }
1414 #endif
1415 }
1416 
1417 #define HCR_VM        (1ULL << 0)
1418 #define HCR_SWIO      (1ULL << 1)
1419 #define HCR_PTW       (1ULL << 2)
1420 #define HCR_FMO       (1ULL << 3)
1421 #define HCR_IMO       (1ULL << 4)
1422 #define HCR_AMO       (1ULL << 5)
1423 #define HCR_VF        (1ULL << 6)
1424 #define HCR_VI        (1ULL << 7)
1425 #define HCR_VSE       (1ULL << 8)
1426 #define HCR_FB        (1ULL << 9)
1427 #define HCR_BSU_MASK  (3ULL << 10)
1428 #define HCR_DC        (1ULL << 12)
1429 #define HCR_TWI       (1ULL << 13)
1430 #define HCR_TWE       (1ULL << 14)
1431 #define HCR_TID0      (1ULL << 15)
1432 #define HCR_TID1      (1ULL << 16)
1433 #define HCR_TID2      (1ULL << 17)
1434 #define HCR_TID3      (1ULL << 18)
1435 #define HCR_TSC       (1ULL << 19)
1436 #define HCR_TIDCP     (1ULL << 20)
1437 #define HCR_TACR      (1ULL << 21)
1438 #define HCR_TSW       (1ULL << 22)
1439 #define HCR_TPCP      (1ULL << 23)
1440 #define HCR_TPU       (1ULL << 24)
1441 #define HCR_TTLB      (1ULL << 25)
1442 #define HCR_TVM       (1ULL << 26)
1443 #define HCR_TGE       (1ULL << 27)
1444 #define HCR_TDZ       (1ULL << 28)
1445 #define HCR_HCD       (1ULL << 29)
1446 #define HCR_TRVM      (1ULL << 30)
1447 #define HCR_RW        (1ULL << 31)
1448 #define HCR_CD        (1ULL << 32)
1449 #define HCR_ID        (1ULL << 33)
1450 #define HCR_E2H       (1ULL << 34)
1451 #define HCR_TLOR      (1ULL << 35)
1452 #define HCR_TERR      (1ULL << 36)
1453 #define HCR_TEA       (1ULL << 37)
1454 #define HCR_MIOCNCE   (1ULL << 38)
1455 /* RES0 bit 39 */
1456 #define HCR_APK       (1ULL << 40)
1457 #define HCR_API       (1ULL << 41)
1458 #define HCR_NV        (1ULL << 42)
1459 #define HCR_NV1       (1ULL << 43)
1460 #define HCR_AT        (1ULL << 44)
1461 #define HCR_NV2       (1ULL << 45)
1462 #define HCR_FWB       (1ULL << 46)
1463 #define HCR_FIEN      (1ULL << 47)
1464 /* RES0 bit 48 */
1465 #define HCR_TID4      (1ULL << 49)
1466 #define HCR_TICAB     (1ULL << 50)
1467 #define HCR_AMVOFFEN  (1ULL << 51)
1468 #define HCR_TOCU      (1ULL << 52)
1469 #define HCR_ENSCXT    (1ULL << 53)
1470 #define HCR_TTLBIS    (1ULL << 54)
1471 #define HCR_TTLBOS    (1ULL << 55)
1472 #define HCR_ATA       (1ULL << 56)
1473 #define HCR_DCT       (1ULL << 57)
1474 #define HCR_TID5      (1ULL << 58)
1475 #define HCR_TWEDEN    (1ULL << 59)
1476 #define HCR_TWEDEL    MAKE_64BIT_MASK(60, 4)
1477 
1478 #define SCR_NS                (1U << 0)
1479 #define SCR_IRQ               (1U << 1)
1480 #define SCR_FIQ               (1U << 2)
1481 #define SCR_EA                (1U << 3)
1482 #define SCR_FW                (1U << 4)
1483 #define SCR_AW                (1U << 5)
1484 #define SCR_NET               (1U << 6)
1485 #define SCR_SMD               (1U << 7)
1486 #define SCR_HCE               (1U << 8)
1487 #define SCR_SIF               (1U << 9)
1488 #define SCR_RW                (1U << 10)
1489 #define SCR_ST                (1U << 11)
1490 #define SCR_TWI               (1U << 12)
1491 #define SCR_TWE               (1U << 13)
1492 #define SCR_TLOR              (1U << 14)
1493 #define SCR_TERR              (1U << 15)
1494 #define SCR_APK               (1U << 16)
1495 #define SCR_API               (1U << 17)
1496 #define SCR_EEL2              (1U << 18)
1497 #define SCR_EASE              (1U << 19)
1498 #define SCR_NMEA              (1U << 20)
1499 #define SCR_FIEN              (1U << 21)
1500 #define SCR_ENSCXT            (1U << 25)
1501 #define SCR_ATA               (1U << 26)
1502 
1503 /* Return the current FPSCR value.  */
1504 uint32_t vfp_get_fpscr(CPUARMState *env);
1505 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1506 
1507 /* FPCR, Floating Point Control Register
1508  * FPSR, Floating Poiht Status Register
1509  *
1510  * For A64 the FPSCR is split into two logically distinct registers,
1511  * FPCR and FPSR. However since they still use non-overlapping bits
1512  * we store the underlying state in fpscr and just mask on read/write.
1513  */
1514 #define FPSR_MASK 0xf800009f
1515 #define FPCR_MASK 0x07ff9f00
1516 
1517 #define FPCR_IOE    (1 << 8)    /* Invalid Operation exception trap enable */
1518 #define FPCR_DZE    (1 << 9)    /* Divide by Zero exception trap enable */
1519 #define FPCR_OFE    (1 << 10)   /* Overflow exception trap enable */
1520 #define FPCR_UFE    (1 << 11)   /* Underflow exception trap enable */
1521 #define FPCR_IXE    (1 << 12)   /* Inexact exception trap enable */
1522 #define FPCR_IDE    (1 << 15)   /* Input Denormal exception trap enable */
1523 #define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
1524 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
1525 #define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
1526 #define FPCR_DN     (1 << 25)   /* Default NaN enable bit */
1527 #define FPCR_AHP    (1 << 26)   /* Alternative half-precision */
1528 #define FPCR_QC     (1 << 27)   /* Cumulative saturation bit */
1529 #define FPCR_V      (1 << 28)   /* FP overflow flag */
1530 #define FPCR_C      (1 << 29)   /* FP carry flag */
1531 #define FPCR_Z      (1 << 30)   /* FP zero flag */
1532 #define FPCR_N      (1 << 31)   /* FP negative flag */
1533 
1534 #define FPCR_LTPSIZE_SHIFT 16   /* LTPSIZE, M-profile only */
1535 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
1536 
1537 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
1538 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
1539 
1540 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1541 {
1542     return vfp_get_fpscr(env) & FPSR_MASK;
1543 }
1544 
1545 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1546 {
1547     uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1548     vfp_set_fpscr(env, new_fpscr);
1549 }
1550 
1551 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1552 {
1553     return vfp_get_fpscr(env) & FPCR_MASK;
1554 }
1555 
1556 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1557 {
1558     uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1559     vfp_set_fpscr(env, new_fpscr);
1560 }
1561 
1562 enum arm_cpu_mode {
1563   ARM_CPU_MODE_USR = 0x10,
1564   ARM_CPU_MODE_FIQ = 0x11,
1565   ARM_CPU_MODE_IRQ = 0x12,
1566   ARM_CPU_MODE_SVC = 0x13,
1567   ARM_CPU_MODE_MON = 0x16,
1568   ARM_CPU_MODE_ABT = 0x17,
1569   ARM_CPU_MODE_HYP = 0x1a,
1570   ARM_CPU_MODE_UND = 0x1b,
1571   ARM_CPU_MODE_SYS = 0x1f
1572 };
1573 
1574 /* VFP system registers.  */
1575 #define ARM_VFP_FPSID   0
1576 #define ARM_VFP_FPSCR   1
1577 #define ARM_VFP_MVFR2   5
1578 #define ARM_VFP_MVFR1   6
1579 #define ARM_VFP_MVFR0   7
1580 #define ARM_VFP_FPEXC   8
1581 #define ARM_VFP_FPINST  9
1582 #define ARM_VFP_FPINST2 10
1583 /* These ones are M-profile only */
1584 #define ARM_VFP_FPSCR_NZCVQC 2
1585 #define ARM_VFP_VPR 12
1586 #define ARM_VFP_P0 13
1587 #define ARM_VFP_FPCXT_NS 14
1588 #define ARM_VFP_FPCXT_S 15
1589 
1590 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
1591 #define QEMU_VFP_FPSCR_NZCV 0xffff
1592 
1593 /* iwMMXt coprocessor control registers.  */
1594 #define ARM_IWMMXT_wCID  0
1595 #define ARM_IWMMXT_wCon  1
1596 #define ARM_IWMMXT_wCSSF 2
1597 #define ARM_IWMMXT_wCASF 3
1598 #define ARM_IWMMXT_wCGR0 8
1599 #define ARM_IWMMXT_wCGR1 9
1600 #define ARM_IWMMXT_wCGR2 10
1601 #define ARM_IWMMXT_wCGR3 11
1602 
1603 /* V7M CCR bits */
1604 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1605 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1606 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1607 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1608 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1609 FIELD(V7M_CCR, STKALIGN, 9, 1)
1610 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1611 FIELD(V7M_CCR, DC, 16, 1)
1612 FIELD(V7M_CCR, IC, 17, 1)
1613 FIELD(V7M_CCR, BP, 18, 1)
1614 FIELD(V7M_CCR, LOB, 19, 1)
1615 FIELD(V7M_CCR, TRD, 20, 1)
1616 
1617 /* V7M SCR bits */
1618 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1619 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1620 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1621 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1622 
1623 /* V7M AIRCR bits */
1624 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1625 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1626 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1627 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1628 FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1629 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1630 FIELD(V7M_AIRCR, PRIS, 14, 1)
1631 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1632 FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1633 
1634 /* V7M CFSR bits for MMFSR */
1635 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1636 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1637 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1638 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1639 FIELD(V7M_CFSR, MLSPERR, 5, 1)
1640 FIELD(V7M_CFSR, MMARVALID, 7, 1)
1641 
1642 /* V7M CFSR bits for BFSR */
1643 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1644 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1645 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1646 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1647 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1648 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1649 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1650 
1651 /* V7M CFSR bits for UFSR */
1652 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1653 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1654 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1655 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1656 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1657 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1658 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1659 
1660 /* V7M CFSR bit masks covering all of the subregister bits */
1661 FIELD(V7M_CFSR, MMFSR, 0, 8)
1662 FIELD(V7M_CFSR, BFSR, 8, 8)
1663 FIELD(V7M_CFSR, UFSR, 16, 16)
1664 
1665 /* V7M HFSR bits */
1666 FIELD(V7M_HFSR, VECTTBL, 1, 1)
1667 FIELD(V7M_HFSR, FORCED, 30, 1)
1668 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1669 
1670 /* V7M DFSR bits */
1671 FIELD(V7M_DFSR, HALTED, 0, 1)
1672 FIELD(V7M_DFSR, BKPT, 1, 1)
1673 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1674 FIELD(V7M_DFSR, VCATCH, 3, 1)
1675 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1676 
1677 /* V7M SFSR bits */
1678 FIELD(V7M_SFSR, INVEP, 0, 1)
1679 FIELD(V7M_SFSR, INVIS, 1, 1)
1680 FIELD(V7M_SFSR, INVER, 2, 1)
1681 FIELD(V7M_SFSR, AUVIOL, 3, 1)
1682 FIELD(V7M_SFSR, INVTRAN, 4, 1)
1683 FIELD(V7M_SFSR, LSPERR, 5, 1)
1684 FIELD(V7M_SFSR, SFARVALID, 6, 1)
1685 FIELD(V7M_SFSR, LSERR, 7, 1)
1686 
1687 /* v7M MPU_CTRL bits */
1688 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1689 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1690 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1691 
1692 /* v7M CLIDR bits */
1693 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1694 FIELD(V7M_CLIDR, LOUIS, 21, 3)
1695 FIELD(V7M_CLIDR, LOC, 24, 3)
1696 FIELD(V7M_CLIDR, LOUU, 27, 3)
1697 FIELD(V7M_CLIDR, ICB, 30, 2)
1698 
1699 FIELD(V7M_CSSELR, IND, 0, 1)
1700 FIELD(V7M_CSSELR, LEVEL, 1, 3)
1701 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1702  * define a mask for this and check that it doesn't permit running off
1703  * the end of the array.
1704  */
1705 FIELD(V7M_CSSELR, INDEX, 0, 4)
1706 
1707 /* v7M FPCCR bits */
1708 FIELD(V7M_FPCCR, LSPACT, 0, 1)
1709 FIELD(V7M_FPCCR, USER, 1, 1)
1710 FIELD(V7M_FPCCR, S, 2, 1)
1711 FIELD(V7M_FPCCR, THREAD, 3, 1)
1712 FIELD(V7M_FPCCR, HFRDY, 4, 1)
1713 FIELD(V7M_FPCCR, MMRDY, 5, 1)
1714 FIELD(V7M_FPCCR, BFRDY, 6, 1)
1715 FIELD(V7M_FPCCR, SFRDY, 7, 1)
1716 FIELD(V7M_FPCCR, MONRDY, 8, 1)
1717 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1718 FIELD(V7M_FPCCR, UFRDY, 10, 1)
1719 FIELD(V7M_FPCCR, RES0, 11, 15)
1720 FIELD(V7M_FPCCR, TS, 26, 1)
1721 FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1722 FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1723 FIELD(V7M_FPCCR, LSPENS, 29, 1)
1724 FIELD(V7M_FPCCR, LSPEN, 30, 1)
1725 FIELD(V7M_FPCCR, ASPEN, 31, 1)
1726 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
1727 #define R_V7M_FPCCR_BANKED_MASK                 \
1728     (R_V7M_FPCCR_LSPACT_MASK |                  \
1729      R_V7M_FPCCR_USER_MASK |                    \
1730      R_V7M_FPCCR_THREAD_MASK |                  \
1731      R_V7M_FPCCR_MMRDY_MASK |                   \
1732      R_V7M_FPCCR_SPLIMVIOL_MASK |               \
1733      R_V7M_FPCCR_UFRDY_MASK |                   \
1734      R_V7M_FPCCR_ASPEN_MASK)
1735 
1736 /*
1737  * System register ID fields.
1738  */
1739 FIELD(MIDR_EL1, REVISION, 0, 4)
1740 FIELD(MIDR_EL1, PARTNUM, 4, 12)
1741 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
1742 FIELD(MIDR_EL1, VARIANT, 20, 4)
1743 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
1744 
1745 FIELD(ID_ISAR0, SWAP, 0, 4)
1746 FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1747 FIELD(ID_ISAR0, BITFIELD, 8, 4)
1748 FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1749 FIELD(ID_ISAR0, COPROC, 16, 4)
1750 FIELD(ID_ISAR0, DEBUG, 20, 4)
1751 FIELD(ID_ISAR0, DIVIDE, 24, 4)
1752 
1753 FIELD(ID_ISAR1, ENDIAN, 0, 4)
1754 FIELD(ID_ISAR1, EXCEPT, 4, 4)
1755 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1756 FIELD(ID_ISAR1, EXTEND, 12, 4)
1757 FIELD(ID_ISAR1, IFTHEN, 16, 4)
1758 FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1759 FIELD(ID_ISAR1, INTERWORK, 24, 4)
1760 FIELD(ID_ISAR1, JAZELLE, 28, 4)
1761 
1762 FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1763 FIELD(ID_ISAR2, MEMHINT, 4, 4)
1764 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1765 FIELD(ID_ISAR2, MULT, 12, 4)
1766 FIELD(ID_ISAR2, MULTS, 16, 4)
1767 FIELD(ID_ISAR2, MULTU, 20, 4)
1768 FIELD(ID_ISAR2, PSR_AR, 24, 4)
1769 FIELD(ID_ISAR2, REVERSAL, 28, 4)
1770 
1771 FIELD(ID_ISAR3, SATURATE, 0, 4)
1772 FIELD(ID_ISAR3, SIMD, 4, 4)
1773 FIELD(ID_ISAR3, SVC, 8, 4)
1774 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
1775 FIELD(ID_ISAR3, TABBRANCH, 16, 4)
1776 FIELD(ID_ISAR3, T32COPY, 20, 4)
1777 FIELD(ID_ISAR3, TRUENOP, 24, 4)
1778 FIELD(ID_ISAR3, T32EE, 28, 4)
1779 
1780 FIELD(ID_ISAR4, UNPRIV, 0, 4)
1781 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
1782 FIELD(ID_ISAR4, WRITEBACK, 8, 4)
1783 FIELD(ID_ISAR4, SMC, 12, 4)
1784 FIELD(ID_ISAR4, BARRIER, 16, 4)
1785 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
1786 FIELD(ID_ISAR4, PSR_M, 24, 4)
1787 FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
1788 
1789 FIELD(ID_ISAR5, SEVL, 0, 4)
1790 FIELD(ID_ISAR5, AES, 4, 4)
1791 FIELD(ID_ISAR5, SHA1, 8, 4)
1792 FIELD(ID_ISAR5, SHA2, 12, 4)
1793 FIELD(ID_ISAR5, CRC32, 16, 4)
1794 FIELD(ID_ISAR5, RDM, 24, 4)
1795 FIELD(ID_ISAR5, VCMA, 28, 4)
1796 
1797 FIELD(ID_ISAR6, JSCVT, 0, 4)
1798 FIELD(ID_ISAR6, DP, 4, 4)
1799 FIELD(ID_ISAR6, FHM, 8, 4)
1800 FIELD(ID_ISAR6, SB, 12, 4)
1801 FIELD(ID_ISAR6, SPECRES, 16, 4)
1802 
1803 FIELD(ID_MMFR0, VMSA, 0, 4)
1804 FIELD(ID_MMFR0, PMSA, 4, 4)
1805 FIELD(ID_MMFR0, OUTERSHR, 8, 4)
1806 FIELD(ID_MMFR0, SHARELVL, 12, 4)
1807 FIELD(ID_MMFR0, TCM, 16, 4)
1808 FIELD(ID_MMFR0, AUXREG, 20, 4)
1809 FIELD(ID_MMFR0, FCSE, 24, 4)
1810 FIELD(ID_MMFR0, INNERSHR, 28, 4)
1811 
1812 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
1813 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
1814 FIELD(ID_MMFR3, BPMAINT, 8, 4)
1815 FIELD(ID_MMFR3, MAINTBCST, 12, 4)
1816 FIELD(ID_MMFR3, PAN, 16, 4)
1817 FIELD(ID_MMFR3, COHWALK, 20, 4)
1818 FIELD(ID_MMFR3, CMEMSZ, 24, 4)
1819 FIELD(ID_MMFR3, SUPERSEC, 28, 4)
1820 
1821 FIELD(ID_MMFR4, SPECSEI, 0, 4)
1822 FIELD(ID_MMFR4, AC2, 4, 4)
1823 FIELD(ID_MMFR4, XNX, 8, 4)
1824 FIELD(ID_MMFR4, CNP, 12, 4)
1825 FIELD(ID_MMFR4, HPDS, 16, 4)
1826 FIELD(ID_MMFR4, LSM, 20, 4)
1827 FIELD(ID_MMFR4, CCIDX, 24, 4)
1828 FIELD(ID_MMFR4, EVT, 28, 4)
1829 
1830 FIELD(ID_PFR0, STATE0, 0, 4)
1831 FIELD(ID_PFR0, STATE1, 4, 4)
1832 FIELD(ID_PFR0, STATE2, 8, 4)
1833 FIELD(ID_PFR0, STATE3, 12, 4)
1834 FIELD(ID_PFR0, CSV2, 16, 4)
1835 FIELD(ID_PFR0, AMU, 20, 4)
1836 FIELD(ID_PFR0, DIT, 24, 4)
1837 FIELD(ID_PFR0, RAS, 28, 4)
1838 
1839 FIELD(ID_PFR1, PROGMOD, 0, 4)
1840 FIELD(ID_PFR1, SECURITY, 4, 4)
1841 FIELD(ID_PFR1, MPROGMOD, 8, 4)
1842 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
1843 FIELD(ID_PFR1, GENTIMER, 16, 4)
1844 FIELD(ID_PFR1, SEC_FRAC, 20, 4)
1845 FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
1846 FIELD(ID_PFR1, GIC, 28, 4)
1847 
1848 FIELD(ID_AA64ISAR0, AES, 4, 4)
1849 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
1850 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
1851 FIELD(ID_AA64ISAR0, CRC32, 16, 4)
1852 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
1853 FIELD(ID_AA64ISAR0, RDM, 28, 4)
1854 FIELD(ID_AA64ISAR0, SHA3, 32, 4)
1855 FIELD(ID_AA64ISAR0, SM3, 36, 4)
1856 FIELD(ID_AA64ISAR0, SM4, 40, 4)
1857 FIELD(ID_AA64ISAR0, DP, 44, 4)
1858 FIELD(ID_AA64ISAR0, FHM, 48, 4)
1859 FIELD(ID_AA64ISAR0, TS, 52, 4)
1860 FIELD(ID_AA64ISAR0, TLB, 56, 4)
1861 FIELD(ID_AA64ISAR0, RNDR, 60, 4)
1862 
1863 FIELD(ID_AA64ISAR1, DPB, 0, 4)
1864 FIELD(ID_AA64ISAR1, APA, 4, 4)
1865 FIELD(ID_AA64ISAR1, API, 8, 4)
1866 FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
1867 FIELD(ID_AA64ISAR1, FCMA, 16, 4)
1868 FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
1869 FIELD(ID_AA64ISAR1, GPA, 24, 4)
1870 FIELD(ID_AA64ISAR1, GPI, 28, 4)
1871 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
1872 FIELD(ID_AA64ISAR1, SB, 36, 4)
1873 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
1874 
1875 FIELD(ID_AA64PFR0, EL0, 0, 4)
1876 FIELD(ID_AA64PFR0, EL1, 4, 4)
1877 FIELD(ID_AA64PFR0, EL2, 8, 4)
1878 FIELD(ID_AA64PFR0, EL3, 12, 4)
1879 FIELD(ID_AA64PFR0, FP, 16, 4)
1880 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
1881 FIELD(ID_AA64PFR0, GIC, 24, 4)
1882 FIELD(ID_AA64PFR0, RAS, 28, 4)
1883 FIELD(ID_AA64PFR0, SVE, 32, 4)
1884 
1885 FIELD(ID_AA64PFR1, BT, 0, 4)
1886 FIELD(ID_AA64PFR1, SBSS, 4, 4)
1887 FIELD(ID_AA64PFR1, MTE, 8, 4)
1888 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
1889 
1890 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
1891 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
1892 FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
1893 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
1894 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
1895 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
1896 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
1897 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
1898 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
1899 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
1900 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
1901 FIELD(ID_AA64MMFR0, EXS, 44, 4)
1902 
1903 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
1904 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
1905 FIELD(ID_AA64MMFR1, VH, 8, 4)
1906 FIELD(ID_AA64MMFR1, HPDS, 12, 4)
1907 FIELD(ID_AA64MMFR1, LO, 16, 4)
1908 FIELD(ID_AA64MMFR1, PAN, 20, 4)
1909 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
1910 FIELD(ID_AA64MMFR1, XNX, 28, 4)
1911 
1912 FIELD(ID_AA64MMFR2, CNP, 0, 4)
1913 FIELD(ID_AA64MMFR2, UAO, 4, 4)
1914 FIELD(ID_AA64MMFR2, LSM, 8, 4)
1915 FIELD(ID_AA64MMFR2, IESB, 12, 4)
1916 FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
1917 FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
1918 FIELD(ID_AA64MMFR2, NV, 24, 4)
1919 FIELD(ID_AA64MMFR2, ST, 28, 4)
1920 FIELD(ID_AA64MMFR2, AT, 32, 4)
1921 FIELD(ID_AA64MMFR2, IDS, 36, 4)
1922 FIELD(ID_AA64MMFR2, FWB, 40, 4)
1923 FIELD(ID_AA64MMFR2, TTL, 48, 4)
1924 FIELD(ID_AA64MMFR2, BBM, 52, 4)
1925 FIELD(ID_AA64MMFR2, EVT, 56, 4)
1926 FIELD(ID_AA64MMFR2, E0PD, 60, 4)
1927 
1928 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
1929 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
1930 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
1931 FIELD(ID_AA64DFR0, BRPS, 12, 4)
1932 FIELD(ID_AA64DFR0, WRPS, 20, 4)
1933 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
1934 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
1935 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
1936 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
1937 
1938 FIELD(ID_DFR0, COPDBG, 0, 4)
1939 FIELD(ID_DFR0, COPSDBG, 4, 4)
1940 FIELD(ID_DFR0, MMAPDBG, 8, 4)
1941 FIELD(ID_DFR0, COPTRC, 12, 4)
1942 FIELD(ID_DFR0, MMAPTRC, 16, 4)
1943 FIELD(ID_DFR0, MPROFDBG, 20, 4)
1944 FIELD(ID_DFR0, PERFMON, 24, 4)
1945 FIELD(ID_DFR0, TRACEFILT, 28, 4)
1946 
1947 FIELD(DBGDIDR, SE_IMP, 12, 1)
1948 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
1949 FIELD(DBGDIDR, VERSION, 16, 4)
1950 FIELD(DBGDIDR, CTX_CMPS, 20, 4)
1951 FIELD(DBGDIDR, BRPS, 24, 4)
1952 FIELD(DBGDIDR, WRPS, 28, 4)
1953 
1954 FIELD(MVFR0, SIMDREG, 0, 4)
1955 FIELD(MVFR0, FPSP, 4, 4)
1956 FIELD(MVFR0, FPDP, 8, 4)
1957 FIELD(MVFR0, FPTRAP, 12, 4)
1958 FIELD(MVFR0, FPDIVIDE, 16, 4)
1959 FIELD(MVFR0, FPSQRT, 20, 4)
1960 FIELD(MVFR0, FPSHVEC, 24, 4)
1961 FIELD(MVFR0, FPROUND, 28, 4)
1962 
1963 FIELD(MVFR1, FPFTZ, 0, 4)
1964 FIELD(MVFR1, FPDNAN, 4, 4)
1965 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
1966 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
1967 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
1968 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
1969 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
1970 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
1971 FIELD(MVFR1, FPHP, 24, 4)
1972 FIELD(MVFR1, SIMDFMAC, 28, 4)
1973 
1974 FIELD(MVFR2, SIMDMISC, 0, 4)
1975 FIELD(MVFR2, FPMISC, 4, 4)
1976 
1977 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
1978 
1979 /* If adding a feature bit which corresponds to a Linux ELF
1980  * HWCAP bit, remember to update the feature-bit-to-hwcap
1981  * mapping in linux-user/elfload.c:get_elf_hwcap().
1982  */
1983 enum arm_features {
1984     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
1985     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
1986     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
1987     ARM_FEATURE_V6,
1988     ARM_FEATURE_V6K,
1989     ARM_FEATURE_V7,
1990     ARM_FEATURE_THUMB2,
1991     ARM_FEATURE_PMSA,   /* no MMU; may have Memory Protection Unit */
1992     ARM_FEATURE_NEON,
1993     ARM_FEATURE_M, /* Microcontroller profile.  */
1994     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
1995     ARM_FEATURE_THUMB2EE,
1996     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
1997     ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
1998     ARM_FEATURE_V4T,
1999     ARM_FEATURE_V5,
2000     ARM_FEATURE_STRONGARM,
2001     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
2002     ARM_FEATURE_GENERIC_TIMER,
2003     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
2004     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
2005     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
2006     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
2007     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
2008     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
2009     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
2010     ARM_FEATURE_V8,
2011     ARM_FEATURE_AARCH64, /* supports 64 bit mode */
2012     ARM_FEATURE_CBAR, /* has cp15 CBAR */
2013     ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
2014     ARM_FEATURE_EL2, /* has EL2 Virtualization support */
2015     ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
2016     ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
2017     ARM_FEATURE_PMU, /* has PMU support */
2018     ARM_FEATURE_VBAR, /* has cp15 VBAR */
2019     ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
2020     ARM_FEATURE_M_MAIN, /* M profile Main Extension */
2021     ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
2022 };
2023 
2024 static inline int arm_feature(CPUARMState *env, int feature)
2025 {
2026     return (env->features & (1ULL << feature)) != 0;
2027 }
2028 
2029 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
2030 
2031 #if !defined(CONFIG_USER_ONLY)
2032 /* Return true if exception levels below EL3 are in secure state,
2033  * or would be following an exception return to that level.
2034  * Unlike arm_is_secure() (which is always a question about the
2035  * _current_ state of the CPU) this doesn't care about the current
2036  * EL or mode.
2037  */
2038 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2039 {
2040     if (arm_feature(env, ARM_FEATURE_EL3)) {
2041         return !(env->cp15.scr_el3 & SCR_NS);
2042     } else {
2043         /* If EL3 is not supported then the secure state is implementation
2044          * defined, in which case QEMU defaults to non-secure.
2045          */
2046         return false;
2047     }
2048 }
2049 
2050 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
2051 static inline bool arm_is_el3_or_mon(CPUARMState *env)
2052 {
2053     if (arm_feature(env, ARM_FEATURE_EL3)) {
2054         if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2055             /* CPU currently in AArch64 state and EL3 */
2056             return true;
2057         } else if (!is_a64(env) &&
2058                 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2059             /* CPU currently in AArch32 state and monitor mode */
2060             return true;
2061         }
2062     }
2063     return false;
2064 }
2065 
2066 /* Return true if the processor is in secure state */
2067 static inline bool arm_is_secure(CPUARMState *env)
2068 {
2069     if (arm_is_el3_or_mon(env)) {
2070         return true;
2071     }
2072     return arm_is_secure_below_el3(env);
2073 }
2074 
2075 #else
2076 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2077 {
2078     return false;
2079 }
2080 
2081 static inline bool arm_is_secure(CPUARMState *env)
2082 {
2083     return false;
2084 }
2085 #endif
2086 
2087 /**
2088  * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
2089  * E.g. when in secure state, fields in HCR_EL2 are suppressed,
2090  * "for all purposes other than a direct read or write access of HCR_EL2."
2091  * Not included here is HCR_RW.
2092  */
2093 uint64_t arm_hcr_el2_eff(CPUARMState *env);
2094 
2095 /* Return true if the specified exception level is running in AArch64 state. */
2096 static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2097 {
2098     /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
2099      * and if we're not in EL0 then the state of EL0 isn't well defined.)
2100      */
2101     assert(el >= 1 && el <= 3);
2102     bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2103 
2104     /* The highest exception level is always at the maximum supported
2105      * register width, and then lower levels have a register width controlled
2106      * by bits in the SCR or HCR registers.
2107      */
2108     if (el == 3) {
2109         return aa64;
2110     }
2111 
2112     if (arm_feature(env, ARM_FEATURE_EL3)) {
2113         aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2114     }
2115 
2116     if (el == 2) {
2117         return aa64;
2118     }
2119 
2120     if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
2121         aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2122     }
2123 
2124     return aa64;
2125 }
2126 
2127 /* Function for determing whether guest cp register reads and writes should
2128  * access the secure or non-secure bank of a cp register.  When EL3 is
2129  * operating in AArch32 state, the NS-bit determines whether the secure
2130  * instance of a cp register should be used. When EL3 is AArch64 (or if
2131  * it doesn't exist at all) then there is no register banking, and all
2132  * accesses are to the non-secure version.
2133  */
2134 static inline bool access_secure_reg(CPUARMState *env)
2135 {
2136     bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2137                 !arm_el_is_aa64(env, 3) &&
2138                 !(env->cp15.scr_el3 & SCR_NS));
2139 
2140     return ret;
2141 }
2142 
2143 /* Macros for accessing a specified CP register bank */
2144 #define A32_BANKED_REG_GET(_env, _regname, _secure)    \
2145     ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2146 
2147 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val)   \
2148     do {                                                \
2149         if (_secure) {                                   \
2150             (_env)->cp15._regname##_s = (_val);            \
2151         } else {                                        \
2152             (_env)->cp15._regname##_ns = (_val);           \
2153         }                                               \
2154     } while (0)
2155 
2156 /* Macros for automatically accessing a specific CP register bank depending on
2157  * the current secure state of the system.  These macros are not intended for
2158  * supporting instruction translation reads/writes as these are dependent
2159  * solely on the SCR.NS bit and not the mode.
2160  */
2161 #define A32_BANKED_CURRENT_REG_GET(_env, _regname)        \
2162     A32_BANKED_REG_GET((_env), _regname,                \
2163                        (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2164 
2165 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val)                       \
2166     A32_BANKED_REG_SET((_env), _regname,                                    \
2167                        (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2168                        (_val))
2169 
2170 void arm_cpu_list(void);
2171 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2172                                  uint32_t cur_el, bool secure);
2173 
2174 /* Interface between CPU and Interrupt controller.  */
2175 #ifndef CONFIG_USER_ONLY
2176 bool armv7m_nvic_can_take_pending_exception(void *opaque);
2177 #else
2178 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
2179 {
2180     return true;
2181 }
2182 #endif
2183 /**
2184  * armv7m_nvic_set_pending: mark the specified exception as pending
2185  * @opaque: the NVIC
2186  * @irq: the exception number to mark pending
2187  * @secure: false for non-banked exceptions or for the nonsecure
2188  * version of a banked exception, true for the secure version of a banked
2189  * exception.
2190  *
2191  * Marks the specified exception as pending. Note that we will assert()
2192  * if @secure is true and @irq does not specify one of the fixed set
2193  * of architecturally banked exceptions.
2194  */
2195 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
2196 /**
2197  * armv7m_nvic_set_pending_derived: mark this derived exception as pending
2198  * @opaque: the NVIC
2199  * @irq: the exception number to mark pending
2200  * @secure: false for non-banked exceptions or for the nonsecure
2201  * version of a banked exception, true for the secure version of a banked
2202  * exception.
2203  *
2204  * Similar to armv7m_nvic_set_pending(), but specifically for derived
2205  * exceptions (exceptions generated in the course of trying to take
2206  * a different exception).
2207  */
2208 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
2209 /**
2210  * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
2211  * @opaque: the NVIC
2212  * @irq: the exception number to mark pending
2213  * @secure: false for non-banked exceptions or for the nonsecure
2214  * version of a banked exception, true for the secure version of a banked
2215  * exception.
2216  *
2217  * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
2218  * generated in the course of lazy stacking of FP registers.
2219  */
2220 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
2221 /**
2222  * armv7m_nvic_get_pending_irq_info: return highest priority pending
2223  *    exception, and whether it targets Secure state
2224  * @opaque: the NVIC
2225  * @pirq: set to pending exception number
2226  * @ptargets_secure: set to whether pending exception targets Secure
2227  *
2228  * This function writes the number of the highest priority pending
2229  * exception (the one which would be made active by
2230  * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
2231  * to true if the current highest priority pending exception should
2232  * be taken to Secure state, false for NS.
2233  */
2234 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
2235                                       bool *ptargets_secure);
2236 /**
2237  * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
2238  * @opaque: the NVIC
2239  *
2240  * Move the current highest priority pending exception from the pending
2241  * state to the active state, and update v7m.exception to indicate that
2242  * it is the exception currently being handled.
2243  */
2244 void armv7m_nvic_acknowledge_irq(void *opaque);
2245 /**
2246  * armv7m_nvic_complete_irq: complete specified interrupt or exception
2247  * @opaque: the NVIC
2248  * @irq: the exception number to complete
2249  * @secure: true if this exception was secure
2250  *
2251  * Returns: -1 if the irq was not active
2252  *           1 if completing this irq brought us back to base (no active irqs)
2253  *           0 if there is still an irq active after this one was completed
2254  * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
2255  */
2256 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2257 /**
2258  * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
2259  * @opaque: the NVIC
2260  * @irq: the exception number to mark pending
2261  * @secure: false for non-banked exceptions or for the nonsecure
2262  * version of a banked exception, true for the secure version of a banked
2263  * exception.
2264  *
2265  * Return whether an exception is "ready", i.e. whether the exception is
2266  * enabled and is configured at a priority which would allow it to
2267  * interrupt the current execution priority. This controls whether the
2268  * RDY bit for it in the FPCCR is set.
2269  */
2270 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
2271 /**
2272  * armv7m_nvic_raw_execution_priority: return the raw execution priority
2273  * @opaque: the NVIC
2274  *
2275  * Returns: the raw execution priority as defined by the v8M architecture.
2276  * This is the execution priority minus the effects of AIRCR.PRIS,
2277  * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
2278  * (v8M ARM ARM I_PKLD.)
2279  */
2280 int armv7m_nvic_raw_execution_priority(void *opaque);
2281 /**
2282  * armv7m_nvic_neg_prio_requested: return true if the requested execution
2283  * priority is negative for the specified security state.
2284  * @opaque: the NVIC
2285  * @secure: the security state to test
2286  * This corresponds to the pseudocode IsReqExecPriNeg().
2287  */
2288 #ifndef CONFIG_USER_ONLY
2289 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2290 #else
2291 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2292 {
2293     return false;
2294 }
2295 #endif
2296 
2297 /* Interface for defining coprocessor registers.
2298  * Registers are defined in tables of arm_cp_reginfo structs
2299  * which are passed to define_arm_cp_regs().
2300  */
2301 
2302 /* When looking up a coprocessor register we look for it
2303  * via an integer which encodes all of:
2304  *  coprocessor number
2305  *  Crn, Crm, opc1, opc2 fields
2306  *  32 or 64 bit register (ie is it accessed via MRC/MCR
2307  *    or via MRRC/MCRR?)
2308  *  non-secure/secure bank (AArch32 only)
2309  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
2310  * (In this case crn and opc2 should be zero.)
2311  * For AArch64, there is no 32/64 bit size distinction;
2312  * instead all registers have a 2 bit op0, 3 bit op1 and op2,
2313  * and 4 bit CRn and CRm. The encoding patterns are chosen
2314  * to be easy to convert to and from the KVM encodings, and also
2315  * so that the hashtable can contain both AArch32 and AArch64
2316  * registers (to allow for interprocessing where we might run
2317  * 32 bit code on a 64 bit core).
2318  */
2319 /* This bit is private to our hashtable cpreg; in KVM register
2320  * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
2321  * in the upper bits of the 64 bit ID.
2322  */
2323 #define CP_REG_AA64_SHIFT 28
2324 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2325 
2326 /* To enable banking of coprocessor registers depending on ns-bit we
2327  * add a bit to distinguish between secure and non-secure cpregs in the
2328  * hashtable.
2329  */
2330 #define CP_REG_NS_SHIFT 29
2331 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2332 
2333 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
2334     ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
2335      ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2336 
2337 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2338     (CP_REG_AA64_MASK |                                 \
2339      ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
2340      ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
2341      ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
2342      ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
2343      ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
2344      ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2345 
2346 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
2347  * version used as a key for the coprocessor register hashtable
2348  */
2349 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2350 {
2351     uint32_t cpregid = kvmid;
2352     if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2353         cpregid |= CP_REG_AA64_MASK;
2354     } else {
2355         if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2356             cpregid |= (1 << 15);
2357         }
2358 
2359         /* KVM is always non-secure so add the NS flag on AArch32 register
2360          * entries.
2361          */
2362          cpregid |= 1 << CP_REG_NS_SHIFT;
2363     }
2364     return cpregid;
2365 }
2366 
2367 /* Convert a truncated 32 bit hashtable key into the full
2368  * 64 bit KVM register ID.
2369  */
2370 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2371 {
2372     uint64_t kvmid;
2373 
2374     if (cpregid & CP_REG_AA64_MASK) {
2375         kvmid = cpregid & ~CP_REG_AA64_MASK;
2376         kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2377     } else {
2378         kvmid = cpregid & ~(1 << 15);
2379         if (cpregid & (1 << 15)) {
2380             kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2381         } else {
2382             kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2383         }
2384     }
2385     return kvmid;
2386 }
2387 
2388 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
2389  * special-behaviour cp reg and bits [11..8] indicate what behaviour
2390  * it has. Otherwise it is a simple cp reg, where CONST indicates that
2391  * TCG can assume the value to be constant (ie load at translate time)
2392  * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
2393  * indicates that the TB should not be ended after a write to this register
2394  * (the default is that the TB ends after cp writes). OVERRIDE permits
2395  * a register definition to override a previous definition for the
2396  * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
2397  * old must have the OVERRIDE bit set.
2398  * ALIAS indicates that this register is an alias view of some underlying
2399  * state which is also visible via another register, and that the other
2400  * register is handling migration and reset; registers marked ALIAS will not be
2401  * migrated but may have their state set by syncing of register state from KVM.
2402  * NO_RAW indicates that this register has no underlying state and does not
2403  * support raw access for state saving/loading; it will not be used for either
2404  * migration or KVM state synchronization. (Typically this is for "registers"
2405  * which are actually used as instructions for cache maintenance and so on.)
2406  * IO indicates that this register does I/O and therefore its accesses
2407  * need to be marked with gen_io_start() and also end the TB. In particular,
2408  * registers which implement clocks or timers require this.
2409  * RAISES_EXC is for when the read or write hook might raise an exception;
2410  * the generated code will synchronize the CPU state before calling the hook
2411  * so that it is safe for the hook to call raise_exception().
2412  * NEWEL is for writes to registers that might change the exception
2413  * level - typically on older ARM chips. For those cases we need to
2414  * re-read the new el when recomputing the translation flags.
2415  */
2416 #define ARM_CP_SPECIAL           0x0001
2417 #define ARM_CP_CONST             0x0002
2418 #define ARM_CP_64BIT             0x0004
2419 #define ARM_CP_SUPPRESS_TB_END   0x0008
2420 #define ARM_CP_OVERRIDE          0x0010
2421 #define ARM_CP_ALIAS             0x0020
2422 #define ARM_CP_IO                0x0040
2423 #define ARM_CP_NO_RAW            0x0080
2424 #define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
2425 #define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
2426 #define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
2427 #define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
2428 #define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
2429 #define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
2430 #define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
2431 #define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
2432 #define ARM_CP_FPU               0x1000
2433 #define ARM_CP_SVE               0x2000
2434 #define ARM_CP_NO_GDB            0x4000
2435 #define ARM_CP_RAISES_EXC        0x8000
2436 #define ARM_CP_NEWEL             0x10000
2437 /* Used only as a terminator for ARMCPRegInfo lists */
2438 #define ARM_CP_SENTINEL          0xfffff
2439 /* Mask of only the flag bits in a type field */
2440 #define ARM_CP_FLAG_MASK         0x1f0ff
2441 
2442 /* Valid values for ARMCPRegInfo state field, indicating which of
2443  * the AArch32 and AArch64 execution states this register is visible in.
2444  * If the reginfo doesn't explicitly specify then it is AArch32 only.
2445  * If the reginfo is declared to be visible in both states then a second
2446  * reginfo is synthesised for the AArch32 view of the AArch64 register,
2447  * such that the AArch32 view is the lower 32 bits of the AArch64 one.
2448  * Note that we rely on the values of these enums as we iterate through
2449  * the various states in some places.
2450  */
2451 enum {
2452     ARM_CP_STATE_AA32 = 0,
2453     ARM_CP_STATE_AA64 = 1,
2454     ARM_CP_STATE_BOTH = 2,
2455 };
2456 
2457 /* ARM CP register secure state flags.  These flags identify security state
2458  * attributes for a given CP register entry.
2459  * The existence of both or neither secure and non-secure flags indicates that
2460  * the register has both a secure and non-secure hash entry.  A single one of
2461  * these flags causes the register to only be hashed for the specified
2462  * security state.
2463  * Although definitions may have any combination of the S/NS bits, each
2464  * registered entry will only have one to identify whether the entry is secure
2465  * or non-secure.
2466  */
2467 enum {
2468     ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
2469     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
2470 };
2471 
2472 /* Return true if cptype is a valid type field. This is used to try to
2473  * catch errors where the sentinel has been accidentally left off the end
2474  * of a list of registers.
2475  */
2476 static inline bool cptype_valid(int cptype)
2477 {
2478     return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
2479         || ((cptype & ARM_CP_SPECIAL) &&
2480             ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
2481 }
2482 
2483 /* Access rights:
2484  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
2485  * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
2486  * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
2487  * (ie any of the privileged modes in Secure state, or Monitor mode).
2488  * If a register is accessible in one privilege level it's always accessible
2489  * in higher privilege levels too. Since "Secure PL1" also follows this rule
2490  * (ie anything visible in PL2 is visible in S-PL1, some things are only
2491  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
2492  * terminology a little and call this PL3.
2493  * In AArch64 things are somewhat simpler as the PLx bits line up exactly
2494  * with the ELx exception levels.
2495  *
2496  * If access permissions for a register are more complex than can be
2497  * described with these bits, then use a laxer set of restrictions, and
2498  * do the more restrictive/complex check inside a helper function.
2499  */
2500 #define PL3_R 0x80
2501 #define PL3_W 0x40
2502 #define PL2_R (0x20 | PL3_R)
2503 #define PL2_W (0x10 | PL3_W)
2504 #define PL1_R (0x08 | PL2_R)
2505 #define PL1_W (0x04 | PL2_W)
2506 #define PL0_R (0x02 | PL1_R)
2507 #define PL0_W (0x01 | PL1_W)
2508 
2509 /*
2510  * For user-mode some registers are accessible to EL0 via a kernel
2511  * trap-and-emulate ABI. In this case we define the read permissions
2512  * as actually being PL0_R. However some bits of any given register
2513  * may still be masked.
2514  */
2515 #ifdef CONFIG_USER_ONLY
2516 #define PL0U_R PL0_R
2517 #else
2518 #define PL0U_R PL1_R
2519 #endif
2520 
2521 #define PL3_RW (PL3_R | PL3_W)
2522 #define PL2_RW (PL2_R | PL2_W)
2523 #define PL1_RW (PL1_R | PL1_W)
2524 #define PL0_RW (PL0_R | PL0_W)
2525 
2526 /* Return the highest implemented Exception Level */
2527 static inline int arm_highest_el(CPUARMState *env)
2528 {
2529     if (arm_feature(env, ARM_FEATURE_EL3)) {
2530         return 3;
2531     }
2532     if (arm_feature(env, ARM_FEATURE_EL2)) {
2533         return 2;
2534     }
2535     return 1;
2536 }
2537 
2538 /* Return true if a v7M CPU is in Handler mode */
2539 static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2540 {
2541     return env->v7m.exception != 0;
2542 }
2543 
2544 /* Return the current Exception Level (as per ARMv8; note that this differs
2545  * from the ARMv7 Privilege Level).
2546  */
2547 static inline int arm_current_el(CPUARMState *env)
2548 {
2549     if (arm_feature(env, ARM_FEATURE_M)) {
2550         return arm_v7m_is_handler_mode(env) ||
2551             !(env->v7m.control[env->v7m.secure] & 1);
2552     }
2553 
2554     if (is_a64(env)) {
2555         return extract32(env->pstate, 2, 2);
2556     }
2557 
2558     switch (env->uncached_cpsr & 0x1f) {
2559     case ARM_CPU_MODE_USR:
2560         return 0;
2561     case ARM_CPU_MODE_HYP:
2562         return 2;
2563     case ARM_CPU_MODE_MON:
2564         return 3;
2565     default:
2566         if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2567             /* If EL3 is 32-bit then all secure privileged modes run in
2568              * EL3
2569              */
2570             return 3;
2571         }
2572 
2573         return 1;
2574     }
2575 }
2576 
2577 typedef struct ARMCPRegInfo ARMCPRegInfo;
2578 
2579 typedef enum CPAccessResult {
2580     /* Access is permitted */
2581     CP_ACCESS_OK = 0,
2582     /* Access fails due to a configurable trap or enable which would
2583      * result in a categorized exception syndrome giving information about
2584      * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
2585      * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
2586      * PL1 if in EL0, otherwise to the current EL).
2587      */
2588     CP_ACCESS_TRAP = 1,
2589     /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
2590      * Note that this is not a catch-all case -- the set of cases which may
2591      * result in this failure is specifically defined by the architecture.
2592      */
2593     CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2594     /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
2595     CP_ACCESS_TRAP_EL2 = 3,
2596     CP_ACCESS_TRAP_EL3 = 4,
2597     /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
2598     CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2599     CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2600     /* Access fails and results in an exception syndrome for an FP access,
2601      * trapped directly to EL2 or EL3
2602      */
2603     CP_ACCESS_TRAP_FP_EL2 = 7,
2604     CP_ACCESS_TRAP_FP_EL3 = 8,
2605 } CPAccessResult;
2606 
2607 /* Access functions for coprocessor registers. These cannot fail and
2608  * may not raise exceptions.
2609  */
2610 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2611 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2612                        uint64_t value);
2613 /* Access permission check functions for coprocessor registers. */
2614 typedef CPAccessResult CPAccessFn(CPUARMState *env,
2615                                   const ARMCPRegInfo *opaque,
2616                                   bool isread);
2617 /* Hook function for register reset */
2618 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2619 
2620 #define CP_ANY 0xff
2621 
2622 /* Definition of an ARM coprocessor register */
2623 struct ARMCPRegInfo {
2624     /* Name of register (useful mainly for debugging, need not be unique) */
2625     const char *name;
2626     /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
2627      * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
2628      * 'wildcard' field -- any value of that field in the MRC/MCR insn
2629      * will be decoded to this register. The register read and write
2630      * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
2631      * used by the program, so it is possible to register a wildcard and
2632      * then behave differently on read/write if necessary.
2633      * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
2634      * must both be zero.
2635      * For AArch64-visible registers, opc0 is also used.
2636      * Since there are no "coprocessors" in AArch64, cp is purely used as a
2637      * way to distinguish (for KVM's benefit) guest-visible system registers
2638      * from demuxed ones provided to preserve the "no side effects on
2639      * KVM register read/write from QEMU" semantics. cp==0x13 is guest
2640      * visible (to match KVM's encoding); cp==0 will be converted to
2641      * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
2642      */
2643     uint8_t cp;
2644     uint8_t crn;
2645     uint8_t crm;
2646     uint8_t opc0;
2647     uint8_t opc1;
2648     uint8_t opc2;
2649     /* Execution state in which this register is visible: ARM_CP_STATE_* */
2650     int state;
2651     /* Register type: ARM_CP_* bits/values */
2652     int type;
2653     /* Access rights: PL*_[RW] */
2654     int access;
2655     /* Security state: ARM_CP_SECSTATE_* bits/values */
2656     int secure;
2657     /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
2658      * this register was defined: can be used to hand data through to the
2659      * register read/write functions, since they are passed the ARMCPRegInfo*.
2660      */
2661     void *opaque;
2662     /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
2663      * fieldoffset is non-zero, the reset value of the register.
2664      */
2665     uint64_t resetvalue;
2666     /* Offset of the field in CPUARMState for this register.
2667      *
2668      * This is not needed if either:
2669      *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
2670      *  2. both readfn and writefn are specified
2671      */
2672     ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
2673 
2674     /* Offsets of the secure and non-secure fields in CPUARMState for the
2675      * register if it is banked.  These fields are only used during the static
2676      * registration of a register.  During hashing the bank associated
2677      * with a given security state is copied to fieldoffset which is used from
2678      * there on out.
2679      *
2680      * It is expected that register definitions use either fieldoffset or
2681      * bank_fieldoffsets in the definition but not both.  It is also expected
2682      * that both bank offsets are set when defining a banked register.  This
2683      * use indicates that a register is banked.
2684      */
2685     ptrdiff_t bank_fieldoffsets[2];
2686 
2687     /* Function for making any access checks for this register in addition to
2688      * those specified by the 'access' permissions bits. If NULL, no extra
2689      * checks required. The access check is performed at runtime, not at
2690      * translate time.
2691      */
2692     CPAccessFn *accessfn;
2693     /* Function for handling reads of this register. If NULL, then reads
2694      * will be done by loading from the offset into CPUARMState specified
2695      * by fieldoffset.
2696      */
2697     CPReadFn *readfn;
2698     /* Function for handling writes of this register. If NULL, then writes
2699      * will be done by writing to the offset into CPUARMState specified
2700      * by fieldoffset.
2701      */
2702     CPWriteFn *writefn;
2703     /* Function for doing a "raw" read; used when we need to copy
2704      * coprocessor state to the kernel for KVM or out for
2705      * migration. This only needs to be provided if there is also a
2706      * readfn and it has side effects (for instance clear-on-read bits).
2707      */
2708     CPReadFn *raw_readfn;
2709     /* Function for doing a "raw" write; used when we need to copy KVM
2710      * kernel coprocessor state into userspace, or for inbound
2711      * migration. This only needs to be provided if there is also a
2712      * writefn and it masks out "unwritable" bits or has write-one-to-clear
2713      * or similar behaviour.
2714      */
2715     CPWriteFn *raw_writefn;
2716     /* Function for resetting the register. If NULL, then reset will be done
2717      * by writing resetvalue to the field specified in fieldoffset. If
2718      * fieldoffset is 0 then no reset will be done.
2719      */
2720     CPResetFn *resetfn;
2721 
2722     /*
2723      * "Original" writefn and readfn.
2724      * For ARMv8.1-VHE register aliases, we overwrite the read/write
2725      * accessor functions of various EL1/EL0 to perform the runtime
2726      * check for which sysreg should actually be modified, and then
2727      * forwards the operation.  Before overwriting the accessors,
2728      * the original function is copied here, so that accesses that
2729      * really do go to the EL1/EL0 version proceed normally.
2730      * (The corresponding EL2 register is linked via opaque.)
2731      */
2732     CPReadFn *orig_readfn;
2733     CPWriteFn *orig_writefn;
2734 };
2735 
2736 /* Macros which are lvalues for the field in CPUARMState for the
2737  * ARMCPRegInfo *ri.
2738  */
2739 #define CPREG_FIELD32(env, ri) \
2740     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2741 #define CPREG_FIELD64(env, ri) \
2742     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2743 
2744 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2745 
2746 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2747                                     const ARMCPRegInfo *regs, void *opaque);
2748 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2749                                        const ARMCPRegInfo *regs, void *opaque);
2750 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2751 {
2752     define_arm_cp_regs_with_opaque(cpu, regs, 0);
2753 }
2754 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2755 {
2756     define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2757 }
2758 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2759 
2760 /*
2761  * Definition of an ARM co-processor register as viewed from
2762  * userspace. This is used for presenting sanitised versions of
2763  * registers to userspace when emulating the Linux AArch64 CPU
2764  * ID/feature ABI (advertised as HWCAP_CPUID).
2765  */
2766 typedef struct ARMCPRegUserSpaceInfo {
2767     /* Name of register */
2768     const char *name;
2769 
2770     /* Is the name actually a glob pattern */
2771     bool is_glob;
2772 
2773     /* Only some bits are exported to user space */
2774     uint64_t exported_bits;
2775 
2776     /* Fixed bits are applied after the mask */
2777     uint64_t fixed_bits;
2778 } ARMCPRegUserSpaceInfo;
2779 
2780 #define REGUSERINFO_SENTINEL { .name = NULL }
2781 
2782 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
2783 
2784 /* CPWriteFn that can be used to implement writes-ignored behaviour */
2785 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2786                          uint64_t value);
2787 /* CPReadFn that can be used for read-as-zero behaviour */
2788 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2789 
2790 /* CPResetFn that does nothing, for use if no reset is required even
2791  * if fieldoffset is non zero.
2792  */
2793 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2794 
2795 /* Return true if this reginfo struct's field in the cpu state struct
2796  * is 64 bits wide.
2797  */
2798 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2799 {
2800     return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2801 }
2802 
2803 static inline bool cp_access_ok(int current_el,
2804                                 const ARMCPRegInfo *ri, int isread)
2805 {
2806     return (ri->access >> ((current_el * 2) + isread)) & 1;
2807 }
2808 
2809 /* Raw read of a coprocessor register (as needed for migration, etc) */
2810 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2811 
2812 /**
2813  * write_list_to_cpustate
2814  * @cpu: ARMCPU
2815  *
2816  * For each register listed in the ARMCPU cpreg_indexes list, write
2817  * its value from the cpreg_values list into the ARMCPUState structure.
2818  * This updates TCG's working data structures from KVM data or
2819  * from incoming migration state.
2820  *
2821  * Returns: true if all register values were updated correctly,
2822  * false if some register was unknown or could not be written.
2823  * Note that we do not stop early on failure -- we will attempt
2824  * writing all registers in the list.
2825  */
2826 bool write_list_to_cpustate(ARMCPU *cpu);
2827 
2828 /**
2829  * write_cpustate_to_list:
2830  * @cpu: ARMCPU
2831  * @kvm_sync: true if this is for syncing back to KVM
2832  *
2833  * For each register listed in the ARMCPU cpreg_indexes list, write
2834  * its value from the ARMCPUState structure into the cpreg_values list.
2835  * This is used to copy info from TCG's working data structures into
2836  * KVM or for outbound migration.
2837  *
2838  * @kvm_sync is true if we are doing this in order to sync the
2839  * register state back to KVM. In this case we will only update
2840  * values in the list if the previous list->cpustate sync actually
2841  * successfully wrote the CPU state. Otherwise we will keep the value
2842  * that is in the list.
2843  *
2844  * Returns: true if all register values were read correctly,
2845  * false if some register was unknown or could not be read.
2846  * Note that we do not stop early on failure -- we will attempt
2847  * reading all registers in the list.
2848  */
2849 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2850 
2851 #define ARM_CPUID_TI915T      0x54029152
2852 #define ARM_CPUID_TI925T      0x54029252
2853 
2854 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2855 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2856 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2857 
2858 #define cpu_signal_handler cpu_arm_signal_handler
2859 #define cpu_list arm_cpu_list
2860 
2861 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
2862  *
2863  * If EL3 is 64-bit:
2864  *  + NonSecure EL1 & 0 stage 1
2865  *  + NonSecure EL1 & 0 stage 2
2866  *  + NonSecure EL2
2867  *  + NonSecure EL2 & 0   (ARMv8.1-VHE)
2868  *  + Secure EL1 & 0
2869  *  + Secure EL3
2870  * If EL3 is 32-bit:
2871  *  + NonSecure PL1 & 0 stage 1
2872  *  + NonSecure PL1 & 0 stage 2
2873  *  + NonSecure PL2
2874  *  + Secure PL0
2875  *  + Secure PL1
2876  * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2877  *
2878  * For QEMU, an mmu_idx is not quite the same as a translation regime because:
2879  *  1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
2880  *     because they may differ in access permissions even if the VA->PA map is
2881  *     the same
2882  *  2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2883  *     translation, which means that we have one mmu_idx that deals with two
2884  *     concatenated translation regimes [this sort of combined s1+2 TLB is
2885  *     architecturally permitted]
2886  *  3. we don't need to allocate an mmu_idx to translations that we won't be
2887  *     handling via the TLB. The only way to do a stage 1 translation without
2888  *     the immediate stage 2 translation is via the ATS or AT system insns,
2889  *     which can be slow-pathed and always do a page table walk.
2890  *     The only use of stage 2 translations is either as part of an s1+2
2891  *     lookup or when loading the descriptors during a stage 1 page table walk,
2892  *     and in both those cases we don't use the TLB.
2893  *  4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2894  *     translation regimes, because they map reasonably well to each other
2895  *     and they can't both be active at the same time.
2896  *  5. we want to be able to use the TLB for accesses done as part of a
2897  *     stage1 page table walk, rather than having to walk the stage2 page
2898  *     table over and over.
2899  *  6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
2900  *     Never (PAN) bit within PSTATE.
2901  *
2902  * This gives us the following list of cases:
2903  *
2904  * NS EL0 EL1&0 stage 1+2 (aka NS PL0)
2905  * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
2906  * NS EL1 EL1&0 stage 1+2 +PAN
2907  * NS EL0 EL2&0
2908  * NS EL2 EL2&0
2909  * NS EL2 EL2&0 +PAN
2910  * NS EL2 (aka NS PL2)
2911  * S EL0 EL1&0 (aka S PL0)
2912  * S EL1 EL1&0 (not used if EL3 is 32 bit)
2913  * S EL1 EL1&0 +PAN
2914  * S EL3 (aka S PL1)
2915  *
2916  * for a total of 11 different mmu_idx.
2917  *
2918  * R profile CPUs have an MPU, but can use the same set of MMU indexes
2919  * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
2920  * NS EL2 if we ever model a Cortex-R52).
2921  *
2922  * M profile CPUs are rather different as they do not have a true MMU.
2923  * They have the following different MMU indexes:
2924  *  User
2925  *  Privileged
2926  *  User, execution priority negative (ie the MPU HFNMIENA bit may apply)
2927  *  Privileged, execution priority negative (ditto)
2928  * If the CPU supports the v8M Security Extension then there are also:
2929  *  Secure User
2930  *  Secure Privileged
2931  *  Secure User, execution priority negative
2932  *  Secure Privileged, execution priority negative
2933  *
2934  * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
2935  * are not quite the same -- different CPU types (most notably M profile
2936  * vs A/R profile) would like to use MMU indexes with different semantics,
2937  * but since we don't ever need to use all of those in a single CPU we
2938  * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
2939  * modes + total number of M profile MMU modes". The lower bits of
2940  * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
2941  * the same for any particular CPU.
2942  * Variables of type ARMMUIdx are always full values, and the core
2943  * index values are in variables of type 'int'.
2944  *
2945  * Our enumeration includes at the end some entries which are not "true"
2946  * mmu_idx values in that they don't have corresponding TLBs and are only
2947  * valid for doing slow path page table walks.
2948  *
2949  * The constant names here are patterned after the general style of the names
2950  * of the AT/ATS operations.
2951  * The values used are carefully arranged to make mmu_idx => EL lookup easy.
2952  * For M profile we arrange them to have a bit for priv, a bit for negpri
2953  * and a bit for secure.
2954  */
2955 #define ARM_MMU_IDX_A     0x10  /* A profile */
2956 #define ARM_MMU_IDX_NOTLB 0x20  /* does not have a TLB */
2957 #define ARM_MMU_IDX_M     0x40  /* M profile */
2958 
2959 /* Meanings of the bits for M profile mmu idx values */
2960 #define ARM_MMU_IDX_M_PRIV   0x1
2961 #define ARM_MMU_IDX_M_NEGPRI 0x2
2962 #define ARM_MMU_IDX_M_S      0x4  /* Secure */
2963 
2964 #define ARM_MMU_IDX_TYPE_MASK \
2965     (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
2966 #define ARM_MMU_IDX_COREIDX_MASK 0xf
2967 
2968 typedef enum ARMMMUIdx {
2969     /*
2970      * A-profile.
2971      */
2972     ARMMMUIdx_E10_0      =  0 | ARM_MMU_IDX_A,
2973     ARMMMUIdx_E20_0      =  1 | ARM_MMU_IDX_A,
2974 
2975     ARMMMUIdx_E10_1      =  2 | ARM_MMU_IDX_A,
2976     ARMMMUIdx_E10_1_PAN  =  3 | ARM_MMU_IDX_A,
2977 
2978     ARMMMUIdx_E2         =  4 | ARM_MMU_IDX_A,
2979     ARMMMUIdx_E20_2      =  5 | ARM_MMU_IDX_A,
2980     ARMMMUIdx_E20_2_PAN  =  6 | ARM_MMU_IDX_A,
2981 
2982     ARMMMUIdx_SE10_0     = 7 | ARM_MMU_IDX_A,
2983     ARMMMUIdx_SE10_1     = 8 | ARM_MMU_IDX_A,
2984     ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,
2985     ARMMMUIdx_SE3        = 10 | ARM_MMU_IDX_A,
2986 
2987     /*
2988      * These are not allocated TLBs and are used only for AT system
2989      * instructions or for the first stage of an S12 page table walk.
2990      */
2991     ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
2992     ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
2993     ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
2994     /*
2995      * Not allocated a TLB: used only for second stage of an S12 page
2996      * table walk, or for descriptor loads during first stage of an S1
2997      * page table walk. Note that if we ever want to have a TLB for this
2998      * then various TLB flush insns which currently are no-ops or flush
2999      * only stage 1 MMU indexes will need to change to flush stage 2.
3000      */
3001     ARMMMUIdx_Stage2     = 3 | ARM_MMU_IDX_NOTLB,
3002 
3003     /*
3004      * M-profile.
3005      */
3006     ARMMMUIdx_MUser = ARM_MMU_IDX_M,
3007     ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
3008     ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
3009     ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
3010     ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
3011     ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
3012     ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
3013     ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
3014 } ARMMMUIdx;
3015 
3016 /*
3017  * Bit macros for the core-mmu-index values for each index,
3018  * for use when calling tlb_flush_by_mmuidx() and friends.
3019  */
3020 #define TO_CORE_BIT(NAME) \
3021     ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
3022 
3023 typedef enum ARMMMUIdxBit {
3024     TO_CORE_BIT(E10_0),
3025     TO_CORE_BIT(E20_0),
3026     TO_CORE_BIT(E10_1),
3027     TO_CORE_BIT(E10_1_PAN),
3028     TO_CORE_BIT(E2),
3029     TO_CORE_BIT(E20_2),
3030     TO_CORE_BIT(E20_2_PAN),
3031     TO_CORE_BIT(SE10_0),
3032     TO_CORE_BIT(SE10_1),
3033     TO_CORE_BIT(SE10_1_PAN),
3034     TO_CORE_BIT(SE3),
3035 
3036     TO_CORE_BIT(MUser),
3037     TO_CORE_BIT(MPriv),
3038     TO_CORE_BIT(MUserNegPri),
3039     TO_CORE_BIT(MPrivNegPri),
3040     TO_CORE_BIT(MSUser),
3041     TO_CORE_BIT(MSPriv),
3042     TO_CORE_BIT(MSUserNegPri),
3043     TO_CORE_BIT(MSPrivNegPri),
3044 } ARMMMUIdxBit;
3045 
3046 #undef TO_CORE_BIT
3047 
3048 #define MMU_USER_IDX 0
3049 
3050 /* Indexes used when registering address spaces with cpu_address_space_init */
3051 typedef enum ARMASIdx {
3052     ARMASIdx_NS = 0,
3053     ARMASIdx_S = 1,
3054     ARMASIdx_TagNS = 2,
3055     ARMASIdx_TagS = 3,
3056 } ARMASIdx;
3057 
3058 /* Return the Exception Level targeted by debug exceptions. */
3059 static inline int arm_debug_target_el(CPUARMState *env)
3060 {
3061     bool secure = arm_is_secure(env);
3062     bool route_to_el2 = false;
3063 
3064     if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
3065         route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
3066                        env->cp15.mdcr_el2 & MDCR_TDE;
3067     }
3068 
3069     if (route_to_el2) {
3070         return 2;
3071     } else if (arm_feature(env, ARM_FEATURE_EL3) &&
3072                !arm_el_is_aa64(env, 3) && secure) {
3073         return 3;
3074     } else {
3075         return 1;
3076     }
3077 }
3078 
3079 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
3080 {
3081     /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
3082      * CSSELR is RAZ/WI.
3083      */
3084     return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
3085 }
3086 
3087 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
3088 static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
3089 {
3090     int cur_el = arm_current_el(env);
3091     int debug_el;
3092 
3093     if (cur_el == 3) {
3094         return false;
3095     }
3096 
3097     /* MDCR_EL3.SDD disables debug events from Secure state */
3098     if (arm_is_secure_below_el3(env)
3099         && extract32(env->cp15.mdcr_el3, 16, 1)) {
3100         return false;
3101     }
3102 
3103     /*
3104      * Same EL to same EL debug exceptions need MDSCR_KDE enabled
3105      * while not masking the (D)ebug bit in DAIF.
3106      */
3107     debug_el = arm_debug_target_el(env);
3108 
3109     if (cur_el == debug_el) {
3110         return extract32(env->cp15.mdscr_el1, 13, 1)
3111             && !(env->daif & PSTATE_D);
3112     }
3113 
3114     /* Otherwise the debug target needs to be a higher EL */
3115     return debug_el > cur_el;
3116 }
3117 
3118 static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
3119 {
3120     int el = arm_current_el(env);
3121 
3122     if (el == 0 && arm_el_is_aa64(env, 1)) {
3123         return aa64_generate_debug_exceptions(env);
3124     }
3125 
3126     if (arm_is_secure(env)) {
3127         int spd;
3128 
3129         if (el == 0 && (env->cp15.sder & 1)) {
3130             /* SDER.SUIDEN means debug exceptions from Secure EL0
3131              * are always enabled. Otherwise they are controlled by
3132              * SDCR.SPD like those from other Secure ELs.
3133              */
3134             return true;
3135         }
3136 
3137         spd = extract32(env->cp15.mdcr_el3, 14, 2);
3138         switch (spd) {
3139         case 1:
3140             /* SPD == 0b01 is reserved, but behaves as 0b00. */
3141         case 0:
3142             /* For 0b00 we return true if external secure invasive debug
3143              * is enabled. On real hardware this is controlled by external
3144              * signals to the core. QEMU always permits debug, and behaves
3145              * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
3146              */
3147             return true;
3148         case 2:
3149             return false;
3150         case 3:
3151             return true;
3152         }
3153     }
3154 
3155     return el != 2;
3156 }
3157 
3158 /* Return true if debugging exceptions are currently enabled.
3159  * This corresponds to what in ARM ARM pseudocode would be
3160  *    if UsingAArch32() then
3161  *        return AArch32.GenerateDebugExceptions()
3162  *    else
3163  *        return AArch64.GenerateDebugExceptions()
3164  * We choose to push the if() down into this function for clarity,
3165  * since the pseudocode has it at all callsites except for the one in
3166  * CheckSoftwareStep(), where it is elided because both branches would
3167  * always return the same value.
3168  */
3169 static inline bool arm_generate_debug_exceptions(CPUARMState *env)
3170 {
3171     if (env->aarch64) {
3172         return aa64_generate_debug_exceptions(env);
3173     } else {
3174         return aa32_generate_debug_exceptions(env);
3175     }
3176 }
3177 
3178 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
3179  * implicitly means this always returns false in pre-v8 CPUs.)
3180  */
3181 static inline bool arm_singlestep_active(CPUARMState *env)
3182 {
3183     return extract32(env->cp15.mdscr_el1, 0, 1)
3184         && arm_el_is_aa64(env, arm_debug_target_el(env))
3185         && arm_generate_debug_exceptions(env);
3186 }
3187 
3188 static inline bool arm_sctlr_b(CPUARMState *env)
3189 {
3190     return
3191         /* We need not implement SCTLR.ITD in user-mode emulation, so
3192          * let linux-user ignore the fact that it conflicts with SCTLR_B.
3193          * This lets people run BE32 binaries with "-cpu any".
3194          */
3195 #ifndef CONFIG_USER_ONLY
3196         !arm_feature(env, ARM_FEATURE_V7) &&
3197 #endif
3198         (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3199 }
3200 
3201 uint64_t arm_sctlr(CPUARMState *env, int el);
3202 
3203 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
3204                                                   bool sctlr_b)
3205 {
3206 #ifdef CONFIG_USER_ONLY
3207     /*
3208      * In system mode, BE32 is modelled in line with the
3209      * architecture (as word-invariant big-endianness), where loads
3210      * and stores are done little endian but from addresses which
3211      * are adjusted by XORing with the appropriate constant. So the
3212      * endianness to use for the raw data access is not affected by
3213      * SCTLR.B.
3214      * In user mode, however, we model BE32 as byte-invariant
3215      * big-endianness (because user-only code cannot tell the
3216      * difference), and so we need to use a data access endianness
3217      * that depends on SCTLR.B.
3218      */
3219     if (sctlr_b) {
3220         return true;
3221     }
3222 #endif
3223     /* In 32bit endianness is determined by looking at CPSR's E bit */
3224     return env->uncached_cpsr & CPSR_E;
3225 }
3226 
3227 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3228 {
3229     return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3230 }
3231 
3232 /* Return true if the processor is in big-endian mode. */
3233 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3234 {
3235     if (!is_a64(env)) {
3236         return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3237     } else {
3238         int cur_el = arm_current_el(env);
3239         uint64_t sctlr = arm_sctlr(env, cur_el);
3240         return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3241     }
3242 }
3243 
3244 typedef CPUARMState CPUArchState;
3245 typedef ARMCPU ArchCPU;
3246 
3247 #include "exec/cpu-all.h"
3248 
3249 /*
3250  * Bit usage in the TB flags field: bit 31 indicates whether we are
3251  * in 32 or 64 bit mode. The meaning of the other bits depends on that.
3252  * We put flags which are shared between 32 and 64 bit mode at the top
3253  * of the word, and flags which apply to only one mode at the bottom.
3254  *
3255  *  31          20    18    14          9              0
3256  * +--------------+-----+-----+----------+--------------+
3257  * |              |     |   TBFLAG_A32   |              |
3258  * |              |     +-----+----------+  TBFLAG_AM32 |
3259  * |  TBFLAG_ANY  |           |TBFLAG_M32|              |
3260  * |              +-----------+----------+--------------|
3261  * |              |            TBFLAG_A64               |
3262  * +--------------+-------------------------------------+
3263  *  31          20                                     0
3264  *
3265  * Unless otherwise noted, these bits are cached in env->hflags.
3266  */
3267 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
3268 FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
3269 FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1)     /* Not cached. */
3270 FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
3271 FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
3272 /* Target EL if we take a floating-point-disabled exception */
3273 FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
3274 /* For A-profile only, target EL for debug exceptions.  */
3275 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
3276 
3277 /*
3278  * Bit usage when in AArch32 state, both A- and M-profile.
3279  */
3280 FIELD(TBFLAG_AM32, CONDEXEC, 0, 8)      /* Not cached. */
3281 FIELD(TBFLAG_AM32, THUMB, 8, 1)         /* Not cached. */
3282 
3283 /*
3284  * Bit usage when in AArch32 state, for A-profile only.
3285  */
3286 FIELD(TBFLAG_A32, VECLEN, 9, 3)         /* Not cached. */
3287 FIELD(TBFLAG_A32, VECSTRIDE, 12, 2)     /* Not cached. */
3288 /*
3289  * We store the bottom two bits of the CPAR as TB flags and handle
3290  * checks on the other bits at runtime. This shares the same bits as
3291  * VECSTRIDE, which is OK as no XScale CPU has VFP.
3292  * Not cached, because VECLEN+VECSTRIDE are not cached.
3293  */
3294 FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
3295 FIELD(TBFLAG_A32, VFPEN, 14, 1)         /* Partially cached, minus FPEXC. */
3296 FIELD(TBFLAG_A32, SCTLR_B, 15, 1)
3297 FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
3298 /*
3299  * Indicates whether cp register reads and writes by guest code should access
3300  * the secure or nonsecure bank of banked registers; note that this is not
3301  * the same thing as the current security state of the processor!
3302  */
3303 FIELD(TBFLAG_A32, NS, 17, 1)
3304 
3305 /*
3306  * Bit usage when in AArch32 state, for M-profile only.
3307  */
3308 /* Handler (ie not Thread) mode */
3309 FIELD(TBFLAG_M32, HANDLER, 9, 1)
3310 /* Whether we should generate stack-limit checks */
3311 FIELD(TBFLAG_M32, STACKCHECK, 10, 1)
3312 /* Set if FPCCR.LSPACT is set */
3313 FIELD(TBFLAG_M32, LSPACT, 11, 1)                 /* Not cached. */
3314 /* Set if we must create a new FP context */
3315 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1)     /* Not cached. */
3316 /* Set if FPCCR.S does not match current security state */
3317 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1)          /* Not cached. */
3318 
3319 /*
3320  * Bit usage when in AArch64 state
3321  */
3322 FIELD(TBFLAG_A64, TBII, 0, 2)
3323 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3324 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
3325 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3326 FIELD(TBFLAG_A64, BT, 9, 1)
3327 FIELD(TBFLAG_A64, BTYPE, 10, 2)         /* Not cached. */
3328 FIELD(TBFLAG_A64, TBID, 12, 2)
3329 FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3330 FIELD(TBFLAG_A64, ATA, 15, 1)
3331 FIELD(TBFLAG_A64, TCMA, 16, 2)
3332 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3333 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3334 
3335 /**
3336  * cpu_mmu_index:
3337  * @env: The cpu environment
3338  * @ifetch: True for code access, false for data access.
3339  *
3340  * Return the core mmu index for the current translation regime.
3341  * This function is used by generic TCG code paths.
3342  */
3343 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3344 {
3345     return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX);
3346 }
3347 
3348 static inline bool bswap_code(bool sctlr_b)
3349 {
3350 #ifdef CONFIG_USER_ONLY
3351     /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
3352      * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
3353      * would also end up as a mixed-endian mode with BE code, LE data.
3354      */
3355     return
3356 #ifdef TARGET_WORDS_BIGENDIAN
3357         1 ^
3358 #endif
3359         sctlr_b;
3360 #else
3361     /* All code access in ARM is little endian, and there are no loaders
3362      * doing swaps that need to be reversed
3363      */
3364     return 0;
3365 #endif
3366 }
3367 
3368 #ifdef CONFIG_USER_ONLY
3369 static inline bool arm_cpu_bswap_data(CPUARMState *env)
3370 {
3371     return
3372 #ifdef TARGET_WORDS_BIGENDIAN
3373        1 ^
3374 #endif
3375        arm_cpu_data_is_big_endian(env);
3376 }
3377 #endif
3378 
3379 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3380                           target_ulong *cs_base, uint32_t *flags);
3381 
3382 enum {
3383     QEMU_PSCI_CONDUIT_DISABLED = 0,
3384     QEMU_PSCI_CONDUIT_SMC = 1,
3385     QEMU_PSCI_CONDUIT_HVC = 2,
3386 };
3387 
3388 #ifndef CONFIG_USER_ONLY
3389 /* Return the address space index to use for a memory access */
3390 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3391 {
3392     return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3393 }
3394 
3395 /* Return the AddressSpace to use for a memory access
3396  * (which depends on whether the access is S or NS, and whether
3397  * the board gave us a separate AddressSpace for S accesses).
3398  */
3399 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3400 {
3401     return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3402 }
3403 #endif
3404 
3405 /**
3406  * arm_register_pre_el_change_hook:
3407  * Register a hook function which will be called immediately before this
3408  * CPU changes exception level or mode. The hook function will be
3409  * passed a pointer to the ARMCPU and the opaque data pointer passed
3410  * to this function when the hook was registered.
3411  *
3412  * Note that if a pre-change hook is called, any registered post-change hooks
3413  * are guaranteed to subsequently be called.
3414  */
3415 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3416                                  void *opaque);
3417 /**
3418  * arm_register_el_change_hook:
3419  * Register a hook function which will be called immediately after this
3420  * CPU changes exception level or mode. The hook function will be
3421  * passed a pointer to the ARMCPU and the opaque data pointer passed
3422  * to this function when the hook was registered.
3423  *
3424  * Note that any registered hooks registered here are guaranteed to be called
3425  * if pre-change hooks have been.
3426  */
3427 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3428         *opaque);
3429 
3430 /**
3431  * arm_rebuild_hflags:
3432  * Rebuild the cached TBFLAGS for arbitrary changed processor state.
3433  */
3434 void arm_rebuild_hflags(CPUARMState *env);
3435 
3436 /**
3437  * aa32_vfp_dreg:
3438  * Return a pointer to the Dn register within env in 32-bit mode.
3439  */
3440 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3441 {
3442     return &env->vfp.zregs[regno >> 1].d[regno & 1];
3443 }
3444 
3445 /**
3446  * aa32_vfp_qreg:
3447  * Return a pointer to the Qn register within env in 32-bit mode.
3448  */
3449 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3450 {
3451     return &env->vfp.zregs[regno].d[0];
3452 }
3453 
3454 /**
3455  * aa64_vfp_qreg:
3456  * Return a pointer to the Qn register within env in 64-bit mode.
3457  */
3458 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3459 {
3460     return &env->vfp.zregs[regno].d[0];
3461 }
3462 
3463 /* Shared between translate-sve.c and sve_helper.c.  */
3464 extern const uint64_t pred_esz_masks[4];
3465 
3466 /* Helper for the macros below, validating the argument type. */
3467 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
3468 {
3469     return x;
3470 }
3471 
3472 /*
3473  * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB.
3474  * Using these should be a bit more self-documenting than using the
3475  * generic target bits directly.
3476  */
3477 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
3478 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
3479 
3480 /*
3481  * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
3482  */
3483 #define PAGE_BTI  PAGE_TARGET_1
3484 
3485 /*
3486  * Naming convention for isar_feature functions:
3487  * Functions which test 32-bit ID registers should have _aa32_ in
3488  * their name. Functions which test 64-bit ID registers should have
3489  * _aa64_ in their name. These must only be used in code where we
3490  * know for certain that the CPU has AArch32 or AArch64 respectively
3491  * or where the correct answer for a CPU which doesn't implement that
3492  * CPU state is "false" (eg when generating A32 or A64 code, if adding
3493  * system registers that are specific to that CPU state, for "should
3494  * we let this system register bit be set" tests where the 32-bit
3495  * flavour of the register doesn't have the bit, and so on).
3496  * Functions which simply ask "does this feature exist at all" have
3497  * _any_ in their name, and always return the logical OR of the _aa64_
3498  * and the _aa32_ function.
3499  */
3500 
3501 /*
3502  * 32-bit feature tests via id registers.
3503  */
3504 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
3505 {
3506     return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3507 }
3508 
3509 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
3510 {
3511     return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3512 }
3513 
3514 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
3515 {
3516     /* (M-profile) low-overhead loops and branch future */
3517     return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
3518 }
3519 
3520 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
3521 {
3522     return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3523 }
3524 
3525 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3526 {
3527     return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3528 }
3529 
3530 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3531 {
3532     return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3533 }
3534 
3535 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3536 {
3537     return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3538 }
3539 
3540 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3541 {
3542     return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3543 }
3544 
3545 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3546 {
3547     return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3548 }
3549 
3550 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3551 {
3552     return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3553 }
3554 
3555 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3556 {
3557     return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3558 }
3559 
3560 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
3561 {
3562     return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
3563 }
3564 
3565 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3566 {
3567     return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3568 }
3569 
3570 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
3571 {
3572     return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
3573 }
3574 
3575 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
3576 {
3577     return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
3578 }
3579 
3580 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
3581 {
3582     return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
3583 }
3584 
3585 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
3586 {
3587     return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
3588 }
3589 
3590 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
3591 {
3592     return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
3593 }
3594 
3595 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
3596 {
3597     /*
3598      * Return true if M-profile state handling insns
3599      * (VSCCLRM, CLRM, FPCTX access insns) are implemented
3600      */
3601     return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
3602 }
3603 
3604 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
3605 {
3606     /* Sadly this is encoded differently for A-profile and M-profile */
3607     if (isar_feature_aa32_mprofile(id)) {
3608         return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
3609     } else {
3610         return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
3611     }
3612 }
3613 
3614 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
3615 {
3616     /*
3617      * Return true if either VFP or SIMD is implemented.
3618      * In this case, a minimum of VFP w/ D0-D15.
3619      */
3620     return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
3621 }
3622 
3623 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
3624 {
3625     /* Return true if D16-D31 are implemented */
3626     return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
3627 }
3628 
3629 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3630 {
3631     return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
3632 }
3633 
3634 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
3635 {
3636     /* Return true if CPU supports single precision floating point, VFPv2 */
3637     return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
3638 }
3639 
3640 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
3641 {
3642     /* Return true if CPU supports single precision floating point, VFPv3 */
3643     return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
3644 }
3645 
3646 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
3647 {
3648     /* Return true if CPU supports double precision floating point, VFPv2 */
3649     return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
3650 }
3651 
3652 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
3653 {
3654     /* Return true if CPU supports double precision floating point, VFPv3 */
3655     return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
3656 }
3657 
3658 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
3659 {
3660     return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
3661 }
3662 
3663 /*
3664  * We always set the FP and SIMD FP16 fields to indicate identical
3665  * levels of support (assuming SIMD is implemented at all), so
3666  * we only need one set of accessors.
3667  */
3668 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
3669 {
3670     return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
3671 }
3672 
3673 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
3674 {
3675     return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
3676 }
3677 
3678 /*
3679  * Note that this ID register field covers both VFP and Neon FMAC,
3680  * so should usually be tested in combination with some other
3681  * check that confirms the presence of whichever of VFP or Neon is
3682  * relevant, to avoid accidentally enabling a Neon feature on
3683  * a VFP-no-Neon core or vice-versa.
3684  */
3685 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
3686 {
3687     return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
3688 }
3689 
3690 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
3691 {
3692     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
3693 }
3694 
3695 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
3696 {
3697     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
3698 }
3699 
3700 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
3701 {
3702     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
3703 }
3704 
3705 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
3706 {
3707     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
3708 }
3709 
3710 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
3711 {
3712     return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
3713 }
3714 
3715 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
3716 {
3717     return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
3718 }
3719 
3720 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
3721 {
3722     return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
3723 }
3724 
3725 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
3726 {
3727     /* 0xf means "non-standard IMPDEF PMU" */
3728     return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
3729         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3730 }
3731 
3732 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id)
3733 {
3734     /* 0xf means "non-standard IMPDEF PMU" */
3735     return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
3736         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3737 }
3738 
3739 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
3740 {
3741     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
3742 }
3743 
3744 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
3745 {
3746     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
3747 }
3748 
3749 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
3750 {
3751     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
3752 }
3753 
3754 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
3755 {
3756     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
3757 }
3758 
3759 /*
3760  * 64-bit feature tests via id registers.
3761  */
3762 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
3763 {
3764     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
3765 }
3766 
3767 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
3768 {
3769     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
3770 }
3771 
3772 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
3773 {
3774     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
3775 }
3776 
3777 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
3778 {
3779     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
3780 }
3781 
3782 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
3783 {
3784     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
3785 }
3786 
3787 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
3788 {
3789     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
3790 }
3791 
3792 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
3793 {
3794     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
3795 }
3796 
3797 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
3798 {
3799     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
3800 }
3801 
3802 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
3803 {
3804     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
3805 }
3806 
3807 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
3808 {
3809     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
3810 }
3811 
3812 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
3813 {
3814     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
3815 }
3816 
3817 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
3818 {
3819     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
3820 }
3821 
3822 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
3823 {
3824     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
3825 }
3826 
3827 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
3828 {
3829     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
3830 }
3831 
3832 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
3833 {
3834     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
3835 }
3836 
3837 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
3838 {
3839     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
3840 }
3841 
3842 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
3843 {
3844     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
3845 }
3846 
3847 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
3848 {
3849     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
3850 }
3851 
3852 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
3853 {
3854     /*
3855      * Note that while QEMU will only implement the architected algorithm
3856      * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation
3857      * defined algorithms, and thus API+GPI, and this predicate controls
3858      * migration of the 128-bit keys.
3859      */
3860     return (id->id_aa64isar1 &
3861             (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
3862              FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
3863              FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
3864              FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
3865 }
3866 
3867 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
3868 {
3869     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
3870 }
3871 
3872 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
3873 {
3874     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
3875 }
3876 
3877 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
3878 {
3879     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
3880 }
3881 
3882 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
3883 {
3884     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
3885 }
3886 
3887 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
3888 {
3889     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
3890 }
3891 
3892 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
3893 {
3894     /* We always set the AdvSIMD and FP fields identically.  */
3895     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
3896 }
3897 
3898 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
3899 {
3900     /* We always set the AdvSIMD and FP fields identically wrt FP16.  */
3901     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3902 }
3903 
3904 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
3905 {
3906     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
3907 }
3908 
3909 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
3910 {
3911     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
3912 }
3913 
3914 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
3915 {
3916     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
3917 }
3918 
3919 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
3920 {
3921     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
3922 }
3923 
3924 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
3925 {
3926     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
3927 }
3928 
3929 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
3930 {
3931     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
3932 }
3933 
3934 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
3935 {
3936     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
3937 }
3938 
3939 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
3940 {
3941     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
3942 }
3943 
3944 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
3945 {
3946     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
3947 }
3948 
3949 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
3950 {
3951     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
3952 }
3953 
3954 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
3955 {
3956     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
3957         FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
3958 }
3959 
3960 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
3961 {
3962     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
3963         FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
3964 }
3965 
3966 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
3967 {
3968     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
3969 }
3970 
3971 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
3972 {
3973     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
3974 }
3975 
3976 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
3977 {
3978     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
3979 }
3980 
3981 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
3982 {
3983     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
3984 }
3985 
3986 /*
3987  * Feature tests for "does this exist in either 32-bit or 64-bit?"
3988  */
3989 static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
3990 {
3991     return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
3992 }
3993 
3994 static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
3995 {
3996     return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
3997 }
3998 
3999 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id)
4000 {
4001     return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id);
4002 }
4003 
4004 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id)
4005 {
4006     return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id);
4007 }
4008 
4009 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
4010 {
4011     return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
4012 }
4013 
4014 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
4015 {
4016     return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
4017 }
4018 
4019 /*
4020  * Forward to the above feature tests given an ARMCPU pointer.
4021  */
4022 #define cpu_isar_feature(name, cpu) \
4023     ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
4024 
4025 #endif
4026