1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-common.h" 28 #include "exec/cpu-defs.h" 29 #include "exec/cpu-interrupt.h" 30 #include "exec/gdbstub.h" 31 #include "exec/page-protection.h" 32 #include "qapi/qapi-types-common.h" 33 #include "target/arm/multiprocessing.h" 34 #include "target/arm/gtimer.h" 35 #include "target/arm/cpu-sysregs.h" 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 61 #define EXCP_NMI 26 62 #define EXCP_VINMI 27 63 #define EXCP_VFNMI 28 64 #define EXCP_MON_TRAP 29 /* AArch32 trap to Monitor mode */ 65 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 66 67 #define ARMV7M_EXCP_RESET 1 68 #define ARMV7M_EXCP_NMI 2 69 #define ARMV7M_EXCP_HARD 3 70 #define ARMV7M_EXCP_MEM 4 71 #define ARMV7M_EXCP_BUS 5 72 #define ARMV7M_EXCP_USAGE 6 73 #define ARMV7M_EXCP_SECURE 7 74 #define ARMV7M_EXCP_SVC 11 75 #define ARMV7M_EXCP_DEBUG 12 76 #define ARMV7M_EXCP_PENDSV 14 77 #define ARMV7M_EXCP_SYSTICK 15 78 79 /* ARM-specific interrupt pending bits. */ 80 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 81 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 82 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 83 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 84 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4 85 #define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0 86 #define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1 87 88 /* The usual mapping for an AArch64 system register to its AArch32 89 * counterpart is for the 32 bit world to have access to the lower 90 * half only (with writes leaving the upper half untouched). It's 91 * therefore useful to be able to pass TCG the offset of the least 92 * significant half of a uint64_t struct member. 93 */ 94 #if HOST_BIG_ENDIAN 95 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 96 #define offsetofhigh32(S, M) offsetof(S, M) 97 #else 98 #define offsetoflow32(S, M) offsetof(S, M) 99 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 100 #endif 101 102 /* The 2nd extra word holding syndrome info for data aborts does not use 103 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 104 * help the sleb128 encoder do a better job. 105 * When restoring the CPU state, we shift it back up. 106 */ 107 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 108 #define ARM_INSN_START_WORD2_SHIFT 13 109 110 /* We currently assume float and double are IEEE single and double 111 precision respectively. 112 Doing runtime conversions is tricky because VFP registers may contain 113 integer values (eg. as the result of a FTOSI instruction). 114 s<2n> maps to the least significant half of d<n> 115 s<2n+1> maps to the most significant half of d<n> 116 */ 117 118 /** 119 * DynamicGDBFeatureInfo: 120 * @desc: Contains the feature descriptions. 121 * @data: A union with data specific to the set of registers 122 * @cpregs_keys: Array that contains the corresponding Key of 123 * a given cpreg with the same order of the cpreg 124 * in the XML description. 125 */ 126 typedef struct DynamicGDBFeatureInfo { 127 GDBFeature desc; 128 union { 129 struct { 130 uint32_t *keys; 131 } cpregs; 132 } data; 133 } DynamicGDBFeatureInfo; 134 135 /* CPU state for each instance of a generic timer (in cp15 c14) */ 136 typedef struct ARMGenericTimer { 137 uint64_t cval; /* Timer CompareValue register */ 138 uint64_t ctl; /* Timer Control register */ 139 } ARMGenericTimer; 140 141 /* Define a maximum sized vector register. 142 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 143 * For 64-bit, this is a 2048-bit SVE register. 144 * 145 * Note that the mapping between S, D, and Q views of the register bank 146 * differs between AArch64 and AArch32. 147 * In AArch32: 148 * Qn = regs[n].d[1]:regs[n].d[0] 149 * Dn = regs[n / 2].d[n & 1] 150 * Sn = regs[n / 4].d[n % 4 / 2], 151 * bits 31..0 for even n, and bits 63..32 for odd n 152 * (and regs[16] to regs[31] are inaccessible) 153 * In AArch64: 154 * Zn = regs[n].d[*] 155 * Qn = regs[n].d[1]:regs[n].d[0] 156 * Dn = regs[n].d[0] 157 * Sn = regs[n].d[0] bits 31..0 158 * Hn = regs[n].d[0] bits 15..0 159 * 160 * This corresponds to the architecturally defined mapping between 161 * the two execution states, and means we do not need to explicitly 162 * map these registers when changing states. 163 * 164 * Align the data for use with TCG host vector operations. 165 */ 166 167 #define ARM_MAX_VQ 16 168 169 typedef struct ARMVectorReg { 170 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 171 } ARMVectorReg; 172 173 /* In AArch32 mode, predicate registers do not exist at all. */ 174 typedef struct ARMPredicateReg { 175 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 176 } ARMPredicateReg; 177 178 /* In AArch32 mode, PAC keys do not exist at all. */ 179 typedef struct ARMPACKey { 180 uint64_t lo, hi; 181 } ARMPACKey; 182 183 /* See the commentary above the TBFLAG field definitions. */ 184 typedef struct CPUARMTBFlags { 185 uint32_t flags; 186 uint64_t flags2; 187 } CPUARMTBFlags; 188 189 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 190 191 typedef struct NVICState NVICState; 192 193 /* 194 * Enum for indexing vfp.fp_status[]. 195 * 196 * FPST_A32: is the "normal" fp status for AArch32 insns 197 * FPST_A64: is the "normal" fp status for AArch64 insns 198 * FPST_A32_F16: used for AArch32 half-precision calculations 199 * FPST_A64_F16: used for AArch64 half-precision calculations 200 * FPST_STD: the ARM "Standard FPSCR Value" 201 * FPST_STD_F16: used for half-precision 202 * calculations with the ARM "Standard FPSCR Value" 203 * FPST_AH: used for the A64 insns which change behaviour 204 * when FPCR.AH == 1 (bfloat16 conversions and multiplies, 205 * and the reciprocal and square root estimate/step insns) 206 * FPST_AH_F16: used for the A64 insns which change behaviour 207 * when FPCR.AH == 1 (bfloat16 conversions and multiplies, 208 * and the reciprocal and square root estimate/step insns); 209 * for half-precision 210 * 211 * Half-precision operations are governed by a separate 212 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 213 * status structure to control this. 214 * 215 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 216 * round-to-nearest and is used by any operations (generally 217 * Neon) which the architecture defines as controlled by the 218 * standard FPSCR value rather than the FPSCR. 219 * 220 * The "standard FPSCR but for fp16 ops" is needed because 221 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 222 * using a fixed value for it. 223 * 224 * FPST_AH is needed because some insns have different 225 * behaviour when FPCR.AH == 1: they don't update cumulative 226 * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and 227 * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16, 228 * which means we need an FPST_AH_F16 as well. 229 * 230 * To avoid having to transfer exception bits around, we simply 231 * say that the FPSCR cumulative exception flags are the logical 232 * OR of the flags in the four fp statuses. This relies on the 233 * only thing which needs to read the exception flags being 234 * an explicit FPSCR read. 235 */ 236 typedef enum ARMFPStatusFlavour { 237 FPST_A32, 238 FPST_A64, 239 FPST_A32_F16, 240 FPST_A64_F16, 241 FPST_AH, 242 FPST_AH_F16, 243 FPST_STD, 244 FPST_STD_F16, 245 } ARMFPStatusFlavour; 246 #define FPST_COUNT 8 247 248 typedef struct CPUArchState { 249 /* Regs for current mode. */ 250 uint32_t regs[16]; 251 252 /* 32/64 switch only happens when taking and returning from 253 * exceptions so the overlap semantics are taken care of then 254 * instead of having a complicated union. 255 */ 256 /* Regs for A64 mode. */ 257 uint64_t xregs[32]; 258 uint64_t pc; 259 /* PSTATE isn't an architectural register for ARMv8. However, it is 260 * convenient for us to assemble the underlying state into a 32 bit format 261 * identical to the architectural format used for the SPSR. (This is also 262 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 263 * 'pstate' register are.) Of the PSTATE bits: 264 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 265 * semantics as for AArch32, as described in the comments on each field) 266 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 267 * DAIF (exception masks) are kept in env->daif 268 * BTYPE is kept in env->btype 269 * SM and ZA are kept in env->svcr 270 * all other bits are stored in their correct places in env->pstate 271 */ 272 uint32_t pstate; 273 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 274 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 275 276 /* Cached TBFLAGS state. See below for which bits are included. */ 277 CPUARMTBFlags hflags; 278 279 /* Frequently accessed CPSR bits are stored separately for efficiency. 280 This contains all the other bits. Use cpsr_{read,write} to access 281 the whole CPSR. */ 282 uint32_t uncached_cpsr; 283 uint32_t spsr; 284 285 /* Banked registers. */ 286 uint64_t banked_spsr[8]; 287 uint32_t banked_r13[8]; 288 uint32_t banked_r14[8]; 289 290 /* These hold r8-r12. */ 291 uint32_t usr_regs[5]; 292 uint32_t fiq_regs[5]; 293 294 /* cpsr flag cache for faster execution */ 295 uint32_t CF; /* 0 or 1 */ 296 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 297 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 298 uint32_t ZF; /* Z set if zero. */ 299 uint32_t QF; /* 0 or 1 */ 300 uint32_t GE; /* cpsr[19:16] */ 301 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 302 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 303 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 304 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 305 306 uint64_t elr_el[4]; /* AArch64 exception link regs */ 307 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 308 309 /* System control coprocessor (cp15) */ 310 struct { 311 uint32_t c0_cpuid; 312 union { /* Cache size selection */ 313 struct { 314 uint64_t _unused_csselr0; 315 uint64_t csselr_ns; 316 uint64_t _unused_csselr1; 317 uint64_t csselr_s; 318 }; 319 uint64_t csselr_el[4]; 320 }; 321 union { /* System control register. */ 322 struct { 323 uint64_t _unused_sctlr; 324 uint64_t sctlr_ns; 325 uint64_t hsctlr; 326 uint64_t sctlr_s; 327 }; 328 uint64_t sctlr_el[4]; 329 }; 330 uint64_t vsctlr; /* Virtualization System control register. */ 331 uint64_t cpacr_el1; /* Architectural feature access control register */ 332 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 333 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 334 uint64_t sder; /* Secure debug enable register. */ 335 uint32_t nsacr; /* Non-secure access control register. */ 336 union { /* MMU translation table base 0. */ 337 struct { 338 uint64_t _unused_ttbr0_0; 339 uint64_t ttbr0_ns; 340 uint64_t _unused_ttbr0_1; 341 uint64_t ttbr0_s; 342 }; 343 uint64_t ttbr0_el[4]; 344 }; 345 union { /* MMU translation table base 1. */ 346 struct { 347 uint64_t _unused_ttbr1_0; 348 uint64_t ttbr1_ns; 349 uint64_t _unused_ttbr1_1; 350 uint64_t ttbr1_s; 351 }; 352 uint64_t ttbr1_el[4]; 353 }; 354 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 355 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 356 /* MMU translation table base control. */ 357 uint64_t tcr_el[4]; 358 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 359 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 360 uint32_t c2_data; /* MPU data cacheable bits. */ 361 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 362 union { /* MMU domain access control register 363 * MPU write buffer control. 364 */ 365 struct { 366 uint64_t dacr_ns; 367 uint64_t dacr_s; 368 }; 369 struct { 370 uint64_t dacr32_el2; 371 }; 372 }; 373 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 374 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 375 uint64_t hcr_el2; /* Hypervisor configuration register */ 376 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 377 uint64_t scr_el3; /* Secure configuration register. */ 378 union { /* Fault status registers. */ 379 struct { 380 uint64_t ifsr_ns; 381 uint64_t ifsr_s; 382 }; 383 struct { 384 uint64_t ifsr32_el2; 385 }; 386 }; 387 union { 388 struct { 389 uint64_t _unused_dfsr; 390 uint64_t dfsr_ns; 391 uint64_t hsr; 392 uint64_t dfsr_s; 393 }; 394 uint64_t esr_el[4]; 395 }; 396 uint32_t c6_region[8]; /* MPU base/size registers. */ 397 union { /* Fault address registers. */ 398 struct { 399 uint64_t _unused_far0; 400 #if HOST_BIG_ENDIAN 401 uint32_t ifar_ns; 402 uint32_t dfar_ns; 403 uint32_t ifar_s; 404 uint32_t dfar_s; 405 #else 406 uint32_t dfar_ns; 407 uint32_t ifar_ns; 408 uint32_t dfar_s; 409 uint32_t ifar_s; 410 #endif 411 uint64_t _unused_far3; 412 }; 413 uint64_t far_el[4]; 414 }; 415 uint64_t hpfar_el2; 416 uint64_t hstr_el2; 417 union { /* Translation result. */ 418 struct { 419 uint64_t _unused_par_0; 420 uint64_t par_ns; 421 uint64_t _unused_par_1; 422 uint64_t par_s; 423 }; 424 uint64_t par_el[4]; 425 }; 426 427 uint32_t c9_insn; /* Cache lockdown registers. */ 428 uint32_t c9_data; 429 uint64_t c9_pmcr; /* performance monitor control register */ 430 uint64_t c9_pmcnten; /* perf monitor counter enables */ 431 uint64_t c9_pmovsr; /* perf monitor overflow status */ 432 uint64_t c9_pmuserenr; /* perf monitor user enable */ 433 uint64_t c9_pmselr; /* perf monitor counter selection register */ 434 uint64_t c9_pminten; /* perf monitor interrupt enables */ 435 union { /* Memory attribute redirection */ 436 struct { 437 #if HOST_BIG_ENDIAN 438 uint64_t _unused_mair_0; 439 uint32_t mair1_ns; 440 uint32_t mair0_ns; 441 uint64_t _unused_mair_1; 442 uint32_t mair1_s; 443 uint32_t mair0_s; 444 #else 445 uint64_t _unused_mair_0; 446 uint32_t mair0_ns; 447 uint32_t mair1_ns; 448 uint64_t _unused_mair_1; 449 uint32_t mair0_s; 450 uint32_t mair1_s; 451 #endif 452 }; 453 uint64_t mair_el[4]; 454 }; 455 union { /* vector base address register */ 456 struct { 457 uint64_t _unused_vbar; 458 uint64_t vbar_ns; 459 uint64_t hvbar; 460 uint64_t vbar_s; 461 }; 462 uint64_t vbar_el[4]; 463 }; 464 uint32_t mvbar; /* (monitor) vector base address register */ 465 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 466 struct { /* FCSE PID. */ 467 uint32_t fcseidr_ns; 468 uint32_t fcseidr_s; 469 }; 470 union { /* Context ID. */ 471 struct { 472 uint64_t _unused_contextidr_0; 473 uint64_t contextidr_ns; 474 uint64_t _unused_contextidr_1; 475 uint64_t contextidr_s; 476 }; 477 uint64_t contextidr_el[4]; 478 }; 479 union { /* User RW Thread register. */ 480 struct { 481 uint64_t tpidrurw_ns; 482 uint64_t tpidrprw_ns; 483 uint64_t htpidr; 484 uint64_t _tpidr_el3; 485 }; 486 uint64_t tpidr_el[4]; 487 }; 488 uint64_t tpidr2_el0; 489 /* The secure banks of these registers don't map anywhere */ 490 uint64_t tpidrurw_s; 491 uint64_t tpidrprw_s; 492 uint64_t tpidruro_s; 493 494 union { /* User RO Thread register. */ 495 uint64_t tpidruro_ns; 496 uint64_t tpidrro_el[1]; 497 }; 498 uint64_t c14_cntfrq; /* Counter Frequency register */ 499 uint64_t c14_cntkctl; /* Timer Control register */ 500 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 501 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 502 uint64_t cntpoff_el2; /* Counter Physical Offset register */ 503 ARMGenericTimer c14_timer[NUM_GTIMERS]; 504 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 505 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 506 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 507 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 508 uint32_t c15_threadid; /* TI debugger thread-ID. */ 509 uint32_t c15_config_base_address; /* SCU base address. */ 510 uint32_t c15_diagnostic; /* diagnostic register */ 511 uint32_t c15_power_diagnostic; 512 uint32_t c15_power_control; /* power control */ 513 uint64_t dbgbvr[16]; /* breakpoint value registers */ 514 uint64_t dbgbcr[16]; /* breakpoint control registers */ 515 uint64_t dbgwvr[16]; /* watchpoint value registers */ 516 uint64_t dbgwcr[16]; /* watchpoint control registers */ 517 uint64_t dbgclaim; /* DBGCLAIM bits */ 518 uint64_t mdscr_el1; 519 uint64_t oslsr_el1; /* OS Lock Status */ 520 uint64_t osdlr_el1; /* OS DoubleLock status */ 521 uint64_t mdcr_el2; 522 uint64_t mdcr_el3; 523 /* Stores the architectural value of the counter *the last time it was 524 * updated* by pmccntr_op_start. Accesses should always be surrounded 525 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 526 * architecturally-correct value is being read/set. 527 */ 528 uint64_t c15_ccnt; 529 /* Stores the delta between the architectural value and the underlying 530 * cycle count during normal operation. It is used to update c15_ccnt 531 * to be the correct architectural value before accesses. During 532 * accesses, c15_ccnt_delta contains the underlying count being used 533 * for the access, after which it reverts to the delta value in 534 * pmccntr_op_finish. 535 */ 536 uint64_t c15_ccnt_delta; 537 uint64_t c14_pmevcntr[31]; 538 uint64_t c14_pmevcntr_delta[31]; 539 uint64_t c14_pmevtyper[31]; 540 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 541 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 542 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 543 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 544 uint64_t gcr_el1; 545 uint64_t rgsr_el1; 546 547 /* Minimal RAS registers */ 548 uint64_t disr_el1; 549 uint64_t vdisr_el2; 550 uint64_t vsesr_el2; 551 552 /* 553 * Fine-Grained Trap registers. We store these as arrays so the 554 * access checking code doesn't have to manually select 555 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 556 * FEAT_FGT2 will add more elements to these arrays. 557 */ 558 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 559 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 560 uint64_t fgt_exec[1]; /* HFGITR */ 561 562 /* RME registers */ 563 uint64_t gpccr_el3; 564 uint64_t gptbr_el3; 565 uint64_t mfar_el3; 566 567 /* NV2 register */ 568 uint64_t vncr_el2; 569 } cp15; 570 571 struct { 572 /* M profile has up to 4 stack pointers: 573 * a Main Stack Pointer and a Process Stack Pointer for each 574 * of the Secure and Non-Secure states. (If the CPU doesn't support 575 * the security extension then it has only two SPs.) 576 * In QEMU we always store the currently active SP in regs[13], 577 * and the non-active SP for the current security state in 578 * v7m.other_sp. The stack pointers for the inactive security state 579 * are stored in other_ss_msp and other_ss_psp. 580 * switch_v7m_security_state() is responsible for rearranging them 581 * when we change security state. 582 */ 583 uint32_t other_sp; 584 uint32_t other_ss_msp; 585 uint32_t other_ss_psp; 586 uint32_t vecbase[M_REG_NUM_BANKS]; 587 uint32_t basepri[M_REG_NUM_BANKS]; 588 uint32_t control[M_REG_NUM_BANKS]; 589 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 590 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 591 uint32_t hfsr; /* HardFault Status */ 592 uint32_t dfsr; /* Debug Fault Status Register */ 593 uint32_t sfsr; /* Secure Fault Status Register */ 594 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 595 uint32_t bfar; /* BusFault Address */ 596 uint32_t sfar; /* Secure Fault Address Register */ 597 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 598 int exception; 599 uint32_t primask[M_REG_NUM_BANKS]; 600 uint32_t faultmask[M_REG_NUM_BANKS]; 601 uint32_t aircr; /* only holds r/w state if security extn implemented */ 602 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 603 uint32_t csselr[M_REG_NUM_BANKS]; 604 uint32_t scr[M_REG_NUM_BANKS]; 605 uint32_t msplim[M_REG_NUM_BANKS]; 606 uint32_t psplim[M_REG_NUM_BANKS]; 607 uint32_t fpcar[M_REG_NUM_BANKS]; 608 uint32_t fpccr[M_REG_NUM_BANKS]; 609 uint32_t fpdscr[M_REG_NUM_BANKS]; 610 uint32_t cpacr[M_REG_NUM_BANKS]; 611 uint32_t nsacr; 612 uint32_t ltpsize; 613 uint32_t vpr; 614 } v7m; 615 616 /* Information associated with an exception about to be taken: 617 * code which raises an exception must set cs->exception_index and 618 * the relevant parts of this structure; the cpu_do_interrupt function 619 * will then set the guest-visible registers as part of the exception 620 * entry process. 621 */ 622 struct { 623 uint32_t syndrome; /* AArch64 format syndrome register */ 624 uint32_t fsr; /* AArch32 format fault status register info */ 625 uint64_t vaddress; /* virtual addr associated with exception, if any */ 626 uint32_t target_el; /* EL the exception should be targeted for */ 627 /* If we implement EL2 we will also need to store information 628 * about the intermediate physical address for stage 2 faults. 629 */ 630 } exception; 631 632 /* Information associated with an SError */ 633 struct { 634 uint8_t pending; 635 uint8_t has_esr; 636 uint64_t esr; 637 } serror; 638 639 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 640 641 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 642 uint32_t irq_line_state; 643 644 /* Thumb-2 EE state. */ 645 uint32_t teecr; 646 uint32_t teehbr; 647 648 /* VFP coprocessor state. */ 649 struct { 650 ARMVectorReg zregs[32]; 651 652 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 653 #define FFR_PRED_NUM 16 654 ARMPredicateReg pregs[17]; 655 /* Scratch space for aa64 sve predicate temporary. */ 656 ARMPredicateReg preg_tmp; 657 658 /* We store these fpcsr fields separately for convenience. */ 659 uint32_t qc[4] QEMU_ALIGNED(16); 660 int vec_len; 661 int vec_stride; 662 663 /* 664 * Floating point status and control registers. Some bits are 665 * stored separately in other fields or in the float_status below. 666 */ 667 uint64_t fpsr; 668 uint64_t fpcr; 669 670 uint32_t xregs[16]; 671 672 /* Scratch space for aa32 neon expansion. */ 673 uint32_t scratch[8]; 674 675 /* There are a number of distinct float control structures. */ 676 float_status fp_status[FPST_COUNT]; 677 678 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 679 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 680 } vfp; 681 682 uint64_t exclusive_addr; 683 uint64_t exclusive_val; 684 /* 685 * Contains the 'val' for the second 64-bit register of LDXP, which comes 686 * from the higher address, not the high part of a complete 128-bit value. 687 * In some ways it might be more convenient to record the exclusive value 688 * as the low and high halves of a 128 bit data value, but the current 689 * semantics of these fields are baked into the migration format. 690 */ 691 uint64_t exclusive_high; 692 693 /* iwMMXt coprocessor state. */ 694 struct { 695 uint64_t regs[16]; 696 uint64_t val; 697 698 uint32_t cregs[16]; 699 } iwmmxt; 700 701 struct { 702 ARMPACKey apia; 703 ARMPACKey apib; 704 ARMPACKey apda; 705 ARMPACKey apdb; 706 ARMPACKey apga; 707 } keys; 708 709 uint64_t scxtnum_el[4]; 710 711 /* 712 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 713 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 714 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 715 * When SVL is less than the architectural maximum, the accessible 716 * storage is restricted, such that if the SVL is X bytes the guest can 717 * see only the bottom X elements of zarray[], and only the least 718 * significant X bytes of each element of the array. (In other words, 719 * the observable part is always square.) 720 * 721 * The ZA storage can also be considered as a set of square tiles of 722 * elements of different sizes. The mapping from tiles to the ZA array 723 * is architecturally defined, such that for tiles of elements of esz 724 * bytes, the Nth row (or "horizontal slice") of tile T is in 725 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 726 * in the ZA storage, because its rows are striped through the ZA array. 727 * 728 * Because this is so large, keep this toward the end of the reset area, 729 * to keep the offsets into the rest of the structure smaller. 730 */ 731 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 732 733 struct CPUBreakpoint *cpu_breakpoint[16]; 734 struct CPUWatchpoint *cpu_watchpoint[16]; 735 736 /* Optional fault info across tlb lookup. */ 737 ARMMMUFaultInfo *tlb_fi; 738 739 /* Fields up to this point are cleared by a CPU reset */ 740 struct {} end_reset_fields; 741 742 /* Fields after this point are preserved across CPU reset. */ 743 744 /* Internal CPU feature flags. */ 745 uint64_t features; 746 747 /* PMSAv7 MPU */ 748 struct { 749 uint32_t *drbar; 750 uint32_t *drsr; 751 uint32_t *dracr; 752 uint32_t rnr[M_REG_NUM_BANKS]; 753 } pmsav7; 754 755 /* PMSAv8 MPU */ 756 struct { 757 /* The PMSAv8 implementation also shares some PMSAv7 config 758 * and state: 759 * pmsav7.rnr (region number register) 760 * pmsav7_dregion (number of configured regions) 761 */ 762 uint32_t *rbar[M_REG_NUM_BANKS]; 763 uint32_t *rlar[M_REG_NUM_BANKS]; 764 uint32_t *hprbar; 765 uint32_t *hprlar; 766 uint32_t mair0[M_REG_NUM_BANKS]; 767 uint32_t mair1[M_REG_NUM_BANKS]; 768 uint32_t hprselr; 769 } pmsav8; 770 771 /* v8M SAU */ 772 struct { 773 uint32_t *rbar; 774 uint32_t *rlar; 775 uint32_t rnr; 776 uint32_t ctrl; 777 } sau; 778 779 #if !defined(CONFIG_USER_ONLY) 780 NVICState *nvic; 781 const struct arm_boot_info *boot_info; 782 /* Store GICv3CPUState to access from this struct */ 783 void *gicv3state; 784 #else /* CONFIG_USER_ONLY */ 785 /* For usermode syscall translation. */ 786 bool eabi; 787 /* Linux syscall tagged address support */ 788 bool tagged_addr_enable; 789 #endif /* CONFIG_USER_ONLY */ 790 } CPUARMState; 791 792 static inline void set_feature(CPUARMState *env, int feature) 793 { 794 env->features |= 1ULL << feature; 795 } 796 797 static inline void unset_feature(CPUARMState *env, int feature) 798 { 799 env->features &= ~(1ULL << feature); 800 } 801 802 /** 803 * ARMELChangeHookFn: 804 * type of a function which can be registered via arm_register_el_change_hook() 805 * to get callbacks when the CPU changes its exception level or mode. 806 */ 807 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 808 typedef struct ARMELChangeHook ARMELChangeHook; 809 struct ARMELChangeHook { 810 ARMELChangeHookFn *hook; 811 void *opaque; 812 QLIST_ENTRY(ARMELChangeHook) node; 813 }; 814 815 /* These values map onto the return values for 816 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 817 typedef enum ARMPSCIState { 818 PSCI_ON = 0, 819 PSCI_OFF = 1, 820 PSCI_ON_PENDING = 2 821 } ARMPSCIState; 822 823 typedef struct ARMISARegisters ARMISARegisters; 824 825 /* 826 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 827 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 828 * 829 * While processing properties during initialization, corresponding init bits 830 * are set for bits in sve_vq_map that have been set by properties. 831 * 832 * Bits set in supported represent valid vector lengths for the CPU type. 833 */ 834 typedef struct { 835 uint32_t map, init, supported; 836 } ARMVQMap; 837 838 /* REG is ID_XXX */ 839 #define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \ 840 ({ \ 841 ARMISARegisters *i_ = (ISAR); \ 842 uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \ 843 regval = FIELD_DP64(regval, REG, FIELD, VALUE); \ 844 i_->idregs[REG ## _EL1_IDX] = regval; \ 845 }) 846 847 #define FIELD_DP32_IDREG(ISAR, REG, FIELD, VALUE) \ 848 ({ \ 849 ARMISARegisters *i_ = (ISAR); \ 850 uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \ 851 regval = FIELD_DP32(regval, REG, FIELD, VALUE); \ 852 i_->idregs[REG ## _EL1_IDX] = regval; \ 853 }) 854 855 #define FIELD_EX64_IDREG(ISAR, REG, FIELD) \ 856 ({ \ 857 const ARMISARegisters *i_ = (ISAR); \ 858 FIELD_EX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ 859 }) 860 861 #define FIELD_EX32_IDREG(ISAR, REG, FIELD) \ 862 ({ \ 863 const ARMISARegisters *i_ = (ISAR); \ 864 FIELD_EX32(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ 865 }) 866 867 #define FIELD_SEX64_IDREG(ISAR, REG, FIELD) \ 868 ({ \ 869 const ARMISARegisters *i_ = (ISAR); \ 870 FIELD_SEX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ 871 }) 872 873 #define SET_IDREG(ISAR, REG, VALUE) \ 874 ({ \ 875 ARMISARegisters *i_ = (ISAR); \ 876 i_->idregs[REG ## _EL1_IDX] = VALUE; \ 877 }) 878 879 #define GET_IDREG(ISAR, REG) \ 880 ({ \ 881 const ARMISARegisters *i_ = (ISAR); \ 882 i_->idregs[REG ## _EL1_IDX]; \ 883 }) 884 885 /** 886 * ARMCPU: 887 * @env: #CPUARMState 888 * 889 * An ARM CPU core. 890 */ 891 struct ArchCPU { 892 CPUState parent_obj; 893 894 CPUARMState env; 895 896 /* Coprocessor information */ 897 GHashTable *cp_regs; 898 /* For marshalling (mostly coprocessor) register state between the 899 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 900 * we use these arrays. 901 */ 902 /* List of register indexes managed via these arrays; (full KVM style 903 * 64 bit indexes, not CPRegInfo 32 bit indexes) 904 */ 905 uint64_t *cpreg_indexes; 906 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 907 uint64_t *cpreg_values; 908 /* Length of the indexes, values, reset_values arrays */ 909 int32_t cpreg_array_len; 910 /* These are used only for migration: incoming data arrives in 911 * these fields and is sanity checked in post_load before copying 912 * to the working data structures above. 913 */ 914 uint64_t *cpreg_vmstate_indexes; 915 uint64_t *cpreg_vmstate_values; 916 int32_t cpreg_vmstate_array_len; 917 918 DynamicGDBFeatureInfo dyn_sysreg_feature; 919 DynamicGDBFeatureInfo dyn_svereg_feature; 920 DynamicGDBFeatureInfo dyn_m_systemreg_feature; 921 DynamicGDBFeatureInfo dyn_m_secextreg_feature; 922 923 /* Timers used by the generic (architected) timer */ 924 QEMUTimer *gt_timer[NUM_GTIMERS]; 925 /* 926 * Timer used by the PMU. Its state is restored after migration by 927 * pmu_op_finish() - it does not need other handling during migration 928 */ 929 QEMUTimer *pmu_timer; 930 /* Timer used for WFxT timeouts */ 931 QEMUTimer *wfxt_timer; 932 933 /* GPIO outputs for generic timer */ 934 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 935 /* GPIO output for GICv3 maintenance interrupt signal */ 936 qemu_irq gicv3_maintenance_interrupt; 937 /* GPIO output for the PMU interrupt */ 938 qemu_irq pmu_interrupt; 939 940 /* MemoryRegion to use for secure physical accesses */ 941 MemoryRegion *secure_memory; 942 943 /* MemoryRegion to use for allocation tag accesses */ 944 MemoryRegion *tag_memory; 945 MemoryRegion *secure_tag_memory; 946 947 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 948 Object *idau; 949 950 /* 'compatible' string for this CPU for Linux device trees */ 951 const char *dtb_compatible; 952 953 /* PSCI version for this CPU 954 * Bits[31:16] = Major Version 955 * Bits[15:0] = Minor Version 956 */ 957 uint32_t psci_version; 958 959 /* Current power state, access guarded by BQL */ 960 ARMPSCIState power_state; 961 962 /* CPU has virtualization extension */ 963 bool has_el2; 964 /* CPU has security extension */ 965 bool has_el3; 966 /* CPU has PMU (Performance Monitor Unit) */ 967 bool has_pmu; 968 /* CPU has VFP */ 969 bool has_vfp; 970 /* CPU has 32 VFP registers */ 971 bool has_vfp_d32; 972 /* CPU has Neon */ 973 bool has_neon; 974 /* CPU has M-profile DSP extension */ 975 bool has_dsp; 976 977 /* CPU has memory protection unit */ 978 bool has_mpu; 979 /* CPU has MTE enabled in KVM mode */ 980 bool kvm_mte; 981 /* PMSAv7 MPU number of supported regions */ 982 uint32_t pmsav7_dregion; 983 /* PMSAv8 MPU number of supported hyp regions */ 984 uint32_t pmsav8r_hdregion; 985 /* v8M SAU number of supported regions */ 986 uint32_t sau_sregion; 987 988 /* PSCI conduit used to invoke PSCI methods 989 * 0 - disabled, 1 - smc, 2 - hvc 990 */ 991 uint32_t psci_conduit; 992 993 /* For v8M, initial value of the Secure VTOR */ 994 uint32_t init_svtor; 995 /* For v8M, initial value of the Non-secure VTOR */ 996 uint32_t init_nsvtor; 997 998 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 999 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 1000 */ 1001 uint32_t kvm_target; 1002 1003 /* KVM init features for this CPU */ 1004 uint32_t kvm_init_features[7]; 1005 1006 /* KVM CPU state */ 1007 1008 /* KVM virtual time adjustment */ 1009 bool kvm_adjvtime; 1010 bool kvm_vtime_dirty; 1011 uint64_t kvm_vtime; 1012 1013 /* KVM steal time */ 1014 OnOffAuto kvm_steal_time; 1015 1016 /* Uniprocessor system with MP extensions */ 1017 bool mp_is_up; 1018 1019 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 1020 * and the probe failed (so we need to report the error in realize) 1021 */ 1022 bool host_cpu_probe_failed; 1023 1024 /* QOM property to indicate we should use the back-compat CNTFRQ default */ 1025 bool backcompat_cntfrq; 1026 1027 /* QOM property to indicate we should use the back-compat QARMA5 default */ 1028 bool backcompat_pauth_default_use_qarma5; 1029 1030 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 1031 * register. 1032 */ 1033 int32_t core_count; 1034 1035 /* The instance init functions for implementation-specific subclasses 1036 * set these fields to specify the implementation-dependent values of 1037 * various constant registers and reset values of non-constant 1038 * registers. 1039 * Some of these might become QOM properties eventually. 1040 * Field names match the official register names as defined in the 1041 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 1042 * is used for reset values of non-constant registers; no reset_ 1043 * prefix means a constant register. 1044 * Some of these registers are split out into a substructure that 1045 * is shared with the translators to control the ISA. 1046 * 1047 * Note that if you add an ID register to the ARMISARegisters struct 1048 * you need to also update the 32-bit and 64-bit versions of the 1049 * kvm_arm_get_host_cpu_features() function to correctly populate the 1050 * field by reading the value from the KVM vCPU. 1051 */ 1052 struct ARMISARegisters { 1053 uint32_t id_mmfr0; 1054 uint32_t id_mmfr1; 1055 uint32_t id_mmfr2; 1056 uint32_t id_mmfr3; 1057 uint32_t id_mmfr4; 1058 uint32_t id_mmfr5; 1059 uint32_t id_pfr0; 1060 uint32_t id_pfr1; 1061 uint32_t id_pfr2; 1062 uint32_t mvfr0; 1063 uint32_t mvfr1; 1064 uint32_t mvfr2; 1065 uint32_t id_dfr0; 1066 uint32_t id_dfr1; 1067 uint32_t dbgdidr; 1068 uint32_t dbgdevid; 1069 uint32_t dbgdevid1; 1070 uint64_t reset_pmcr_el0; 1071 uint64_t idregs[NUM_ID_IDX]; 1072 } isar; 1073 uint64_t midr; 1074 uint32_t revidr; 1075 uint32_t reset_fpsid; 1076 uint64_t ctr; 1077 uint32_t reset_sctlr; 1078 uint64_t pmceid0; 1079 uint64_t pmceid1; 1080 uint32_t id_afr0; 1081 uint64_t id_aa64afr0; 1082 uint64_t id_aa64afr1; 1083 uint64_t clidr; 1084 uint64_t mp_affinity; /* MP ID without feature bits */ 1085 /* The elements of this array are the CCSIDR values for each cache, 1086 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1087 */ 1088 uint64_t ccsidr[16]; 1089 uint64_t reset_cbar; 1090 uint32_t reset_auxcr; 1091 bool reset_hivecs; 1092 uint8_t reset_l0gptsz; 1093 1094 /* 1095 * Intermediate values used during property parsing. 1096 * Once finalized, the values should be read from ID_AA64*. 1097 */ 1098 bool prop_pauth; 1099 bool prop_pauth_impdef; 1100 bool prop_pauth_qarma3; 1101 bool prop_pauth_qarma5; 1102 bool prop_lpa2; 1103 1104 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1105 uint8_t dcz_blocksize; 1106 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1107 uint8_t gm_blocksize; 1108 1109 uint64_t rvbar_prop; /* Property/input signals. */ 1110 1111 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1112 int gic_num_lrs; /* number of list registers */ 1113 int gic_vpribits; /* number of virtual priority bits */ 1114 int gic_vprebits; /* number of virtual preemption bits */ 1115 int gic_pribits; /* number of physical priority bits */ 1116 1117 /* Whether the cfgend input is high (i.e. this CPU should reset into 1118 * big-endian mode). This setting isn't used directly: instead it modifies 1119 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1120 * architecture version. 1121 */ 1122 bool cfgend; 1123 1124 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1125 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1126 1127 int32_t node_id; /* NUMA node this CPU belongs to */ 1128 1129 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1130 uint8_t device_irq_level; 1131 1132 /* Used to set the maximum vector length the cpu will support. */ 1133 uint32_t sve_max_vq; 1134 1135 #ifdef CONFIG_USER_ONLY 1136 /* Used to set the default vector length at process start. */ 1137 uint32_t sve_default_vq; 1138 uint32_t sme_default_vq; 1139 #endif 1140 1141 ARMVQMap sve_vq; 1142 ARMVQMap sme_vq; 1143 1144 /* Generic timer counter frequency, in Hz */ 1145 uint64_t gt_cntfrq_hz; 1146 }; 1147 1148 typedef struct ARMCPUInfo { 1149 const char *name; 1150 const char *deprecation_note; 1151 void (*initfn)(Object *obj); 1152 void (*class_init)(ObjectClass *oc, const void *data); 1153 } ARMCPUInfo; 1154 1155 /** 1156 * ARMCPUClass: 1157 * @parent_realize: The parent class' realize handler. 1158 * @parent_phases: The parent class' reset phase handlers. 1159 * 1160 * An ARM CPU model. 1161 */ 1162 struct ARMCPUClass { 1163 CPUClass parent_class; 1164 1165 const ARMCPUInfo *info; 1166 DeviceRealize parent_realize; 1167 ResettablePhases parent_phases; 1168 }; 1169 1170 /* Callback functions for the generic timer's timers. */ 1171 void arm_gt_ptimer_cb(void *opaque); 1172 void arm_gt_vtimer_cb(void *opaque); 1173 void arm_gt_htimer_cb(void *opaque); 1174 void arm_gt_stimer_cb(void *opaque); 1175 void arm_gt_hvtimer_cb(void *opaque); 1176 void arm_gt_sel2timer_cb(void *opaque); 1177 void arm_gt_sel2vtimer_cb(void *opaque); 1178 1179 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1180 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1181 1182 void arm_cpu_post_init(Object *obj); 1183 1184 #define ARM_AFF0_SHIFT 0 1185 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1186 #define ARM_AFF1_SHIFT 8 1187 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1188 #define ARM_AFF2_SHIFT 16 1189 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1190 #define ARM_AFF3_SHIFT 32 1191 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1192 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1193 1194 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1195 #define ARM64_AFFINITY_MASK \ 1196 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1197 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1198 1199 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1200 1201 #ifndef CONFIG_USER_ONLY 1202 extern const VMStateDescription vmstate_arm_cpu; 1203 1204 void arm_cpu_do_interrupt(CPUState *cpu); 1205 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1206 1207 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1208 MemTxAttrs *attrs); 1209 #endif /* !CONFIG_USER_ONLY */ 1210 1211 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1212 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1213 1214 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1215 int cpuid, DumpState *s); 1216 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1217 int cpuid, DumpState *s); 1218 1219 /** 1220 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1221 * @cpu: CPU (which must have been freshly reset) 1222 * @target_el: exception level to put the CPU into 1223 * @secure: whether to put the CPU in secure state 1224 * 1225 * When QEMU is directly running a guest kernel at a lower level than 1226 * EL3 it implicitly emulates some aspects of the guest firmware. 1227 * This includes that on reset we need to configure the parts of the 1228 * CPU corresponding to EL3 so that the real guest code can run at its 1229 * lower exception level. This function does that post-reset CPU setup, 1230 * for when we do direct boot of a guest kernel, and for when we 1231 * emulate PSCI and similar firmware interfaces starting a CPU at a 1232 * lower exception level. 1233 * 1234 * @target_el must be an EL implemented by the CPU between 1 and 3. 1235 * We do not support dropping into a Secure EL other than 3. 1236 * 1237 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1238 */ 1239 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1240 1241 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1242 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1243 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1244 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1245 int new_el, bool el0_a64); 1246 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1247 1248 /* 1249 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1250 * The byte at offset i from the start of the in-memory representation contains 1251 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1252 * lowest offsets are stored in the lowest memory addresses, then that nearly 1253 * matches QEMU's representation, which is to use an array of host-endian 1254 * uint64_t's, where the lower offsets are at the lower indices. To complete 1255 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1256 */ 1257 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1258 { 1259 #if HOST_BIG_ENDIAN 1260 int i; 1261 1262 for (i = 0; i < nr; ++i) { 1263 dst[i] = bswap64(src[i]); 1264 } 1265 1266 return dst; 1267 #else 1268 return src; 1269 #endif 1270 } 1271 1272 void aarch64_sync_32_to_64(CPUARMState *env); 1273 void aarch64_sync_64_to_32(CPUARMState *env); 1274 1275 int fp_exception_el(CPUARMState *env, int cur_el); 1276 int sve_exception_el(CPUARMState *env, int cur_el); 1277 int sme_exception_el(CPUARMState *env, int cur_el); 1278 1279 /** 1280 * sve_vqm1_for_el_sm: 1281 * @env: CPUARMState 1282 * @el: exception level 1283 * @sm: streaming mode 1284 * 1285 * Compute the current vector length for @el & @sm, in units of 1286 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1287 * If @sm, compute for SVL, otherwise NVL. 1288 */ 1289 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1290 1291 /* Likewise, but using @sm = PSTATE.SM. */ 1292 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1293 1294 static inline bool is_a64(CPUARMState *env) 1295 { 1296 return env->aarch64; 1297 } 1298 1299 /** 1300 * pmu_op_start/finish 1301 * @env: CPUARMState 1302 * 1303 * Convert all PMU counters between their delta form (the typical mode when 1304 * they are enabled) and the guest-visible values. These two calls must 1305 * surround any action which might affect the counters. 1306 */ 1307 void pmu_op_start(CPUARMState *env); 1308 void pmu_op_finish(CPUARMState *env); 1309 1310 /* 1311 * Called when a PMU counter is due to overflow 1312 */ 1313 void arm_pmu_timer_cb(void *opaque); 1314 1315 /** 1316 * Functions to register as EL change hooks for PMU mode filtering 1317 */ 1318 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1319 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1320 1321 /* 1322 * pmu_init 1323 * @cpu: ARMCPU 1324 * 1325 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1326 * for the current configuration 1327 */ 1328 void pmu_init(ARMCPU *cpu); 1329 1330 /* SCTLR bit meanings. Several bits have been reused in newer 1331 * versions of the architecture; in that case we define constants 1332 * for both old and new bit meanings. Code which tests against those 1333 * bits should probably check or otherwise arrange that the CPU 1334 * is the architectural version it expects. 1335 */ 1336 #define SCTLR_M (1U << 0) 1337 #define SCTLR_A (1U << 1) 1338 #define SCTLR_C (1U << 2) 1339 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1340 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1341 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1342 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1343 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1344 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1345 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1346 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1347 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1348 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1349 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1350 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1351 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1352 #define SCTLR_SED (1U << 8) /* v8 onward */ 1353 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1354 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1355 #define SCTLR_F (1U << 10) /* up to v6 */ 1356 #define SCTLR_SW (1U << 10) /* v7 */ 1357 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1358 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1359 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1360 #define SCTLR_I (1U << 12) 1361 #define SCTLR_V (1U << 13) /* AArch32 only */ 1362 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1363 #define SCTLR_RR (1U << 14) /* up to v7 */ 1364 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1365 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1366 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1367 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1368 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1369 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1370 #define SCTLR_BR (1U << 17) /* PMSA only */ 1371 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1372 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1373 #define SCTLR_WXN (1U << 19) 1374 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1375 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1376 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1377 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1378 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1379 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1380 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1381 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1382 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1383 #define SCTLR_VE (1U << 24) /* up to v7 */ 1384 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1385 #define SCTLR_EE (1U << 25) 1386 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1387 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1388 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1389 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1390 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1391 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1392 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1393 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1394 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1395 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1396 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1397 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1398 #define SCTLR_CMOW (1ULL << 32) /* FEAT_CMOW */ 1399 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1400 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1401 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1402 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1403 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1404 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1405 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1406 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1407 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1408 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1409 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1410 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1411 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1412 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1413 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1414 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1415 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1416 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1417 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1418 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1419 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1420 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1421 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1422 1423 #define CPSR_M (0x1fU) 1424 #define CPSR_T (1U << 5) 1425 #define CPSR_F (1U << 6) 1426 #define CPSR_I (1U << 7) 1427 #define CPSR_A (1U << 8) 1428 #define CPSR_E (1U << 9) 1429 #define CPSR_IT_2_7 (0xfc00U) 1430 #define CPSR_GE (0xfU << 16) 1431 #define CPSR_IL (1U << 20) 1432 #define CPSR_DIT (1U << 21) 1433 #define CPSR_PAN (1U << 22) 1434 #define CPSR_SSBS (1U << 23) 1435 #define CPSR_J (1U << 24) 1436 #define CPSR_IT_0_1 (3U << 25) 1437 #define CPSR_Q (1U << 27) 1438 #define CPSR_V (1U << 28) 1439 #define CPSR_C (1U << 29) 1440 #define CPSR_Z (1U << 30) 1441 #define CPSR_N (1U << 31) 1442 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1443 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1444 #define ISR_FS (1U << 9) 1445 #define ISR_IS (1U << 10) 1446 1447 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1448 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1449 | CPSR_NZCV) 1450 /* Bits writable in user mode. */ 1451 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1452 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1453 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1454 1455 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1456 #define XPSR_EXCP 0x1ffU 1457 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1458 #define XPSR_IT_2_7 CPSR_IT_2_7 1459 #define XPSR_GE CPSR_GE 1460 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1461 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1462 #define XPSR_IT_0_1 CPSR_IT_0_1 1463 #define XPSR_Q CPSR_Q 1464 #define XPSR_V CPSR_V 1465 #define XPSR_C CPSR_C 1466 #define XPSR_Z CPSR_Z 1467 #define XPSR_N CPSR_N 1468 #define XPSR_NZCV CPSR_NZCV 1469 #define XPSR_IT CPSR_IT 1470 1471 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1472 * Only these are valid when in AArch64 mode; in 1473 * AArch32 mode SPSRs are basically CPSR-format. 1474 */ 1475 #define PSTATE_SP (1U) 1476 #define PSTATE_M (0xFU) 1477 #define PSTATE_nRW (1U << 4) 1478 #define PSTATE_F (1U << 6) 1479 #define PSTATE_I (1U << 7) 1480 #define PSTATE_A (1U << 8) 1481 #define PSTATE_D (1U << 9) 1482 #define PSTATE_BTYPE (3U << 10) 1483 #define PSTATE_SSBS (1U << 12) 1484 #define PSTATE_ALLINT (1U << 13) 1485 #define PSTATE_IL (1U << 20) 1486 #define PSTATE_SS (1U << 21) 1487 #define PSTATE_PAN (1U << 22) 1488 #define PSTATE_UAO (1U << 23) 1489 #define PSTATE_DIT (1U << 24) 1490 #define PSTATE_TCO (1U << 25) 1491 #define PSTATE_V (1U << 28) 1492 #define PSTATE_C (1U << 29) 1493 #define PSTATE_Z (1U << 30) 1494 #define PSTATE_N (1U << 31) 1495 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1496 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1497 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1498 /* Mode values for AArch64 */ 1499 #define PSTATE_MODE_EL3h 13 1500 #define PSTATE_MODE_EL3t 12 1501 #define PSTATE_MODE_EL2h 9 1502 #define PSTATE_MODE_EL2t 8 1503 #define PSTATE_MODE_EL1h 5 1504 #define PSTATE_MODE_EL1t 4 1505 #define PSTATE_MODE_EL0t 0 1506 1507 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1508 FIELD(SVCR, SM, 0, 1) 1509 FIELD(SVCR, ZA, 1, 1) 1510 1511 /* Fields for SMCR_ELx. */ 1512 FIELD(SMCR, LEN, 0, 4) 1513 FIELD(SMCR, FA64, 31, 1) 1514 1515 /* Write a new value to v7m.exception, thus transitioning into or out 1516 * of Handler mode; this may result in a change of active stack pointer. 1517 */ 1518 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1519 1520 /* Map EL and handler into a PSTATE_MODE. */ 1521 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1522 { 1523 return (el << 2) | handler; 1524 } 1525 1526 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1527 * interprocessing, so we don't attempt to sync with the cpsr state used by 1528 * the 32 bit decoder. 1529 */ 1530 static inline uint32_t pstate_read(CPUARMState *env) 1531 { 1532 int ZF; 1533 1534 ZF = (env->ZF == 0); 1535 return (env->NF & 0x80000000) | (ZF << 30) 1536 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1537 | env->pstate | env->daif | (env->btype << 10); 1538 } 1539 1540 static inline void pstate_write(CPUARMState *env, uint32_t val) 1541 { 1542 env->ZF = (~val) & PSTATE_Z; 1543 env->NF = val; 1544 env->CF = (val >> 29) & 1; 1545 env->VF = (val << 3) & 0x80000000; 1546 env->daif = val & PSTATE_DAIF; 1547 env->btype = (val >> 10) & 3; 1548 env->pstate = val & ~CACHED_PSTATE_BITS; 1549 } 1550 1551 /* Return the current CPSR value. */ 1552 uint32_t cpsr_read(CPUARMState *env); 1553 1554 typedef enum CPSRWriteType { 1555 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1556 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1557 CPSRWriteRaw = 2, 1558 /* trust values, no reg bank switch, no hflags rebuild */ 1559 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1560 } CPSRWriteType; 1561 1562 /* 1563 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1564 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1565 * correspond to TB flags bits cached in the hflags, unless @write_type 1566 * is CPSRWriteRaw. 1567 */ 1568 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1569 CPSRWriteType write_type); 1570 1571 /* Return the current xPSR value. */ 1572 static inline uint32_t xpsr_read(CPUARMState *env) 1573 { 1574 int ZF; 1575 ZF = (env->ZF == 0); 1576 return (env->NF & 0x80000000) | (ZF << 30) 1577 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1578 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1579 | ((env->condexec_bits & 0xfc) << 8) 1580 | (env->GE << 16) 1581 | env->v7m.exception; 1582 } 1583 1584 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1585 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1586 { 1587 if (mask & XPSR_NZCV) { 1588 env->ZF = (~val) & XPSR_Z; 1589 env->NF = val; 1590 env->CF = (val >> 29) & 1; 1591 env->VF = (val << 3) & 0x80000000; 1592 } 1593 if (mask & XPSR_Q) { 1594 env->QF = ((val & XPSR_Q) != 0); 1595 } 1596 if (mask & XPSR_GE) { 1597 env->GE = (val & XPSR_GE) >> 16; 1598 } 1599 #ifndef CONFIG_USER_ONLY 1600 if (mask & XPSR_T) { 1601 env->thumb = ((val & XPSR_T) != 0); 1602 } 1603 if (mask & XPSR_IT_0_1) { 1604 env->condexec_bits &= ~3; 1605 env->condexec_bits |= (val >> 25) & 3; 1606 } 1607 if (mask & XPSR_IT_2_7) { 1608 env->condexec_bits &= 3; 1609 env->condexec_bits |= (val >> 8) & 0xfc; 1610 } 1611 if (mask & XPSR_EXCP) { 1612 /* Note that this only happens on exception exit */ 1613 write_v7m_exception(env, val & XPSR_EXCP); 1614 } 1615 #endif 1616 } 1617 1618 #define HCR_VM (1ULL << 0) 1619 #define HCR_SWIO (1ULL << 1) 1620 #define HCR_PTW (1ULL << 2) 1621 #define HCR_FMO (1ULL << 3) 1622 #define HCR_IMO (1ULL << 4) 1623 #define HCR_AMO (1ULL << 5) 1624 #define HCR_VF (1ULL << 6) 1625 #define HCR_VI (1ULL << 7) 1626 #define HCR_VSE (1ULL << 8) 1627 #define HCR_FB (1ULL << 9) 1628 #define HCR_BSU_MASK (3ULL << 10) 1629 #define HCR_DC (1ULL << 12) 1630 #define HCR_TWI (1ULL << 13) 1631 #define HCR_TWE (1ULL << 14) 1632 #define HCR_TID0 (1ULL << 15) 1633 #define HCR_TID1 (1ULL << 16) 1634 #define HCR_TID2 (1ULL << 17) 1635 #define HCR_TID3 (1ULL << 18) 1636 #define HCR_TSC (1ULL << 19) 1637 #define HCR_TIDCP (1ULL << 20) 1638 #define HCR_TACR (1ULL << 21) 1639 #define HCR_TSW (1ULL << 22) 1640 #define HCR_TPCP (1ULL << 23) 1641 #define HCR_TPU (1ULL << 24) 1642 #define HCR_TTLB (1ULL << 25) 1643 #define HCR_TVM (1ULL << 26) 1644 #define HCR_TGE (1ULL << 27) 1645 #define HCR_TDZ (1ULL << 28) 1646 #define HCR_HCD (1ULL << 29) 1647 #define HCR_TRVM (1ULL << 30) 1648 #define HCR_RW (1ULL << 31) 1649 #define HCR_CD (1ULL << 32) 1650 #define HCR_ID (1ULL << 33) 1651 #define HCR_E2H (1ULL << 34) 1652 #define HCR_TLOR (1ULL << 35) 1653 #define HCR_TERR (1ULL << 36) 1654 #define HCR_TEA (1ULL << 37) 1655 #define HCR_MIOCNCE (1ULL << 38) 1656 #define HCR_TME (1ULL << 39) 1657 #define HCR_APK (1ULL << 40) 1658 #define HCR_API (1ULL << 41) 1659 #define HCR_NV (1ULL << 42) 1660 #define HCR_NV1 (1ULL << 43) 1661 #define HCR_AT (1ULL << 44) 1662 #define HCR_NV2 (1ULL << 45) 1663 #define HCR_FWB (1ULL << 46) 1664 #define HCR_FIEN (1ULL << 47) 1665 #define HCR_GPF (1ULL << 48) 1666 #define HCR_TID4 (1ULL << 49) 1667 #define HCR_TICAB (1ULL << 50) 1668 #define HCR_AMVOFFEN (1ULL << 51) 1669 #define HCR_TOCU (1ULL << 52) 1670 #define HCR_ENSCXT (1ULL << 53) 1671 #define HCR_TTLBIS (1ULL << 54) 1672 #define HCR_TTLBOS (1ULL << 55) 1673 #define HCR_ATA (1ULL << 56) 1674 #define HCR_DCT (1ULL << 57) 1675 #define HCR_TID5 (1ULL << 58) 1676 #define HCR_TWEDEN (1ULL << 59) 1677 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1678 1679 #define SCR_NS (1ULL << 0) 1680 #define SCR_IRQ (1ULL << 1) 1681 #define SCR_FIQ (1ULL << 2) 1682 #define SCR_EA (1ULL << 3) 1683 #define SCR_FW (1ULL << 4) 1684 #define SCR_AW (1ULL << 5) 1685 #define SCR_NET (1ULL << 6) 1686 #define SCR_SMD (1ULL << 7) 1687 #define SCR_HCE (1ULL << 8) 1688 #define SCR_SIF (1ULL << 9) 1689 #define SCR_RW (1ULL << 10) 1690 #define SCR_ST (1ULL << 11) 1691 #define SCR_TWI (1ULL << 12) 1692 #define SCR_TWE (1ULL << 13) 1693 #define SCR_TLOR (1ULL << 14) 1694 #define SCR_TERR (1ULL << 15) 1695 #define SCR_APK (1ULL << 16) 1696 #define SCR_API (1ULL << 17) 1697 #define SCR_EEL2 (1ULL << 18) 1698 #define SCR_EASE (1ULL << 19) 1699 #define SCR_NMEA (1ULL << 20) 1700 #define SCR_FIEN (1ULL << 21) 1701 #define SCR_ENSCXT (1ULL << 25) 1702 #define SCR_ATA (1ULL << 26) 1703 #define SCR_FGTEN (1ULL << 27) 1704 #define SCR_ECVEN (1ULL << 28) 1705 #define SCR_TWEDEN (1ULL << 29) 1706 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1707 #define SCR_TME (1ULL << 34) 1708 #define SCR_AMVOFFEN (1ULL << 35) 1709 #define SCR_ENAS0 (1ULL << 36) 1710 #define SCR_ADEN (1ULL << 37) 1711 #define SCR_HXEN (1ULL << 38) 1712 #define SCR_TRNDR (1ULL << 40) 1713 #define SCR_ENTP2 (1ULL << 41) 1714 #define SCR_GPF (1ULL << 48) 1715 #define SCR_NSE (1ULL << 62) 1716 1717 /* Return the current FPSCR value. */ 1718 uint32_t vfp_get_fpscr(CPUARMState *env); 1719 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1720 1721 /* 1722 * FPCR, Floating Point Control Register 1723 * FPSR, Floating Point Status Register 1724 * 1725 * For A64 floating point control and status bits are stored in 1726 * two logically distinct registers, FPCR and FPSR. We store these 1727 * in QEMU in vfp.fpcr and vfp.fpsr. 1728 * For A32 there was only one register, FPSCR. The bits are arranged 1729 * such that FPSCR bits map to FPCR or FPSR bits in the same bit positions, 1730 * so we can use appropriate masking to handle FPSCR reads and writes. 1731 * Note that the FPCR has some bits which are not visible in the 1732 * AArch32 view (for FEAT_AFP). Writing the FPSCR leaves these unchanged. 1733 */ 1734 1735 /* FPCR bits */ 1736 #define FPCR_FIZ (1 << 0) /* Flush Inputs to Zero (FEAT_AFP) */ 1737 #define FPCR_AH (1 << 1) /* Alternate Handling (FEAT_AFP) */ 1738 #define FPCR_NEP (1 << 2) /* SIMD scalar ops preserve elts (FEAT_AFP) */ 1739 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1740 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1741 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1742 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1743 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1744 #define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */ 1745 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1746 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */ 1747 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1748 #define FPCR_STRIDE_MASK (3 << 20) /* Stride */ 1749 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1750 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1751 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1752 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1753 1754 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1755 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1756 #define FPCR_LTPSIZE_LENGTH 3 1757 1758 /* Cumulative exception trap enable bits */ 1759 #define FPCR_EEXC_MASK (FPCR_IOE | FPCR_DZE | FPCR_OFE | FPCR_UFE | FPCR_IXE | FPCR_IDE) 1760 1761 /* FPSR bits */ 1762 #define FPSR_IOC (1 << 0) /* Invalid Operation cumulative exception */ 1763 #define FPSR_DZC (1 << 1) /* Divide by Zero cumulative exception */ 1764 #define FPSR_OFC (1 << 2) /* Overflow cumulative exception */ 1765 #define FPSR_UFC (1 << 3) /* Underflow cumulative exception */ 1766 #define FPSR_IXC (1 << 4) /* Inexact cumulative exception */ 1767 #define FPSR_IDC (1 << 7) /* Input Denormal cumulative exception */ 1768 #define FPSR_QC (1 << 27) /* Cumulative saturation bit */ 1769 #define FPSR_V (1 << 28) /* FP overflow flag */ 1770 #define FPSR_C (1 << 29) /* FP carry flag */ 1771 #define FPSR_Z (1 << 30) /* FP zero flag */ 1772 #define FPSR_N (1 << 31) /* FP negative flag */ 1773 1774 /* Cumulative exception status bits */ 1775 #define FPSR_CEXC_MASK (FPSR_IOC | FPSR_DZC | FPSR_OFC | FPSR_UFC | FPSR_IXC | FPSR_IDC) 1776 1777 #define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V) 1778 #define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC) 1779 1780 /* A32 FPSCR bits which architecturally map to FPSR bits */ 1781 #define FPSCR_FPSR_MASK (FPSR_NZCVQC_MASK | FPSR_CEXC_MASK) 1782 /* A32 FPSCR bits which architecturally map to FPCR bits */ 1783 #define FPSCR_FPCR_MASK (FPCR_EEXC_MASK | FPCR_LEN_MASK | FPCR_FZ16 | \ 1784 FPCR_STRIDE_MASK | FPCR_RMODE_MASK | \ 1785 FPCR_FZ | FPCR_DN | FPCR_AHP) 1786 /* These masks don't overlap: each bit lives in only one place */ 1787 QEMU_BUILD_BUG_ON(FPSCR_FPSR_MASK & FPSCR_FPCR_MASK); 1788 1789 /** 1790 * vfp_get_fpsr: read the AArch64 FPSR 1791 * @env: CPU context 1792 * 1793 * Return the current AArch64 FPSR value 1794 */ 1795 uint32_t vfp_get_fpsr(CPUARMState *env); 1796 1797 /** 1798 * vfp_get_fpcr: read the AArch64 FPCR 1799 * @env: CPU context 1800 * 1801 * Return the current AArch64 FPCR value 1802 */ 1803 uint32_t vfp_get_fpcr(CPUARMState *env); 1804 1805 /** 1806 * vfp_set_fpsr: write the AArch64 FPSR 1807 * @env: CPU context 1808 * @value: new value 1809 */ 1810 void vfp_set_fpsr(CPUARMState *env, uint32_t value); 1811 1812 /** 1813 * vfp_set_fpcr: write the AArch64 FPCR 1814 * @env: CPU context 1815 * @value: new value 1816 */ 1817 void vfp_set_fpcr(CPUARMState *env, uint32_t value); 1818 1819 enum arm_cpu_mode { 1820 ARM_CPU_MODE_USR = 0x10, 1821 ARM_CPU_MODE_FIQ = 0x11, 1822 ARM_CPU_MODE_IRQ = 0x12, 1823 ARM_CPU_MODE_SVC = 0x13, 1824 ARM_CPU_MODE_MON = 0x16, 1825 ARM_CPU_MODE_ABT = 0x17, 1826 ARM_CPU_MODE_HYP = 0x1a, 1827 ARM_CPU_MODE_UND = 0x1b, 1828 ARM_CPU_MODE_SYS = 0x1f 1829 }; 1830 1831 /* VFP system registers. */ 1832 #define ARM_VFP_FPSID 0 1833 #define ARM_VFP_FPSCR 1 1834 #define ARM_VFP_MVFR2 5 1835 #define ARM_VFP_MVFR1 6 1836 #define ARM_VFP_MVFR0 7 1837 #define ARM_VFP_FPEXC 8 1838 #define ARM_VFP_FPINST 9 1839 #define ARM_VFP_FPINST2 10 1840 /* These ones are M-profile only */ 1841 #define ARM_VFP_FPSCR_NZCVQC 2 1842 #define ARM_VFP_VPR 12 1843 #define ARM_VFP_P0 13 1844 #define ARM_VFP_FPCXT_NS 14 1845 #define ARM_VFP_FPCXT_S 15 1846 1847 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1848 #define QEMU_VFP_FPSCR_NZCV 0xffff 1849 1850 /* iwMMXt coprocessor control registers. */ 1851 #define ARM_IWMMXT_wCID 0 1852 #define ARM_IWMMXT_wCon 1 1853 #define ARM_IWMMXT_wCSSF 2 1854 #define ARM_IWMMXT_wCASF 3 1855 #define ARM_IWMMXT_wCGR0 8 1856 #define ARM_IWMMXT_wCGR1 9 1857 #define ARM_IWMMXT_wCGR2 10 1858 #define ARM_IWMMXT_wCGR3 11 1859 1860 /* V7M CCR bits */ 1861 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1862 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1863 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1864 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1865 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1866 FIELD(V7M_CCR, STKALIGN, 9, 1) 1867 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1868 FIELD(V7M_CCR, DC, 16, 1) 1869 FIELD(V7M_CCR, IC, 17, 1) 1870 FIELD(V7M_CCR, BP, 18, 1) 1871 FIELD(V7M_CCR, LOB, 19, 1) 1872 FIELD(V7M_CCR, TRD, 20, 1) 1873 1874 /* V7M SCR bits */ 1875 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1876 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1877 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1878 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1879 1880 /* V7M AIRCR bits */ 1881 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1882 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1883 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1884 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1885 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1886 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1887 FIELD(V7M_AIRCR, PRIS, 14, 1) 1888 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1889 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1890 1891 /* V7M CFSR bits for MMFSR */ 1892 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1893 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1894 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1895 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1896 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1897 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1898 1899 /* V7M CFSR bits for BFSR */ 1900 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1901 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1902 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1903 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1904 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1905 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1906 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1907 1908 /* V7M CFSR bits for UFSR */ 1909 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1910 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1911 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1912 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1913 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1914 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1915 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1916 1917 /* V7M CFSR bit masks covering all of the subregister bits */ 1918 FIELD(V7M_CFSR, MMFSR, 0, 8) 1919 FIELD(V7M_CFSR, BFSR, 8, 8) 1920 FIELD(V7M_CFSR, UFSR, 16, 16) 1921 1922 /* V7M HFSR bits */ 1923 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1924 FIELD(V7M_HFSR, FORCED, 30, 1) 1925 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1926 1927 /* V7M DFSR bits */ 1928 FIELD(V7M_DFSR, HALTED, 0, 1) 1929 FIELD(V7M_DFSR, BKPT, 1, 1) 1930 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1931 FIELD(V7M_DFSR, VCATCH, 3, 1) 1932 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1933 1934 /* V7M SFSR bits */ 1935 FIELD(V7M_SFSR, INVEP, 0, 1) 1936 FIELD(V7M_SFSR, INVIS, 1, 1) 1937 FIELD(V7M_SFSR, INVER, 2, 1) 1938 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1939 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1940 FIELD(V7M_SFSR, LSPERR, 5, 1) 1941 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1942 FIELD(V7M_SFSR, LSERR, 7, 1) 1943 1944 /* v7M MPU_CTRL bits */ 1945 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1946 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1947 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1948 1949 /* v7M CLIDR bits */ 1950 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1951 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1952 FIELD(V7M_CLIDR, LOC, 24, 3) 1953 FIELD(V7M_CLIDR, LOUU, 27, 3) 1954 FIELD(V7M_CLIDR, ICB, 30, 2) 1955 1956 FIELD(V7M_CSSELR, IND, 0, 1) 1957 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1958 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1959 * define a mask for this and check that it doesn't permit running off 1960 * the end of the array. 1961 */ 1962 FIELD(V7M_CSSELR, INDEX, 0, 4) 1963 1964 /* v7M FPCCR bits */ 1965 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1966 FIELD(V7M_FPCCR, USER, 1, 1) 1967 FIELD(V7M_FPCCR, S, 2, 1) 1968 FIELD(V7M_FPCCR, THREAD, 3, 1) 1969 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1970 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1971 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1972 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1973 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1974 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1975 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1976 FIELD(V7M_FPCCR, RES0, 11, 15) 1977 FIELD(V7M_FPCCR, TS, 26, 1) 1978 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1979 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1980 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1981 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1982 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1983 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1984 #define R_V7M_FPCCR_BANKED_MASK \ 1985 (R_V7M_FPCCR_LSPACT_MASK | \ 1986 R_V7M_FPCCR_USER_MASK | \ 1987 R_V7M_FPCCR_THREAD_MASK | \ 1988 R_V7M_FPCCR_MMRDY_MASK | \ 1989 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1990 R_V7M_FPCCR_UFRDY_MASK | \ 1991 R_V7M_FPCCR_ASPEN_MASK) 1992 1993 /* v7M VPR bits */ 1994 FIELD(V7M_VPR, P0, 0, 16) 1995 FIELD(V7M_VPR, MASK01, 16, 4) 1996 FIELD(V7M_VPR, MASK23, 20, 4) 1997 1998 /* 1999 * System register ID fields. 2000 */ 2001 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 2002 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 2003 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 2004 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 2005 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 2006 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 2007 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 2008 FIELD(CLIDR_EL1, LOUIS, 21, 3) 2009 FIELD(CLIDR_EL1, LOC, 24, 3) 2010 FIELD(CLIDR_EL1, LOUU, 27, 3) 2011 FIELD(CLIDR_EL1, ICB, 30, 3) 2012 2013 /* When FEAT_CCIDX is implemented */ 2014 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 2015 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 2016 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 2017 2018 /* When FEAT_CCIDX is not implemented */ 2019 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 2020 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 2021 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 2022 2023 FIELD(CTR_EL0, IMINLINE, 0, 4) 2024 FIELD(CTR_EL0, L1IP, 14, 2) 2025 FIELD(CTR_EL0, DMINLINE, 16, 4) 2026 FIELD(CTR_EL0, ERG, 20, 4) 2027 FIELD(CTR_EL0, CWG, 24, 4) 2028 FIELD(CTR_EL0, IDC, 28, 1) 2029 FIELD(CTR_EL0, DIC, 29, 1) 2030 FIELD(CTR_EL0, TMINLINE, 32, 6) 2031 2032 FIELD(MIDR_EL1, REVISION, 0, 4) 2033 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2034 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2035 FIELD(MIDR_EL1, VARIANT, 20, 4) 2036 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2037 2038 FIELD(ID_ISAR0, SWAP, 0, 4) 2039 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2040 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2041 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2042 FIELD(ID_ISAR0, COPROC, 16, 4) 2043 FIELD(ID_ISAR0, DEBUG, 20, 4) 2044 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2045 2046 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2047 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2048 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2049 FIELD(ID_ISAR1, EXTEND, 12, 4) 2050 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2051 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2052 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2053 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2054 2055 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2056 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2057 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2058 FIELD(ID_ISAR2, MULT, 12, 4) 2059 FIELD(ID_ISAR2, MULTS, 16, 4) 2060 FIELD(ID_ISAR2, MULTU, 20, 4) 2061 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2062 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2063 2064 FIELD(ID_ISAR3, SATURATE, 0, 4) 2065 FIELD(ID_ISAR3, SIMD, 4, 4) 2066 FIELD(ID_ISAR3, SVC, 8, 4) 2067 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2068 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2069 FIELD(ID_ISAR3, T32COPY, 20, 4) 2070 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2071 FIELD(ID_ISAR3, T32EE, 28, 4) 2072 2073 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2074 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2075 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2076 FIELD(ID_ISAR4, SMC, 12, 4) 2077 FIELD(ID_ISAR4, BARRIER, 16, 4) 2078 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2079 FIELD(ID_ISAR4, PSR_M, 24, 4) 2080 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2081 2082 FIELD(ID_ISAR5, SEVL, 0, 4) 2083 FIELD(ID_ISAR5, AES, 4, 4) 2084 FIELD(ID_ISAR5, SHA1, 8, 4) 2085 FIELD(ID_ISAR5, SHA2, 12, 4) 2086 FIELD(ID_ISAR5, CRC32, 16, 4) 2087 FIELD(ID_ISAR5, RDM, 24, 4) 2088 FIELD(ID_ISAR5, VCMA, 28, 4) 2089 2090 FIELD(ID_ISAR6, JSCVT, 0, 4) 2091 FIELD(ID_ISAR6, DP, 4, 4) 2092 FIELD(ID_ISAR6, FHM, 8, 4) 2093 FIELD(ID_ISAR6, SB, 12, 4) 2094 FIELD(ID_ISAR6, SPECRES, 16, 4) 2095 FIELD(ID_ISAR6, BF16, 20, 4) 2096 FIELD(ID_ISAR6, I8MM, 24, 4) 2097 2098 FIELD(ID_MMFR0, VMSA, 0, 4) 2099 FIELD(ID_MMFR0, PMSA, 4, 4) 2100 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2101 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2102 FIELD(ID_MMFR0, TCM, 16, 4) 2103 FIELD(ID_MMFR0, AUXREG, 20, 4) 2104 FIELD(ID_MMFR0, FCSE, 24, 4) 2105 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2106 2107 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2108 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2109 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2110 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2111 FIELD(ID_MMFR1, L1HVD, 16, 4) 2112 FIELD(ID_MMFR1, L1UNI, 20, 4) 2113 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2114 FIELD(ID_MMFR1, BPRED, 28, 4) 2115 2116 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2117 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2118 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2119 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2120 FIELD(ID_MMFR2, UNITLB, 16, 4) 2121 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2122 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2123 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2124 2125 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2126 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2127 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2128 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2129 FIELD(ID_MMFR3, PAN, 16, 4) 2130 FIELD(ID_MMFR3, COHWALK, 20, 4) 2131 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2132 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2133 2134 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2135 FIELD(ID_MMFR4, AC2, 4, 4) 2136 FIELD(ID_MMFR4, XNX, 8, 4) 2137 FIELD(ID_MMFR4, CNP, 12, 4) 2138 FIELD(ID_MMFR4, HPDS, 16, 4) 2139 FIELD(ID_MMFR4, LSM, 20, 4) 2140 FIELD(ID_MMFR4, CCIDX, 24, 4) 2141 FIELD(ID_MMFR4, EVT, 28, 4) 2142 2143 FIELD(ID_MMFR5, ETS, 0, 4) 2144 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2145 2146 FIELD(ID_PFR0, STATE0, 0, 4) 2147 FIELD(ID_PFR0, STATE1, 4, 4) 2148 FIELD(ID_PFR0, STATE2, 8, 4) 2149 FIELD(ID_PFR0, STATE3, 12, 4) 2150 FIELD(ID_PFR0, CSV2, 16, 4) 2151 FIELD(ID_PFR0, AMU, 20, 4) 2152 FIELD(ID_PFR0, DIT, 24, 4) 2153 FIELD(ID_PFR0, RAS, 28, 4) 2154 2155 FIELD(ID_PFR1, PROGMOD, 0, 4) 2156 FIELD(ID_PFR1, SECURITY, 4, 4) 2157 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2158 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2159 FIELD(ID_PFR1, GENTIMER, 16, 4) 2160 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2161 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2162 FIELD(ID_PFR1, GIC, 28, 4) 2163 2164 FIELD(ID_PFR2, CSV3, 0, 4) 2165 FIELD(ID_PFR2, SSBS, 4, 4) 2166 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2167 2168 FIELD(ID_AA64ISAR0, AES, 4, 4) 2169 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2170 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2171 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2172 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2173 FIELD(ID_AA64ISAR0, TME, 24, 4) 2174 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2175 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2176 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2177 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2178 FIELD(ID_AA64ISAR0, DP, 44, 4) 2179 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2180 FIELD(ID_AA64ISAR0, TS, 52, 4) 2181 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2182 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2183 2184 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2185 FIELD(ID_AA64ISAR1, APA, 4, 4) 2186 FIELD(ID_AA64ISAR1, API, 8, 4) 2187 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2188 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2189 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2190 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2191 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2192 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2193 FIELD(ID_AA64ISAR1, SB, 36, 4) 2194 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2195 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2196 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2197 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2198 FIELD(ID_AA64ISAR1, XS, 56, 4) 2199 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2200 2201 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2202 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2203 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2204 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2205 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2206 FIELD(ID_AA64ISAR2, BC, 20, 4) 2207 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2208 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2209 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2210 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2211 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2212 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2213 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2214 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2215 2216 FIELD(ID_AA64PFR0, EL0, 0, 4) 2217 FIELD(ID_AA64PFR0, EL1, 4, 4) 2218 FIELD(ID_AA64PFR0, EL2, 8, 4) 2219 FIELD(ID_AA64PFR0, EL3, 12, 4) 2220 FIELD(ID_AA64PFR0, FP, 16, 4) 2221 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2222 FIELD(ID_AA64PFR0, GIC, 24, 4) 2223 FIELD(ID_AA64PFR0, RAS, 28, 4) 2224 FIELD(ID_AA64PFR0, SVE, 32, 4) 2225 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2226 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2227 FIELD(ID_AA64PFR0, AMU, 44, 4) 2228 FIELD(ID_AA64PFR0, DIT, 48, 4) 2229 FIELD(ID_AA64PFR0, RME, 52, 4) 2230 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2231 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2232 2233 FIELD(ID_AA64PFR1, BT, 0, 4) 2234 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2235 FIELD(ID_AA64PFR1, MTE, 8, 4) 2236 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2237 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2238 FIELD(ID_AA64PFR1, SME, 24, 4) 2239 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2240 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2241 FIELD(ID_AA64PFR1, NMI, 36, 4) 2242 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2243 FIELD(ID_AA64PFR1, GCS, 44, 4) 2244 FIELD(ID_AA64PFR1, THE, 48, 4) 2245 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2246 FIELD(ID_AA64PFR1, DF2, 56, 4) 2247 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2248 2249 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2250 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2251 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2252 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2253 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2254 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2255 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2256 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2257 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2258 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2259 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2260 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2261 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2262 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2263 2264 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2265 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2266 FIELD(ID_AA64MMFR1, VH, 8, 4) 2267 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2268 FIELD(ID_AA64MMFR1, LO, 16, 4) 2269 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2270 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2271 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2272 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2273 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2274 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2275 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2276 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2277 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2278 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2279 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2280 2281 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2282 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2283 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2284 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2285 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2286 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2287 FIELD(ID_AA64MMFR2, NV, 24, 4) 2288 FIELD(ID_AA64MMFR2, ST, 28, 4) 2289 FIELD(ID_AA64MMFR2, AT, 32, 4) 2290 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2291 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2292 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2293 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2294 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2295 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2296 2297 FIELD(ID_AA64MMFR3, TCRX, 0, 4) 2298 FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) 2299 FIELD(ID_AA64MMFR3, S1PIE, 8, 4) 2300 FIELD(ID_AA64MMFR3, S2PIE, 12, 4) 2301 FIELD(ID_AA64MMFR3, S1POE, 16, 4) 2302 FIELD(ID_AA64MMFR3, S2POE, 20, 4) 2303 FIELD(ID_AA64MMFR3, AIE, 24, 4) 2304 FIELD(ID_AA64MMFR3, MEC, 28, 4) 2305 FIELD(ID_AA64MMFR3, D128, 32, 4) 2306 FIELD(ID_AA64MMFR3, D128_2, 36, 4) 2307 FIELD(ID_AA64MMFR3, SNERR, 40, 4) 2308 FIELD(ID_AA64MMFR3, ANERR, 44, 4) 2309 FIELD(ID_AA64MMFR3, SDERR, 52, 4) 2310 FIELD(ID_AA64MMFR3, ADERR, 56, 4) 2311 FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) 2312 2313 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2314 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2315 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2316 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2317 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2318 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2319 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2320 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2321 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2322 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2323 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2324 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2325 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2326 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2327 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2328 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2329 2330 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2331 FIELD(ID_AA64ZFR0, AES, 4, 4) 2332 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2333 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2334 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2335 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2336 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2337 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2338 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2339 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2340 2341 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2342 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2343 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2344 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2345 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2346 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2347 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2348 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2349 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2350 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2351 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2352 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2353 2354 FIELD(ID_DFR0, COPDBG, 0, 4) 2355 FIELD(ID_DFR0, COPSDBG, 4, 4) 2356 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2357 FIELD(ID_DFR0, COPTRC, 12, 4) 2358 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2359 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2360 FIELD(ID_DFR0, PERFMON, 24, 4) 2361 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2362 2363 FIELD(ID_DFR1, MTPMU, 0, 4) 2364 FIELD(ID_DFR1, HPMN0, 4, 4) 2365 2366 FIELD(DBGDIDR, SE_IMP, 12, 1) 2367 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2368 FIELD(DBGDIDR, VERSION, 16, 4) 2369 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2370 FIELD(DBGDIDR, BRPS, 24, 4) 2371 FIELD(DBGDIDR, WRPS, 28, 4) 2372 2373 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2374 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2375 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2376 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2377 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2378 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2379 FIELD(DBGDEVID, AUXREGS, 24, 4) 2380 FIELD(DBGDEVID, CIDMASK, 28, 4) 2381 2382 FIELD(DBGDEVID1, PCSROFFSET, 0, 4) 2383 2384 FIELD(MVFR0, SIMDREG, 0, 4) 2385 FIELD(MVFR0, FPSP, 4, 4) 2386 FIELD(MVFR0, FPDP, 8, 4) 2387 FIELD(MVFR0, FPTRAP, 12, 4) 2388 FIELD(MVFR0, FPDIVIDE, 16, 4) 2389 FIELD(MVFR0, FPSQRT, 20, 4) 2390 FIELD(MVFR0, FPSHVEC, 24, 4) 2391 FIELD(MVFR0, FPROUND, 28, 4) 2392 2393 FIELD(MVFR1, FPFTZ, 0, 4) 2394 FIELD(MVFR1, FPDNAN, 4, 4) 2395 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2396 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2397 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2398 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2399 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2400 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2401 FIELD(MVFR1, FPHP, 24, 4) 2402 FIELD(MVFR1, SIMDFMAC, 28, 4) 2403 2404 FIELD(MVFR2, SIMDMISC, 0, 4) 2405 FIELD(MVFR2, FPMISC, 4, 4) 2406 2407 FIELD(GPCCR, PPS, 0, 3) 2408 FIELD(GPCCR, IRGN, 8, 2) 2409 FIELD(GPCCR, ORGN, 10, 2) 2410 FIELD(GPCCR, SH, 12, 2) 2411 FIELD(GPCCR, PGS, 14, 2) 2412 FIELD(GPCCR, GPC, 16, 1) 2413 FIELD(GPCCR, GPCP, 17, 1) 2414 FIELD(GPCCR, L0GPTSZ, 20, 4) 2415 2416 FIELD(MFAR, FPA, 12, 40) 2417 FIELD(MFAR, NSE, 62, 1) 2418 FIELD(MFAR, NS, 63, 1) 2419 2420 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2421 2422 /* If adding a feature bit which corresponds to a Linux ELF 2423 * HWCAP bit, remember to update the feature-bit-to-hwcap 2424 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2425 */ 2426 enum arm_features { 2427 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2428 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2429 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2430 ARM_FEATURE_V6, 2431 ARM_FEATURE_V6K, 2432 ARM_FEATURE_V7, 2433 ARM_FEATURE_THUMB2, 2434 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2435 ARM_FEATURE_NEON, 2436 ARM_FEATURE_M, /* Microcontroller profile. */ 2437 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2438 ARM_FEATURE_THUMB2EE, 2439 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2440 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2441 ARM_FEATURE_V4T, 2442 ARM_FEATURE_V5, 2443 ARM_FEATURE_STRONGARM, 2444 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2445 ARM_FEATURE_GENERIC_TIMER, 2446 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2447 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2448 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2449 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2450 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2451 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2452 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2453 ARM_FEATURE_V8, 2454 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2455 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2456 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2457 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2458 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2459 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2460 ARM_FEATURE_PMU, /* has PMU support */ 2461 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2462 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2463 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2464 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2465 /* 2466 * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz 2467 * if the board doesn't set a value, instead of 1GHz. It is for backwards 2468 * compatibility and used only with CPU definitions that were already 2469 * in QEMU before we changed the default. It should not be set on any 2470 * CPU types added in future. 2471 */ 2472 ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ 2473 }; 2474 2475 static inline int arm_feature(CPUARMState *env, int feature) 2476 { 2477 return (env->features & (1ULL << feature)) != 0; 2478 } 2479 2480 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2481 2482 /* 2483 * ARM v9 security states. 2484 * The ordering of the enumeration corresponds to the low 2 bits 2485 * of the GPI value, and (except for Root) the concat of NSE:NS. 2486 */ 2487 2488 typedef enum ARMSecuritySpace { 2489 ARMSS_Secure = 0, 2490 ARMSS_NonSecure = 1, 2491 ARMSS_Root = 2, 2492 ARMSS_Realm = 3, 2493 } ARMSecuritySpace; 2494 2495 /* Return true if @space is secure, in the pre-v9 sense. */ 2496 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2497 { 2498 return space == ARMSS_Secure || space == ARMSS_Root; 2499 } 2500 2501 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2502 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2503 { 2504 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2505 } 2506 2507 #if !defined(CONFIG_USER_ONLY) 2508 /** 2509 * arm_security_space_below_el3: 2510 * @env: cpu context 2511 * 2512 * Return the security space of exception levels below EL3, following 2513 * an exception return to those levels. Unlike arm_security_space, 2514 * this doesn't care about the current EL. 2515 */ 2516 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2517 2518 /** 2519 * arm_is_secure_below_el3: 2520 * @env: cpu context 2521 * 2522 * Return true if exception levels below EL3 are in secure state, 2523 * or would be following an exception return to those levels. 2524 */ 2525 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2526 { 2527 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2528 return ss == ARMSS_Secure; 2529 } 2530 2531 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2532 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2533 { 2534 assert(!arm_feature(env, ARM_FEATURE_M)); 2535 if (arm_feature(env, ARM_FEATURE_EL3)) { 2536 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2537 /* CPU currently in AArch64 state and EL3 */ 2538 return true; 2539 } else if (!is_a64(env) && 2540 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2541 /* CPU currently in AArch32 state and monitor mode */ 2542 return true; 2543 } 2544 } 2545 return false; 2546 } 2547 2548 /** 2549 * arm_security_space: 2550 * @env: cpu context 2551 * 2552 * Return the current security space of the cpu. 2553 */ 2554 ARMSecuritySpace arm_security_space(CPUARMState *env); 2555 2556 /** 2557 * arm_is_secure: 2558 * @env: cpu context 2559 * 2560 * Return true if the processor is in secure state. 2561 */ 2562 static inline bool arm_is_secure(CPUARMState *env) 2563 { 2564 return arm_space_is_secure(arm_security_space(env)); 2565 } 2566 2567 /* 2568 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2569 * This corresponds to the pseudocode EL2Enabled(). 2570 */ 2571 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2572 ARMSecuritySpace space) 2573 { 2574 assert(space != ARMSS_Root); 2575 return arm_feature(env, ARM_FEATURE_EL2) 2576 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2577 } 2578 2579 static inline bool arm_is_el2_enabled(CPUARMState *env) 2580 { 2581 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2582 } 2583 2584 #else 2585 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2586 { 2587 return ARMSS_NonSecure; 2588 } 2589 2590 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2591 { 2592 return false; 2593 } 2594 2595 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2596 { 2597 return false; 2598 } 2599 2600 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2601 { 2602 return ARMSS_NonSecure; 2603 } 2604 2605 static inline bool arm_is_secure(CPUARMState *env) 2606 { 2607 return false; 2608 } 2609 2610 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2611 ARMSecuritySpace space) 2612 { 2613 return false; 2614 } 2615 2616 static inline bool arm_is_el2_enabled(CPUARMState *env) 2617 { 2618 return false; 2619 } 2620 #endif 2621 2622 /** 2623 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2624 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2625 * "for all purposes other than a direct read or write access of HCR_EL2." 2626 * Not included here is HCR_RW. 2627 */ 2628 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2629 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2630 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2631 2632 /* 2633 * Function for determining whether guest cp register reads and writes should 2634 * access the secure or non-secure bank of a cp register. When EL3 is 2635 * operating in AArch32 state, the NS-bit determines whether the secure 2636 * instance of a cp register should be used. When EL3 is AArch64 (or if 2637 * it doesn't exist at all) then there is no register banking, and all 2638 * accesses are to the non-secure version. 2639 */ 2640 bool access_secure_reg(CPUARMState *env); 2641 2642 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2643 uint32_t cur_el, bool secure); 2644 2645 /* Return the highest implemented Exception Level */ 2646 static inline int arm_highest_el(CPUARMState *env) 2647 { 2648 if (arm_feature(env, ARM_FEATURE_EL3)) { 2649 return 3; 2650 } 2651 if (arm_feature(env, ARM_FEATURE_EL2)) { 2652 return 2; 2653 } 2654 return 1; 2655 } 2656 2657 /* Return true if a v7M CPU is in Handler mode */ 2658 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2659 { 2660 return env->v7m.exception != 0; 2661 } 2662 2663 /** 2664 * write_list_to_cpustate 2665 * @cpu: ARMCPU 2666 * 2667 * For each register listed in the ARMCPU cpreg_indexes list, write 2668 * its value from the cpreg_values list into the ARMCPUState structure. 2669 * This updates TCG's working data structures from KVM data or 2670 * from incoming migration state. 2671 * 2672 * Returns: true if all register values were updated correctly, 2673 * false if some register was unknown or could not be written. 2674 * Note that we do not stop early on failure -- we will attempt 2675 * writing all registers in the list. 2676 */ 2677 bool write_list_to_cpustate(ARMCPU *cpu); 2678 2679 /** 2680 * write_cpustate_to_list: 2681 * @cpu: ARMCPU 2682 * @kvm_sync: true if this is for syncing back to KVM 2683 * 2684 * For each register listed in the ARMCPU cpreg_indexes list, write 2685 * its value from the ARMCPUState structure into the cpreg_values list. 2686 * This is used to copy info from TCG's working data structures into 2687 * KVM or for outbound migration. 2688 * 2689 * @kvm_sync is true if we are doing this in order to sync the 2690 * register state back to KVM. In this case we will only update 2691 * values in the list if the previous list->cpustate sync actually 2692 * successfully wrote the CPU state. Otherwise we will keep the value 2693 * that is in the list. 2694 * 2695 * Returns: true if all register values were read correctly, 2696 * false if some register was unknown or could not be read. 2697 * Note that we do not stop early on failure -- we will attempt 2698 * reading all registers in the list. 2699 */ 2700 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2701 2702 #define ARM_CPUID_TI915T 0x54029152 2703 #define ARM_CPUID_TI925T 0x54029252 2704 2705 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2706 2707 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2708 2709 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2710 * 2711 * If EL3 is 64-bit: 2712 * + NonSecure EL1 & 0 stage 1 2713 * + NonSecure EL1 & 0 stage 2 2714 * + NonSecure EL2 2715 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2716 * + Secure EL1 & 0 stage 1 2717 * + Secure EL1 & 0 stage 2 (FEAT_SEL2) 2718 * + Secure EL2 (FEAT_SEL2) 2719 * + Secure EL2 & 0 (FEAT_SEL2) 2720 * + Realm EL1 & 0 stage 1 (FEAT_RME) 2721 * + Realm EL1 & 0 stage 2 (FEAT_RME) 2722 * + Realm EL2 (FEAT_RME) 2723 * + EL3 2724 * If EL3 is 32-bit: 2725 * + NonSecure PL1 & 0 stage 1 2726 * + NonSecure PL1 & 0 stage 2 2727 * + NonSecure PL2 2728 * + Secure PL1 & 0 2729 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2730 * 2731 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2732 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2733 * because they may differ in access permissions even if the VA->PA map is 2734 * the same 2735 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2736 * translation, which means that we have one mmu_idx that deals with two 2737 * concatenated translation regimes [this sort of combined s1+2 TLB is 2738 * architecturally permitted] 2739 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2740 * handling via the TLB. The only way to do a stage 1 translation without 2741 * the immediate stage 2 translation is via the ATS or AT system insns, 2742 * which can be slow-pathed and always do a page table walk. 2743 * The only use of stage 2 translations is either as part of an s1+2 2744 * lookup or when loading the descriptors during a stage 1 page table walk, 2745 * and in both those cases we don't use the TLB. 2746 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2747 * translation regimes, because they map reasonably well to each other 2748 * and they can't both be active at the same time. 2749 * 5. we want to be able to use the TLB for accesses done as part of a 2750 * stage1 page table walk, rather than having to walk the stage2 page 2751 * table over and over. 2752 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2753 * Never (PAN) bit within PSTATE. 2754 * 7. we fold together most secure and non-secure regimes for A-profile, 2755 * because there are no banked system registers for aarch64, so the 2756 * process of switching between secure and non-secure is 2757 * already heavyweight. 2758 * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, 2759 * because both are in use simultaneously for Secure EL2. 2760 * 2761 * This gives us the following list of cases: 2762 * 2763 * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2) 2764 * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2) 2765 * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN) 2766 * EL0 EL2&0 2767 * EL2 EL2&0 2768 * EL2 EL2&0 +PAN 2769 * EL2 (aka NS PL2) 2770 * EL3 (aka AArch32 S PL1 PL1&0) 2771 * AArch32 S PL0 PL1&0 (we call this EL30_0) 2772 * AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN) 2773 * Stage2 Secure 2774 * Stage2 NonSecure 2775 * plus one TLB per Physical address space: S, NS, Realm, Root 2776 * 2777 * for a total of 16 different mmu_idx. 2778 * 2779 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2780 * as A profile. They only need to distinguish EL0 and EL1 (and 2781 * EL2 for cores like the Cortex-R52). 2782 * 2783 * M profile CPUs are rather different as they do not have a true MMU. 2784 * They have the following different MMU indexes: 2785 * User 2786 * Privileged 2787 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2788 * Privileged, execution priority negative (ditto) 2789 * If the CPU supports the v8M Security Extension then there are also: 2790 * Secure User 2791 * Secure Privileged 2792 * Secure User, execution priority negative 2793 * Secure Privileged, execution priority negative 2794 * 2795 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2796 * are not quite the same -- different CPU types (most notably M profile 2797 * vs A/R profile) would like to use MMU indexes with different semantics, 2798 * but since we don't ever need to use all of those in a single CPU we 2799 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2800 * modes + total number of M profile MMU modes". The lower bits of 2801 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2802 * the same for any particular CPU. 2803 * Variables of type ARMMUIdx are always full values, and the core 2804 * index values are in variables of type 'int'. 2805 * 2806 * Our enumeration includes at the end some entries which are not "true" 2807 * mmu_idx values in that they don't have corresponding TLBs and are only 2808 * valid for doing slow path page table walks. 2809 * 2810 * The constant names here are patterned after the general style of the names 2811 * of the AT/ATS operations. 2812 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2813 * For M profile we arrange them to have a bit for priv, a bit for negpri 2814 * and a bit for secure. 2815 */ 2816 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2817 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2818 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2819 2820 /* Meanings of the bits for M profile mmu idx values */ 2821 #define ARM_MMU_IDX_M_PRIV 0x1 2822 #define ARM_MMU_IDX_M_NEGPRI 0x2 2823 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2824 2825 #define ARM_MMU_IDX_TYPE_MASK \ 2826 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2827 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2828 2829 typedef enum ARMMMUIdx { 2830 /* 2831 * A-profile. 2832 */ 2833 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2834 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2835 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2836 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2837 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2838 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2839 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2840 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2841 ARMMMUIdx_E30_0 = 8 | ARM_MMU_IDX_A, 2842 ARMMMUIdx_E30_3_PAN = 9 | ARM_MMU_IDX_A, 2843 2844 /* 2845 * Used for second stage of an S12 page table walk, or for descriptor 2846 * loads during first stage of an S1 page table walk. Note that both 2847 * are in use simultaneously for SecureEL2: the security state for 2848 * the S2 ptw is selected by the NS bit from the S1 ptw. 2849 */ 2850 ARMMMUIdx_Stage2_S = 10 | ARM_MMU_IDX_A, 2851 ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A, 2852 2853 /* TLBs with 1-1 mapping to the physical address spaces. */ 2854 ARMMMUIdx_Phys_S = 12 | ARM_MMU_IDX_A, 2855 ARMMMUIdx_Phys_NS = 13 | ARM_MMU_IDX_A, 2856 ARMMMUIdx_Phys_Root = 14 | ARM_MMU_IDX_A, 2857 ARMMMUIdx_Phys_Realm = 15 | ARM_MMU_IDX_A, 2858 2859 /* 2860 * These are not allocated TLBs and are used only for AT system 2861 * instructions or for the first stage of an S12 page table walk. 2862 */ 2863 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2864 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2865 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2866 2867 /* 2868 * M-profile. 2869 */ 2870 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2871 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2872 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2873 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2874 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2875 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2876 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2877 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2878 } ARMMMUIdx; 2879 2880 /* 2881 * Bit macros for the core-mmu-index values for each index, 2882 * for use when calling tlb_flush_by_mmuidx() and friends. 2883 */ 2884 #define TO_CORE_BIT(NAME) \ 2885 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2886 2887 typedef enum ARMMMUIdxBit { 2888 TO_CORE_BIT(E10_0), 2889 TO_CORE_BIT(E20_0), 2890 TO_CORE_BIT(E10_1), 2891 TO_CORE_BIT(E10_1_PAN), 2892 TO_CORE_BIT(E2), 2893 TO_CORE_BIT(E20_2), 2894 TO_CORE_BIT(E20_2_PAN), 2895 TO_CORE_BIT(E3), 2896 TO_CORE_BIT(E30_0), 2897 TO_CORE_BIT(E30_3_PAN), 2898 TO_CORE_BIT(Stage2), 2899 TO_CORE_BIT(Stage2_S), 2900 2901 TO_CORE_BIT(MUser), 2902 TO_CORE_BIT(MPriv), 2903 TO_CORE_BIT(MUserNegPri), 2904 TO_CORE_BIT(MPrivNegPri), 2905 TO_CORE_BIT(MSUser), 2906 TO_CORE_BIT(MSPriv), 2907 TO_CORE_BIT(MSUserNegPri), 2908 TO_CORE_BIT(MSPrivNegPri), 2909 } ARMMMUIdxBit; 2910 2911 #undef TO_CORE_BIT 2912 2913 #define MMU_USER_IDX 0 2914 2915 /* Indexes used when registering address spaces with cpu_address_space_init */ 2916 typedef enum ARMASIdx { 2917 ARMASIdx_NS = 0, 2918 ARMASIdx_S = 1, 2919 ARMASIdx_TagNS = 2, 2920 ARMASIdx_TagS = 3, 2921 } ARMASIdx; 2922 2923 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 2924 { 2925 /* Assert the relative order of the physical mmu indexes. */ 2926 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 2927 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 2928 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 2929 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 2930 2931 return ARMMMUIdx_Phys_S + space; 2932 } 2933 2934 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 2935 { 2936 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 2937 return idx - ARMMMUIdx_Phys_S; 2938 } 2939 2940 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2941 { 2942 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2943 * CSSELR is RAZ/WI. 2944 */ 2945 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2946 } 2947 2948 static inline bool arm_sctlr_b(CPUARMState *env) 2949 { 2950 return 2951 /* We need not implement SCTLR.ITD in user-mode emulation, so 2952 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2953 * This lets people run BE32 binaries with "-cpu any". 2954 */ 2955 #ifndef CONFIG_USER_ONLY 2956 !arm_feature(env, ARM_FEATURE_V7) && 2957 #endif 2958 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2959 } 2960 2961 uint64_t arm_sctlr(CPUARMState *env, int el); 2962 2963 /* 2964 * We have more than 32-bits worth of state per TB, so we split the data 2965 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 2966 * We collect these two parts in CPUARMTBFlags where they are named 2967 * flags and flags2 respectively. 2968 * 2969 * The flags that are shared between all execution modes, TBFLAG_ANY, are stored 2970 * in flags. The flags that are specific to a given mode are stored in flags2. 2971 * flags2 always has 64-bits, even though only 32-bits are used for A32 and M32. 2972 * 2973 * The bits for 32-bit A-profile and M-profile partially overlap: 2974 * 2975 * 31 23 11 10 0 2976 * +-------------+----------+----------------+ 2977 * | | | TBFLAG_A32 | 2978 * | TBFLAG_AM32 | +-----+----------+ 2979 * | | |TBFLAG_M32| 2980 * +-------------+----------------+----------+ 2981 * 31 23 6 5 0 2982 * 2983 * Unless otherwise noted, these bits are cached in env->hflags. 2984 */ 2985 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 2986 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 2987 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 2988 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 2989 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 2990 /* Target EL if we take a floating-point-disabled exception */ 2991 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 2992 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 2993 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 2994 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 2995 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 2996 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 2997 2998 /* 2999 * Bit usage when in AArch32 state, both A- and M-profile. 3000 */ 3001 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3002 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3003 3004 /* 3005 * Bit usage when in AArch32 state, for A-profile only. 3006 */ 3007 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3008 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3009 /* 3010 * We store the bottom two bits of the CPAR as TB flags and handle 3011 * checks on the other bits at runtime. This shares the same bits as 3012 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3013 * Not cached, because VECLEN+VECSTRIDE are not cached. 3014 */ 3015 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3016 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3017 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3018 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3019 /* 3020 * Indicates whether cp register reads and writes by guest code should access 3021 * the secure or nonsecure bank of banked registers; note that this is not 3022 * the same thing as the current security state of the processor! 3023 */ 3024 FIELD(TBFLAG_A32, NS, 10, 1) 3025 /* 3026 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3027 * This requires an SME trap from AArch32 mode when using NEON. 3028 */ 3029 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3030 3031 /* 3032 * Bit usage when in AArch32 state, for M-profile only. 3033 */ 3034 /* Handler (ie not Thread) mode */ 3035 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3036 /* Whether we should generate stack-limit checks */ 3037 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3038 /* Set if FPCCR.LSPACT is set */ 3039 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3040 /* Set if we must create a new FP context */ 3041 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3042 /* Set if FPCCR.S does not match current security state */ 3043 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3044 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3045 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3046 /* Set if in secure mode */ 3047 FIELD(TBFLAG_M32, SECURE, 6, 1) 3048 3049 /* 3050 * Bit usage when in AArch64 state 3051 */ 3052 FIELD(TBFLAG_A64, TBII, 0, 2) 3053 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3054 /* The current vector length, either NVL or SVL. */ 3055 FIELD(TBFLAG_A64, VL, 4, 4) 3056 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3057 FIELD(TBFLAG_A64, BT, 9, 1) 3058 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3059 FIELD(TBFLAG_A64, TBID, 12, 2) 3060 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3061 FIELD(TBFLAG_A64, ATA, 15, 1) 3062 FIELD(TBFLAG_A64, TCMA, 16, 2) 3063 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3064 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3065 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3066 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3067 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3068 FIELD(TBFLAG_A64, SVL, 24, 4) 3069 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3070 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3071 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 3072 FIELD(TBFLAG_A64, NAA, 30, 1) 3073 FIELD(TBFLAG_A64, ATA0, 31, 1) 3074 FIELD(TBFLAG_A64, NV, 32, 1) 3075 FIELD(TBFLAG_A64, NV1, 33, 1) 3076 FIELD(TBFLAG_A64, NV2, 34, 1) 3077 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ 3078 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) 3079 /* Set if FEAT_NV2 RAM accesses are big-endian */ 3080 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 3081 FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */ 3082 FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */ 3083 3084 /* 3085 * Helpers for using the above. Note that only the A64 accessors use 3086 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 3087 * word either is or might be 32 bits only. 3088 */ 3089 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3090 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3091 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3092 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3093 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3094 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3095 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3096 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3097 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3098 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3099 3100 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3101 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 3102 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3103 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3104 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3105 3106 /** 3107 * sve_vq 3108 * @env: the cpu context 3109 * 3110 * Return the VL cached within env->hflags, in units of quadwords. 3111 */ 3112 static inline int sve_vq(CPUARMState *env) 3113 { 3114 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3115 } 3116 3117 /** 3118 * sme_vq 3119 * @env: the cpu context 3120 * 3121 * Return the SVL cached within env->hflags, in units of quadwords. 3122 */ 3123 static inline int sme_vq(CPUARMState *env) 3124 { 3125 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3126 } 3127 3128 static inline bool bswap_code(bool sctlr_b) 3129 { 3130 #ifdef CONFIG_USER_ONLY 3131 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3132 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3133 * would also end up as a mixed-endian mode with BE code, LE data. 3134 */ 3135 return TARGET_BIG_ENDIAN ^ sctlr_b; 3136 #else 3137 /* All code access in ARM is little endian, and there are no loaders 3138 * doing swaps that need to be reversed 3139 */ 3140 return 0; 3141 #endif 3142 } 3143 3144 enum { 3145 QEMU_PSCI_CONDUIT_DISABLED = 0, 3146 QEMU_PSCI_CONDUIT_SMC = 1, 3147 QEMU_PSCI_CONDUIT_HVC = 2, 3148 }; 3149 3150 #ifndef CONFIG_USER_ONLY 3151 /* Return the address space index to use for a memory access */ 3152 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3153 { 3154 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3155 } 3156 3157 /* Return the AddressSpace to use for a memory access 3158 * (which depends on whether the access is S or NS, and whether 3159 * the board gave us a separate AddressSpace for S accesses). 3160 */ 3161 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3162 { 3163 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3164 } 3165 #endif 3166 3167 /** 3168 * arm_register_pre_el_change_hook: 3169 * Register a hook function which will be called immediately before this 3170 * CPU changes exception level or mode. The hook function will be 3171 * passed a pointer to the ARMCPU and the opaque data pointer passed 3172 * to this function when the hook was registered. 3173 * 3174 * Note that if a pre-change hook is called, any registered post-change hooks 3175 * are guaranteed to subsequently be called. 3176 */ 3177 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3178 void *opaque); 3179 /** 3180 * arm_register_el_change_hook: 3181 * Register a hook function which will be called immediately after this 3182 * CPU changes exception level or mode. The hook function will be 3183 * passed a pointer to the ARMCPU and the opaque data pointer passed 3184 * to this function when the hook was registered. 3185 * 3186 * Note that any registered hooks registered here are guaranteed to be called 3187 * if pre-change hooks have been. 3188 */ 3189 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3190 *opaque); 3191 3192 /** 3193 * arm_rebuild_hflags: 3194 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3195 */ 3196 void arm_rebuild_hflags(CPUARMState *env); 3197 3198 /** 3199 * aa32_vfp_dreg: 3200 * Return a pointer to the Dn register within env in 32-bit mode. 3201 */ 3202 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3203 { 3204 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3205 } 3206 3207 /** 3208 * aa32_vfp_qreg: 3209 * Return a pointer to the Qn register within env in 32-bit mode. 3210 */ 3211 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3212 { 3213 return &env->vfp.zregs[regno].d[0]; 3214 } 3215 3216 /** 3217 * aa64_vfp_qreg: 3218 * Return a pointer to the Qn register within env in 64-bit mode. 3219 */ 3220 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3221 { 3222 return &env->vfp.zregs[regno].d[0]; 3223 } 3224 3225 /* Shared between translate-sve.c and sve_helper.c. */ 3226 extern const uint64_t pred_esz_masks[5]; 3227 3228 /* 3229 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3230 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3231 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3232 */ 3233 #define PAGE_BTI PAGE_TARGET_1 3234 #define PAGE_MTE PAGE_TARGET_2 3235 #define PAGE_TARGET_STICKY PAGE_MTE 3236 3237 /* We associate one allocation tag per 16 bytes, the minimum. */ 3238 #define LOG2_TAG_GRANULE 4 3239 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3240 3241 #endif 3242