1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #include "fpu/softfloat.h" 43 44 #define EXCP_UDEF 1 /* undefined instruction */ 45 #define EXCP_SWI 2 /* software interrupt */ 46 #define EXCP_PREFETCH_ABORT 3 47 #define EXCP_DATA_ABORT 4 48 #define EXCP_IRQ 5 49 #define EXCP_FIQ 6 50 #define EXCP_BKPT 7 51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 53 #define EXCP_HVC 11 /* HyperVisor Call */ 54 #define EXCP_HYP_TRAP 12 55 #define EXCP_SMC 13 /* Secure Monitor Call */ 56 #define EXCP_VIRQ 14 57 #define EXCP_VFIQ 15 58 #define EXCP_SEMIHOST 16 /* semihosting call */ 59 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 60 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 61 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 62 63 #define ARMV7M_EXCP_RESET 1 64 #define ARMV7M_EXCP_NMI 2 65 #define ARMV7M_EXCP_HARD 3 66 #define ARMV7M_EXCP_MEM 4 67 #define ARMV7M_EXCP_BUS 5 68 #define ARMV7M_EXCP_USAGE 6 69 #define ARMV7M_EXCP_SECURE 7 70 #define ARMV7M_EXCP_SVC 11 71 #define ARMV7M_EXCP_DEBUG 12 72 #define ARMV7M_EXCP_PENDSV 14 73 #define ARMV7M_EXCP_SYSTICK 15 74 75 /* For M profile, some registers are banked secure vs non-secure; 76 * these are represented as a 2-element array where the first element 77 * is the non-secure copy and the second is the secure copy. 78 * When the CPU does not have implement the security extension then 79 * only the first element is used. 80 * This means that the copy for the current security state can be 81 * accessed via env->registerfield[env->v7m.secure] (whether the security 82 * extension is implemented or not). 83 */ 84 enum { 85 M_REG_NS = 0, 86 M_REG_S = 1, 87 M_REG_NUM_BANKS = 2, 88 }; 89 90 /* ARM-specific interrupt pending bits. */ 91 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 92 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 93 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #ifdef HOST_WORDS_BIGENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 #define NB_MMU_MODES 7 116 /* ARM-specific extra insn start words: 117 * 1: Conditional execution bits 118 * 2: Partial exception syndrome for data aborts 119 */ 120 #define TARGET_INSN_START_EXTRA_WORDS 2 121 122 /* The 2nd extra word holding syndrome info for data aborts does not use 123 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 124 * help the sleb128 encoder do a better job. 125 * When restoring the CPU state, we shift it back up. 126 */ 127 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 128 #define ARM_INSN_START_WORD2_SHIFT 14 129 130 /* We currently assume float and double are IEEE single and double 131 precision respectively. 132 Doing runtime conversions is tricky because VFP registers may contain 133 integer values (eg. as the result of a FTOSI instruction). 134 s<2n> maps to the least significant half of d<n> 135 s<2n+1> maps to the most significant half of d<n> 136 */ 137 138 /* CPU state for each instance of a generic timer (in cp15 c14) */ 139 typedef struct ARMGenericTimer { 140 uint64_t cval; /* Timer CompareValue register */ 141 uint64_t ctl; /* Timer Control register */ 142 } ARMGenericTimer; 143 144 #define GTIMER_PHYS 0 145 #define GTIMER_VIRT 1 146 #define GTIMER_HYP 2 147 #define GTIMER_SEC 3 148 #define NUM_GTIMERS 4 149 150 typedef struct { 151 uint64_t raw_tcr; 152 uint32_t mask; 153 uint32_t base_mask; 154 } TCR; 155 156 typedef struct CPUARMState { 157 /* Regs for current mode. */ 158 uint32_t regs[16]; 159 160 /* 32/64 switch only happens when taking and returning from 161 * exceptions so the overlap semantics are taken care of then 162 * instead of having a complicated union. 163 */ 164 /* Regs for A64 mode. */ 165 uint64_t xregs[32]; 166 uint64_t pc; 167 /* PSTATE isn't an architectural register for ARMv8. However, it is 168 * convenient for us to assemble the underlying state into a 32 bit format 169 * identical to the architectural format used for the SPSR. (This is also 170 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 171 * 'pstate' register are.) Of the PSTATE bits: 172 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 173 * semantics as for AArch32, as described in the comments on each field) 174 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 175 * DAIF (exception masks) are kept in env->daif 176 * all other bits are stored in their correct places in env->pstate 177 */ 178 uint32_t pstate; 179 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 180 181 /* Frequently accessed CPSR bits are stored separately for efficiency. 182 This contains all the other bits. Use cpsr_{read,write} to access 183 the whole CPSR. */ 184 uint32_t uncached_cpsr; 185 uint32_t spsr; 186 187 /* Banked registers. */ 188 uint64_t banked_spsr[8]; 189 uint32_t banked_r13[8]; 190 uint32_t banked_r14[8]; 191 192 /* These hold r8-r12. */ 193 uint32_t usr_regs[5]; 194 uint32_t fiq_regs[5]; 195 196 /* cpsr flag cache for faster execution */ 197 uint32_t CF; /* 0 or 1 */ 198 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 199 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 200 uint32_t ZF; /* Z set if zero. */ 201 uint32_t QF; /* 0 or 1 */ 202 uint32_t GE; /* cpsr[19:16] */ 203 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 204 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 205 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 206 207 uint64_t elr_el[4]; /* AArch64 exception link regs */ 208 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 209 210 /* System control coprocessor (cp15) */ 211 struct { 212 uint32_t c0_cpuid; 213 union { /* Cache size selection */ 214 struct { 215 uint64_t _unused_csselr0; 216 uint64_t csselr_ns; 217 uint64_t _unused_csselr1; 218 uint64_t csselr_s; 219 }; 220 uint64_t csselr_el[4]; 221 }; 222 union { /* System control register. */ 223 struct { 224 uint64_t _unused_sctlr; 225 uint64_t sctlr_ns; 226 uint64_t hsctlr; 227 uint64_t sctlr_s; 228 }; 229 uint64_t sctlr_el[4]; 230 }; 231 uint64_t cpacr_el1; /* Architectural feature access control register */ 232 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 233 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 234 uint64_t sder; /* Secure debug enable register. */ 235 uint32_t nsacr; /* Non-secure access control register. */ 236 union { /* MMU translation table base 0. */ 237 struct { 238 uint64_t _unused_ttbr0_0; 239 uint64_t ttbr0_ns; 240 uint64_t _unused_ttbr0_1; 241 uint64_t ttbr0_s; 242 }; 243 uint64_t ttbr0_el[4]; 244 }; 245 union { /* MMU translation table base 1. */ 246 struct { 247 uint64_t _unused_ttbr1_0; 248 uint64_t ttbr1_ns; 249 uint64_t _unused_ttbr1_1; 250 uint64_t ttbr1_s; 251 }; 252 uint64_t ttbr1_el[4]; 253 }; 254 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 255 /* MMU translation table base control. */ 256 TCR tcr_el[4]; 257 TCR vtcr_el2; /* Virtualization Translation Control. */ 258 uint32_t c2_data; /* MPU data cacheable bits. */ 259 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 260 union { /* MMU domain access control register 261 * MPU write buffer control. 262 */ 263 struct { 264 uint64_t dacr_ns; 265 uint64_t dacr_s; 266 }; 267 struct { 268 uint64_t dacr32_el2; 269 }; 270 }; 271 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 272 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 273 uint64_t hcr_el2; /* Hypervisor configuration register */ 274 uint64_t scr_el3; /* Secure configuration register. */ 275 union { /* Fault status registers. */ 276 struct { 277 uint64_t ifsr_ns; 278 uint64_t ifsr_s; 279 }; 280 struct { 281 uint64_t ifsr32_el2; 282 }; 283 }; 284 union { 285 struct { 286 uint64_t _unused_dfsr; 287 uint64_t dfsr_ns; 288 uint64_t hsr; 289 uint64_t dfsr_s; 290 }; 291 uint64_t esr_el[4]; 292 }; 293 uint32_t c6_region[8]; /* MPU base/size registers. */ 294 union { /* Fault address registers. */ 295 struct { 296 uint64_t _unused_far0; 297 #ifdef HOST_WORDS_BIGENDIAN 298 uint32_t ifar_ns; 299 uint32_t dfar_ns; 300 uint32_t ifar_s; 301 uint32_t dfar_s; 302 #else 303 uint32_t dfar_ns; 304 uint32_t ifar_ns; 305 uint32_t dfar_s; 306 uint32_t ifar_s; 307 #endif 308 uint64_t _unused_far3; 309 }; 310 uint64_t far_el[4]; 311 }; 312 uint64_t hpfar_el2; 313 uint64_t hstr_el2; 314 union { /* Translation result. */ 315 struct { 316 uint64_t _unused_par_0; 317 uint64_t par_ns; 318 uint64_t _unused_par_1; 319 uint64_t par_s; 320 }; 321 uint64_t par_el[4]; 322 }; 323 324 uint32_t c9_insn; /* Cache lockdown registers. */ 325 uint32_t c9_data; 326 uint64_t c9_pmcr; /* performance monitor control register */ 327 uint64_t c9_pmcnten; /* perf monitor counter enables */ 328 uint32_t c9_pmovsr; /* perf monitor overflow status */ 329 uint32_t c9_pmuserenr; /* perf monitor user enable */ 330 uint64_t c9_pmselr; /* perf monitor counter selection register */ 331 uint64_t c9_pminten; /* perf monitor interrupt enables */ 332 union { /* Memory attribute redirection */ 333 struct { 334 #ifdef HOST_WORDS_BIGENDIAN 335 uint64_t _unused_mair_0; 336 uint32_t mair1_ns; 337 uint32_t mair0_ns; 338 uint64_t _unused_mair_1; 339 uint32_t mair1_s; 340 uint32_t mair0_s; 341 #else 342 uint64_t _unused_mair_0; 343 uint32_t mair0_ns; 344 uint32_t mair1_ns; 345 uint64_t _unused_mair_1; 346 uint32_t mair0_s; 347 uint32_t mair1_s; 348 #endif 349 }; 350 uint64_t mair_el[4]; 351 }; 352 union { /* vector base address register */ 353 struct { 354 uint64_t _unused_vbar; 355 uint64_t vbar_ns; 356 uint64_t hvbar; 357 uint64_t vbar_s; 358 }; 359 uint64_t vbar_el[4]; 360 }; 361 uint32_t mvbar; /* (monitor) vector base address register */ 362 struct { /* FCSE PID. */ 363 uint32_t fcseidr_ns; 364 uint32_t fcseidr_s; 365 }; 366 union { /* Context ID. */ 367 struct { 368 uint64_t _unused_contextidr_0; 369 uint64_t contextidr_ns; 370 uint64_t _unused_contextidr_1; 371 uint64_t contextidr_s; 372 }; 373 uint64_t contextidr_el[4]; 374 }; 375 union { /* User RW Thread register. */ 376 struct { 377 uint64_t tpidrurw_ns; 378 uint64_t tpidrprw_ns; 379 uint64_t htpidr; 380 uint64_t _tpidr_el3; 381 }; 382 uint64_t tpidr_el[4]; 383 }; 384 /* The secure banks of these registers don't map anywhere */ 385 uint64_t tpidrurw_s; 386 uint64_t tpidrprw_s; 387 uint64_t tpidruro_s; 388 389 union { /* User RO Thread register. */ 390 uint64_t tpidruro_ns; 391 uint64_t tpidrro_el[1]; 392 }; 393 uint64_t c14_cntfrq; /* Counter Frequency register */ 394 uint64_t c14_cntkctl; /* Timer Control register */ 395 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 396 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 397 ARMGenericTimer c14_timer[NUM_GTIMERS]; 398 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 399 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 400 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 401 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 402 uint32_t c15_threadid; /* TI debugger thread-ID. */ 403 uint32_t c15_config_base_address; /* SCU base address. */ 404 uint32_t c15_diagnostic; /* diagnostic register */ 405 uint32_t c15_power_diagnostic; 406 uint32_t c15_power_control; /* power control */ 407 uint64_t dbgbvr[16]; /* breakpoint value registers */ 408 uint64_t dbgbcr[16]; /* breakpoint control registers */ 409 uint64_t dbgwvr[16]; /* watchpoint value registers */ 410 uint64_t dbgwcr[16]; /* watchpoint control registers */ 411 uint64_t mdscr_el1; 412 uint64_t oslsr_el1; /* OS Lock Status */ 413 uint64_t mdcr_el2; 414 uint64_t mdcr_el3; 415 /* If the counter is enabled, this stores the last time the counter 416 * was reset. Otherwise it stores the counter value 417 */ 418 uint64_t c15_ccnt; 419 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 420 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 421 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 422 } cp15; 423 424 struct { 425 /* M profile has up to 4 stack pointers: 426 * a Main Stack Pointer and a Process Stack Pointer for each 427 * of the Secure and Non-Secure states. (If the CPU doesn't support 428 * the security extension then it has only two SPs.) 429 * In QEMU we always store the currently active SP in regs[13], 430 * and the non-active SP for the current security state in 431 * v7m.other_sp. The stack pointers for the inactive security state 432 * are stored in other_ss_msp and other_ss_psp. 433 * switch_v7m_security_state() is responsible for rearranging them 434 * when we change security state. 435 */ 436 uint32_t other_sp; 437 uint32_t other_ss_msp; 438 uint32_t other_ss_psp; 439 uint32_t vecbase[M_REG_NUM_BANKS]; 440 uint32_t basepri[M_REG_NUM_BANKS]; 441 uint32_t control[M_REG_NUM_BANKS]; 442 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 443 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 444 uint32_t hfsr; /* HardFault Status */ 445 uint32_t dfsr; /* Debug Fault Status Register */ 446 uint32_t sfsr; /* Secure Fault Status Register */ 447 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 448 uint32_t bfar; /* BusFault Address */ 449 uint32_t sfar; /* Secure Fault Address Register */ 450 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 451 int exception; 452 uint32_t primask[M_REG_NUM_BANKS]; 453 uint32_t faultmask[M_REG_NUM_BANKS]; 454 uint32_t aircr; /* only holds r/w state if security extn implemented */ 455 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 456 } v7m; 457 458 /* Information associated with an exception about to be taken: 459 * code which raises an exception must set cs->exception_index and 460 * the relevant parts of this structure; the cpu_do_interrupt function 461 * will then set the guest-visible registers as part of the exception 462 * entry process. 463 */ 464 struct { 465 uint32_t syndrome; /* AArch64 format syndrome register */ 466 uint32_t fsr; /* AArch32 format fault status register info */ 467 uint64_t vaddress; /* virtual addr associated with exception, if any */ 468 uint32_t target_el; /* EL the exception should be targeted for */ 469 /* If we implement EL2 we will also need to store information 470 * about the intermediate physical address for stage 2 faults. 471 */ 472 } exception; 473 474 /* Thumb-2 EE state. */ 475 uint32_t teecr; 476 uint32_t teehbr; 477 478 /* VFP coprocessor state. */ 479 struct { 480 /* VFP/Neon register state. Note that the mapping between S, D and Q 481 * views of the register bank differs between AArch64 and AArch32: 482 * In AArch32: 483 * Qn = regs[2n+1]:regs[2n] 484 * Dn = regs[n] 485 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n 486 * (and regs[32] to regs[63] are inaccessible) 487 * In AArch64: 488 * Qn = regs[2n+1]:regs[2n] 489 * Dn = regs[2n] 490 * Sn = regs[2n] bits 31..0 491 * This corresponds to the architecturally defined mapping between 492 * the two execution states, and means we do not need to explicitly 493 * map these registers when changing states. 494 */ 495 float64 regs[64]; 496 497 uint32_t xregs[16]; 498 /* We store these fpcsr fields separately for convenience. */ 499 int vec_len; 500 int vec_stride; 501 502 /* scratch space when Tn are not sufficient. */ 503 uint32_t scratch[8]; 504 505 /* fp_status is the "normal" fp status. standard_fp_status retains 506 * values corresponding to the ARM "Standard FPSCR Value", ie 507 * default-NaN, flush-to-zero, round-to-nearest and is used by 508 * any operations (generally Neon) which the architecture defines 509 * as controlled by the standard FPSCR value rather than the FPSCR. 510 * 511 * To avoid having to transfer exception bits around, we simply 512 * say that the FPSCR cumulative exception flags are the logical 513 * OR of the flags in the two fp statuses. This relies on the 514 * only thing which needs to read the exception flags being 515 * an explicit FPSCR read. 516 */ 517 float_status fp_status; 518 float_status standard_fp_status; 519 } vfp; 520 uint64_t exclusive_addr; 521 uint64_t exclusive_val; 522 uint64_t exclusive_high; 523 524 /* iwMMXt coprocessor state. */ 525 struct { 526 uint64_t regs[16]; 527 uint64_t val; 528 529 uint32_t cregs[16]; 530 } iwmmxt; 531 532 #if defined(CONFIG_USER_ONLY) 533 /* For usermode syscall translation. */ 534 int eabi; 535 #endif 536 537 struct CPUBreakpoint *cpu_breakpoint[16]; 538 struct CPUWatchpoint *cpu_watchpoint[16]; 539 540 /* Fields up to this point are cleared by a CPU reset */ 541 struct {} end_reset_fields; 542 543 CPU_COMMON 544 545 /* Fields after CPU_COMMON are preserved across CPU reset. */ 546 547 /* Internal CPU feature flags. */ 548 uint64_t features; 549 550 /* PMSAv7 MPU */ 551 struct { 552 uint32_t *drbar; 553 uint32_t *drsr; 554 uint32_t *dracr; 555 uint32_t rnr[M_REG_NUM_BANKS]; 556 } pmsav7; 557 558 /* PMSAv8 MPU */ 559 struct { 560 /* The PMSAv8 implementation also shares some PMSAv7 config 561 * and state: 562 * pmsav7.rnr (region number register) 563 * pmsav7_dregion (number of configured regions) 564 */ 565 uint32_t *rbar[M_REG_NUM_BANKS]; 566 uint32_t *rlar[M_REG_NUM_BANKS]; 567 uint32_t mair0[M_REG_NUM_BANKS]; 568 uint32_t mair1[M_REG_NUM_BANKS]; 569 } pmsav8; 570 571 void *nvic; 572 const struct arm_boot_info *boot_info; 573 /* Store GICv3CPUState to access from this struct */ 574 void *gicv3state; 575 } CPUARMState; 576 577 /** 578 * ARMELChangeHook: 579 * type of a function which can be registered via arm_register_el_change_hook() 580 * to get callbacks when the CPU changes its exception level or mode. 581 */ 582 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); 583 584 585 /* These values map onto the return values for 586 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 587 typedef enum ARMPSCIState { 588 PSCI_ON = 0, 589 PSCI_OFF = 1, 590 PSCI_ON_PENDING = 2 591 } ARMPSCIState; 592 593 /** 594 * ARMCPU: 595 * @env: #CPUARMState 596 * 597 * An ARM CPU core. 598 */ 599 struct ARMCPU { 600 /*< private >*/ 601 CPUState parent_obj; 602 /*< public >*/ 603 604 CPUARMState env; 605 606 /* Coprocessor information */ 607 GHashTable *cp_regs; 608 /* For marshalling (mostly coprocessor) register state between the 609 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 610 * we use these arrays. 611 */ 612 /* List of register indexes managed via these arrays; (full KVM style 613 * 64 bit indexes, not CPRegInfo 32 bit indexes) 614 */ 615 uint64_t *cpreg_indexes; 616 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 617 uint64_t *cpreg_values; 618 /* Length of the indexes, values, reset_values arrays */ 619 int32_t cpreg_array_len; 620 /* These are used only for migration: incoming data arrives in 621 * these fields and is sanity checked in post_load before copying 622 * to the working data structures above. 623 */ 624 uint64_t *cpreg_vmstate_indexes; 625 uint64_t *cpreg_vmstate_values; 626 int32_t cpreg_vmstate_array_len; 627 628 /* Timers used by the generic (architected) timer */ 629 QEMUTimer *gt_timer[NUM_GTIMERS]; 630 /* GPIO outputs for generic timer */ 631 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 632 /* GPIO output for GICv3 maintenance interrupt signal */ 633 qemu_irq gicv3_maintenance_interrupt; 634 /* GPIO output for the PMU interrupt */ 635 qemu_irq pmu_interrupt; 636 637 /* MemoryRegion to use for secure physical accesses */ 638 MemoryRegion *secure_memory; 639 640 /* 'compatible' string for this CPU for Linux device trees */ 641 const char *dtb_compatible; 642 643 /* PSCI version for this CPU 644 * Bits[31:16] = Major Version 645 * Bits[15:0] = Minor Version 646 */ 647 uint32_t psci_version; 648 649 /* Should CPU start in PSCI powered-off state? */ 650 bool start_powered_off; 651 652 /* Current power state, access guarded by BQL */ 653 ARMPSCIState power_state; 654 655 /* CPU has virtualization extension */ 656 bool has_el2; 657 /* CPU has security extension */ 658 bool has_el3; 659 /* CPU has PMU (Performance Monitor Unit) */ 660 bool has_pmu; 661 662 /* CPU has memory protection unit */ 663 bool has_mpu; 664 /* PMSAv7 MPU number of supported regions */ 665 uint32_t pmsav7_dregion; 666 667 /* PSCI conduit used to invoke PSCI methods 668 * 0 - disabled, 1 - smc, 2 - hvc 669 */ 670 uint32_t psci_conduit; 671 672 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 673 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 674 */ 675 uint32_t kvm_target; 676 677 /* KVM init features for this CPU */ 678 uint32_t kvm_init_features[7]; 679 680 /* Uniprocessor system with MP extensions */ 681 bool mp_is_up; 682 683 /* The instance init functions for implementation-specific subclasses 684 * set these fields to specify the implementation-dependent values of 685 * various constant registers and reset values of non-constant 686 * registers. 687 * Some of these might become QOM properties eventually. 688 * Field names match the official register names as defined in the 689 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 690 * is used for reset values of non-constant registers; no reset_ 691 * prefix means a constant register. 692 */ 693 uint32_t midr; 694 uint32_t revidr; 695 uint32_t reset_fpsid; 696 uint32_t mvfr0; 697 uint32_t mvfr1; 698 uint32_t mvfr2; 699 uint32_t ctr; 700 uint32_t reset_sctlr; 701 uint32_t id_pfr0; 702 uint32_t id_pfr1; 703 uint32_t id_dfr0; 704 uint32_t pmceid0; 705 uint32_t pmceid1; 706 uint32_t id_afr0; 707 uint32_t id_mmfr0; 708 uint32_t id_mmfr1; 709 uint32_t id_mmfr2; 710 uint32_t id_mmfr3; 711 uint32_t id_mmfr4; 712 uint32_t id_isar0; 713 uint32_t id_isar1; 714 uint32_t id_isar2; 715 uint32_t id_isar3; 716 uint32_t id_isar4; 717 uint32_t id_isar5; 718 uint64_t id_aa64pfr0; 719 uint64_t id_aa64pfr1; 720 uint64_t id_aa64dfr0; 721 uint64_t id_aa64dfr1; 722 uint64_t id_aa64afr0; 723 uint64_t id_aa64afr1; 724 uint64_t id_aa64isar0; 725 uint64_t id_aa64isar1; 726 uint64_t id_aa64mmfr0; 727 uint64_t id_aa64mmfr1; 728 uint32_t dbgdidr; 729 uint32_t clidr; 730 uint64_t mp_affinity; /* MP ID without feature bits */ 731 /* The elements of this array are the CCSIDR values for each cache, 732 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 733 */ 734 uint32_t ccsidr[16]; 735 uint64_t reset_cbar; 736 uint32_t reset_auxcr; 737 bool reset_hivecs; 738 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 739 uint32_t dcz_blocksize; 740 uint64_t rvbar; 741 742 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 743 int gic_num_lrs; /* number of list registers */ 744 int gic_vpribits; /* number of virtual priority bits */ 745 int gic_vprebits; /* number of virtual preemption bits */ 746 747 /* Whether the cfgend input is high (i.e. this CPU should reset into 748 * big-endian mode). This setting isn't used directly: instead it modifies 749 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 750 * architecture version. 751 */ 752 bool cfgend; 753 754 ARMELChangeHook *el_change_hook; 755 void *el_change_hook_opaque; 756 757 int32_t node_id; /* NUMA node this CPU belongs to */ 758 759 /* Used to synchronize KVM and QEMU in-kernel device levels */ 760 uint8_t device_irq_level; 761 }; 762 763 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 764 { 765 return container_of(env, ARMCPU, env); 766 } 767 768 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 769 770 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 771 772 #define ENV_OFFSET offsetof(ARMCPU, env) 773 774 #ifndef CONFIG_USER_ONLY 775 extern const struct VMStateDescription vmstate_arm_cpu; 776 #endif 777 778 void arm_cpu_do_interrupt(CPUState *cpu); 779 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 780 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 781 782 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 783 int flags); 784 785 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 786 MemTxAttrs *attrs); 787 788 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 789 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 790 791 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 792 int cpuid, void *opaque); 793 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 794 int cpuid, void *opaque); 795 796 #ifdef TARGET_AARCH64 797 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 798 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 799 #endif 800 801 target_ulong do_arm_semihosting(CPUARMState *env); 802 void aarch64_sync_32_to_64(CPUARMState *env); 803 void aarch64_sync_64_to_32(CPUARMState *env); 804 805 static inline bool is_a64(CPUARMState *env) 806 { 807 return env->aarch64; 808 } 809 810 /* you can call this signal handler from your SIGBUS and SIGSEGV 811 signal handlers to inform the virtual CPU of exceptions. non zero 812 is returned if the signal was handled by the virtual CPU. */ 813 int cpu_arm_signal_handler(int host_signum, void *pinfo, 814 void *puc); 815 816 /** 817 * pmccntr_sync 818 * @env: CPUARMState 819 * 820 * Synchronises the counter in the PMCCNTR. This must always be called twice, 821 * once before any action that might affect the timer and again afterwards. 822 * The function is used to swap the state of the register if required. 823 * This only happens when not in user mode (!CONFIG_USER_ONLY) 824 */ 825 void pmccntr_sync(CPUARMState *env); 826 827 /* SCTLR bit meanings. Several bits have been reused in newer 828 * versions of the architecture; in that case we define constants 829 * for both old and new bit meanings. Code which tests against those 830 * bits should probably check or otherwise arrange that the CPU 831 * is the architectural version it expects. 832 */ 833 #define SCTLR_M (1U << 0) 834 #define SCTLR_A (1U << 1) 835 #define SCTLR_C (1U << 2) 836 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 837 #define SCTLR_SA (1U << 3) 838 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 839 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 840 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 841 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 842 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 843 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 844 #define SCTLR_ITD (1U << 7) /* v8 onward */ 845 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 846 #define SCTLR_SED (1U << 8) /* v8 onward */ 847 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 848 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 849 #define SCTLR_F (1U << 10) /* up to v6 */ 850 #define SCTLR_SW (1U << 10) /* v7 onward */ 851 #define SCTLR_Z (1U << 11) 852 #define SCTLR_I (1U << 12) 853 #define SCTLR_V (1U << 13) 854 #define SCTLR_RR (1U << 14) /* up to v7 */ 855 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 856 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 857 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 858 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 859 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 860 #define SCTLR_HA (1U << 17) 861 #define SCTLR_BR (1U << 17) /* PMSA only */ 862 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 863 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 864 #define SCTLR_WXN (1U << 19) 865 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 866 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 867 #define SCTLR_FI (1U << 21) 868 #define SCTLR_U (1U << 22) 869 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 870 #define SCTLR_VE (1U << 24) /* up to v7 */ 871 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 872 #define SCTLR_EE (1U << 25) 873 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 874 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 875 #define SCTLR_NMFI (1U << 27) 876 #define SCTLR_TRE (1U << 28) 877 #define SCTLR_AFE (1U << 29) 878 #define SCTLR_TE (1U << 30) 879 880 #define CPTR_TCPAC (1U << 31) 881 #define CPTR_TTA (1U << 20) 882 #define CPTR_TFP (1U << 10) 883 884 #define MDCR_EPMAD (1U << 21) 885 #define MDCR_EDAD (1U << 20) 886 #define MDCR_SPME (1U << 17) 887 #define MDCR_SDD (1U << 16) 888 #define MDCR_SPD (3U << 14) 889 #define MDCR_TDRA (1U << 11) 890 #define MDCR_TDOSA (1U << 10) 891 #define MDCR_TDA (1U << 9) 892 #define MDCR_TDE (1U << 8) 893 #define MDCR_HPME (1U << 7) 894 #define MDCR_TPM (1U << 6) 895 #define MDCR_TPMCR (1U << 5) 896 897 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 898 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 899 900 #define CPSR_M (0x1fU) 901 #define CPSR_T (1U << 5) 902 #define CPSR_F (1U << 6) 903 #define CPSR_I (1U << 7) 904 #define CPSR_A (1U << 8) 905 #define CPSR_E (1U << 9) 906 #define CPSR_IT_2_7 (0xfc00U) 907 #define CPSR_GE (0xfU << 16) 908 #define CPSR_IL (1U << 20) 909 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 910 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 911 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 912 * where it is live state but not accessible to the AArch32 code. 913 */ 914 #define CPSR_RESERVED (0x7U << 21) 915 #define CPSR_J (1U << 24) 916 #define CPSR_IT_0_1 (3U << 25) 917 #define CPSR_Q (1U << 27) 918 #define CPSR_V (1U << 28) 919 #define CPSR_C (1U << 29) 920 #define CPSR_Z (1U << 30) 921 #define CPSR_N (1U << 31) 922 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 923 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 924 925 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 926 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 927 | CPSR_NZCV) 928 /* Bits writable in user mode. */ 929 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 930 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 931 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 932 /* Mask of bits which may be set by exception return copying them from SPSR */ 933 #define CPSR_ERET_MASK (~CPSR_RESERVED) 934 935 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 936 #define XPSR_EXCP 0x1ffU 937 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 938 #define XPSR_IT_2_7 CPSR_IT_2_7 939 #define XPSR_GE CPSR_GE 940 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 941 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 942 #define XPSR_IT_0_1 CPSR_IT_0_1 943 #define XPSR_Q CPSR_Q 944 #define XPSR_V CPSR_V 945 #define XPSR_C CPSR_C 946 #define XPSR_Z CPSR_Z 947 #define XPSR_N CPSR_N 948 #define XPSR_NZCV CPSR_NZCV 949 #define XPSR_IT CPSR_IT 950 951 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 952 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 953 #define TTBCR_PD0 (1U << 4) 954 #define TTBCR_PD1 (1U << 5) 955 #define TTBCR_EPD0 (1U << 7) 956 #define TTBCR_IRGN0 (3U << 8) 957 #define TTBCR_ORGN0 (3U << 10) 958 #define TTBCR_SH0 (3U << 12) 959 #define TTBCR_T1SZ (3U << 16) 960 #define TTBCR_A1 (1U << 22) 961 #define TTBCR_EPD1 (1U << 23) 962 #define TTBCR_IRGN1 (3U << 24) 963 #define TTBCR_ORGN1 (3U << 26) 964 #define TTBCR_SH1 (1U << 28) 965 #define TTBCR_EAE (1U << 31) 966 967 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 968 * Only these are valid when in AArch64 mode; in 969 * AArch32 mode SPSRs are basically CPSR-format. 970 */ 971 #define PSTATE_SP (1U) 972 #define PSTATE_M (0xFU) 973 #define PSTATE_nRW (1U << 4) 974 #define PSTATE_F (1U << 6) 975 #define PSTATE_I (1U << 7) 976 #define PSTATE_A (1U << 8) 977 #define PSTATE_D (1U << 9) 978 #define PSTATE_IL (1U << 20) 979 #define PSTATE_SS (1U << 21) 980 #define PSTATE_V (1U << 28) 981 #define PSTATE_C (1U << 29) 982 #define PSTATE_Z (1U << 30) 983 #define PSTATE_N (1U << 31) 984 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 985 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 986 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 987 /* Mode values for AArch64 */ 988 #define PSTATE_MODE_EL3h 13 989 #define PSTATE_MODE_EL3t 12 990 #define PSTATE_MODE_EL2h 9 991 #define PSTATE_MODE_EL2t 8 992 #define PSTATE_MODE_EL1h 5 993 #define PSTATE_MODE_EL1t 4 994 #define PSTATE_MODE_EL0t 0 995 996 /* Write a new value to v7m.exception, thus transitioning into or out 997 * of Handler mode; this may result in a change of active stack pointer. 998 */ 999 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1000 1001 /* Map EL and handler into a PSTATE_MODE. */ 1002 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1003 { 1004 return (el << 2) | handler; 1005 } 1006 1007 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1008 * interprocessing, so we don't attempt to sync with the cpsr state used by 1009 * the 32 bit decoder. 1010 */ 1011 static inline uint32_t pstate_read(CPUARMState *env) 1012 { 1013 int ZF; 1014 1015 ZF = (env->ZF == 0); 1016 return (env->NF & 0x80000000) | (ZF << 30) 1017 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1018 | env->pstate | env->daif; 1019 } 1020 1021 static inline void pstate_write(CPUARMState *env, uint32_t val) 1022 { 1023 env->ZF = (~val) & PSTATE_Z; 1024 env->NF = val; 1025 env->CF = (val >> 29) & 1; 1026 env->VF = (val << 3) & 0x80000000; 1027 env->daif = val & PSTATE_DAIF; 1028 env->pstate = val & ~CACHED_PSTATE_BITS; 1029 } 1030 1031 /* Return the current CPSR value. */ 1032 uint32_t cpsr_read(CPUARMState *env); 1033 1034 typedef enum CPSRWriteType { 1035 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1036 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1037 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1038 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1039 } CPSRWriteType; 1040 1041 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1042 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1043 CPSRWriteType write_type); 1044 1045 /* Return the current xPSR value. */ 1046 static inline uint32_t xpsr_read(CPUARMState *env) 1047 { 1048 int ZF; 1049 ZF = (env->ZF == 0); 1050 return (env->NF & 0x80000000) | (ZF << 30) 1051 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1052 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1053 | ((env->condexec_bits & 0xfc) << 8) 1054 | env->v7m.exception; 1055 } 1056 1057 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1058 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1059 { 1060 if (mask & XPSR_NZCV) { 1061 env->ZF = (~val) & XPSR_Z; 1062 env->NF = val; 1063 env->CF = (val >> 29) & 1; 1064 env->VF = (val << 3) & 0x80000000; 1065 } 1066 if (mask & XPSR_Q) { 1067 env->QF = ((val & XPSR_Q) != 0); 1068 } 1069 if (mask & XPSR_T) { 1070 env->thumb = ((val & XPSR_T) != 0); 1071 } 1072 if (mask & XPSR_IT_0_1) { 1073 env->condexec_bits &= ~3; 1074 env->condexec_bits |= (val >> 25) & 3; 1075 } 1076 if (mask & XPSR_IT_2_7) { 1077 env->condexec_bits &= 3; 1078 env->condexec_bits |= (val >> 8) & 0xfc; 1079 } 1080 if (mask & XPSR_EXCP) { 1081 /* Note that this only happens on exception exit */ 1082 write_v7m_exception(env, val & XPSR_EXCP); 1083 } 1084 } 1085 1086 #define HCR_VM (1ULL << 0) 1087 #define HCR_SWIO (1ULL << 1) 1088 #define HCR_PTW (1ULL << 2) 1089 #define HCR_FMO (1ULL << 3) 1090 #define HCR_IMO (1ULL << 4) 1091 #define HCR_AMO (1ULL << 5) 1092 #define HCR_VF (1ULL << 6) 1093 #define HCR_VI (1ULL << 7) 1094 #define HCR_VSE (1ULL << 8) 1095 #define HCR_FB (1ULL << 9) 1096 #define HCR_BSU_MASK (3ULL << 10) 1097 #define HCR_DC (1ULL << 12) 1098 #define HCR_TWI (1ULL << 13) 1099 #define HCR_TWE (1ULL << 14) 1100 #define HCR_TID0 (1ULL << 15) 1101 #define HCR_TID1 (1ULL << 16) 1102 #define HCR_TID2 (1ULL << 17) 1103 #define HCR_TID3 (1ULL << 18) 1104 #define HCR_TSC (1ULL << 19) 1105 #define HCR_TIDCP (1ULL << 20) 1106 #define HCR_TACR (1ULL << 21) 1107 #define HCR_TSW (1ULL << 22) 1108 #define HCR_TPC (1ULL << 23) 1109 #define HCR_TPU (1ULL << 24) 1110 #define HCR_TTLB (1ULL << 25) 1111 #define HCR_TVM (1ULL << 26) 1112 #define HCR_TGE (1ULL << 27) 1113 #define HCR_TDZ (1ULL << 28) 1114 #define HCR_HCD (1ULL << 29) 1115 #define HCR_TRVM (1ULL << 30) 1116 #define HCR_RW (1ULL << 31) 1117 #define HCR_CD (1ULL << 32) 1118 #define HCR_ID (1ULL << 33) 1119 #define HCR_MASK ((1ULL << 34) - 1) 1120 1121 #define SCR_NS (1U << 0) 1122 #define SCR_IRQ (1U << 1) 1123 #define SCR_FIQ (1U << 2) 1124 #define SCR_EA (1U << 3) 1125 #define SCR_FW (1U << 4) 1126 #define SCR_AW (1U << 5) 1127 #define SCR_NET (1U << 6) 1128 #define SCR_SMD (1U << 7) 1129 #define SCR_HCE (1U << 8) 1130 #define SCR_SIF (1U << 9) 1131 #define SCR_RW (1U << 10) 1132 #define SCR_ST (1U << 11) 1133 #define SCR_TWI (1U << 12) 1134 #define SCR_TWE (1U << 13) 1135 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1136 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1137 1138 /* Return the current FPSCR value. */ 1139 uint32_t vfp_get_fpscr(CPUARMState *env); 1140 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1141 1142 /* For A64 the FPSCR is split into two logically distinct registers, 1143 * FPCR and FPSR. However since they still use non-overlapping bits 1144 * we store the underlying state in fpscr and just mask on read/write. 1145 */ 1146 #define FPSR_MASK 0xf800009f 1147 #define FPCR_MASK 0x07f79f00 1148 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1149 { 1150 return vfp_get_fpscr(env) & FPSR_MASK; 1151 } 1152 1153 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1154 { 1155 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1156 vfp_set_fpscr(env, new_fpscr); 1157 } 1158 1159 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1160 { 1161 return vfp_get_fpscr(env) & FPCR_MASK; 1162 } 1163 1164 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1165 { 1166 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1167 vfp_set_fpscr(env, new_fpscr); 1168 } 1169 1170 enum arm_cpu_mode { 1171 ARM_CPU_MODE_USR = 0x10, 1172 ARM_CPU_MODE_FIQ = 0x11, 1173 ARM_CPU_MODE_IRQ = 0x12, 1174 ARM_CPU_MODE_SVC = 0x13, 1175 ARM_CPU_MODE_MON = 0x16, 1176 ARM_CPU_MODE_ABT = 0x17, 1177 ARM_CPU_MODE_HYP = 0x1a, 1178 ARM_CPU_MODE_UND = 0x1b, 1179 ARM_CPU_MODE_SYS = 0x1f 1180 }; 1181 1182 /* VFP system registers. */ 1183 #define ARM_VFP_FPSID 0 1184 #define ARM_VFP_FPSCR 1 1185 #define ARM_VFP_MVFR2 5 1186 #define ARM_VFP_MVFR1 6 1187 #define ARM_VFP_MVFR0 7 1188 #define ARM_VFP_FPEXC 8 1189 #define ARM_VFP_FPINST 9 1190 #define ARM_VFP_FPINST2 10 1191 1192 /* iwMMXt coprocessor control registers. */ 1193 #define ARM_IWMMXT_wCID 0 1194 #define ARM_IWMMXT_wCon 1 1195 #define ARM_IWMMXT_wCSSF 2 1196 #define ARM_IWMMXT_wCASF 3 1197 #define ARM_IWMMXT_wCGR0 8 1198 #define ARM_IWMMXT_wCGR1 9 1199 #define ARM_IWMMXT_wCGR2 10 1200 #define ARM_IWMMXT_wCGR3 11 1201 1202 /* V7M CCR bits */ 1203 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1204 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1205 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1206 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1207 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1208 FIELD(V7M_CCR, STKALIGN, 9, 1) 1209 FIELD(V7M_CCR, DC, 16, 1) 1210 FIELD(V7M_CCR, IC, 17, 1) 1211 1212 /* V7M AIRCR bits */ 1213 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1214 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1215 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1216 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1217 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1218 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1219 FIELD(V7M_AIRCR, PRIS, 14, 1) 1220 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1221 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1222 1223 /* V7M CFSR bits for MMFSR */ 1224 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1225 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1226 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1227 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1228 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1229 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1230 1231 /* V7M CFSR bits for BFSR */ 1232 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1233 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1234 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1235 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1236 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1237 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1238 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1239 1240 /* V7M CFSR bits for UFSR */ 1241 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1242 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1243 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1244 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1245 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1246 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1247 1248 /* V7M CFSR bit masks covering all of the subregister bits */ 1249 FIELD(V7M_CFSR, MMFSR, 0, 8) 1250 FIELD(V7M_CFSR, BFSR, 8, 8) 1251 FIELD(V7M_CFSR, UFSR, 16, 16) 1252 1253 /* V7M HFSR bits */ 1254 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1255 FIELD(V7M_HFSR, FORCED, 30, 1) 1256 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1257 1258 /* V7M DFSR bits */ 1259 FIELD(V7M_DFSR, HALTED, 0, 1) 1260 FIELD(V7M_DFSR, BKPT, 1, 1) 1261 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1262 FIELD(V7M_DFSR, VCATCH, 3, 1) 1263 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1264 1265 /* V7M SFSR bits */ 1266 FIELD(V7M_SFSR, INVEP, 0, 1) 1267 FIELD(V7M_SFSR, INVIS, 1, 1) 1268 FIELD(V7M_SFSR, INVER, 2, 1) 1269 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1270 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1271 FIELD(V7M_SFSR, LSPERR, 5, 1) 1272 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1273 FIELD(V7M_SFSR, LSERR, 7, 1) 1274 1275 /* v7M MPU_CTRL bits */ 1276 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1277 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1278 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1279 1280 /* If adding a feature bit which corresponds to a Linux ELF 1281 * HWCAP bit, remember to update the feature-bit-to-hwcap 1282 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1283 */ 1284 enum arm_features { 1285 ARM_FEATURE_VFP, 1286 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1287 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1288 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1289 ARM_FEATURE_V6, 1290 ARM_FEATURE_V6K, 1291 ARM_FEATURE_V7, 1292 ARM_FEATURE_THUMB2, 1293 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1294 ARM_FEATURE_VFP3, 1295 ARM_FEATURE_VFP_FP16, 1296 ARM_FEATURE_NEON, 1297 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1298 ARM_FEATURE_M, /* Microcontroller profile. */ 1299 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1300 ARM_FEATURE_THUMB2EE, 1301 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1302 ARM_FEATURE_V4T, 1303 ARM_FEATURE_V5, 1304 ARM_FEATURE_STRONGARM, 1305 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1306 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1307 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1308 ARM_FEATURE_GENERIC_TIMER, 1309 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1310 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1311 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1312 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1313 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1314 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1315 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1316 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1317 ARM_FEATURE_V8, 1318 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1319 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1320 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1321 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1322 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1323 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1324 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1325 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1326 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1327 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1328 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1329 ARM_FEATURE_PMU, /* has PMU support */ 1330 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1331 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1332 ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ 1333 }; 1334 1335 static inline int arm_feature(CPUARMState *env, int feature) 1336 { 1337 return (env->features & (1ULL << feature)) != 0; 1338 } 1339 1340 #if !defined(CONFIG_USER_ONLY) 1341 /* Return true if exception levels below EL3 are in secure state, 1342 * or would be following an exception return to that level. 1343 * Unlike arm_is_secure() (which is always a question about the 1344 * _current_ state of the CPU) this doesn't care about the current 1345 * EL or mode. 1346 */ 1347 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1348 { 1349 if (arm_feature(env, ARM_FEATURE_EL3)) { 1350 return !(env->cp15.scr_el3 & SCR_NS); 1351 } else { 1352 /* If EL3 is not supported then the secure state is implementation 1353 * defined, in which case QEMU defaults to non-secure. 1354 */ 1355 return false; 1356 } 1357 } 1358 1359 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1360 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1361 { 1362 if (arm_feature(env, ARM_FEATURE_EL3)) { 1363 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1364 /* CPU currently in AArch64 state and EL3 */ 1365 return true; 1366 } else if (!is_a64(env) && 1367 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1368 /* CPU currently in AArch32 state and monitor mode */ 1369 return true; 1370 } 1371 } 1372 return false; 1373 } 1374 1375 /* Return true if the processor is in secure state */ 1376 static inline bool arm_is_secure(CPUARMState *env) 1377 { 1378 if (arm_is_el3_or_mon(env)) { 1379 return true; 1380 } 1381 return arm_is_secure_below_el3(env); 1382 } 1383 1384 #else 1385 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1386 { 1387 return false; 1388 } 1389 1390 static inline bool arm_is_secure(CPUARMState *env) 1391 { 1392 return false; 1393 } 1394 #endif 1395 1396 /* Return true if the specified exception level is running in AArch64 state. */ 1397 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1398 { 1399 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1400 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1401 */ 1402 assert(el >= 1 && el <= 3); 1403 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1404 1405 /* The highest exception level is always at the maximum supported 1406 * register width, and then lower levels have a register width controlled 1407 * by bits in the SCR or HCR registers. 1408 */ 1409 if (el == 3) { 1410 return aa64; 1411 } 1412 1413 if (arm_feature(env, ARM_FEATURE_EL3)) { 1414 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1415 } 1416 1417 if (el == 2) { 1418 return aa64; 1419 } 1420 1421 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1422 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1423 } 1424 1425 return aa64; 1426 } 1427 1428 /* Function for determing whether guest cp register reads and writes should 1429 * access the secure or non-secure bank of a cp register. When EL3 is 1430 * operating in AArch32 state, the NS-bit determines whether the secure 1431 * instance of a cp register should be used. When EL3 is AArch64 (or if 1432 * it doesn't exist at all) then there is no register banking, and all 1433 * accesses are to the non-secure version. 1434 */ 1435 static inline bool access_secure_reg(CPUARMState *env) 1436 { 1437 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1438 !arm_el_is_aa64(env, 3) && 1439 !(env->cp15.scr_el3 & SCR_NS)); 1440 1441 return ret; 1442 } 1443 1444 /* Macros for accessing a specified CP register bank */ 1445 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1446 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1447 1448 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1449 do { \ 1450 if (_secure) { \ 1451 (_env)->cp15._regname##_s = (_val); \ 1452 } else { \ 1453 (_env)->cp15._regname##_ns = (_val); \ 1454 } \ 1455 } while (0) 1456 1457 /* Macros for automatically accessing a specific CP register bank depending on 1458 * the current secure state of the system. These macros are not intended for 1459 * supporting instruction translation reads/writes as these are dependent 1460 * solely on the SCR.NS bit and not the mode. 1461 */ 1462 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1463 A32_BANKED_REG_GET((_env), _regname, \ 1464 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1465 1466 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1467 A32_BANKED_REG_SET((_env), _regname, \ 1468 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1469 (_val)) 1470 1471 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1472 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1473 uint32_t cur_el, bool secure); 1474 1475 /* Interface between CPU and Interrupt controller. */ 1476 #ifndef CONFIG_USER_ONLY 1477 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1478 #else 1479 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1480 { 1481 return true; 1482 } 1483 #endif 1484 /** 1485 * armv7m_nvic_set_pending: mark the specified exception as pending 1486 * @opaque: the NVIC 1487 * @irq: the exception number to mark pending 1488 * @secure: false for non-banked exceptions or for the nonsecure 1489 * version of a banked exception, true for the secure version of a banked 1490 * exception. 1491 * 1492 * Marks the specified exception as pending. Note that we will assert() 1493 * if @secure is true and @irq does not specify one of the fixed set 1494 * of architecturally banked exceptions. 1495 */ 1496 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1497 /** 1498 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 1499 * @opaque: the NVIC 1500 * 1501 * Move the current highest priority pending exception from the pending 1502 * state to the active state, and update v7m.exception to indicate that 1503 * it is the exception currently being handled. 1504 * 1505 * Returns: true if exception should be taken to Secure state, false for NS 1506 */ 1507 bool armv7m_nvic_acknowledge_irq(void *opaque); 1508 /** 1509 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1510 * @opaque: the NVIC 1511 * @irq: the exception number to complete 1512 * @secure: true if this exception was secure 1513 * 1514 * Returns: -1 if the irq was not active 1515 * 1 if completing this irq brought us back to base (no active irqs) 1516 * 0 if there is still an irq active after this one was completed 1517 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1518 */ 1519 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 1520 /** 1521 * armv7m_nvic_raw_execution_priority: return the raw execution priority 1522 * @opaque: the NVIC 1523 * 1524 * Returns: the raw execution priority as defined by the v8M architecture. 1525 * This is the execution priority minus the effects of AIRCR.PRIS, 1526 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 1527 * (v8M ARM ARM I_PKLD.) 1528 */ 1529 int armv7m_nvic_raw_execution_priority(void *opaque); 1530 /** 1531 * armv7m_nvic_neg_prio_requested: return true if the requested execution 1532 * priority is negative for the specified security state. 1533 * @opaque: the NVIC 1534 * @secure: the security state to test 1535 * This corresponds to the pseudocode IsReqExecPriNeg(). 1536 */ 1537 #ifndef CONFIG_USER_ONLY 1538 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 1539 #else 1540 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 1541 { 1542 return false; 1543 } 1544 #endif 1545 1546 /* Interface for defining coprocessor registers. 1547 * Registers are defined in tables of arm_cp_reginfo structs 1548 * which are passed to define_arm_cp_regs(). 1549 */ 1550 1551 /* When looking up a coprocessor register we look for it 1552 * via an integer which encodes all of: 1553 * coprocessor number 1554 * Crn, Crm, opc1, opc2 fields 1555 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1556 * or via MRRC/MCRR?) 1557 * non-secure/secure bank (AArch32 only) 1558 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1559 * (In this case crn and opc2 should be zero.) 1560 * For AArch64, there is no 32/64 bit size distinction; 1561 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1562 * and 4 bit CRn and CRm. The encoding patterns are chosen 1563 * to be easy to convert to and from the KVM encodings, and also 1564 * so that the hashtable can contain both AArch32 and AArch64 1565 * registers (to allow for interprocessing where we might run 1566 * 32 bit code on a 64 bit core). 1567 */ 1568 /* This bit is private to our hashtable cpreg; in KVM register 1569 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1570 * in the upper bits of the 64 bit ID. 1571 */ 1572 #define CP_REG_AA64_SHIFT 28 1573 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1574 1575 /* To enable banking of coprocessor registers depending on ns-bit we 1576 * add a bit to distinguish between secure and non-secure cpregs in the 1577 * hashtable. 1578 */ 1579 #define CP_REG_NS_SHIFT 29 1580 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1581 1582 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1583 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1584 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1585 1586 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1587 (CP_REG_AA64_MASK | \ 1588 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1589 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1590 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1591 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1592 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1593 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1594 1595 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1596 * version used as a key for the coprocessor register hashtable 1597 */ 1598 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1599 { 1600 uint32_t cpregid = kvmid; 1601 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1602 cpregid |= CP_REG_AA64_MASK; 1603 } else { 1604 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1605 cpregid |= (1 << 15); 1606 } 1607 1608 /* KVM is always non-secure so add the NS flag on AArch32 register 1609 * entries. 1610 */ 1611 cpregid |= 1 << CP_REG_NS_SHIFT; 1612 } 1613 return cpregid; 1614 } 1615 1616 /* Convert a truncated 32 bit hashtable key into the full 1617 * 64 bit KVM register ID. 1618 */ 1619 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1620 { 1621 uint64_t kvmid; 1622 1623 if (cpregid & CP_REG_AA64_MASK) { 1624 kvmid = cpregid & ~CP_REG_AA64_MASK; 1625 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1626 } else { 1627 kvmid = cpregid & ~(1 << 15); 1628 if (cpregid & (1 << 15)) { 1629 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1630 } else { 1631 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1632 } 1633 } 1634 return kvmid; 1635 } 1636 1637 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1638 * special-behaviour cp reg and bits [15..8] indicate what behaviour 1639 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1640 * TCG can assume the value to be constant (ie load at translate time) 1641 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1642 * indicates that the TB should not be ended after a write to this register 1643 * (the default is that the TB ends after cp writes). OVERRIDE permits 1644 * a register definition to override a previous definition for the 1645 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1646 * old must have the OVERRIDE bit set. 1647 * ALIAS indicates that this register is an alias view of some underlying 1648 * state which is also visible via another register, and that the other 1649 * register is handling migration and reset; registers marked ALIAS will not be 1650 * migrated but may have their state set by syncing of register state from KVM. 1651 * NO_RAW indicates that this register has no underlying state and does not 1652 * support raw access for state saving/loading; it will not be used for either 1653 * migration or KVM state synchronization. (Typically this is for "registers" 1654 * which are actually used as instructions for cache maintenance and so on.) 1655 * IO indicates that this register does I/O and therefore its accesses 1656 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1657 * registers which implement clocks or timers require this. 1658 */ 1659 #define ARM_CP_SPECIAL 1 1660 #define ARM_CP_CONST 2 1661 #define ARM_CP_64BIT 4 1662 #define ARM_CP_SUPPRESS_TB_END 8 1663 #define ARM_CP_OVERRIDE 16 1664 #define ARM_CP_ALIAS 32 1665 #define ARM_CP_IO 64 1666 #define ARM_CP_NO_RAW 128 1667 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) 1668 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) 1669 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) 1670 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) 1671 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) 1672 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1673 /* Used only as a terminator for ARMCPRegInfo lists */ 1674 #define ARM_CP_SENTINEL 0xffff 1675 /* Mask of only the flag bits in a type field */ 1676 #define ARM_CP_FLAG_MASK 0xff 1677 1678 /* Valid values for ARMCPRegInfo state field, indicating which of 1679 * the AArch32 and AArch64 execution states this register is visible in. 1680 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1681 * If the reginfo is declared to be visible in both states then a second 1682 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1683 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1684 * Note that we rely on the values of these enums as we iterate through 1685 * the various states in some places. 1686 */ 1687 enum { 1688 ARM_CP_STATE_AA32 = 0, 1689 ARM_CP_STATE_AA64 = 1, 1690 ARM_CP_STATE_BOTH = 2, 1691 }; 1692 1693 /* ARM CP register secure state flags. These flags identify security state 1694 * attributes for a given CP register entry. 1695 * The existence of both or neither secure and non-secure flags indicates that 1696 * the register has both a secure and non-secure hash entry. A single one of 1697 * these flags causes the register to only be hashed for the specified 1698 * security state. 1699 * Although definitions may have any combination of the S/NS bits, each 1700 * registered entry will only have one to identify whether the entry is secure 1701 * or non-secure. 1702 */ 1703 enum { 1704 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1705 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1706 }; 1707 1708 /* Return true if cptype is a valid type field. This is used to try to 1709 * catch errors where the sentinel has been accidentally left off the end 1710 * of a list of registers. 1711 */ 1712 static inline bool cptype_valid(int cptype) 1713 { 1714 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1715 || ((cptype & ARM_CP_SPECIAL) && 1716 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1717 } 1718 1719 /* Access rights: 1720 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1721 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1722 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1723 * (ie any of the privileged modes in Secure state, or Monitor mode). 1724 * If a register is accessible in one privilege level it's always accessible 1725 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1726 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1727 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1728 * terminology a little and call this PL3. 1729 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1730 * with the ELx exception levels. 1731 * 1732 * If access permissions for a register are more complex than can be 1733 * described with these bits, then use a laxer set of restrictions, and 1734 * do the more restrictive/complex check inside a helper function. 1735 */ 1736 #define PL3_R 0x80 1737 #define PL3_W 0x40 1738 #define PL2_R (0x20 | PL3_R) 1739 #define PL2_W (0x10 | PL3_W) 1740 #define PL1_R (0x08 | PL2_R) 1741 #define PL1_W (0x04 | PL2_W) 1742 #define PL0_R (0x02 | PL1_R) 1743 #define PL0_W (0x01 | PL1_W) 1744 1745 #define PL3_RW (PL3_R | PL3_W) 1746 #define PL2_RW (PL2_R | PL2_W) 1747 #define PL1_RW (PL1_R | PL1_W) 1748 #define PL0_RW (PL0_R | PL0_W) 1749 1750 /* Return the highest implemented Exception Level */ 1751 static inline int arm_highest_el(CPUARMState *env) 1752 { 1753 if (arm_feature(env, ARM_FEATURE_EL3)) { 1754 return 3; 1755 } 1756 if (arm_feature(env, ARM_FEATURE_EL2)) { 1757 return 2; 1758 } 1759 return 1; 1760 } 1761 1762 /* Return true if a v7M CPU is in Handler mode */ 1763 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 1764 { 1765 return env->v7m.exception != 0; 1766 } 1767 1768 /* Return the current Exception Level (as per ARMv8; note that this differs 1769 * from the ARMv7 Privilege Level). 1770 */ 1771 static inline int arm_current_el(CPUARMState *env) 1772 { 1773 if (arm_feature(env, ARM_FEATURE_M)) { 1774 return arm_v7m_is_handler_mode(env) || 1775 !(env->v7m.control[env->v7m.secure] & 1); 1776 } 1777 1778 if (is_a64(env)) { 1779 return extract32(env->pstate, 2, 2); 1780 } 1781 1782 switch (env->uncached_cpsr & 0x1f) { 1783 case ARM_CPU_MODE_USR: 1784 return 0; 1785 case ARM_CPU_MODE_HYP: 1786 return 2; 1787 case ARM_CPU_MODE_MON: 1788 return 3; 1789 default: 1790 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1791 /* If EL3 is 32-bit then all secure privileged modes run in 1792 * EL3 1793 */ 1794 return 3; 1795 } 1796 1797 return 1; 1798 } 1799 } 1800 1801 typedef struct ARMCPRegInfo ARMCPRegInfo; 1802 1803 typedef enum CPAccessResult { 1804 /* Access is permitted */ 1805 CP_ACCESS_OK = 0, 1806 /* Access fails due to a configurable trap or enable which would 1807 * result in a categorized exception syndrome giving information about 1808 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1809 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1810 * PL1 if in EL0, otherwise to the current EL). 1811 */ 1812 CP_ACCESS_TRAP = 1, 1813 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1814 * Note that this is not a catch-all case -- the set of cases which may 1815 * result in this failure is specifically defined by the architecture. 1816 */ 1817 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 1818 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 1819 CP_ACCESS_TRAP_EL2 = 3, 1820 CP_ACCESS_TRAP_EL3 = 4, 1821 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 1822 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 1823 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 1824 /* Access fails and results in an exception syndrome for an FP access, 1825 * trapped directly to EL2 or EL3 1826 */ 1827 CP_ACCESS_TRAP_FP_EL2 = 7, 1828 CP_ACCESS_TRAP_FP_EL3 = 8, 1829 } CPAccessResult; 1830 1831 /* Access functions for coprocessor registers. These cannot fail and 1832 * may not raise exceptions. 1833 */ 1834 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1835 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 1836 uint64_t value); 1837 /* Access permission check functions for coprocessor registers. */ 1838 typedef CPAccessResult CPAccessFn(CPUARMState *env, 1839 const ARMCPRegInfo *opaque, 1840 bool isread); 1841 /* Hook function for register reset */ 1842 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1843 1844 #define CP_ANY 0xff 1845 1846 /* Definition of an ARM coprocessor register */ 1847 struct ARMCPRegInfo { 1848 /* Name of register (useful mainly for debugging, need not be unique) */ 1849 const char *name; 1850 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 1851 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 1852 * 'wildcard' field -- any value of that field in the MRC/MCR insn 1853 * will be decoded to this register. The register read and write 1854 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 1855 * used by the program, so it is possible to register a wildcard and 1856 * then behave differently on read/write if necessary. 1857 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 1858 * must both be zero. 1859 * For AArch64-visible registers, opc0 is also used. 1860 * Since there are no "coprocessors" in AArch64, cp is purely used as a 1861 * way to distinguish (for KVM's benefit) guest-visible system registers 1862 * from demuxed ones provided to preserve the "no side effects on 1863 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 1864 * visible (to match KVM's encoding); cp==0 will be converted to 1865 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 1866 */ 1867 uint8_t cp; 1868 uint8_t crn; 1869 uint8_t crm; 1870 uint8_t opc0; 1871 uint8_t opc1; 1872 uint8_t opc2; 1873 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 1874 int state; 1875 /* Register type: ARM_CP_* bits/values */ 1876 int type; 1877 /* Access rights: PL*_[RW] */ 1878 int access; 1879 /* Security state: ARM_CP_SECSTATE_* bits/values */ 1880 int secure; 1881 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 1882 * this register was defined: can be used to hand data through to the 1883 * register read/write functions, since they are passed the ARMCPRegInfo*. 1884 */ 1885 void *opaque; 1886 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 1887 * fieldoffset is non-zero, the reset value of the register. 1888 */ 1889 uint64_t resetvalue; 1890 /* Offset of the field in CPUARMState for this register. 1891 * 1892 * This is not needed if either: 1893 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 1894 * 2. both readfn and writefn are specified 1895 */ 1896 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 1897 1898 /* Offsets of the secure and non-secure fields in CPUARMState for the 1899 * register if it is banked. These fields are only used during the static 1900 * registration of a register. During hashing the bank associated 1901 * with a given security state is copied to fieldoffset which is used from 1902 * there on out. 1903 * 1904 * It is expected that register definitions use either fieldoffset or 1905 * bank_fieldoffsets in the definition but not both. It is also expected 1906 * that both bank offsets are set when defining a banked register. This 1907 * use indicates that a register is banked. 1908 */ 1909 ptrdiff_t bank_fieldoffsets[2]; 1910 1911 /* Function for making any access checks for this register in addition to 1912 * those specified by the 'access' permissions bits. If NULL, no extra 1913 * checks required. The access check is performed at runtime, not at 1914 * translate time. 1915 */ 1916 CPAccessFn *accessfn; 1917 /* Function for handling reads of this register. If NULL, then reads 1918 * will be done by loading from the offset into CPUARMState specified 1919 * by fieldoffset. 1920 */ 1921 CPReadFn *readfn; 1922 /* Function for handling writes of this register. If NULL, then writes 1923 * will be done by writing to the offset into CPUARMState specified 1924 * by fieldoffset. 1925 */ 1926 CPWriteFn *writefn; 1927 /* Function for doing a "raw" read; used when we need to copy 1928 * coprocessor state to the kernel for KVM or out for 1929 * migration. This only needs to be provided if there is also a 1930 * readfn and it has side effects (for instance clear-on-read bits). 1931 */ 1932 CPReadFn *raw_readfn; 1933 /* Function for doing a "raw" write; used when we need to copy KVM 1934 * kernel coprocessor state into userspace, or for inbound 1935 * migration. This only needs to be provided if there is also a 1936 * writefn and it masks out "unwritable" bits or has write-one-to-clear 1937 * or similar behaviour. 1938 */ 1939 CPWriteFn *raw_writefn; 1940 /* Function for resetting the register. If NULL, then reset will be done 1941 * by writing resetvalue to the field specified in fieldoffset. If 1942 * fieldoffset is 0 then no reset will be done. 1943 */ 1944 CPResetFn *resetfn; 1945 }; 1946 1947 /* Macros which are lvalues for the field in CPUARMState for the 1948 * ARMCPRegInfo *ri. 1949 */ 1950 #define CPREG_FIELD32(env, ri) \ 1951 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 1952 #define CPREG_FIELD64(env, ri) \ 1953 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 1954 1955 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 1956 1957 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 1958 const ARMCPRegInfo *regs, void *opaque); 1959 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 1960 const ARMCPRegInfo *regs, void *opaque); 1961 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 1962 { 1963 define_arm_cp_regs_with_opaque(cpu, regs, 0); 1964 } 1965 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 1966 { 1967 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 1968 } 1969 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 1970 1971 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 1972 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 1973 uint64_t value); 1974 /* CPReadFn that can be used for read-as-zero behaviour */ 1975 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 1976 1977 /* CPResetFn that does nothing, for use if no reset is required even 1978 * if fieldoffset is non zero. 1979 */ 1980 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 1981 1982 /* Return true if this reginfo struct's field in the cpu state struct 1983 * is 64 bits wide. 1984 */ 1985 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 1986 { 1987 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 1988 } 1989 1990 static inline bool cp_access_ok(int current_el, 1991 const ARMCPRegInfo *ri, int isread) 1992 { 1993 return (ri->access >> ((current_el * 2) + isread)) & 1; 1994 } 1995 1996 /* Raw read of a coprocessor register (as needed for migration, etc) */ 1997 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 1998 1999 /** 2000 * write_list_to_cpustate 2001 * @cpu: ARMCPU 2002 * 2003 * For each register listed in the ARMCPU cpreg_indexes list, write 2004 * its value from the cpreg_values list into the ARMCPUState structure. 2005 * This updates TCG's working data structures from KVM data or 2006 * from incoming migration state. 2007 * 2008 * Returns: true if all register values were updated correctly, 2009 * false if some register was unknown or could not be written. 2010 * Note that we do not stop early on failure -- we will attempt 2011 * writing all registers in the list. 2012 */ 2013 bool write_list_to_cpustate(ARMCPU *cpu); 2014 2015 /** 2016 * write_cpustate_to_list: 2017 * @cpu: ARMCPU 2018 * 2019 * For each register listed in the ARMCPU cpreg_indexes list, write 2020 * its value from the ARMCPUState structure into the cpreg_values list. 2021 * This is used to copy info from TCG's working data structures into 2022 * KVM or for outbound migration. 2023 * 2024 * Returns: true if all register values were read correctly, 2025 * false if some register was unknown or could not be read. 2026 * Note that we do not stop early on failure -- we will attempt 2027 * reading all registers in the list. 2028 */ 2029 bool write_cpustate_to_list(ARMCPU *cpu); 2030 2031 #define ARM_CPUID_TI915T 0x54029152 2032 #define ARM_CPUID_TI925T 0x54029252 2033 2034 #if defined(CONFIG_USER_ONLY) 2035 #define TARGET_PAGE_BITS 12 2036 #else 2037 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2038 * have to support 1K tiny pages. 2039 */ 2040 #define TARGET_PAGE_BITS_VARY 2041 #define TARGET_PAGE_BITS_MIN 10 2042 #endif 2043 2044 #if defined(TARGET_AARCH64) 2045 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2046 # define TARGET_VIRT_ADDR_SPACE_BITS 64 2047 #else 2048 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2049 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2050 #endif 2051 2052 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2053 unsigned int target_el) 2054 { 2055 CPUARMState *env = cs->env_ptr; 2056 unsigned int cur_el = arm_current_el(env); 2057 bool secure = arm_is_secure(env); 2058 bool pstate_unmasked; 2059 int8_t unmasked = 0; 2060 2061 /* Don't take exceptions if they target a lower EL. 2062 * This check should catch any exceptions that would not be taken but left 2063 * pending. 2064 */ 2065 if (cur_el > target_el) { 2066 return false; 2067 } 2068 2069 switch (excp_idx) { 2070 case EXCP_FIQ: 2071 pstate_unmasked = !(env->daif & PSTATE_F); 2072 break; 2073 2074 case EXCP_IRQ: 2075 pstate_unmasked = !(env->daif & PSTATE_I); 2076 break; 2077 2078 case EXCP_VFIQ: 2079 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 2080 /* VFIQs are only taken when hypervized and non-secure. */ 2081 return false; 2082 } 2083 return !(env->daif & PSTATE_F); 2084 case EXCP_VIRQ: 2085 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 2086 /* VIRQs are only taken when hypervized and non-secure. */ 2087 return false; 2088 } 2089 return !(env->daif & PSTATE_I); 2090 default: 2091 g_assert_not_reached(); 2092 } 2093 2094 /* Use the target EL, current execution state and SCR/HCR settings to 2095 * determine whether the corresponding CPSR bit is used to mask the 2096 * interrupt. 2097 */ 2098 if ((target_el > cur_el) && (target_el != 1)) { 2099 /* Exceptions targeting a higher EL may not be maskable */ 2100 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2101 /* 64-bit masking rules are simple: exceptions to EL3 2102 * can't be masked, and exceptions to EL2 can only be 2103 * masked from Secure state. The HCR and SCR settings 2104 * don't affect the masking logic, only the interrupt routing. 2105 */ 2106 if (target_el == 3 || !secure) { 2107 unmasked = 1; 2108 } 2109 } else { 2110 /* The old 32-bit-only environment has a more complicated 2111 * masking setup. HCR and SCR bits not only affect interrupt 2112 * routing but also change the behaviour of masking. 2113 */ 2114 bool hcr, scr; 2115 2116 switch (excp_idx) { 2117 case EXCP_FIQ: 2118 /* If FIQs are routed to EL3 or EL2 then there are cases where 2119 * we override the CPSR.F in determining if the exception is 2120 * masked or not. If neither of these are set then we fall back 2121 * to the CPSR.F setting otherwise we further assess the state 2122 * below. 2123 */ 2124 hcr = (env->cp15.hcr_el2 & HCR_FMO); 2125 scr = (env->cp15.scr_el3 & SCR_FIQ); 2126 2127 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2128 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2129 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2130 * when non-secure but only when FIQs are only routed to EL3. 2131 */ 2132 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2133 break; 2134 case EXCP_IRQ: 2135 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2136 * we may override the CPSR.I masking when in non-secure state. 2137 * The SCR.IRQ setting has already been taken into consideration 2138 * when setting the target EL, so it does not have a further 2139 * affect here. 2140 */ 2141 hcr = (env->cp15.hcr_el2 & HCR_IMO); 2142 scr = false; 2143 break; 2144 default: 2145 g_assert_not_reached(); 2146 } 2147 2148 if ((scr || hcr) && !secure) { 2149 unmasked = 1; 2150 } 2151 } 2152 } 2153 2154 /* The PSTATE bits only mask the interrupt if we have not overriden the 2155 * ability above. 2156 */ 2157 return unmasked || pstate_unmasked; 2158 } 2159 2160 #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model) 2161 2162 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2163 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2164 2165 #define cpu_signal_handler cpu_arm_signal_handler 2166 #define cpu_list arm_cpu_list 2167 2168 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2169 * 2170 * If EL3 is 64-bit: 2171 * + NonSecure EL1 & 0 stage 1 2172 * + NonSecure EL1 & 0 stage 2 2173 * + NonSecure EL2 2174 * + Secure EL1 & EL0 2175 * + Secure EL3 2176 * If EL3 is 32-bit: 2177 * + NonSecure PL1 & 0 stage 1 2178 * + NonSecure PL1 & 0 stage 2 2179 * + NonSecure PL2 2180 * + Secure PL0 & PL1 2181 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2182 * 2183 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2184 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2185 * may differ in access permissions even if the VA->PA map is the same 2186 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2187 * translation, which means that we have one mmu_idx that deals with two 2188 * concatenated translation regimes [this sort of combined s1+2 TLB is 2189 * architecturally permitted] 2190 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2191 * handling via the TLB. The only way to do a stage 1 translation without 2192 * the immediate stage 2 translation is via the ATS or AT system insns, 2193 * which can be slow-pathed and always do a page table walk. 2194 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2195 * translation regimes, because they map reasonably well to each other 2196 * and they can't both be active at the same time. 2197 * This gives us the following list of mmu_idx values: 2198 * 2199 * NS EL0 (aka NS PL0) stage 1+2 2200 * NS EL1 (aka NS PL1) stage 1+2 2201 * NS EL2 (aka NS PL2) 2202 * S EL3 (aka S PL1) 2203 * S EL0 (aka S PL0) 2204 * S EL1 (not used if EL3 is 32 bit) 2205 * NS EL0+1 stage 2 2206 * 2207 * (The last of these is an mmu_idx because we want to be able to use the TLB 2208 * for the accesses done as part of a stage 1 page table walk, rather than 2209 * having to walk the stage 2 page table over and over.) 2210 * 2211 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2212 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2213 * NS EL2 if we ever model a Cortex-R52). 2214 * 2215 * M profile CPUs are rather different as they do not have a true MMU. 2216 * They have the following different MMU indexes: 2217 * User 2218 * Privileged 2219 * Execution priority negative (this is like privileged, but the 2220 * MPU HFNMIENA bit means that it may have different access permission 2221 * check results to normal privileged code, so can't share a TLB). 2222 * If the CPU supports the v8M Security Extension then there are also: 2223 * Secure User 2224 * Secure Privileged 2225 * Secure, execution priority negative 2226 * 2227 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2228 * are not quite the same -- different CPU types (most notably M profile 2229 * vs A/R profile) would like to use MMU indexes with different semantics, 2230 * but since we don't ever need to use all of those in a single CPU we 2231 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2232 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2233 * the same for any particular CPU. 2234 * Variables of type ARMMUIdx are always full values, and the core 2235 * index values are in variables of type 'int'. 2236 * 2237 * Our enumeration includes at the end some entries which are not "true" 2238 * mmu_idx values in that they don't have corresponding TLBs and are only 2239 * valid for doing slow path page table walks. 2240 * 2241 * The constant names here are patterned after the general style of the names 2242 * of the AT/ATS operations. 2243 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2244 */ 2245 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2246 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2247 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2248 2249 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2250 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2251 2252 typedef enum ARMMMUIdx { 2253 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2254 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2255 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2256 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2257 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2258 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2259 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2260 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2261 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2262 ARMMMUIdx_MNegPri = 2 | ARM_MMU_IDX_M, 2263 ARMMMUIdx_MSUser = 3 | ARM_MMU_IDX_M, 2264 ARMMMUIdx_MSPriv = 4 | ARM_MMU_IDX_M, 2265 ARMMMUIdx_MSNegPri = 5 | ARM_MMU_IDX_M, 2266 /* Indexes below here don't have TLBs and are used only for AT system 2267 * instructions or for the first stage of an S12 page table walk. 2268 */ 2269 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2270 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2271 } ARMMMUIdx; 2272 2273 /* Bit macros for the core-mmu-index values for each index, 2274 * for use when calling tlb_flush_by_mmuidx() and friends. 2275 */ 2276 typedef enum ARMMMUIdxBit { 2277 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2278 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2279 ARMMMUIdxBit_S1E2 = 1 << 2, 2280 ARMMMUIdxBit_S1E3 = 1 << 3, 2281 ARMMMUIdxBit_S1SE0 = 1 << 4, 2282 ARMMMUIdxBit_S1SE1 = 1 << 5, 2283 ARMMMUIdxBit_S2NS = 1 << 6, 2284 ARMMMUIdxBit_MUser = 1 << 0, 2285 ARMMMUIdxBit_MPriv = 1 << 1, 2286 ARMMMUIdxBit_MNegPri = 1 << 2, 2287 ARMMMUIdxBit_MSUser = 1 << 3, 2288 ARMMMUIdxBit_MSPriv = 1 << 4, 2289 ARMMMUIdxBit_MSNegPri = 1 << 5, 2290 } ARMMMUIdxBit; 2291 2292 #define MMU_USER_IDX 0 2293 2294 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2295 { 2296 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2297 } 2298 2299 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2300 { 2301 if (arm_feature(env, ARM_FEATURE_M)) { 2302 return mmu_idx | ARM_MMU_IDX_M; 2303 } else { 2304 return mmu_idx | ARM_MMU_IDX_A; 2305 } 2306 } 2307 2308 /* Return the exception level we're running at if this is our mmu_idx */ 2309 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2310 { 2311 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2312 case ARM_MMU_IDX_A: 2313 return mmu_idx & 3; 2314 case ARM_MMU_IDX_M: 2315 return (mmu_idx == ARMMMUIdx_MUser || mmu_idx == ARMMMUIdx_MSUser) 2316 ? 0 : 1; 2317 default: 2318 g_assert_not_reached(); 2319 } 2320 } 2321 2322 /* Determine the current mmu_idx to use for normal loads/stores */ 2323 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2324 { 2325 int el = arm_current_el(env); 2326 2327 if (arm_feature(env, ARM_FEATURE_M)) { 2328 ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv; 2329 2330 if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) { 2331 mmu_idx = ARMMMUIdx_MNegPri; 2332 } 2333 2334 if (env->v7m.secure) { 2335 mmu_idx += ARMMMUIdx_MSUser; 2336 } 2337 2338 return arm_to_core_mmu_idx(mmu_idx); 2339 } 2340 2341 if (el < 2 && arm_is_secure_below_el3(env)) { 2342 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); 2343 } 2344 return el; 2345 } 2346 2347 /* Indexes used when registering address spaces with cpu_address_space_init */ 2348 typedef enum ARMASIdx { 2349 ARMASIdx_NS = 0, 2350 ARMASIdx_S = 1, 2351 } ARMASIdx; 2352 2353 /* Return the Exception Level targeted by debug exceptions. */ 2354 static inline int arm_debug_target_el(CPUARMState *env) 2355 { 2356 bool secure = arm_is_secure(env); 2357 bool route_to_el2 = false; 2358 2359 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2360 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2361 env->cp15.mdcr_el2 & (1 << 8); 2362 } 2363 2364 if (route_to_el2) { 2365 return 2; 2366 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2367 !arm_el_is_aa64(env, 3) && secure) { 2368 return 3; 2369 } else { 2370 return 1; 2371 } 2372 } 2373 2374 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2375 { 2376 if (arm_is_secure(env)) { 2377 /* MDCR_EL3.SDD disables debug events from Secure state */ 2378 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2379 || arm_current_el(env) == 3) { 2380 return false; 2381 } 2382 } 2383 2384 if (arm_current_el(env) == arm_debug_target_el(env)) { 2385 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2386 || (env->daif & PSTATE_D)) { 2387 return false; 2388 } 2389 } 2390 return true; 2391 } 2392 2393 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2394 { 2395 int el = arm_current_el(env); 2396 2397 if (el == 0 && arm_el_is_aa64(env, 1)) { 2398 return aa64_generate_debug_exceptions(env); 2399 } 2400 2401 if (arm_is_secure(env)) { 2402 int spd; 2403 2404 if (el == 0 && (env->cp15.sder & 1)) { 2405 /* SDER.SUIDEN means debug exceptions from Secure EL0 2406 * are always enabled. Otherwise they are controlled by 2407 * SDCR.SPD like those from other Secure ELs. 2408 */ 2409 return true; 2410 } 2411 2412 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2413 switch (spd) { 2414 case 1: 2415 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2416 case 0: 2417 /* For 0b00 we return true if external secure invasive debug 2418 * is enabled. On real hardware this is controlled by external 2419 * signals to the core. QEMU always permits debug, and behaves 2420 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2421 */ 2422 return true; 2423 case 2: 2424 return false; 2425 case 3: 2426 return true; 2427 } 2428 } 2429 2430 return el != 2; 2431 } 2432 2433 /* Return true if debugging exceptions are currently enabled. 2434 * This corresponds to what in ARM ARM pseudocode would be 2435 * if UsingAArch32() then 2436 * return AArch32.GenerateDebugExceptions() 2437 * else 2438 * return AArch64.GenerateDebugExceptions() 2439 * We choose to push the if() down into this function for clarity, 2440 * since the pseudocode has it at all callsites except for the one in 2441 * CheckSoftwareStep(), where it is elided because both branches would 2442 * always return the same value. 2443 * 2444 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2445 * don't yet implement those exception levels or their associated trap bits. 2446 */ 2447 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2448 { 2449 if (env->aarch64) { 2450 return aa64_generate_debug_exceptions(env); 2451 } else { 2452 return aa32_generate_debug_exceptions(env); 2453 } 2454 } 2455 2456 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2457 * implicitly means this always returns false in pre-v8 CPUs.) 2458 */ 2459 static inline bool arm_singlestep_active(CPUARMState *env) 2460 { 2461 return extract32(env->cp15.mdscr_el1, 0, 1) 2462 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2463 && arm_generate_debug_exceptions(env); 2464 } 2465 2466 static inline bool arm_sctlr_b(CPUARMState *env) 2467 { 2468 return 2469 /* We need not implement SCTLR.ITD in user-mode emulation, so 2470 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2471 * This lets people run BE32 binaries with "-cpu any". 2472 */ 2473 #ifndef CONFIG_USER_ONLY 2474 !arm_feature(env, ARM_FEATURE_V7) && 2475 #endif 2476 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2477 } 2478 2479 /* Return true if the processor is in big-endian mode. */ 2480 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2481 { 2482 int cur_el; 2483 2484 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2485 if (!is_a64(env)) { 2486 return 2487 #ifdef CONFIG_USER_ONLY 2488 /* In system mode, BE32 is modelled in line with the 2489 * architecture (as word-invariant big-endianness), where loads 2490 * and stores are done little endian but from addresses which 2491 * are adjusted by XORing with the appropriate constant. So the 2492 * endianness to use for the raw data access is not affected by 2493 * SCTLR.B. 2494 * In user mode, however, we model BE32 as byte-invariant 2495 * big-endianness (because user-only code cannot tell the 2496 * difference), and so we need to use a data access endianness 2497 * that depends on SCTLR.B. 2498 */ 2499 arm_sctlr_b(env) || 2500 #endif 2501 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2502 } 2503 2504 cur_el = arm_current_el(env); 2505 2506 if (cur_el == 0) { 2507 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2508 } 2509 2510 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2511 } 2512 2513 #include "exec/cpu-all.h" 2514 2515 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2516 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2517 * We put flags which are shared between 32 and 64 bit mode at the top 2518 * of the word, and flags which apply to only one mode at the bottom. 2519 */ 2520 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2521 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2522 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2523 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2524 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2525 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2526 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2527 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2528 /* Target EL if we take a floating-point-disabled exception */ 2529 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2530 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2531 2532 /* Bit usage when in AArch32 state: */ 2533 #define ARM_TBFLAG_THUMB_SHIFT 0 2534 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2535 #define ARM_TBFLAG_VECLEN_SHIFT 1 2536 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2537 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2538 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2539 #define ARM_TBFLAG_VFPEN_SHIFT 7 2540 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2541 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2542 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2543 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2544 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2545 /* We store the bottom two bits of the CPAR as TB flags and handle 2546 * checks on the other bits at runtime 2547 */ 2548 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2549 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2550 /* Indicates whether cp register reads and writes by guest code should access 2551 * the secure or nonsecure bank of banked registers; note that this is not 2552 * the same thing as the current security state of the processor! 2553 */ 2554 #define ARM_TBFLAG_NS_SHIFT 19 2555 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2556 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2557 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2558 /* For M profile only, Handler (ie not Thread) mode */ 2559 #define ARM_TBFLAG_HANDLER_SHIFT 21 2560 #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) 2561 2562 /* Bit usage when in AArch64 state */ 2563 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2564 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2565 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2566 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2567 2568 /* some convenience accessor macros */ 2569 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2570 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2571 #define ARM_TBFLAG_MMUIDX(F) \ 2572 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2573 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2574 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2575 #define ARM_TBFLAG_PSTATE_SS(F) \ 2576 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2577 #define ARM_TBFLAG_FPEXC_EL(F) \ 2578 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2579 #define ARM_TBFLAG_THUMB(F) \ 2580 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2581 #define ARM_TBFLAG_VECLEN(F) \ 2582 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2583 #define ARM_TBFLAG_VECSTRIDE(F) \ 2584 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2585 #define ARM_TBFLAG_VFPEN(F) \ 2586 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2587 #define ARM_TBFLAG_CONDEXEC(F) \ 2588 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2589 #define ARM_TBFLAG_SCTLR_B(F) \ 2590 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2591 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2592 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2593 #define ARM_TBFLAG_NS(F) \ 2594 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2595 #define ARM_TBFLAG_BE_DATA(F) \ 2596 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2597 #define ARM_TBFLAG_HANDLER(F) \ 2598 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) 2599 #define ARM_TBFLAG_TBI0(F) \ 2600 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2601 #define ARM_TBFLAG_TBI1(F) \ 2602 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2603 2604 static inline bool bswap_code(bool sctlr_b) 2605 { 2606 #ifdef CONFIG_USER_ONLY 2607 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2608 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2609 * would also end up as a mixed-endian mode with BE code, LE data. 2610 */ 2611 return 2612 #ifdef TARGET_WORDS_BIGENDIAN 2613 1 ^ 2614 #endif 2615 sctlr_b; 2616 #else 2617 /* All code access in ARM is little endian, and there are no loaders 2618 * doing swaps that need to be reversed 2619 */ 2620 return 0; 2621 #endif 2622 } 2623 2624 /* Return the exception level to which FP-disabled exceptions should 2625 * be taken, or 0 if FP is enabled. 2626 */ 2627 static inline int fp_exception_el(CPUARMState *env) 2628 { 2629 int fpen; 2630 int cur_el = arm_current_el(env); 2631 2632 /* CPACR and the CPTR registers don't exist before v6, so FP is 2633 * always accessible 2634 */ 2635 if (!arm_feature(env, ARM_FEATURE_V6)) { 2636 return 0; 2637 } 2638 2639 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: 2640 * 0, 2 : trap EL0 and EL1/PL1 accesses 2641 * 1 : trap only EL0 accesses 2642 * 3 : trap no accesses 2643 */ 2644 fpen = extract32(env->cp15.cpacr_el1, 20, 2); 2645 switch (fpen) { 2646 case 0: 2647 case 2: 2648 if (cur_el == 0 || cur_el == 1) { 2649 /* Trap to PL1, which might be EL1 or EL3 */ 2650 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2651 return 3; 2652 } 2653 return 1; 2654 } 2655 if (cur_el == 3 && !is_a64(env)) { 2656 /* Secure PL1 running at EL3 */ 2657 return 3; 2658 } 2659 break; 2660 case 1: 2661 if (cur_el == 0) { 2662 return 1; 2663 } 2664 break; 2665 case 3: 2666 break; 2667 } 2668 2669 /* For the CPTR registers we don't need to guard with an ARM_FEATURE 2670 * check because zero bits in the registers mean "don't trap". 2671 */ 2672 2673 /* CPTR_EL2 : present in v7VE or v8 */ 2674 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) 2675 && !arm_is_secure_below_el3(env)) { 2676 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ 2677 return 2; 2678 } 2679 2680 /* CPTR_EL3 : present in v8 */ 2681 if (extract32(env->cp15.cptr_el[3], 10, 1)) { 2682 /* Trap all FP ops to EL3 */ 2683 return 3; 2684 } 2685 2686 return 0; 2687 } 2688 2689 #ifdef CONFIG_USER_ONLY 2690 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2691 { 2692 return 2693 #ifdef TARGET_WORDS_BIGENDIAN 2694 1 ^ 2695 #endif 2696 arm_cpu_data_is_big_endian(env); 2697 } 2698 #endif 2699 2700 #ifndef CONFIG_USER_ONLY 2701 /** 2702 * arm_regime_tbi0: 2703 * @env: CPUARMState 2704 * @mmu_idx: MMU index indicating required translation regime 2705 * 2706 * Extracts the TBI0 value from the appropriate TCR for the current EL 2707 * 2708 * Returns: the TBI0 value. 2709 */ 2710 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2711 2712 /** 2713 * arm_regime_tbi1: 2714 * @env: CPUARMState 2715 * @mmu_idx: MMU index indicating required translation regime 2716 * 2717 * Extracts the TBI1 value from the appropriate TCR for the current EL 2718 * 2719 * Returns: the TBI1 value. 2720 */ 2721 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2722 #else 2723 /* We can't handle tagged addresses properly in user-only mode */ 2724 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2725 { 2726 return 0; 2727 } 2728 2729 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2730 { 2731 return 0; 2732 } 2733 #endif 2734 2735 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2736 target_ulong *cs_base, uint32_t *flags) 2737 { 2738 ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); 2739 if (is_a64(env)) { 2740 *pc = env->pc; 2741 *flags = ARM_TBFLAG_AARCH64_STATE_MASK; 2742 /* Get control bits for tagged addresses */ 2743 *flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); 2744 *flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); 2745 } else { 2746 *pc = env->regs[15]; 2747 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) 2748 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) 2749 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) 2750 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) 2751 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); 2752 if (!(access_secure_reg(env))) { 2753 *flags |= ARM_TBFLAG_NS_MASK; 2754 } 2755 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) 2756 || arm_el_is_aa64(env, 1)) { 2757 *flags |= ARM_TBFLAG_VFPEN_MASK; 2758 } 2759 *flags |= (extract32(env->cp15.c15_cpar, 0, 2) 2760 << ARM_TBFLAG_XSCALE_CPAR_SHIFT); 2761 } 2762 2763 *flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); 2764 2765 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine 2766 * states defined in the ARM ARM for software singlestep: 2767 * SS_ACTIVE PSTATE.SS State 2768 * 0 x Inactive (the TB flag for SS is always 0) 2769 * 1 0 Active-pending 2770 * 1 1 Active-not-pending 2771 */ 2772 if (arm_singlestep_active(env)) { 2773 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; 2774 if (is_a64(env)) { 2775 if (env->pstate & PSTATE_SS) { 2776 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2777 } 2778 } else { 2779 if (env->uncached_cpsr & PSTATE_SS) { 2780 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2781 } 2782 } 2783 } 2784 if (arm_cpu_data_is_big_endian(env)) { 2785 *flags |= ARM_TBFLAG_BE_DATA_MASK; 2786 } 2787 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; 2788 2789 if (arm_v7m_is_handler_mode(env)) { 2790 *flags |= ARM_TBFLAG_HANDLER_MASK; 2791 } 2792 2793 *cs_base = 0; 2794 } 2795 2796 enum { 2797 QEMU_PSCI_CONDUIT_DISABLED = 0, 2798 QEMU_PSCI_CONDUIT_SMC = 1, 2799 QEMU_PSCI_CONDUIT_HVC = 2, 2800 }; 2801 2802 #ifndef CONFIG_USER_ONLY 2803 /* Return the address space index to use for a memory access */ 2804 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2805 { 2806 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2807 } 2808 2809 /* Return the AddressSpace to use for a memory access 2810 * (which depends on whether the access is S or NS, and whether 2811 * the board gave us a separate AddressSpace for S accesses). 2812 */ 2813 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2814 { 2815 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2816 } 2817 #endif 2818 2819 /** 2820 * arm_register_el_change_hook: 2821 * Register a hook function which will be called back whenever this 2822 * CPU changes exception level or mode. The hook function will be 2823 * passed a pointer to the ARMCPU and the opaque data pointer passed 2824 * to this function when the hook was registered. 2825 * 2826 * Note that we currently only support registering a single hook function, 2827 * and will assert if this function is called twice. 2828 * This facility is intended for the use of the GICv3 emulation. 2829 */ 2830 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 2831 void *opaque); 2832 2833 /** 2834 * arm_get_el_change_hook_opaque: 2835 * Return the opaque data that will be used by the el_change_hook 2836 * for this CPU. 2837 */ 2838 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) 2839 { 2840 return cpu->el_change_hook_opaque; 2841 } 2842 2843 #endif 2844