1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 #include "cpu-qom.h" 26 #include "exec/cpu-defs.h" 27 #include "qapi/qapi-types-common.h" 28 29 /* ARM processors have a weak memory model */ 30 #define TCG_GUEST_DEFAULT_MO (0) 31 32 #ifdef TARGET_AARCH64 33 #define KVM_HAVE_MCE_INJECTION 1 34 #endif 35 36 #define EXCP_UDEF 1 /* undefined instruction */ 37 #define EXCP_SWI 2 /* software interrupt */ 38 #define EXCP_PREFETCH_ABORT 3 39 #define EXCP_DATA_ABORT 4 40 #define EXCP_IRQ 5 41 #define EXCP_FIQ 6 42 #define EXCP_BKPT 7 43 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 44 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 45 #define EXCP_HVC 11 /* HyperVisor Call */ 46 #define EXCP_HYP_TRAP 12 47 #define EXCP_SMC 13 /* Secure Monitor Call */ 48 #define EXCP_VIRQ 14 49 #define EXCP_VFIQ 15 50 #define EXCP_SEMIHOST 16 /* semihosting call */ 51 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 52 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 53 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 54 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 55 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 56 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 57 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 58 59 #define ARMV7M_EXCP_RESET 1 60 #define ARMV7M_EXCP_NMI 2 61 #define ARMV7M_EXCP_HARD 3 62 #define ARMV7M_EXCP_MEM 4 63 #define ARMV7M_EXCP_BUS 5 64 #define ARMV7M_EXCP_USAGE 6 65 #define ARMV7M_EXCP_SECURE 7 66 #define ARMV7M_EXCP_SVC 11 67 #define ARMV7M_EXCP_DEBUG 12 68 #define ARMV7M_EXCP_PENDSV 14 69 #define ARMV7M_EXCP_SYSTICK 15 70 71 /* For M profile, some registers are banked secure vs non-secure; 72 * these are represented as a 2-element array where the first element 73 * is the non-secure copy and the second is the secure copy. 74 * When the CPU does not have implement the security extension then 75 * only the first element is used. 76 * This means that the copy for the current security state can be 77 * accessed via env->registerfield[env->v7m.secure] (whether the security 78 * extension is implemented or not). 79 */ 80 enum { 81 M_REG_NS = 0, 82 M_REG_S = 1, 83 M_REG_NUM_BANKS = 2, 84 }; 85 86 /* ARM-specific interrupt pending bits. */ 87 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 88 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 89 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 90 91 /* The usual mapping for an AArch64 system register to its AArch32 92 * counterpart is for the 32 bit world to have access to the lower 93 * half only (with writes leaving the upper half untouched). It's 94 * therefore useful to be able to pass TCG the offset of the least 95 * significant half of a uint64_t struct member. 96 */ 97 #ifdef HOST_WORDS_BIGENDIAN 98 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 99 #define offsetofhigh32(S, M) offsetof(S, M) 100 #else 101 #define offsetoflow32(S, M) offsetof(S, M) 102 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #endif 104 105 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 106 #define ARM_CPU_IRQ 0 107 #define ARM_CPU_FIQ 1 108 #define ARM_CPU_VIRQ 2 109 #define ARM_CPU_VFIQ 3 110 111 /* ARM-specific extra insn start words: 112 * 1: Conditional execution bits 113 * 2: Partial exception syndrome for data aborts 114 */ 115 #define TARGET_INSN_START_EXTRA_WORDS 2 116 117 /* The 2nd extra word holding syndrome info for data aborts does not use 118 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 119 * help the sleb128 encoder do a better job. 120 * When restoring the CPU state, we shift it back up. 121 */ 122 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 123 #define ARM_INSN_START_WORD2_SHIFT 14 124 125 /* We currently assume float and double are IEEE single and double 126 precision respectively. 127 Doing runtime conversions is tricky because VFP registers may contain 128 integer values (eg. as the result of a FTOSI instruction). 129 s<2n> maps to the least significant half of d<n> 130 s<2n+1> maps to the most significant half of d<n> 131 */ 132 133 /** 134 * DynamicGDBXMLInfo: 135 * @desc: Contains the XML descriptions. 136 * @num: Number of the registers in this XML seen by GDB. 137 * @data: A union with data specific to the set of registers 138 * @cpregs_keys: Array that contains the corresponding Key of 139 * a given cpreg with the same order of the cpreg 140 * in the XML description. 141 */ 142 typedef struct DynamicGDBXMLInfo { 143 char *desc; 144 int num; 145 union { 146 struct { 147 uint32_t *keys; 148 } cpregs; 149 } data; 150 } DynamicGDBXMLInfo; 151 152 /* CPU state for each instance of a generic timer (in cp15 c14) */ 153 typedef struct ARMGenericTimer { 154 uint64_t cval; /* Timer CompareValue register */ 155 uint64_t ctl; /* Timer Control register */ 156 } ARMGenericTimer; 157 158 #define GTIMER_PHYS 0 159 #define GTIMER_VIRT 1 160 #define GTIMER_HYP 2 161 #define GTIMER_SEC 3 162 #define GTIMER_HYPVIRT 4 163 #define NUM_GTIMERS 5 164 165 typedef struct { 166 uint64_t raw_tcr; 167 uint32_t mask; 168 uint32_t base_mask; 169 } TCR; 170 171 #define VTCR_NSW (1u << 29) 172 #define VTCR_NSA (1u << 30) 173 #define VSTCR_SW VTCR_NSW 174 #define VSTCR_SA VTCR_NSA 175 176 /* Define a maximum sized vector register. 177 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 178 * For 64-bit, this is a 2048-bit SVE register. 179 * 180 * Note that the mapping between S, D, and Q views of the register bank 181 * differs between AArch64 and AArch32. 182 * In AArch32: 183 * Qn = regs[n].d[1]:regs[n].d[0] 184 * Dn = regs[n / 2].d[n & 1] 185 * Sn = regs[n / 4].d[n % 4 / 2], 186 * bits 31..0 for even n, and bits 63..32 for odd n 187 * (and regs[16] to regs[31] are inaccessible) 188 * In AArch64: 189 * Zn = regs[n].d[*] 190 * Qn = regs[n].d[1]:regs[n].d[0] 191 * Dn = regs[n].d[0] 192 * Sn = regs[n].d[0] bits 31..0 193 * Hn = regs[n].d[0] bits 15..0 194 * 195 * This corresponds to the architecturally defined mapping between 196 * the two execution states, and means we do not need to explicitly 197 * map these registers when changing states. 198 * 199 * Align the data for use with TCG host vector operations. 200 */ 201 202 #ifdef TARGET_AARCH64 203 # define ARM_MAX_VQ 16 204 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 205 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); 206 #else 207 # define ARM_MAX_VQ 1 208 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 209 static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } 210 #endif 211 212 typedef struct ARMVectorReg { 213 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 214 } ARMVectorReg; 215 216 #ifdef TARGET_AARCH64 217 /* In AArch32 mode, predicate registers do not exist at all. */ 218 typedef struct ARMPredicateReg { 219 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 220 } ARMPredicateReg; 221 222 /* In AArch32 mode, PAC keys do not exist at all. */ 223 typedef struct ARMPACKey { 224 uint64_t lo, hi; 225 } ARMPACKey; 226 #endif 227 228 229 typedef struct CPUARMState { 230 /* Regs for current mode. */ 231 uint32_t regs[16]; 232 233 /* 32/64 switch only happens when taking and returning from 234 * exceptions so the overlap semantics are taken care of then 235 * instead of having a complicated union. 236 */ 237 /* Regs for A64 mode. */ 238 uint64_t xregs[32]; 239 uint64_t pc; 240 /* PSTATE isn't an architectural register for ARMv8. However, it is 241 * convenient for us to assemble the underlying state into a 32 bit format 242 * identical to the architectural format used for the SPSR. (This is also 243 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 244 * 'pstate' register are.) Of the PSTATE bits: 245 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 246 * semantics as for AArch32, as described in the comments on each field) 247 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 248 * DAIF (exception masks) are kept in env->daif 249 * BTYPE is kept in env->btype 250 * all other bits are stored in their correct places in env->pstate 251 */ 252 uint32_t pstate; 253 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 254 255 /* Cached TBFLAGS state. See below for which bits are included. */ 256 uint32_t hflags; 257 258 /* Frequently accessed CPSR bits are stored separately for efficiency. 259 This contains all the other bits. Use cpsr_{read,write} to access 260 the whole CPSR. */ 261 uint32_t uncached_cpsr; 262 uint32_t spsr; 263 264 /* Banked registers. */ 265 uint64_t banked_spsr[8]; 266 uint32_t banked_r13[8]; 267 uint32_t banked_r14[8]; 268 269 /* These hold r8-r12. */ 270 uint32_t usr_regs[5]; 271 uint32_t fiq_regs[5]; 272 273 /* cpsr flag cache for faster execution */ 274 uint32_t CF; /* 0 or 1 */ 275 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 276 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 277 uint32_t ZF; /* Z set if zero. */ 278 uint32_t QF; /* 0 or 1 */ 279 uint32_t GE; /* cpsr[19:16] */ 280 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 281 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 282 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 283 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 284 285 uint64_t elr_el[4]; /* AArch64 exception link regs */ 286 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 287 288 /* System control coprocessor (cp15) */ 289 struct { 290 uint32_t c0_cpuid; 291 union { /* Cache size selection */ 292 struct { 293 uint64_t _unused_csselr0; 294 uint64_t csselr_ns; 295 uint64_t _unused_csselr1; 296 uint64_t csselr_s; 297 }; 298 uint64_t csselr_el[4]; 299 }; 300 union { /* System control register. */ 301 struct { 302 uint64_t _unused_sctlr; 303 uint64_t sctlr_ns; 304 uint64_t hsctlr; 305 uint64_t sctlr_s; 306 }; 307 uint64_t sctlr_el[4]; 308 }; 309 uint64_t cpacr_el1; /* Architectural feature access control register */ 310 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 311 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 312 uint64_t sder; /* Secure debug enable register. */ 313 uint32_t nsacr; /* Non-secure access control register. */ 314 union { /* MMU translation table base 0. */ 315 struct { 316 uint64_t _unused_ttbr0_0; 317 uint64_t ttbr0_ns; 318 uint64_t _unused_ttbr0_1; 319 uint64_t ttbr0_s; 320 }; 321 uint64_t ttbr0_el[4]; 322 }; 323 union { /* MMU translation table base 1. */ 324 struct { 325 uint64_t _unused_ttbr1_0; 326 uint64_t ttbr1_ns; 327 uint64_t _unused_ttbr1_1; 328 uint64_t ttbr1_s; 329 }; 330 uint64_t ttbr1_el[4]; 331 }; 332 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 333 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 334 /* MMU translation table base control. */ 335 TCR tcr_el[4]; 336 TCR vtcr_el2; /* Virtualization Translation Control. */ 337 TCR vstcr_el2; /* Secure Virtualization Translation Control. */ 338 uint32_t c2_data; /* MPU data cacheable bits. */ 339 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 340 union { /* MMU domain access control register 341 * MPU write buffer control. 342 */ 343 struct { 344 uint64_t dacr_ns; 345 uint64_t dacr_s; 346 }; 347 struct { 348 uint64_t dacr32_el2; 349 }; 350 }; 351 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 352 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 353 uint64_t hcr_el2; /* Hypervisor configuration register */ 354 uint64_t scr_el3; /* Secure configuration register. */ 355 union { /* Fault status registers. */ 356 struct { 357 uint64_t ifsr_ns; 358 uint64_t ifsr_s; 359 }; 360 struct { 361 uint64_t ifsr32_el2; 362 }; 363 }; 364 union { 365 struct { 366 uint64_t _unused_dfsr; 367 uint64_t dfsr_ns; 368 uint64_t hsr; 369 uint64_t dfsr_s; 370 }; 371 uint64_t esr_el[4]; 372 }; 373 uint32_t c6_region[8]; /* MPU base/size registers. */ 374 union { /* Fault address registers. */ 375 struct { 376 uint64_t _unused_far0; 377 #ifdef HOST_WORDS_BIGENDIAN 378 uint32_t ifar_ns; 379 uint32_t dfar_ns; 380 uint32_t ifar_s; 381 uint32_t dfar_s; 382 #else 383 uint32_t dfar_ns; 384 uint32_t ifar_ns; 385 uint32_t dfar_s; 386 uint32_t ifar_s; 387 #endif 388 uint64_t _unused_far3; 389 }; 390 uint64_t far_el[4]; 391 }; 392 uint64_t hpfar_el2; 393 uint64_t hstr_el2; 394 union { /* Translation result. */ 395 struct { 396 uint64_t _unused_par_0; 397 uint64_t par_ns; 398 uint64_t _unused_par_1; 399 uint64_t par_s; 400 }; 401 uint64_t par_el[4]; 402 }; 403 404 uint32_t c9_insn; /* Cache lockdown registers. */ 405 uint32_t c9_data; 406 uint64_t c9_pmcr; /* performance monitor control register */ 407 uint64_t c9_pmcnten; /* perf monitor counter enables */ 408 uint64_t c9_pmovsr; /* perf monitor overflow status */ 409 uint64_t c9_pmuserenr; /* perf monitor user enable */ 410 uint64_t c9_pmselr; /* perf monitor counter selection register */ 411 uint64_t c9_pminten; /* perf monitor interrupt enables */ 412 union { /* Memory attribute redirection */ 413 struct { 414 #ifdef HOST_WORDS_BIGENDIAN 415 uint64_t _unused_mair_0; 416 uint32_t mair1_ns; 417 uint32_t mair0_ns; 418 uint64_t _unused_mair_1; 419 uint32_t mair1_s; 420 uint32_t mair0_s; 421 #else 422 uint64_t _unused_mair_0; 423 uint32_t mair0_ns; 424 uint32_t mair1_ns; 425 uint64_t _unused_mair_1; 426 uint32_t mair0_s; 427 uint32_t mair1_s; 428 #endif 429 }; 430 uint64_t mair_el[4]; 431 }; 432 union { /* vector base address register */ 433 struct { 434 uint64_t _unused_vbar; 435 uint64_t vbar_ns; 436 uint64_t hvbar; 437 uint64_t vbar_s; 438 }; 439 uint64_t vbar_el[4]; 440 }; 441 uint32_t mvbar; /* (monitor) vector base address register */ 442 struct { /* FCSE PID. */ 443 uint32_t fcseidr_ns; 444 uint32_t fcseidr_s; 445 }; 446 union { /* Context ID. */ 447 struct { 448 uint64_t _unused_contextidr_0; 449 uint64_t contextidr_ns; 450 uint64_t _unused_contextidr_1; 451 uint64_t contextidr_s; 452 }; 453 uint64_t contextidr_el[4]; 454 }; 455 union { /* User RW Thread register. */ 456 struct { 457 uint64_t tpidrurw_ns; 458 uint64_t tpidrprw_ns; 459 uint64_t htpidr; 460 uint64_t _tpidr_el3; 461 }; 462 uint64_t tpidr_el[4]; 463 }; 464 /* The secure banks of these registers don't map anywhere */ 465 uint64_t tpidrurw_s; 466 uint64_t tpidrprw_s; 467 uint64_t tpidruro_s; 468 469 union { /* User RO Thread register. */ 470 uint64_t tpidruro_ns; 471 uint64_t tpidrro_el[1]; 472 }; 473 uint64_t c14_cntfrq; /* Counter Frequency register */ 474 uint64_t c14_cntkctl; /* Timer Control register */ 475 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 476 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 477 ARMGenericTimer c14_timer[NUM_GTIMERS]; 478 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 479 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 480 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 481 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 482 uint32_t c15_threadid; /* TI debugger thread-ID. */ 483 uint32_t c15_config_base_address; /* SCU base address. */ 484 uint32_t c15_diagnostic; /* diagnostic register */ 485 uint32_t c15_power_diagnostic; 486 uint32_t c15_power_control; /* power control */ 487 uint64_t dbgbvr[16]; /* breakpoint value registers */ 488 uint64_t dbgbcr[16]; /* breakpoint control registers */ 489 uint64_t dbgwvr[16]; /* watchpoint value registers */ 490 uint64_t dbgwcr[16]; /* watchpoint control registers */ 491 uint64_t mdscr_el1; 492 uint64_t oslsr_el1; /* OS Lock Status */ 493 uint64_t mdcr_el2; 494 uint64_t mdcr_el3; 495 /* Stores the architectural value of the counter *the last time it was 496 * updated* by pmccntr_op_start. Accesses should always be surrounded 497 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 498 * architecturally-correct value is being read/set. 499 */ 500 uint64_t c15_ccnt; 501 /* Stores the delta between the architectural value and the underlying 502 * cycle count during normal operation. It is used to update c15_ccnt 503 * to be the correct architectural value before accesses. During 504 * accesses, c15_ccnt_delta contains the underlying count being used 505 * for the access, after which it reverts to the delta value in 506 * pmccntr_op_finish. 507 */ 508 uint64_t c15_ccnt_delta; 509 uint64_t c14_pmevcntr[31]; 510 uint64_t c14_pmevcntr_delta[31]; 511 uint64_t c14_pmevtyper[31]; 512 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 513 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 514 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 515 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 516 uint64_t gcr_el1; 517 uint64_t rgsr_el1; 518 } cp15; 519 520 struct { 521 /* M profile has up to 4 stack pointers: 522 * a Main Stack Pointer and a Process Stack Pointer for each 523 * of the Secure and Non-Secure states. (If the CPU doesn't support 524 * the security extension then it has only two SPs.) 525 * In QEMU we always store the currently active SP in regs[13], 526 * and the non-active SP for the current security state in 527 * v7m.other_sp. The stack pointers for the inactive security state 528 * are stored in other_ss_msp and other_ss_psp. 529 * switch_v7m_security_state() is responsible for rearranging them 530 * when we change security state. 531 */ 532 uint32_t other_sp; 533 uint32_t other_ss_msp; 534 uint32_t other_ss_psp; 535 uint32_t vecbase[M_REG_NUM_BANKS]; 536 uint32_t basepri[M_REG_NUM_BANKS]; 537 uint32_t control[M_REG_NUM_BANKS]; 538 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 539 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 540 uint32_t hfsr; /* HardFault Status */ 541 uint32_t dfsr; /* Debug Fault Status Register */ 542 uint32_t sfsr; /* Secure Fault Status Register */ 543 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 544 uint32_t bfar; /* BusFault Address */ 545 uint32_t sfar; /* Secure Fault Address Register */ 546 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 547 int exception; 548 uint32_t primask[M_REG_NUM_BANKS]; 549 uint32_t faultmask[M_REG_NUM_BANKS]; 550 uint32_t aircr; /* only holds r/w state if security extn implemented */ 551 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 552 uint32_t csselr[M_REG_NUM_BANKS]; 553 uint32_t scr[M_REG_NUM_BANKS]; 554 uint32_t msplim[M_REG_NUM_BANKS]; 555 uint32_t psplim[M_REG_NUM_BANKS]; 556 uint32_t fpcar[M_REG_NUM_BANKS]; 557 uint32_t fpccr[M_REG_NUM_BANKS]; 558 uint32_t fpdscr[M_REG_NUM_BANKS]; 559 uint32_t cpacr[M_REG_NUM_BANKS]; 560 uint32_t nsacr; 561 int ltpsize; 562 } v7m; 563 564 /* Information associated with an exception about to be taken: 565 * code which raises an exception must set cs->exception_index and 566 * the relevant parts of this structure; the cpu_do_interrupt function 567 * will then set the guest-visible registers as part of the exception 568 * entry process. 569 */ 570 struct { 571 uint32_t syndrome; /* AArch64 format syndrome register */ 572 uint32_t fsr; /* AArch32 format fault status register info */ 573 uint64_t vaddress; /* virtual addr associated with exception, if any */ 574 uint32_t target_el; /* EL the exception should be targeted for */ 575 /* If we implement EL2 we will also need to store information 576 * about the intermediate physical address for stage 2 faults. 577 */ 578 } exception; 579 580 /* Information associated with an SError */ 581 struct { 582 uint8_t pending; 583 uint8_t has_esr; 584 uint64_t esr; 585 } serror; 586 587 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 588 589 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 590 uint32_t irq_line_state; 591 592 /* Thumb-2 EE state. */ 593 uint32_t teecr; 594 uint32_t teehbr; 595 596 /* VFP coprocessor state. */ 597 struct { 598 ARMVectorReg zregs[32]; 599 600 #ifdef TARGET_AARCH64 601 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 602 #define FFR_PRED_NUM 16 603 ARMPredicateReg pregs[17]; 604 /* Scratch space for aa64 sve predicate temporary. */ 605 ARMPredicateReg preg_tmp; 606 #endif 607 608 /* We store these fpcsr fields separately for convenience. */ 609 uint32_t qc[4] QEMU_ALIGNED(16); 610 int vec_len; 611 int vec_stride; 612 613 uint32_t xregs[16]; 614 615 /* Scratch space for aa32 neon expansion. */ 616 uint32_t scratch[8]; 617 618 /* There are a number of distinct float control structures: 619 * 620 * fp_status: is the "normal" fp status. 621 * fp_status_fp16: used for half-precision calculations 622 * standard_fp_status : the ARM "Standard FPSCR Value" 623 * standard_fp_status_fp16 : used for half-precision 624 * calculations with the ARM "Standard FPSCR Value" 625 * 626 * Half-precision operations are governed by a separate 627 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 628 * status structure to control this. 629 * 630 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 631 * round-to-nearest and is used by any operations (generally 632 * Neon) which the architecture defines as controlled by the 633 * standard FPSCR value rather than the FPSCR. 634 * 635 * The "standard FPSCR but for fp16 ops" is needed because 636 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 637 * using a fixed value for it. 638 * 639 * To avoid having to transfer exception bits around, we simply 640 * say that the FPSCR cumulative exception flags are the logical 641 * OR of the flags in the four fp statuses. This relies on the 642 * only thing which needs to read the exception flags being 643 * an explicit FPSCR read. 644 */ 645 float_status fp_status; 646 float_status fp_status_f16; 647 float_status standard_fp_status; 648 float_status standard_fp_status_f16; 649 650 /* ZCR_EL[1-3] */ 651 uint64_t zcr_el[4]; 652 } vfp; 653 uint64_t exclusive_addr; 654 uint64_t exclusive_val; 655 uint64_t exclusive_high; 656 657 /* iwMMXt coprocessor state. */ 658 struct { 659 uint64_t regs[16]; 660 uint64_t val; 661 662 uint32_t cregs[16]; 663 } iwmmxt; 664 665 #ifdef TARGET_AARCH64 666 struct { 667 ARMPACKey apia; 668 ARMPACKey apib; 669 ARMPACKey apda; 670 ARMPACKey apdb; 671 ARMPACKey apga; 672 } keys; 673 #endif 674 675 #if defined(CONFIG_USER_ONLY) 676 /* For usermode syscall translation. */ 677 int eabi; 678 #endif 679 680 struct CPUBreakpoint *cpu_breakpoint[16]; 681 struct CPUWatchpoint *cpu_watchpoint[16]; 682 683 /* Fields up to this point are cleared by a CPU reset */ 684 struct {} end_reset_fields; 685 686 /* Fields after this point are preserved across CPU reset. */ 687 688 /* Internal CPU feature flags. */ 689 uint64_t features; 690 691 /* PMSAv7 MPU */ 692 struct { 693 uint32_t *drbar; 694 uint32_t *drsr; 695 uint32_t *dracr; 696 uint32_t rnr[M_REG_NUM_BANKS]; 697 } pmsav7; 698 699 /* PMSAv8 MPU */ 700 struct { 701 /* The PMSAv8 implementation also shares some PMSAv7 config 702 * and state: 703 * pmsav7.rnr (region number register) 704 * pmsav7_dregion (number of configured regions) 705 */ 706 uint32_t *rbar[M_REG_NUM_BANKS]; 707 uint32_t *rlar[M_REG_NUM_BANKS]; 708 uint32_t mair0[M_REG_NUM_BANKS]; 709 uint32_t mair1[M_REG_NUM_BANKS]; 710 } pmsav8; 711 712 /* v8M SAU */ 713 struct { 714 uint32_t *rbar; 715 uint32_t *rlar; 716 uint32_t rnr; 717 uint32_t ctrl; 718 } sau; 719 720 void *nvic; 721 const struct arm_boot_info *boot_info; 722 /* Store GICv3CPUState to access from this struct */ 723 void *gicv3state; 724 } CPUARMState; 725 726 static inline void set_feature(CPUARMState *env, int feature) 727 { 728 env->features |= 1ULL << feature; 729 } 730 731 static inline void unset_feature(CPUARMState *env, int feature) 732 { 733 env->features &= ~(1ULL << feature); 734 } 735 736 /** 737 * ARMELChangeHookFn: 738 * type of a function which can be registered via arm_register_el_change_hook() 739 * to get callbacks when the CPU changes its exception level or mode. 740 */ 741 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 742 typedef struct ARMELChangeHook ARMELChangeHook; 743 struct ARMELChangeHook { 744 ARMELChangeHookFn *hook; 745 void *opaque; 746 QLIST_ENTRY(ARMELChangeHook) node; 747 }; 748 749 /* These values map onto the return values for 750 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 751 typedef enum ARMPSCIState { 752 PSCI_ON = 0, 753 PSCI_OFF = 1, 754 PSCI_ON_PENDING = 2 755 } ARMPSCIState; 756 757 typedef struct ARMISARegisters ARMISARegisters; 758 759 /** 760 * ARMCPU: 761 * @env: #CPUARMState 762 * 763 * An ARM CPU core. 764 */ 765 struct ARMCPU { 766 /*< private >*/ 767 CPUState parent_obj; 768 /*< public >*/ 769 770 CPUNegativeOffsetState neg; 771 CPUARMState env; 772 773 /* Coprocessor information */ 774 GHashTable *cp_regs; 775 /* For marshalling (mostly coprocessor) register state between the 776 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 777 * we use these arrays. 778 */ 779 /* List of register indexes managed via these arrays; (full KVM style 780 * 64 bit indexes, not CPRegInfo 32 bit indexes) 781 */ 782 uint64_t *cpreg_indexes; 783 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 784 uint64_t *cpreg_values; 785 /* Length of the indexes, values, reset_values arrays */ 786 int32_t cpreg_array_len; 787 /* These are used only for migration: incoming data arrives in 788 * these fields and is sanity checked in post_load before copying 789 * to the working data structures above. 790 */ 791 uint64_t *cpreg_vmstate_indexes; 792 uint64_t *cpreg_vmstate_values; 793 int32_t cpreg_vmstate_array_len; 794 795 DynamicGDBXMLInfo dyn_sysreg_xml; 796 DynamicGDBXMLInfo dyn_svereg_xml; 797 798 /* Timers used by the generic (architected) timer */ 799 QEMUTimer *gt_timer[NUM_GTIMERS]; 800 /* 801 * Timer used by the PMU. Its state is restored after migration by 802 * pmu_op_finish() - it does not need other handling during migration 803 */ 804 QEMUTimer *pmu_timer; 805 /* GPIO outputs for generic timer */ 806 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 807 /* GPIO output for GICv3 maintenance interrupt signal */ 808 qemu_irq gicv3_maintenance_interrupt; 809 /* GPIO output for the PMU interrupt */ 810 qemu_irq pmu_interrupt; 811 812 /* MemoryRegion to use for secure physical accesses */ 813 MemoryRegion *secure_memory; 814 815 /* MemoryRegion to use for allocation tag accesses */ 816 MemoryRegion *tag_memory; 817 MemoryRegion *secure_tag_memory; 818 819 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 820 Object *idau; 821 822 /* 'compatible' string for this CPU for Linux device trees */ 823 const char *dtb_compatible; 824 825 /* PSCI version for this CPU 826 * Bits[31:16] = Major Version 827 * Bits[15:0] = Minor Version 828 */ 829 uint32_t psci_version; 830 831 /* Current power state, access guarded by BQL */ 832 ARMPSCIState power_state; 833 834 /* CPU has virtualization extension */ 835 bool has_el2; 836 /* CPU has security extension */ 837 bool has_el3; 838 /* CPU has PMU (Performance Monitor Unit) */ 839 bool has_pmu; 840 /* CPU has VFP */ 841 bool has_vfp; 842 /* CPU has Neon */ 843 bool has_neon; 844 /* CPU has M-profile DSP extension */ 845 bool has_dsp; 846 847 /* CPU has memory protection unit */ 848 bool has_mpu; 849 /* PMSAv7 MPU number of supported regions */ 850 uint32_t pmsav7_dregion; 851 /* v8M SAU number of supported regions */ 852 uint32_t sau_sregion; 853 854 /* PSCI conduit used to invoke PSCI methods 855 * 0 - disabled, 1 - smc, 2 - hvc 856 */ 857 uint32_t psci_conduit; 858 859 /* For v8M, initial value of the Secure VTOR */ 860 uint32_t init_svtor; 861 862 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 863 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 864 */ 865 uint32_t kvm_target; 866 867 /* KVM init features for this CPU */ 868 uint32_t kvm_init_features[7]; 869 870 /* KVM CPU state */ 871 872 /* KVM virtual time adjustment */ 873 bool kvm_adjvtime; 874 bool kvm_vtime_dirty; 875 uint64_t kvm_vtime; 876 877 /* KVM steal time */ 878 OnOffAuto kvm_steal_time; 879 880 /* Uniprocessor system with MP extensions */ 881 bool mp_is_up; 882 883 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 884 * and the probe failed (so we need to report the error in realize) 885 */ 886 bool host_cpu_probe_failed; 887 888 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 889 * register. 890 */ 891 int32_t core_count; 892 893 /* The instance init functions for implementation-specific subclasses 894 * set these fields to specify the implementation-dependent values of 895 * various constant registers and reset values of non-constant 896 * registers. 897 * Some of these might become QOM properties eventually. 898 * Field names match the official register names as defined in the 899 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 900 * is used for reset values of non-constant registers; no reset_ 901 * prefix means a constant register. 902 * Some of these registers are split out into a substructure that 903 * is shared with the translators to control the ISA. 904 * 905 * Note that if you add an ID register to the ARMISARegisters struct 906 * you need to also update the 32-bit and 64-bit versions of the 907 * kvm_arm_get_host_cpu_features() function to correctly populate the 908 * field by reading the value from the KVM vCPU. 909 */ 910 struct ARMISARegisters { 911 uint32_t id_isar0; 912 uint32_t id_isar1; 913 uint32_t id_isar2; 914 uint32_t id_isar3; 915 uint32_t id_isar4; 916 uint32_t id_isar5; 917 uint32_t id_isar6; 918 uint32_t id_mmfr0; 919 uint32_t id_mmfr1; 920 uint32_t id_mmfr2; 921 uint32_t id_mmfr3; 922 uint32_t id_mmfr4; 923 uint32_t id_pfr0; 924 uint32_t id_pfr1; 925 uint32_t mvfr0; 926 uint32_t mvfr1; 927 uint32_t mvfr2; 928 uint32_t id_dfr0; 929 uint32_t dbgdidr; 930 uint64_t id_aa64isar0; 931 uint64_t id_aa64isar1; 932 uint64_t id_aa64pfr0; 933 uint64_t id_aa64pfr1; 934 uint64_t id_aa64mmfr0; 935 uint64_t id_aa64mmfr1; 936 uint64_t id_aa64mmfr2; 937 uint64_t id_aa64dfr0; 938 uint64_t id_aa64dfr1; 939 } isar; 940 uint64_t midr; 941 uint32_t revidr; 942 uint32_t reset_fpsid; 943 uint64_t ctr; 944 uint32_t reset_sctlr; 945 uint64_t pmceid0; 946 uint64_t pmceid1; 947 uint32_t id_afr0; 948 uint64_t id_aa64afr0; 949 uint64_t id_aa64afr1; 950 uint64_t clidr; 951 uint64_t mp_affinity; /* MP ID without feature bits */ 952 /* The elements of this array are the CCSIDR values for each cache, 953 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 954 */ 955 uint64_t ccsidr[16]; 956 uint64_t reset_cbar; 957 uint32_t reset_auxcr; 958 bool reset_hivecs; 959 960 /* 961 * Intermediate values used during property parsing. 962 * Once finalized, the values should be read from ID_AA64ISAR1. 963 */ 964 bool prop_pauth; 965 bool prop_pauth_impdef; 966 967 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 968 uint32_t dcz_blocksize; 969 uint64_t rvbar; 970 971 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 972 int gic_num_lrs; /* number of list registers */ 973 int gic_vpribits; /* number of virtual priority bits */ 974 int gic_vprebits; /* number of virtual preemption bits */ 975 976 /* Whether the cfgend input is high (i.e. this CPU should reset into 977 * big-endian mode). This setting isn't used directly: instead it modifies 978 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 979 * architecture version. 980 */ 981 bool cfgend; 982 983 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 984 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 985 986 int32_t node_id; /* NUMA node this CPU belongs to */ 987 988 /* Used to synchronize KVM and QEMU in-kernel device levels */ 989 uint8_t device_irq_level; 990 991 /* Used to set the maximum vector length the cpu will support. */ 992 uint32_t sve_max_vq; 993 994 /* 995 * In sve_vq_map each set bit is a supported vector length of 996 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 997 * length in quadwords. 998 * 999 * While processing properties during initialization, corresponding 1000 * sve_vq_init bits are set for bits in sve_vq_map that have been 1001 * set by properties. 1002 */ 1003 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 1004 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 1005 1006 /* Generic timer counter frequency, in Hz */ 1007 uint64_t gt_cntfrq_hz; 1008 }; 1009 1010 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1011 1012 void arm_cpu_post_init(Object *obj); 1013 1014 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1015 1016 #ifndef CONFIG_USER_ONLY 1017 extern const VMStateDescription vmstate_arm_cpu; 1018 #endif 1019 1020 void arm_cpu_do_interrupt(CPUState *cpu); 1021 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1022 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 1023 1024 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1025 MemTxAttrs *attrs); 1026 1027 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1028 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1029 1030 /* 1031 * Helpers to dynamically generates XML descriptions of the sysregs 1032 * and SVE registers. Returns the number of registers in each set. 1033 */ 1034 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1035 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1036 1037 /* Returns the dynamically generated XML for the gdb stub. 1038 * Returns a pointer to the XML contents for the specified XML file or NULL 1039 * if the XML name doesn't match the predefined one. 1040 */ 1041 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1042 1043 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1044 int cpuid, void *opaque); 1045 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1046 int cpuid, void *opaque); 1047 1048 #ifdef TARGET_AARCH64 1049 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1050 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1051 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1052 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1053 int new_el, bool el0_a64); 1054 void aarch64_add_sve_properties(Object *obj); 1055 1056 /* 1057 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1058 * The byte at offset i from the start of the in-memory representation contains 1059 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1060 * lowest offsets are stored in the lowest memory addresses, then that nearly 1061 * matches QEMU's representation, which is to use an array of host-endian 1062 * uint64_t's, where the lower offsets are at the lower indices. To complete 1063 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1064 */ 1065 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1066 { 1067 #ifdef HOST_WORDS_BIGENDIAN 1068 int i; 1069 1070 for (i = 0; i < nr; ++i) { 1071 dst[i] = bswap64(src[i]); 1072 } 1073 1074 return dst; 1075 #else 1076 return src; 1077 #endif 1078 } 1079 1080 #else 1081 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1082 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1083 int n, bool a) 1084 { } 1085 static inline void aarch64_add_sve_properties(Object *obj) { } 1086 #endif 1087 1088 void aarch64_sync_32_to_64(CPUARMState *env); 1089 void aarch64_sync_64_to_32(CPUARMState *env); 1090 1091 int fp_exception_el(CPUARMState *env, int cur_el); 1092 int sve_exception_el(CPUARMState *env, int cur_el); 1093 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1094 1095 static inline bool is_a64(CPUARMState *env) 1096 { 1097 return env->aarch64; 1098 } 1099 1100 /* you can call this signal handler from your SIGBUS and SIGSEGV 1101 signal handlers to inform the virtual CPU of exceptions. non zero 1102 is returned if the signal was handled by the virtual CPU. */ 1103 int cpu_arm_signal_handler(int host_signum, void *pinfo, 1104 void *puc); 1105 1106 /** 1107 * pmu_op_start/finish 1108 * @env: CPUARMState 1109 * 1110 * Convert all PMU counters between their delta form (the typical mode when 1111 * they are enabled) and the guest-visible values. These two calls must 1112 * surround any action which might affect the counters. 1113 */ 1114 void pmu_op_start(CPUARMState *env); 1115 void pmu_op_finish(CPUARMState *env); 1116 1117 /* 1118 * Called when a PMU counter is due to overflow 1119 */ 1120 void arm_pmu_timer_cb(void *opaque); 1121 1122 /** 1123 * Functions to register as EL change hooks for PMU mode filtering 1124 */ 1125 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1126 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1127 1128 /* 1129 * pmu_init 1130 * @cpu: ARMCPU 1131 * 1132 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1133 * for the current configuration 1134 */ 1135 void pmu_init(ARMCPU *cpu); 1136 1137 /* SCTLR bit meanings. Several bits have been reused in newer 1138 * versions of the architecture; in that case we define constants 1139 * for both old and new bit meanings. Code which tests against those 1140 * bits should probably check or otherwise arrange that the CPU 1141 * is the architectural version it expects. 1142 */ 1143 #define SCTLR_M (1U << 0) 1144 #define SCTLR_A (1U << 1) 1145 #define SCTLR_C (1U << 2) 1146 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1147 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1148 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1149 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1150 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1151 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1152 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1153 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1154 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1155 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1156 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1157 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1158 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1159 #define SCTLR_SED (1U << 8) /* v8 onward */ 1160 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1161 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1162 #define SCTLR_F (1U << 10) /* up to v6 */ 1163 #define SCTLR_SW (1U << 10) /* v7 */ 1164 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1165 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1166 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1167 #define SCTLR_I (1U << 12) 1168 #define SCTLR_V (1U << 13) /* AArch32 only */ 1169 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1170 #define SCTLR_RR (1U << 14) /* up to v7 */ 1171 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1172 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1173 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1174 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1175 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1176 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1177 #define SCTLR_BR (1U << 17) /* PMSA only */ 1178 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1179 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1180 #define SCTLR_WXN (1U << 19) 1181 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1182 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1183 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1184 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1185 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1186 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1187 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1188 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1189 #define SCTLR_VE (1U << 24) /* up to v7 */ 1190 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1191 #define SCTLR_EE (1U << 25) 1192 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1193 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1194 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1195 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1196 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1197 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1198 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1199 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1200 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1201 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1202 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1203 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1204 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1205 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1206 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1207 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1208 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1209 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1210 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1211 1212 #define CPTR_TCPAC (1U << 31) 1213 #define CPTR_TTA (1U << 20) 1214 #define CPTR_TFP (1U << 10) 1215 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1216 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1217 1218 #define MDCR_EPMAD (1U << 21) 1219 #define MDCR_EDAD (1U << 20) 1220 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1221 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1222 #define MDCR_SDD (1U << 16) 1223 #define MDCR_SPD (3U << 14) 1224 #define MDCR_TDRA (1U << 11) 1225 #define MDCR_TDOSA (1U << 10) 1226 #define MDCR_TDA (1U << 9) 1227 #define MDCR_TDE (1U << 8) 1228 #define MDCR_HPME (1U << 7) 1229 #define MDCR_TPM (1U << 6) 1230 #define MDCR_TPMCR (1U << 5) 1231 #define MDCR_HPMN (0x1fU) 1232 1233 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1234 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1235 1236 #define CPSR_M (0x1fU) 1237 #define CPSR_T (1U << 5) 1238 #define CPSR_F (1U << 6) 1239 #define CPSR_I (1U << 7) 1240 #define CPSR_A (1U << 8) 1241 #define CPSR_E (1U << 9) 1242 #define CPSR_IT_2_7 (0xfc00U) 1243 #define CPSR_GE (0xfU << 16) 1244 #define CPSR_IL (1U << 20) 1245 #define CPSR_PAN (1U << 22) 1246 #define CPSR_J (1U << 24) 1247 #define CPSR_IT_0_1 (3U << 25) 1248 #define CPSR_Q (1U << 27) 1249 #define CPSR_V (1U << 28) 1250 #define CPSR_C (1U << 29) 1251 #define CPSR_Z (1U << 30) 1252 #define CPSR_N (1U << 31) 1253 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1254 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1255 1256 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1257 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1258 | CPSR_NZCV) 1259 /* Bits writable in user mode. */ 1260 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1261 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1262 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1263 1264 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1265 #define XPSR_EXCP 0x1ffU 1266 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1267 #define XPSR_IT_2_7 CPSR_IT_2_7 1268 #define XPSR_GE CPSR_GE 1269 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1270 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1271 #define XPSR_IT_0_1 CPSR_IT_0_1 1272 #define XPSR_Q CPSR_Q 1273 #define XPSR_V CPSR_V 1274 #define XPSR_C CPSR_C 1275 #define XPSR_Z CPSR_Z 1276 #define XPSR_N CPSR_N 1277 #define XPSR_NZCV CPSR_NZCV 1278 #define XPSR_IT CPSR_IT 1279 1280 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1281 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1282 #define TTBCR_PD0 (1U << 4) 1283 #define TTBCR_PD1 (1U << 5) 1284 #define TTBCR_EPD0 (1U << 7) 1285 #define TTBCR_IRGN0 (3U << 8) 1286 #define TTBCR_ORGN0 (3U << 10) 1287 #define TTBCR_SH0 (3U << 12) 1288 #define TTBCR_T1SZ (3U << 16) 1289 #define TTBCR_A1 (1U << 22) 1290 #define TTBCR_EPD1 (1U << 23) 1291 #define TTBCR_IRGN1 (3U << 24) 1292 #define TTBCR_ORGN1 (3U << 26) 1293 #define TTBCR_SH1 (1U << 28) 1294 #define TTBCR_EAE (1U << 31) 1295 1296 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1297 * Only these are valid when in AArch64 mode; in 1298 * AArch32 mode SPSRs are basically CPSR-format. 1299 */ 1300 #define PSTATE_SP (1U) 1301 #define PSTATE_M (0xFU) 1302 #define PSTATE_nRW (1U << 4) 1303 #define PSTATE_F (1U << 6) 1304 #define PSTATE_I (1U << 7) 1305 #define PSTATE_A (1U << 8) 1306 #define PSTATE_D (1U << 9) 1307 #define PSTATE_BTYPE (3U << 10) 1308 #define PSTATE_IL (1U << 20) 1309 #define PSTATE_SS (1U << 21) 1310 #define PSTATE_PAN (1U << 22) 1311 #define PSTATE_UAO (1U << 23) 1312 #define PSTATE_TCO (1U << 25) 1313 #define PSTATE_V (1U << 28) 1314 #define PSTATE_C (1U << 29) 1315 #define PSTATE_Z (1U << 30) 1316 #define PSTATE_N (1U << 31) 1317 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1318 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1319 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1320 /* Mode values for AArch64 */ 1321 #define PSTATE_MODE_EL3h 13 1322 #define PSTATE_MODE_EL3t 12 1323 #define PSTATE_MODE_EL2h 9 1324 #define PSTATE_MODE_EL2t 8 1325 #define PSTATE_MODE_EL1h 5 1326 #define PSTATE_MODE_EL1t 4 1327 #define PSTATE_MODE_EL0t 0 1328 1329 /* Write a new value to v7m.exception, thus transitioning into or out 1330 * of Handler mode; this may result in a change of active stack pointer. 1331 */ 1332 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1333 1334 /* Map EL and handler into a PSTATE_MODE. */ 1335 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1336 { 1337 return (el << 2) | handler; 1338 } 1339 1340 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1341 * interprocessing, so we don't attempt to sync with the cpsr state used by 1342 * the 32 bit decoder. 1343 */ 1344 static inline uint32_t pstate_read(CPUARMState *env) 1345 { 1346 int ZF; 1347 1348 ZF = (env->ZF == 0); 1349 return (env->NF & 0x80000000) | (ZF << 30) 1350 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1351 | env->pstate | env->daif | (env->btype << 10); 1352 } 1353 1354 static inline void pstate_write(CPUARMState *env, uint32_t val) 1355 { 1356 env->ZF = (~val) & PSTATE_Z; 1357 env->NF = val; 1358 env->CF = (val >> 29) & 1; 1359 env->VF = (val << 3) & 0x80000000; 1360 env->daif = val & PSTATE_DAIF; 1361 env->btype = (val >> 10) & 3; 1362 env->pstate = val & ~CACHED_PSTATE_BITS; 1363 } 1364 1365 /* Return the current CPSR value. */ 1366 uint32_t cpsr_read(CPUARMState *env); 1367 1368 typedef enum CPSRWriteType { 1369 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1370 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1371 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1372 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1373 } CPSRWriteType; 1374 1375 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1376 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1377 CPSRWriteType write_type); 1378 1379 /* Return the current xPSR value. */ 1380 static inline uint32_t xpsr_read(CPUARMState *env) 1381 { 1382 int ZF; 1383 ZF = (env->ZF == 0); 1384 return (env->NF & 0x80000000) | (ZF << 30) 1385 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1386 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1387 | ((env->condexec_bits & 0xfc) << 8) 1388 | (env->GE << 16) 1389 | env->v7m.exception; 1390 } 1391 1392 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1393 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1394 { 1395 if (mask & XPSR_NZCV) { 1396 env->ZF = (~val) & XPSR_Z; 1397 env->NF = val; 1398 env->CF = (val >> 29) & 1; 1399 env->VF = (val << 3) & 0x80000000; 1400 } 1401 if (mask & XPSR_Q) { 1402 env->QF = ((val & XPSR_Q) != 0); 1403 } 1404 if (mask & XPSR_GE) { 1405 env->GE = (val & XPSR_GE) >> 16; 1406 } 1407 #ifndef CONFIG_USER_ONLY 1408 if (mask & XPSR_T) { 1409 env->thumb = ((val & XPSR_T) != 0); 1410 } 1411 if (mask & XPSR_IT_0_1) { 1412 env->condexec_bits &= ~3; 1413 env->condexec_bits |= (val >> 25) & 3; 1414 } 1415 if (mask & XPSR_IT_2_7) { 1416 env->condexec_bits &= 3; 1417 env->condexec_bits |= (val >> 8) & 0xfc; 1418 } 1419 if (mask & XPSR_EXCP) { 1420 /* Note that this only happens on exception exit */ 1421 write_v7m_exception(env, val & XPSR_EXCP); 1422 } 1423 #endif 1424 } 1425 1426 #define HCR_VM (1ULL << 0) 1427 #define HCR_SWIO (1ULL << 1) 1428 #define HCR_PTW (1ULL << 2) 1429 #define HCR_FMO (1ULL << 3) 1430 #define HCR_IMO (1ULL << 4) 1431 #define HCR_AMO (1ULL << 5) 1432 #define HCR_VF (1ULL << 6) 1433 #define HCR_VI (1ULL << 7) 1434 #define HCR_VSE (1ULL << 8) 1435 #define HCR_FB (1ULL << 9) 1436 #define HCR_BSU_MASK (3ULL << 10) 1437 #define HCR_DC (1ULL << 12) 1438 #define HCR_TWI (1ULL << 13) 1439 #define HCR_TWE (1ULL << 14) 1440 #define HCR_TID0 (1ULL << 15) 1441 #define HCR_TID1 (1ULL << 16) 1442 #define HCR_TID2 (1ULL << 17) 1443 #define HCR_TID3 (1ULL << 18) 1444 #define HCR_TSC (1ULL << 19) 1445 #define HCR_TIDCP (1ULL << 20) 1446 #define HCR_TACR (1ULL << 21) 1447 #define HCR_TSW (1ULL << 22) 1448 #define HCR_TPCP (1ULL << 23) 1449 #define HCR_TPU (1ULL << 24) 1450 #define HCR_TTLB (1ULL << 25) 1451 #define HCR_TVM (1ULL << 26) 1452 #define HCR_TGE (1ULL << 27) 1453 #define HCR_TDZ (1ULL << 28) 1454 #define HCR_HCD (1ULL << 29) 1455 #define HCR_TRVM (1ULL << 30) 1456 #define HCR_RW (1ULL << 31) 1457 #define HCR_CD (1ULL << 32) 1458 #define HCR_ID (1ULL << 33) 1459 #define HCR_E2H (1ULL << 34) 1460 #define HCR_TLOR (1ULL << 35) 1461 #define HCR_TERR (1ULL << 36) 1462 #define HCR_TEA (1ULL << 37) 1463 #define HCR_MIOCNCE (1ULL << 38) 1464 /* RES0 bit 39 */ 1465 #define HCR_APK (1ULL << 40) 1466 #define HCR_API (1ULL << 41) 1467 #define HCR_NV (1ULL << 42) 1468 #define HCR_NV1 (1ULL << 43) 1469 #define HCR_AT (1ULL << 44) 1470 #define HCR_NV2 (1ULL << 45) 1471 #define HCR_FWB (1ULL << 46) 1472 #define HCR_FIEN (1ULL << 47) 1473 /* RES0 bit 48 */ 1474 #define HCR_TID4 (1ULL << 49) 1475 #define HCR_TICAB (1ULL << 50) 1476 #define HCR_AMVOFFEN (1ULL << 51) 1477 #define HCR_TOCU (1ULL << 52) 1478 #define HCR_ENSCXT (1ULL << 53) 1479 #define HCR_TTLBIS (1ULL << 54) 1480 #define HCR_TTLBOS (1ULL << 55) 1481 #define HCR_ATA (1ULL << 56) 1482 #define HCR_DCT (1ULL << 57) 1483 #define HCR_TID5 (1ULL << 58) 1484 #define HCR_TWEDEN (1ULL << 59) 1485 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1486 1487 #define HPFAR_NS (1ULL << 63) 1488 1489 #define SCR_NS (1U << 0) 1490 #define SCR_IRQ (1U << 1) 1491 #define SCR_FIQ (1U << 2) 1492 #define SCR_EA (1U << 3) 1493 #define SCR_FW (1U << 4) 1494 #define SCR_AW (1U << 5) 1495 #define SCR_NET (1U << 6) 1496 #define SCR_SMD (1U << 7) 1497 #define SCR_HCE (1U << 8) 1498 #define SCR_SIF (1U << 9) 1499 #define SCR_RW (1U << 10) 1500 #define SCR_ST (1U << 11) 1501 #define SCR_TWI (1U << 12) 1502 #define SCR_TWE (1U << 13) 1503 #define SCR_TLOR (1U << 14) 1504 #define SCR_TERR (1U << 15) 1505 #define SCR_APK (1U << 16) 1506 #define SCR_API (1U << 17) 1507 #define SCR_EEL2 (1U << 18) 1508 #define SCR_EASE (1U << 19) 1509 #define SCR_NMEA (1U << 20) 1510 #define SCR_FIEN (1U << 21) 1511 #define SCR_ENSCXT (1U << 25) 1512 #define SCR_ATA (1U << 26) 1513 1514 /* Return the current FPSCR value. */ 1515 uint32_t vfp_get_fpscr(CPUARMState *env); 1516 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1517 1518 /* FPCR, Floating Point Control Register 1519 * FPSR, Floating Poiht Status Register 1520 * 1521 * For A64 the FPSCR is split into two logically distinct registers, 1522 * FPCR and FPSR. However since they still use non-overlapping bits 1523 * we store the underlying state in fpscr and just mask on read/write. 1524 */ 1525 #define FPSR_MASK 0xf800009f 1526 #define FPCR_MASK 0x07ff9f00 1527 1528 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1529 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1530 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1531 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1532 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1533 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1534 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1535 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1536 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1537 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1538 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1539 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1540 #define FPCR_V (1 << 28) /* FP overflow flag */ 1541 #define FPCR_C (1 << 29) /* FP carry flag */ 1542 #define FPCR_Z (1 << 30) /* FP zero flag */ 1543 #define FPCR_N (1 << 31) /* FP negative flag */ 1544 1545 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1546 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1547 1548 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1549 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1550 1551 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1552 { 1553 return vfp_get_fpscr(env) & FPSR_MASK; 1554 } 1555 1556 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1557 { 1558 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1559 vfp_set_fpscr(env, new_fpscr); 1560 } 1561 1562 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1563 { 1564 return vfp_get_fpscr(env) & FPCR_MASK; 1565 } 1566 1567 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1568 { 1569 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1570 vfp_set_fpscr(env, new_fpscr); 1571 } 1572 1573 enum arm_cpu_mode { 1574 ARM_CPU_MODE_USR = 0x10, 1575 ARM_CPU_MODE_FIQ = 0x11, 1576 ARM_CPU_MODE_IRQ = 0x12, 1577 ARM_CPU_MODE_SVC = 0x13, 1578 ARM_CPU_MODE_MON = 0x16, 1579 ARM_CPU_MODE_ABT = 0x17, 1580 ARM_CPU_MODE_HYP = 0x1a, 1581 ARM_CPU_MODE_UND = 0x1b, 1582 ARM_CPU_MODE_SYS = 0x1f 1583 }; 1584 1585 /* VFP system registers. */ 1586 #define ARM_VFP_FPSID 0 1587 #define ARM_VFP_FPSCR 1 1588 #define ARM_VFP_MVFR2 5 1589 #define ARM_VFP_MVFR1 6 1590 #define ARM_VFP_MVFR0 7 1591 #define ARM_VFP_FPEXC 8 1592 #define ARM_VFP_FPINST 9 1593 #define ARM_VFP_FPINST2 10 1594 /* These ones are M-profile only */ 1595 #define ARM_VFP_FPSCR_NZCVQC 2 1596 #define ARM_VFP_VPR 12 1597 #define ARM_VFP_P0 13 1598 #define ARM_VFP_FPCXT_NS 14 1599 #define ARM_VFP_FPCXT_S 15 1600 1601 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1602 #define QEMU_VFP_FPSCR_NZCV 0xffff 1603 1604 /* iwMMXt coprocessor control registers. */ 1605 #define ARM_IWMMXT_wCID 0 1606 #define ARM_IWMMXT_wCon 1 1607 #define ARM_IWMMXT_wCSSF 2 1608 #define ARM_IWMMXT_wCASF 3 1609 #define ARM_IWMMXT_wCGR0 8 1610 #define ARM_IWMMXT_wCGR1 9 1611 #define ARM_IWMMXT_wCGR2 10 1612 #define ARM_IWMMXT_wCGR3 11 1613 1614 /* V7M CCR bits */ 1615 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1616 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1617 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1618 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1619 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1620 FIELD(V7M_CCR, STKALIGN, 9, 1) 1621 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1622 FIELD(V7M_CCR, DC, 16, 1) 1623 FIELD(V7M_CCR, IC, 17, 1) 1624 FIELD(V7M_CCR, BP, 18, 1) 1625 FIELD(V7M_CCR, LOB, 19, 1) 1626 FIELD(V7M_CCR, TRD, 20, 1) 1627 1628 /* V7M SCR bits */ 1629 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1630 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1631 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1632 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1633 1634 /* V7M AIRCR bits */ 1635 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1636 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1637 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1638 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1639 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1640 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1641 FIELD(V7M_AIRCR, PRIS, 14, 1) 1642 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1643 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1644 1645 /* V7M CFSR bits for MMFSR */ 1646 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1647 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1648 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1649 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1650 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1651 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1652 1653 /* V7M CFSR bits for BFSR */ 1654 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1655 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1656 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1657 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1658 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1659 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1660 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1661 1662 /* V7M CFSR bits for UFSR */ 1663 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1664 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1665 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1666 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1667 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1668 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1669 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1670 1671 /* V7M CFSR bit masks covering all of the subregister bits */ 1672 FIELD(V7M_CFSR, MMFSR, 0, 8) 1673 FIELD(V7M_CFSR, BFSR, 8, 8) 1674 FIELD(V7M_CFSR, UFSR, 16, 16) 1675 1676 /* V7M HFSR bits */ 1677 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1678 FIELD(V7M_HFSR, FORCED, 30, 1) 1679 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1680 1681 /* V7M DFSR bits */ 1682 FIELD(V7M_DFSR, HALTED, 0, 1) 1683 FIELD(V7M_DFSR, BKPT, 1, 1) 1684 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1685 FIELD(V7M_DFSR, VCATCH, 3, 1) 1686 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1687 1688 /* V7M SFSR bits */ 1689 FIELD(V7M_SFSR, INVEP, 0, 1) 1690 FIELD(V7M_SFSR, INVIS, 1, 1) 1691 FIELD(V7M_SFSR, INVER, 2, 1) 1692 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1693 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1694 FIELD(V7M_SFSR, LSPERR, 5, 1) 1695 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1696 FIELD(V7M_SFSR, LSERR, 7, 1) 1697 1698 /* v7M MPU_CTRL bits */ 1699 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1700 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1701 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1702 1703 /* v7M CLIDR bits */ 1704 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1705 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1706 FIELD(V7M_CLIDR, LOC, 24, 3) 1707 FIELD(V7M_CLIDR, LOUU, 27, 3) 1708 FIELD(V7M_CLIDR, ICB, 30, 2) 1709 1710 FIELD(V7M_CSSELR, IND, 0, 1) 1711 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1712 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1713 * define a mask for this and check that it doesn't permit running off 1714 * the end of the array. 1715 */ 1716 FIELD(V7M_CSSELR, INDEX, 0, 4) 1717 1718 /* v7M FPCCR bits */ 1719 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1720 FIELD(V7M_FPCCR, USER, 1, 1) 1721 FIELD(V7M_FPCCR, S, 2, 1) 1722 FIELD(V7M_FPCCR, THREAD, 3, 1) 1723 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1724 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1725 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1726 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1727 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1728 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1729 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1730 FIELD(V7M_FPCCR, RES0, 11, 15) 1731 FIELD(V7M_FPCCR, TS, 26, 1) 1732 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1733 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1734 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1735 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1736 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1737 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1738 #define R_V7M_FPCCR_BANKED_MASK \ 1739 (R_V7M_FPCCR_LSPACT_MASK | \ 1740 R_V7M_FPCCR_USER_MASK | \ 1741 R_V7M_FPCCR_THREAD_MASK | \ 1742 R_V7M_FPCCR_MMRDY_MASK | \ 1743 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1744 R_V7M_FPCCR_UFRDY_MASK | \ 1745 R_V7M_FPCCR_ASPEN_MASK) 1746 1747 /* 1748 * System register ID fields. 1749 */ 1750 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1751 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1752 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1753 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1754 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1755 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1756 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1757 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1758 FIELD(CLIDR_EL1, LOC, 24, 3) 1759 FIELD(CLIDR_EL1, LOUU, 27, 3) 1760 FIELD(CLIDR_EL1, ICB, 30, 3) 1761 1762 /* When FEAT_CCIDX is implemented */ 1763 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1764 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1765 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1766 1767 /* When FEAT_CCIDX is not implemented */ 1768 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1769 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1770 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1771 1772 FIELD(CTR_EL0, IMINLINE, 0, 4) 1773 FIELD(CTR_EL0, L1IP, 14, 2) 1774 FIELD(CTR_EL0, DMINLINE, 16, 4) 1775 FIELD(CTR_EL0, ERG, 20, 4) 1776 FIELD(CTR_EL0, CWG, 24, 4) 1777 FIELD(CTR_EL0, IDC, 28, 1) 1778 FIELD(CTR_EL0, DIC, 29, 1) 1779 FIELD(CTR_EL0, TMINLINE, 32, 6) 1780 1781 FIELD(MIDR_EL1, REVISION, 0, 4) 1782 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1783 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1784 FIELD(MIDR_EL1, VARIANT, 20, 4) 1785 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1786 1787 FIELD(ID_ISAR0, SWAP, 0, 4) 1788 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1789 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1790 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1791 FIELD(ID_ISAR0, COPROC, 16, 4) 1792 FIELD(ID_ISAR0, DEBUG, 20, 4) 1793 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1794 1795 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1796 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1797 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1798 FIELD(ID_ISAR1, EXTEND, 12, 4) 1799 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1800 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1801 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1802 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1803 1804 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1805 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1806 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1807 FIELD(ID_ISAR2, MULT, 12, 4) 1808 FIELD(ID_ISAR2, MULTS, 16, 4) 1809 FIELD(ID_ISAR2, MULTU, 20, 4) 1810 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1811 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1812 1813 FIELD(ID_ISAR3, SATURATE, 0, 4) 1814 FIELD(ID_ISAR3, SIMD, 4, 4) 1815 FIELD(ID_ISAR3, SVC, 8, 4) 1816 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1817 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1818 FIELD(ID_ISAR3, T32COPY, 20, 4) 1819 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1820 FIELD(ID_ISAR3, T32EE, 28, 4) 1821 1822 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1823 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1824 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1825 FIELD(ID_ISAR4, SMC, 12, 4) 1826 FIELD(ID_ISAR4, BARRIER, 16, 4) 1827 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1828 FIELD(ID_ISAR4, PSR_M, 24, 4) 1829 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1830 1831 FIELD(ID_ISAR5, SEVL, 0, 4) 1832 FIELD(ID_ISAR5, AES, 4, 4) 1833 FIELD(ID_ISAR5, SHA1, 8, 4) 1834 FIELD(ID_ISAR5, SHA2, 12, 4) 1835 FIELD(ID_ISAR5, CRC32, 16, 4) 1836 FIELD(ID_ISAR5, RDM, 24, 4) 1837 FIELD(ID_ISAR5, VCMA, 28, 4) 1838 1839 FIELD(ID_ISAR6, JSCVT, 0, 4) 1840 FIELD(ID_ISAR6, DP, 4, 4) 1841 FIELD(ID_ISAR6, FHM, 8, 4) 1842 FIELD(ID_ISAR6, SB, 12, 4) 1843 FIELD(ID_ISAR6, SPECRES, 16, 4) 1844 FIELD(ID_ISAR6, BF16, 20, 4) 1845 FIELD(ID_ISAR6, I8MM, 24, 4) 1846 1847 FIELD(ID_MMFR0, VMSA, 0, 4) 1848 FIELD(ID_MMFR0, PMSA, 4, 4) 1849 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 1850 FIELD(ID_MMFR0, SHARELVL, 12, 4) 1851 FIELD(ID_MMFR0, TCM, 16, 4) 1852 FIELD(ID_MMFR0, AUXREG, 20, 4) 1853 FIELD(ID_MMFR0, FCSE, 24, 4) 1854 FIELD(ID_MMFR0, INNERSHR, 28, 4) 1855 1856 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 1857 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 1858 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 1859 FIELD(ID_MMFR1, L1UNISW, 12, 4) 1860 FIELD(ID_MMFR1, L1HVD, 16, 4) 1861 FIELD(ID_MMFR1, L1UNI, 20, 4) 1862 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 1863 FIELD(ID_MMFR1, BPRED, 28, 4) 1864 1865 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 1866 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 1867 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 1868 FIELD(ID_MMFR2, HVDTLB, 12, 4) 1869 FIELD(ID_MMFR2, UNITLB, 16, 4) 1870 FIELD(ID_MMFR2, MEMBARR, 20, 4) 1871 FIELD(ID_MMFR2, WFISTALL, 24, 4) 1872 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 1873 1874 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 1875 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 1876 FIELD(ID_MMFR3, BPMAINT, 8, 4) 1877 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 1878 FIELD(ID_MMFR3, PAN, 16, 4) 1879 FIELD(ID_MMFR3, COHWALK, 20, 4) 1880 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 1881 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 1882 1883 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1884 FIELD(ID_MMFR4, AC2, 4, 4) 1885 FIELD(ID_MMFR4, XNX, 8, 4) 1886 FIELD(ID_MMFR4, CNP, 12, 4) 1887 FIELD(ID_MMFR4, HPDS, 16, 4) 1888 FIELD(ID_MMFR4, LSM, 20, 4) 1889 FIELD(ID_MMFR4, CCIDX, 24, 4) 1890 FIELD(ID_MMFR4, EVT, 28, 4) 1891 1892 FIELD(ID_MMFR5, ETS, 0, 4) 1893 1894 FIELD(ID_PFR0, STATE0, 0, 4) 1895 FIELD(ID_PFR0, STATE1, 4, 4) 1896 FIELD(ID_PFR0, STATE2, 8, 4) 1897 FIELD(ID_PFR0, STATE3, 12, 4) 1898 FIELD(ID_PFR0, CSV2, 16, 4) 1899 FIELD(ID_PFR0, AMU, 20, 4) 1900 FIELD(ID_PFR0, DIT, 24, 4) 1901 FIELD(ID_PFR0, RAS, 28, 4) 1902 1903 FIELD(ID_PFR1, PROGMOD, 0, 4) 1904 FIELD(ID_PFR1, SECURITY, 4, 4) 1905 FIELD(ID_PFR1, MPROGMOD, 8, 4) 1906 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 1907 FIELD(ID_PFR1, GENTIMER, 16, 4) 1908 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 1909 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 1910 FIELD(ID_PFR1, GIC, 28, 4) 1911 1912 FIELD(ID_PFR2, CSV3, 0, 4) 1913 FIELD(ID_PFR2, SSBS, 4, 4) 1914 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 1915 1916 FIELD(ID_AA64ISAR0, AES, 4, 4) 1917 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1918 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1919 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1920 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1921 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1922 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1923 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1924 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1925 FIELD(ID_AA64ISAR0, DP, 44, 4) 1926 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1927 FIELD(ID_AA64ISAR0, TS, 52, 4) 1928 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1929 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1930 1931 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1932 FIELD(ID_AA64ISAR1, APA, 4, 4) 1933 FIELD(ID_AA64ISAR1, API, 8, 4) 1934 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1935 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1936 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1937 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1938 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1939 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1940 FIELD(ID_AA64ISAR1, SB, 36, 4) 1941 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1942 FIELD(ID_AA64ISAR1, BF16, 44, 4) 1943 FIELD(ID_AA64ISAR1, DGH, 48, 4) 1944 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 1945 1946 FIELD(ID_AA64PFR0, EL0, 0, 4) 1947 FIELD(ID_AA64PFR0, EL1, 4, 4) 1948 FIELD(ID_AA64PFR0, EL2, 8, 4) 1949 FIELD(ID_AA64PFR0, EL3, 12, 4) 1950 FIELD(ID_AA64PFR0, FP, 16, 4) 1951 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1952 FIELD(ID_AA64PFR0, GIC, 24, 4) 1953 FIELD(ID_AA64PFR0, RAS, 28, 4) 1954 FIELD(ID_AA64PFR0, SVE, 32, 4) 1955 FIELD(ID_AA64PFR0, SEL2, 36, 4) 1956 FIELD(ID_AA64PFR0, MPAM, 40, 4) 1957 FIELD(ID_AA64PFR0, AMU, 44, 4) 1958 FIELD(ID_AA64PFR0, DIT, 48, 4) 1959 FIELD(ID_AA64PFR0, CSV2, 56, 4) 1960 FIELD(ID_AA64PFR0, CSV3, 60, 4) 1961 1962 FIELD(ID_AA64PFR1, BT, 0, 4) 1963 FIELD(ID_AA64PFR1, SSBS, 4, 4) 1964 FIELD(ID_AA64PFR1, MTE, 8, 4) 1965 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1966 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 1967 1968 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1969 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1970 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1971 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1972 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1973 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1974 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1975 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1976 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1977 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1978 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1979 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1980 FIELD(ID_AA64MMFR0, FGT, 56, 4) 1981 FIELD(ID_AA64MMFR0, ECV, 60, 4) 1982 1983 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1984 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1985 FIELD(ID_AA64MMFR1, VH, 8, 4) 1986 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1987 FIELD(ID_AA64MMFR1, LO, 16, 4) 1988 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1989 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1990 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1991 FIELD(ID_AA64MMFR1, TWED, 32, 4) 1992 FIELD(ID_AA64MMFR1, ETS, 36, 4) 1993 1994 FIELD(ID_AA64MMFR2, CNP, 0, 4) 1995 FIELD(ID_AA64MMFR2, UAO, 4, 4) 1996 FIELD(ID_AA64MMFR2, LSM, 8, 4) 1997 FIELD(ID_AA64MMFR2, IESB, 12, 4) 1998 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 1999 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2000 FIELD(ID_AA64MMFR2, NV, 24, 4) 2001 FIELD(ID_AA64MMFR2, ST, 28, 4) 2002 FIELD(ID_AA64MMFR2, AT, 32, 4) 2003 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2004 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2005 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2006 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2007 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2008 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2009 2010 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2011 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2012 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2013 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2014 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2015 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2016 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2017 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2018 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2019 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2020 2021 FIELD(ID_DFR0, COPDBG, 0, 4) 2022 FIELD(ID_DFR0, COPSDBG, 4, 4) 2023 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2024 FIELD(ID_DFR0, COPTRC, 12, 4) 2025 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2026 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2027 FIELD(ID_DFR0, PERFMON, 24, 4) 2028 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2029 2030 FIELD(ID_DFR1, MTPMU, 0, 4) 2031 2032 FIELD(DBGDIDR, SE_IMP, 12, 1) 2033 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2034 FIELD(DBGDIDR, VERSION, 16, 4) 2035 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2036 FIELD(DBGDIDR, BRPS, 24, 4) 2037 FIELD(DBGDIDR, WRPS, 28, 4) 2038 2039 FIELD(MVFR0, SIMDREG, 0, 4) 2040 FIELD(MVFR0, FPSP, 4, 4) 2041 FIELD(MVFR0, FPDP, 8, 4) 2042 FIELD(MVFR0, FPTRAP, 12, 4) 2043 FIELD(MVFR0, FPDIVIDE, 16, 4) 2044 FIELD(MVFR0, FPSQRT, 20, 4) 2045 FIELD(MVFR0, FPSHVEC, 24, 4) 2046 FIELD(MVFR0, FPROUND, 28, 4) 2047 2048 FIELD(MVFR1, FPFTZ, 0, 4) 2049 FIELD(MVFR1, FPDNAN, 4, 4) 2050 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2051 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2052 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2053 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2054 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2055 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2056 FIELD(MVFR1, FPHP, 24, 4) 2057 FIELD(MVFR1, SIMDFMAC, 28, 4) 2058 2059 FIELD(MVFR2, SIMDMISC, 0, 4) 2060 FIELD(MVFR2, FPMISC, 4, 4) 2061 2062 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2063 2064 /* If adding a feature bit which corresponds to a Linux ELF 2065 * HWCAP bit, remember to update the feature-bit-to-hwcap 2066 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2067 */ 2068 enum arm_features { 2069 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2070 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2071 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2072 ARM_FEATURE_V6, 2073 ARM_FEATURE_V6K, 2074 ARM_FEATURE_V7, 2075 ARM_FEATURE_THUMB2, 2076 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2077 ARM_FEATURE_NEON, 2078 ARM_FEATURE_M, /* Microcontroller profile. */ 2079 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2080 ARM_FEATURE_THUMB2EE, 2081 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2082 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2083 ARM_FEATURE_V4T, 2084 ARM_FEATURE_V5, 2085 ARM_FEATURE_STRONGARM, 2086 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2087 ARM_FEATURE_GENERIC_TIMER, 2088 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2089 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2090 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2091 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2092 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2093 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2094 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2095 ARM_FEATURE_V8, 2096 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2097 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2098 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2099 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2100 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2101 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2102 ARM_FEATURE_PMU, /* has PMU support */ 2103 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2104 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2105 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2106 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2107 }; 2108 2109 static inline int arm_feature(CPUARMState *env, int feature) 2110 { 2111 return (env->features & (1ULL << feature)) != 0; 2112 } 2113 2114 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2115 2116 #if !defined(CONFIG_USER_ONLY) 2117 /* Return true if exception levels below EL3 are in secure state, 2118 * or would be following an exception return to that level. 2119 * Unlike arm_is_secure() (which is always a question about the 2120 * _current_ state of the CPU) this doesn't care about the current 2121 * EL or mode. 2122 */ 2123 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2124 { 2125 if (arm_feature(env, ARM_FEATURE_EL3)) { 2126 return !(env->cp15.scr_el3 & SCR_NS); 2127 } else { 2128 /* If EL3 is not supported then the secure state is implementation 2129 * defined, in which case QEMU defaults to non-secure. 2130 */ 2131 return false; 2132 } 2133 } 2134 2135 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2136 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2137 { 2138 if (arm_feature(env, ARM_FEATURE_EL3)) { 2139 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2140 /* CPU currently in AArch64 state and EL3 */ 2141 return true; 2142 } else if (!is_a64(env) && 2143 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2144 /* CPU currently in AArch32 state and monitor mode */ 2145 return true; 2146 } 2147 } 2148 return false; 2149 } 2150 2151 /* Return true if the processor is in secure state */ 2152 static inline bool arm_is_secure(CPUARMState *env) 2153 { 2154 if (arm_is_el3_or_mon(env)) { 2155 return true; 2156 } 2157 return arm_is_secure_below_el3(env); 2158 } 2159 2160 /* 2161 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2162 * This corresponds to the pseudocode EL2Enabled() 2163 */ 2164 static inline bool arm_is_el2_enabled(CPUARMState *env) 2165 { 2166 if (arm_feature(env, ARM_FEATURE_EL2)) { 2167 if (arm_is_secure_below_el3(env)) { 2168 return (env->cp15.scr_el3 & SCR_EEL2) != 0; 2169 } 2170 return true; 2171 } 2172 return false; 2173 } 2174 2175 #else 2176 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2177 { 2178 return false; 2179 } 2180 2181 static inline bool arm_is_secure(CPUARMState *env) 2182 { 2183 return false; 2184 } 2185 2186 static inline bool arm_is_el2_enabled(CPUARMState *env) 2187 { 2188 return false; 2189 } 2190 #endif 2191 2192 /** 2193 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2194 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2195 * "for all purposes other than a direct read or write access of HCR_EL2." 2196 * Not included here is HCR_RW. 2197 */ 2198 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2199 2200 /* Return true if the specified exception level is running in AArch64 state. */ 2201 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2202 { 2203 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2204 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2205 */ 2206 assert(el >= 1 && el <= 3); 2207 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2208 2209 /* The highest exception level is always at the maximum supported 2210 * register width, and then lower levels have a register width controlled 2211 * by bits in the SCR or HCR registers. 2212 */ 2213 if (el == 3) { 2214 return aa64; 2215 } 2216 2217 if (arm_feature(env, ARM_FEATURE_EL3) && 2218 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2219 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2220 } 2221 2222 if (el == 2) { 2223 return aa64; 2224 } 2225 2226 if (arm_is_el2_enabled(env)) { 2227 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2228 } 2229 2230 return aa64; 2231 } 2232 2233 /* Function for determing whether guest cp register reads and writes should 2234 * access the secure or non-secure bank of a cp register. When EL3 is 2235 * operating in AArch32 state, the NS-bit determines whether the secure 2236 * instance of a cp register should be used. When EL3 is AArch64 (or if 2237 * it doesn't exist at all) then there is no register banking, and all 2238 * accesses are to the non-secure version. 2239 */ 2240 static inline bool access_secure_reg(CPUARMState *env) 2241 { 2242 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2243 !arm_el_is_aa64(env, 3) && 2244 !(env->cp15.scr_el3 & SCR_NS)); 2245 2246 return ret; 2247 } 2248 2249 /* Macros for accessing a specified CP register bank */ 2250 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2251 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2252 2253 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2254 do { \ 2255 if (_secure) { \ 2256 (_env)->cp15._regname##_s = (_val); \ 2257 } else { \ 2258 (_env)->cp15._regname##_ns = (_val); \ 2259 } \ 2260 } while (0) 2261 2262 /* Macros for automatically accessing a specific CP register bank depending on 2263 * the current secure state of the system. These macros are not intended for 2264 * supporting instruction translation reads/writes as these are dependent 2265 * solely on the SCR.NS bit and not the mode. 2266 */ 2267 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2268 A32_BANKED_REG_GET((_env), _regname, \ 2269 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2270 2271 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2272 A32_BANKED_REG_SET((_env), _regname, \ 2273 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2274 (_val)) 2275 2276 void arm_cpu_list(void); 2277 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2278 uint32_t cur_el, bool secure); 2279 2280 /* Interface between CPU and Interrupt controller. */ 2281 #ifndef CONFIG_USER_ONLY 2282 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2283 #else 2284 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2285 { 2286 return true; 2287 } 2288 #endif 2289 /** 2290 * armv7m_nvic_set_pending: mark the specified exception as pending 2291 * @opaque: the NVIC 2292 * @irq: the exception number to mark pending 2293 * @secure: false for non-banked exceptions or for the nonsecure 2294 * version of a banked exception, true for the secure version of a banked 2295 * exception. 2296 * 2297 * Marks the specified exception as pending. Note that we will assert() 2298 * if @secure is true and @irq does not specify one of the fixed set 2299 * of architecturally banked exceptions. 2300 */ 2301 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2302 /** 2303 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2304 * @opaque: the NVIC 2305 * @irq: the exception number to mark pending 2306 * @secure: false for non-banked exceptions or for the nonsecure 2307 * version of a banked exception, true for the secure version of a banked 2308 * exception. 2309 * 2310 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2311 * exceptions (exceptions generated in the course of trying to take 2312 * a different exception). 2313 */ 2314 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2315 /** 2316 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2317 * @opaque: the NVIC 2318 * @irq: the exception number to mark pending 2319 * @secure: false for non-banked exceptions or for the nonsecure 2320 * version of a banked exception, true for the secure version of a banked 2321 * exception. 2322 * 2323 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2324 * generated in the course of lazy stacking of FP registers. 2325 */ 2326 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2327 /** 2328 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2329 * exception, and whether it targets Secure state 2330 * @opaque: the NVIC 2331 * @pirq: set to pending exception number 2332 * @ptargets_secure: set to whether pending exception targets Secure 2333 * 2334 * This function writes the number of the highest priority pending 2335 * exception (the one which would be made active by 2336 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2337 * to true if the current highest priority pending exception should 2338 * be taken to Secure state, false for NS. 2339 */ 2340 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2341 bool *ptargets_secure); 2342 /** 2343 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2344 * @opaque: the NVIC 2345 * 2346 * Move the current highest priority pending exception from the pending 2347 * state to the active state, and update v7m.exception to indicate that 2348 * it is the exception currently being handled. 2349 */ 2350 void armv7m_nvic_acknowledge_irq(void *opaque); 2351 /** 2352 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2353 * @opaque: the NVIC 2354 * @irq: the exception number to complete 2355 * @secure: true if this exception was secure 2356 * 2357 * Returns: -1 if the irq was not active 2358 * 1 if completing this irq brought us back to base (no active irqs) 2359 * 0 if there is still an irq active after this one was completed 2360 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2361 */ 2362 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2363 /** 2364 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2365 * @opaque: the NVIC 2366 * @irq: the exception number to mark pending 2367 * @secure: false for non-banked exceptions or for the nonsecure 2368 * version of a banked exception, true for the secure version of a banked 2369 * exception. 2370 * 2371 * Return whether an exception is "ready", i.e. whether the exception is 2372 * enabled and is configured at a priority which would allow it to 2373 * interrupt the current execution priority. This controls whether the 2374 * RDY bit for it in the FPCCR is set. 2375 */ 2376 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2377 /** 2378 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2379 * @opaque: the NVIC 2380 * 2381 * Returns: the raw execution priority as defined by the v8M architecture. 2382 * This is the execution priority minus the effects of AIRCR.PRIS, 2383 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2384 * (v8M ARM ARM I_PKLD.) 2385 */ 2386 int armv7m_nvic_raw_execution_priority(void *opaque); 2387 /** 2388 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2389 * priority is negative for the specified security state. 2390 * @opaque: the NVIC 2391 * @secure: the security state to test 2392 * This corresponds to the pseudocode IsReqExecPriNeg(). 2393 */ 2394 #ifndef CONFIG_USER_ONLY 2395 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2396 #else 2397 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2398 { 2399 return false; 2400 } 2401 #endif 2402 2403 /* Interface for defining coprocessor registers. 2404 * Registers are defined in tables of arm_cp_reginfo structs 2405 * which are passed to define_arm_cp_regs(). 2406 */ 2407 2408 /* When looking up a coprocessor register we look for it 2409 * via an integer which encodes all of: 2410 * coprocessor number 2411 * Crn, Crm, opc1, opc2 fields 2412 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2413 * or via MRRC/MCRR?) 2414 * non-secure/secure bank (AArch32 only) 2415 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2416 * (In this case crn and opc2 should be zero.) 2417 * For AArch64, there is no 32/64 bit size distinction; 2418 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2419 * and 4 bit CRn and CRm. The encoding patterns are chosen 2420 * to be easy to convert to and from the KVM encodings, and also 2421 * so that the hashtable can contain both AArch32 and AArch64 2422 * registers (to allow for interprocessing where we might run 2423 * 32 bit code on a 64 bit core). 2424 */ 2425 /* This bit is private to our hashtable cpreg; in KVM register 2426 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2427 * in the upper bits of the 64 bit ID. 2428 */ 2429 #define CP_REG_AA64_SHIFT 28 2430 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2431 2432 /* To enable banking of coprocessor registers depending on ns-bit we 2433 * add a bit to distinguish between secure and non-secure cpregs in the 2434 * hashtable. 2435 */ 2436 #define CP_REG_NS_SHIFT 29 2437 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2438 2439 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2440 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2441 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2442 2443 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2444 (CP_REG_AA64_MASK | \ 2445 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2446 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2447 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2448 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2449 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2450 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2451 2452 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2453 * version used as a key for the coprocessor register hashtable 2454 */ 2455 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2456 { 2457 uint32_t cpregid = kvmid; 2458 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2459 cpregid |= CP_REG_AA64_MASK; 2460 } else { 2461 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2462 cpregid |= (1 << 15); 2463 } 2464 2465 /* KVM is always non-secure so add the NS flag on AArch32 register 2466 * entries. 2467 */ 2468 cpregid |= 1 << CP_REG_NS_SHIFT; 2469 } 2470 return cpregid; 2471 } 2472 2473 /* Convert a truncated 32 bit hashtable key into the full 2474 * 64 bit KVM register ID. 2475 */ 2476 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2477 { 2478 uint64_t kvmid; 2479 2480 if (cpregid & CP_REG_AA64_MASK) { 2481 kvmid = cpregid & ~CP_REG_AA64_MASK; 2482 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2483 } else { 2484 kvmid = cpregid & ~(1 << 15); 2485 if (cpregid & (1 << 15)) { 2486 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2487 } else { 2488 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2489 } 2490 } 2491 return kvmid; 2492 } 2493 2494 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2495 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2496 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2497 * TCG can assume the value to be constant (ie load at translate time) 2498 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2499 * indicates that the TB should not be ended after a write to this register 2500 * (the default is that the TB ends after cp writes). OVERRIDE permits 2501 * a register definition to override a previous definition for the 2502 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2503 * old must have the OVERRIDE bit set. 2504 * ALIAS indicates that this register is an alias view of some underlying 2505 * state which is also visible via another register, and that the other 2506 * register is handling migration and reset; registers marked ALIAS will not be 2507 * migrated but may have their state set by syncing of register state from KVM. 2508 * NO_RAW indicates that this register has no underlying state and does not 2509 * support raw access for state saving/loading; it will not be used for either 2510 * migration or KVM state synchronization. (Typically this is for "registers" 2511 * which are actually used as instructions for cache maintenance and so on.) 2512 * IO indicates that this register does I/O and therefore its accesses 2513 * need to be marked with gen_io_start() and also end the TB. In particular, 2514 * registers which implement clocks or timers require this. 2515 * RAISES_EXC is for when the read or write hook might raise an exception; 2516 * the generated code will synchronize the CPU state before calling the hook 2517 * so that it is safe for the hook to call raise_exception(). 2518 * NEWEL is for writes to registers that might change the exception 2519 * level - typically on older ARM chips. For those cases we need to 2520 * re-read the new el when recomputing the translation flags. 2521 */ 2522 #define ARM_CP_SPECIAL 0x0001 2523 #define ARM_CP_CONST 0x0002 2524 #define ARM_CP_64BIT 0x0004 2525 #define ARM_CP_SUPPRESS_TB_END 0x0008 2526 #define ARM_CP_OVERRIDE 0x0010 2527 #define ARM_CP_ALIAS 0x0020 2528 #define ARM_CP_IO 0x0040 2529 #define ARM_CP_NO_RAW 0x0080 2530 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2531 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2532 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2533 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2534 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2535 #define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) 2536 #define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) 2537 #define ARM_LAST_SPECIAL ARM_CP_DC_GZVA 2538 #define ARM_CP_FPU 0x1000 2539 #define ARM_CP_SVE 0x2000 2540 #define ARM_CP_NO_GDB 0x4000 2541 #define ARM_CP_RAISES_EXC 0x8000 2542 #define ARM_CP_NEWEL 0x10000 2543 /* Used only as a terminator for ARMCPRegInfo lists */ 2544 #define ARM_CP_SENTINEL 0xfffff 2545 /* Mask of only the flag bits in a type field */ 2546 #define ARM_CP_FLAG_MASK 0x1f0ff 2547 2548 /* Valid values for ARMCPRegInfo state field, indicating which of 2549 * the AArch32 and AArch64 execution states this register is visible in. 2550 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2551 * If the reginfo is declared to be visible in both states then a second 2552 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2553 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2554 * Note that we rely on the values of these enums as we iterate through 2555 * the various states in some places. 2556 */ 2557 enum { 2558 ARM_CP_STATE_AA32 = 0, 2559 ARM_CP_STATE_AA64 = 1, 2560 ARM_CP_STATE_BOTH = 2, 2561 }; 2562 2563 /* ARM CP register secure state flags. These flags identify security state 2564 * attributes for a given CP register entry. 2565 * The existence of both or neither secure and non-secure flags indicates that 2566 * the register has both a secure and non-secure hash entry. A single one of 2567 * these flags causes the register to only be hashed for the specified 2568 * security state. 2569 * Although definitions may have any combination of the S/NS bits, each 2570 * registered entry will only have one to identify whether the entry is secure 2571 * or non-secure. 2572 */ 2573 enum { 2574 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2575 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2576 }; 2577 2578 /* Return true if cptype is a valid type field. This is used to try to 2579 * catch errors where the sentinel has been accidentally left off the end 2580 * of a list of registers. 2581 */ 2582 static inline bool cptype_valid(int cptype) 2583 { 2584 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2585 || ((cptype & ARM_CP_SPECIAL) && 2586 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2587 } 2588 2589 /* Access rights: 2590 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2591 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2592 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2593 * (ie any of the privileged modes in Secure state, or Monitor mode). 2594 * If a register is accessible in one privilege level it's always accessible 2595 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2596 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2597 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2598 * terminology a little and call this PL3. 2599 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2600 * with the ELx exception levels. 2601 * 2602 * If access permissions for a register are more complex than can be 2603 * described with these bits, then use a laxer set of restrictions, and 2604 * do the more restrictive/complex check inside a helper function. 2605 */ 2606 #define PL3_R 0x80 2607 #define PL3_W 0x40 2608 #define PL2_R (0x20 | PL3_R) 2609 #define PL2_W (0x10 | PL3_W) 2610 #define PL1_R (0x08 | PL2_R) 2611 #define PL1_W (0x04 | PL2_W) 2612 #define PL0_R (0x02 | PL1_R) 2613 #define PL0_W (0x01 | PL1_W) 2614 2615 /* 2616 * For user-mode some registers are accessible to EL0 via a kernel 2617 * trap-and-emulate ABI. In this case we define the read permissions 2618 * as actually being PL0_R. However some bits of any given register 2619 * may still be masked. 2620 */ 2621 #ifdef CONFIG_USER_ONLY 2622 #define PL0U_R PL0_R 2623 #else 2624 #define PL0U_R PL1_R 2625 #endif 2626 2627 #define PL3_RW (PL3_R | PL3_W) 2628 #define PL2_RW (PL2_R | PL2_W) 2629 #define PL1_RW (PL1_R | PL1_W) 2630 #define PL0_RW (PL0_R | PL0_W) 2631 2632 /* Return the highest implemented Exception Level */ 2633 static inline int arm_highest_el(CPUARMState *env) 2634 { 2635 if (arm_feature(env, ARM_FEATURE_EL3)) { 2636 return 3; 2637 } 2638 if (arm_feature(env, ARM_FEATURE_EL2)) { 2639 return 2; 2640 } 2641 return 1; 2642 } 2643 2644 /* Return true if a v7M CPU is in Handler mode */ 2645 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2646 { 2647 return env->v7m.exception != 0; 2648 } 2649 2650 /* Return the current Exception Level (as per ARMv8; note that this differs 2651 * from the ARMv7 Privilege Level). 2652 */ 2653 static inline int arm_current_el(CPUARMState *env) 2654 { 2655 if (arm_feature(env, ARM_FEATURE_M)) { 2656 return arm_v7m_is_handler_mode(env) || 2657 !(env->v7m.control[env->v7m.secure] & 1); 2658 } 2659 2660 if (is_a64(env)) { 2661 return extract32(env->pstate, 2, 2); 2662 } 2663 2664 switch (env->uncached_cpsr & 0x1f) { 2665 case ARM_CPU_MODE_USR: 2666 return 0; 2667 case ARM_CPU_MODE_HYP: 2668 return 2; 2669 case ARM_CPU_MODE_MON: 2670 return 3; 2671 default: 2672 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2673 /* If EL3 is 32-bit then all secure privileged modes run in 2674 * EL3 2675 */ 2676 return 3; 2677 } 2678 2679 return 1; 2680 } 2681 } 2682 2683 typedef struct ARMCPRegInfo ARMCPRegInfo; 2684 2685 typedef enum CPAccessResult { 2686 /* Access is permitted */ 2687 CP_ACCESS_OK = 0, 2688 /* Access fails due to a configurable trap or enable which would 2689 * result in a categorized exception syndrome giving information about 2690 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2691 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2692 * PL1 if in EL0, otherwise to the current EL). 2693 */ 2694 CP_ACCESS_TRAP = 1, 2695 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2696 * Note that this is not a catch-all case -- the set of cases which may 2697 * result in this failure is specifically defined by the architecture. 2698 */ 2699 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2700 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2701 CP_ACCESS_TRAP_EL2 = 3, 2702 CP_ACCESS_TRAP_EL3 = 4, 2703 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2704 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2705 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2706 /* Access fails and results in an exception syndrome for an FP access, 2707 * trapped directly to EL2 or EL3 2708 */ 2709 CP_ACCESS_TRAP_FP_EL2 = 7, 2710 CP_ACCESS_TRAP_FP_EL3 = 8, 2711 } CPAccessResult; 2712 2713 /* Access functions for coprocessor registers. These cannot fail and 2714 * may not raise exceptions. 2715 */ 2716 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2717 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2718 uint64_t value); 2719 /* Access permission check functions for coprocessor registers. */ 2720 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2721 const ARMCPRegInfo *opaque, 2722 bool isread); 2723 /* Hook function for register reset */ 2724 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2725 2726 #define CP_ANY 0xff 2727 2728 /* Definition of an ARM coprocessor register */ 2729 struct ARMCPRegInfo { 2730 /* Name of register (useful mainly for debugging, need not be unique) */ 2731 const char *name; 2732 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2733 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2734 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2735 * will be decoded to this register. The register read and write 2736 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2737 * used by the program, so it is possible to register a wildcard and 2738 * then behave differently on read/write if necessary. 2739 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2740 * must both be zero. 2741 * For AArch64-visible registers, opc0 is also used. 2742 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2743 * way to distinguish (for KVM's benefit) guest-visible system registers 2744 * from demuxed ones provided to preserve the "no side effects on 2745 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2746 * visible (to match KVM's encoding); cp==0 will be converted to 2747 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2748 */ 2749 uint8_t cp; 2750 uint8_t crn; 2751 uint8_t crm; 2752 uint8_t opc0; 2753 uint8_t opc1; 2754 uint8_t opc2; 2755 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2756 int state; 2757 /* Register type: ARM_CP_* bits/values */ 2758 int type; 2759 /* Access rights: PL*_[RW] */ 2760 int access; 2761 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2762 int secure; 2763 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2764 * this register was defined: can be used to hand data through to the 2765 * register read/write functions, since they are passed the ARMCPRegInfo*. 2766 */ 2767 void *opaque; 2768 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2769 * fieldoffset is non-zero, the reset value of the register. 2770 */ 2771 uint64_t resetvalue; 2772 /* Offset of the field in CPUARMState for this register. 2773 * 2774 * This is not needed if either: 2775 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2776 * 2. both readfn and writefn are specified 2777 */ 2778 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2779 2780 /* Offsets of the secure and non-secure fields in CPUARMState for the 2781 * register if it is banked. These fields are only used during the static 2782 * registration of a register. During hashing the bank associated 2783 * with a given security state is copied to fieldoffset which is used from 2784 * there on out. 2785 * 2786 * It is expected that register definitions use either fieldoffset or 2787 * bank_fieldoffsets in the definition but not both. It is also expected 2788 * that both bank offsets are set when defining a banked register. This 2789 * use indicates that a register is banked. 2790 */ 2791 ptrdiff_t bank_fieldoffsets[2]; 2792 2793 /* Function for making any access checks for this register in addition to 2794 * those specified by the 'access' permissions bits. If NULL, no extra 2795 * checks required. The access check is performed at runtime, not at 2796 * translate time. 2797 */ 2798 CPAccessFn *accessfn; 2799 /* Function for handling reads of this register. If NULL, then reads 2800 * will be done by loading from the offset into CPUARMState specified 2801 * by fieldoffset. 2802 */ 2803 CPReadFn *readfn; 2804 /* Function for handling writes of this register. If NULL, then writes 2805 * will be done by writing to the offset into CPUARMState specified 2806 * by fieldoffset. 2807 */ 2808 CPWriteFn *writefn; 2809 /* Function for doing a "raw" read; used when we need to copy 2810 * coprocessor state to the kernel for KVM or out for 2811 * migration. This only needs to be provided if there is also a 2812 * readfn and it has side effects (for instance clear-on-read bits). 2813 */ 2814 CPReadFn *raw_readfn; 2815 /* Function for doing a "raw" write; used when we need to copy KVM 2816 * kernel coprocessor state into userspace, or for inbound 2817 * migration. This only needs to be provided if there is also a 2818 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2819 * or similar behaviour. 2820 */ 2821 CPWriteFn *raw_writefn; 2822 /* Function for resetting the register. If NULL, then reset will be done 2823 * by writing resetvalue to the field specified in fieldoffset. If 2824 * fieldoffset is 0 then no reset will be done. 2825 */ 2826 CPResetFn *resetfn; 2827 2828 /* 2829 * "Original" writefn and readfn. 2830 * For ARMv8.1-VHE register aliases, we overwrite the read/write 2831 * accessor functions of various EL1/EL0 to perform the runtime 2832 * check for which sysreg should actually be modified, and then 2833 * forwards the operation. Before overwriting the accessors, 2834 * the original function is copied here, so that accesses that 2835 * really do go to the EL1/EL0 version proceed normally. 2836 * (The corresponding EL2 register is linked via opaque.) 2837 */ 2838 CPReadFn *orig_readfn; 2839 CPWriteFn *orig_writefn; 2840 }; 2841 2842 /* Macros which are lvalues for the field in CPUARMState for the 2843 * ARMCPRegInfo *ri. 2844 */ 2845 #define CPREG_FIELD32(env, ri) \ 2846 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2847 #define CPREG_FIELD64(env, ri) \ 2848 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2849 2850 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2851 2852 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2853 const ARMCPRegInfo *regs, void *opaque); 2854 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2855 const ARMCPRegInfo *regs, void *opaque); 2856 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2857 { 2858 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2859 } 2860 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2861 { 2862 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2863 } 2864 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2865 2866 /* 2867 * Definition of an ARM co-processor register as viewed from 2868 * userspace. This is used for presenting sanitised versions of 2869 * registers to userspace when emulating the Linux AArch64 CPU 2870 * ID/feature ABI (advertised as HWCAP_CPUID). 2871 */ 2872 typedef struct ARMCPRegUserSpaceInfo { 2873 /* Name of register */ 2874 const char *name; 2875 2876 /* Is the name actually a glob pattern */ 2877 bool is_glob; 2878 2879 /* Only some bits are exported to user space */ 2880 uint64_t exported_bits; 2881 2882 /* Fixed bits are applied after the mask */ 2883 uint64_t fixed_bits; 2884 } ARMCPRegUserSpaceInfo; 2885 2886 #define REGUSERINFO_SENTINEL { .name = NULL } 2887 2888 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2889 2890 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2891 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2892 uint64_t value); 2893 /* CPReadFn that can be used for read-as-zero behaviour */ 2894 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2895 2896 /* CPResetFn that does nothing, for use if no reset is required even 2897 * if fieldoffset is non zero. 2898 */ 2899 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2900 2901 /* Return true if this reginfo struct's field in the cpu state struct 2902 * is 64 bits wide. 2903 */ 2904 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2905 { 2906 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2907 } 2908 2909 static inline bool cp_access_ok(int current_el, 2910 const ARMCPRegInfo *ri, int isread) 2911 { 2912 return (ri->access >> ((current_el * 2) + isread)) & 1; 2913 } 2914 2915 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2916 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2917 2918 /** 2919 * write_list_to_cpustate 2920 * @cpu: ARMCPU 2921 * 2922 * For each register listed in the ARMCPU cpreg_indexes list, write 2923 * its value from the cpreg_values list into the ARMCPUState structure. 2924 * This updates TCG's working data structures from KVM data or 2925 * from incoming migration state. 2926 * 2927 * Returns: true if all register values were updated correctly, 2928 * false if some register was unknown or could not be written. 2929 * Note that we do not stop early on failure -- we will attempt 2930 * writing all registers in the list. 2931 */ 2932 bool write_list_to_cpustate(ARMCPU *cpu); 2933 2934 /** 2935 * write_cpustate_to_list: 2936 * @cpu: ARMCPU 2937 * @kvm_sync: true if this is for syncing back to KVM 2938 * 2939 * For each register listed in the ARMCPU cpreg_indexes list, write 2940 * its value from the ARMCPUState structure into the cpreg_values list. 2941 * This is used to copy info from TCG's working data structures into 2942 * KVM or for outbound migration. 2943 * 2944 * @kvm_sync is true if we are doing this in order to sync the 2945 * register state back to KVM. In this case we will only update 2946 * values in the list if the previous list->cpustate sync actually 2947 * successfully wrote the CPU state. Otherwise we will keep the value 2948 * that is in the list. 2949 * 2950 * Returns: true if all register values were read correctly, 2951 * false if some register was unknown or could not be read. 2952 * Note that we do not stop early on failure -- we will attempt 2953 * reading all registers in the list. 2954 */ 2955 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2956 2957 #define ARM_CPUID_TI915T 0x54029152 2958 #define ARM_CPUID_TI925T 0x54029252 2959 2960 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2961 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2962 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2963 2964 #define cpu_signal_handler cpu_arm_signal_handler 2965 #define cpu_list arm_cpu_list 2966 2967 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2968 * 2969 * If EL3 is 64-bit: 2970 * + NonSecure EL1 & 0 stage 1 2971 * + NonSecure EL1 & 0 stage 2 2972 * + NonSecure EL2 2973 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2974 * + Secure EL1 & 0 2975 * + Secure EL3 2976 * If EL3 is 32-bit: 2977 * + NonSecure PL1 & 0 stage 1 2978 * + NonSecure PL1 & 0 stage 2 2979 * + NonSecure PL2 2980 * + Secure PL0 2981 * + Secure PL1 2982 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2983 * 2984 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2985 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2986 * because they may differ in access permissions even if the VA->PA map is 2987 * the same 2988 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2989 * translation, which means that we have one mmu_idx that deals with two 2990 * concatenated translation regimes [this sort of combined s1+2 TLB is 2991 * architecturally permitted] 2992 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2993 * handling via the TLB. The only way to do a stage 1 translation without 2994 * the immediate stage 2 translation is via the ATS or AT system insns, 2995 * which can be slow-pathed and always do a page table walk. 2996 * The only use of stage 2 translations is either as part of an s1+2 2997 * lookup or when loading the descriptors during a stage 1 page table walk, 2998 * and in both those cases we don't use the TLB. 2999 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 3000 * translation regimes, because they map reasonably well to each other 3001 * and they can't both be active at the same time. 3002 * 5. we want to be able to use the TLB for accesses done as part of a 3003 * stage1 page table walk, rather than having to walk the stage2 page 3004 * table over and over. 3005 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 3006 * Never (PAN) bit within PSTATE. 3007 * 3008 * This gives us the following list of cases: 3009 * 3010 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 3011 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 3012 * NS EL1 EL1&0 stage 1+2 +PAN 3013 * NS EL0 EL2&0 3014 * NS EL2 EL2&0 3015 * NS EL2 EL2&0 +PAN 3016 * NS EL2 (aka NS PL2) 3017 * S EL0 EL1&0 (aka S PL0) 3018 * S EL1 EL1&0 (not used if EL3 is 32 bit) 3019 * S EL1 EL1&0 +PAN 3020 * S EL3 (aka S PL1) 3021 * 3022 * for a total of 11 different mmu_idx. 3023 * 3024 * R profile CPUs have an MPU, but can use the same set of MMU indexes 3025 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 3026 * NS EL2 if we ever model a Cortex-R52). 3027 * 3028 * M profile CPUs are rather different as they do not have a true MMU. 3029 * They have the following different MMU indexes: 3030 * User 3031 * Privileged 3032 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 3033 * Privileged, execution priority negative (ditto) 3034 * If the CPU supports the v8M Security Extension then there are also: 3035 * Secure User 3036 * Secure Privileged 3037 * Secure User, execution priority negative 3038 * Secure Privileged, execution priority negative 3039 * 3040 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 3041 * are not quite the same -- different CPU types (most notably M profile 3042 * vs A/R profile) would like to use MMU indexes with different semantics, 3043 * but since we don't ever need to use all of those in a single CPU we 3044 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 3045 * modes + total number of M profile MMU modes". The lower bits of 3046 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 3047 * the same for any particular CPU. 3048 * Variables of type ARMMUIdx are always full values, and the core 3049 * index values are in variables of type 'int'. 3050 * 3051 * Our enumeration includes at the end some entries which are not "true" 3052 * mmu_idx values in that they don't have corresponding TLBs and are only 3053 * valid for doing slow path page table walks. 3054 * 3055 * The constant names here are patterned after the general style of the names 3056 * of the AT/ATS operations. 3057 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 3058 * For M profile we arrange them to have a bit for priv, a bit for negpri 3059 * and a bit for secure. 3060 */ 3061 #define ARM_MMU_IDX_A 0x10 /* A profile */ 3062 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 3063 #define ARM_MMU_IDX_M 0x40 /* M profile */ 3064 3065 /* Meanings of the bits for A profile mmu idx values */ 3066 #define ARM_MMU_IDX_A_NS 0x8 3067 3068 /* Meanings of the bits for M profile mmu idx values */ 3069 #define ARM_MMU_IDX_M_PRIV 0x1 3070 #define ARM_MMU_IDX_M_NEGPRI 0x2 3071 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 3072 3073 #define ARM_MMU_IDX_TYPE_MASK \ 3074 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 3075 #define ARM_MMU_IDX_COREIDX_MASK 0xf 3076 3077 typedef enum ARMMMUIdx { 3078 /* 3079 * A-profile. 3080 */ 3081 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, 3082 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, 3083 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, 3084 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, 3085 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, 3086 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, 3087 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, 3088 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, 3089 3090 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, 3091 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, 3092 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, 3093 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, 3094 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, 3095 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, 3096 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, 3097 3098 /* 3099 * These are not allocated TLBs and are used only for AT system 3100 * instructions or for the first stage of an S12 page table walk. 3101 */ 3102 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 3103 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 3104 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 3105 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, 3106 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, 3107 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, 3108 /* 3109 * Not allocated a TLB: used only for second stage of an S12 page 3110 * table walk, or for descriptor loads during first stage of an S1 3111 * page table walk. Note that if we ever want to have a TLB for this 3112 * then various TLB flush insns which currently are no-ops or flush 3113 * only stage 1 MMU indexes will need to change to flush stage 2. 3114 */ 3115 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, 3116 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, 3117 3118 /* 3119 * M-profile. 3120 */ 3121 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 3122 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 3123 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 3124 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 3125 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 3126 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 3127 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 3128 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 3129 } ARMMMUIdx; 3130 3131 /* 3132 * Bit macros for the core-mmu-index values for each index, 3133 * for use when calling tlb_flush_by_mmuidx() and friends. 3134 */ 3135 #define TO_CORE_BIT(NAME) \ 3136 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 3137 3138 typedef enum ARMMMUIdxBit { 3139 TO_CORE_BIT(E10_0), 3140 TO_CORE_BIT(E20_0), 3141 TO_CORE_BIT(E10_1), 3142 TO_CORE_BIT(E10_1_PAN), 3143 TO_CORE_BIT(E2), 3144 TO_CORE_BIT(E20_2), 3145 TO_CORE_BIT(E20_2_PAN), 3146 TO_CORE_BIT(SE10_0), 3147 TO_CORE_BIT(SE20_0), 3148 TO_CORE_BIT(SE10_1), 3149 TO_CORE_BIT(SE20_2), 3150 TO_CORE_BIT(SE10_1_PAN), 3151 TO_CORE_BIT(SE20_2_PAN), 3152 TO_CORE_BIT(SE2), 3153 TO_CORE_BIT(SE3), 3154 3155 TO_CORE_BIT(MUser), 3156 TO_CORE_BIT(MPriv), 3157 TO_CORE_BIT(MUserNegPri), 3158 TO_CORE_BIT(MPrivNegPri), 3159 TO_CORE_BIT(MSUser), 3160 TO_CORE_BIT(MSPriv), 3161 TO_CORE_BIT(MSUserNegPri), 3162 TO_CORE_BIT(MSPrivNegPri), 3163 } ARMMMUIdxBit; 3164 3165 #undef TO_CORE_BIT 3166 3167 #define MMU_USER_IDX 0 3168 3169 /* Indexes used when registering address spaces with cpu_address_space_init */ 3170 typedef enum ARMASIdx { 3171 ARMASIdx_NS = 0, 3172 ARMASIdx_S = 1, 3173 ARMASIdx_TagNS = 2, 3174 ARMASIdx_TagS = 3, 3175 } ARMASIdx; 3176 3177 /* Return the Exception Level targeted by debug exceptions. */ 3178 static inline int arm_debug_target_el(CPUARMState *env) 3179 { 3180 bool secure = arm_is_secure(env); 3181 bool route_to_el2 = false; 3182 3183 if (arm_is_el2_enabled(env)) { 3184 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 3185 env->cp15.mdcr_el2 & MDCR_TDE; 3186 } 3187 3188 if (route_to_el2) { 3189 return 2; 3190 } else if (arm_feature(env, ARM_FEATURE_EL3) && 3191 !arm_el_is_aa64(env, 3) && secure) { 3192 return 3; 3193 } else { 3194 return 1; 3195 } 3196 } 3197 3198 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3199 { 3200 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3201 * CSSELR is RAZ/WI. 3202 */ 3203 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3204 } 3205 3206 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 3207 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 3208 { 3209 int cur_el = arm_current_el(env); 3210 int debug_el; 3211 3212 if (cur_el == 3) { 3213 return false; 3214 } 3215 3216 /* MDCR_EL3.SDD disables debug events from Secure state */ 3217 if (arm_is_secure_below_el3(env) 3218 && extract32(env->cp15.mdcr_el3, 16, 1)) { 3219 return false; 3220 } 3221 3222 /* 3223 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 3224 * while not masking the (D)ebug bit in DAIF. 3225 */ 3226 debug_el = arm_debug_target_el(env); 3227 3228 if (cur_el == debug_el) { 3229 return extract32(env->cp15.mdscr_el1, 13, 1) 3230 && !(env->daif & PSTATE_D); 3231 } 3232 3233 /* Otherwise the debug target needs to be a higher EL */ 3234 return debug_el > cur_el; 3235 } 3236 3237 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 3238 { 3239 int el = arm_current_el(env); 3240 3241 if (el == 0 && arm_el_is_aa64(env, 1)) { 3242 return aa64_generate_debug_exceptions(env); 3243 } 3244 3245 if (arm_is_secure(env)) { 3246 int spd; 3247 3248 if (el == 0 && (env->cp15.sder & 1)) { 3249 /* SDER.SUIDEN means debug exceptions from Secure EL0 3250 * are always enabled. Otherwise they are controlled by 3251 * SDCR.SPD like those from other Secure ELs. 3252 */ 3253 return true; 3254 } 3255 3256 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3257 switch (spd) { 3258 case 1: 3259 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3260 case 0: 3261 /* For 0b00 we return true if external secure invasive debug 3262 * is enabled. On real hardware this is controlled by external 3263 * signals to the core. QEMU always permits debug, and behaves 3264 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3265 */ 3266 return true; 3267 case 2: 3268 return false; 3269 case 3: 3270 return true; 3271 } 3272 } 3273 3274 return el != 2; 3275 } 3276 3277 /* Return true if debugging exceptions are currently enabled. 3278 * This corresponds to what in ARM ARM pseudocode would be 3279 * if UsingAArch32() then 3280 * return AArch32.GenerateDebugExceptions() 3281 * else 3282 * return AArch64.GenerateDebugExceptions() 3283 * We choose to push the if() down into this function for clarity, 3284 * since the pseudocode has it at all callsites except for the one in 3285 * CheckSoftwareStep(), where it is elided because both branches would 3286 * always return the same value. 3287 */ 3288 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3289 { 3290 if (env->aarch64) { 3291 return aa64_generate_debug_exceptions(env); 3292 } else { 3293 return aa32_generate_debug_exceptions(env); 3294 } 3295 } 3296 3297 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3298 * implicitly means this always returns false in pre-v8 CPUs.) 3299 */ 3300 static inline bool arm_singlestep_active(CPUARMState *env) 3301 { 3302 return extract32(env->cp15.mdscr_el1, 0, 1) 3303 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3304 && arm_generate_debug_exceptions(env); 3305 } 3306 3307 static inline bool arm_sctlr_b(CPUARMState *env) 3308 { 3309 return 3310 /* We need not implement SCTLR.ITD in user-mode emulation, so 3311 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3312 * This lets people run BE32 binaries with "-cpu any". 3313 */ 3314 #ifndef CONFIG_USER_ONLY 3315 !arm_feature(env, ARM_FEATURE_V7) && 3316 #endif 3317 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3318 } 3319 3320 uint64_t arm_sctlr(CPUARMState *env, int el); 3321 3322 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3323 bool sctlr_b) 3324 { 3325 #ifdef CONFIG_USER_ONLY 3326 /* 3327 * In system mode, BE32 is modelled in line with the 3328 * architecture (as word-invariant big-endianness), where loads 3329 * and stores are done little endian but from addresses which 3330 * are adjusted by XORing with the appropriate constant. So the 3331 * endianness to use for the raw data access is not affected by 3332 * SCTLR.B. 3333 * In user mode, however, we model BE32 as byte-invariant 3334 * big-endianness (because user-only code cannot tell the 3335 * difference), and so we need to use a data access endianness 3336 * that depends on SCTLR.B. 3337 */ 3338 if (sctlr_b) { 3339 return true; 3340 } 3341 #endif 3342 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3343 return env->uncached_cpsr & CPSR_E; 3344 } 3345 3346 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3347 { 3348 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3349 } 3350 3351 /* Return true if the processor is in big-endian mode. */ 3352 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3353 { 3354 if (!is_a64(env)) { 3355 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3356 } else { 3357 int cur_el = arm_current_el(env); 3358 uint64_t sctlr = arm_sctlr(env, cur_el); 3359 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3360 } 3361 } 3362 3363 typedef CPUARMState CPUArchState; 3364 typedef ARMCPU ArchCPU; 3365 3366 #include "exec/cpu-all.h" 3367 3368 /* 3369 * Bit usage in the TB flags field: bit 31 indicates whether we are 3370 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 3371 * We put flags which are shared between 32 and 64 bit mode at the top 3372 * of the word, and flags which apply to only one mode at the bottom. 3373 * 3374 * 31 20 18 14 9 0 3375 * +--------------+-----+-----+----------+--------------+ 3376 * | | | TBFLAG_A32 | | 3377 * | | +-----+----------+ TBFLAG_AM32 | 3378 * | TBFLAG_ANY | |TBFLAG_M32| | 3379 * | +-----------+----------+--------------| 3380 * | | TBFLAG_A64 | 3381 * +--------------+-------------------------------------+ 3382 * 31 20 0 3383 * 3384 * Unless otherwise noted, these bits are cached in env->hflags. 3385 */ 3386 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3387 FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) 3388 FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */ 3389 FIELD(TBFLAG_ANY, BE_DATA, 28, 1) 3390 FIELD(TBFLAG_ANY, MMUIDX, 24, 4) 3391 /* Target EL if we take a floating-point-disabled exception */ 3392 FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2) 3393 /* For A-profile only, target EL for debug exceptions. */ 3394 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) 3395 3396 /* 3397 * Bit usage when in AArch32 state, both A- and M-profile. 3398 */ 3399 FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */ 3400 FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */ 3401 3402 /* 3403 * Bit usage when in AArch32 state, for A-profile only. 3404 */ 3405 FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */ 3406 FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ 3407 /* 3408 * We store the bottom two bits of the CPAR as TB flags and handle 3409 * checks on the other bits at runtime. This shares the same bits as 3410 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3411 * Not cached, because VECLEN+VECSTRIDE are not cached. 3412 */ 3413 FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) 3414 FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */ 3415 FIELD(TBFLAG_A32, SCTLR_B, 15, 1) 3416 FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) 3417 /* 3418 * Indicates whether cp register reads and writes by guest code should access 3419 * the secure or nonsecure bank of banked registers; note that this is not 3420 * the same thing as the current security state of the processor! 3421 */ 3422 FIELD(TBFLAG_A32, NS, 17, 1) 3423 3424 /* 3425 * Bit usage when in AArch32 state, for M-profile only. 3426 */ 3427 /* Handler (ie not Thread) mode */ 3428 FIELD(TBFLAG_M32, HANDLER, 9, 1) 3429 /* Whether we should generate stack-limit checks */ 3430 FIELD(TBFLAG_M32, STACKCHECK, 10, 1) 3431 /* Set if FPCCR.LSPACT is set */ 3432 FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */ 3433 /* Set if we must create a new FP context */ 3434 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */ 3435 /* Set if FPCCR.S does not match current security state */ 3436 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */ 3437 3438 /* 3439 * Bit usage when in AArch64 state 3440 */ 3441 FIELD(TBFLAG_A64, TBII, 0, 2) 3442 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3443 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3444 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3445 FIELD(TBFLAG_A64, BT, 9, 1) 3446 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3447 FIELD(TBFLAG_A64, TBID, 12, 2) 3448 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3449 FIELD(TBFLAG_A64, ATA, 15, 1) 3450 FIELD(TBFLAG_A64, TCMA, 16, 2) 3451 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3452 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3453 3454 /** 3455 * cpu_mmu_index: 3456 * @env: The cpu environment 3457 * @ifetch: True for code access, false for data access. 3458 * 3459 * Return the core mmu index for the current translation regime. 3460 * This function is used by generic TCG code paths. 3461 */ 3462 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3463 { 3464 return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX); 3465 } 3466 3467 static inline bool bswap_code(bool sctlr_b) 3468 { 3469 #ifdef CONFIG_USER_ONLY 3470 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3471 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3472 * would also end up as a mixed-endian mode with BE code, LE data. 3473 */ 3474 return 3475 #ifdef TARGET_WORDS_BIGENDIAN 3476 1 ^ 3477 #endif 3478 sctlr_b; 3479 #else 3480 /* All code access in ARM is little endian, and there are no loaders 3481 * doing swaps that need to be reversed 3482 */ 3483 return 0; 3484 #endif 3485 } 3486 3487 #ifdef CONFIG_USER_ONLY 3488 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3489 { 3490 return 3491 #ifdef TARGET_WORDS_BIGENDIAN 3492 1 ^ 3493 #endif 3494 arm_cpu_data_is_big_endian(env); 3495 } 3496 #endif 3497 3498 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3499 target_ulong *cs_base, uint32_t *flags); 3500 3501 enum { 3502 QEMU_PSCI_CONDUIT_DISABLED = 0, 3503 QEMU_PSCI_CONDUIT_SMC = 1, 3504 QEMU_PSCI_CONDUIT_HVC = 2, 3505 }; 3506 3507 #ifndef CONFIG_USER_ONLY 3508 /* Return the address space index to use for a memory access */ 3509 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3510 { 3511 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3512 } 3513 3514 /* Return the AddressSpace to use for a memory access 3515 * (which depends on whether the access is S or NS, and whether 3516 * the board gave us a separate AddressSpace for S accesses). 3517 */ 3518 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3519 { 3520 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3521 } 3522 #endif 3523 3524 /** 3525 * arm_register_pre_el_change_hook: 3526 * Register a hook function which will be called immediately before this 3527 * CPU changes exception level or mode. The hook function will be 3528 * passed a pointer to the ARMCPU and the opaque data pointer passed 3529 * to this function when the hook was registered. 3530 * 3531 * Note that if a pre-change hook is called, any registered post-change hooks 3532 * are guaranteed to subsequently be called. 3533 */ 3534 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3535 void *opaque); 3536 /** 3537 * arm_register_el_change_hook: 3538 * Register a hook function which will be called immediately after this 3539 * CPU changes exception level or mode. The hook function will be 3540 * passed a pointer to the ARMCPU and the opaque data pointer passed 3541 * to this function when the hook was registered. 3542 * 3543 * Note that any registered hooks registered here are guaranteed to be called 3544 * if pre-change hooks have been. 3545 */ 3546 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3547 *opaque); 3548 3549 /** 3550 * arm_rebuild_hflags: 3551 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3552 */ 3553 void arm_rebuild_hflags(CPUARMState *env); 3554 3555 /** 3556 * aa32_vfp_dreg: 3557 * Return a pointer to the Dn register within env in 32-bit mode. 3558 */ 3559 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3560 { 3561 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3562 } 3563 3564 /** 3565 * aa32_vfp_qreg: 3566 * Return a pointer to the Qn register within env in 32-bit mode. 3567 */ 3568 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3569 { 3570 return &env->vfp.zregs[regno].d[0]; 3571 } 3572 3573 /** 3574 * aa64_vfp_qreg: 3575 * Return a pointer to the Qn register within env in 64-bit mode. 3576 */ 3577 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3578 { 3579 return &env->vfp.zregs[regno].d[0]; 3580 } 3581 3582 /* Shared between translate-sve.c and sve_helper.c. */ 3583 extern const uint64_t pred_esz_masks[4]; 3584 3585 /* Helper for the macros below, validating the argument type. */ 3586 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) 3587 { 3588 return x; 3589 } 3590 3591 /* 3592 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. 3593 * Using these should be a bit more self-documenting than using the 3594 * generic target bits directly. 3595 */ 3596 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) 3597 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) 3598 3599 /* 3600 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3601 */ 3602 #define PAGE_BTI PAGE_TARGET_1 3603 3604 /* 3605 * Naming convention for isar_feature functions: 3606 * Functions which test 32-bit ID registers should have _aa32_ in 3607 * their name. Functions which test 64-bit ID registers should have 3608 * _aa64_ in their name. These must only be used in code where we 3609 * know for certain that the CPU has AArch32 or AArch64 respectively 3610 * or where the correct answer for a CPU which doesn't implement that 3611 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3612 * system registers that are specific to that CPU state, for "should 3613 * we let this system register bit be set" tests where the 32-bit 3614 * flavour of the register doesn't have the bit, and so on). 3615 * Functions which simply ask "does this feature exist at all" have 3616 * _any_ in their name, and always return the logical OR of the _aa64_ 3617 * and the _aa32_ function. 3618 */ 3619 3620 /* 3621 * 32-bit feature tests via id registers. 3622 */ 3623 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3624 { 3625 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3626 } 3627 3628 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3629 { 3630 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3631 } 3632 3633 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3634 { 3635 /* (M-profile) low-overhead loops and branch future */ 3636 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3637 } 3638 3639 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3640 { 3641 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3642 } 3643 3644 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3645 { 3646 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3647 } 3648 3649 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3650 { 3651 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3652 } 3653 3654 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3655 { 3656 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3657 } 3658 3659 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3660 { 3661 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3662 } 3663 3664 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3665 { 3666 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3667 } 3668 3669 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3670 { 3671 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3672 } 3673 3674 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3675 { 3676 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3677 } 3678 3679 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3680 { 3681 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3682 } 3683 3684 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3685 { 3686 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3687 } 3688 3689 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3690 { 3691 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3692 } 3693 3694 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3695 { 3696 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3697 } 3698 3699 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3700 { 3701 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3702 } 3703 3704 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3705 { 3706 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3707 } 3708 3709 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3710 { 3711 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3712 } 3713 3714 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3715 { 3716 /* 3717 * Return true if M-profile state handling insns 3718 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3719 */ 3720 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3721 } 3722 3723 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3724 { 3725 /* Sadly this is encoded differently for A-profile and M-profile */ 3726 if (isar_feature_aa32_mprofile(id)) { 3727 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3728 } else { 3729 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3730 } 3731 } 3732 3733 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3734 { 3735 /* 3736 * Return true if either VFP or SIMD is implemented. 3737 * In this case, a minimum of VFP w/ D0-D15. 3738 */ 3739 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3740 } 3741 3742 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3743 { 3744 /* Return true if D16-D31 are implemented */ 3745 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3746 } 3747 3748 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3749 { 3750 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3751 } 3752 3753 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3754 { 3755 /* Return true if CPU supports single precision floating point, VFPv2 */ 3756 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3757 } 3758 3759 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3760 { 3761 /* Return true if CPU supports single precision floating point, VFPv3 */ 3762 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3763 } 3764 3765 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3766 { 3767 /* Return true if CPU supports double precision floating point, VFPv2 */ 3768 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3769 } 3770 3771 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3772 { 3773 /* Return true if CPU supports double precision floating point, VFPv3 */ 3774 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3775 } 3776 3777 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3778 { 3779 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3780 } 3781 3782 /* 3783 * We always set the FP and SIMD FP16 fields to indicate identical 3784 * levels of support (assuming SIMD is implemented at all), so 3785 * we only need one set of accessors. 3786 */ 3787 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3788 { 3789 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3790 } 3791 3792 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3793 { 3794 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3795 } 3796 3797 /* 3798 * Note that this ID register field covers both VFP and Neon FMAC, 3799 * so should usually be tested in combination with some other 3800 * check that confirms the presence of whichever of VFP or Neon is 3801 * relevant, to avoid accidentally enabling a Neon feature on 3802 * a VFP-no-Neon core or vice-versa. 3803 */ 3804 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3805 { 3806 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3807 } 3808 3809 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3810 { 3811 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3812 } 3813 3814 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3815 { 3816 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3817 } 3818 3819 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3820 { 3821 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3822 } 3823 3824 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3825 { 3826 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3827 } 3828 3829 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3830 { 3831 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3832 } 3833 3834 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3835 { 3836 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3837 } 3838 3839 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3840 { 3841 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3842 } 3843 3844 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3845 { 3846 /* 0xf means "non-standard IMPDEF PMU" */ 3847 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3848 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3849 } 3850 3851 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3852 { 3853 /* 0xf means "non-standard IMPDEF PMU" */ 3854 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3855 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3856 } 3857 3858 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3859 { 3860 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3861 } 3862 3863 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3864 { 3865 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3866 } 3867 3868 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3869 { 3870 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3871 } 3872 3873 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3874 { 3875 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3876 } 3877 3878 /* 3879 * 64-bit feature tests via id registers. 3880 */ 3881 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3882 { 3883 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3884 } 3885 3886 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3887 { 3888 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3889 } 3890 3891 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3892 { 3893 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3894 } 3895 3896 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3897 { 3898 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3899 } 3900 3901 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3902 { 3903 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3904 } 3905 3906 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3907 { 3908 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3909 } 3910 3911 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3912 { 3913 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3914 } 3915 3916 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3917 { 3918 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3919 } 3920 3921 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3922 { 3923 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3924 } 3925 3926 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3927 { 3928 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3929 } 3930 3931 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3932 { 3933 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3934 } 3935 3936 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3937 { 3938 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3939 } 3940 3941 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3942 { 3943 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3944 } 3945 3946 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3947 { 3948 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3949 } 3950 3951 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3952 { 3953 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3954 } 3955 3956 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3957 { 3958 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3959 } 3960 3961 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3962 { 3963 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3964 } 3965 3966 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3967 { 3968 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3969 } 3970 3971 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3972 { 3973 /* 3974 * Return true if any form of pauth is enabled, as this 3975 * predicate controls migration of the 128-bit keys. 3976 */ 3977 return (id->id_aa64isar1 & 3978 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3979 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3980 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3981 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3982 } 3983 3984 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3985 { 3986 /* 3987 * Return true if pauth is enabled with the architected QARMA algorithm. 3988 * QEMU will always set APA+GPA to the same value. 3989 */ 3990 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3991 } 3992 3993 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3994 { 3995 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3996 } 3997 3998 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3999 { 4000 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 4001 } 4002 4003 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 4004 { 4005 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 4006 } 4007 4008 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 4009 { 4010 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 4011 } 4012 4013 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 4014 { 4015 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 4016 } 4017 4018 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 4019 { 4020 /* We always set the AdvSIMD and FP fields identically. */ 4021 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 4022 } 4023 4024 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 4025 { 4026 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 4027 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 4028 } 4029 4030 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 4031 { 4032 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 4033 } 4034 4035 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 4036 { 4037 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 4038 } 4039 4040 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 4041 { 4042 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 4043 } 4044 4045 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 4046 { 4047 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 4048 } 4049 4050 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 4051 { 4052 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 4053 } 4054 4055 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 4056 { 4057 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 4058 } 4059 4060 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 4061 { 4062 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 4063 } 4064 4065 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 4066 { 4067 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 4068 } 4069 4070 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 4071 { 4072 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 4073 } 4074 4075 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 4076 { 4077 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 4078 } 4079 4080 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 4081 { 4082 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 4083 } 4084 4085 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 4086 { 4087 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 4088 } 4089 4090 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 4091 { 4092 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 4093 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4094 } 4095 4096 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 4097 { 4098 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 4099 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4100 } 4101 4102 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 4103 { 4104 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 4105 } 4106 4107 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 4108 { 4109 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 4110 } 4111 4112 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4113 { 4114 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4115 } 4116 4117 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4118 { 4119 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4120 } 4121 4122 /* 4123 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4124 */ 4125 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4126 { 4127 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4128 } 4129 4130 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4131 { 4132 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4133 } 4134 4135 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 4136 { 4137 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 4138 } 4139 4140 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 4141 { 4142 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 4143 } 4144 4145 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4146 { 4147 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4148 } 4149 4150 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4151 { 4152 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4153 } 4154 4155 /* 4156 * Forward to the above feature tests given an ARMCPU pointer. 4157 */ 4158 #define cpu_isar_feature(name, cpu) \ 4159 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4160 4161 #endif 4162