1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #define EXCP_UDEF 1 /* undefined instruction */ 43 #define EXCP_SWI 2 /* software interrupt */ 44 #define EXCP_PREFETCH_ABORT 3 45 #define EXCP_DATA_ABORT 4 46 #define EXCP_IRQ 5 47 #define EXCP_FIQ 6 48 #define EXCP_BKPT 7 49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 51 #define EXCP_HVC 11 /* HyperVisor Call */ 52 #define EXCP_HYP_TRAP 12 53 #define EXCP_SMC 13 /* Secure Monitor Call */ 54 #define EXCP_VIRQ 14 55 #define EXCP_VFIQ 15 56 #define EXCP_SEMIHOST 16 /* semihosting call */ 57 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 58 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 59 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 94 /* The usual mapping for an AArch64 system register to its AArch32 95 * counterpart is for the 32 bit world to have access to the lower 96 * half only (with writes leaving the upper half untouched). It's 97 * therefore useful to be able to pass TCG the offset of the least 98 * significant half of a uint64_t struct member. 99 */ 100 #ifdef HOST_WORDS_BIGENDIAN 101 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 102 #define offsetofhigh32(S, M) offsetof(S, M) 103 #else 104 #define offsetoflow32(S, M) offsetof(S, M) 105 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 106 #endif 107 108 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 109 #define ARM_CPU_IRQ 0 110 #define ARM_CPU_FIQ 1 111 #define ARM_CPU_VIRQ 2 112 #define ARM_CPU_VFIQ 3 113 114 #define NB_MMU_MODES 8 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num_cpregs: Number of the Coprocessor registers seen by GDB. 141 * @cpregs_keys: Array that contains the corresponding Key of 142 * a given cpreg with the same order of the cpreg in the XML description. 143 */ 144 typedef struct DynamicGDBXMLInfo { 145 char *desc; 146 int num_cpregs; 147 uint32_t *cpregs_keys; 148 } DynamicGDBXMLInfo; 149 150 /* CPU state for each instance of a generic timer (in cp15 c14) */ 151 typedef struct ARMGenericTimer { 152 uint64_t cval; /* Timer CompareValue register */ 153 uint64_t ctl; /* Timer Control register */ 154 } ARMGenericTimer; 155 156 #define GTIMER_PHYS 0 157 #define GTIMER_VIRT 1 158 #define GTIMER_HYP 2 159 #define GTIMER_SEC 3 160 #define NUM_GTIMERS 4 161 162 typedef struct { 163 uint64_t raw_tcr; 164 uint32_t mask; 165 uint32_t base_mask; 166 } TCR; 167 168 /* Define a maximum sized vector register. 169 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 170 * For 64-bit, this is a 2048-bit SVE register. 171 * 172 * Note that the mapping between S, D, and Q views of the register bank 173 * differs between AArch64 and AArch32. 174 * In AArch32: 175 * Qn = regs[n].d[1]:regs[n].d[0] 176 * Dn = regs[n / 2].d[n & 1] 177 * Sn = regs[n / 4].d[n % 4 / 2], 178 * bits 31..0 for even n, and bits 63..32 for odd n 179 * (and regs[16] to regs[31] are inaccessible) 180 * In AArch64: 181 * Zn = regs[n].d[*] 182 * Qn = regs[n].d[1]:regs[n].d[0] 183 * Dn = regs[n].d[0] 184 * Sn = regs[n].d[0] bits 31..0 185 * Hn = regs[n].d[0] bits 15..0 186 * 187 * This corresponds to the architecturally defined mapping between 188 * the two execution states, and means we do not need to explicitly 189 * map these registers when changing states. 190 * 191 * Align the data for use with TCG host vector operations. 192 */ 193 194 #ifdef TARGET_AARCH64 195 # define ARM_MAX_VQ 16 196 #else 197 # define ARM_MAX_VQ 1 198 #endif 199 200 typedef struct ARMVectorReg { 201 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 202 } ARMVectorReg; 203 204 #ifdef TARGET_AARCH64 205 /* In AArch32 mode, predicate registers do not exist at all. */ 206 typedef struct ARMPredicateReg { 207 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); 208 } ARMPredicateReg; 209 210 /* In AArch32 mode, PAC keys do not exist at all. */ 211 typedef struct ARMPACKey { 212 uint64_t lo, hi; 213 } ARMPACKey; 214 #endif 215 216 217 typedef struct CPUARMState { 218 /* Regs for current mode. */ 219 uint32_t regs[16]; 220 221 /* 32/64 switch only happens when taking and returning from 222 * exceptions so the overlap semantics are taken care of then 223 * instead of having a complicated union. 224 */ 225 /* Regs for A64 mode. */ 226 uint64_t xregs[32]; 227 uint64_t pc; 228 /* PSTATE isn't an architectural register for ARMv8. However, it is 229 * convenient for us to assemble the underlying state into a 32 bit format 230 * identical to the architectural format used for the SPSR. (This is also 231 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 232 * 'pstate' register are.) Of the PSTATE bits: 233 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 234 * semantics as for AArch32, as described in the comments on each field) 235 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 236 * DAIF (exception masks) are kept in env->daif 237 * BTYPE is kept in env->btype 238 * all other bits are stored in their correct places in env->pstate 239 */ 240 uint32_t pstate; 241 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 242 243 /* Frequently accessed CPSR bits are stored separately for efficiency. 244 This contains all the other bits. Use cpsr_{read,write} to access 245 the whole CPSR. */ 246 uint32_t uncached_cpsr; 247 uint32_t spsr; 248 249 /* Banked registers. */ 250 uint64_t banked_spsr[8]; 251 uint32_t banked_r13[8]; 252 uint32_t banked_r14[8]; 253 254 /* These hold r8-r12. */ 255 uint32_t usr_regs[5]; 256 uint32_t fiq_regs[5]; 257 258 /* cpsr flag cache for faster execution */ 259 uint32_t CF; /* 0 or 1 */ 260 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 261 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 262 uint32_t ZF; /* Z set if zero. */ 263 uint32_t QF; /* 0 or 1 */ 264 uint32_t GE; /* cpsr[19:16] */ 265 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 266 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 267 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 268 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 269 270 uint64_t elr_el[4]; /* AArch64 exception link regs */ 271 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 272 273 /* System control coprocessor (cp15) */ 274 struct { 275 uint32_t c0_cpuid; 276 union { /* Cache size selection */ 277 struct { 278 uint64_t _unused_csselr0; 279 uint64_t csselr_ns; 280 uint64_t _unused_csselr1; 281 uint64_t csselr_s; 282 }; 283 uint64_t csselr_el[4]; 284 }; 285 union { /* System control register. */ 286 struct { 287 uint64_t _unused_sctlr; 288 uint64_t sctlr_ns; 289 uint64_t hsctlr; 290 uint64_t sctlr_s; 291 }; 292 uint64_t sctlr_el[4]; 293 }; 294 uint64_t cpacr_el1; /* Architectural feature access control register */ 295 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 296 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 297 uint64_t sder; /* Secure debug enable register. */ 298 uint32_t nsacr; /* Non-secure access control register. */ 299 union { /* MMU translation table base 0. */ 300 struct { 301 uint64_t _unused_ttbr0_0; 302 uint64_t ttbr0_ns; 303 uint64_t _unused_ttbr0_1; 304 uint64_t ttbr0_s; 305 }; 306 uint64_t ttbr0_el[4]; 307 }; 308 union { /* MMU translation table base 1. */ 309 struct { 310 uint64_t _unused_ttbr1_0; 311 uint64_t ttbr1_ns; 312 uint64_t _unused_ttbr1_1; 313 uint64_t ttbr1_s; 314 }; 315 uint64_t ttbr1_el[4]; 316 }; 317 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 318 /* MMU translation table base control. */ 319 TCR tcr_el[4]; 320 TCR vtcr_el2; /* Virtualization Translation Control. */ 321 uint32_t c2_data; /* MPU data cacheable bits. */ 322 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 323 union { /* MMU domain access control register 324 * MPU write buffer control. 325 */ 326 struct { 327 uint64_t dacr_ns; 328 uint64_t dacr_s; 329 }; 330 struct { 331 uint64_t dacr32_el2; 332 }; 333 }; 334 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 335 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 336 uint64_t hcr_el2; /* Hypervisor configuration register */ 337 uint64_t scr_el3; /* Secure configuration register. */ 338 union { /* Fault status registers. */ 339 struct { 340 uint64_t ifsr_ns; 341 uint64_t ifsr_s; 342 }; 343 struct { 344 uint64_t ifsr32_el2; 345 }; 346 }; 347 union { 348 struct { 349 uint64_t _unused_dfsr; 350 uint64_t dfsr_ns; 351 uint64_t hsr; 352 uint64_t dfsr_s; 353 }; 354 uint64_t esr_el[4]; 355 }; 356 uint32_t c6_region[8]; /* MPU base/size registers. */ 357 union { /* Fault address registers. */ 358 struct { 359 uint64_t _unused_far0; 360 #ifdef HOST_WORDS_BIGENDIAN 361 uint32_t ifar_ns; 362 uint32_t dfar_ns; 363 uint32_t ifar_s; 364 uint32_t dfar_s; 365 #else 366 uint32_t dfar_ns; 367 uint32_t ifar_ns; 368 uint32_t dfar_s; 369 uint32_t ifar_s; 370 #endif 371 uint64_t _unused_far3; 372 }; 373 uint64_t far_el[4]; 374 }; 375 uint64_t hpfar_el2; 376 uint64_t hstr_el2; 377 union { /* Translation result. */ 378 struct { 379 uint64_t _unused_par_0; 380 uint64_t par_ns; 381 uint64_t _unused_par_1; 382 uint64_t par_s; 383 }; 384 uint64_t par_el[4]; 385 }; 386 387 uint32_t c9_insn; /* Cache lockdown registers. */ 388 uint32_t c9_data; 389 uint64_t c9_pmcr; /* performance monitor control register */ 390 uint64_t c9_pmcnten; /* perf monitor counter enables */ 391 uint64_t c9_pmovsr; /* perf monitor overflow status */ 392 uint64_t c9_pmuserenr; /* perf monitor user enable */ 393 uint64_t c9_pmselr; /* perf monitor counter selection register */ 394 uint64_t c9_pminten; /* perf monitor interrupt enables */ 395 union { /* Memory attribute redirection */ 396 struct { 397 #ifdef HOST_WORDS_BIGENDIAN 398 uint64_t _unused_mair_0; 399 uint32_t mair1_ns; 400 uint32_t mair0_ns; 401 uint64_t _unused_mair_1; 402 uint32_t mair1_s; 403 uint32_t mair0_s; 404 #else 405 uint64_t _unused_mair_0; 406 uint32_t mair0_ns; 407 uint32_t mair1_ns; 408 uint64_t _unused_mair_1; 409 uint32_t mair0_s; 410 uint32_t mair1_s; 411 #endif 412 }; 413 uint64_t mair_el[4]; 414 }; 415 union { /* vector base address register */ 416 struct { 417 uint64_t _unused_vbar; 418 uint64_t vbar_ns; 419 uint64_t hvbar; 420 uint64_t vbar_s; 421 }; 422 uint64_t vbar_el[4]; 423 }; 424 uint32_t mvbar; /* (monitor) vector base address register */ 425 struct { /* FCSE PID. */ 426 uint32_t fcseidr_ns; 427 uint32_t fcseidr_s; 428 }; 429 union { /* Context ID. */ 430 struct { 431 uint64_t _unused_contextidr_0; 432 uint64_t contextidr_ns; 433 uint64_t _unused_contextidr_1; 434 uint64_t contextidr_s; 435 }; 436 uint64_t contextidr_el[4]; 437 }; 438 union { /* User RW Thread register. */ 439 struct { 440 uint64_t tpidrurw_ns; 441 uint64_t tpidrprw_ns; 442 uint64_t htpidr; 443 uint64_t _tpidr_el3; 444 }; 445 uint64_t tpidr_el[4]; 446 }; 447 /* The secure banks of these registers don't map anywhere */ 448 uint64_t tpidrurw_s; 449 uint64_t tpidrprw_s; 450 uint64_t tpidruro_s; 451 452 union { /* User RO Thread register. */ 453 uint64_t tpidruro_ns; 454 uint64_t tpidrro_el[1]; 455 }; 456 uint64_t c14_cntfrq; /* Counter Frequency register */ 457 uint64_t c14_cntkctl; /* Timer Control register */ 458 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 459 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 460 ARMGenericTimer c14_timer[NUM_GTIMERS]; 461 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 462 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 463 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 464 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 465 uint32_t c15_threadid; /* TI debugger thread-ID. */ 466 uint32_t c15_config_base_address; /* SCU base address. */ 467 uint32_t c15_diagnostic; /* diagnostic register */ 468 uint32_t c15_power_diagnostic; 469 uint32_t c15_power_control; /* power control */ 470 uint64_t dbgbvr[16]; /* breakpoint value registers */ 471 uint64_t dbgbcr[16]; /* breakpoint control registers */ 472 uint64_t dbgwvr[16]; /* watchpoint value registers */ 473 uint64_t dbgwcr[16]; /* watchpoint control registers */ 474 uint64_t mdscr_el1; 475 uint64_t oslsr_el1; /* OS Lock Status */ 476 uint64_t mdcr_el2; 477 uint64_t mdcr_el3; 478 /* Stores the architectural value of the counter *the last time it was 479 * updated* by pmccntr_op_start. Accesses should always be surrounded 480 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 481 * architecturally-correct value is being read/set. 482 */ 483 uint64_t c15_ccnt; 484 /* Stores the delta between the architectural value and the underlying 485 * cycle count during normal operation. It is used to update c15_ccnt 486 * to be the correct architectural value before accesses. During 487 * accesses, c15_ccnt_delta contains the underlying count being used 488 * for the access, after which it reverts to the delta value in 489 * pmccntr_op_finish. 490 */ 491 uint64_t c15_ccnt_delta; 492 uint64_t c14_pmevcntr[31]; 493 uint64_t c14_pmevcntr_delta[31]; 494 uint64_t c14_pmevtyper[31]; 495 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 496 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 497 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 498 } cp15; 499 500 struct { 501 /* M profile has up to 4 stack pointers: 502 * a Main Stack Pointer and a Process Stack Pointer for each 503 * of the Secure and Non-Secure states. (If the CPU doesn't support 504 * the security extension then it has only two SPs.) 505 * In QEMU we always store the currently active SP in regs[13], 506 * and the non-active SP for the current security state in 507 * v7m.other_sp. The stack pointers for the inactive security state 508 * are stored in other_ss_msp and other_ss_psp. 509 * switch_v7m_security_state() is responsible for rearranging them 510 * when we change security state. 511 */ 512 uint32_t other_sp; 513 uint32_t other_ss_msp; 514 uint32_t other_ss_psp; 515 uint32_t vecbase[M_REG_NUM_BANKS]; 516 uint32_t basepri[M_REG_NUM_BANKS]; 517 uint32_t control[M_REG_NUM_BANKS]; 518 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 519 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 520 uint32_t hfsr; /* HardFault Status */ 521 uint32_t dfsr; /* Debug Fault Status Register */ 522 uint32_t sfsr; /* Secure Fault Status Register */ 523 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 524 uint32_t bfar; /* BusFault Address */ 525 uint32_t sfar; /* Secure Fault Address Register */ 526 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 527 int exception; 528 uint32_t primask[M_REG_NUM_BANKS]; 529 uint32_t faultmask[M_REG_NUM_BANKS]; 530 uint32_t aircr; /* only holds r/w state if security extn implemented */ 531 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 532 uint32_t csselr[M_REG_NUM_BANKS]; 533 uint32_t scr[M_REG_NUM_BANKS]; 534 uint32_t msplim[M_REG_NUM_BANKS]; 535 uint32_t psplim[M_REG_NUM_BANKS]; 536 uint32_t fpcar[M_REG_NUM_BANKS]; 537 uint32_t fpccr[M_REG_NUM_BANKS]; 538 uint32_t fpdscr[M_REG_NUM_BANKS]; 539 uint32_t cpacr[M_REG_NUM_BANKS]; 540 uint32_t nsacr; 541 } v7m; 542 543 /* Information associated with an exception about to be taken: 544 * code which raises an exception must set cs->exception_index and 545 * the relevant parts of this structure; the cpu_do_interrupt function 546 * will then set the guest-visible registers as part of the exception 547 * entry process. 548 */ 549 struct { 550 uint32_t syndrome; /* AArch64 format syndrome register */ 551 uint32_t fsr; /* AArch32 format fault status register info */ 552 uint64_t vaddress; /* virtual addr associated with exception, if any */ 553 uint32_t target_el; /* EL the exception should be targeted for */ 554 /* If we implement EL2 we will also need to store information 555 * about the intermediate physical address for stage 2 faults. 556 */ 557 } exception; 558 559 /* Information associated with an SError */ 560 struct { 561 uint8_t pending; 562 uint8_t has_esr; 563 uint64_t esr; 564 } serror; 565 566 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 567 uint32_t irq_line_state; 568 569 /* Thumb-2 EE state. */ 570 uint32_t teecr; 571 uint32_t teehbr; 572 573 /* VFP coprocessor state. */ 574 struct { 575 ARMVectorReg zregs[32]; 576 577 #ifdef TARGET_AARCH64 578 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 579 #define FFR_PRED_NUM 16 580 ARMPredicateReg pregs[17]; 581 /* Scratch space for aa64 sve predicate temporary. */ 582 ARMPredicateReg preg_tmp; 583 #endif 584 585 /* We store these fpcsr fields separately for convenience. */ 586 uint32_t qc[4] QEMU_ALIGNED(16); 587 int vec_len; 588 int vec_stride; 589 590 uint32_t xregs[16]; 591 592 /* Scratch space for aa32 neon expansion. */ 593 uint32_t scratch[8]; 594 595 /* There are a number of distinct float control structures: 596 * 597 * fp_status: is the "normal" fp status. 598 * fp_status_fp16: used for half-precision calculations 599 * standard_fp_status : the ARM "Standard FPSCR Value" 600 * 601 * Half-precision operations are governed by a separate 602 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 603 * status structure to control this. 604 * 605 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 606 * round-to-nearest and is used by any operations (generally 607 * Neon) which the architecture defines as controlled by the 608 * standard FPSCR value rather than the FPSCR. 609 * 610 * To avoid having to transfer exception bits around, we simply 611 * say that the FPSCR cumulative exception flags are the logical 612 * OR of the flags in the three fp statuses. This relies on the 613 * only thing which needs to read the exception flags being 614 * an explicit FPSCR read. 615 */ 616 float_status fp_status; 617 float_status fp_status_f16; 618 float_status standard_fp_status; 619 620 /* ZCR_EL[1-3] */ 621 uint64_t zcr_el[4]; 622 } vfp; 623 uint64_t exclusive_addr; 624 uint64_t exclusive_val; 625 uint64_t exclusive_high; 626 627 /* iwMMXt coprocessor state. */ 628 struct { 629 uint64_t regs[16]; 630 uint64_t val; 631 632 uint32_t cregs[16]; 633 } iwmmxt; 634 635 #ifdef TARGET_AARCH64 636 ARMPACKey apia_key; 637 ARMPACKey apib_key; 638 ARMPACKey apda_key; 639 ARMPACKey apdb_key; 640 ARMPACKey apga_key; 641 #endif 642 643 #if defined(CONFIG_USER_ONLY) 644 /* For usermode syscall translation. */ 645 int eabi; 646 #endif 647 648 struct CPUBreakpoint *cpu_breakpoint[16]; 649 struct CPUWatchpoint *cpu_watchpoint[16]; 650 651 /* Fields up to this point are cleared by a CPU reset */ 652 struct {} end_reset_fields; 653 654 CPU_COMMON 655 656 /* Fields after CPU_COMMON are preserved across CPU reset. */ 657 658 /* Internal CPU feature flags. */ 659 uint64_t features; 660 661 /* PMSAv7 MPU */ 662 struct { 663 uint32_t *drbar; 664 uint32_t *drsr; 665 uint32_t *dracr; 666 uint32_t rnr[M_REG_NUM_BANKS]; 667 } pmsav7; 668 669 /* PMSAv8 MPU */ 670 struct { 671 /* The PMSAv8 implementation also shares some PMSAv7 config 672 * and state: 673 * pmsav7.rnr (region number register) 674 * pmsav7_dregion (number of configured regions) 675 */ 676 uint32_t *rbar[M_REG_NUM_BANKS]; 677 uint32_t *rlar[M_REG_NUM_BANKS]; 678 uint32_t mair0[M_REG_NUM_BANKS]; 679 uint32_t mair1[M_REG_NUM_BANKS]; 680 } pmsav8; 681 682 /* v8M SAU */ 683 struct { 684 uint32_t *rbar; 685 uint32_t *rlar; 686 uint32_t rnr; 687 uint32_t ctrl; 688 } sau; 689 690 void *nvic; 691 const struct arm_boot_info *boot_info; 692 /* Store GICv3CPUState to access from this struct */ 693 void *gicv3state; 694 } CPUARMState; 695 696 /** 697 * ARMELChangeHookFn: 698 * type of a function which can be registered via arm_register_el_change_hook() 699 * to get callbacks when the CPU changes its exception level or mode. 700 */ 701 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 702 typedef struct ARMELChangeHook ARMELChangeHook; 703 struct ARMELChangeHook { 704 ARMELChangeHookFn *hook; 705 void *opaque; 706 QLIST_ENTRY(ARMELChangeHook) node; 707 }; 708 709 /* These values map onto the return values for 710 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 711 typedef enum ARMPSCIState { 712 PSCI_ON = 0, 713 PSCI_OFF = 1, 714 PSCI_ON_PENDING = 2 715 } ARMPSCIState; 716 717 typedef struct ARMISARegisters ARMISARegisters; 718 719 /** 720 * ARMCPU: 721 * @env: #CPUARMState 722 * 723 * An ARM CPU core. 724 */ 725 struct ARMCPU { 726 /*< private >*/ 727 CPUState parent_obj; 728 /*< public >*/ 729 730 CPUARMState env; 731 732 /* Coprocessor information */ 733 GHashTable *cp_regs; 734 /* For marshalling (mostly coprocessor) register state between the 735 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 736 * we use these arrays. 737 */ 738 /* List of register indexes managed via these arrays; (full KVM style 739 * 64 bit indexes, not CPRegInfo 32 bit indexes) 740 */ 741 uint64_t *cpreg_indexes; 742 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 743 uint64_t *cpreg_values; 744 /* Length of the indexes, values, reset_values arrays */ 745 int32_t cpreg_array_len; 746 /* These are used only for migration: incoming data arrives in 747 * these fields and is sanity checked in post_load before copying 748 * to the working data structures above. 749 */ 750 uint64_t *cpreg_vmstate_indexes; 751 uint64_t *cpreg_vmstate_values; 752 int32_t cpreg_vmstate_array_len; 753 754 DynamicGDBXMLInfo dyn_xml; 755 756 /* Timers used by the generic (architected) timer */ 757 QEMUTimer *gt_timer[NUM_GTIMERS]; 758 /* 759 * Timer used by the PMU. Its state is restored after migration by 760 * pmu_op_finish() - it does not need other handling during migration 761 */ 762 QEMUTimer *pmu_timer; 763 /* GPIO outputs for generic timer */ 764 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 765 /* GPIO output for GICv3 maintenance interrupt signal */ 766 qemu_irq gicv3_maintenance_interrupt; 767 /* GPIO output for the PMU interrupt */ 768 qemu_irq pmu_interrupt; 769 770 /* MemoryRegion to use for secure physical accesses */ 771 MemoryRegion *secure_memory; 772 773 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 774 Object *idau; 775 776 /* 'compatible' string for this CPU for Linux device trees */ 777 const char *dtb_compatible; 778 779 /* PSCI version for this CPU 780 * Bits[31:16] = Major Version 781 * Bits[15:0] = Minor Version 782 */ 783 uint32_t psci_version; 784 785 /* Should CPU start in PSCI powered-off state? */ 786 bool start_powered_off; 787 788 /* Current power state, access guarded by BQL */ 789 ARMPSCIState power_state; 790 791 /* CPU has virtualization extension */ 792 bool has_el2; 793 /* CPU has security extension */ 794 bool has_el3; 795 /* CPU has PMU (Performance Monitor Unit) */ 796 bool has_pmu; 797 798 /* CPU has memory protection unit */ 799 bool has_mpu; 800 /* PMSAv7 MPU number of supported regions */ 801 uint32_t pmsav7_dregion; 802 /* v8M SAU number of supported regions */ 803 uint32_t sau_sregion; 804 805 /* PSCI conduit used to invoke PSCI methods 806 * 0 - disabled, 1 - smc, 2 - hvc 807 */ 808 uint32_t psci_conduit; 809 810 /* For v8M, initial value of the Secure VTOR */ 811 uint32_t init_svtor; 812 813 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 814 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 815 */ 816 uint32_t kvm_target; 817 818 /* KVM init features for this CPU */ 819 uint32_t kvm_init_features[7]; 820 821 /* Uniprocessor system with MP extensions */ 822 bool mp_is_up; 823 824 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 825 * and the probe failed (so we need to report the error in realize) 826 */ 827 bool host_cpu_probe_failed; 828 829 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 830 * register. 831 */ 832 int32_t core_count; 833 834 /* The instance init functions for implementation-specific subclasses 835 * set these fields to specify the implementation-dependent values of 836 * various constant registers and reset values of non-constant 837 * registers. 838 * Some of these might become QOM properties eventually. 839 * Field names match the official register names as defined in the 840 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 841 * is used for reset values of non-constant registers; no reset_ 842 * prefix means a constant register. 843 * Some of these registers are split out into a substructure that 844 * is shared with the translators to control the ISA. 845 */ 846 struct ARMISARegisters { 847 uint32_t id_isar0; 848 uint32_t id_isar1; 849 uint32_t id_isar2; 850 uint32_t id_isar3; 851 uint32_t id_isar4; 852 uint32_t id_isar5; 853 uint32_t id_isar6; 854 uint32_t mvfr0; 855 uint32_t mvfr1; 856 uint32_t mvfr2; 857 uint64_t id_aa64isar0; 858 uint64_t id_aa64isar1; 859 uint64_t id_aa64pfr0; 860 uint64_t id_aa64pfr1; 861 uint64_t id_aa64mmfr0; 862 uint64_t id_aa64mmfr1; 863 } isar; 864 uint32_t midr; 865 uint32_t revidr; 866 uint32_t reset_fpsid; 867 uint32_t ctr; 868 uint32_t reset_sctlr; 869 uint32_t id_pfr0; 870 uint32_t id_pfr1; 871 uint32_t id_dfr0; 872 uint64_t pmceid0; 873 uint64_t pmceid1; 874 uint32_t id_afr0; 875 uint32_t id_mmfr0; 876 uint32_t id_mmfr1; 877 uint32_t id_mmfr2; 878 uint32_t id_mmfr3; 879 uint32_t id_mmfr4; 880 uint64_t id_aa64dfr0; 881 uint64_t id_aa64dfr1; 882 uint64_t id_aa64afr0; 883 uint64_t id_aa64afr1; 884 uint32_t dbgdidr; 885 uint32_t clidr; 886 uint64_t mp_affinity; /* MP ID without feature bits */ 887 /* The elements of this array are the CCSIDR values for each cache, 888 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 889 */ 890 uint32_t ccsidr[16]; 891 uint64_t reset_cbar; 892 uint32_t reset_auxcr; 893 bool reset_hivecs; 894 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 895 uint32_t dcz_blocksize; 896 uint64_t rvbar; 897 898 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 899 int gic_num_lrs; /* number of list registers */ 900 int gic_vpribits; /* number of virtual priority bits */ 901 int gic_vprebits; /* number of virtual preemption bits */ 902 903 /* Whether the cfgend input is high (i.e. this CPU should reset into 904 * big-endian mode). This setting isn't used directly: instead it modifies 905 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 906 * architecture version. 907 */ 908 bool cfgend; 909 910 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 911 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 912 913 int32_t node_id; /* NUMA node this CPU belongs to */ 914 915 /* Used to synchronize KVM and QEMU in-kernel device levels */ 916 uint8_t device_irq_level; 917 918 /* Used to set the maximum vector length the cpu will support. */ 919 uint32_t sve_max_vq; 920 }; 921 922 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 923 { 924 return container_of(env, ARMCPU, env); 925 } 926 927 void arm_cpu_post_init(Object *obj); 928 929 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 930 931 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 932 933 #define ENV_OFFSET offsetof(ARMCPU, env) 934 935 #ifndef CONFIG_USER_ONLY 936 extern const struct VMStateDescription vmstate_arm_cpu; 937 #endif 938 939 void arm_cpu_do_interrupt(CPUState *cpu); 940 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 941 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 942 943 void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags); 944 945 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 946 MemTxAttrs *attrs); 947 948 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 949 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 950 951 /* Dynamically generates for gdb stub an XML description of the sysregs from 952 * the cp_regs hashtable. Returns the registered sysregs number. 953 */ 954 int arm_gen_dynamic_xml(CPUState *cpu); 955 956 /* Returns the dynamically generated XML for the gdb stub. 957 * Returns a pointer to the XML contents for the specified XML file or NULL 958 * if the XML name doesn't match the predefined one. 959 */ 960 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 961 962 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 963 int cpuid, void *opaque); 964 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 965 int cpuid, void *opaque); 966 967 #ifdef TARGET_AARCH64 968 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 969 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 970 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 971 void aarch64_sve_change_el(CPUARMState *env, int old_el, 972 int new_el, bool el0_a64); 973 #else 974 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 975 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 976 int n, bool a) 977 { } 978 #endif 979 980 target_ulong do_arm_semihosting(CPUARMState *env); 981 void aarch64_sync_32_to_64(CPUARMState *env); 982 void aarch64_sync_64_to_32(CPUARMState *env); 983 984 int fp_exception_el(CPUARMState *env, int cur_el); 985 int sve_exception_el(CPUARMState *env, int cur_el); 986 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 987 988 static inline bool is_a64(CPUARMState *env) 989 { 990 return env->aarch64; 991 } 992 993 /* you can call this signal handler from your SIGBUS and SIGSEGV 994 signal handlers to inform the virtual CPU of exceptions. non zero 995 is returned if the signal was handled by the virtual CPU. */ 996 int cpu_arm_signal_handler(int host_signum, void *pinfo, 997 void *puc); 998 999 /** 1000 * pmu_op_start/finish 1001 * @env: CPUARMState 1002 * 1003 * Convert all PMU counters between their delta form (the typical mode when 1004 * they are enabled) and the guest-visible values. These two calls must 1005 * surround any action which might affect the counters. 1006 */ 1007 void pmu_op_start(CPUARMState *env); 1008 void pmu_op_finish(CPUARMState *env); 1009 1010 /* 1011 * Called when a PMU counter is due to overflow 1012 */ 1013 void arm_pmu_timer_cb(void *opaque); 1014 1015 /** 1016 * Functions to register as EL change hooks for PMU mode filtering 1017 */ 1018 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1019 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1020 1021 /* 1022 * pmu_init 1023 * @cpu: ARMCPU 1024 * 1025 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1026 * for the current configuration 1027 */ 1028 void pmu_init(ARMCPU *cpu); 1029 1030 /* SCTLR bit meanings. Several bits have been reused in newer 1031 * versions of the architecture; in that case we define constants 1032 * for both old and new bit meanings. Code which tests against those 1033 * bits should probably check or otherwise arrange that the CPU 1034 * is the architectural version it expects. 1035 */ 1036 #define SCTLR_M (1U << 0) 1037 #define SCTLR_A (1U << 1) 1038 #define SCTLR_C (1U << 2) 1039 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1040 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1041 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1042 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1043 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1044 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1045 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1046 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1047 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1048 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1049 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1050 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1051 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1052 #define SCTLR_SED (1U << 8) /* v8 onward */ 1053 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1054 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1055 #define SCTLR_F (1U << 10) /* up to v6 */ 1056 #define SCTLR_SW (1U << 10) /* v7 */ 1057 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1058 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1059 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1060 #define SCTLR_I (1U << 12) 1061 #define SCTLR_V (1U << 13) /* AArch32 only */ 1062 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1063 #define SCTLR_RR (1U << 14) /* up to v7 */ 1064 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1065 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1066 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1067 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1068 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1069 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1070 #define SCTLR_BR (1U << 17) /* PMSA only */ 1071 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1072 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1073 #define SCTLR_WXN (1U << 19) 1074 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1075 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1076 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1077 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1078 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1079 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1080 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1081 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1082 #define SCTLR_VE (1U << 24) /* up to v7 */ 1083 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1084 #define SCTLR_EE (1U << 25) 1085 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1086 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1087 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1088 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1089 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1090 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1091 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1092 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1093 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1094 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1095 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1096 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1097 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1098 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1099 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1100 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1101 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1102 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1103 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1104 1105 #define CPTR_TCPAC (1U << 31) 1106 #define CPTR_TTA (1U << 20) 1107 #define CPTR_TFP (1U << 10) 1108 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1109 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1110 1111 #define MDCR_EPMAD (1U << 21) 1112 #define MDCR_EDAD (1U << 20) 1113 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1114 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1115 #define MDCR_SDD (1U << 16) 1116 #define MDCR_SPD (3U << 14) 1117 #define MDCR_TDRA (1U << 11) 1118 #define MDCR_TDOSA (1U << 10) 1119 #define MDCR_TDA (1U << 9) 1120 #define MDCR_TDE (1U << 8) 1121 #define MDCR_HPME (1U << 7) 1122 #define MDCR_TPM (1U << 6) 1123 #define MDCR_TPMCR (1U << 5) 1124 #define MDCR_HPMN (0x1fU) 1125 1126 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1127 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1128 1129 #define CPSR_M (0x1fU) 1130 #define CPSR_T (1U << 5) 1131 #define CPSR_F (1U << 6) 1132 #define CPSR_I (1U << 7) 1133 #define CPSR_A (1U << 8) 1134 #define CPSR_E (1U << 9) 1135 #define CPSR_IT_2_7 (0xfc00U) 1136 #define CPSR_GE (0xfU << 16) 1137 #define CPSR_IL (1U << 20) 1138 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 1139 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 1140 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 1141 * where it is live state but not accessible to the AArch32 code. 1142 */ 1143 #define CPSR_RESERVED (0x7U << 21) 1144 #define CPSR_J (1U << 24) 1145 #define CPSR_IT_0_1 (3U << 25) 1146 #define CPSR_Q (1U << 27) 1147 #define CPSR_V (1U << 28) 1148 #define CPSR_C (1U << 29) 1149 #define CPSR_Z (1U << 30) 1150 #define CPSR_N (1U << 31) 1151 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1152 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1153 1154 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1155 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1156 | CPSR_NZCV) 1157 /* Bits writable in user mode. */ 1158 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1159 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1160 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1161 /* Mask of bits which may be set by exception return copying them from SPSR */ 1162 #define CPSR_ERET_MASK (~CPSR_RESERVED) 1163 1164 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1165 #define XPSR_EXCP 0x1ffU 1166 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1167 #define XPSR_IT_2_7 CPSR_IT_2_7 1168 #define XPSR_GE CPSR_GE 1169 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1170 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1171 #define XPSR_IT_0_1 CPSR_IT_0_1 1172 #define XPSR_Q CPSR_Q 1173 #define XPSR_V CPSR_V 1174 #define XPSR_C CPSR_C 1175 #define XPSR_Z CPSR_Z 1176 #define XPSR_N CPSR_N 1177 #define XPSR_NZCV CPSR_NZCV 1178 #define XPSR_IT CPSR_IT 1179 1180 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1181 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1182 #define TTBCR_PD0 (1U << 4) 1183 #define TTBCR_PD1 (1U << 5) 1184 #define TTBCR_EPD0 (1U << 7) 1185 #define TTBCR_IRGN0 (3U << 8) 1186 #define TTBCR_ORGN0 (3U << 10) 1187 #define TTBCR_SH0 (3U << 12) 1188 #define TTBCR_T1SZ (3U << 16) 1189 #define TTBCR_A1 (1U << 22) 1190 #define TTBCR_EPD1 (1U << 23) 1191 #define TTBCR_IRGN1 (3U << 24) 1192 #define TTBCR_ORGN1 (3U << 26) 1193 #define TTBCR_SH1 (1U << 28) 1194 #define TTBCR_EAE (1U << 31) 1195 1196 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1197 * Only these are valid when in AArch64 mode; in 1198 * AArch32 mode SPSRs are basically CPSR-format. 1199 */ 1200 #define PSTATE_SP (1U) 1201 #define PSTATE_M (0xFU) 1202 #define PSTATE_nRW (1U << 4) 1203 #define PSTATE_F (1U << 6) 1204 #define PSTATE_I (1U << 7) 1205 #define PSTATE_A (1U << 8) 1206 #define PSTATE_D (1U << 9) 1207 #define PSTATE_BTYPE (3U << 10) 1208 #define PSTATE_IL (1U << 20) 1209 #define PSTATE_SS (1U << 21) 1210 #define PSTATE_V (1U << 28) 1211 #define PSTATE_C (1U << 29) 1212 #define PSTATE_Z (1U << 30) 1213 #define PSTATE_N (1U << 31) 1214 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1215 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1216 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1217 /* Mode values for AArch64 */ 1218 #define PSTATE_MODE_EL3h 13 1219 #define PSTATE_MODE_EL3t 12 1220 #define PSTATE_MODE_EL2h 9 1221 #define PSTATE_MODE_EL2t 8 1222 #define PSTATE_MODE_EL1h 5 1223 #define PSTATE_MODE_EL1t 4 1224 #define PSTATE_MODE_EL0t 0 1225 1226 /* Write a new value to v7m.exception, thus transitioning into or out 1227 * of Handler mode; this may result in a change of active stack pointer. 1228 */ 1229 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1230 1231 /* Map EL and handler into a PSTATE_MODE. */ 1232 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1233 { 1234 return (el << 2) | handler; 1235 } 1236 1237 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1238 * interprocessing, so we don't attempt to sync with the cpsr state used by 1239 * the 32 bit decoder. 1240 */ 1241 static inline uint32_t pstate_read(CPUARMState *env) 1242 { 1243 int ZF; 1244 1245 ZF = (env->ZF == 0); 1246 return (env->NF & 0x80000000) | (ZF << 30) 1247 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1248 | env->pstate | env->daif | (env->btype << 10); 1249 } 1250 1251 static inline void pstate_write(CPUARMState *env, uint32_t val) 1252 { 1253 env->ZF = (~val) & PSTATE_Z; 1254 env->NF = val; 1255 env->CF = (val >> 29) & 1; 1256 env->VF = (val << 3) & 0x80000000; 1257 env->daif = val & PSTATE_DAIF; 1258 env->btype = (val >> 10) & 3; 1259 env->pstate = val & ~CACHED_PSTATE_BITS; 1260 } 1261 1262 /* Return the current CPSR value. */ 1263 uint32_t cpsr_read(CPUARMState *env); 1264 1265 typedef enum CPSRWriteType { 1266 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1267 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1268 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1269 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1270 } CPSRWriteType; 1271 1272 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1273 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1274 CPSRWriteType write_type); 1275 1276 /* Return the current xPSR value. */ 1277 static inline uint32_t xpsr_read(CPUARMState *env) 1278 { 1279 int ZF; 1280 ZF = (env->ZF == 0); 1281 return (env->NF & 0x80000000) | (ZF << 30) 1282 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1283 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1284 | ((env->condexec_bits & 0xfc) << 8) 1285 | env->v7m.exception; 1286 } 1287 1288 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1289 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1290 { 1291 if (mask & XPSR_NZCV) { 1292 env->ZF = (~val) & XPSR_Z; 1293 env->NF = val; 1294 env->CF = (val >> 29) & 1; 1295 env->VF = (val << 3) & 0x80000000; 1296 } 1297 if (mask & XPSR_Q) { 1298 env->QF = ((val & XPSR_Q) != 0); 1299 } 1300 if (mask & XPSR_T) { 1301 env->thumb = ((val & XPSR_T) != 0); 1302 } 1303 if (mask & XPSR_IT_0_1) { 1304 env->condexec_bits &= ~3; 1305 env->condexec_bits |= (val >> 25) & 3; 1306 } 1307 if (mask & XPSR_IT_2_7) { 1308 env->condexec_bits &= 3; 1309 env->condexec_bits |= (val >> 8) & 0xfc; 1310 } 1311 if (mask & XPSR_EXCP) { 1312 /* Note that this only happens on exception exit */ 1313 write_v7m_exception(env, val & XPSR_EXCP); 1314 } 1315 } 1316 1317 #define HCR_VM (1ULL << 0) 1318 #define HCR_SWIO (1ULL << 1) 1319 #define HCR_PTW (1ULL << 2) 1320 #define HCR_FMO (1ULL << 3) 1321 #define HCR_IMO (1ULL << 4) 1322 #define HCR_AMO (1ULL << 5) 1323 #define HCR_VF (1ULL << 6) 1324 #define HCR_VI (1ULL << 7) 1325 #define HCR_VSE (1ULL << 8) 1326 #define HCR_FB (1ULL << 9) 1327 #define HCR_BSU_MASK (3ULL << 10) 1328 #define HCR_DC (1ULL << 12) 1329 #define HCR_TWI (1ULL << 13) 1330 #define HCR_TWE (1ULL << 14) 1331 #define HCR_TID0 (1ULL << 15) 1332 #define HCR_TID1 (1ULL << 16) 1333 #define HCR_TID2 (1ULL << 17) 1334 #define HCR_TID3 (1ULL << 18) 1335 #define HCR_TSC (1ULL << 19) 1336 #define HCR_TIDCP (1ULL << 20) 1337 #define HCR_TACR (1ULL << 21) 1338 #define HCR_TSW (1ULL << 22) 1339 #define HCR_TPCP (1ULL << 23) 1340 #define HCR_TPU (1ULL << 24) 1341 #define HCR_TTLB (1ULL << 25) 1342 #define HCR_TVM (1ULL << 26) 1343 #define HCR_TGE (1ULL << 27) 1344 #define HCR_TDZ (1ULL << 28) 1345 #define HCR_HCD (1ULL << 29) 1346 #define HCR_TRVM (1ULL << 30) 1347 #define HCR_RW (1ULL << 31) 1348 #define HCR_CD (1ULL << 32) 1349 #define HCR_ID (1ULL << 33) 1350 #define HCR_E2H (1ULL << 34) 1351 #define HCR_TLOR (1ULL << 35) 1352 #define HCR_TERR (1ULL << 36) 1353 #define HCR_TEA (1ULL << 37) 1354 #define HCR_MIOCNCE (1ULL << 38) 1355 #define HCR_APK (1ULL << 40) 1356 #define HCR_API (1ULL << 41) 1357 #define HCR_NV (1ULL << 42) 1358 #define HCR_NV1 (1ULL << 43) 1359 #define HCR_AT (1ULL << 44) 1360 #define HCR_NV2 (1ULL << 45) 1361 #define HCR_FWB (1ULL << 46) 1362 #define HCR_FIEN (1ULL << 47) 1363 #define HCR_TID4 (1ULL << 49) 1364 #define HCR_TICAB (1ULL << 50) 1365 #define HCR_TOCU (1ULL << 52) 1366 #define HCR_TTLBIS (1ULL << 54) 1367 #define HCR_TTLBOS (1ULL << 55) 1368 #define HCR_ATA (1ULL << 56) 1369 #define HCR_DCT (1ULL << 57) 1370 1371 /* 1372 * When we actually implement ARMv8.1-VHE we should add HCR_E2H to 1373 * HCR_MASK and then clear it again if the feature bit is not set in 1374 * hcr_write(). 1375 */ 1376 #define HCR_MASK ((1ULL << 34) - 1) 1377 1378 #define SCR_NS (1U << 0) 1379 #define SCR_IRQ (1U << 1) 1380 #define SCR_FIQ (1U << 2) 1381 #define SCR_EA (1U << 3) 1382 #define SCR_FW (1U << 4) 1383 #define SCR_AW (1U << 5) 1384 #define SCR_NET (1U << 6) 1385 #define SCR_SMD (1U << 7) 1386 #define SCR_HCE (1U << 8) 1387 #define SCR_SIF (1U << 9) 1388 #define SCR_RW (1U << 10) 1389 #define SCR_ST (1U << 11) 1390 #define SCR_TWI (1U << 12) 1391 #define SCR_TWE (1U << 13) 1392 #define SCR_TLOR (1U << 14) 1393 #define SCR_TERR (1U << 15) 1394 #define SCR_APK (1U << 16) 1395 #define SCR_API (1U << 17) 1396 #define SCR_EEL2 (1U << 18) 1397 #define SCR_EASE (1U << 19) 1398 #define SCR_NMEA (1U << 20) 1399 #define SCR_FIEN (1U << 21) 1400 #define SCR_ENSCXT (1U << 25) 1401 #define SCR_ATA (1U << 26) 1402 1403 /* Return the current FPSCR value. */ 1404 uint32_t vfp_get_fpscr(CPUARMState *env); 1405 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1406 1407 /* FPCR, Floating Point Control Register 1408 * FPSR, Floating Poiht Status Register 1409 * 1410 * For A64 the FPSCR is split into two logically distinct registers, 1411 * FPCR and FPSR. However since they still use non-overlapping bits 1412 * we store the underlying state in fpscr and just mask on read/write. 1413 */ 1414 #define FPSR_MASK 0xf800009f 1415 #define FPCR_MASK 0x07ff9f00 1416 1417 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1418 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1419 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1420 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1421 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1422 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1423 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1424 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1425 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1426 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1427 1428 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1429 { 1430 return vfp_get_fpscr(env) & FPSR_MASK; 1431 } 1432 1433 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1434 { 1435 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1436 vfp_set_fpscr(env, new_fpscr); 1437 } 1438 1439 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1440 { 1441 return vfp_get_fpscr(env) & FPCR_MASK; 1442 } 1443 1444 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1445 { 1446 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1447 vfp_set_fpscr(env, new_fpscr); 1448 } 1449 1450 enum arm_cpu_mode { 1451 ARM_CPU_MODE_USR = 0x10, 1452 ARM_CPU_MODE_FIQ = 0x11, 1453 ARM_CPU_MODE_IRQ = 0x12, 1454 ARM_CPU_MODE_SVC = 0x13, 1455 ARM_CPU_MODE_MON = 0x16, 1456 ARM_CPU_MODE_ABT = 0x17, 1457 ARM_CPU_MODE_HYP = 0x1a, 1458 ARM_CPU_MODE_UND = 0x1b, 1459 ARM_CPU_MODE_SYS = 0x1f 1460 }; 1461 1462 /* VFP system registers. */ 1463 #define ARM_VFP_FPSID 0 1464 #define ARM_VFP_FPSCR 1 1465 #define ARM_VFP_MVFR2 5 1466 #define ARM_VFP_MVFR1 6 1467 #define ARM_VFP_MVFR0 7 1468 #define ARM_VFP_FPEXC 8 1469 #define ARM_VFP_FPINST 9 1470 #define ARM_VFP_FPINST2 10 1471 1472 /* iwMMXt coprocessor control registers. */ 1473 #define ARM_IWMMXT_wCID 0 1474 #define ARM_IWMMXT_wCon 1 1475 #define ARM_IWMMXT_wCSSF 2 1476 #define ARM_IWMMXT_wCASF 3 1477 #define ARM_IWMMXT_wCGR0 8 1478 #define ARM_IWMMXT_wCGR1 9 1479 #define ARM_IWMMXT_wCGR2 10 1480 #define ARM_IWMMXT_wCGR3 11 1481 1482 /* V7M CCR bits */ 1483 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1484 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1485 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1486 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1487 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1488 FIELD(V7M_CCR, STKALIGN, 9, 1) 1489 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1490 FIELD(V7M_CCR, DC, 16, 1) 1491 FIELD(V7M_CCR, IC, 17, 1) 1492 FIELD(V7M_CCR, BP, 18, 1) 1493 1494 /* V7M SCR bits */ 1495 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1496 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1497 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1498 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1499 1500 /* V7M AIRCR bits */ 1501 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1502 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1503 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1504 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1505 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1506 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1507 FIELD(V7M_AIRCR, PRIS, 14, 1) 1508 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1509 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1510 1511 /* V7M CFSR bits for MMFSR */ 1512 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1513 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1514 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1515 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1516 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1517 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1518 1519 /* V7M CFSR bits for BFSR */ 1520 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1521 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1522 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1523 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1524 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1525 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1526 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1527 1528 /* V7M CFSR bits for UFSR */ 1529 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1530 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1531 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1532 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1533 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1534 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1535 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1536 1537 /* V7M CFSR bit masks covering all of the subregister bits */ 1538 FIELD(V7M_CFSR, MMFSR, 0, 8) 1539 FIELD(V7M_CFSR, BFSR, 8, 8) 1540 FIELD(V7M_CFSR, UFSR, 16, 16) 1541 1542 /* V7M HFSR bits */ 1543 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1544 FIELD(V7M_HFSR, FORCED, 30, 1) 1545 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1546 1547 /* V7M DFSR bits */ 1548 FIELD(V7M_DFSR, HALTED, 0, 1) 1549 FIELD(V7M_DFSR, BKPT, 1, 1) 1550 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1551 FIELD(V7M_DFSR, VCATCH, 3, 1) 1552 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1553 1554 /* V7M SFSR bits */ 1555 FIELD(V7M_SFSR, INVEP, 0, 1) 1556 FIELD(V7M_SFSR, INVIS, 1, 1) 1557 FIELD(V7M_SFSR, INVER, 2, 1) 1558 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1559 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1560 FIELD(V7M_SFSR, LSPERR, 5, 1) 1561 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1562 FIELD(V7M_SFSR, LSERR, 7, 1) 1563 1564 /* v7M MPU_CTRL bits */ 1565 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1566 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1567 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1568 1569 /* v7M CLIDR bits */ 1570 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1571 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1572 FIELD(V7M_CLIDR, LOC, 24, 3) 1573 FIELD(V7M_CLIDR, LOUU, 27, 3) 1574 FIELD(V7M_CLIDR, ICB, 30, 2) 1575 1576 FIELD(V7M_CSSELR, IND, 0, 1) 1577 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1578 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1579 * define a mask for this and check that it doesn't permit running off 1580 * the end of the array. 1581 */ 1582 FIELD(V7M_CSSELR, INDEX, 0, 4) 1583 1584 /* v7M FPCCR bits */ 1585 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1586 FIELD(V7M_FPCCR, USER, 1, 1) 1587 FIELD(V7M_FPCCR, S, 2, 1) 1588 FIELD(V7M_FPCCR, THREAD, 3, 1) 1589 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1590 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1591 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1592 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1593 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1594 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1595 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1596 FIELD(V7M_FPCCR, RES0, 11, 15) 1597 FIELD(V7M_FPCCR, TS, 26, 1) 1598 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1599 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1600 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1601 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1602 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1603 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1604 #define R_V7M_FPCCR_BANKED_MASK \ 1605 (R_V7M_FPCCR_LSPACT_MASK | \ 1606 R_V7M_FPCCR_USER_MASK | \ 1607 R_V7M_FPCCR_THREAD_MASK | \ 1608 R_V7M_FPCCR_MMRDY_MASK | \ 1609 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1610 R_V7M_FPCCR_UFRDY_MASK | \ 1611 R_V7M_FPCCR_ASPEN_MASK) 1612 1613 /* 1614 * System register ID fields. 1615 */ 1616 FIELD(ID_ISAR0, SWAP, 0, 4) 1617 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1618 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1619 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1620 FIELD(ID_ISAR0, COPROC, 16, 4) 1621 FIELD(ID_ISAR0, DEBUG, 20, 4) 1622 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1623 1624 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1625 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1626 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1627 FIELD(ID_ISAR1, EXTEND, 12, 4) 1628 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1629 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1630 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1631 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1632 1633 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1634 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1635 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1636 FIELD(ID_ISAR2, MULT, 12, 4) 1637 FIELD(ID_ISAR2, MULTS, 16, 4) 1638 FIELD(ID_ISAR2, MULTU, 20, 4) 1639 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1640 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1641 1642 FIELD(ID_ISAR3, SATURATE, 0, 4) 1643 FIELD(ID_ISAR3, SIMD, 4, 4) 1644 FIELD(ID_ISAR3, SVC, 8, 4) 1645 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1646 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1647 FIELD(ID_ISAR3, T32COPY, 20, 4) 1648 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1649 FIELD(ID_ISAR3, T32EE, 28, 4) 1650 1651 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1652 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1653 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1654 FIELD(ID_ISAR4, SMC, 12, 4) 1655 FIELD(ID_ISAR4, BARRIER, 16, 4) 1656 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1657 FIELD(ID_ISAR4, PSR_M, 24, 4) 1658 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1659 1660 FIELD(ID_ISAR5, SEVL, 0, 4) 1661 FIELD(ID_ISAR5, AES, 4, 4) 1662 FIELD(ID_ISAR5, SHA1, 8, 4) 1663 FIELD(ID_ISAR5, SHA2, 12, 4) 1664 FIELD(ID_ISAR5, CRC32, 16, 4) 1665 FIELD(ID_ISAR5, RDM, 24, 4) 1666 FIELD(ID_ISAR5, VCMA, 28, 4) 1667 1668 FIELD(ID_ISAR6, JSCVT, 0, 4) 1669 FIELD(ID_ISAR6, DP, 4, 4) 1670 FIELD(ID_ISAR6, FHM, 8, 4) 1671 FIELD(ID_ISAR6, SB, 12, 4) 1672 FIELD(ID_ISAR6, SPECRES, 16, 4) 1673 1674 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1675 FIELD(ID_MMFR4, AC2, 4, 4) 1676 FIELD(ID_MMFR4, XNX, 8, 4) 1677 FIELD(ID_MMFR4, CNP, 12, 4) 1678 FIELD(ID_MMFR4, HPDS, 16, 4) 1679 FIELD(ID_MMFR4, LSM, 20, 4) 1680 FIELD(ID_MMFR4, CCIDX, 24, 4) 1681 FIELD(ID_MMFR4, EVT, 28, 4) 1682 1683 FIELD(ID_AA64ISAR0, AES, 4, 4) 1684 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1685 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1686 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1687 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1688 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1689 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1690 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1691 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1692 FIELD(ID_AA64ISAR0, DP, 44, 4) 1693 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1694 FIELD(ID_AA64ISAR0, TS, 52, 4) 1695 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1696 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1697 1698 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1699 FIELD(ID_AA64ISAR1, APA, 4, 4) 1700 FIELD(ID_AA64ISAR1, API, 8, 4) 1701 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1702 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1703 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1704 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1705 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1706 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1707 FIELD(ID_AA64ISAR1, SB, 36, 4) 1708 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1709 1710 FIELD(ID_AA64PFR0, EL0, 0, 4) 1711 FIELD(ID_AA64PFR0, EL1, 4, 4) 1712 FIELD(ID_AA64PFR0, EL2, 8, 4) 1713 FIELD(ID_AA64PFR0, EL3, 12, 4) 1714 FIELD(ID_AA64PFR0, FP, 16, 4) 1715 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1716 FIELD(ID_AA64PFR0, GIC, 24, 4) 1717 FIELD(ID_AA64PFR0, RAS, 28, 4) 1718 FIELD(ID_AA64PFR0, SVE, 32, 4) 1719 1720 FIELD(ID_AA64PFR1, BT, 0, 4) 1721 FIELD(ID_AA64PFR1, SBSS, 4, 4) 1722 FIELD(ID_AA64PFR1, MTE, 8, 4) 1723 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1724 1725 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1726 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1727 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1728 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1729 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1730 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1731 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1732 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1733 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1734 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1735 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1736 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1737 1738 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1739 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1740 FIELD(ID_AA64MMFR1, VH, 8, 4) 1741 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1742 FIELD(ID_AA64MMFR1, LO, 16, 4) 1743 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1744 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1745 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1746 1747 FIELD(ID_DFR0, COPDBG, 0, 4) 1748 FIELD(ID_DFR0, COPSDBG, 4, 4) 1749 FIELD(ID_DFR0, MMAPDBG, 8, 4) 1750 FIELD(ID_DFR0, COPTRC, 12, 4) 1751 FIELD(ID_DFR0, MMAPTRC, 16, 4) 1752 FIELD(ID_DFR0, MPROFDBG, 20, 4) 1753 FIELD(ID_DFR0, PERFMON, 24, 4) 1754 FIELD(ID_DFR0, TRACEFILT, 28, 4) 1755 1756 FIELD(MVFR0, SIMDREG, 0, 4) 1757 FIELD(MVFR0, FPSP, 4, 4) 1758 FIELD(MVFR0, FPDP, 8, 4) 1759 FIELD(MVFR0, FPTRAP, 12, 4) 1760 FIELD(MVFR0, FPDIVIDE, 16, 4) 1761 FIELD(MVFR0, FPSQRT, 20, 4) 1762 FIELD(MVFR0, FPSHVEC, 24, 4) 1763 FIELD(MVFR0, FPROUND, 28, 4) 1764 1765 FIELD(MVFR1, FPFTZ, 0, 4) 1766 FIELD(MVFR1, FPDNAN, 4, 4) 1767 FIELD(MVFR1, SIMDLS, 8, 4) 1768 FIELD(MVFR1, SIMDINT, 12, 4) 1769 FIELD(MVFR1, SIMDSP, 16, 4) 1770 FIELD(MVFR1, SIMDHP, 20, 4) 1771 FIELD(MVFR1, FPHP, 24, 4) 1772 FIELD(MVFR1, SIMDFMAC, 28, 4) 1773 1774 FIELD(MVFR2, SIMDMISC, 0, 4) 1775 FIELD(MVFR2, FPMISC, 4, 4) 1776 1777 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1778 1779 /* If adding a feature bit which corresponds to a Linux ELF 1780 * HWCAP bit, remember to update the feature-bit-to-hwcap 1781 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1782 */ 1783 enum arm_features { 1784 ARM_FEATURE_VFP, 1785 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1786 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1787 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1788 ARM_FEATURE_V6, 1789 ARM_FEATURE_V6K, 1790 ARM_FEATURE_V7, 1791 ARM_FEATURE_THUMB2, 1792 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1793 ARM_FEATURE_VFP3, 1794 ARM_FEATURE_NEON, 1795 ARM_FEATURE_M, /* Microcontroller profile. */ 1796 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1797 ARM_FEATURE_THUMB2EE, 1798 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1799 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1800 ARM_FEATURE_V4T, 1801 ARM_FEATURE_V5, 1802 ARM_FEATURE_STRONGARM, 1803 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1804 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1805 ARM_FEATURE_GENERIC_TIMER, 1806 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1807 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1808 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1809 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1810 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1811 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1812 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1813 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1814 ARM_FEATURE_V8, 1815 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1816 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1817 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1818 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1819 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1820 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1821 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1822 ARM_FEATURE_PMU, /* has PMU support */ 1823 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1824 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1825 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1826 }; 1827 1828 static inline int arm_feature(CPUARMState *env, int feature) 1829 { 1830 return (env->features & (1ULL << feature)) != 0; 1831 } 1832 1833 #if !defined(CONFIG_USER_ONLY) 1834 /* Return true if exception levels below EL3 are in secure state, 1835 * or would be following an exception return to that level. 1836 * Unlike arm_is_secure() (which is always a question about the 1837 * _current_ state of the CPU) this doesn't care about the current 1838 * EL or mode. 1839 */ 1840 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1841 { 1842 if (arm_feature(env, ARM_FEATURE_EL3)) { 1843 return !(env->cp15.scr_el3 & SCR_NS); 1844 } else { 1845 /* If EL3 is not supported then the secure state is implementation 1846 * defined, in which case QEMU defaults to non-secure. 1847 */ 1848 return false; 1849 } 1850 } 1851 1852 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1853 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1854 { 1855 if (arm_feature(env, ARM_FEATURE_EL3)) { 1856 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1857 /* CPU currently in AArch64 state and EL3 */ 1858 return true; 1859 } else if (!is_a64(env) && 1860 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1861 /* CPU currently in AArch32 state and monitor mode */ 1862 return true; 1863 } 1864 } 1865 return false; 1866 } 1867 1868 /* Return true if the processor is in secure state */ 1869 static inline bool arm_is_secure(CPUARMState *env) 1870 { 1871 if (arm_is_el3_or_mon(env)) { 1872 return true; 1873 } 1874 return arm_is_secure_below_el3(env); 1875 } 1876 1877 #else 1878 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1879 { 1880 return false; 1881 } 1882 1883 static inline bool arm_is_secure(CPUARMState *env) 1884 { 1885 return false; 1886 } 1887 #endif 1888 1889 /** 1890 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 1891 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 1892 * "for all purposes other than a direct read or write access of HCR_EL2." 1893 * Not included here is HCR_RW. 1894 */ 1895 uint64_t arm_hcr_el2_eff(CPUARMState *env); 1896 1897 /* Return true if the specified exception level is running in AArch64 state. */ 1898 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1899 { 1900 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1901 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1902 */ 1903 assert(el >= 1 && el <= 3); 1904 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1905 1906 /* The highest exception level is always at the maximum supported 1907 * register width, and then lower levels have a register width controlled 1908 * by bits in the SCR or HCR registers. 1909 */ 1910 if (el == 3) { 1911 return aa64; 1912 } 1913 1914 if (arm_feature(env, ARM_FEATURE_EL3)) { 1915 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1916 } 1917 1918 if (el == 2) { 1919 return aa64; 1920 } 1921 1922 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1923 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1924 } 1925 1926 return aa64; 1927 } 1928 1929 /* Function for determing whether guest cp register reads and writes should 1930 * access the secure or non-secure bank of a cp register. When EL3 is 1931 * operating in AArch32 state, the NS-bit determines whether the secure 1932 * instance of a cp register should be used. When EL3 is AArch64 (or if 1933 * it doesn't exist at all) then there is no register banking, and all 1934 * accesses are to the non-secure version. 1935 */ 1936 static inline bool access_secure_reg(CPUARMState *env) 1937 { 1938 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1939 !arm_el_is_aa64(env, 3) && 1940 !(env->cp15.scr_el3 & SCR_NS)); 1941 1942 return ret; 1943 } 1944 1945 /* Macros for accessing a specified CP register bank */ 1946 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1947 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1948 1949 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1950 do { \ 1951 if (_secure) { \ 1952 (_env)->cp15._regname##_s = (_val); \ 1953 } else { \ 1954 (_env)->cp15._regname##_ns = (_val); \ 1955 } \ 1956 } while (0) 1957 1958 /* Macros for automatically accessing a specific CP register bank depending on 1959 * the current secure state of the system. These macros are not intended for 1960 * supporting instruction translation reads/writes as these are dependent 1961 * solely on the SCR.NS bit and not the mode. 1962 */ 1963 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1964 A32_BANKED_REG_GET((_env), _regname, \ 1965 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1966 1967 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1968 A32_BANKED_REG_SET((_env), _regname, \ 1969 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1970 (_val)) 1971 1972 void arm_cpu_list(void); 1973 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1974 uint32_t cur_el, bool secure); 1975 1976 /* Interface between CPU and Interrupt controller. */ 1977 #ifndef CONFIG_USER_ONLY 1978 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1979 #else 1980 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1981 { 1982 return true; 1983 } 1984 #endif 1985 /** 1986 * armv7m_nvic_set_pending: mark the specified exception as pending 1987 * @opaque: the NVIC 1988 * @irq: the exception number to mark pending 1989 * @secure: false for non-banked exceptions or for the nonsecure 1990 * version of a banked exception, true for the secure version of a banked 1991 * exception. 1992 * 1993 * Marks the specified exception as pending. Note that we will assert() 1994 * if @secure is true and @irq does not specify one of the fixed set 1995 * of architecturally banked exceptions. 1996 */ 1997 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1998 /** 1999 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2000 * @opaque: the NVIC 2001 * @irq: the exception number to mark pending 2002 * @secure: false for non-banked exceptions or for the nonsecure 2003 * version of a banked exception, true for the secure version of a banked 2004 * exception. 2005 * 2006 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2007 * exceptions (exceptions generated in the course of trying to take 2008 * a different exception). 2009 */ 2010 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2011 /** 2012 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2013 * exception, and whether it targets Secure state 2014 * @opaque: the NVIC 2015 * @pirq: set to pending exception number 2016 * @ptargets_secure: set to whether pending exception targets Secure 2017 * 2018 * This function writes the number of the highest priority pending 2019 * exception (the one which would be made active by 2020 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2021 * to true if the current highest priority pending exception should 2022 * be taken to Secure state, false for NS. 2023 */ 2024 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2025 bool *ptargets_secure); 2026 /** 2027 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2028 * @opaque: the NVIC 2029 * 2030 * Move the current highest priority pending exception from the pending 2031 * state to the active state, and update v7m.exception to indicate that 2032 * it is the exception currently being handled. 2033 */ 2034 void armv7m_nvic_acknowledge_irq(void *opaque); 2035 /** 2036 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2037 * @opaque: the NVIC 2038 * @irq: the exception number to complete 2039 * @secure: true if this exception was secure 2040 * 2041 * Returns: -1 if the irq was not active 2042 * 1 if completing this irq brought us back to base (no active irqs) 2043 * 0 if there is still an irq active after this one was completed 2044 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2045 */ 2046 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2047 /** 2048 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2049 * @opaque: the NVIC 2050 * @irq: the exception number to mark pending 2051 * @secure: false for non-banked exceptions or for the nonsecure 2052 * version of a banked exception, true for the secure version of a banked 2053 * exception. 2054 * 2055 * Return whether an exception is "ready", i.e. whether the exception is 2056 * enabled and is configured at a priority which would allow it to 2057 * interrupt the current execution priority. This controls whether the 2058 * RDY bit for it in the FPCCR is set. 2059 */ 2060 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2061 /** 2062 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2063 * @opaque: the NVIC 2064 * 2065 * Returns: the raw execution priority as defined by the v8M architecture. 2066 * This is the execution priority minus the effects of AIRCR.PRIS, 2067 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2068 * (v8M ARM ARM I_PKLD.) 2069 */ 2070 int armv7m_nvic_raw_execution_priority(void *opaque); 2071 /** 2072 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2073 * priority is negative for the specified security state. 2074 * @opaque: the NVIC 2075 * @secure: the security state to test 2076 * This corresponds to the pseudocode IsReqExecPriNeg(). 2077 */ 2078 #ifndef CONFIG_USER_ONLY 2079 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2080 #else 2081 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2082 { 2083 return false; 2084 } 2085 #endif 2086 2087 /* Interface for defining coprocessor registers. 2088 * Registers are defined in tables of arm_cp_reginfo structs 2089 * which are passed to define_arm_cp_regs(). 2090 */ 2091 2092 /* When looking up a coprocessor register we look for it 2093 * via an integer which encodes all of: 2094 * coprocessor number 2095 * Crn, Crm, opc1, opc2 fields 2096 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2097 * or via MRRC/MCRR?) 2098 * non-secure/secure bank (AArch32 only) 2099 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2100 * (In this case crn and opc2 should be zero.) 2101 * For AArch64, there is no 32/64 bit size distinction; 2102 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2103 * and 4 bit CRn and CRm. The encoding patterns are chosen 2104 * to be easy to convert to and from the KVM encodings, and also 2105 * so that the hashtable can contain both AArch32 and AArch64 2106 * registers (to allow for interprocessing where we might run 2107 * 32 bit code on a 64 bit core). 2108 */ 2109 /* This bit is private to our hashtable cpreg; in KVM register 2110 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2111 * in the upper bits of the 64 bit ID. 2112 */ 2113 #define CP_REG_AA64_SHIFT 28 2114 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2115 2116 /* To enable banking of coprocessor registers depending on ns-bit we 2117 * add a bit to distinguish between secure and non-secure cpregs in the 2118 * hashtable. 2119 */ 2120 #define CP_REG_NS_SHIFT 29 2121 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2122 2123 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2124 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2125 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2126 2127 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2128 (CP_REG_AA64_MASK | \ 2129 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2130 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2131 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2132 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2133 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2134 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2135 2136 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2137 * version used as a key for the coprocessor register hashtable 2138 */ 2139 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2140 { 2141 uint32_t cpregid = kvmid; 2142 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2143 cpregid |= CP_REG_AA64_MASK; 2144 } else { 2145 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2146 cpregid |= (1 << 15); 2147 } 2148 2149 /* KVM is always non-secure so add the NS flag on AArch32 register 2150 * entries. 2151 */ 2152 cpregid |= 1 << CP_REG_NS_SHIFT; 2153 } 2154 return cpregid; 2155 } 2156 2157 /* Convert a truncated 32 bit hashtable key into the full 2158 * 64 bit KVM register ID. 2159 */ 2160 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2161 { 2162 uint64_t kvmid; 2163 2164 if (cpregid & CP_REG_AA64_MASK) { 2165 kvmid = cpregid & ~CP_REG_AA64_MASK; 2166 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2167 } else { 2168 kvmid = cpregid & ~(1 << 15); 2169 if (cpregid & (1 << 15)) { 2170 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2171 } else { 2172 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2173 } 2174 } 2175 return kvmid; 2176 } 2177 2178 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2179 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2180 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2181 * TCG can assume the value to be constant (ie load at translate time) 2182 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2183 * indicates that the TB should not be ended after a write to this register 2184 * (the default is that the TB ends after cp writes). OVERRIDE permits 2185 * a register definition to override a previous definition for the 2186 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2187 * old must have the OVERRIDE bit set. 2188 * ALIAS indicates that this register is an alias view of some underlying 2189 * state which is also visible via another register, and that the other 2190 * register is handling migration and reset; registers marked ALIAS will not be 2191 * migrated but may have their state set by syncing of register state from KVM. 2192 * NO_RAW indicates that this register has no underlying state and does not 2193 * support raw access for state saving/loading; it will not be used for either 2194 * migration or KVM state synchronization. (Typically this is for "registers" 2195 * which are actually used as instructions for cache maintenance and so on.) 2196 * IO indicates that this register does I/O and therefore its accesses 2197 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2198 * registers which implement clocks or timers require this. 2199 */ 2200 #define ARM_CP_SPECIAL 0x0001 2201 #define ARM_CP_CONST 0x0002 2202 #define ARM_CP_64BIT 0x0004 2203 #define ARM_CP_SUPPRESS_TB_END 0x0008 2204 #define ARM_CP_OVERRIDE 0x0010 2205 #define ARM_CP_ALIAS 0x0020 2206 #define ARM_CP_IO 0x0040 2207 #define ARM_CP_NO_RAW 0x0080 2208 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2209 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2210 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2211 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2212 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2213 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2214 #define ARM_CP_FPU 0x1000 2215 #define ARM_CP_SVE 0x2000 2216 #define ARM_CP_NO_GDB 0x4000 2217 /* Used only as a terminator for ARMCPRegInfo lists */ 2218 #define ARM_CP_SENTINEL 0xffff 2219 /* Mask of only the flag bits in a type field */ 2220 #define ARM_CP_FLAG_MASK 0x70ff 2221 2222 /* Valid values for ARMCPRegInfo state field, indicating which of 2223 * the AArch32 and AArch64 execution states this register is visible in. 2224 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2225 * If the reginfo is declared to be visible in both states then a second 2226 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2227 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2228 * Note that we rely on the values of these enums as we iterate through 2229 * the various states in some places. 2230 */ 2231 enum { 2232 ARM_CP_STATE_AA32 = 0, 2233 ARM_CP_STATE_AA64 = 1, 2234 ARM_CP_STATE_BOTH = 2, 2235 }; 2236 2237 /* ARM CP register secure state flags. These flags identify security state 2238 * attributes for a given CP register entry. 2239 * The existence of both or neither secure and non-secure flags indicates that 2240 * the register has both a secure and non-secure hash entry. A single one of 2241 * these flags causes the register to only be hashed for the specified 2242 * security state. 2243 * Although definitions may have any combination of the S/NS bits, each 2244 * registered entry will only have one to identify whether the entry is secure 2245 * or non-secure. 2246 */ 2247 enum { 2248 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2249 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2250 }; 2251 2252 /* Return true if cptype is a valid type field. This is used to try to 2253 * catch errors where the sentinel has been accidentally left off the end 2254 * of a list of registers. 2255 */ 2256 static inline bool cptype_valid(int cptype) 2257 { 2258 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2259 || ((cptype & ARM_CP_SPECIAL) && 2260 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2261 } 2262 2263 /* Access rights: 2264 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2265 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2266 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2267 * (ie any of the privileged modes in Secure state, or Monitor mode). 2268 * If a register is accessible in one privilege level it's always accessible 2269 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2270 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2271 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2272 * terminology a little and call this PL3. 2273 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2274 * with the ELx exception levels. 2275 * 2276 * If access permissions for a register are more complex than can be 2277 * described with these bits, then use a laxer set of restrictions, and 2278 * do the more restrictive/complex check inside a helper function. 2279 */ 2280 #define PL3_R 0x80 2281 #define PL3_W 0x40 2282 #define PL2_R (0x20 | PL3_R) 2283 #define PL2_W (0x10 | PL3_W) 2284 #define PL1_R (0x08 | PL2_R) 2285 #define PL1_W (0x04 | PL2_W) 2286 #define PL0_R (0x02 | PL1_R) 2287 #define PL0_W (0x01 | PL1_W) 2288 2289 /* 2290 * For user-mode some registers are accessible to EL0 via a kernel 2291 * trap-and-emulate ABI. In this case we define the read permissions 2292 * as actually being PL0_R. However some bits of any given register 2293 * may still be masked. 2294 */ 2295 #ifdef CONFIG_USER_ONLY 2296 #define PL0U_R PL0_R 2297 #else 2298 #define PL0U_R PL1_R 2299 #endif 2300 2301 #define PL3_RW (PL3_R | PL3_W) 2302 #define PL2_RW (PL2_R | PL2_W) 2303 #define PL1_RW (PL1_R | PL1_W) 2304 #define PL0_RW (PL0_R | PL0_W) 2305 2306 /* Return the highest implemented Exception Level */ 2307 static inline int arm_highest_el(CPUARMState *env) 2308 { 2309 if (arm_feature(env, ARM_FEATURE_EL3)) { 2310 return 3; 2311 } 2312 if (arm_feature(env, ARM_FEATURE_EL2)) { 2313 return 2; 2314 } 2315 return 1; 2316 } 2317 2318 /* Return true if a v7M CPU is in Handler mode */ 2319 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2320 { 2321 return env->v7m.exception != 0; 2322 } 2323 2324 /* Return the current Exception Level (as per ARMv8; note that this differs 2325 * from the ARMv7 Privilege Level). 2326 */ 2327 static inline int arm_current_el(CPUARMState *env) 2328 { 2329 if (arm_feature(env, ARM_FEATURE_M)) { 2330 return arm_v7m_is_handler_mode(env) || 2331 !(env->v7m.control[env->v7m.secure] & 1); 2332 } 2333 2334 if (is_a64(env)) { 2335 return extract32(env->pstate, 2, 2); 2336 } 2337 2338 switch (env->uncached_cpsr & 0x1f) { 2339 case ARM_CPU_MODE_USR: 2340 return 0; 2341 case ARM_CPU_MODE_HYP: 2342 return 2; 2343 case ARM_CPU_MODE_MON: 2344 return 3; 2345 default: 2346 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2347 /* If EL3 is 32-bit then all secure privileged modes run in 2348 * EL3 2349 */ 2350 return 3; 2351 } 2352 2353 return 1; 2354 } 2355 } 2356 2357 typedef struct ARMCPRegInfo ARMCPRegInfo; 2358 2359 typedef enum CPAccessResult { 2360 /* Access is permitted */ 2361 CP_ACCESS_OK = 0, 2362 /* Access fails due to a configurable trap or enable which would 2363 * result in a categorized exception syndrome giving information about 2364 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2365 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2366 * PL1 if in EL0, otherwise to the current EL). 2367 */ 2368 CP_ACCESS_TRAP = 1, 2369 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2370 * Note that this is not a catch-all case -- the set of cases which may 2371 * result in this failure is specifically defined by the architecture. 2372 */ 2373 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2374 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2375 CP_ACCESS_TRAP_EL2 = 3, 2376 CP_ACCESS_TRAP_EL3 = 4, 2377 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2378 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2379 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2380 /* Access fails and results in an exception syndrome for an FP access, 2381 * trapped directly to EL2 or EL3 2382 */ 2383 CP_ACCESS_TRAP_FP_EL2 = 7, 2384 CP_ACCESS_TRAP_FP_EL3 = 8, 2385 } CPAccessResult; 2386 2387 /* Access functions for coprocessor registers. These cannot fail and 2388 * may not raise exceptions. 2389 */ 2390 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2391 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2392 uint64_t value); 2393 /* Access permission check functions for coprocessor registers. */ 2394 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2395 const ARMCPRegInfo *opaque, 2396 bool isread); 2397 /* Hook function for register reset */ 2398 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2399 2400 #define CP_ANY 0xff 2401 2402 /* Definition of an ARM coprocessor register */ 2403 struct ARMCPRegInfo { 2404 /* Name of register (useful mainly for debugging, need not be unique) */ 2405 const char *name; 2406 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2407 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2408 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2409 * will be decoded to this register. The register read and write 2410 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2411 * used by the program, so it is possible to register a wildcard and 2412 * then behave differently on read/write if necessary. 2413 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2414 * must both be zero. 2415 * For AArch64-visible registers, opc0 is also used. 2416 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2417 * way to distinguish (for KVM's benefit) guest-visible system registers 2418 * from demuxed ones provided to preserve the "no side effects on 2419 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2420 * visible (to match KVM's encoding); cp==0 will be converted to 2421 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2422 */ 2423 uint8_t cp; 2424 uint8_t crn; 2425 uint8_t crm; 2426 uint8_t opc0; 2427 uint8_t opc1; 2428 uint8_t opc2; 2429 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2430 int state; 2431 /* Register type: ARM_CP_* bits/values */ 2432 int type; 2433 /* Access rights: PL*_[RW] */ 2434 int access; 2435 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2436 int secure; 2437 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2438 * this register was defined: can be used to hand data through to the 2439 * register read/write functions, since they are passed the ARMCPRegInfo*. 2440 */ 2441 void *opaque; 2442 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2443 * fieldoffset is non-zero, the reset value of the register. 2444 */ 2445 uint64_t resetvalue; 2446 /* Offset of the field in CPUARMState for this register. 2447 * 2448 * This is not needed if either: 2449 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2450 * 2. both readfn and writefn are specified 2451 */ 2452 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2453 2454 /* Offsets of the secure and non-secure fields in CPUARMState for the 2455 * register if it is banked. These fields are only used during the static 2456 * registration of a register. During hashing the bank associated 2457 * with a given security state is copied to fieldoffset which is used from 2458 * there on out. 2459 * 2460 * It is expected that register definitions use either fieldoffset or 2461 * bank_fieldoffsets in the definition but not both. It is also expected 2462 * that both bank offsets are set when defining a banked register. This 2463 * use indicates that a register is banked. 2464 */ 2465 ptrdiff_t bank_fieldoffsets[2]; 2466 2467 /* Function for making any access checks for this register in addition to 2468 * those specified by the 'access' permissions bits. If NULL, no extra 2469 * checks required. The access check is performed at runtime, not at 2470 * translate time. 2471 */ 2472 CPAccessFn *accessfn; 2473 /* Function for handling reads of this register. If NULL, then reads 2474 * will be done by loading from the offset into CPUARMState specified 2475 * by fieldoffset. 2476 */ 2477 CPReadFn *readfn; 2478 /* Function for handling writes of this register. If NULL, then writes 2479 * will be done by writing to the offset into CPUARMState specified 2480 * by fieldoffset. 2481 */ 2482 CPWriteFn *writefn; 2483 /* Function for doing a "raw" read; used when we need to copy 2484 * coprocessor state to the kernel for KVM or out for 2485 * migration. This only needs to be provided if there is also a 2486 * readfn and it has side effects (for instance clear-on-read bits). 2487 */ 2488 CPReadFn *raw_readfn; 2489 /* Function for doing a "raw" write; used when we need to copy KVM 2490 * kernel coprocessor state into userspace, or for inbound 2491 * migration. This only needs to be provided if there is also a 2492 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2493 * or similar behaviour. 2494 */ 2495 CPWriteFn *raw_writefn; 2496 /* Function for resetting the register. If NULL, then reset will be done 2497 * by writing resetvalue to the field specified in fieldoffset. If 2498 * fieldoffset is 0 then no reset will be done. 2499 */ 2500 CPResetFn *resetfn; 2501 }; 2502 2503 /* Macros which are lvalues for the field in CPUARMState for the 2504 * ARMCPRegInfo *ri. 2505 */ 2506 #define CPREG_FIELD32(env, ri) \ 2507 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2508 #define CPREG_FIELD64(env, ri) \ 2509 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2510 2511 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2512 2513 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2514 const ARMCPRegInfo *regs, void *opaque); 2515 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2516 const ARMCPRegInfo *regs, void *opaque); 2517 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2518 { 2519 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2520 } 2521 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2522 { 2523 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2524 } 2525 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2526 2527 /* 2528 * Definition of an ARM co-processor register as viewed from 2529 * userspace. This is used for presenting sanitised versions of 2530 * registers to userspace when emulating the Linux AArch64 CPU 2531 * ID/feature ABI (advertised as HWCAP_CPUID). 2532 */ 2533 typedef struct ARMCPRegUserSpaceInfo { 2534 /* Name of register */ 2535 const char *name; 2536 2537 /* Is the name actually a glob pattern */ 2538 bool is_glob; 2539 2540 /* Only some bits are exported to user space */ 2541 uint64_t exported_bits; 2542 2543 /* Fixed bits are applied after the mask */ 2544 uint64_t fixed_bits; 2545 } ARMCPRegUserSpaceInfo; 2546 2547 #define REGUSERINFO_SENTINEL { .name = NULL } 2548 2549 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2550 2551 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2552 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2553 uint64_t value); 2554 /* CPReadFn that can be used for read-as-zero behaviour */ 2555 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2556 2557 /* CPResetFn that does nothing, for use if no reset is required even 2558 * if fieldoffset is non zero. 2559 */ 2560 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2561 2562 /* Return true if this reginfo struct's field in the cpu state struct 2563 * is 64 bits wide. 2564 */ 2565 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2566 { 2567 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2568 } 2569 2570 static inline bool cp_access_ok(int current_el, 2571 const ARMCPRegInfo *ri, int isread) 2572 { 2573 return (ri->access >> ((current_el * 2) + isread)) & 1; 2574 } 2575 2576 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2577 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2578 2579 /** 2580 * write_list_to_cpustate 2581 * @cpu: ARMCPU 2582 * 2583 * For each register listed in the ARMCPU cpreg_indexes list, write 2584 * its value from the cpreg_values list into the ARMCPUState structure. 2585 * This updates TCG's working data structures from KVM data or 2586 * from incoming migration state. 2587 * 2588 * Returns: true if all register values were updated correctly, 2589 * false if some register was unknown or could not be written. 2590 * Note that we do not stop early on failure -- we will attempt 2591 * writing all registers in the list. 2592 */ 2593 bool write_list_to_cpustate(ARMCPU *cpu); 2594 2595 /** 2596 * write_cpustate_to_list: 2597 * @cpu: ARMCPU 2598 * 2599 * For each register listed in the ARMCPU cpreg_indexes list, write 2600 * its value from the ARMCPUState structure into the cpreg_values list. 2601 * This is used to copy info from TCG's working data structures into 2602 * KVM or for outbound migration. 2603 * 2604 * Returns: true if all register values were read correctly, 2605 * false if some register was unknown or could not be read. 2606 * Note that we do not stop early on failure -- we will attempt 2607 * reading all registers in the list. 2608 */ 2609 bool write_cpustate_to_list(ARMCPU *cpu); 2610 2611 #define ARM_CPUID_TI915T 0x54029152 2612 #define ARM_CPUID_TI925T 0x54029252 2613 2614 #if defined(CONFIG_USER_ONLY) 2615 #define TARGET_PAGE_BITS 12 2616 #else 2617 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2618 * have to support 1K tiny pages. 2619 */ 2620 #define TARGET_PAGE_BITS_VARY 2621 #define TARGET_PAGE_BITS_MIN 10 2622 #endif 2623 2624 #if defined(TARGET_AARCH64) 2625 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2626 # define TARGET_VIRT_ADDR_SPACE_BITS 48 2627 #else 2628 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2629 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2630 #endif 2631 2632 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2633 unsigned int target_el) 2634 { 2635 CPUARMState *env = cs->env_ptr; 2636 unsigned int cur_el = arm_current_el(env); 2637 bool secure = arm_is_secure(env); 2638 bool pstate_unmasked; 2639 int8_t unmasked = 0; 2640 uint64_t hcr_el2; 2641 2642 /* Don't take exceptions if they target a lower EL. 2643 * This check should catch any exceptions that would not be taken but left 2644 * pending. 2645 */ 2646 if (cur_el > target_el) { 2647 return false; 2648 } 2649 2650 hcr_el2 = arm_hcr_el2_eff(env); 2651 2652 switch (excp_idx) { 2653 case EXCP_FIQ: 2654 pstate_unmasked = !(env->daif & PSTATE_F); 2655 break; 2656 2657 case EXCP_IRQ: 2658 pstate_unmasked = !(env->daif & PSTATE_I); 2659 break; 2660 2661 case EXCP_VFIQ: 2662 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 2663 /* VFIQs are only taken when hypervized and non-secure. */ 2664 return false; 2665 } 2666 return !(env->daif & PSTATE_F); 2667 case EXCP_VIRQ: 2668 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 2669 /* VIRQs are only taken when hypervized and non-secure. */ 2670 return false; 2671 } 2672 return !(env->daif & PSTATE_I); 2673 default: 2674 g_assert_not_reached(); 2675 } 2676 2677 /* Use the target EL, current execution state and SCR/HCR settings to 2678 * determine whether the corresponding CPSR bit is used to mask the 2679 * interrupt. 2680 */ 2681 if ((target_el > cur_el) && (target_el != 1)) { 2682 /* Exceptions targeting a higher EL may not be maskable */ 2683 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2684 /* 64-bit masking rules are simple: exceptions to EL3 2685 * can't be masked, and exceptions to EL2 can only be 2686 * masked from Secure state. The HCR and SCR settings 2687 * don't affect the masking logic, only the interrupt routing. 2688 */ 2689 if (target_el == 3 || !secure) { 2690 unmasked = 1; 2691 } 2692 } else { 2693 /* The old 32-bit-only environment has a more complicated 2694 * masking setup. HCR and SCR bits not only affect interrupt 2695 * routing but also change the behaviour of masking. 2696 */ 2697 bool hcr, scr; 2698 2699 switch (excp_idx) { 2700 case EXCP_FIQ: 2701 /* If FIQs are routed to EL3 or EL2 then there are cases where 2702 * we override the CPSR.F in determining if the exception is 2703 * masked or not. If neither of these are set then we fall back 2704 * to the CPSR.F setting otherwise we further assess the state 2705 * below. 2706 */ 2707 hcr = hcr_el2 & HCR_FMO; 2708 scr = (env->cp15.scr_el3 & SCR_FIQ); 2709 2710 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2711 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2712 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2713 * when non-secure but only when FIQs are only routed to EL3. 2714 */ 2715 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2716 break; 2717 case EXCP_IRQ: 2718 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2719 * we may override the CPSR.I masking when in non-secure state. 2720 * The SCR.IRQ setting has already been taken into consideration 2721 * when setting the target EL, so it does not have a further 2722 * affect here. 2723 */ 2724 hcr = hcr_el2 & HCR_IMO; 2725 scr = false; 2726 break; 2727 default: 2728 g_assert_not_reached(); 2729 } 2730 2731 if ((scr || hcr) && !secure) { 2732 unmasked = 1; 2733 } 2734 } 2735 } 2736 2737 /* The PSTATE bits only mask the interrupt if we have not overriden the 2738 * ability above. 2739 */ 2740 return unmasked || pstate_unmasked; 2741 } 2742 2743 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2744 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2745 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2746 2747 #define cpu_signal_handler cpu_arm_signal_handler 2748 #define cpu_list arm_cpu_list 2749 2750 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2751 * 2752 * If EL3 is 64-bit: 2753 * + NonSecure EL1 & 0 stage 1 2754 * + NonSecure EL1 & 0 stage 2 2755 * + NonSecure EL2 2756 * + Secure EL1 & EL0 2757 * + Secure EL3 2758 * If EL3 is 32-bit: 2759 * + NonSecure PL1 & 0 stage 1 2760 * + NonSecure PL1 & 0 stage 2 2761 * + NonSecure PL2 2762 * + Secure PL0 & PL1 2763 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2764 * 2765 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2766 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2767 * may differ in access permissions even if the VA->PA map is the same 2768 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2769 * translation, which means that we have one mmu_idx that deals with two 2770 * concatenated translation regimes [this sort of combined s1+2 TLB is 2771 * architecturally permitted] 2772 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2773 * handling via the TLB. The only way to do a stage 1 translation without 2774 * the immediate stage 2 translation is via the ATS or AT system insns, 2775 * which can be slow-pathed and always do a page table walk. 2776 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2777 * translation regimes, because they map reasonably well to each other 2778 * and they can't both be active at the same time. 2779 * This gives us the following list of mmu_idx values: 2780 * 2781 * NS EL0 (aka NS PL0) stage 1+2 2782 * NS EL1 (aka NS PL1) stage 1+2 2783 * NS EL2 (aka NS PL2) 2784 * S EL3 (aka S PL1) 2785 * S EL0 (aka S PL0) 2786 * S EL1 (not used if EL3 is 32 bit) 2787 * NS EL0+1 stage 2 2788 * 2789 * (The last of these is an mmu_idx because we want to be able to use the TLB 2790 * for the accesses done as part of a stage 1 page table walk, rather than 2791 * having to walk the stage 2 page table over and over.) 2792 * 2793 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2794 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2795 * NS EL2 if we ever model a Cortex-R52). 2796 * 2797 * M profile CPUs are rather different as they do not have a true MMU. 2798 * They have the following different MMU indexes: 2799 * User 2800 * Privileged 2801 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2802 * Privileged, execution priority negative (ditto) 2803 * If the CPU supports the v8M Security Extension then there are also: 2804 * Secure User 2805 * Secure Privileged 2806 * Secure User, execution priority negative 2807 * Secure Privileged, execution priority negative 2808 * 2809 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2810 * are not quite the same -- different CPU types (most notably M profile 2811 * vs A/R profile) would like to use MMU indexes with different semantics, 2812 * but since we don't ever need to use all of those in a single CPU we 2813 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2814 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2815 * the same for any particular CPU. 2816 * Variables of type ARMMUIdx are always full values, and the core 2817 * index values are in variables of type 'int'. 2818 * 2819 * Our enumeration includes at the end some entries which are not "true" 2820 * mmu_idx values in that they don't have corresponding TLBs and are only 2821 * valid for doing slow path page table walks. 2822 * 2823 * The constant names here are patterned after the general style of the names 2824 * of the AT/ATS operations. 2825 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2826 * For M profile we arrange them to have a bit for priv, a bit for negpri 2827 * and a bit for secure. 2828 */ 2829 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2830 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2831 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2832 2833 /* meanings of the bits for M profile mmu idx values */ 2834 #define ARM_MMU_IDX_M_PRIV 0x1 2835 #define ARM_MMU_IDX_M_NEGPRI 0x2 2836 #define ARM_MMU_IDX_M_S 0x4 2837 2838 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2839 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2840 2841 typedef enum ARMMMUIdx { 2842 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2843 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2844 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2845 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2846 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2847 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2848 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2849 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2850 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2851 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2852 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2853 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2854 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2855 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2856 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2857 /* Indexes below here don't have TLBs and are used only for AT system 2858 * instructions or for the first stage of an S12 page table walk. 2859 */ 2860 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2861 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2862 } ARMMMUIdx; 2863 2864 /* Bit macros for the core-mmu-index values for each index, 2865 * for use when calling tlb_flush_by_mmuidx() and friends. 2866 */ 2867 typedef enum ARMMMUIdxBit { 2868 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2869 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2870 ARMMMUIdxBit_S1E2 = 1 << 2, 2871 ARMMMUIdxBit_S1E3 = 1 << 3, 2872 ARMMMUIdxBit_S1SE0 = 1 << 4, 2873 ARMMMUIdxBit_S1SE1 = 1 << 5, 2874 ARMMMUIdxBit_S2NS = 1 << 6, 2875 ARMMMUIdxBit_MUser = 1 << 0, 2876 ARMMMUIdxBit_MPriv = 1 << 1, 2877 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2878 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2879 ARMMMUIdxBit_MSUser = 1 << 4, 2880 ARMMMUIdxBit_MSPriv = 1 << 5, 2881 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2882 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2883 } ARMMMUIdxBit; 2884 2885 #define MMU_USER_IDX 0 2886 2887 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2888 { 2889 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2890 } 2891 2892 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2893 { 2894 if (arm_feature(env, ARM_FEATURE_M)) { 2895 return mmu_idx | ARM_MMU_IDX_M; 2896 } else { 2897 return mmu_idx | ARM_MMU_IDX_A; 2898 } 2899 } 2900 2901 /* Return the exception level we're running at if this is our mmu_idx */ 2902 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2903 { 2904 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2905 case ARM_MMU_IDX_A: 2906 return mmu_idx & 3; 2907 case ARM_MMU_IDX_M: 2908 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2909 default: 2910 g_assert_not_reached(); 2911 } 2912 } 2913 2914 /* Return the MMU index for a v7M CPU in the specified security and 2915 * privilege state. 2916 */ 2917 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2918 bool secstate, bool priv); 2919 2920 /* Return the MMU index for a v7M CPU in the specified security state */ 2921 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); 2922 2923 /** 2924 * cpu_mmu_index: 2925 * @env: The cpu environment 2926 * @ifetch: True for code access, false for data access. 2927 * 2928 * Return the core mmu index for the current translation regime. 2929 * This function is used by generic TCG code paths. 2930 */ 2931 int cpu_mmu_index(CPUARMState *env, bool ifetch); 2932 2933 /* Indexes used when registering address spaces with cpu_address_space_init */ 2934 typedef enum ARMASIdx { 2935 ARMASIdx_NS = 0, 2936 ARMASIdx_S = 1, 2937 } ARMASIdx; 2938 2939 /* Return the Exception Level targeted by debug exceptions. */ 2940 static inline int arm_debug_target_el(CPUARMState *env) 2941 { 2942 bool secure = arm_is_secure(env); 2943 bool route_to_el2 = false; 2944 2945 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2946 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2947 env->cp15.mdcr_el2 & MDCR_TDE; 2948 } 2949 2950 if (route_to_el2) { 2951 return 2; 2952 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2953 !arm_el_is_aa64(env, 3) && secure) { 2954 return 3; 2955 } else { 2956 return 1; 2957 } 2958 } 2959 2960 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2961 { 2962 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2963 * CSSELR is RAZ/WI. 2964 */ 2965 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2966 } 2967 2968 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 2969 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2970 { 2971 int cur_el = arm_current_el(env); 2972 int debug_el; 2973 2974 if (cur_el == 3) { 2975 return false; 2976 } 2977 2978 /* MDCR_EL3.SDD disables debug events from Secure state */ 2979 if (arm_is_secure_below_el3(env) 2980 && extract32(env->cp15.mdcr_el3, 16, 1)) { 2981 return false; 2982 } 2983 2984 /* 2985 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 2986 * while not masking the (D)ebug bit in DAIF. 2987 */ 2988 debug_el = arm_debug_target_el(env); 2989 2990 if (cur_el == debug_el) { 2991 return extract32(env->cp15.mdscr_el1, 13, 1) 2992 && !(env->daif & PSTATE_D); 2993 } 2994 2995 /* Otherwise the debug target needs to be a higher EL */ 2996 return debug_el > cur_el; 2997 } 2998 2999 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 3000 { 3001 int el = arm_current_el(env); 3002 3003 if (el == 0 && arm_el_is_aa64(env, 1)) { 3004 return aa64_generate_debug_exceptions(env); 3005 } 3006 3007 if (arm_is_secure(env)) { 3008 int spd; 3009 3010 if (el == 0 && (env->cp15.sder & 1)) { 3011 /* SDER.SUIDEN means debug exceptions from Secure EL0 3012 * are always enabled. Otherwise they are controlled by 3013 * SDCR.SPD like those from other Secure ELs. 3014 */ 3015 return true; 3016 } 3017 3018 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3019 switch (spd) { 3020 case 1: 3021 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3022 case 0: 3023 /* For 0b00 we return true if external secure invasive debug 3024 * is enabled. On real hardware this is controlled by external 3025 * signals to the core. QEMU always permits debug, and behaves 3026 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3027 */ 3028 return true; 3029 case 2: 3030 return false; 3031 case 3: 3032 return true; 3033 } 3034 } 3035 3036 return el != 2; 3037 } 3038 3039 /* Return true if debugging exceptions are currently enabled. 3040 * This corresponds to what in ARM ARM pseudocode would be 3041 * if UsingAArch32() then 3042 * return AArch32.GenerateDebugExceptions() 3043 * else 3044 * return AArch64.GenerateDebugExceptions() 3045 * We choose to push the if() down into this function for clarity, 3046 * since the pseudocode has it at all callsites except for the one in 3047 * CheckSoftwareStep(), where it is elided because both branches would 3048 * always return the same value. 3049 */ 3050 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3051 { 3052 if (env->aarch64) { 3053 return aa64_generate_debug_exceptions(env); 3054 } else { 3055 return aa32_generate_debug_exceptions(env); 3056 } 3057 } 3058 3059 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3060 * implicitly means this always returns false in pre-v8 CPUs.) 3061 */ 3062 static inline bool arm_singlestep_active(CPUARMState *env) 3063 { 3064 return extract32(env->cp15.mdscr_el1, 0, 1) 3065 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3066 && arm_generate_debug_exceptions(env); 3067 } 3068 3069 static inline bool arm_sctlr_b(CPUARMState *env) 3070 { 3071 return 3072 /* We need not implement SCTLR.ITD in user-mode emulation, so 3073 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3074 * This lets people run BE32 binaries with "-cpu any". 3075 */ 3076 #ifndef CONFIG_USER_ONLY 3077 !arm_feature(env, ARM_FEATURE_V7) && 3078 #endif 3079 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3080 } 3081 3082 static inline uint64_t arm_sctlr(CPUARMState *env, int el) 3083 { 3084 if (el == 0) { 3085 /* FIXME: ARMv8.1-VHE S2 translation regime. */ 3086 return env->cp15.sctlr_el[1]; 3087 } else { 3088 return env->cp15.sctlr_el[el]; 3089 } 3090 } 3091 3092 3093 /* Return true if the processor is in big-endian mode. */ 3094 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3095 { 3096 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3097 if (!is_a64(env)) { 3098 return 3099 #ifdef CONFIG_USER_ONLY 3100 /* In system mode, BE32 is modelled in line with the 3101 * architecture (as word-invariant big-endianness), where loads 3102 * and stores are done little endian but from addresses which 3103 * are adjusted by XORing with the appropriate constant. So the 3104 * endianness to use for the raw data access is not affected by 3105 * SCTLR.B. 3106 * In user mode, however, we model BE32 as byte-invariant 3107 * big-endianness (because user-only code cannot tell the 3108 * difference), and so we need to use a data access endianness 3109 * that depends on SCTLR.B. 3110 */ 3111 arm_sctlr_b(env) || 3112 #endif 3113 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 3114 } else { 3115 int cur_el = arm_current_el(env); 3116 uint64_t sctlr = arm_sctlr(env, cur_el); 3117 3118 return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; 3119 } 3120 } 3121 3122 #include "exec/cpu-all.h" 3123 3124 /* Bit usage in the TB flags field: bit 31 indicates whether we are 3125 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 3126 * We put flags which are shared between 32 and 64 bit mode at the top 3127 * of the word, and flags which apply to only one mode at the bottom. 3128 */ 3129 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3130 FIELD(TBFLAG_ANY, MMUIDX, 28, 3) 3131 FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) 3132 FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) 3133 /* Target EL if we take a floating-point-disabled exception */ 3134 FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) 3135 FIELD(TBFLAG_ANY, BE_DATA, 23, 1) 3136 3137 /* Bit usage when in AArch32 state: */ 3138 FIELD(TBFLAG_A32, THUMB, 0, 1) 3139 FIELD(TBFLAG_A32, VECLEN, 1, 3) 3140 FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) 3141 FIELD(TBFLAG_A32, VFPEN, 7, 1) 3142 FIELD(TBFLAG_A32, CONDEXEC, 8, 8) 3143 FIELD(TBFLAG_A32, SCTLR_B, 16, 1) 3144 /* We store the bottom two bits of the CPAR as TB flags and handle 3145 * checks on the other bits at runtime 3146 */ 3147 FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) 3148 /* Indicates whether cp register reads and writes by guest code should access 3149 * the secure or nonsecure bank of banked registers; note that this is not 3150 * the same thing as the current security state of the processor! 3151 */ 3152 FIELD(TBFLAG_A32, NS, 19, 1) 3153 /* For M profile only, Handler (ie not Thread) mode */ 3154 FIELD(TBFLAG_A32, HANDLER, 21, 1) 3155 /* For M profile only, whether we should generate stack-limit checks */ 3156 FIELD(TBFLAG_A32, STACKCHECK, 22, 1) 3157 3158 /* Bit usage when in AArch64 state */ 3159 FIELD(TBFLAG_A64, TBII, 0, 2) 3160 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3161 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3162 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3163 FIELD(TBFLAG_A64, BT, 9, 1) 3164 FIELD(TBFLAG_A64, BTYPE, 10, 2) 3165 FIELD(TBFLAG_A64, TBID, 12, 2) 3166 3167 static inline bool bswap_code(bool sctlr_b) 3168 { 3169 #ifdef CONFIG_USER_ONLY 3170 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3171 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3172 * would also end up as a mixed-endian mode with BE code, LE data. 3173 */ 3174 return 3175 #ifdef TARGET_WORDS_BIGENDIAN 3176 1 ^ 3177 #endif 3178 sctlr_b; 3179 #else 3180 /* All code access in ARM is little endian, and there are no loaders 3181 * doing swaps that need to be reversed 3182 */ 3183 return 0; 3184 #endif 3185 } 3186 3187 #ifdef CONFIG_USER_ONLY 3188 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3189 { 3190 return 3191 #ifdef TARGET_WORDS_BIGENDIAN 3192 1 ^ 3193 #endif 3194 arm_cpu_data_is_big_endian(env); 3195 } 3196 #endif 3197 3198 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3199 target_ulong *cs_base, uint32_t *flags); 3200 3201 enum { 3202 QEMU_PSCI_CONDUIT_DISABLED = 0, 3203 QEMU_PSCI_CONDUIT_SMC = 1, 3204 QEMU_PSCI_CONDUIT_HVC = 2, 3205 }; 3206 3207 #ifndef CONFIG_USER_ONLY 3208 /* Return the address space index to use for a memory access */ 3209 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3210 { 3211 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3212 } 3213 3214 /* Return the AddressSpace to use for a memory access 3215 * (which depends on whether the access is S or NS, and whether 3216 * the board gave us a separate AddressSpace for S accesses). 3217 */ 3218 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3219 { 3220 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3221 } 3222 #endif 3223 3224 /** 3225 * arm_register_pre_el_change_hook: 3226 * Register a hook function which will be called immediately before this 3227 * CPU changes exception level or mode. The hook function will be 3228 * passed a pointer to the ARMCPU and the opaque data pointer passed 3229 * to this function when the hook was registered. 3230 * 3231 * Note that if a pre-change hook is called, any registered post-change hooks 3232 * are guaranteed to subsequently be called. 3233 */ 3234 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3235 void *opaque); 3236 /** 3237 * arm_register_el_change_hook: 3238 * Register a hook function which will be called immediately after this 3239 * CPU changes exception level or mode. The hook function will be 3240 * passed a pointer to the ARMCPU and the opaque data pointer passed 3241 * to this function when the hook was registered. 3242 * 3243 * Note that any registered hooks registered here are guaranteed to be called 3244 * if pre-change hooks have been. 3245 */ 3246 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3247 *opaque); 3248 3249 /** 3250 * aa32_vfp_dreg: 3251 * Return a pointer to the Dn register within env in 32-bit mode. 3252 */ 3253 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3254 { 3255 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3256 } 3257 3258 /** 3259 * aa32_vfp_qreg: 3260 * Return a pointer to the Qn register within env in 32-bit mode. 3261 */ 3262 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3263 { 3264 return &env->vfp.zregs[regno].d[0]; 3265 } 3266 3267 /** 3268 * aa64_vfp_qreg: 3269 * Return a pointer to the Qn register within env in 64-bit mode. 3270 */ 3271 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3272 { 3273 return &env->vfp.zregs[regno].d[0]; 3274 } 3275 3276 /* Shared between translate-sve.c and sve_helper.c. */ 3277 extern const uint64_t pred_esz_masks[4]; 3278 3279 /* 3280 * 32-bit feature tests via id registers. 3281 */ 3282 static inline bool isar_feature_thumb_div(const ARMISARegisters *id) 3283 { 3284 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3285 } 3286 3287 static inline bool isar_feature_arm_div(const ARMISARegisters *id) 3288 { 3289 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3290 } 3291 3292 static inline bool isar_feature_jazelle(const ARMISARegisters *id) 3293 { 3294 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3295 } 3296 3297 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3298 { 3299 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3300 } 3301 3302 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3303 { 3304 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3305 } 3306 3307 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3308 { 3309 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3310 } 3311 3312 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3313 { 3314 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3315 } 3316 3317 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3318 { 3319 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3320 } 3321 3322 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3323 { 3324 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3325 } 3326 3327 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3328 { 3329 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3330 } 3331 3332 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3333 { 3334 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3335 } 3336 3337 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3338 { 3339 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3340 } 3341 3342 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3343 { 3344 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3345 } 3346 3347 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3348 { 3349 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3350 } 3351 3352 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3353 { 3354 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3355 } 3356 3357 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3358 { 3359 /* 3360 * This is a placeholder for use by VCMA until the rest of 3361 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3362 * At which point we can properly set and check MVFR1.FPHP. 3363 */ 3364 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3365 } 3366 3367 /* 3368 * We always set the FP and SIMD FP16 fields to indicate identical 3369 * levels of support (assuming SIMD is implemented at all), so 3370 * we only need one set of accessors. 3371 */ 3372 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3373 { 3374 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0; 3375 } 3376 3377 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3378 { 3379 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; 3380 } 3381 3382 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3383 { 3384 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1; 3385 } 3386 3387 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3388 { 3389 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2; 3390 } 3391 3392 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3393 { 3394 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3; 3395 } 3396 3397 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3398 { 3399 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; 3400 } 3401 3402 /* 3403 * 64-bit feature tests via id registers. 3404 */ 3405 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3406 { 3407 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3408 } 3409 3410 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3411 { 3412 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3413 } 3414 3415 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3416 { 3417 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3418 } 3419 3420 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3421 { 3422 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3423 } 3424 3425 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3426 { 3427 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3428 } 3429 3430 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3431 { 3432 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3433 } 3434 3435 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3436 { 3437 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3438 } 3439 3440 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3441 { 3442 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3443 } 3444 3445 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3446 { 3447 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3448 } 3449 3450 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3451 { 3452 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3453 } 3454 3455 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3456 { 3457 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3458 } 3459 3460 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3461 { 3462 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3463 } 3464 3465 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3466 { 3467 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3468 } 3469 3470 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3471 { 3472 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3473 } 3474 3475 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3476 { 3477 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3478 } 3479 3480 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3481 { 3482 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3483 } 3484 3485 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3486 { 3487 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3488 } 3489 3490 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3491 { 3492 /* 3493 * Note that while QEMU will only implement the architected algorithm 3494 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation 3495 * defined algorithms, and thus API+GPI, and this predicate controls 3496 * migration of the 128-bit keys. 3497 */ 3498 return (id->id_aa64isar1 & 3499 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3500 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3501 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3502 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3503 } 3504 3505 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3506 { 3507 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3508 } 3509 3510 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3511 { 3512 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3513 } 3514 3515 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3516 { 3517 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3518 } 3519 3520 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3521 { 3522 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3523 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3524 } 3525 3526 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3527 { 3528 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3529 } 3530 3531 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3532 { 3533 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3534 } 3535 3536 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3537 { 3538 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3539 } 3540 3541 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3542 { 3543 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3544 } 3545 3546 /* 3547 * Forward to the above feature tests given an ARMCPU pointer. 3548 */ 3549 #define cpu_isar_feature(name, cpu) \ 3550 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3551 3552 #endif 3553