1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #define EXCP_UDEF 1 /* undefined instruction */ 43 #define EXCP_SWI 2 /* software interrupt */ 44 #define EXCP_PREFETCH_ABORT 3 45 #define EXCP_DATA_ABORT 4 46 #define EXCP_IRQ 5 47 #define EXCP_FIQ 6 48 #define EXCP_BKPT 7 49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 51 #define EXCP_HVC 11 /* HyperVisor Call */ 52 #define EXCP_HYP_TRAP 12 53 #define EXCP_SMC 13 /* Secure Monitor Call */ 54 #define EXCP_VIRQ 14 55 #define EXCP_VFIQ 15 56 #define EXCP_SEMIHOST 16 /* semihosting call */ 57 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 58 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 59 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 94 /* The usual mapping for an AArch64 system register to its AArch32 95 * counterpart is for the 32 bit world to have access to the lower 96 * half only (with writes leaving the upper half untouched). It's 97 * therefore useful to be able to pass TCG the offset of the least 98 * significant half of a uint64_t struct member. 99 */ 100 #ifdef HOST_WORDS_BIGENDIAN 101 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 102 #define offsetofhigh32(S, M) offsetof(S, M) 103 #else 104 #define offsetoflow32(S, M) offsetof(S, M) 105 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 106 #endif 107 108 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 109 #define ARM_CPU_IRQ 0 110 #define ARM_CPU_FIQ 1 111 #define ARM_CPU_VIRQ 2 112 #define ARM_CPU_VFIQ 3 113 114 #define NB_MMU_MODES 8 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num_cpregs: Number of the Coprocessor registers seen by GDB. 141 * @cpregs_keys: Array that contains the corresponding Key of 142 * a given cpreg with the same order of the cpreg in the XML description. 143 */ 144 typedef struct DynamicGDBXMLInfo { 145 char *desc; 146 int num_cpregs; 147 uint32_t *cpregs_keys; 148 } DynamicGDBXMLInfo; 149 150 /* CPU state for each instance of a generic timer (in cp15 c14) */ 151 typedef struct ARMGenericTimer { 152 uint64_t cval; /* Timer CompareValue register */ 153 uint64_t ctl; /* Timer Control register */ 154 } ARMGenericTimer; 155 156 #define GTIMER_PHYS 0 157 #define GTIMER_VIRT 1 158 #define GTIMER_HYP 2 159 #define GTIMER_SEC 3 160 #define NUM_GTIMERS 4 161 162 typedef struct { 163 uint64_t raw_tcr; 164 uint32_t mask; 165 uint32_t base_mask; 166 } TCR; 167 168 /* Define a maximum sized vector register. 169 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 170 * For 64-bit, this is a 2048-bit SVE register. 171 * 172 * Note that the mapping between S, D, and Q views of the register bank 173 * differs between AArch64 and AArch32. 174 * In AArch32: 175 * Qn = regs[n].d[1]:regs[n].d[0] 176 * Dn = regs[n / 2].d[n & 1] 177 * Sn = regs[n / 4].d[n % 4 / 2], 178 * bits 31..0 for even n, and bits 63..32 for odd n 179 * (and regs[16] to regs[31] are inaccessible) 180 * In AArch64: 181 * Zn = regs[n].d[*] 182 * Qn = regs[n].d[1]:regs[n].d[0] 183 * Dn = regs[n].d[0] 184 * Sn = regs[n].d[0] bits 31..0 185 * Hn = regs[n].d[0] bits 15..0 186 * 187 * This corresponds to the architecturally defined mapping between 188 * the two execution states, and means we do not need to explicitly 189 * map these registers when changing states. 190 * 191 * Align the data for use with TCG host vector operations. 192 */ 193 194 #ifdef TARGET_AARCH64 195 # define ARM_MAX_VQ 16 196 #else 197 # define ARM_MAX_VQ 1 198 #endif 199 200 typedef struct ARMVectorReg { 201 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 202 } ARMVectorReg; 203 204 #ifdef TARGET_AARCH64 205 /* In AArch32 mode, predicate registers do not exist at all. */ 206 typedef struct ARMPredicateReg { 207 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); 208 } ARMPredicateReg; 209 210 /* In AArch32 mode, PAC keys do not exist at all. */ 211 typedef struct ARMPACKey { 212 uint64_t lo, hi; 213 } ARMPACKey; 214 #endif 215 216 217 typedef struct CPUARMState { 218 /* Regs for current mode. */ 219 uint32_t regs[16]; 220 221 /* 32/64 switch only happens when taking and returning from 222 * exceptions so the overlap semantics are taken care of then 223 * instead of having a complicated union. 224 */ 225 /* Regs for A64 mode. */ 226 uint64_t xregs[32]; 227 uint64_t pc; 228 /* PSTATE isn't an architectural register for ARMv8. However, it is 229 * convenient for us to assemble the underlying state into a 32 bit format 230 * identical to the architectural format used for the SPSR. (This is also 231 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 232 * 'pstate' register are.) Of the PSTATE bits: 233 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 234 * semantics as for AArch32, as described in the comments on each field) 235 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 236 * DAIF (exception masks) are kept in env->daif 237 * BTYPE is kept in env->btype 238 * all other bits are stored in their correct places in env->pstate 239 */ 240 uint32_t pstate; 241 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 242 243 /* Frequently accessed CPSR bits are stored separately for efficiency. 244 This contains all the other bits. Use cpsr_{read,write} to access 245 the whole CPSR. */ 246 uint32_t uncached_cpsr; 247 uint32_t spsr; 248 249 /* Banked registers. */ 250 uint64_t banked_spsr[8]; 251 uint32_t banked_r13[8]; 252 uint32_t banked_r14[8]; 253 254 /* These hold r8-r12. */ 255 uint32_t usr_regs[5]; 256 uint32_t fiq_regs[5]; 257 258 /* cpsr flag cache for faster execution */ 259 uint32_t CF; /* 0 or 1 */ 260 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 261 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 262 uint32_t ZF; /* Z set if zero. */ 263 uint32_t QF; /* 0 or 1 */ 264 uint32_t GE; /* cpsr[19:16] */ 265 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 266 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 267 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 268 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 269 270 uint64_t elr_el[4]; /* AArch64 exception link regs */ 271 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 272 273 /* System control coprocessor (cp15) */ 274 struct { 275 uint32_t c0_cpuid; 276 union { /* Cache size selection */ 277 struct { 278 uint64_t _unused_csselr0; 279 uint64_t csselr_ns; 280 uint64_t _unused_csselr1; 281 uint64_t csselr_s; 282 }; 283 uint64_t csselr_el[4]; 284 }; 285 union { /* System control register. */ 286 struct { 287 uint64_t _unused_sctlr; 288 uint64_t sctlr_ns; 289 uint64_t hsctlr; 290 uint64_t sctlr_s; 291 }; 292 uint64_t sctlr_el[4]; 293 }; 294 uint64_t cpacr_el1; /* Architectural feature access control register */ 295 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 296 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 297 uint64_t sder; /* Secure debug enable register. */ 298 uint32_t nsacr; /* Non-secure access control register. */ 299 union { /* MMU translation table base 0. */ 300 struct { 301 uint64_t _unused_ttbr0_0; 302 uint64_t ttbr0_ns; 303 uint64_t _unused_ttbr0_1; 304 uint64_t ttbr0_s; 305 }; 306 uint64_t ttbr0_el[4]; 307 }; 308 union { /* MMU translation table base 1. */ 309 struct { 310 uint64_t _unused_ttbr1_0; 311 uint64_t ttbr1_ns; 312 uint64_t _unused_ttbr1_1; 313 uint64_t ttbr1_s; 314 }; 315 uint64_t ttbr1_el[4]; 316 }; 317 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 318 /* MMU translation table base control. */ 319 TCR tcr_el[4]; 320 TCR vtcr_el2; /* Virtualization Translation Control. */ 321 uint32_t c2_data; /* MPU data cacheable bits. */ 322 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 323 union { /* MMU domain access control register 324 * MPU write buffer control. 325 */ 326 struct { 327 uint64_t dacr_ns; 328 uint64_t dacr_s; 329 }; 330 struct { 331 uint64_t dacr32_el2; 332 }; 333 }; 334 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 335 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 336 uint64_t hcr_el2; /* Hypervisor configuration register */ 337 uint64_t scr_el3; /* Secure configuration register. */ 338 union { /* Fault status registers. */ 339 struct { 340 uint64_t ifsr_ns; 341 uint64_t ifsr_s; 342 }; 343 struct { 344 uint64_t ifsr32_el2; 345 }; 346 }; 347 union { 348 struct { 349 uint64_t _unused_dfsr; 350 uint64_t dfsr_ns; 351 uint64_t hsr; 352 uint64_t dfsr_s; 353 }; 354 uint64_t esr_el[4]; 355 }; 356 uint32_t c6_region[8]; /* MPU base/size registers. */ 357 union { /* Fault address registers. */ 358 struct { 359 uint64_t _unused_far0; 360 #ifdef HOST_WORDS_BIGENDIAN 361 uint32_t ifar_ns; 362 uint32_t dfar_ns; 363 uint32_t ifar_s; 364 uint32_t dfar_s; 365 #else 366 uint32_t dfar_ns; 367 uint32_t ifar_ns; 368 uint32_t dfar_s; 369 uint32_t ifar_s; 370 #endif 371 uint64_t _unused_far3; 372 }; 373 uint64_t far_el[4]; 374 }; 375 uint64_t hpfar_el2; 376 uint64_t hstr_el2; 377 union { /* Translation result. */ 378 struct { 379 uint64_t _unused_par_0; 380 uint64_t par_ns; 381 uint64_t _unused_par_1; 382 uint64_t par_s; 383 }; 384 uint64_t par_el[4]; 385 }; 386 387 uint32_t c9_insn; /* Cache lockdown registers. */ 388 uint32_t c9_data; 389 uint64_t c9_pmcr; /* performance monitor control register */ 390 uint64_t c9_pmcnten; /* perf monitor counter enables */ 391 uint64_t c9_pmovsr; /* perf monitor overflow status */ 392 uint64_t c9_pmuserenr; /* perf monitor user enable */ 393 uint64_t c9_pmselr; /* perf monitor counter selection register */ 394 uint64_t c9_pminten; /* perf monitor interrupt enables */ 395 union { /* Memory attribute redirection */ 396 struct { 397 #ifdef HOST_WORDS_BIGENDIAN 398 uint64_t _unused_mair_0; 399 uint32_t mair1_ns; 400 uint32_t mair0_ns; 401 uint64_t _unused_mair_1; 402 uint32_t mair1_s; 403 uint32_t mair0_s; 404 #else 405 uint64_t _unused_mair_0; 406 uint32_t mair0_ns; 407 uint32_t mair1_ns; 408 uint64_t _unused_mair_1; 409 uint32_t mair0_s; 410 uint32_t mair1_s; 411 #endif 412 }; 413 uint64_t mair_el[4]; 414 }; 415 union { /* vector base address register */ 416 struct { 417 uint64_t _unused_vbar; 418 uint64_t vbar_ns; 419 uint64_t hvbar; 420 uint64_t vbar_s; 421 }; 422 uint64_t vbar_el[4]; 423 }; 424 uint32_t mvbar; /* (monitor) vector base address register */ 425 struct { /* FCSE PID. */ 426 uint32_t fcseidr_ns; 427 uint32_t fcseidr_s; 428 }; 429 union { /* Context ID. */ 430 struct { 431 uint64_t _unused_contextidr_0; 432 uint64_t contextidr_ns; 433 uint64_t _unused_contextidr_1; 434 uint64_t contextidr_s; 435 }; 436 uint64_t contextidr_el[4]; 437 }; 438 union { /* User RW Thread register. */ 439 struct { 440 uint64_t tpidrurw_ns; 441 uint64_t tpidrprw_ns; 442 uint64_t htpidr; 443 uint64_t _tpidr_el3; 444 }; 445 uint64_t tpidr_el[4]; 446 }; 447 /* The secure banks of these registers don't map anywhere */ 448 uint64_t tpidrurw_s; 449 uint64_t tpidrprw_s; 450 uint64_t tpidruro_s; 451 452 union { /* User RO Thread register. */ 453 uint64_t tpidruro_ns; 454 uint64_t tpidrro_el[1]; 455 }; 456 uint64_t c14_cntfrq; /* Counter Frequency register */ 457 uint64_t c14_cntkctl; /* Timer Control register */ 458 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 459 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 460 ARMGenericTimer c14_timer[NUM_GTIMERS]; 461 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 462 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 463 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 464 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 465 uint32_t c15_threadid; /* TI debugger thread-ID. */ 466 uint32_t c15_config_base_address; /* SCU base address. */ 467 uint32_t c15_diagnostic; /* diagnostic register */ 468 uint32_t c15_power_diagnostic; 469 uint32_t c15_power_control; /* power control */ 470 uint64_t dbgbvr[16]; /* breakpoint value registers */ 471 uint64_t dbgbcr[16]; /* breakpoint control registers */ 472 uint64_t dbgwvr[16]; /* watchpoint value registers */ 473 uint64_t dbgwcr[16]; /* watchpoint control registers */ 474 uint64_t mdscr_el1; 475 uint64_t oslsr_el1; /* OS Lock Status */ 476 uint64_t mdcr_el2; 477 uint64_t mdcr_el3; 478 /* Stores the architectural value of the counter *the last time it was 479 * updated* by pmccntr_op_start. Accesses should always be surrounded 480 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 481 * architecturally-correct value is being read/set. 482 */ 483 uint64_t c15_ccnt; 484 /* Stores the delta between the architectural value and the underlying 485 * cycle count during normal operation. It is used to update c15_ccnt 486 * to be the correct architectural value before accesses. During 487 * accesses, c15_ccnt_delta contains the underlying count being used 488 * for the access, after which it reverts to the delta value in 489 * pmccntr_op_finish. 490 */ 491 uint64_t c15_ccnt_delta; 492 uint64_t c14_pmevcntr[31]; 493 uint64_t c14_pmevcntr_delta[31]; 494 uint64_t c14_pmevtyper[31]; 495 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 496 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 497 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 498 } cp15; 499 500 struct { 501 /* M profile has up to 4 stack pointers: 502 * a Main Stack Pointer and a Process Stack Pointer for each 503 * of the Secure and Non-Secure states. (If the CPU doesn't support 504 * the security extension then it has only two SPs.) 505 * In QEMU we always store the currently active SP in regs[13], 506 * and the non-active SP for the current security state in 507 * v7m.other_sp. The stack pointers for the inactive security state 508 * are stored in other_ss_msp and other_ss_psp. 509 * switch_v7m_security_state() is responsible for rearranging them 510 * when we change security state. 511 */ 512 uint32_t other_sp; 513 uint32_t other_ss_msp; 514 uint32_t other_ss_psp; 515 uint32_t vecbase[M_REG_NUM_BANKS]; 516 uint32_t basepri[M_REG_NUM_BANKS]; 517 uint32_t control[M_REG_NUM_BANKS]; 518 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 519 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 520 uint32_t hfsr; /* HardFault Status */ 521 uint32_t dfsr; /* Debug Fault Status Register */ 522 uint32_t sfsr; /* Secure Fault Status Register */ 523 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 524 uint32_t bfar; /* BusFault Address */ 525 uint32_t sfar; /* Secure Fault Address Register */ 526 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 527 int exception; 528 uint32_t primask[M_REG_NUM_BANKS]; 529 uint32_t faultmask[M_REG_NUM_BANKS]; 530 uint32_t aircr; /* only holds r/w state if security extn implemented */ 531 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 532 uint32_t csselr[M_REG_NUM_BANKS]; 533 uint32_t scr[M_REG_NUM_BANKS]; 534 uint32_t msplim[M_REG_NUM_BANKS]; 535 uint32_t psplim[M_REG_NUM_BANKS]; 536 } v7m; 537 538 /* Information associated with an exception about to be taken: 539 * code which raises an exception must set cs->exception_index and 540 * the relevant parts of this structure; the cpu_do_interrupt function 541 * will then set the guest-visible registers as part of the exception 542 * entry process. 543 */ 544 struct { 545 uint32_t syndrome; /* AArch64 format syndrome register */ 546 uint32_t fsr; /* AArch32 format fault status register info */ 547 uint64_t vaddress; /* virtual addr associated with exception, if any */ 548 uint32_t target_el; /* EL the exception should be targeted for */ 549 /* If we implement EL2 we will also need to store information 550 * about the intermediate physical address for stage 2 faults. 551 */ 552 } exception; 553 554 /* Information associated with an SError */ 555 struct { 556 uint8_t pending; 557 uint8_t has_esr; 558 uint64_t esr; 559 } serror; 560 561 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 562 uint32_t irq_line_state; 563 564 /* Thumb-2 EE state. */ 565 uint32_t teecr; 566 uint32_t teehbr; 567 568 /* VFP coprocessor state. */ 569 struct { 570 ARMVectorReg zregs[32]; 571 572 #ifdef TARGET_AARCH64 573 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 574 #define FFR_PRED_NUM 16 575 ARMPredicateReg pregs[17]; 576 /* Scratch space for aa64 sve predicate temporary. */ 577 ARMPredicateReg preg_tmp; 578 #endif 579 580 /* We store these fpcsr fields separately for convenience. */ 581 uint32_t qc[4] QEMU_ALIGNED(16); 582 int vec_len; 583 int vec_stride; 584 585 uint32_t xregs[16]; 586 587 /* Scratch space for aa32 neon expansion. */ 588 uint32_t scratch[8]; 589 590 /* There are a number of distinct float control structures: 591 * 592 * fp_status: is the "normal" fp status. 593 * fp_status_fp16: used for half-precision calculations 594 * standard_fp_status : the ARM "Standard FPSCR Value" 595 * 596 * Half-precision operations are governed by a separate 597 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 598 * status structure to control this. 599 * 600 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 601 * round-to-nearest and is used by any operations (generally 602 * Neon) which the architecture defines as controlled by the 603 * standard FPSCR value rather than the FPSCR. 604 * 605 * To avoid having to transfer exception bits around, we simply 606 * say that the FPSCR cumulative exception flags are the logical 607 * OR of the flags in the three fp statuses. This relies on the 608 * only thing which needs to read the exception flags being 609 * an explicit FPSCR read. 610 */ 611 float_status fp_status; 612 float_status fp_status_f16; 613 float_status standard_fp_status; 614 615 /* ZCR_EL[1-3] */ 616 uint64_t zcr_el[4]; 617 } vfp; 618 uint64_t exclusive_addr; 619 uint64_t exclusive_val; 620 uint64_t exclusive_high; 621 622 /* iwMMXt coprocessor state. */ 623 struct { 624 uint64_t regs[16]; 625 uint64_t val; 626 627 uint32_t cregs[16]; 628 } iwmmxt; 629 630 #ifdef TARGET_AARCH64 631 ARMPACKey apia_key; 632 ARMPACKey apib_key; 633 ARMPACKey apda_key; 634 ARMPACKey apdb_key; 635 ARMPACKey apga_key; 636 #endif 637 638 #if defined(CONFIG_USER_ONLY) 639 /* For usermode syscall translation. */ 640 int eabi; 641 #endif 642 643 struct CPUBreakpoint *cpu_breakpoint[16]; 644 struct CPUWatchpoint *cpu_watchpoint[16]; 645 646 /* Fields up to this point are cleared by a CPU reset */ 647 struct {} end_reset_fields; 648 649 CPU_COMMON 650 651 /* Fields after CPU_COMMON are preserved across CPU reset. */ 652 653 /* Internal CPU feature flags. */ 654 uint64_t features; 655 656 /* PMSAv7 MPU */ 657 struct { 658 uint32_t *drbar; 659 uint32_t *drsr; 660 uint32_t *dracr; 661 uint32_t rnr[M_REG_NUM_BANKS]; 662 } pmsav7; 663 664 /* PMSAv8 MPU */ 665 struct { 666 /* The PMSAv8 implementation also shares some PMSAv7 config 667 * and state: 668 * pmsav7.rnr (region number register) 669 * pmsav7_dregion (number of configured regions) 670 */ 671 uint32_t *rbar[M_REG_NUM_BANKS]; 672 uint32_t *rlar[M_REG_NUM_BANKS]; 673 uint32_t mair0[M_REG_NUM_BANKS]; 674 uint32_t mair1[M_REG_NUM_BANKS]; 675 } pmsav8; 676 677 /* v8M SAU */ 678 struct { 679 uint32_t *rbar; 680 uint32_t *rlar; 681 uint32_t rnr; 682 uint32_t ctrl; 683 } sau; 684 685 void *nvic; 686 const struct arm_boot_info *boot_info; 687 /* Store GICv3CPUState to access from this struct */ 688 void *gicv3state; 689 } CPUARMState; 690 691 /** 692 * ARMELChangeHookFn: 693 * type of a function which can be registered via arm_register_el_change_hook() 694 * to get callbacks when the CPU changes its exception level or mode. 695 */ 696 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 697 typedef struct ARMELChangeHook ARMELChangeHook; 698 struct ARMELChangeHook { 699 ARMELChangeHookFn *hook; 700 void *opaque; 701 QLIST_ENTRY(ARMELChangeHook) node; 702 }; 703 704 /* These values map onto the return values for 705 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 706 typedef enum ARMPSCIState { 707 PSCI_ON = 0, 708 PSCI_OFF = 1, 709 PSCI_ON_PENDING = 2 710 } ARMPSCIState; 711 712 typedef struct ARMISARegisters ARMISARegisters; 713 714 /** 715 * ARMCPU: 716 * @env: #CPUARMState 717 * 718 * An ARM CPU core. 719 */ 720 struct ARMCPU { 721 /*< private >*/ 722 CPUState parent_obj; 723 /*< public >*/ 724 725 CPUARMState env; 726 727 /* Coprocessor information */ 728 GHashTable *cp_regs; 729 /* For marshalling (mostly coprocessor) register state between the 730 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 731 * we use these arrays. 732 */ 733 /* List of register indexes managed via these arrays; (full KVM style 734 * 64 bit indexes, not CPRegInfo 32 bit indexes) 735 */ 736 uint64_t *cpreg_indexes; 737 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 738 uint64_t *cpreg_values; 739 /* Length of the indexes, values, reset_values arrays */ 740 int32_t cpreg_array_len; 741 /* These are used only for migration: incoming data arrives in 742 * these fields and is sanity checked in post_load before copying 743 * to the working data structures above. 744 */ 745 uint64_t *cpreg_vmstate_indexes; 746 uint64_t *cpreg_vmstate_values; 747 int32_t cpreg_vmstate_array_len; 748 749 DynamicGDBXMLInfo dyn_xml; 750 751 /* Timers used by the generic (architected) timer */ 752 QEMUTimer *gt_timer[NUM_GTIMERS]; 753 /* 754 * Timer used by the PMU. Its state is restored after migration by 755 * pmu_op_finish() - it does not need other handling during migration 756 */ 757 QEMUTimer *pmu_timer; 758 /* GPIO outputs for generic timer */ 759 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 760 /* GPIO output for GICv3 maintenance interrupt signal */ 761 qemu_irq gicv3_maintenance_interrupt; 762 /* GPIO output for the PMU interrupt */ 763 qemu_irq pmu_interrupt; 764 765 /* MemoryRegion to use for secure physical accesses */ 766 MemoryRegion *secure_memory; 767 768 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 769 Object *idau; 770 771 /* 'compatible' string for this CPU for Linux device trees */ 772 const char *dtb_compatible; 773 774 /* PSCI version for this CPU 775 * Bits[31:16] = Major Version 776 * Bits[15:0] = Minor Version 777 */ 778 uint32_t psci_version; 779 780 /* Should CPU start in PSCI powered-off state? */ 781 bool start_powered_off; 782 783 /* Current power state, access guarded by BQL */ 784 ARMPSCIState power_state; 785 786 /* CPU has virtualization extension */ 787 bool has_el2; 788 /* CPU has security extension */ 789 bool has_el3; 790 /* CPU has PMU (Performance Monitor Unit) */ 791 bool has_pmu; 792 793 /* CPU has memory protection unit */ 794 bool has_mpu; 795 /* PMSAv7 MPU number of supported regions */ 796 uint32_t pmsav7_dregion; 797 /* v8M SAU number of supported regions */ 798 uint32_t sau_sregion; 799 800 /* PSCI conduit used to invoke PSCI methods 801 * 0 - disabled, 1 - smc, 2 - hvc 802 */ 803 uint32_t psci_conduit; 804 805 /* For v8M, initial value of the Secure VTOR */ 806 uint32_t init_svtor; 807 808 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 809 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 810 */ 811 uint32_t kvm_target; 812 813 /* KVM init features for this CPU */ 814 uint32_t kvm_init_features[7]; 815 816 /* Uniprocessor system with MP extensions */ 817 bool mp_is_up; 818 819 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 820 * and the probe failed (so we need to report the error in realize) 821 */ 822 bool host_cpu_probe_failed; 823 824 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 825 * register. 826 */ 827 int32_t core_count; 828 829 /* The instance init functions for implementation-specific subclasses 830 * set these fields to specify the implementation-dependent values of 831 * various constant registers and reset values of non-constant 832 * registers. 833 * Some of these might become QOM properties eventually. 834 * Field names match the official register names as defined in the 835 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 836 * is used for reset values of non-constant registers; no reset_ 837 * prefix means a constant register. 838 * Some of these registers are split out into a substructure that 839 * is shared with the translators to control the ISA. 840 */ 841 struct ARMISARegisters { 842 uint32_t id_isar0; 843 uint32_t id_isar1; 844 uint32_t id_isar2; 845 uint32_t id_isar3; 846 uint32_t id_isar4; 847 uint32_t id_isar5; 848 uint32_t id_isar6; 849 uint32_t mvfr0; 850 uint32_t mvfr1; 851 uint32_t mvfr2; 852 uint64_t id_aa64isar0; 853 uint64_t id_aa64isar1; 854 uint64_t id_aa64pfr0; 855 uint64_t id_aa64pfr1; 856 uint64_t id_aa64mmfr0; 857 uint64_t id_aa64mmfr1; 858 } isar; 859 uint32_t midr; 860 uint32_t revidr; 861 uint32_t reset_fpsid; 862 uint32_t ctr; 863 uint32_t reset_sctlr; 864 uint32_t id_pfr0; 865 uint32_t id_pfr1; 866 uint32_t id_dfr0; 867 uint64_t pmceid0; 868 uint64_t pmceid1; 869 uint32_t id_afr0; 870 uint32_t id_mmfr0; 871 uint32_t id_mmfr1; 872 uint32_t id_mmfr2; 873 uint32_t id_mmfr3; 874 uint32_t id_mmfr4; 875 uint64_t id_aa64dfr0; 876 uint64_t id_aa64dfr1; 877 uint64_t id_aa64afr0; 878 uint64_t id_aa64afr1; 879 uint32_t dbgdidr; 880 uint32_t clidr; 881 uint64_t mp_affinity; /* MP ID without feature bits */ 882 /* The elements of this array are the CCSIDR values for each cache, 883 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 884 */ 885 uint32_t ccsidr[16]; 886 uint64_t reset_cbar; 887 uint32_t reset_auxcr; 888 bool reset_hivecs; 889 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 890 uint32_t dcz_blocksize; 891 uint64_t rvbar; 892 893 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 894 int gic_num_lrs; /* number of list registers */ 895 int gic_vpribits; /* number of virtual priority bits */ 896 int gic_vprebits; /* number of virtual preemption bits */ 897 898 /* Whether the cfgend input is high (i.e. this CPU should reset into 899 * big-endian mode). This setting isn't used directly: instead it modifies 900 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 901 * architecture version. 902 */ 903 bool cfgend; 904 905 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 906 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 907 908 int32_t node_id; /* NUMA node this CPU belongs to */ 909 910 /* Used to synchronize KVM and QEMU in-kernel device levels */ 911 uint8_t device_irq_level; 912 913 /* Used to set the maximum vector length the cpu will support. */ 914 uint32_t sve_max_vq; 915 }; 916 917 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 918 { 919 return container_of(env, ARMCPU, env); 920 } 921 922 void arm_cpu_post_init(Object *obj); 923 924 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 925 926 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 927 928 #define ENV_OFFSET offsetof(ARMCPU, env) 929 930 #ifndef CONFIG_USER_ONLY 931 extern const struct VMStateDescription vmstate_arm_cpu; 932 #endif 933 934 void arm_cpu_do_interrupt(CPUState *cpu); 935 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 936 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 937 938 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 939 int flags); 940 941 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 942 MemTxAttrs *attrs); 943 944 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 945 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 946 947 /* Dynamically generates for gdb stub an XML description of the sysregs from 948 * the cp_regs hashtable. Returns the registered sysregs number. 949 */ 950 int arm_gen_dynamic_xml(CPUState *cpu); 951 952 /* Returns the dynamically generated XML for the gdb stub. 953 * Returns a pointer to the XML contents for the specified XML file or NULL 954 * if the XML name doesn't match the predefined one. 955 */ 956 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 957 958 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 959 int cpuid, void *opaque); 960 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 961 int cpuid, void *opaque); 962 963 #ifdef TARGET_AARCH64 964 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 965 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 966 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 967 void aarch64_sve_change_el(CPUARMState *env, int old_el, 968 int new_el, bool el0_a64); 969 #else 970 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 971 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 972 int n, bool a) 973 { } 974 #endif 975 976 target_ulong do_arm_semihosting(CPUARMState *env); 977 void aarch64_sync_32_to_64(CPUARMState *env); 978 void aarch64_sync_64_to_32(CPUARMState *env); 979 980 int fp_exception_el(CPUARMState *env, int cur_el); 981 int sve_exception_el(CPUARMState *env, int cur_el); 982 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 983 984 static inline bool is_a64(CPUARMState *env) 985 { 986 return env->aarch64; 987 } 988 989 /* you can call this signal handler from your SIGBUS and SIGSEGV 990 signal handlers to inform the virtual CPU of exceptions. non zero 991 is returned if the signal was handled by the virtual CPU. */ 992 int cpu_arm_signal_handler(int host_signum, void *pinfo, 993 void *puc); 994 995 /** 996 * pmccntr_op_start/finish 997 * @env: CPUARMState 998 * 999 * Convert the counter in the PMCCNTR between its delta form (the typical mode 1000 * when it's enabled) and the guest-visible value. These two calls must always 1001 * surround any action which might affect the counter. 1002 */ 1003 void pmccntr_op_start(CPUARMState *env); 1004 void pmccntr_op_finish(CPUARMState *env); 1005 1006 /** 1007 * pmu_op_start/finish 1008 * @env: CPUARMState 1009 * 1010 * Convert all PMU counters between their delta form (the typical mode when 1011 * they are enabled) and the guest-visible values. These two calls must 1012 * surround any action which might affect the counters. 1013 */ 1014 void pmu_op_start(CPUARMState *env); 1015 void pmu_op_finish(CPUARMState *env); 1016 1017 /* 1018 * Called when a PMU counter is due to overflow 1019 */ 1020 void arm_pmu_timer_cb(void *opaque); 1021 1022 /** 1023 * Functions to register as EL change hooks for PMU mode filtering 1024 */ 1025 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1026 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1027 1028 /* 1029 * pmu_init 1030 * @cpu: ARMCPU 1031 * 1032 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1033 * for the current configuration 1034 */ 1035 void pmu_init(ARMCPU *cpu); 1036 1037 /* SCTLR bit meanings. Several bits have been reused in newer 1038 * versions of the architecture; in that case we define constants 1039 * for both old and new bit meanings. Code which tests against those 1040 * bits should probably check or otherwise arrange that the CPU 1041 * is the architectural version it expects. 1042 */ 1043 #define SCTLR_M (1U << 0) 1044 #define SCTLR_A (1U << 1) 1045 #define SCTLR_C (1U << 2) 1046 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1047 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1048 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1049 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1050 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1051 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1052 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1053 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1054 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1055 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1056 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1057 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1058 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1059 #define SCTLR_SED (1U << 8) /* v8 onward */ 1060 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1061 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1062 #define SCTLR_F (1U << 10) /* up to v6 */ 1063 #define SCTLR_SW (1U << 10) /* v7 */ 1064 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1065 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1066 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1067 #define SCTLR_I (1U << 12) 1068 #define SCTLR_V (1U << 13) /* AArch32 only */ 1069 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1070 #define SCTLR_RR (1U << 14) /* up to v7 */ 1071 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1072 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1073 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1074 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1075 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1076 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1077 #define SCTLR_BR (1U << 17) /* PMSA only */ 1078 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1079 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1080 #define SCTLR_WXN (1U << 19) 1081 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1082 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1083 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1084 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1085 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1086 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1087 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1088 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1089 #define SCTLR_VE (1U << 24) /* up to v7 */ 1090 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1091 #define SCTLR_EE (1U << 25) 1092 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1093 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1094 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1095 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1096 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1097 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1098 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1099 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1100 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1101 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1102 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1103 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1104 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1105 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1106 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1107 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1108 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1109 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1110 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1111 1112 #define CPTR_TCPAC (1U << 31) 1113 #define CPTR_TTA (1U << 20) 1114 #define CPTR_TFP (1U << 10) 1115 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1116 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1117 1118 #define MDCR_EPMAD (1U << 21) 1119 #define MDCR_EDAD (1U << 20) 1120 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1121 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1122 #define MDCR_SDD (1U << 16) 1123 #define MDCR_SPD (3U << 14) 1124 #define MDCR_TDRA (1U << 11) 1125 #define MDCR_TDOSA (1U << 10) 1126 #define MDCR_TDA (1U << 9) 1127 #define MDCR_TDE (1U << 8) 1128 #define MDCR_HPME (1U << 7) 1129 #define MDCR_TPM (1U << 6) 1130 #define MDCR_TPMCR (1U << 5) 1131 #define MDCR_HPMN (0x1fU) 1132 1133 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1134 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1135 1136 #define CPSR_M (0x1fU) 1137 #define CPSR_T (1U << 5) 1138 #define CPSR_F (1U << 6) 1139 #define CPSR_I (1U << 7) 1140 #define CPSR_A (1U << 8) 1141 #define CPSR_E (1U << 9) 1142 #define CPSR_IT_2_7 (0xfc00U) 1143 #define CPSR_GE (0xfU << 16) 1144 #define CPSR_IL (1U << 20) 1145 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 1146 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 1147 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 1148 * where it is live state but not accessible to the AArch32 code. 1149 */ 1150 #define CPSR_RESERVED (0x7U << 21) 1151 #define CPSR_J (1U << 24) 1152 #define CPSR_IT_0_1 (3U << 25) 1153 #define CPSR_Q (1U << 27) 1154 #define CPSR_V (1U << 28) 1155 #define CPSR_C (1U << 29) 1156 #define CPSR_Z (1U << 30) 1157 #define CPSR_N (1U << 31) 1158 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1159 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1160 1161 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1162 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1163 | CPSR_NZCV) 1164 /* Bits writable in user mode. */ 1165 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1166 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1167 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1168 /* Mask of bits which may be set by exception return copying them from SPSR */ 1169 #define CPSR_ERET_MASK (~CPSR_RESERVED) 1170 1171 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1172 #define XPSR_EXCP 0x1ffU 1173 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1174 #define XPSR_IT_2_7 CPSR_IT_2_7 1175 #define XPSR_GE CPSR_GE 1176 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1177 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1178 #define XPSR_IT_0_1 CPSR_IT_0_1 1179 #define XPSR_Q CPSR_Q 1180 #define XPSR_V CPSR_V 1181 #define XPSR_C CPSR_C 1182 #define XPSR_Z CPSR_Z 1183 #define XPSR_N CPSR_N 1184 #define XPSR_NZCV CPSR_NZCV 1185 #define XPSR_IT CPSR_IT 1186 1187 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1188 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1189 #define TTBCR_PD0 (1U << 4) 1190 #define TTBCR_PD1 (1U << 5) 1191 #define TTBCR_EPD0 (1U << 7) 1192 #define TTBCR_IRGN0 (3U << 8) 1193 #define TTBCR_ORGN0 (3U << 10) 1194 #define TTBCR_SH0 (3U << 12) 1195 #define TTBCR_T1SZ (3U << 16) 1196 #define TTBCR_A1 (1U << 22) 1197 #define TTBCR_EPD1 (1U << 23) 1198 #define TTBCR_IRGN1 (3U << 24) 1199 #define TTBCR_ORGN1 (3U << 26) 1200 #define TTBCR_SH1 (1U << 28) 1201 #define TTBCR_EAE (1U << 31) 1202 1203 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1204 * Only these are valid when in AArch64 mode; in 1205 * AArch32 mode SPSRs are basically CPSR-format. 1206 */ 1207 #define PSTATE_SP (1U) 1208 #define PSTATE_M (0xFU) 1209 #define PSTATE_nRW (1U << 4) 1210 #define PSTATE_F (1U << 6) 1211 #define PSTATE_I (1U << 7) 1212 #define PSTATE_A (1U << 8) 1213 #define PSTATE_D (1U << 9) 1214 #define PSTATE_BTYPE (3U << 10) 1215 #define PSTATE_IL (1U << 20) 1216 #define PSTATE_SS (1U << 21) 1217 #define PSTATE_V (1U << 28) 1218 #define PSTATE_C (1U << 29) 1219 #define PSTATE_Z (1U << 30) 1220 #define PSTATE_N (1U << 31) 1221 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1222 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1223 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1224 /* Mode values for AArch64 */ 1225 #define PSTATE_MODE_EL3h 13 1226 #define PSTATE_MODE_EL3t 12 1227 #define PSTATE_MODE_EL2h 9 1228 #define PSTATE_MODE_EL2t 8 1229 #define PSTATE_MODE_EL1h 5 1230 #define PSTATE_MODE_EL1t 4 1231 #define PSTATE_MODE_EL0t 0 1232 1233 /* Write a new value to v7m.exception, thus transitioning into or out 1234 * of Handler mode; this may result in a change of active stack pointer. 1235 */ 1236 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1237 1238 /* Map EL and handler into a PSTATE_MODE. */ 1239 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1240 { 1241 return (el << 2) | handler; 1242 } 1243 1244 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1245 * interprocessing, so we don't attempt to sync with the cpsr state used by 1246 * the 32 bit decoder. 1247 */ 1248 static inline uint32_t pstate_read(CPUARMState *env) 1249 { 1250 int ZF; 1251 1252 ZF = (env->ZF == 0); 1253 return (env->NF & 0x80000000) | (ZF << 30) 1254 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1255 | env->pstate | env->daif | (env->btype << 10); 1256 } 1257 1258 static inline void pstate_write(CPUARMState *env, uint32_t val) 1259 { 1260 env->ZF = (~val) & PSTATE_Z; 1261 env->NF = val; 1262 env->CF = (val >> 29) & 1; 1263 env->VF = (val << 3) & 0x80000000; 1264 env->daif = val & PSTATE_DAIF; 1265 env->btype = (val >> 10) & 3; 1266 env->pstate = val & ~CACHED_PSTATE_BITS; 1267 } 1268 1269 /* Return the current CPSR value. */ 1270 uint32_t cpsr_read(CPUARMState *env); 1271 1272 typedef enum CPSRWriteType { 1273 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1274 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1275 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1276 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1277 } CPSRWriteType; 1278 1279 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1280 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1281 CPSRWriteType write_type); 1282 1283 /* Return the current xPSR value. */ 1284 static inline uint32_t xpsr_read(CPUARMState *env) 1285 { 1286 int ZF; 1287 ZF = (env->ZF == 0); 1288 return (env->NF & 0x80000000) | (ZF << 30) 1289 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1290 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1291 | ((env->condexec_bits & 0xfc) << 8) 1292 | env->v7m.exception; 1293 } 1294 1295 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1296 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1297 { 1298 if (mask & XPSR_NZCV) { 1299 env->ZF = (~val) & XPSR_Z; 1300 env->NF = val; 1301 env->CF = (val >> 29) & 1; 1302 env->VF = (val << 3) & 0x80000000; 1303 } 1304 if (mask & XPSR_Q) { 1305 env->QF = ((val & XPSR_Q) != 0); 1306 } 1307 if (mask & XPSR_T) { 1308 env->thumb = ((val & XPSR_T) != 0); 1309 } 1310 if (mask & XPSR_IT_0_1) { 1311 env->condexec_bits &= ~3; 1312 env->condexec_bits |= (val >> 25) & 3; 1313 } 1314 if (mask & XPSR_IT_2_7) { 1315 env->condexec_bits &= 3; 1316 env->condexec_bits |= (val >> 8) & 0xfc; 1317 } 1318 if (mask & XPSR_EXCP) { 1319 /* Note that this only happens on exception exit */ 1320 write_v7m_exception(env, val & XPSR_EXCP); 1321 } 1322 } 1323 1324 #define HCR_VM (1ULL << 0) 1325 #define HCR_SWIO (1ULL << 1) 1326 #define HCR_PTW (1ULL << 2) 1327 #define HCR_FMO (1ULL << 3) 1328 #define HCR_IMO (1ULL << 4) 1329 #define HCR_AMO (1ULL << 5) 1330 #define HCR_VF (1ULL << 6) 1331 #define HCR_VI (1ULL << 7) 1332 #define HCR_VSE (1ULL << 8) 1333 #define HCR_FB (1ULL << 9) 1334 #define HCR_BSU_MASK (3ULL << 10) 1335 #define HCR_DC (1ULL << 12) 1336 #define HCR_TWI (1ULL << 13) 1337 #define HCR_TWE (1ULL << 14) 1338 #define HCR_TID0 (1ULL << 15) 1339 #define HCR_TID1 (1ULL << 16) 1340 #define HCR_TID2 (1ULL << 17) 1341 #define HCR_TID3 (1ULL << 18) 1342 #define HCR_TSC (1ULL << 19) 1343 #define HCR_TIDCP (1ULL << 20) 1344 #define HCR_TACR (1ULL << 21) 1345 #define HCR_TSW (1ULL << 22) 1346 #define HCR_TPCP (1ULL << 23) 1347 #define HCR_TPU (1ULL << 24) 1348 #define HCR_TTLB (1ULL << 25) 1349 #define HCR_TVM (1ULL << 26) 1350 #define HCR_TGE (1ULL << 27) 1351 #define HCR_TDZ (1ULL << 28) 1352 #define HCR_HCD (1ULL << 29) 1353 #define HCR_TRVM (1ULL << 30) 1354 #define HCR_RW (1ULL << 31) 1355 #define HCR_CD (1ULL << 32) 1356 #define HCR_ID (1ULL << 33) 1357 #define HCR_E2H (1ULL << 34) 1358 #define HCR_TLOR (1ULL << 35) 1359 #define HCR_TERR (1ULL << 36) 1360 #define HCR_TEA (1ULL << 37) 1361 #define HCR_MIOCNCE (1ULL << 38) 1362 #define HCR_APK (1ULL << 40) 1363 #define HCR_API (1ULL << 41) 1364 #define HCR_NV (1ULL << 42) 1365 #define HCR_NV1 (1ULL << 43) 1366 #define HCR_AT (1ULL << 44) 1367 #define HCR_NV2 (1ULL << 45) 1368 #define HCR_FWB (1ULL << 46) 1369 #define HCR_FIEN (1ULL << 47) 1370 #define HCR_TID4 (1ULL << 49) 1371 #define HCR_TICAB (1ULL << 50) 1372 #define HCR_TOCU (1ULL << 52) 1373 #define HCR_TTLBIS (1ULL << 54) 1374 #define HCR_TTLBOS (1ULL << 55) 1375 #define HCR_ATA (1ULL << 56) 1376 #define HCR_DCT (1ULL << 57) 1377 1378 /* 1379 * When we actually implement ARMv8.1-VHE we should add HCR_E2H to 1380 * HCR_MASK and then clear it again if the feature bit is not set in 1381 * hcr_write(). 1382 */ 1383 #define HCR_MASK ((1ULL << 34) - 1) 1384 1385 #define SCR_NS (1U << 0) 1386 #define SCR_IRQ (1U << 1) 1387 #define SCR_FIQ (1U << 2) 1388 #define SCR_EA (1U << 3) 1389 #define SCR_FW (1U << 4) 1390 #define SCR_AW (1U << 5) 1391 #define SCR_NET (1U << 6) 1392 #define SCR_SMD (1U << 7) 1393 #define SCR_HCE (1U << 8) 1394 #define SCR_SIF (1U << 9) 1395 #define SCR_RW (1U << 10) 1396 #define SCR_ST (1U << 11) 1397 #define SCR_TWI (1U << 12) 1398 #define SCR_TWE (1U << 13) 1399 #define SCR_TLOR (1U << 14) 1400 #define SCR_TERR (1U << 15) 1401 #define SCR_APK (1U << 16) 1402 #define SCR_API (1U << 17) 1403 #define SCR_EEL2 (1U << 18) 1404 #define SCR_EASE (1U << 19) 1405 #define SCR_NMEA (1U << 20) 1406 #define SCR_FIEN (1U << 21) 1407 #define SCR_ENSCXT (1U << 25) 1408 #define SCR_ATA (1U << 26) 1409 1410 /* Return the current FPSCR value. */ 1411 uint32_t vfp_get_fpscr(CPUARMState *env); 1412 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1413 1414 /* FPCR, Floating Point Control Register 1415 * FPSR, Floating Poiht Status Register 1416 * 1417 * For A64 the FPSCR is split into two logically distinct registers, 1418 * FPCR and FPSR. However since they still use non-overlapping bits 1419 * we store the underlying state in fpscr and just mask on read/write. 1420 */ 1421 #define FPSR_MASK 0xf800009f 1422 #define FPCR_MASK 0x07ff9f00 1423 1424 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1425 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1426 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1427 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1428 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1429 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1430 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1431 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1432 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1433 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1434 1435 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1436 { 1437 return vfp_get_fpscr(env) & FPSR_MASK; 1438 } 1439 1440 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1441 { 1442 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1443 vfp_set_fpscr(env, new_fpscr); 1444 } 1445 1446 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1447 { 1448 return vfp_get_fpscr(env) & FPCR_MASK; 1449 } 1450 1451 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1452 { 1453 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1454 vfp_set_fpscr(env, new_fpscr); 1455 } 1456 1457 enum arm_cpu_mode { 1458 ARM_CPU_MODE_USR = 0x10, 1459 ARM_CPU_MODE_FIQ = 0x11, 1460 ARM_CPU_MODE_IRQ = 0x12, 1461 ARM_CPU_MODE_SVC = 0x13, 1462 ARM_CPU_MODE_MON = 0x16, 1463 ARM_CPU_MODE_ABT = 0x17, 1464 ARM_CPU_MODE_HYP = 0x1a, 1465 ARM_CPU_MODE_UND = 0x1b, 1466 ARM_CPU_MODE_SYS = 0x1f 1467 }; 1468 1469 /* VFP system registers. */ 1470 #define ARM_VFP_FPSID 0 1471 #define ARM_VFP_FPSCR 1 1472 #define ARM_VFP_MVFR2 5 1473 #define ARM_VFP_MVFR1 6 1474 #define ARM_VFP_MVFR0 7 1475 #define ARM_VFP_FPEXC 8 1476 #define ARM_VFP_FPINST 9 1477 #define ARM_VFP_FPINST2 10 1478 1479 /* iwMMXt coprocessor control registers. */ 1480 #define ARM_IWMMXT_wCID 0 1481 #define ARM_IWMMXT_wCon 1 1482 #define ARM_IWMMXT_wCSSF 2 1483 #define ARM_IWMMXT_wCASF 3 1484 #define ARM_IWMMXT_wCGR0 8 1485 #define ARM_IWMMXT_wCGR1 9 1486 #define ARM_IWMMXT_wCGR2 10 1487 #define ARM_IWMMXT_wCGR3 11 1488 1489 /* V7M CCR bits */ 1490 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1491 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1492 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1493 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1494 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1495 FIELD(V7M_CCR, STKALIGN, 9, 1) 1496 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1497 FIELD(V7M_CCR, DC, 16, 1) 1498 FIELD(V7M_CCR, IC, 17, 1) 1499 FIELD(V7M_CCR, BP, 18, 1) 1500 1501 /* V7M SCR bits */ 1502 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1503 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1504 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1505 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1506 1507 /* V7M AIRCR bits */ 1508 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1509 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1510 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1511 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1512 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1513 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1514 FIELD(V7M_AIRCR, PRIS, 14, 1) 1515 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1516 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1517 1518 /* V7M CFSR bits for MMFSR */ 1519 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1520 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1521 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1522 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1523 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1524 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1525 1526 /* V7M CFSR bits for BFSR */ 1527 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1528 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1529 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1530 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1531 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1532 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1533 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1534 1535 /* V7M CFSR bits for UFSR */ 1536 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1537 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1538 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1539 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1540 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1541 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1542 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1543 1544 /* V7M CFSR bit masks covering all of the subregister bits */ 1545 FIELD(V7M_CFSR, MMFSR, 0, 8) 1546 FIELD(V7M_CFSR, BFSR, 8, 8) 1547 FIELD(V7M_CFSR, UFSR, 16, 16) 1548 1549 /* V7M HFSR bits */ 1550 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1551 FIELD(V7M_HFSR, FORCED, 30, 1) 1552 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1553 1554 /* V7M DFSR bits */ 1555 FIELD(V7M_DFSR, HALTED, 0, 1) 1556 FIELD(V7M_DFSR, BKPT, 1, 1) 1557 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1558 FIELD(V7M_DFSR, VCATCH, 3, 1) 1559 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1560 1561 /* V7M SFSR bits */ 1562 FIELD(V7M_SFSR, INVEP, 0, 1) 1563 FIELD(V7M_SFSR, INVIS, 1, 1) 1564 FIELD(V7M_SFSR, INVER, 2, 1) 1565 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1566 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1567 FIELD(V7M_SFSR, LSPERR, 5, 1) 1568 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1569 FIELD(V7M_SFSR, LSERR, 7, 1) 1570 1571 /* v7M MPU_CTRL bits */ 1572 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1573 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1574 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1575 1576 /* v7M CLIDR bits */ 1577 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1578 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1579 FIELD(V7M_CLIDR, LOC, 24, 3) 1580 FIELD(V7M_CLIDR, LOUU, 27, 3) 1581 FIELD(V7M_CLIDR, ICB, 30, 2) 1582 1583 FIELD(V7M_CSSELR, IND, 0, 1) 1584 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1585 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1586 * define a mask for this and check that it doesn't permit running off 1587 * the end of the array. 1588 */ 1589 FIELD(V7M_CSSELR, INDEX, 0, 4) 1590 1591 /* 1592 * System register ID fields. 1593 */ 1594 FIELD(ID_ISAR0, SWAP, 0, 4) 1595 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1596 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1597 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1598 FIELD(ID_ISAR0, COPROC, 16, 4) 1599 FIELD(ID_ISAR0, DEBUG, 20, 4) 1600 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1601 1602 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1603 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1604 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1605 FIELD(ID_ISAR1, EXTEND, 12, 4) 1606 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1607 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1608 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1609 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1610 1611 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1612 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1613 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1614 FIELD(ID_ISAR2, MULT, 12, 4) 1615 FIELD(ID_ISAR2, MULTS, 16, 4) 1616 FIELD(ID_ISAR2, MULTU, 20, 4) 1617 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1618 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1619 1620 FIELD(ID_ISAR3, SATURATE, 0, 4) 1621 FIELD(ID_ISAR3, SIMD, 4, 4) 1622 FIELD(ID_ISAR3, SVC, 8, 4) 1623 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1624 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1625 FIELD(ID_ISAR3, T32COPY, 20, 4) 1626 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1627 FIELD(ID_ISAR3, T32EE, 28, 4) 1628 1629 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1630 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1631 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1632 FIELD(ID_ISAR4, SMC, 12, 4) 1633 FIELD(ID_ISAR4, BARRIER, 16, 4) 1634 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1635 FIELD(ID_ISAR4, PSR_M, 24, 4) 1636 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1637 1638 FIELD(ID_ISAR5, SEVL, 0, 4) 1639 FIELD(ID_ISAR5, AES, 4, 4) 1640 FIELD(ID_ISAR5, SHA1, 8, 4) 1641 FIELD(ID_ISAR5, SHA2, 12, 4) 1642 FIELD(ID_ISAR5, CRC32, 16, 4) 1643 FIELD(ID_ISAR5, RDM, 24, 4) 1644 FIELD(ID_ISAR5, VCMA, 28, 4) 1645 1646 FIELD(ID_ISAR6, JSCVT, 0, 4) 1647 FIELD(ID_ISAR6, DP, 4, 4) 1648 FIELD(ID_ISAR6, FHM, 8, 4) 1649 FIELD(ID_ISAR6, SB, 12, 4) 1650 FIELD(ID_ISAR6, SPECRES, 16, 4) 1651 1652 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1653 FIELD(ID_MMFR4, AC2, 4, 4) 1654 FIELD(ID_MMFR4, XNX, 8, 4) 1655 FIELD(ID_MMFR4, CNP, 12, 4) 1656 FIELD(ID_MMFR4, HPDS, 16, 4) 1657 FIELD(ID_MMFR4, LSM, 20, 4) 1658 FIELD(ID_MMFR4, CCIDX, 24, 4) 1659 FIELD(ID_MMFR4, EVT, 28, 4) 1660 1661 FIELD(ID_AA64ISAR0, AES, 4, 4) 1662 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1663 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1664 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1665 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1666 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1667 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1668 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1669 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1670 FIELD(ID_AA64ISAR0, DP, 44, 4) 1671 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1672 FIELD(ID_AA64ISAR0, TS, 52, 4) 1673 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1674 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1675 1676 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1677 FIELD(ID_AA64ISAR1, APA, 4, 4) 1678 FIELD(ID_AA64ISAR1, API, 8, 4) 1679 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1680 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1681 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1682 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1683 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1684 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1685 FIELD(ID_AA64ISAR1, SB, 36, 4) 1686 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1687 1688 FIELD(ID_AA64PFR0, EL0, 0, 4) 1689 FIELD(ID_AA64PFR0, EL1, 4, 4) 1690 FIELD(ID_AA64PFR0, EL2, 8, 4) 1691 FIELD(ID_AA64PFR0, EL3, 12, 4) 1692 FIELD(ID_AA64PFR0, FP, 16, 4) 1693 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1694 FIELD(ID_AA64PFR0, GIC, 24, 4) 1695 FIELD(ID_AA64PFR0, RAS, 28, 4) 1696 FIELD(ID_AA64PFR0, SVE, 32, 4) 1697 1698 FIELD(ID_AA64PFR1, BT, 0, 4) 1699 FIELD(ID_AA64PFR1, SBSS, 4, 4) 1700 FIELD(ID_AA64PFR1, MTE, 8, 4) 1701 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1702 1703 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1704 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1705 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1706 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1707 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1708 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1709 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1710 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1711 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1712 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1713 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1714 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1715 1716 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1717 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1718 FIELD(ID_AA64MMFR1, VH, 8, 4) 1719 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1720 FIELD(ID_AA64MMFR1, LO, 16, 4) 1721 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1722 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1723 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1724 1725 FIELD(ID_DFR0, COPDBG, 0, 4) 1726 FIELD(ID_DFR0, COPSDBG, 4, 4) 1727 FIELD(ID_DFR0, MMAPDBG, 8, 4) 1728 FIELD(ID_DFR0, COPTRC, 12, 4) 1729 FIELD(ID_DFR0, MMAPTRC, 16, 4) 1730 FIELD(ID_DFR0, MPROFDBG, 20, 4) 1731 FIELD(ID_DFR0, PERFMON, 24, 4) 1732 FIELD(ID_DFR0, TRACEFILT, 28, 4) 1733 1734 FIELD(MVFR0, SIMDREG, 0, 4) 1735 FIELD(MVFR0, FPSP, 4, 4) 1736 FIELD(MVFR0, FPDP, 8, 4) 1737 FIELD(MVFR0, FPTRAP, 12, 4) 1738 FIELD(MVFR0, FPDIVIDE, 16, 4) 1739 FIELD(MVFR0, FPSQRT, 20, 4) 1740 FIELD(MVFR0, FPSHVEC, 24, 4) 1741 FIELD(MVFR0, FPROUND, 28, 4) 1742 1743 FIELD(MVFR1, FPFTZ, 0, 4) 1744 FIELD(MVFR1, FPDNAN, 4, 4) 1745 FIELD(MVFR1, SIMDLS, 8, 4) 1746 FIELD(MVFR1, SIMDINT, 12, 4) 1747 FIELD(MVFR1, SIMDSP, 16, 4) 1748 FIELD(MVFR1, SIMDHP, 20, 4) 1749 FIELD(MVFR1, FPHP, 24, 4) 1750 FIELD(MVFR1, SIMDFMAC, 28, 4) 1751 1752 FIELD(MVFR2, SIMDMISC, 0, 4) 1753 FIELD(MVFR2, FPMISC, 4, 4) 1754 1755 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1756 1757 /* If adding a feature bit which corresponds to a Linux ELF 1758 * HWCAP bit, remember to update the feature-bit-to-hwcap 1759 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1760 */ 1761 enum arm_features { 1762 ARM_FEATURE_VFP, 1763 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1764 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1765 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1766 ARM_FEATURE_V6, 1767 ARM_FEATURE_V6K, 1768 ARM_FEATURE_V7, 1769 ARM_FEATURE_THUMB2, 1770 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1771 ARM_FEATURE_VFP3, 1772 ARM_FEATURE_NEON, 1773 ARM_FEATURE_M, /* Microcontroller profile. */ 1774 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1775 ARM_FEATURE_THUMB2EE, 1776 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1777 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1778 ARM_FEATURE_V4T, 1779 ARM_FEATURE_V5, 1780 ARM_FEATURE_STRONGARM, 1781 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1782 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1783 ARM_FEATURE_GENERIC_TIMER, 1784 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1785 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1786 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1787 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1788 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1789 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1790 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1791 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1792 ARM_FEATURE_V8, 1793 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1794 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1795 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1796 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1797 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1798 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1799 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1800 ARM_FEATURE_PMU, /* has PMU support */ 1801 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1802 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1803 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1804 }; 1805 1806 static inline int arm_feature(CPUARMState *env, int feature) 1807 { 1808 return (env->features & (1ULL << feature)) != 0; 1809 } 1810 1811 #if !defined(CONFIG_USER_ONLY) 1812 /* Return true if exception levels below EL3 are in secure state, 1813 * or would be following an exception return to that level. 1814 * Unlike arm_is_secure() (which is always a question about the 1815 * _current_ state of the CPU) this doesn't care about the current 1816 * EL or mode. 1817 */ 1818 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1819 { 1820 if (arm_feature(env, ARM_FEATURE_EL3)) { 1821 return !(env->cp15.scr_el3 & SCR_NS); 1822 } else { 1823 /* If EL3 is not supported then the secure state is implementation 1824 * defined, in which case QEMU defaults to non-secure. 1825 */ 1826 return false; 1827 } 1828 } 1829 1830 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1831 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1832 { 1833 if (arm_feature(env, ARM_FEATURE_EL3)) { 1834 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1835 /* CPU currently in AArch64 state and EL3 */ 1836 return true; 1837 } else if (!is_a64(env) && 1838 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1839 /* CPU currently in AArch32 state and monitor mode */ 1840 return true; 1841 } 1842 } 1843 return false; 1844 } 1845 1846 /* Return true if the processor is in secure state */ 1847 static inline bool arm_is_secure(CPUARMState *env) 1848 { 1849 if (arm_is_el3_or_mon(env)) { 1850 return true; 1851 } 1852 return arm_is_secure_below_el3(env); 1853 } 1854 1855 #else 1856 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1857 { 1858 return false; 1859 } 1860 1861 static inline bool arm_is_secure(CPUARMState *env) 1862 { 1863 return false; 1864 } 1865 #endif 1866 1867 /** 1868 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 1869 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 1870 * "for all purposes other than a direct read or write access of HCR_EL2." 1871 * Not included here is HCR_RW. 1872 */ 1873 uint64_t arm_hcr_el2_eff(CPUARMState *env); 1874 1875 /* Return true if the specified exception level is running in AArch64 state. */ 1876 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1877 { 1878 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1879 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1880 */ 1881 assert(el >= 1 && el <= 3); 1882 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1883 1884 /* The highest exception level is always at the maximum supported 1885 * register width, and then lower levels have a register width controlled 1886 * by bits in the SCR or HCR registers. 1887 */ 1888 if (el == 3) { 1889 return aa64; 1890 } 1891 1892 if (arm_feature(env, ARM_FEATURE_EL3)) { 1893 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1894 } 1895 1896 if (el == 2) { 1897 return aa64; 1898 } 1899 1900 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1901 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1902 } 1903 1904 return aa64; 1905 } 1906 1907 /* Function for determing whether guest cp register reads and writes should 1908 * access the secure or non-secure bank of a cp register. When EL3 is 1909 * operating in AArch32 state, the NS-bit determines whether the secure 1910 * instance of a cp register should be used. When EL3 is AArch64 (or if 1911 * it doesn't exist at all) then there is no register banking, and all 1912 * accesses are to the non-secure version. 1913 */ 1914 static inline bool access_secure_reg(CPUARMState *env) 1915 { 1916 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1917 !arm_el_is_aa64(env, 3) && 1918 !(env->cp15.scr_el3 & SCR_NS)); 1919 1920 return ret; 1921 } 1922 1923 /* Macros for accessing a specified CP register bank */ 1924 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1925 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1926 1927 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1928 do { \ 1929 if (_secure) { \ 1930 (_env)->cp15._regname##_s = (_val); \ 1931 } else { \ 1932 (_env)->cp15._regname##_ns = (_val); \ 1933 } \ 1934 } while (0) 1935 1936 /* Macros for automatically accessing a specific CP register bank depending on 1937 * the current secure state of the system. These macros are not intended for 1938 * supporting instruction translation reads/writes as these are dependent 1939 * solely on the SCR.NS bit and not the mode. 1940 */ 1941 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1942 A32_BANKED_REG_GET((_env), _regname, \ 1943 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1944 1945 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1946 A32_BANKED_REG_SET((_env), _regname, \ 1947 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1948 (_val)) 1949 1950 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1951 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1952 uint32_t cur_el, bool secure); 1953 1954 /* Interface between CPU and Interrupt controller. */ 1955 #ifndef CONFIG_USER_ONLY 1956 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1957 #else 1958 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1959 { 1960 return true; 1961 } 1962 #endif 1963 /** 1964 * armv7m_nvic_set_pending: mark the specified exception as pending 1965 * @opaque: the NVIC 1966 * @irq: the exception number to mark pending 1967 * @secure: false for non-banked exceptions or for the nonsecure 1968 * version of a banked exception, true for the secure version of a banked 1969 * exception. 1970 * 1971 * Marks the specified exception as pending. Note that we will assert() 1972 * if @secure is true and @irq does not specify one of the fixed set 1973 * of architecturally banked exceptions. 1974 */ 1975 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1976 /** 1977 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 1978 * @opaque: the NVIC 1979 * @irq: the exception number to mark pending 1980 * @secure: false for non-banked exceptions or for the nonsecure 1981 * version of a banked exception, true for the secure version of a banked 1982 * exception. 1983 * 1984 * Similar to armv7m_nvic_set_pending(), but specifically for derived 1985 * exceptions (exceptions generated in the course of trying to take 1986 * a different exception). 1987 */ 1988 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 1989 /** 1990 * armv7m_nvic_get_pending_irq_info: return highest priority pending 1991 * exception, and whether it targets Secure state 1992 * @opaque: the NVIC 1993 * @pirq: set to pending exception number 1994 * @ptargets_secure: set to whether pending exception targets Secure 1995 * 1996 * This function writes the number of the highest priority pending 1997 * exception (the one which would be made active by 1998 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 1999 * to true if the current highest priority pending exception should 2000 * be taken to Secure state, false for NS. 2001 */ 2002 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2003 bool *ptargets_secure); 2004 /** 2005 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2006 * @opaque: the NVIC 2007 * 2008 * Move the current highest priority pending exception from the pending 2009 * state to the active state, and update v7m.exception to indicate that 2010 * it is the exception currently being handled. 2011 */ 2012 void armv7m_nvic_acknowledge_irq(void *opaque); 2013 /** 2014 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2015 * @opaque: the NVIC 2016 * @irq: the exception number to complete 2017 * @secure: true if this exception was secure 2018 * 2019 * Returns: -1 if the irq was not active 2020 * 1 if completing this irq brought us back to base (no active irqs) 2021 * 0 if there is still an irq active after this one was completed 2022 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2023 */ 2024 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2025 /** 2026 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2027 * @opaque: the NVIC 2028 * 2029 * Returns: the raw execution priority as defined by the v8M architecture. 2030 * This is the execution priority minus the effects of AIRCR.PRIS, 2031 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2032 * (v8M ARM ARM I_PKLD.) 2033 */ 2034 int armv7m_nvic_raw_execution_priority(void *opaque); 2035 /** 2036 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2037 * priority is negative for the specified security state. 2038 * @opaque: the NVIC 2039 * @secure: the security state to test 2040 * This corresponds to the pseudocode IsReqExecPriNeg(). 2041 */ 2042 #ifndef CONFIG_USER_ONLY 2043 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2044 #else 2045 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2046 { 2047 return false; 2048 } 2049 #endif 2050 2051 /* Interface for defining coprocessor registers. 2052 * Registers are defined in tables of arm_cp_reginfo structs 2053 * which are passed to define_arm_cp_regs(). 2054 */ 2055 2056 /* When looking up a coprocessor register we look for it 2057 * via an integer which encodes all of: 2058 * coprocessor number 2059 * Crn, Crm, opc1, opc2 fields 2060 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2061 * or via MRRC/MCRR?) 2062 * non-secure/secure bank (AArch32 only) 2063 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2064 * (In this case crn and opc2 should be zero.) 2065 * For AArch64, there is no 32/64 bit size distinction; 2066 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2067 * and 4 bit CRn and CRm. The encoding patterns are chosen 2068 * to be easy to convert to and from the KVM encodings, and also 2069 * so that the hashtable can contain both AArch32 and AArch64 2070 * registers (to allow for interprocessing where we might run 2071 * 32 bit code on a 64 bit core). 2072 */ 2073 /* This bit is private to our hashtable cpreg; in KVM register 2074 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2075 * in the upper bits of the 64 bit ID. 2076 */ 2077 #define CP_REG_AA64_SHIFT 28 2078 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2079 2080 /* To enable banking of coprocessor registers depending on ns-bit we 2081 * add a bit to distinguish between secure and non-secure cpregs in the 2082 * hashtable. 2083 */ 2084 #define CP_REG_NS_SHIFT 29 2085 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2086 2087 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2088 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2089 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2090 2091 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2092 (CP_REG_AA64_MASK | \ 2093 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2094 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2095 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2096 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2097 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2098 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2099 2100 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2101 * version used as a key for the coprocessor register hashtable 2102 */ 2103 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2104 { 2105 uint32_t cpregid = kvmid; 2106 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2107 cpregid |= CP_REG_AA64_MASK; 2108 } else { 2109 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2110 cpregid |= (1 << 15); 2111 } 2112 2113 /* KVM is always non-secure so add the NS flag on AArch32 register 2114 * entries. 2115 */ 2116 cpregid |= 1 << CP_REG_NS_SHIFT; 2117 } 2118 return cpregid; 2119 } 2120 2121 /* Convert a truncated 32 bit hashtable key into the full 2122 * 64 bit KVM register ID. 2123 */ 2124 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2125 { 2126 uint64_t kvmid; 2127 2128 if (cpregid & CP_REG_AA64_MASK) { 2129 kvmid = cpregid & ~CP_REG_AA64_MASK; 2130 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2131 } else { 2132 kvmid = cpregid & ~(1 << 15); 2133 if (cpregid & (1 << 15)) { 2134 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2135 } else { 2136 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2137 } 2138 } 2139 return kvmid; 2140 } 2141 2142 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2143 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2144 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2145 * TCG can assume the value to be constant (ie load at translate time) 2146 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2147 * indicates that the TB should not be ended after a write to this register 2148 * (the default is that the TB ends after cp writes). OVERRIDE permits 2149 * a register definition to override a previous definition for the 2150 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2151 * old must have the OVERRIDE bit set. 2152 * ALIAS indicates that this register is an alias view of some underlying 2153 * state which is also visible via another register, and that the other 2154 * register is handling migration and reset; registers marked ALIAS will not be 2155 * migrated but may have their state set by syncing of register state from KVM. 2156 * NO_RAW indicates that this register has no underlying state and does not 2157 * support raw access for state saving/loading; it will not be used for either 2158 * migration or KVM state synchronization. (Typically this is for "registers" 2159 * which are actually used as instructions for cache maintenance and so on.) 2160 * IO indicates that this register does I/O and therefore its accesses 2161 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2162 * registers which implement clocks or timers require this. 2163 */ 2164 #define ARM_CP_SPECIAL 0x0001 2165 #define ARM_CP_CONST 0x0002 2166 #define ARM_CP_64BIT 0x0004 2167 #define ARM_CP_SUPPRESS_TB_END 0x0008 2168 #define ARM_CP_OVERRIDE 0x0010 2169 #define ARM_CP_ALIAS 0x0020 2170 #define ARM_CP_IO 0x0040 2171 #define ARM_CP_NO_RAW 0x0080 2172 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2173 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2174 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2175 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2176 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2177 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2178 #define ARM_CP_FPU 0x1000 2179 #define ARM_CP_SVE 0x2000 2180 #define ARM_CP_NO_GDB 0x4000 2181 /* Used only as a terminator for ARMCPRegInfo lists */ 2182 #define ARM_CP_SENTINEL 0xffff 2183 /* Mask of only the flag bits in a type field */ 2184 #define ARM_CP_FLAG_MASK 0x70ff 2185 2186 /* Valid values for ARMCPRegInfo state field, indicating which of 2187 * the AArch32 and AArch64 execution states this register is visible in. 2188 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2189 * If the reginfo is declared to be visible in both states then a second 2190 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2191 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2192 * Note that we rely on the values of these enums as we iterate through 2193 * the various states in some places. 2194 */ 2195 enum { 2196 ARM_CP_STATE_AA32 = 0, 2197 ARM_CP_STATE_AA64 = 1, 2198 ARM_CP_STATE_BOTH = 2, 2199 }; 2200 2201 /* ARM CP register secure state flags. These flags identify security state 2202 * attributes for a given CP register entry. 2203 * The existence of both or neither secure and non-secure flags indicates that 2204 * the register has both a secure and non-secure hash entry. A single one of 2205 * these flags causes the register to only be hashed for the specified 2206 * security state. 2207 * Although definitions may have any combination of the S/NS bits, each 2208 * registered entry will only have one to identify whether the entry is secure 2209 * or non-secure. 2210 */ 2211 enum { 2212 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2213 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2214 }; 2215 2216 /* Return true if cptype is a valid type field. This is used to try to 2217 * catch errors where the sentinel has been accidentally left off the end 2218 * of a list of registers. 2219 */ 2220 static inline bool cptype_valid(int cptype) 2221 { 2222 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2223 || ((cptype & ARM_CP_SPECIAL) && 2224 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2225 } 2226 2227 /* Access rights: 2228 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2229 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2230 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2231 * (ie any of the privileged modes in Secure state, or Monitor mode). 2232 * If a register is accessible in one privilege level it's always accessible 2233 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2234 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2235 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2236 * terminology a little and call this PL3. 2237 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2238 * with the ELx exception levels. 2239 * 2240 * If access permissions for a register are more complex than can be 2241 * described with these bits, then use a laxer set of restrictions, and 2242 * do the more restrictive/complex check inside a helper function. 2243 */ 2244 #define PL3_R 0x80 2245 #define PL3_W 0x40 2246 #define PL2_R (0x20 | PL3_R) 2247 #define PL2_W (0x10 | PL3_W) 2248 #define PL1_R (0x08 | PL2_R) 2249 #define PL1_W (0x04 | PL2_W) 2250 #define PL0_R (0x02 | PL1_R) 2251 #define PL0_W (0x01 | PL1_W) 2252 2253 /* 2254 * For user-mode some registers are accessible to EL0 via a kernel 2255 * trap-and-emulate ABI. In this case we define the read permissions 2256 * as actually being PL0_R. However some bits of any given register 2257 * may still be masked. 2258 */ 2259 #ifdef CONFIG_USER_ONLY 2260 #define PL0U_R PL0_R 2261 #else 2262 #define PL0U_R PL1_R 2263 #endif 2264 2265 #define PL3_RW (PL3_R | PL3_W) 2266 #define PL2_RW (PL2_R | PL2_W) 2267 #define PL1_RW (PL1_R | PL1_W) 2268 #define PL0_RW (PL0_R | PL0_W) 2269 2270 /* Return the highest implemented Exception Level */ 2271 static inline int arm_highest_el(CPUARMState *env) 2272 { 2273 if (arm_feature(env, ARM_FEATURE_EL3)) { 2274 return 3; 2275 } 2276 if (arm_feature(env, ARM_FEATURE_EL2)) { 2277 return 2; 2278 } 2279 return 1; 2280 } 2281 2282 /* Return true if a v7M CPU is in Handler mode */ 2283 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2284 { 2285 return env->v7m.exception != 0; 2286 } 2287 2288 /* Return the current Exception Level (as per ARMv8; note that this differs 2289 * from the ARMv7 Privilege Level). 2290 */ 2291 static inline int arm_current_el(CPUARMState *env) 2292 { 2293 if (arm_feature(env, ARM_FEATURE_M)) { 2294 return arm_v7m_is_handler_mode(env) || 2295 !(env->v7m.control[env->v7m.secure] & 1); 2296 } 2297 2298 if (is_a64(env)) { 2299 return extract32(env->pstate, 2, 2); 2300 } 2301 2302 switch (env->uncached_cpsr & 0x1f) { 2303 case ARM_CPU_MODE_USR: 2304 return 0; 2305 case ARM_CPU_MODE_HYP: 2306 return 2; 2307 case ARM_CPU_MODE_MON: 2308 return 3; 2309 default: 2310 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2311 /* If EL3 is 32-bit then all secure privileged modes run in 2312 * EL3 2313 */ 2314 return 3; 2315 } 2316 2317 return 1; 2318 } 2319 } 2320 2321 typedef struct ARMCPRegInfo ARMCPRegInfo; 2322 2323 typedef enum CPAccessResult { 2324 /* Access is permitted */ 2325 CP_ACCESS_OK = 0, 2326 /* Access fails due to a configurable trap or enable which would 2327 * result in a categorized exception syndrome giving information about 2328 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2329 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2330 * PL1 if in EL0, otherwise to the current EL). 2331 */ 2332 CP_ACCESS_TRAP = 1, 2333 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2334 * Note that this is not a catch-all case -- the set of cases which may 2335 * result in this failure is specifically defined by the architecture. 2336 */ 2337 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2338 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2339 CP_ACCESS_TRAP_EL2 = 3, 2340 CP_ACCESS_TRAP_EL3 = 4, 2341 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2342 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2343 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2344 /* Access fails and results in an exception syndrome for an FP access, 2345 * trapped directly to EL2 or EL3 2346 */ 2347 CP_ACCESS_TRAP_FP_EL2 = 7, 2348 CP_ACCESS_TRAP_FP_EL3 = 8, 2349 } CPAccessResult; 2350 2351 /* Access functions for coprocessor registers. These cannot fail and 2352 * may not raise exceptions. 2353 */ 2354 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2355 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2356 uint64_t value); 2357 /* Access permission check functions for coprocessor registers. */ 2358 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2359 const ARMCPRegInfo *opaque, 2360 bool isread); 2361 /* Hook function for register reset */ 2362 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2363 2364 #define CP_ANY 0xff 2365 2366 /* Definition of an ARM coprocessor register */ 2367 struct ARMCPRegInfo { 2368 /* Name of register (useful mainly for debugging, need not be unique) */ 2369 const char *name; 2370 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2371 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2372 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2373 * will be decoded to this register. The register read and write 2374 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2375 * used by the program, so it is possible to register a wildcard and 2376 * then behave differently on read/write if necessary. 2377 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2378 * must both be zero. 2379 * For AArch64-visible registers, opc0 is also used. 2380 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2381 * way to distinguish (for KVM's benefit) guest-visible system registers 2382 * from demuxed ones provided to preserve the "no side effects on 2383 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2384 * visible (to match KVM's encoding); cp==0 will be converted to 2385 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2386 */ 2387 uint8_t cp; 2388 uint8_t crn; 2389 uint8_t crm; 2390 uint8_t opc0; 2391 uint8_t opc1; 2392 uint8_t opc2; 2393 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2394 int state; 2395 /* Register type: ARM_CP_* bits/values */ 2396 int type; 2397 /* Access rights: PL*_[RW] */ 2398 int access; 2399 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2400 int secure; 2401 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2402 * this register was defined: can be used to hand data through to the 2403 * register read/write functions, since they are passed the ARMCPRegInfo*. 2404 */ 2405 void *opaque; 2406 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2407 * fieldoffset is non-zero, the reset value of the register. 2408 */ 2409 uint64_t resetvalue; 2410 /* Offset of the field in CPUARMState for this register. 2411 * 2412 * This is not needed if either: 2413 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2414 * 2. both readfn and writefn are specified 2415 */ 2416 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2417 2418 /* Offsets of the secure and non-secure fields in CPUARMState for the 2419 * register if it is banked. These fields are only used during the static 2420 * registration of a register. During hashing the bank associated 2421 * with a given security state is copied to fieldoffset which is used from 2422 * there on out. 2423 * 2424 * It is expected that register definitions use either fieldoffset or 2425 * bank_fieldoffsets in the definition but not both. It is also expected 2426 * that both bank offsets are set when defining a banked register. This 2427 * use indicates that a register is banked. 2428 */ 2429 ptrdiff_t bank_fieldoffsets[2]; 2430 2431 /* Function for making any access checks for this register in addition to 2432 * those specified by the 'access' permissions bits. If NULL, no extra 2433 * checks required. The access check is performed at runtime, not at 2434 * translate time. 2435 */ 2436 CPAccessFn *accessfn; 2437 /* Function for handling reads of this register. If NULL, then reads 2438 * will be done by loading from the offset into CPUARMState specified 2439 * by fieldoffset. 2440 */ 2441 CPReadFn *readfn; 2442 /* Function for handling writes of this register. If NULL, then writes 2443 * will be done by writing to the offset into CPUARMState specified 2444 * by fieldoffset. 2445 */ 2446 CPWriteFn *writefn; 2447 /* Function for doing a "raw" read; used when we need to copy 2448 * coprocessor state to the kernel for KVM or out for 2449 * migration. This only needs to be provided if there is also a 2450 * readfn and it has side effects (for instance clear-on-read bits). 2451 */ 2452 CPReadFn *raw_readfn; 2453 /* Function for doing a "raw" write; used when we need to copy KVM 2454 * kernel coprocessor state into userspace, or for inbound 2455 * migration. This only needs to be provided if there is also a 2456 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2457 * or similar behaviour. 2458 */ 2459 CPWriteFn *raw_writefn; 2460 /* Function for resetting the register. If NULL, then reset will be done 2461 * by writing resetvalue to the field specified in fieldoffset. If 2462 * fieldoffset is 0 then no reset will be done. 2463 */ 2464 CPResetFn *resetfn; 2465 }; 2466 2467 /* Macros which are lvalues for the field in CPUARMState for the 2468 * ARMCPRegInfo *ri. 2469 */ 2470 #define CPREG_FIELD32(env, ri) \ 2471 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2472 #define CPREG_FIELD64(env, ri) \ 2473 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2474 2475 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2476 2477 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2478 const ARMCPRegInfo *regs, void *opaque); 2479 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2480 const ARMCPRegInfo *regs, void *opaque); 2481 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2482 { 2483 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2484 } 2485 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2486 { 2487 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2488 } 2489 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2490 2491 /* 2492 * Definition of an ARM co-processor register as viewed from 2493 * userspace. This is used for presenting sanitised versions of 2494 * registers to userspace when emulating the Linux AArch64 CPU 2495 * ID/feature ABI (advertised as HWCAP_CPUID). 2496 */ 2497 typedef struct ARMCPRegUserSpaceInfo { 2498 /* Name of register */ 2499 const char *name; 2500 2501 /* Is the name actually a glob pattern */ 2502 bool is_glob; 2503 2504 /* Only some bits are exported to user space */ 2505 uint64_t exported_bits; 2506 2507 /* Fixed bits are applied after the mask */ 2508 uint64_t fixed_bits; 2509 } ARMCPRegUserSpaceInfo; 2510 2511 #define REGUSERINFO_SENTINEL { .name = NULL } 2512 2513 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2514 2515 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2516 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2517 uint64_t value); 2518 /* CPReadFn that can be used for read-as-zero behaviour */ 2519 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2520 2521 /* CPResetFn that does nothing, for use if no reset is required even 2522 * if fieldoffset is non zero. 2523 */ 2524 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2525 2526 /* Return true if this reginfo struct's field in the cpu state struct 2527 * is 64 bits wide. 2528 */ 2529 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2530 { 2531 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2532 } 2533 2534 static inline bool cp_access_ok(int current_el, 2535 const ARMCPRegInfo *ri, int isread) 2536 { 2537 return (ri->access >> ((current_el * 2) + isread)) & 1; 2538 } 2539 2540 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2541 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2542 2543 /** 2544 * write_list_to_cpustate 2545 * @cpu: ARMCPU 2546 * 2547 * For each register listed in the ARMCPU cpreg_indexes list, write 2548 * its value from the cpreg_values list into the ARMCPUState structure. 2549 * This updates TCG's working data structures from KVM data or 2550 * from incoming migration state. 2551 * 2552 * Returns: true if all register values were updated correctly, 2553 * false if some register was unknown or could not be written. 2554 * Note that we do not stop early on failure -- we will attempt 2555 * writing all registers in the list. 2556 */ 2557 bool write_list_to_cpustate(ARMCPU *cpu); 2558 2559 /** 2560 * write_cpustate_to_list: 2561 * @cpu: ARMCPU 2562 * 2563 * For each register listed in the ARMCPU cpreg_indexes list, write 2564 * its value from the ARMCPUState structure into the cpreg_values list. 2565 * This is used to copy info from TCG's working data structures into 2566 * KVM or for outbound migration. 2567 * 2568 * Returns: true if all register values were read correctly, 2569 * false if some register was unknown or could not be read. 2570 * Note that we do not stop early on failure -- we will attempt 2571 * reading all registers in the list. 2572 */ 2573 bool write_cpustate_to_list(ARMCPU *cpu); 2574 2575 #define ARM_CPUID_TI915T 0x54029152 2576 #define ARM_CPUID_TI925T 0x54029252 2577 2578 #if defined(CONFIG_USER_ONLY) 2579 #define TARGET_PAGE_BITS 12 2580 #else 2581 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2582 * have to support 1K tiny pages. 2583 */ 2584 #define TARGET_PAGE_BITS_VARY 2585 #define TARGET_PAGE_BITS_MIN 10 2586 #endif 2587 2588 #if defined(TARGET_AARCH64) 2589 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2590 # define TARGET_VIRT_ADDR_SPACE_BITS 48 2591 #else 2592 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2593 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2594 #endif 2595 2596 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2597 unsigned int target_el) 2598 { 2599 CPUARMState *env = cs->env_ptr; 2600 unsigned int cur_el = arm_current_el(env); 2601 bool secure = arm_is_secure(env); 2602 bool pstate_unmasked; 2603 int8_t unmasked = 0; 2604 uint64_t hcr_el2; 2605 2606 /* Don't take exceptions if they target a lower EL. 2607 * This check should catch any exceptions that would not be taken but left 2608 * pending. 2609 */ 2610 if (cur_el > target_el) { 2611 return false; 2612 } 2613 2614 hcr_el2 = arm_hcr_el2_eff(env); 2615 2616 switch (excp_idx) { 2617 case EXCP_FIQ: 2618 pstate_unmasked = !(env->daif & PSTATE_F); 2619 break; 2620 2621 case EXCP_IRQ: 2622 pstate_unmasked = !(env->daif & PSTATE_I); 2623 break; 2624 2625 case EXCP_VFIQ: 2626 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 2627 /* VFIQs are only taken when hypervized and non-secure. */ 2628 return false; 2629 } 2630 return !(env->daif & PSTATE_F); 2631 case EXCP_VIRQ: 2632 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 2633 /* VIRQs are only taken when hypervized and non-secure. */ 2634 return false; 2635 } 2636 return !(env->daif & PSTATE_I); 2637 default: 2638 g_assert_not_reached(); 2639 } 2640 2641 /* Use the target EL, current execution state and SCR/HCR settings to 2642 * determine whether the corresponding CPSR bit is used to mask the 2643 * interrupt. 2644 */ 2645 if ((target_el > cur_el) && (target_el != 1)) { 2646 /* Exceptions targeting a higher EL may not be maskable */ 2647 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2648 /* 64-bit masking rules are simple: exceptions to EL3 2649 * can't be masked, and exceptions to EL2 can only be 2650 * masked from Secure state. The HCR and SCR settings 2651 * don't affect the masking logic, only the interrupt routing. 2652 */ 2653 if (target_el == 3 || !secure) { 2654 unmasked = 1; 2655 } 2656 } else { 2657 /* The old 32-bit-only environment has a more complicated 2658 * masking setup. HCR and SCR bits not only affect interrupt 2659 * routing but also change the behaviour of masking. 2660 */ 2661 bool hcr, scr; 2662 2663 switch (excp_idx) { 2664 case EXCP_FIQ: 2665 /* If FIQs are routed to EL3 or EL2 then there are cases where 2666 * we override the CPSR.F in determining if the exception is 2667 * masked or not. If neither of these are set then we fall back 2668 * to the CPSR.F setting otherwise we further assess the state 2669 * below. 2670 */ 2671 hcr = hcr_el2 & HCR_FMO; 2672 scr = (env->cp15.scr_el3 & SCR_FIQ); 2673 2674 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2675 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2676 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2677 * when non-secure but only when FIQs are only routed to EL3. 2678 */ 2679 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2680 break; 2681 case EXCP_IRQ: 2682 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2683 * we may override the CPSR.I masking when in non-secure state. 2684 * The SCR.IRQ setting has already been taken into consideration 2685 * when setting the target EL, so it does not have a further 2686 * affect here. 2687 */ 2688 hcr = hcr_el2 & HCR_IMO; 2689 scr = false; 2690 break; 2691 default: 2692 g_assert_not_reached(); 2693 } 2694 2695 if ((scr || hcr) && !secure) { 2696 unmasked = 1; 2697 } 2698 } 2699 } 2700 2701 /* The PSTATE bits only mask the interrupt if we have not overriden the 2702 * ability above. 2703 */ 2704 return unmasked || pstate_unmasked; 2705 } 2706 2707 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2708 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2709 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2710 2711 #define cpu_signal_handler cpu_arm_signal_handler 2712 #define cpu_list arm_cpu_list 2713 2714 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2715 * 2716 * If EL3 is 64-bit: 2717 * + NonSecure EL1 & 0 stage 1 2718 * + NonSecure EL1 & 0 stage 2 2719 * + NonSecure EL2 2720 * + Secure EL1 & EL0 2721 * + Secure EL3 2722 * If EL3 is 32-bit: 2723 * + NonSecure PL1 & 0 stage 1 2724 * + NonSecure PL1 & 0 stage 2 2725 * + NonSecure PL2 2726 * + Secure PL0 & PL1 2727 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2728 * 2729 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2730 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2731 * may differ in access permissions even if the VA->PA map is the same 2732 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2733 * translation, which means that we have one mmu_idx that deals with two 2734 * concatenated translation regimes [this sort of combined s1+2 TLB is 2735 * architecturally permitted] 2736 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2737 * handling via the TLB. The only way to do a stage 1 translation without 2738 * the immediate stage 2 translation is via the ATS or AT system insns, 2739 * which can be slow-pathed and always do a page table walk. 2740 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2741 * translation regimes, because they map reasonably well to each other 2742 * and they can't both be active at the same time. 2743 * This gives us the following list of mmu_idx values: 2744 * 2745 * NS EL0 (aka NS PL0) stage 1+2 2746 * NS EL1 (aka NS PL1) stage 1+2 2747 * NS EL2 (aka NS PL2) 2748 * S EL3 (aka S PL1) 2749 * S EL0 (aka S PL0) 2750 * S EL1 (not used if EL3 is 32 bit) 2751 * NS EL0+1 stage 2 2752 * 2753 * (The last of these is an mmu_idx because we want to be able to use the TLB 2754 * for the accesses done as part of a stage 1 page table walk, rather than 2755 * having to walk the stage 2 page table over and over.) 2756 * 2757 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2758 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2759 * NS EL2 if we ever model a Cortex-R52). 2760 * 2761 * M profile CPUs are rather different as they do not have a true MMU. 2762 * They have the following different MMU indexes: 2763 * User 2764 * Privileged 2765 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2766 * Privileged, execution priority negative (ditto) 2767 * If the CPU supports the v8M Security Extension then there are also: 2768 * Secure User 2769 * Secure Privileged 2770 * Secure User, execution priority negative 2771 * Secure Privileged, execution priority negative 2772 * 2773 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2774 * are not quite the same -- different CPU types (most notably M profile 2775 * vs A/R profile) would like to use MMU indexes with different semantics, 2776 * but since we don't ever need to use all of those in a single CPU we 2777 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2778 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2779 * the same for any particular CPU. 2780 * Variables of type ARMMUIdx are always full values, and the core 2781 * index values are in variables of type 'int'. 2782 * 2783 * Our enumeration includes at the end some entries which are not "true" 2784 * mmu_idx values in that they don't have corresponding TLBs and are only 2785 * valid for doing slow path page table walks. 2786 * 2787 * The constant names here are patterned after the general style of the names 2788 * of the AT/ATS operations. 2789 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2790 * For M profile we arrange them to have a bit for priv, a bit for negpri 2791 * and a bit for secure. 2792 */ 2793 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2794 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2795 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2796 2797 /* meanings of the bits for M profile mmu idx values */ 2798 #define ARM_MMU_IDX_M_PRIV 0x1 2799 #define ARM_MMU_IDX_M_NEGPRI 0x2 2800 #define ARM_MMU_IDX_M_S 0x4 2801 2802 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2803 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2804 2805 typedef enum ARMMMUIdx { 2806 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2807 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2808 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2809 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2810 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2811 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2812 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2813 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2814 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2815 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2816 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2817 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2818 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2819 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2820 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2821 /* Indexes below here don't have TLBs and are used only for AT system 2822 * instructions or for the first stage of an S12 page table walk. 2823 */ 2824 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2825 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2826 } ARMMMUIdx; 2827 2828 /* Bit macros for the core-mmu-index values for each index, 2829 * for use when calling tlb_flush_by_mmuidx() and friends. 2830 */ 2831 typedef enum ARMMMUIdxBit { 2832 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2833 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2834 ARMMMUIdxBit_S1E2 = 1 << 2, 2835 ARMMMUIdxBit_S1E3 = 1 << 3, 2836 ARMMMUIdxBit_S1SE0 = 1 << 4, 2837 ARMMMUIdxBit_S1SE1 = 1 << 5, 2838 ARMMMUIdxBit_S2NS = 1 << 6, 2839 ARMMMUIdxBit_MUser = 1 << 0, 2840 ARMMMUIdxBit_MPriv = 1 << 1, 2841 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2842 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2843 ARMMMUIdxBit_MSUser = 1 << 4, 2844 ARMMMUIdxBit_MSPriv = 1 << 5, 2845 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2846 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2847 } ARMMMUIdxBit; 2848 2849 #define MMU_USER_IDX 0 2850 2851 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2852 { 2853 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2854 } 2855 2856 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2857 { 2858 if (arm_feature(env, ARM_FEATURE_M)) { 2859 return mmu_idx | ARM_MMU_IDX_M; 2860 } else { 2861 return mmu_idx | ARM_MMU_IDX_A; 2862 } 2863 } 2864 2865 /* Return the exception level we're running at if this is our mmu_idx */ 2866 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2867 { 2868 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2869 case ARM_MMU_IDX_A: 2870 return mmu_idx & 3; 2871 case ARM_MMU_IDX_M: 2872 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2873 default: 2874 g_assert_not_reached(); 2875 } 2876 } 2877 2878 /* Return the MMU index for a v7M CPU in the specified security and 2879 * privilege state. 2880 */ 2881 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2882 bool secstate, bool priv); 2883 2884 /* Return the MMU index for a v7M CPU in the specified security state */ 2885 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); 2886 2887 /** 2888 * cpu_mmu_index: 2889 * @env: The cpu environment 2890 * @ifetch: True for code access, false for data access. 2891 * 2892 * Return the core mmu index for the current translation regime. 2893 * This function is used by generic TCG code paths. 2894 */ 2895 int cpu_mmu_index(CPUARMState *env, bool ifetch); 2896 2897 /* Indexes used when registering address spaces with cpu_address_space_init */ 2898 typedef enum ARMASIdx { 2899 ARMASIdx_NS = 0, 2900 ARMASIdx_S = 1, 2901 } ARMASIdx; 2902 2903 /* Return the Exception Level targeted by debug exceptions. */ 2904 static inline int arm_debug_target_el(CPUARMState *env) 2905 { 2906 bool secure = arm_is_secure(env); 2907 bool route_to_el2 = false; 2908 2909 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2910 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2911 env->cp15.mdcr_el2 & MDCR_TDE; 2912 } 2913 2914 if (route_to_el2) { 2915 return 2; 2916 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2917 !arm_el_is_aa64(env, 3) && secure) { 2918 return 3; 2919 } else { 2920 return 1; 2921 } 2922 } 2923 2924 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2925 { 2926 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2927 * CSSELR is RAZ/WI. 2928 */ 2929 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2930 } 2931 2932 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 2933 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2934 { 2935 int cur_el = arm_current_el(env); 2936 int debug_el; 2937 2938 if (cur_el == 3) { 2939 return false; 2940 } 2941 2942 /* MDCR_EL3.SDD disables debug events from Secure state */ 2943 if (arm_is_secure_below_el3(env) 2944 && extract32(env->cp15.mdcr_el3, 16, 1)) { 2945 return false; 2946 } 2947 2948 /* 2949 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 2950 * while not masking the (D)ebug bit in DAIF. 2951 */ 2952 debug_el = arm_debug_target_el(env); 2953 2954 if (cur_el == debug_el) { 2955 return extract32(env->cp15.mdscr_el1, 13, 1) 2956 && !(env->daif & PSTATE_D); 2957 } 2958 2959 /* Otherwise the debug target needs to be a higher EL */ 2960 return debug_el > cur_el; 2961 } 2962 2963 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2964 { 2965 int el = arm_current_el(env); 2966 2967 if (el == 0 && arm_el_is_aa64(env, 1)) { 2968 return aa64_generate_debug_exceptions(env); 2969 } 2970 2971 if (arm_is_secure(env)) { 2972 int spd; 2973 2974 if (el == 0 && (env->cp15.sder & 1)) { 2975 /* SDER.SUIDEN means debug exceptions from Secure EL0 2976 * are always enabled. Otherwise they are controlled by 2977 * SDCR.SPD like those from other Secure ELs. 2978 */ 2979 return true; 2980 } 2981 2982 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2983 switch (spd) { 2984 case 1: 2985 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2986 case 0: 2987 /* For 0b00 we return true if external secure invasive debug 2988 * is enabled. On real hardware this is controlled by external 2989 * signals to the core. QEMU always permits debug, and behaves 2990 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2991 */ 2992 return true; 2993 case 2: 2994 return false; 2995 case 3: 2996 return true; 2997 } 2998 } 2999 3000 return el != 2; 3001 } 3002 3003 /* Return true if debugging exceptions are currently enabled. 3004 * This corresponds to what in ARM ARM pseudocode would be 3005 * if UsingAArch32() then 3006 * return AArch32.GenerateDebugExceptions() 3007 * else 3008 * return AArch64.GenerateDebugExceptions() 3009 * We choose to push the if() down into this function for clarity, 3010 * since the pseudocode has it at all callsites except for the one in 3011 * CheckSoftwareStep(), where it is elided because both branches would 3012 * always return the same value. 3013 */ 3014 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3015 { 3016 if (env->aarch64) { 3017 return aa64_generate_debug_exceptions(env); 3018 } else { 3019 return aa32_generate_debug_exceptions(env); 3020 } 3021 } 3022 3023 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3024 * implicitly means this always returns false in pre-v8 CPUs.) 3025 */ 3026 static inline bool arm_singlestep_active(CPUARMState *env) 3027 { 3028 return extract32(env->cp15.mdscr_el1, 0, 1) 3029 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3030 && arm_generate_debug_exceptions(env); 3031 } 3032 3033 static inline bool arm_sctlr_b(CPUARMState *env) 3034 { 3035 return 3036 /* We need not implement SCTLR.ITD in user-mode emulation, so 3037 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3038 * This lets people run BE32 binaries with "-cpu any". 3039 */ 3040 #ifndef CONFIG_USER_ONLY 3041 !arm_feature(env, ARM_FEATURE_V7) && 3042 #endif 3043 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3044 } 3045 3046 static inline uint64_t arm_sctlr(CPUARMState *env, int el) 3047 { 3048 if (el == 0) { 3049 /* FIXME: ARMv8.1-VHE S2 translation regime. */ 3050 return env->cp15.sctlr_el[1]; 3051 } else { 3052 return env->cp15.sctlr_el[el]; 3053 } 3054 } 3055 3056 3057 /* Return true if the processor is in big-endian mode. */ 3058 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3059 { 3060 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3061 if (!is_a64(env)) { 3062 return 3063 #ifdef CONFIG_USER_ONLY 3064 /* In system mode, BE32 is modelled in line with the 3065 * architecture (as word-invariant big-endianness), where loads 3066 * and stores are done little endian but from addresses which 3067 * are adjusted by XORing with the appropriate constant. So the 3068 * endianness to use for the raw data access is not affected by 3069 * SCTLR.B. 3070 * In user mode, however, we model BE32 as byte-invariant 3071 * big-endianness (because user-only code cannot tell the 3072 * difference), and so we need to use a data access endianness 3073 * that depends on SCTLR.B. 3074 */ 3075 arm_sctlr_b(env) || 3076 #endif 3077 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 3078 } else { 3079 int cur_el = arm_current_el(env); 3080 uint64_t sctlr = arm_sctlr(env, cur_el); 3081 3082 return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; 3083 } 3084 } 3085 3086 #include "exec/cpu-all.h" 3087 3088 /* Bit usage in the TB flags field: bit 31 indicates whether we are 3089 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 3090 * We put flags which are shared between 32 and 64 bit mode at the top 3091 * of the word, and flags which apply to only one mode at the bottom. 3092 */ 3093 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3094 FIELD(TBFLAG_ANY, MMUIDX, 28, 3) 3095 FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) 3096 FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) 3097 /* Target EL if we take a floating-point-disabled exception */ 3098 FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) 3099 FIELD(TBFLAG_ANY, BE_DATA, 23, 1) 3100 3101 /* Bit usage when in AArch32 state: */ 3102 FIELD(TBFLAG_A32, THUMB, 0, 1) 3103 FIELD(TBFLAG_A32, VECLEN, 1, 3) 3104 FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) 3105 FIELD(TBFLAG_A32, VFPEN, 7, 1) 3106 FIELD(TBFLAG_A32, CONDEXEC, 8, 8) 3107 FIELD(TBFLAG_A32, SCTLR_B, 16, 1) 3108 /* We store the bottom two bits of the CPAR as TB flags and handle 3109 * checks on the other bits at runtime 3110 */ 3111 FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) 3112 /* Indicates whether cp register reads and writes by guest code should access 3113 * the secure or nonsecure bank of banked registers; note that this is not 3114 * the same thing as the current security state of the processor! 3115 */ 3116 FIELD(TBFLAG_A32, NS, 19, 1) 3117 /* For M profile only, Handler (ie not Thread) mode */ 3118 FIELD(TBFLAG_A32, HANDLER, 21, 1) 3119 /* For M profile only, whether we should generate stack-limit checks */ 3120 FIELD(TBFLAG_A32, STACKCHECK, 22, 1) 3121 3122 /* Bit usage when in AArch64 state */ 3123 FIELD(TBFLAG_A64, TBII, 0, 2) 3124 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3125 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3126 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3127 FIELD(TBFLAG_A64, BT, 9, 1) 3128 FIELD(TBFLAG_A64, BTYPE, 10, 2) 3129 FIELD(TBFLAG_A64, TBID, 12, 2) 3130 3131 static inline bool bswap_code(bool sctlr_b) 3132 { 3133 #ifdef CONFIG_USER_ONLY 3134 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3135 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3136 * would also end up as a mixed-endian mode with BE code, LE data. 3137 */ 3138 return 3139 #ifdef TARGET_WORDS_BIGENDIAN 3140 1 ^ 3141 #endif 3142 sctlr_b; 3143 #else 3144 /* All code access in ARM is little endian, and there are no loaders 3145 * doing swaps that need to be reversed 3146 */ 3147 return 0; 3148 #endif 3149 } 3150 3151 #ifdef CONFIG_USER_ONLY 3152 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3153 { 3154 return 3155 #ifdef TARGET_WORDS_BIGENDIAN 3156 1 ^ 3157 #endif 3158 arm_cpu_data_is_big_endian(env); 3159 } 3160 #endif 3161 3162 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3163 target_ulong *cs_base, uint32_t *flags); 3164 3165 enum { 3166 QEMU_PSCI_CONDUIT_DISABLED = 0, 3167 QEMU_PSCI_CONDUIT_SMC = 1, 3168 QEMU_PSCI_CONDUIT_HVC = 2, 3169 }; 3170 3171 #ifndef CONFIG_USER_ONLY 3172 /* Return the address space index to use for a memory access */ 3173 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3174 { 3175 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3176 } 3177 3178 /* Return the AddressSpace to use for a memory access 3179 * (which depends on whether the access is S or NS, and whether 3180 * the board gave us a separate AddressSpace for S accesses). 3181 */ 3182 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3183 { 3184 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3185 } 3186 #endif 3187 3188 /** 3189 * arm_register_pre_el_change_hook: 3190 * Register a hook function which will be called immediately before this 3191 * CPU changes exception level or mode. The hook function will be 3192 * passed a pointer to the ARMCPU and the opaque data pointer passed 3193 * to this function when the hook was registered. 3194 * 3195 * Note that if a pre-change hook is called, any registered post-change hooks 3196 * are guaranteed to subsequently be called. 3197 */ 3198 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3199 void *opaque); 3200 /** 3201 * arm_register_el_change_hook: 3202 * Register a hook function which will be called immediately after this 3203 * CPU changes exception level or mode. The hook function will be 3204 * passed a pointer to the ARMCPU and the opaque data pointer passed 3205 * to this function when the hook was registered. 3206 * 3207 * Note that any registered hooks registered here are guaranteed to be called 3208 * if pre-change hooks have been. 3209 */ 3210 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3211 *opaque); 3212 3213 /** 3214 * aa32_vfp_dreg: 3215 * Return a pointer to the Dn register within env in 32-bit mode. 3216 */ 3217 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3218 { 3219 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3220 } 3221 3222 /** 3223 * aa32_vfp_qreg: 3224 * Return a pointer to the Qn register within env in 32-bit mode. 3225 */ 3226 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3227 { 3228 return &env->vfp.zregs[regno].d[0]; 3229 } 3230 3231 /** 3232 * aa64_vfp_qreg: 3233 * Return a pointer to the Qn register within env in 64-bit mode. 3234 */ 3235 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3236 { 3237 return &env->vfp.zregs[regno].d[0]; 3238 } 3239 3240 /* Shared between translate-sve.c and sve_helper.c. */ 3241 extern const uint64_t pred_esz_masks[4]; 3242 3243 /* 3244 * 32-bit feature tests via id registers. 3245 */ 3246 static inline bool isar_feature_thumb_div(const ARMISARegisters *id) 3247 { 3248 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3249 } 3250 3251 static inline bool isar_feature_arm_div(const ARMISARegisters *id) 3252 { 3253 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3254 } 3255 3256 static inline bool isar_feature_jazelle(const ARMISARegisters *id) 3257 { 3258 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3259 } 3260 3261 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3262 { 3263 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3264 } 3265 3266 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3267 { 3268 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3269 } 3270 3271 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3272 { 3273 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3274 } 3275 3276 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3277 { 3278 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3279 } 3280 3281 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3282 { 3283 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3284 } 3285 3286 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3287 { 3288 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3289 } 3290 3291 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3292 { 3293 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3294 } 3295 3296 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3297 { 3298 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3299 } 3300 3301 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3302 { 3303 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3304 } 3305 3306 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3307 { 3308 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3309 } 3310 3311 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3312 { 3313 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3314 } 3315 3316 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3317 { 3318 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3319 } 3320 3321 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3322 { 3323 /* 3324 * This is a placeholder for use by VCMA until the rest of 3325 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3326 * At which point we can properly set and check MVFR1.FPHP. 3327 */ 3328 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3329 } 3330 3331 /* 3332 * We always set the FP and SIMD FP16 fields to indicate identical 3333 * levels of support (assuming SIMD is implemented at all), so 3334 * we only need one set of accessors. 3335 */ 3336 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3337 { 3338 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0; 3339 } 3340 3341 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3342 { 3343 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; 3344 } 3345 3346 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3347 { 3348 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1; 3349 } 3350 3351 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3352 { 3353 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2; 3354 } 3355 3356 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3357 { 3358 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3; 3359 } 3360 3361 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3362 { 3363 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; 3364 } 3365 3366 /* 3367 * 64-bit feature tests via id registers. 3368 */ 3369 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3370 { 3371 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3372 } 3373 3374 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3375 { 3376 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3377 } 3378 3379 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3380 { 3381 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3382 } 3383 3384 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3385 { 3386 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3387 } 3388 3389 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3390 { 3391 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3392 } 3393 3394 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3395 { 3396 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3397 } 3398 3399 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3400 { 3401 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3402 } 3403 3404 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3405 { 3406 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3407 } 3408 3409 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3410 { 3411 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3412 } 3413 3414 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3415 { 3416 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3417 } 3418 3419 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3420 { 3421 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3422 } 3423 3424 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3425 { 3426 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3427 } 3428 3429 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3430 { 3431 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3432 } 3433 3434 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3435 { 3436 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3437 } 3438 3439 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3440 { 3441 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3442 } 3443 3444 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3445 { 3446 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3447 } 3448 3449 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3450 { 3451 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3452 } 3453 3454 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3455 { 3456 /* 3457 * Note that while QEMU will only implement the architected algorithm 3458 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation 3459 * defined algorithms, and thus API+GPI, and this predicate controls 3460 * migration of the 128-bit keys. 3461 */ 3462 return (id->id_aa64isar1 & 3463 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3464 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3465 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3466 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3467 } 3468 3469 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3470 { 3471 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3472 } 3473 3474 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3475 { 3476 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3477 } 3478 3479 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3480 { 3481 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3482 } 3483 3484 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3485 { 3486 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3487 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3488 } 3489 3490 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3491 { 3492 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3493 } 3494 3495 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3496 { 3497 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3498 } 3499 3500 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3501 { 3502 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3503 } 3504 3505 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3506 { 3507 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3508 } 3509 3510 /* 3511 * Forward to the above feature tests given an ARMCPU pointer. 3512 */ 3513 #define cpu_isar_feature(name, cpu) \ 3514 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3515 3516 #endif 3517