1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 #include "cpu-qom.h" 26 #include "exec/cpu-defs.h" 27 #include "qapi/qapi-types-common.h" 28 29 /* ARM processors have a weak memory model */ 30 #define TCG_GUEST_DEFAULT_MO (0) 31 32 #ifdef TARGET_AARCH64 33 #define KVM_HAVE_MCE_INJECTION 1 34 #endif 35 36 #define EXCP_UDEF 1 /* undefined instruction */ 37 #define EXCP_SWI 2 /* software interrupt */ 38 #define EXCP_PREFETCH_ABORT 3 39 #define EXCP_DATA_ABORT 4 40 #define EXCP_IRQ 5 41 #define EXCP_FIQ 6 42 #define EXCP_BKPT 7 43 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 44 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 45 #define EXCP_HVC 11 /* HyperVisor Call */ 46 #define EXCP_HYP_TRAP 12 47 #define EXCP_SMC 13 /* Secure Monitor Call */ 48 #define EXCP_VIRQ 14 49 #define EXCP_VFIQ 15 50 #define EXCP_SEMIHOST 16 /* semihosting call */ 51 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 52 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 53 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 54 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 55 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 56 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 57 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 58 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 59 60 #define ARMV7M_EXCP_RESET 1 61 #define ARMV7M_EXCP_NMI 2 62 #define ARMV7M_EXCP_HARD 3 63 #define ARMV7M_EXCP_MEM 4 64 #define ARMV7M_EXCP_BUS 5 65 #define ARMV7M_EXCP_USAGE 6 66 #define ARMV7M_EXCP_SECURE 7 67 #define ARMV7M_EXCP_SVC 11 68 #define ARMV7M_EXCP_DEBUG 12 69 #define ARMV7M_EXCP_PENDSV 14 70 #define ARMV7M_EXCP_SYSTICK 15 71 72 /* For M profile, some registers are banked secure vs non-secure; 73 * these are represented as a 2-element array where the first element 74 * is the non-secure copy and the second is the secure copy. 75 * When the CPU does not have implement the security extension then 76 * only the first element is used. 77 * This means that the copy for the current security state can be 78 * accessed via env->registerfield[env->v7m.secure] (whether the security 79 * extension is implemented or not). 80 */ 81 enum { 82 M_REG_NS = 0, 83 M_REG_S = 1, 84 M_REG_NUM_BANKS = 2, 85 }; 86 87 /* ARM-specific interrupt pending bits. */ 88 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 89 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 90 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 91 92 /* The usual mapping for an AArch64 system register to its AArch32 93 * counterpart is for the 32 bit world to have access to the lower 94 * half only (with writes leaving the upper half untouched). It's 95 * therefore useful to be able to pass TCG the offset of the least 96 * significant half of a uint64_t struct member. 97 */ 98 #ifdef HOST_WORDS_BIGENDIAN 99 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 100 #define offsetofhigh32(S, M) offsetof(S, M) 101 #else 102 #define offsetoflow32(S, M) offsetof(S, M) 103 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 104 #endif 105 106 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 107 #define ARM_CPU_IRQ 0 108 #define ARM_CPU_FIQ 1 109 #define ARM_CPU_VIRQ 2 110 #define ARM_CPU_VFIQ 3 111 112 /* ARM-specific extra insn start words: 113 * 1: Conditional execution bits 114 * 2: Partial exception syndrome for data aborts 115 */ 116 #define TARGET_INSN_START_EXTRA_WORDS 2 117 118 /* The 2nd extra word holding syndrome info for data aborts does not use 119 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 120 * help the sleb128 encoder do a better job. 121 * When restoring the CPU state, we shift it back up. 122 */ 123 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 124 #define ARM_INSN_START_WORD2_SHIFT 14 125 126 /* We currently assume float and double are IEEE single and double 127 precision respectively. 128 Doing runtime conversions is tricky because VFP registers may contain 129 integer values (eg. as the result of a FTOSI instruction). 130 s<2n> maps to the least significant half of d<n> 131 s<2n+1> maps to the most significant half of d<n> 132 */ 133 134 /** 135 * DynamicGDBXMLInfo: 136 * @desc: Contains the XML descriptions. 137 * @num: Number of the registers in this XML seen by GDB. 138 * @data: A union with data specific to the set of registers 139 * @cpregs_keys: Array that contains the corresponding Key of 140 * a given cpreg with the same order of the cpreg 141 * in the XML description. 142 */ 143 typedef struct DynamicGDBXMLInfo { 144 char *desc; 145 int num; 146 union { 147 struct { 148 uint32_t *keys; 149 } cpregs; 150 } data; 151 } DynamicGDBXMLInfo; 152 153 /* CPU state for each instance of a generic timer (in cp15 c14) */ 154 typedef struct ARMGenericTimer { 155 uint64_t cval; /* Timer CompareValue register */ 156 uint64_t ctl; /* Timer Control register */ 157 } ARMGenericTimer; 158 159 #define GTIMER_PHYS 0 160 #define GTIMER_VIRT 1 161 #define GTIMER_HYP 2 162 #define GTIMER_SEC 3 163 #define GTIMER_HYPVIRT 4 164 #define NUM_GTIMERS 5 165 166 typedef struct { 167 uint64_t raw_tcr; 168 uint32_t mask; 169 uint32_t base_mask; 170 } TCR; 171 172 #define VTCR_NSW (1u << 29) 173 #define VTCR_NSA (1u << 30) 174 #define VSTCR_SW VTCR_NSW 175 #define VSTCR_SA VTCR_NSA 176 177 /* Define a maximum sized vector register. 178 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 179 * For 64-bit, this is a 2048-bit SVE register. 180 * 181 * Note that the mapping between S, D, and Q views of the register bank 182 * differs between AArch64 and AArch32. 183 * In AArch32: 184 * Qn = regs[n].d[1]:regs[n].d[0] 185 * Dn = regs[n / 2].d[n & 1] 186 * Sn = regs[n / 4].d[n % 4 / 2], 187 * bits 31..0 for even n, and bits 63..32 for odd n 188 * (and regs[16] to regs[31] are inaccessible) 189 * In AArch64: 190 * Zn = regs[n].d[*] 191 * Qn = regs[n].d[1]:regs[n].d[0] 192 * Dn = regs[n].d[0] 193 * Sn = regs[n].d[0] bits 31..0 194 * Hn = regs[n].d[0] bits 15..0 195 * 196 * This corresponds to the architecturally defined mapping between 197 * the two execution states, and means we do not need to explicitly 198 * map these registers when changing states. 199 * 200 * Align the data for use with TCG host vector operations. 201 */ 202 203 #ifdef TARGET_AARCH64 204 # define ARM_MAX_VQ 16 205 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 206 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); 207 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); 208 #else 209 # define ARM_MAX_VQ 1 210 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 211 static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } 212 static inline void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { } 213 #endif 214 215 typedef struct ARMVectorReg { 216 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 217 } ARMVectorReg; 218 219 #ifdef TARGET_AARCH64 220 /* In AArch32 mode, predicate registers do not exist at all. */ 221 typedef struct ARMPredicateReg { 222 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 223 } ARMPredicateReg; 224 225 /* In AArch32 mode, PAC keys do not exist at all. */ 226 typedef struct ARMPACKey { 227 uint64_t lo, hi; 228 } ARMPACKey; 229 #endif 230 231 /* See the commentary above the TBFLAG field definitions. */ 232 typedef struct CPUARMTBFlags { 233 uint32_t flags; 234 target_ulong flags2; 235 } CPUARMTBFlags; 236 237 typedef struct CPUArchState { 238 /* Regs for current mode. */ 239 uint32_t regs[16]; 240 241 /* 32/64 switch only happens when taking and returning from 242 * exceptions so the overlap semantics are taken care of then 243 * instead of having a complicated union. 244 */ 245 /* Regs for A64 mode. */ 246 uint64_t xregs[32]; 247 uint64_t pc; 248 /* PSTATE isn't an architectural register for ARMv8. However, it is 249 * convenient for us to assemble the underlying state into a 32 bit format 250 * identical to the architectural format used for the SPSR. (This is also 251 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 252 * 'pstate' register are.) Of the PSTATE bits: 253 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 254 * semantics as for AArch32, as described in the comments on each field) 255 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 256 * DAIF (exception masks) are kept in env->daif 257 * BTYPE is kept in env->btype 258 * all other bits are stored in their correct places in env->pstate 259 */ 260 uint32_t pstate; 261 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 262 263 /* Cached TBFLAGS state. See below for which bits are included. */ 264 CPUARMTBFlags hflags; 265 266 /* Frequently accessed CPSR bits are stored separately for efficiency. 267 This contains all the other bits. Use cpsr_{read,write} to access 268 the whole CPSR. */ 269 uint32_t uncached_cpsr; 270 uint32_t spsr; 271 272 /* Banked registers. */ 273 uint64_t banked_spsr[8]; 274 uint32_t banked_r13[8]; 275 uint32_t banked_r14[8]; 276 277 /* These hold r8-r12. */ 278 uint32_t usr_regs[5]; 279 uint32_t fiq_regs[5]; 280 281 /* cpsr flag cache for faster execution */ 282 uint32_t CF; /* 0 or 1 */ 283 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 284 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 285 uint32_t ZF; /* Z set if zero. */ 286 uint32_t QF; /* 0 or 1 */ 287 uint32_t GE; /* cpsr[19:16] */ 288 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 289 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 290 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 291 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 292 293 uint64_t elr_el[4]; /* AArch64 exception link regs */ 294 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 295 296 /* System control coprocessor (cp15) */ 297 struct { 298 uint32_t c0_cpuid; 299 union { /* Cache size selection */ 300 struct { 301 uint64_t _unused_csselr0; 302 uint64_t csselr_ns; 303 uint64_t _unused_csselr1; 304 uint64_t csselr_s; 305 }; 306 uint64_t csselr_el[4]; 307 }; 308 union { /* System control register. */ 309 struct { 310 uint64_t _unused_sctlr; 311 uint64_t sctlr_ns; 312 uint64_t hsctlr; 313 uint64_t sctlr_s; 314 }; 315 uint64_t sctlr_el[4]; 316 }; 317 uint64_t cpacr_el1; /* Architectural feature access control register */ 318 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 319 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 320 uint64_t sder; /* Secure debug enable register. */ 321 uint32_t nsacr; /* Non-secure access control register. */ 322 union { /* MMU translation table base 0. */ 323 struct { 324 uint64_t _unused_ttbr0_0; 325 uint64_t ttbr0_ns; 326 uint64_t _unused_ttbr0_1; 327 uint64_t ttbr0_s; 328 }; 329 uint64_t ttbr0_el[4]; 330 }; 331 union { /* MMU translation table base 1. */ 332 struct { 333 uint64_t _unused_ttbr1_0; 334 uint64_t ttbr1_ns; 335 uint64_t _unused_ttbr1_1; 336 uint64_t ttbr1_s; 337 }; 338 uint64_t ttbr1_el[4]; 339 }; 340 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 341 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 342 /* MMU translation table base control. */ 343 TCR tcr_el[4]; 344 TCR vtcr_el2; /* Virtualization Translation Control. */ 345 TCR vstcr_el2; /* Secure Virtualization Translation Control. */ 346 uint32_t c2_data; /* MPU data cacheable bits. */ 347 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 348 union { /* MMU domain access control register 349 * MPU write buffer control. 350 */ 351 struct { 352 uint64_t dacr_ns; 353 uint64_t dacr_s; 354 }; 355 struct { 356 uint64_t dacr32_el2; 357 }; 358 }; 359 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 360 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 361 uint64_t hcr_el2; /* Hypervisor configuration register */ 362 uint64_t scr_el3; /* Secure configuration register. */ 363 union { /* Fault status registers. */ 364 struct { 365 uint64_t ifsr_ns; 366 uint64_t ifsr_s; 367 }; 368 struct { 369 uint64_t ifsr32_el2; 370 }; 371 }; 372 union { 373 struct { 374 uint64_t _unused_dfsr; 375 uint64_t dfsr_ns; 376 uint64_t hsr; 377 uint64_t dfsr_s; 378 }; 379 uint64_t esr_el[4]; 380 }; 381 uint32_t c6_region[8]; /* MPU base/size registers. */ 382 union { /* Fault address registers. */ 383 struct { 384 uint64_t _unused_far0; 385 #ifdef HOST_WORDS_BIGENDIAN 386 uint32_t ifar_ns; 387 uint32_t dfar_ns; 388 uint32_t ifar_s; 389 uint32_t dfar_s; 390 #else 391 uint32_t dfar_ns; 392 uint32_t ifar_ns; 393 uint32_t dfar_s; 394 uint32_t ifar_s; 395 #endif 396 uint64_t _unused_far3; 397 }; 398 uint64_t far_el[4]; 399 }; 400 uint64_t hpfar_el2; 401 uint64_t hstr_el2; 402 union { /* Translation result. */ 403 struct { 404 uint64_t _unused_par_0; 405 uint64_t par_ns; 406 uint64_t _unused_par_1; 407 uint64_t par_s; 408 }; 409 uint64_t par_el[4]; 410 }; 411 412 uint32_t c9_insn; /* Cache lockdown registers. */ 413 uint32_t c9_data; 414 uint64_t c9_pmcr; /* performance monitor control register */ 415 uint64_t c9_pmcnten; /* perf monitor counter enables */ 416 uint64_t c9_pmovsr; /* perf monitor overflow status */ 417 uint64_t c9_pmuserenr; /* perf monitor user enable */ 418 uint64_t c9_pmselr; /* perf monitor counter selection register */ 419 uint64_t c9_pminten; /* perf monitor interrupt enables */ 420 union { /* Memory attribute redirection */ 421 struct { 422 #ifdef HOST_WORDS_BIGENDIAN 423 uint64_t _unused_mair_0; 424 uint32_t mair1_ns; 425 uint32_t mair0_ns; 426 uint64_t _unused_mair_1; 427 uint32_t mair1_s; 428 uint32_t mair0_s; 429 #else 430 uint64_t _unused_mair_0; 431 uint32_t mair0_ns; 432 uint32_t mair1_ns; 433 uint64_t _unused_mair_1; 434 uint32_t mair0_s; 435 uint32_t mair1_s; 436 #endif 437 }; 438 uint64_t mair_el[4]; 439 }; 440 union { /* vector base address register */ 441 struct { 442 uint64_t _unused_vbar; 443 uint64_t vbar_ns; 444 uint64_t hvbar; 445 uint64_t vbar_s; 446 }; 447 uint64_t vbar_el[4]; 448 }; 449 uint32_t mvbar; /* (monitor) vector base address register */ 450 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 451 struct { /* FCSE PID. */ 452 uint32_t fcseidr_ns; 453 uint32_t fcseidr_s; 454 }; 455 union { /* Context ID. */ 456 struct { 457 uint64_t _unused_contextidr_0; 458 uint64_t contextidr_ns; 459 uint64_t _unused_contextidr_1; 460 uint64_t contextidr_s; 461 }; 462 uint64_t contextidr_el[4]; 463 }; 464 union { /* User RW Thread register. */ 465 struct { 466 uint64_t tpidrurw_ns; 467 uint64_t tpidrprw_ns; 468 uint64_t htpidr; 469 uint64_t _tpidr_el3; 470 }; 471 uint64_t tpidr_el[4]; 472 }; 473 /* The secure banks of these registers don't map anywhere */ 474 uint64_t tpidrurw_s; 475 uint64_t tpidrprw_s; 476 uint64_t tpidruro_s; 477 478 union { /* User RO Thread register. */ 479 uint64_t tpidruro_ns; 480 uint64_t tpidrro_el[1]; 481 }; 482 uint64_t c14_cntfrq; /* Counter Frequency register */ 483 uint64_t c14_cntkctl; /* Timer Control register */ 484 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 485 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 486 ARMGenericTimer c14_timer[NUM_GTIMERS]; 487 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 488 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 489 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 490 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 491 uint32_t c15_threadid; /* TI debugger thread-ID. */ 492 uint32_t c15_config_base_address; /* SCU base address. */ 493 uint32_t c15_diagnostic; /* diagnostic register */ 494 uint32_t c15_power_diagnostic; 495 uint32_t c15_power_control; /* power control */ 496 uint64_t dbgbvr[16]; /* breakpoint value registers */ 497 uint64_t dbgbcr[16]; /* breakpoint control registers */ 498 uint64_t dbgwvr[16]; /* watchpoint value registers */ 499 uint64_t dbgwcr[16]; /* watchpoint control registers */ 500 uint64_t mdscr_el1; 501 uint64_t oslsr_el1; /* OS Lock Status */ 502 uint64_t mdcr_el2; 503 uint64_t mdcr_el3; 504 /* Stores the architectural value of the counter *the last time it was 505 * updated* by pmccntr_op_start. Accesses should always be surrounded 506 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 507 * architecturally-correct value is being read/set. 508 */ 509 uint64_t c15_ccnt; 510 /* Stores the delta between the architectural value and the underlying 511 * cycle count during normal operation. It is used to update c15_ccnt 512 * to be the correct architectural value before accesses. During 513 * accesses, c15_ccnt_delta contains the underlying count being used 514 * for the access, after which it reverts to the delta value in 515 * pmccntr_op_finish. 516 */ 517 uint64_t c15_ccnt_delta; 518 uint64_t c14_pmevcntr[31]; 519 uint64_t c14_pmevcntr_delta[31]; 520 uint64_t c14_pmevtyper[31]; 521 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 522 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 523 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 524 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 525 uint64_t gcr_el1; 526 uint64_t rgsr_el1; 527 } cp15; 528 529 struct { 530 /* M profile has up to 4 stack pointers: 531 * a Main Stack Pointer and a Process Stack Pointer for each 532 * of the Secure and Non-Secure states. (If the CPU doesn't support 533 * the security extension then it has only two SPs.) 534 * In QEMU we always store the currently active SP in regs[13], 535 * and the non-active SP for the current security state in 536 * v7m.other_sp. The stack pointers for the inactive security state 537 * are stored in other_ss_msp and other_ss_psp. 538 * switch_v7m_security_state() is responsible for rearranging them 539 * when we change security state. 540 */ 541 uint32_t other_sp; 542 uint32_t other_ss_msp; 543 uint32_t other_ss_psp; 544 uint32_t vecbase[M_REG_NUM_BANKS]; 545 uint32_t basepri[M_REG_NUM_BANKS]; 546 uint32_t control[M_REG_NUM_BANKS]; 547 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 548 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 549 uint32_t hfsr; /* HardFault Status */ 550 uint32_t dfsr; /* Debug Fault Status Register */ 551 uint32_t sfsr; /* Secure Fault Status Register */ 552 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 553 uint32_t bfar; /* BusFault Address */ 554 uint32_t sfar; /* Secure Fault Address Register */ 555 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 556 int exception; 557 uint32_t primask[M_REG_NUM_BANKS]; 558 uint32_t faultmask[M_REG_NUM_BANKS]; 559 uint32_t aircr; /* only holds r/w state if security extn implemented */ 560 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 561 uint32_t csselr[M_REG_NUM_BANKS]; 562 uint32_t scr[M_REG_NUM_BANKS]; 563 uint32_t msplim[M_REG_NUM_BANKS]; 564 uint32_t psplim[M_REG_NUM_BANKS]; 565 uint32_t fpcar[M_REG_NUM_BANKS]; 566 uint32_t fpccr[M_REG_NUM_BANKS]; 567 uint32_t fpdscr[M_REG_NUM_BANKS]; 568 uint32_t cpacr[M_REG_NUM_BANKS]; 569 uint32_t nsacr; 570 uint32_t ltpsize; 571 uint32_t vpr; 572 } v7m; 573 574 /* Information associated with an exception about to be taken: 575 * code which raises an exception must set cs->exception_index and 576 * the relevant parts of this structure; the cpu_do_interrupt function 577 * will then set the guest-visible registers as part of the exception 578 * entry process. 579 */ 580 struct { 581 uint32_t syndrome; /* AArch64 format syndrome register */ 582 uint32_t fsr; /* AArch32 format fault status register info */ 583 uint64_t vaddress; /* virtual addr associated with exception, if any */ 584 uint32_t target_el; /* EL the exception should be targeted for */ 585 /* If we implement EL2 we will also need to store information 586 * about the intermediate physical address for stage 2 faults. 587 */ 588 } exception; 589 590 /* Information associated with an SError */ 591 struct { 592 uint8_t pending; 593 uint8_t has_esr; 594 uint64_t esr; 595 } serror; 596 597 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 598 599 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 600 uint32_t irq_line_state; 601 602 /* Thumb-2 EE state. */ 603 uint32_t teecr; 604 uint32_t teehbr; 605 606 /* VFP coprocessor state. */ 607 struct { 608 ARMVectorReg zregs[32]; 609 610 #ifdef TARGET_AARCH64 611 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 612 #define FFR_PRED_NUM 16 613 ARMPredicateReg pregs[17]; 614 /* Scratch space for aa64 sve predicate temporary. */ 615 ARMPredicateReg preg_tmp; 616 #endif 617 618 /* We store these fpcsr fields separately for convenience. */ 619 uint32_t qc[4] QEMU_ALIGNED(16); 620 int vec_len; 621 int vec_stride; 622 623 uint32_t xregs[16]; 624 625 /* Scratch space for aa32 neon expansion. */ 626 uint32_t scratch[8]; 627 628 /* There are a number of distinct float control structures: 629 * 630 * fp_status: is the "normal" fp status. 631 * fp_status_fp16: used for half-precision calculations 632 * standard_fp_status : the ARM "Standard FPSCR Value" 633 * standard_fp_status_fp16 : used for half-precision 634 * calculations with the ARM "Standard FPSCR Value" 635 * 636 * Half-precision operations are governed by a separate 637 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 638 * status structure to control this. 639 * 640 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 641 * round-to-nearest and is used by any operations (generally 642 * Neon) which the architecture defines as controlled by the 643 * standard FPSCR value rather than the FPSCR. 644 * 645 * The "standard FPSCR but for fp16 ops" is needed because 646 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 647 * using a fixed value for it. 648 * 649 * To avoid having to transfer exception bits around, we simply 650 * say that the FPSCR cumulative exception flags are the logical 651 * OR of the flags in the four fp statuses. This relies on the 652 * only thing which needs to read the exception flags being 653 * an explicit FPSCR read. 654 */ 655 float_status fp_status; 656 float_status fp_status_f16; 657 float_status standard_fp_status; 658 float_status standard_fp_status_f16; 659 660 /* ZCR_EL[1-3] */ 661 uint64_t zcr_el[4]; 662 } vfp; 663 uint64_t exclusive_addr; 664 uint64_t exclusive_val; 665 uint64_t exclusive_high; 666 667 /* iwMMXt coprocessor state. */ 668 struct { 669 uint64_t regs[16]; 670 uint64_t val; 671 672 uint32_t cregs[16]; 673 } iwmmxt; 674 675 #ifdef TARGET_AARCH64 676 struct { 677 ARMPACKey apia; 678 ARMPACKey apib; 679 ARMPACKey apda; 680 ARMPACKey apdb; 681 ARMPACKey apga; 682 } keys; 683 #endif 684 685 #if defined(CONFIG_USER_ONLY) 686 /* For usermode syscall translation. */ 687 int eabi; 688 #endif 689 690 struct CPUBreakpoint *cpu_breakpoint[16]; 691 struct CPUWatchpoint *cpu_watchpoint[16]; 692 693 /* Fields up to this point are cleared by a CPU reset */ 694 struct {} end_reset_fields; 695 696 /* Fields after this point are preserved across CPU reset. */ 697 698 /* Internal CPU feature flags. */ 699 uint64_t features; 700 701 /* PMSAv7 MPU */ 702 struct { 703 uint32_t *drbar; 704 uint32_t *drsr; 705 uint32_t *dracr; 706 uint32_t rnr[M_REG_NUM_BANKS]; 707 } pmsav7; 708 709 /* PMSAv8 MPU */ 710 struct { 711 /* The PMSAv8 implementation also shares some PMSAv7 config 712 * and state: 713 * pmsav7.rnr (region number register) 714 * pmsav7_dregion (number of configured regions) 715 */ 716 uint32_t *rbar[M_REG_NUM_BANKS]; 717 uint32_t *rlar[M_REG_NUM_BANKS]; 718 uint32_t mair0[M_REG_NUM_BANKS]; 719 uint32_t mair1[M_REG_NUM_BANKS]; 720 } pmsav8; 721 722 /* v8M SAU */ 723 struct { 724 uint32_t *rbar; 725 uint32_t *rlar; 726 uint32_t rnr; 727 uint32_t ctrl; 728 } sau; 729 730 void *nvic; 731 const struct arm_boot_info *boot_info; 732 /* Store GICv3CPUState to access from this struct */ 733 void *gicv3state; 734 735 #ifdef TARGET_TAGGED_ADDRESSES 736 /* Linux syscall tagged address support */ 737 bool tagged_addr_enable; 738 #endif 739 } CPUARMState; 740 741 static inline void set_feature(CPUARMState *env, int feature) 742 { 743 env->features |= 1ULL << feature; 744 } 745 746 static inline void unset_feature(CPUARMState *env, int feature) 747 { 748 env->features &= ~(1ULL << feature); 749 } 750 751 /** 752 * ARMELChangeHookFn: 753 * type of a function which can be registered via arm_register_el_change_hook() 754 * to get callbacks when the CPU changes its exception level or mode. 755 */ 756 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 757 typedef struct ARMELChangeHook ARMELChangeHook; 758 struct ARMELChangeHook { 759 ARMELChangeHookFn *hook; 760 void *opaque; 761 QLIST_ENTRY(ARMELChangeHook) node; 762 }; 763 764 /* These values map onto the return values for 765 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 766 typedef enum ARMPSCIState { 767 PSCI_ON = 0, 768 PSCI_OFF = 1, 769 PSCI_ON_PENDING = 2 770 } ARMPSCIState; 771 772 typedef struct ARMISARegisters ARMISARegisters; 773 774 /** 775 * ARMCPU: 776 * @env: #CPUARMState 777 * 778 * An ARM CPU core. 779 */ 780 struct ArchCPU { 781 /*< private >*/ 782 CPUState parent_obj; 783 /*< public >*/ 784 785 CPUNegativeOffsetState neg; 786 CPUARMState env; 787 788 /* Coprocessor information */ 789 GHashTable *cp_regs; 790 /* For marshalling (mostly coprocessor) register state between the 791 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 792 * we use these arrays. 793 */ 794 /* List of register indexes managed via these arrays; (full KVM style 795 * 64 bit indexes, not CPRegInfo 32 bit indexes) 796 */ 797 uint64_t *cpreg_indexes; 798 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 799 uint64_t *cpreg_values; 800 /* Length of the indexes, values, reset_values arrays */ 801 int32_t cpreg_array_len; 802 /* These are used only for migration: incoming data arrives in 803 * these fields and is sanity checked in post_load before copying 804 * to the working data structures above. 805 */ 806 uint64_t *cpreg_vmstate_indexes; 807 uint64_t *cpreg_vmstate_values; 808 int32_t cpreg_vmstate_array_len; 809 810 DynamicGDBXMLInfo dyn_sysreg_xml; 811 DynamicGDBXMLInfo dyn_svereg_xml; 812 813 /* Timers used by the generic (architected) timer */ 814 QEMUTimer *gt_timer[NUM_GTIMERS]; 815 /* 816 * Timer used by the PMU. Its state is restored after migration by 817 * pmu_op_finish() - it does not need other handling during migration 818 */ 819 QEMUTimer *pmu_timer; 820 /* GPIO outputs for generic timer */ 821 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 822 /* GPIO output for GICv3 maintenance interrupt signal */ 823 qemu_irq gicv3_maintenance_interrupt; 824 /* GPIO output for the PMU interrupt */ 825 qemu_irq pmu_interrupt; 826 827 /* MemoryRegion to use for secure physical accesses */ 828 MemoryRegion *secure_memory; 829 830 /* MemoryRegion to use for allocation tag accesses */ 831 MemoryRegion *tag_memory; 832 MemoryRegion *secure_tag_memory; 833 834 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 835 Object *idau; 836 837 /* 'compatible' string for this CPU for Linux device trees */ 838 const char *dtb_compatible; 839 840 /* PSCI version for this CPU 841 * Bits[31:16] = Major Version 842 * Bits[15:0] = Minor Version 843 */ 844 uint32_t psci_version; 845 846 /* Current power state, access guarded by BQL */ 847 ARMPSCIState power_state; 848 849 /* CPU has virtualization extension */ 850 bool has_el2; 851 /* CPU has security extension */ 852 bool has_el3; 853 /* CPU has PMU (Performance Monitor Unit) */ 854 bool has_pmu; 855 /* CPU has VFP */ 856 bool has_vfp; 857 /* CPU has Neon */ 858 bool has_neon; 859 /* CPU has M-profile DSP extension */ 860 bool has_dsp; 861 862 /* CPU has memory protection unit */ 863 bool has_mpu; 864 /* PMSAv7 MPU number of supported regions */ 865 uint32_t pmsav7_dregion; 866 /* v8M SAU number of supported regions */ 867 uint32_t sau_sregion; 868 869 /* PSCI conduit used to invoke PSCI methods 870 * 0 - disabled, 1 - smc, 2 - hvc 871 */ 872 uint32_t psci_conduit; 873 874 /* For v8M, initial value of the Secure VTOR */ 875 uint32_t init_svtor; 876 /* For v8M, initial value of the Non-secure VTOR */ 877 uint32_t init_nsvtor; 878 879 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 880 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 881 */ 882 uint32_t kvm_target; 883 884 /* KVM init features for this CPU */ 885 uint32_t kvm_init_features[7]; 886 887 /* KVM CPU state */ 888 889 /* KVM virtual time adjustment */ 890 bool kvm_adjvtime; 891 bool kvm_vtime_dirty; 892 uint64_t kvm_vtime; 893 894 /* KVM steal time */ 895 OnOffAuto kvm_steal_time; 896 897 /* Uniprocessor system with MP extensions */ 898 bool mp_is_up; 899 900 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 901 * and the probe failed (so we need to report the error in realize) 902 */ 903 bool host_cpu_probe_failed; 904 905 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 906 * register. 907 */ 908 int32_t core_count; 909 910 /* The instance init functions for implementation-specific subclasses 911 * set these fields to specify the implementation-dependent values of 912 * various constant registers and reset values of non-constant 913 * registers. 914 * Some of these might become QOM properties eventually. 915 * Field names match the official register names as defined in the 916 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 917 * is used for reset values of non-constant registers; no reset_ 918 * prefix means a constant register. 919 * Some of these registers are split out into a substructure that 920 * is shared with the translators to control the ISA. 921 * 922 * Note that if you add an ID register to the ARMISARegisters struct 923 * you need to also update the 32-bit and 64-bit versions of the 924 * kvm_arm_get_host_cpu_features() function to correctly populate the 925 * field by reading the value from the KVM vCPU. 926 */ 927 struct ARMISARegisters { 928 uint32_t id_isar0; 929 uint32_t id_isar1; 930 uint32_t id_isar2; 931 uint32_t id_isar3; 932 uint32_t id_isar4; 933 uint32_t id_isar5; 934 uint32_t id_isar6; 935 uint32_t id_mmfr0; 936 uint32_t id_mmfr1; 937 uint32_t id_mmfr2; 938 uint32_t id_mmfr3; 939 uint32_t id_mmfr4; 940 uint32_t id_pfr0; 941 uint32_t id_pfr1; 942 uint32_t id_pfr2; 943 uint32_t mvfr0; 944 uint32_t mvfr1; 945 uint32_t mvfr2; 946 uint32_t id_dfr0; 947 uint32_t dbgdidr; 948 uint64_t id_aa64isar0; 949 uint64_t id_aa64isar1; 950 uint64_t id_aa64pfr0; 951 uint64_t id_aa64pfr1; 952 uint64_t id_aa64mmfr0; 953 uint64_t id_aa64mmfr1; 954 uint64_t id_aa64mmfr2; 955 uint64_t id_aa64dfr0; 956 uint64_t id_aa64dfr1; 957 uint64_t id_aa64zfr0; 958 } isar; 959 uint64_t midr; 960 uint32_t revidr; 961 uint32_t reset_fpsid; 962 uint64_t ctr; 963 uint32_t reset_sctlr; 964 uint64_t pmceid0; 965 uint64_t pmceid1; 966 uint32_t id_afr0; 967 uint64_t id_aa64afr0; 968 uint64_t id_aa64afr1; 969 uint64_t clidr; 970 uint64_t mp_affinity; /* MP ID without feature bits */ 971 /* The elements of this array are the CCSIDR values for each cache, 972 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 973 */ 974 uint64_t ccsidr[16]; 975 uint64_t reset_cbar; 976 uint32_t reset_auxcr; 977 bool reset_hivecs; 978 979 /* 980 * Intermediate values used during property parsing. 981 * Once finalized, the values should be read from ID_AA64*. 982 */ 983 bool prop_pauth; 984 bool prop_pauth_impdef; 985 bool prop_lpa2; 986 987 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 988 uint32_t dcz_blocksize; 989 uint64_t rvbar_prop; /* Property/input signals. */ 990 991 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 992 int gic_num_lrs; /* number of list registers */ 993 int gic_vpribits; /* number of virtual priority bits */ 994 int gic_vprebits; /* number of virtual preemption bits */ 995 996 /* Whether the cfgend input is high (i.e. this CPU should reset into 997 * big-endian mode). This setting isn't used directly: instead it modifies 998 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 999 * architecture version. 1000 */ 1001 bool cfgend; 1002 1003 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1004 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1005 1006 int32_t node_id; /* NUMA node this CPU belongs to */ 1007 1008 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1009 uint8_t device_irq_level; 1010 1011 /* Used to set the maximum vector length the cpu will support. */ 1012 uint32_t sve_max_vq; 1013 1014 #ifdef CONFIG_USER_ONLY 1015 /* Used to set the default vector length at process start. */ 1016 uint32_t sve_default_vq; 1017 #endif 1018 1019 /* 1020 * In sve_vq_map each set bit is a supported vector length of 1021 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 1022 * length in quadwords. 1023 * 1024 * While processing properties during initialization, corresponding 1025 * sve_vq_init bits are set for bits in sve_vq_map that have been 1026 * set by properties. 1027 * 1028 * Bits set in sve_vq_supported represent valid vector lengths for 1029 * the CPU type. 1030 */ 1031 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 1032 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 1033 DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ); 1034 1035 /* Generic timer counter frequency, in Hz */ 1036 uint64_t gt_cntfrq_hz; 1037 }; 1038 1039 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1040 1041 void arm_cpu_post_init(Object *obj); 1042 1043 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1044 1045 #ifndef CONFIG_USER_ONLY 1046 extern const VMStateDescription vmstate_arm_cpu; 1047 1048 void arm_cpu_do_interrupt(CPUState *cpu); 1049 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1050 #endif /* !CONFIG_USER_ONLY */ 1051 1052 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1053 MemTxAttrs *attrs); 1054 1055 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1056 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1057 1058 /* 1059 * Helpers to dynamically generates XML descriptions of the sysregs 1060 * and SVE registers. Returns the number of registers in each set. 1061 */ 1062 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1063 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1064 1065 /* Returns the dynamically generated XML for the gdb stub. 1066 * Returns a pointer to the XML contents for the specified XML file or NULL 1067 * if the XML name doesn't match the predefined one. 1068 */ 1069 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1070 1071 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1072 int cpuid, void *opaque); 1073 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1074 int cpuid, void *opaque); 1075 1076 #ifdef TARGET_AARCH64 1077 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1078 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1079 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1080 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1081 int new_el, bool el0_a64); 1082 void aarch64_add_sve_properties(Object *obj); 1083 void aarch64_add_pauth_properties(Object *obj); 1084 1085 /* 1086 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1087 * The byte at offset i from the start of the in-memory representation contains 1088 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1089 * lowest offsets are stored in the lowest memory addresses, then that nearly 1090 * matches QEMU's representation, which is to use an array of host-endian 1091 * uint64_t's, where the lower offsets are at the lower indices. To complete 1092 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1093 */ 1094 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1095 { 1096 #ifdef HOST_WORDS_BIGENDIAN 1097 int i; 1098 1099 for (i = 0; i < nr; ++i) { 1100 dst[i] = bswap64(src[i]); 1101 } 1102 1103 return dst; 1104 #else 1105 return src; 1106 #endif 1107 } 1108 1109 #else 1110 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1111 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1112 int n, bool a) 1113 { } 1114 static inline void aarch64_add_sve_properties(Object *obj) { } 1115 #endif 1116 1117 void aarch64_sync_32_to_64(CPUARMState *env); 1118 void aarch64_sync_64_to_32(CPUARMState *env); 1119 1120 int fp_exception_el(CPUARMState *env, int cur_el); 1121 int sve_exception_el(CPUARMState *env, int cur_el); 1122 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1123 1124 static inline bool is_a64(CPUARMState *env) 1125 { 1126 return env->aarch64; 1127 } 1128 1129 /** 1130 * pmu_op_start/finish 1131 * @env: CPUARMState 1132 * 1133 * Convert all PMU counters between their delta form (the typical mode when 1134 * they are enabled) and the guest-visible values. These two calls must 1135 * surround any action which might affect the counters. 1136 */ 1137 void pmu_op_start(CPUARMState *env); 1138 void pmu_op_finish(CPUARMState *env); 1139 1140 /* 1141 * Called when a PMU counter is due to overflow 1142 */ 1143 void arm_pmu_timer_cb(void *opaque); 1144 1145 /** 1146 * Functions to register as EL change hooks for PMU mode filtering 1147 */ 1148 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1149 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1150 1151 /* 1152 * pmu_init 1153 * @cpu: ARMCPU 1154 * 1155 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1156 * for the current configuration 1157 */ 1158 void pmu_init(ARMCPU *cpu); 1159 1160 /* SCTLR bit meanings. Several bits have been reused in newer 1161 * versions of the architecture; in that case we define constants 1162 * for both old and new bit meanings. Code which tests against those 1163 * bits should probably check or otherwise arrange that the CPU 1164 * is the architectural version it expects. 1165 */ 1166 #define SCTLR_M (1U << 0) 1167 #define SCTLR_A (1U << 1) 1168 #define SCTLR_C (1U << 2) 1169 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1170 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1171 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1172 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1173 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1174 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1175 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1176 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1177 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1178 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1179 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1180 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1181 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1182 #define SCTLR_SED (1U << 8) /* v8 onward */ 1183 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1184 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1185 #define SCTLR_F (1U << 10) /* up to v6 */ 1186 #define SCTLR_SW (1U << 10) /* v7 */ 1187 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1188 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1189 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1190 #define SCTLR_I (1U << 12) 1191 #define SCTLR_V (1U << 13) /* AArch32 only */ 1192 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1193 #define SCTLR_RR (1U << 14) /* up to v7 */ 1194 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1195 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1196 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1197 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1198 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1199 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1200 #define SCTLR_BR (1U << 17) /* PMSA only */ 1201 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1202 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1203 #define SCTLR_WXN (1U << 19) 1204 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1205 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1206 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1207 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1208 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1209 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1210 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1211 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1212 #define SCTLR_VE (1U << 24) /* up to v7 */ 1213 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1214 #define SCTLR_EE (1U << 25) 1215 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1216 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1217 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1218 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1219 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1220 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1221 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1222 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1223 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1224 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1225 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1226 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1227 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1228 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1229 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1230 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1231 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1232 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1233 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1234 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1235 1236 #define CPTR_TCPAC (1U << 31) 1237 #define CPTR_TTA (1U << 20) 1238 #define CPTR_TFP (1U << 10) 1239 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1240 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1241 1242 #define MDCR_EPMAD (1U << 21) 1243 #define MDCR_EDAD (1U << 20) 1244 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1245 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1246 #define MDCR_SDD (1U << 16) 1247 #define MDCR_SPD (3U << 14) 1248 #define MDCR_TDRA (1U << 11) 1249 #define MDCR_TDOSA (1U << 10) 1250 #define MDCR_TDA (1U << 9) 1251 #define MDCR_TDE (1U << 8) 1252 #define MDCR_HPME (1U << 7) 1253 #define MDCR_TPM (1U << 6) 1254 #define MDCR_TPMCR (1U << 5) 1255 #define MDCR_HPMN (0x1fU) 1256 1257 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1258 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1259 1260 #define CPSR_M (0x1fU) 1261 #define CPSR_T (1U << 5) 1262 #define CPSR_F (1U << 6) 1263 #define CPSR_I (1U << 7) 1264 #define CPSR_A (1U << 8) 1265 #define CPSR_E (1U << 9) 1266 #define CPSR_IT_2_7 (0xfc00U) 1267 #define CPSR_GE (0xfU << 16) 1268 #define CPSR_IL (1U << 20) 1269 #define CPSR_DIT (1U << 21) 1270 #define CPSR_PAN (1U << 22) 1271 #define CPSR_SSBS (1U << 23) 1272 #define CPSR_J (1U << 24) 1273 #define CPSR_IT_0_1 (3U << 25) 1274 #define CPSR_Q (1U << 27) 1275 #define CPSR_V (1U << 28) 1276 #define CPSR_C (1U << 29) 1277 #define CPSR_Z (1U << 30) 1278 #define CPSR_N (1U << 31) 1279 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1280 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1281 1282 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1283 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1284 | CPSR_NZCV) 1285 /* Bits writable in user mode. */ 1286 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1287 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1288 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1289 1290 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1291 #define XPSR_EXCP 0x1ffU 1292 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1293 #define XPSR_IT_2_7 CPSR_IT_2_7 1294 #define XPSR_GE CPSR_GE 1295 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1296 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1297 #define XPSR_IT_0_1 CPSR_IT_0_1 1298 #define XPSR_Q CPSR_Q 1299 #define XPSR_V CPSR_V 1300 #define XPSR_C CPSR_C 1301 #define XPSR_Z CPSR_Z 1302 #define XPSR_N CPSR_N 1303 #define XPSR_NZCV CPSR_NZCV 1304 #define XPSR_IT CPSR_IT 1305 1306 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1307 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1308 #define TTBCR_PD0 (1U << 4) 1309 #define TTBCR_PD1 (1U << 5) 1310 #define TTBCR_EPD0 (1U << 7) 1311 #define TTBCR_IRGN0 (3U << 8) 1312 #define TTBCR_ORGN0 (3U << 10) 1313 #define TTBCR_SH0 (3U << 12) 1314 #define TTBCR_T1SZ (3U << 16) 1315 #define TTBCR_A1 (1U << 22) 1316 #define TTBCR_EPD1 (1U << 23) 1317 #define TTBCR_IRGN1 (3U << 24) 1318 #define TTBCR_ORGN1 (3U << 26) 1319 #define TTBCR_SH1 (1U << 28) 1320 #define TTBCR_EAE (1U << 31) 1321 1322 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1323 * Only these are valid when in AArch64 mode; in 1324 * AArch32 mode SPSRs are basically CPSR-format. 1325 */ 1326 #define PSTATE_SP (1U) 1327 #define PSTATE_M (0xFU) 1328 #define PSTATE_nRW (1U << 4) 1329 #define PSTATE_F (1U << 6) 1330 #define PSTATE_I (1U << 7) 1331 #define PSTATE_A (1U << 8) 1332 #define PSTATE_D (1U << 9) 1333 #define PSTATE_BTYPE (3U << 10) 1334 #define PSTATE_SSBS (1U << 12) 1335 #define PSTATE_IL (1U << 20) 1336 #define PSTATE_SS (1U << 21) 1337 #define PSTATE_PAN (1U << 22) 1338 #define PSTATE_UAO (1U << 23) 1339 #define PSTATE_DIT (1U << 24) 1340 #define PSTATE_TCO (1U << 25) 1341 #define PSTATE_V (1U << 28) 1342 #define PSTATE_C (1U << 29) 1343 #define PSTATE_Z (1U << 30) 1344 #define PSTATE_N (1U << 31) 1345 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1346 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1347 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1348 /* Mode values for AArch64 */ 1349 #define PSTATE_MODE_EL3h 13 1350 #define PSTATE_MODE_EL3t 12 1351 #define PSTATE_MODE_EL2h 9 1352 #define PSTATE_MODE_EL2t 8 1353 #define PSTATE_MODE_EL1h 5 1354 #define PSTATE_MODE_EL1t 4 1355 #define PSTATE_MODE_EL0t 0 1356 1357 /* Write a new value to v7m.exception, thus transitioning into or out 1358 * of Handler mode; this may result in a change of active stack pointer. 1359 */ 1360 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1361 1362 /* Map EL and handler into a PSTATE_MODE. */ 1363 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1364 { 1365 return (el << 2) | handler; 1366 } 1367 1368 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1369 * interprocessing, so we don't attempt to sync with the cpsr state used by 1370 * the 32 bit decoder. 1371 */ 1372 static inline uint32_t pstate_read(CPUARMState *env) 1373 { 1374 int ZF; 1375 1376 ZF = (env->ZF == 0); 1377 return (env->NF & 0x80000000) | (ZF << 30) 1378 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1379 | env->pstate | env->daif | (env->btype << 10); 1380 } 1381 1382 static inline void pstate_write(CPUARMState *env, uint32_t val) 1383 { 1384 env->ZF = (~val) & PSTATE_Z; 1385 env->NF = val; 1386 env->CF = (val >> 29) & 1; 1387 env->VF = (val << 3) & 0x80000000; 1388 env->daif = val & PSTATE_DAIF; 1389 env->btype = (val >> 10) & 3; 1390 env->pstate = val & ~CACHED_PSTATE_BITS; 1391 } 1392 1393 /* Return the current CPSR value. */ 1394 uint32_t cpsr_read(CPUARMState *env); 1395 1396 typedef enum CPSRWriteType { 1397 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1398 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1399 CPSRWriteRaw = 2, 1400 /* trust values, no reg bank switch, no hflags rebuild */ 1401 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1402 } CPSRWriteType; 1403 1404 /* 1405 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1406 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1407 * correspond to TB flags bits cached in the hflags, unless @write_type 1408 * is CPSRWriteRaw. 1409 */ 1410 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1411 CPSRWriteType write_type); 1412 1413 /* Return the current xPSR value. */ 1414 static inline uint32_t xpsr_read(CPUARMState *env) 1415 { 1416 int ZF; 1417 ZF = (env->ZF == 0); 1418 return (env->NF & 0x80000000) | (ZF << 30) 1419 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1420 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1421 | ((env->condexec_bits & 0xfc) << 8) 1422 | (env->GE << 16) 1423 | env->v7m.exception; 1424 } 1425 1426 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1427 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1428 { 1429 if (mask & XPSR_NZCV) { 1430 env->ZF = (~val) & XPSR_Z; 1431 env->NF = val; 1432 env->CF = (val >> 29) & 1; 1433 env->VF = (val << 3) & 0x80000000; 1434 } 1435 if (mask & XPSR_Q) { 1436 env->QF = ((val & XPSR_Q) != 0); 1437 } 1438 if (mask & XPSR_GE) { 1439 env->GE = (val & XPSR_GE) >> 16; 1440 } 1441 #ifndef CONFIG_USER_ONLY 1442 if (mask & XPSR_T) { 1443 env->thumb = ((val & XPSR_T) != 0); 1444 } 1445 if (mask & XPSR_IT_0_1) { 1446 env->condexec_bits &= ~3; 1447 env->condexec_bits |= (val >> 25) & 3; 1448 } 1449 if (mask & XPSR_IT_2_7) { 1450 env->condexec_bits &= 3; 1451 env->condexec_bits |= (val >> 8) & 0xfc; 1452 } 1453 if (mask & XPSR_EXCP) { 1454 /* Note that this only happens on exception exit */ 1455 write_v7m_exception(env, val & XPSR_EXCP); 1456 } 1457 #endif 1458 } 1459 1460 #define HCR_VM (1ULL << 0) 1461 #define HCR_SWIO (1ULL << 1) 1462 #define HCR_PTW (1ULL << 2) 1463 #define HCR_FMO (1ULL << 3) 1464 #define HCR_IMO (1ULL << 4) 1465 #define HCR_AMO (1ULL << 5) 1466 #define HCR_VF (1ULL << 6) 1467 #define HCR_VI (1ULL << 7) 1468 #define HCR_VSE (1ULL << 8) 1469 #define HCR_FB (1ULL << 9) 1470 #define HCR_BSU_MASK (3ULL << 10) 1471 #define HCR_DC (1ULL << 12) 1472 #define HCR_TWI (1ULL << 13) 1473 #define HCR_TWE (1ULL << 14) 1474 #define HCR_TID0 (1ULL << 15) 1475 #define HCR_TID1 (1ULL << 16) 1476 #define HCR_TID2 (1ULL << 17) 1477 #define HCR_TID3 (1ULL << 18) 1478 #define HCR_TSC (1ULL << 19) 1479 #define HCR_TIDCP (1ULL << 20) 1480 #define HCR_TACR (1ULL << 21) 1481 #define HCR_TSW (1ULL << 22) 1482 #define HCR_TPCP (1ULL << 23) 1483 #define HCR_TPU (1ULL << 24) 1484 #define HCR_TTLB (1ULL << 25) 1485 #define HCR_TVM (1ULL << 26) 1486 #define HCR_TGE (1ULL << 27) 1487 #define HCR_TDZ (1ULL << 28) 1488 #define HCR_HCD (1ULL << 29) 1489 #define HCR_TRVM (1ULL << 30) 1490 #define HCR_RW (1ULL << 31) 1491 #define HCR_CD (1ULL << 32) 1492 #define HCR_ID (1ULL << 33) 1493 #define HCR_E2H (1ULL << 34) 1494 #define HCR_TLOR (1ULL << 35) 1495 #define HCR_TERR (1ULL << 36) 1496 #define HCR_TEA (1ULL << 37) 1497 #define HCR_MIOCNCE (1ULL << 38) 1498 /* RES0 bit 39 */ 1499 #define HCR_APK (1ULL << 40) 1500 #define HCR_API (1ULL << 41) 1501 #define HCR_NV (1ULL << 42) 1502 #define HCR_NV1 (1ULL << 43) 1503 #define HCR_AT (1ULL << 44) 1504 #define HCR_NV2 (1ULL << 45) 1505 #define HCR_FWB (1ULL << 46) 1506 #define HCR_FIEN (1ULL << 47) 1507 /* RES0 bit 48 */ 1508 #define HCR_TID4 (1ULL << 49) 1509 #define HCR_TICAB (1ULL << 50) 1510 #define HCR_AMVOFFEN (1ULL << 51) 1511 #define HCR_TOCU (1ULL << 52) 1512 #define HCR_ENSCXT (1ULL << 53) 1513 #define HCR_TTLBIS (1ULL << 54) 1514 #define HCR_TTLBOS (1ULL << 55) 1515 #define HCR_ATA (1ULL << 56) 1516 #define HCR_DCT (1ULL << 57) 1517 #define HCR_TID5 (1ULL << 58) 1518 #define HCR_TWEDEN (1ULL << 59) 1519 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1520 1521 #define HPFAR_NS (1ULL << 63) 1522 1523 #define SCR_NS (1U << 0) 1524 #define SCR_IRQ (1U << 1) 1525 #define SCR_FIQ (1U << 2) 1526 #define SCR_EA (1U << 3) 1527 #define SCR_FW (1U << 4) 1528 #define SCR_AW (1U << 5) 1529 #define SCR_NET (1U << 6) 1530 #define SCR_SMD (1U << 7) 1531 #define SCR_HCE (1U << 8) 1532 #define SCR_SIF (1U << 9) 1533 #define SCR_RW (1U << 10) 1534 #define SCR_ST (1U << 11) 1535 #define SCR_TWI (1U << 12) 1536 #define SCR_TWE (1U << 13) 1537 #define SCR_TLOR (1U << 14) 1538 #define SCR_TERR (1U << 15) 1539 #define SCR_APK (1U << 16) 1540 #define SCR_API (1U << 17) 1541 #define SCR_EEL2 (1U << 18) 1542 #define SCR_EASE (1U << 19) 1543 #define SCR_NMEA (1U << 20) 1544 #define SCR_FIEN (1U << 21) 1545 #define SCR_ENSCXT (1U << 25) 1546 #define SCR_ATA (1U << 26) 1547 1548 #define HSTR_TTEE (1 << 16) 1549 #define HSTR_TJDBX (1 << 17) 1550 1551 /* Return the current FPSCR value. */ 1552 uint32_t vfp_get_fpscr(CPUARMState *env); 1553 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1554 1555 /* FPCR, Floating Point Control Register 1556 * FPSR, Floating Poiht Status Register 1557 * 1558 * For A64 the FPSCR is split into two logically distinct registers, 1559 * FPCR and FPSR. However since they still use non-overlapping bits 1560 * we store the underlying state in fpscr and just mask on read/write. 1561 */ 1562 #define FPSR_MASK 0xf800009f 1563 #define FPCR_MASK 0x07ff9f00 1564 1565 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1566 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1567 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1568 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1569 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1570 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1571 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1572 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1573 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1574 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1575 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1576 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1577 #define FPCR_V (1 << 28) /* FP overflow flag */ 1578 #define FPCR_C (1 << 29) /* FP carry flag */ 1579 #define FPCR_Z (1 << 30) /* FP zero flag */ 1580 #define FPCR_N (1 << 31) /* FP negative flag */ 1581 1582 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1583 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1584 #define FPCR_LTPSIZE_LENGTH 3 1585 1586 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1587 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1588 1589 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1590 { 1591 return vfp_get_fpscr(env) & FPSR_MASK; 1592 } 1593 1594 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1595 { 1596 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1597 vfp_set_fpscr(env, new_fpscr); 1598 } 1599 1600 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1601 { 1602 return vfp_get_fpscr(env) & FPCR_MASK; 1603 } 1604 1605 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1606 { 1607 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1608 vfp_set_fpscr(env, new_fpscr); 1609 } 1610 1611 enum arm_cpu_mode { 1612 ARM_CPU_MODE_USR = 0x10, 1613 ARM_CPU_MODE_FIQ = 0x11, 1614 ARM_CPU_MODE_IRQ = 0x12, 1615 ARM_CPU_MODE_SVC = 0x13, 1616 ARM_CPU_MODE_MON = 0x16, 1617 ARM_CPU_MODE_ABT = 0x17, 1618 ARM_CPU_MODE_HYP = 0x1a, 1619 ARM_CPU_MODE_UND = 0x1b, 1620 ARM_CPU_MODE_SYS = 0x1f 1621 }; 1622 1623 /* VFP system registers. */ 1624 #define ARM_VFP_FPSID 0 1625 #define ARM_VFP_FPSCR 1 1626 #define ARM_VFP_MVFR2 5 1627 #define ARM_VFP_MVFR1 6 1628 #define ARM_VFP_MVFR0 7 1629 #define ARM_VFP_FPEXC 8 1630 #define ARM_VFP_FPINST 9 1631 #define ARM_VFP_FPINST2 10 1632 /* These ones are M-profile only */ 1633 #define ARM_VFP_FPSCR_NZCVQC 2 1634 #define ARM_VFP_VPR 12 1635 #define ARM_VFP_P0 13 1636 #define ARM_VFP_FPCXT_NS 14 1637 #define ARM_VFP_FPCXT_S 15 1638 1639 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1640 #define QEMU_VFP_FPSCR_NZCV 0xffff 1641 1642 /* iwMMXt coprocessor control registers. */ 1643 #define ARM_IWMMXT_wCID 0 1644 #define ARM_IWMMXT_wCon 1 1645 #define ARM_IWMMXT_wCSSF 2 1646 #define ARM_IWMMXT_wCASF 3 1647 #define ARM_IWMMXT_wCGR0 8 1648 #define ARM_IWMMXT_wCGR1 9 1649 #define ARM_IWMMXT_wCGR2 10 1650 #define ARM_IWMMXT_wCGR3 11 1651 1652 /* V7M CCR bits */ 1653 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1654 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1655 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1656 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1657 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1658 FIELD(V7M_CCR, STKALIGN, 9, 1) 1659 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1660 FIELD(V7M_CCR, DC, 16, 1) 1661 FIELD(V7M_CCR, IC, 17, 1) 1662 FIELD(V7M_CCR, BP, 18, 1) 1663 FIELD(V7M_CCR, LOB, 19, 1) 1664 FIELD(V7M_CCR, TRD, 20, 1) 1665 1666 /* V7M SCR bits */ 1667 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1668 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1669 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1670 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1671 1672 /* V7M AIRCR bits */ 1673 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1674 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1675 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1676 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1677 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1678 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1679 FIELD(V7M_AIRCR, PRIS, 14, 1) 1680 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1681 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1682 1683 /* V7M CFSR bits for MMFSR */ 1684 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1685 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1686 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1687 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1688 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1689 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1690 1691 /* V7M CFSR bits for BFSR */ 1692 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1693 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1694 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1695 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1696 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1697 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1698 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1699 1700 /* V7M CFSR bits for UFSR */ 1701 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1702 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1703 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1704 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1705 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1706 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1707 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1708 1709 /* V7M CFSR bit masks covering all of the subregister bits */ 1710 FIELD(V7M_CFSR, MMFSR, 0, 8) 1711 FIELD(V7M_CFSR, BFSR, 8, 8) 1712 FIELD(V7M_CFSR, UFSR, 16, 16) 1713 1714 /* V7M HFSR bits */ 1715 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1716 FIELD(V7M_HFSR, FORCED, 30, 1) 1717 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1718 1719 /* V7M DFSR bits */ 1720 FIELD(V7M_DFSR, HALTED, 0, 1) 1721 FIELD(V7M_DFSR, BKPT, 1, 1) 1722 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1723 FIELD(V7M_DFSR, VCATCH, 3, 1) 1724 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1725 1726 /* V7M SFSR bits */ 1727 FIELD(V7M_SFSR, INVEP, 0, 1) 1728 FIELD(V7M_SFSR, INVIS, 1, 1) 1729 FIELD(V7M_SFSR, INVER, 2, 1) 1730 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1731 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1732 FIELD(V7M_SFSR, LSPERR, 5, 1) 1733 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1734 FIELD(V7M_SFSR, LSERR, 7, 1) 1735 1736 /* v7M MPU_CTRL bits */ 1737 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1738 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1739 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1740 1741 /* v7M CLIDR bits */ 1742 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1743 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1744 FIELD(V7M_CLIDR, LOC, 24, 3) 1745 FIELD(V7M_CLIDR, LOUU, 27, 3) 1746 FIELD(V7M_CLIDR, ICB, 30, 2) 1747 1748 FIELD(V7M_CSSELR, IND, 0, 1) 1749 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1750 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1751 * define a mask for this and check that it doesn't permit running off 1752 * the end of the array. 1753 */ 1754 FIELD(V7M_CSSELR, INDEX, 0, 4) 1755 1756 /* v7M FPCCR bits */ 1757 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1758 FIELD(V7M_FPCCR, USER, 1, 1) 1759 FIELD(V7M_FPCCR, S, 2, 1) 1760 FIELD(V7M_FPCCR, THREAD, 3, 1) 1761 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1762 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1763 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1764 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1765 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1766 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1767 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1768 FIELD(V7M_FPCCR, RES0, 11, 15) 1769 FIELD(V7M_FPCCR, TS, 26, 1) 1770 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1771 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1772 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1773 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1774 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1775 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1776 #define R_V7M_FPCCR_BANKED_MASK \ 1777 (R_V7M_FPCCR_LSPACT_MASK | \ 1778 R_V7M_FPCCR_USER_MASK | \ 1779 R_V7M_FPCCR_THREAD_MASK | \ 1780 R_V7M_FPCCR_MMRDY_MASK | \ 1781 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1782 R_V7M_FPCCR_UFRDY_MASK | \ 1783 R_V7M_FPCCR_ASPEN_MASK) 1784 1785 /* v7M VPR bits */ 1786 FIELD(V7M_VPR, P0, 0, 16) 1787 FIELD(V7M_VPR, MASK01, 16, 4) 1788 FIELD(V7M_VPR, MASK23, 20, 4) 1789 1790 /* 1791 * System register ID fields. 1792 */ 1793 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1794 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1795 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1796 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1797 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1798 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1799 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1800 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1801 FIELD(CLIDR_EL1, LOC, 24, 3) 1802 FIELD(CLIDR_EL1, LOUU, 27, 3) 1803 FIELD(CLIDR_EL1, ICB, 30, 3) 1804 1805 /* When FEAT_CCIDX is implemented */ 1806 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1807 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1808 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1809 1810 /* When FEAT_CCIDX is not implemented */ 1811 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1812 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1813 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1814 1815 FIELD(CTR_EL0, IMINLINE, 0, 4) 1816 FIELD(CTR_EL0, L1IP, 14, 2) 1817 FIELD(CTR_EL0, DMINLINE, 16, 4) 1818 FIELD(CTR_EL0, ERG, 20, 4) 1819 FIELD(CTR_EL0, CWG, 24, 4) 1820 FIELD(CTR_EL0, IDC, 28, 1) 1821 FIELD(CTR_EL0, DIC, 29, 1) 1822 FIELD(CTR_EL0, TMINLINE, 32, 6) 1823 1824 FIELD(MIDR_EL1, REVISION, 0, 4) 1825 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1826 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1827 FIELD(MIDR_EL1, VARIANT, 20, 4) 1828 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1829 1830 FIELD(ID_ISAR0, SWAP, 0, 4) 1831 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1832 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1833 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1834 FIELD(ID_ISAR0, COPROC, 16, 4) 1835 FIELD(ID_ISAR0, DEBUG, 20, 4) 1836 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1837 1838 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1839 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1840 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1841 FIELD(ID_ISAR1, EXTEND, 12, 4) 1842 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1843 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1844 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1845 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1846 1847 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1848 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1849 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1850 FIELD(ID_ISAR2, MULT, 12, 4) 1851 FIELD(ID_ISAR2, MULTS, 16, 4) 1852 FIELD(ID_ISAR2, MULTU, 20, 4) 1853 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1854 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1855 1856 FIELD(ID_ISAR3, SATURATE, 0, 4) 1857 FIELD(ID_ISAR3, SIMD, 4, 4) 1858 FIELD(ID_ISAR3, SVC, 8, 4) 1859 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1860 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1861 FIELD(ID_ISAR3, T32COPY, 20, 4) 1862 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1863 FIELD(ID_ISAR3, T32EE, 28, 4) 1864 1865 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1866 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1867 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1868 FIELD(ID_ISAR4, SMC, 12, 4) 1869 FIELD(ID_ISAR4, BARRIER, 16, 4) 1870 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1871 FIELD(ID_ISAR4, PSR_M, 24, 4) 1872 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1873 1874 FIELD(ID_ISAR5, SEVL, 0, 4) 1875 FIELD(ID_ISAR5, AES, 4, 4) 1876 FIELD(ID_ISAR5, SHA1, 8, 4) 1877 FIELD(ID_ISAR5, SHA2, 12, 4) 1878 FIELD(ID_ISAR5, CRC32, 16, 4) 1879 FIELD(ID_ISAR5, RDM, 24, 4) 1880 FIELD(ID_ISAR5, VCMA, 28, 4) 1881 1882 FIELD(ID_ISAR6, JSCVT, 0, 4) 1883 FIELD(ID_ISAR6, DP, 4, 4) 1884 FIELD(ID_ISAR6, FHM, 8, 4) 1885 FIELD(ID_ISAR6, SB, 12, 4) 1886 FIELD(ID_ISAR6, SPECRES, 16, 4) 1887 FIELD(ID_ISAR6, BF16, 20, 4) 1888 FIELD(ID_ISAR6, I8MM, 24, 4) 1889 1890 FIELD(ID_MMFR0, VMSA, 0, 4) 1891 FIELD(ID_MMFR0, PMSA, 4, 4) 1892 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 1893 FIELD(ID_MMFR0, SHARELVL, 12, 4) 1894 FIELD(ID_MMFR0, TCM, 16, 4) 1895 FIELD(ID_MMFR0, AUXREG, 20, 4) 1896 FIELD(ID_MMFR0, FCSE, 24, 4) 1897 FIELD(ID_MMFR0, INNERSHR, 28, 4) 1898 1899 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 1900 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 1901 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 1902 FIELD(ID_MMFR1, L1UNISW, 12, 4) 1903 FIELD(ID_MMFR1, L1HVD, 16, 4) 1904 FIELD(ID_MMFR1, L1UNI, 20, 4) 1905 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 1906 FIELD(ID_MMFR1, BPRED, 28, 4) 1907 1908 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 1909 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 1910 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 1911 FIELD(ID_MMFR2, HVDTLB, 12, 4) 1912 FIELD(ID_MMFR2, UNITLB, 16, 4) 1913 FIELD(ID_MMFR2, MEMBARR, 20, 4) 1914 FIELD(ID_MMFR2, WFISTALL, 24, 4) 1915 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 1916 1917 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 1918 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 1919 FIELD(ID_MMFR3, BPMAINT, 8, 4) 1920 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 1921 FIELD(ID_MMFR3, PAN, 16, 4) 1922 FIELD(ID_MMFR3, COHWALK, 20, 4) 1923 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 1924 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 1925 1926 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1927 FIELD(ID_MMFR4, AC2, 4, 4) 1928 FIELD(ID_MMFR4, XNX, 8, 4) 1929 FIELD(ID_MMFR4, CNP, 12, 4) 1930 FIELD(ID_MMFR4, HPDS, 16, 4) 1931 FIELD(ID_MMFR4, LSM, 20, 4) 1932 FIELD(ID_MMFR4, CCIDX, 24, 4) 1933 FIELD(ID_MMFR4, EVT, 28, 4) 1934 1935 FIELD(ID_MMFR5, ETS, 0, 4) 1936 1937 FIELD(ID_PFR0, STATE0, 0, 4) 1938 FIELD(ID_PFR0, STATE1, 4, 4) 1939 FIELD(ID_PFR0, STATE2, 8, 4) 1940 FIELD(ID_PFR0, STATE3, 12, 4) 1941 FIELD(ID_PFR0, CSV2, 16, 4) 1942 FIELD(ID_PFR0, AMU, 20, 4) 1943 FIELD(ID_PFR0, DIT, 24, 4) 1944 FIELD(ID_PFR0, RAS, 28, 4) 1945 1946 FIELD(ID_PFR1, PROGMOD, 0, 4) 1947 FIELD(ID_PFR1, SECURITY, 4, 4) 1948 FIELD(ID_PFR1, MPROGMOD, 8, 4) 1949 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 1950 FIELD(ID_PFR1, GENTIMER, 16, 4) 1951 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 1952 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 1953 FIELD(ID_PFR1, GIC, 28, 4) 1954 1955 FIELD(ID_PFR2, CSV3, 0, 4) 1956 FIELD(ID_PFR2, SSBS, 4, 4) 1957 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 1958 1959 FIELD(ID_AA64ISAR0, AES, 4, 4) 1960 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1961 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1962 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1963 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1964 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1965 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1966 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1967 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1968 FIELD(ID_AA64ISAR0, DP, 44, 4) 1969 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1970 FIELD(ID_AA64ISAR0, TS, 52, 4) 1971 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1972 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1973 1974 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1975 FIELD(ID_AA64ISAR1, APA, 4, 4) 1976 FIELD(ID_AA64ISAR1, API, 8, 4) 1977 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1978 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1979 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1980 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1981 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1982 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1983 FIELD(ID_AA64ISAR1, SB, 36, 4) 1984 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1985 FIELD(ID_AA64ISAR1, BF16, 44, 4) 1986 FIELD(ID_AA64ISAR1, DGH, 48, 4) 1987 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 1988 1989 FIELD(ID_AA64PFR0, EL0, 0, 4) 1990 FIELD(ID_AA64PFR0, EL1, 4, 4) 1991 FIELD(ID_AA64PFR0, EL2, 8, 4) 1992 FIELD(ID_AA64PFR0, EL3, 12, 4) 1993 FIELD(ID_AA64PFR0, FP, 16, 4) 1994 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1995 FIELD(ID_AA64PFR0, GIC, 24, 4) 1996 FIELD(ID_AA64PFR0, RAS, 28, 4) 1997 FIELD(ID_AA64PFR0, SVE, 32, 4) 1998 FIELD(ID_AA64PFR0, SEL2, 36, 4) 1999 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2000 FIELD(ID_AA64PFR0, AMU, 44, 4) 2001 FIELD(ID_AA64PFR0, DIT, 48, 4) 2002 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2003 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2004 2005 FIELD(ID_AA64PFR1, BT, 0, 4) 2006 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2007 FIELD(ID_AA64PFR1, MTE, 8, 4) 2008 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2009 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2010 2011 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2012 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2013 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2014 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2015 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2016 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2017 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2018 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2019 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2020 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2021 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2022 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2023 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2024 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2025 2026 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2027 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2028 FIELD(ID_AA64MMFR1, VH, 8, 4) 2029 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2030 FIELD(ID_AA64MMFR1, LO, 16, 4) 2031 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2032 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2033 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2034 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2035 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2036 2037 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2038 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2039 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2040 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2041 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2042 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2043 FIELD(ID_AA64MMFR2, NV, 24, 4) 2044 FIELD(ID_AA64MMFR2, ST, 28, 4) 2045 FIELD(ID_AA64MMFR2, AT, 32, 4) 2046 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2047 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2048 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2049 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2050 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2051 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2052 2053 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2054 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2055 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2056 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2057 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2058 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2059 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2060 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2061 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2062 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2063 2064 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2065 FIELD(ID_AA64ZFR0, AES, 4, 4) 2066 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2067 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2068 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2069 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2070 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2071 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2072 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2073 2074 FIELD(ID_DFR0, COPDBG, 0, 4) 2075 FIELD(ID_DFR0, COPSDBG, 4, 4) 2076 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2077 FIELD(ID_DFR0, COPTRC, 12, 4) 2078 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2079 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2080 FIELD(ID_DFR0, PERFMON, 24, 4) 2081 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2082 2083 FIELD(ID_DFR1, MTPMU, 0, 4) 2084 2085 FIELD(DBGDIDR, SE_IMP, 12, 1) 2086 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2087 FIELD(DBGDIDR, VERSION, 16, 4) 2088 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2089 FIELD(DBGDIDR, BRPS, 24, 4) 2090 FIELD(DBGDIDR, WRPS, 28, 4) 2091 2092 FIELD(MVFR0, SIMDREG, 0, 4) 2093 FIELD(MVFR0, FPSP, 4, 4) 2094 FIELD(MVFR0, FPDP, 8, 4) 2095 FIELD(MVFR0, FPTRAP, 12, 4) 2096 FIELD(MVFR0, FPDIVIDE, 16, 4) 2097 FIELD(MVFR0, FPSQRT, 20, 4) 2098 FIELD(MVFR0, FPSHVEC, 24, 4) 2099 FIELD(MVFR0, FPROUND, 28, 4) 2100 2101 FIELD(MVFR1, FPFTZ, 0, 4) 2102 FIELD(MVFR1, FPDNAN, 4, 4) 2103 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2104 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2105 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2106 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2107 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2108 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2109 FIELD(MVFR1, FPHP, 24, 4) 2110 FIELD(MVFR1, SIMDFMAC, 28, 4) 2111 2112 FIELD(MVFR2, SIMDMISC, 0, 4) 2113 FIELD(MVFR2, FPMISC, 4, 4) 2114 2115 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2116 2117 /* If adding a feature bit which corresponds to a Linux ELF 2118 * HWCAP bit, remember to update the feature-bit-to-hwcap 2119 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2120 */ 2121 enum arm_features { 2122 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2123 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2124 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2125 ARM_FEATURE_V6, 2126 ARM_FEATURE_V6K, 2127 ARM_FEATURE_V7, 2128 ARM_FEATURE_THUMB2, 2129 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2130 ARM_FEATURE_NEON, 2131 ARM_FEATURE_M, /* Microcontroller profile. */ 2132 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2133 ARM_FEATURE_THUMB2EE, 2134 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2135 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2136 ARM_FEATURE_V4T, 2137 ARM_FEATURE_V5, 2138 ARM_FEATURE_STRONGARM, 2139 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2140 ARM_FEATURE_GENERIC_TIMER, 2141 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2142 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2143 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2144 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2145 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2146 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2147 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2148 ARM_FEATURE_V8, 2149 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2150 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2151 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2152 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2153 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2154 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2155 ARM_FEATURE_PMU, /* has PMU support */ 2156 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2157 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2158 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2159 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2160 }; 2161 2162 static inline int arm_feature(CPUARMState *env, int feature) 2163 { 2164 return (env->features & (1ULL << feature)) != 0; 2165 } 2166 2167 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2168 2169 #if !defined(CONFIG_USER_ONLY) 2170 /* Return true if exception levels below EL3 are in secure state, 2171 * or would be following an exception return to that level. 2172 * Unlike arm_is_secure() (which is always a question about the 2173 * _current_ state of the CPU) this doesn't care about the current 2174 * EL or mode. 2175 */ 2176 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2177 { 2178 if (arm_feature(env, ARM_FEATURE_EL3)) { 2179 return !(env->cp15.scr_el3 & SCR_NS); 2180 } else { 2181 /* If EL3 is not supported then the secure state is implementation 2182 * defined, in which case QEMU defaults to non-secure. 2183 */ 2184 return false; 2185 } 2186 } 2187 2188 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2189 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2190 { 2191 if (arm_feature(env, ARM_FEATURE_EL3)) { 2192 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2193 /* CPU currently in AArch64 state and EL3 */ 2194 return true; 2195 } else if (!is_a64(env) && 2196 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2197 /* CPU currently in AArch32 state and monitor mode */ 2198 return true; 2199 } 2200 } 2201 return false; 2202 } 2203 2204 /* Return true if the processor is in secure state */ 2205 static inline bool arm_is_secure(CPUARMState *env) 2206 { 2207 if (arm_is_el3_or_mon(env)) { 2208 return true; 2209 } 2210 return arm_is_secure_below_el3(env); 2211 } 2212 2213 /* 2214 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2215 * This corresponds to the pseudocode EL2Enabled() 2216 */ 2217 static inline bool arm_is_el2_enabled(CPUARMState *env) 2218 { 2219 if (arm_feature(env, ARM_FEATURE_EL2)) { 2220 if (arm_is_secure_below_el3(env)) { 2221 return (env->cp15.scr_el3 & SCR_EEL2) != 0; 2222 } 2223 return true; 2224 } 2225 return false; 2226 } 2227 2228 #else 2229 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2230 { 2231 return false; 2232 } 2233 2234 static inline bool arm_is_secure(CPUARMState *env) 2235 { 2236 return false; 2237 } 2238 2239 static inline bool arm_is_el2_enabled(CPUARMState *env) 2240 { 2241 return false; 2242 } 2243 #endif 2244 2245 /** 2246 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2247 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2248 * "for all purposes other than a direct read or write access of HCR_EL2." 2249 * Not included here is HCR_RW. 2250 */ 2251 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2252 2253 /* Return true if the specified exception level is running in AArch64 state. */ 2254 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2255 { 2256 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2257 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2258 */ 2259 assert(el >= 1 && el <= 3); 2260 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2261 2262 /* The highest exception level is always at the maximum supported 2263 * register width, and then lower levels have a register width controlled 2264 * by bits in the SCR or HCR registers. 2265 */ 2266 if (el == 3) { 2267 return aa64; 2268 } 2269 2270 if (arm_feature(env, ARM_FEATURE_EL3) && 2271 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2272 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2273 } 2274 2275 if (el == 2) { 2276 return aa64; 2277 } 2278 2279 if (arm_is_el2_enabled(env)) { 2280 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2281 } 2282 2283 return aa64; 2284 } 2285 2286 /* Function for determing whether guest cp register reads and writes should 2287 * access the secure or non-secure bank of a cp register. When EL3 is 2288 * operating in AArch32 state, the NS-bit determines whether the secure 2289 * instance of a cp register should be used. When EL3 is AArch64 (or if 2290 * it doesn't exist at all) then there is no register banking, and all 2291 * accesses are to the non-secure version. 2292 */ 2293 static inline bool access_secure_reg(CPUARMState *env) 2294 { 2295 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2296 !arm_el_is_aa64(env, 3) && 2297 !(env->cp15.scr_el3 & SCR_NS)); 2298 2299 return ret; 2300 } 2301 2302 /* Macros for accessing a specified CP register bank */ 2303 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2304 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2305 2306 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2307 do { \ 2308 if (_secure) { \ 2309 (_env)->cp15._regname##_s = (_val); \ 2310 } else { \ 2311 (_env)->cp15._regname##_ns = (_val); \ 2312 } \ 2313 } while (0) 2314 2315 /* Macros for automatically accessing a specific CP register bank depending on 2316 * the current secure state of the system. These macros are not intended for 2317 * supporting instruction translation reads/writes as these are dependent 2318 * solely on the SCR.NS bit and not the mode. 2319 */ 2320 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2321 A32_BANKED_REG_GET((_env), _regname, \ 2322 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2323 2324 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2325 A32_BANKED_REG_SET((_env), _regname, \ 2326 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2327 (_val)) 2328 2329 void arm_cpu_list(void); 2330 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2331 uint32_t cur_el, bool secure); 2332 2333 /* Interface between CPU and Interrupt controller. */ 2334 #ifndef CONFIG_USER_ONLY 2335 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2336 #else 2337 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2338 { 2339 return true; 2340 } 2341 #endif 2342 /** 2343 * armv7m_nvic_set_pending: mark the specified exception as pending 2344 * @opaque: the NVIC 2345 * @irq: the exception number to mark pending 2346 * @secure: false for non-banked exceptions or for the nonsecure 2347 * version of a banked exception, true for the secure version of a banked 2348 * exception. 2349 * 2350 * Marks the specified exception as pending. Note that we will assert() 2351 * if @secure is true and @irq does not specify one of the fixed set 2352 * of architecturally banked exceptions. 2353 */ 2354 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2355 /** 2356 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2357 * @opaque: the NVIC 2358 * @irq: the exception number to mark pending 2359 * @secure: false for non-banked exceptions or for the nonsecure 2360 * version of a banked exception, true for the secure version of a banked 2361 * exception. 2362 * 2363 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2364 * exceptions (exceptions generated in the course of trying to take 2365 * a different exception). 2366 */ 2367 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2368 /** 2369 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2370 * @opaque: the NVIC 2371 * @irq: the exception number to mark pending 2372 * @secure: false for non-banked exceptions or for the nonsecure 2373 * version of a banked exception, true for the secure version of a banked 2374 * exception. 2375 * 2376 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2377 * generated in the course of lazy stacking of FP registers. 2378 */ 2379 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2380 /** 2381 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2382 * exception, and whether it targets Secure state 2383 * @opaque: the NVIC 2384 * @pirq: set to pending exception number 2385 * @ptargets_secure: set to whether pending exception targets Secure 2386 * 2387 * This function writes the number of the highest priority pending 2388 * exception (the one which would be made active by 2389 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2390 * to true if the current highest priority pending exception should 2391 * be taken to Secure state, false for NS. 2392 */ 2393 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2394 bool *ptargets_secure); 2395 /** 2396 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2397 * @opaque: the NVIC 2398 * 2399 * Move the current highest priority pending exception from the pending 2400 * state to the active state, and update v7m.exception to indicate that 2401 * it is the exception currently being handled. 2402 */ 2403 void armv7m_nvic_acknowledge_irq(void *opaque); 2404 /** 2405 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2406 * @opaque: the NVIC 2407 * @irq: the exception number to complete 2408 * @secure: true if this exception was secure 2409 * 2410 * Returns: -1 if the irq was not active 2411 * 1 if completing this irq brought us back to base (no active irqs) 2412 * 0 if there is still an irq active after this one was completed 2413 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2414 */ 2415 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2416 /** 2417 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2418 * @opaque: the NVIC 2419 * @irq: the exception number to mark pending 2420 * @secure: false for non-banked exceptions or for the nonsecure 2421 * version of a banked exception, true for the secure version of a banked 2422 * exception. 2423 * 2424 * Return whether an exception is "ready", i.e. whether the exception is 2425 * enabled and is configured at a priority which would allow it to 2426 * interrupt the current execution priority. This controls whether the 2427 * RDY bit for it in the FPCCR is set. 2428 */ 2429 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2430 /** 2431 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2432 * @opaque: the NVIC 2433 * 2434 * Returns: the raw execution priority as defined by the v8M architecture. 2435 * This is the execution priority minus the effects of AIRCR.PRIS, 2436 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2437 * (v8M ARM ARM I_PKLD.) 2438 */ 2439 int armv7m_nvic_raw_execution_priority(void *opaque); 2440 /** 2441 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2442 * priority is negative for the specified security state. 2443 * @opaque: the NVIC 2444 * @secure: the security state to test 2445 * This corresponds to the pseudocode IsReqExecPriNeg(). 2446 */ 2447 #ifndef CONFIG_USER_ONLY 2448 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2449 #else 2450 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2451 { 2452 return false; 2453 } 2454 #endif 2455 2456 /* Interface for defining coprocessor registers. 2457 * Registers are defined in tables of arm_cp_reginfo structs 2458 * which are passed to define_arm_cp_regs(). 2459 */ 2460 2461 /* When looking up a coprocessor register we look for it 2462 * via an integer which encodes all of: 2463 * coprocessor number 2464 * Crn, Crm, opc1, opc2 fields 2465 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2466 * or via MRRC/MCRR?) 2467 * non-secure/secure bank (AArch32 only) 2468 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2469 * (In this case crn and opc2 should be zero.) 2470 * For AArch64, there is no 32/64 bit size distinction; 2471 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2472 * and 4 bit CRn and CRm. The encoding patterns are chosen 2473 * to be easy to convert to and from the KVM encodings, and also 2474 * so that the hashtable can contain both AArch32 and AArch64 2475 * registers (to allow for interprocessing where we might run 2476 * 32 bit code on a 64 bit core). 2477 */ 2478 /* This bit is private to our hashtable cpreg; in KVM register 2479 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2480 * in the upper bits of the 64 bit ID. 2481 */ 2482 #define CP_REG_AA64_SHIFT 28 2483 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2484 2485 /* To enable banking of coprocessor registers depending on ns-bit we 2486 * add a bit to distinguish between secure and non-secure cpregs in the 2487 * hashtable. 2488 */ 2489 #define CP_REG_NS_SHIFT 29 2490 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2491 2492 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2493 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2494 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2495 2496 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2497 (CP_REG_AA64_MASK | \ 2498 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2499 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2500 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2501 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2502 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2503 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2504 2505 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2506 * version used as a key for the coprocessor register hashtable 2507 */ 2508 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2509 { 2510 uint32_t cpregid = kvmid; 2511 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2512 cpregid |= CP_REG_AA64_MASK; 2513 } else { 2514 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2515 cpregid |= (1 << 15); 2516 } 2517 2518 /* KVM is always non-secure so add the NS flag on AArch32 register 2519 * entries. 2520 */ 2521 cpregid |= 1 << CP_REG_NS_SHIFT; 2522 } 2523 return cpregid; 2524 } 2525 2526 /* Convert a truncated 32 bit hashtable key into the full 2527 * 64 bit KVM register ID. 2528 */ 2529 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2530 { 2531 uint64_t kvmid; 2532 2533 if (cpregid & CP_REG_AA64_MASK) { 2534 kvmid = cpregid & ~CP_REG_AA64_MASK; 2535 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2536 } else { 2537 kvmid = cpregid & ~(1 << 15); 2538 if (cpregid & (1 << 15)) { 2539 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2540 } else { 2541 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2542 } 2543 } 2544 return kvmid; 2545 } 2546 2547 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2548 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2549 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2550 * TCG can assume the value to be constant (ie load at translate time) 2551 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2552 * indicates that the TB should not be ended after a write to this register 2553 * (the default is that the TB ends after cp writes). OVERRIDE permits 2554 * a register definition to override a previous definition for the 2555 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2556 * old must have the OVERRIDE bit set. 2557 * ALIAS indicates that this register is an alias view of some underlying 2558 * state which is also visible via another register, and that the other 2559 * register is handling migration and reset; registers marked ALIAS will not be 2560 * migrated but may have their state set by syncing of register state from KVM. 2561 * NO_RAW indicates that this register has no underlying state and does not 2562 * support raw access for state saving/loading; it will not be used for either 2563 * migration or KVM state synchronization. (Typically this is for "registers" 2564 * which are actually used as instructions for cache maintenance and so on.) 2565 * IO indicates that this register does I/O and therefore its accesses 2566 * need to be marked with gen_io_start() and also end the TB. In particular, 2567 * registers which implement clocks or timers require this. 2568 * RAISES_EXC is for when the read or write hook might raise an exception; 2569 * the generated code will synchronize the CPU state before calling the hook 2570 * so that it is safe for the hook to call raise_exception(). 2571 * NEWEL is for writes to registers that might change the exception 2572 * level - typically on older ARM chips. For those cases we need to 2573 * re-read the new el when recomputing the translation flags. 2574 */ 2575 #define ARM_CP_SPECIAL 0x0001 2576 #define ARM_CP_CONST 0x0002 2577 #define ARM_CP_64BIT 0x0004 2578 #define ARM_CP_SUPPRESS_TB_END 0x0008 2579 #define ARM_CP_OVERRIDE 0x0010 2580 #define ARM_CP_ALIAS 0x0020 2581 #define ARM_CP_IO 0x0040 2582 #define ARM_CP_NO_RAW 0x0080 2583 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2584 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2585 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2586 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2587 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2588 #define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) 2589 #define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) 2590 #define ARM_LAST_SPECIAL ARM_CP_DC_GZVA 2591 #define ARM_CP_FPU 0x1000 2592 #define ARM_CP_SVE 0x2000 2593 #define ARM_CP_NO_GDB 0x4000 2594 #define ARM_CP_RAISES_EXC 0x8000 2595 #define ARM_CP_NEWEL 0x10000 2596 /* Used only as a terminator for ARMCPRegInfo lists */ 2597 #define ARM_CP_SENTINEL 0xfffff 2598 /* Mask of only the flag bits in a type field */ 2599 #define ARM_CP_FLAG_MASK 0x1f0ff 2600 2601 /* Valid values for ARMCPRegInfo state field, indicating which of 2602 * the AArch32 and AArch64 execution states this register is visible in. 2603 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2604 * If the reginfo is declared to be visible in both states then a second 2605 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2606 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2607 * Note that we rely on the values of these enums as we iterate through 2608 * the various states in some places. 2609 */ 2610 enum { 2611 ARM_CP_STATE_AA32 = 0, 2612 ARM_CP_STATE_AA64 = 1, 2613 ARM_CP_STATE_BOTH = 2, 2614 }; 2615 2616 /* ARM CP register secure state flags. These flags identify security state 2617 * attributes for a given CP register entry. 2618 * The existence of both or neither secure and non-secure flags indicates that 2619 * the register has both a secure and non-secure hash entry. A single one of 2620 * these flags causes the register to only be hashed for the specified 2621 * security state. 2622 * Although definitions may have any combination of the S/NS bits, each 2623 * registered entry will only have one to identify whether the entry is secure 2624 * or non-secure. 2625 */ 2626 enum { 2627 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2628 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2629 }; 2630 2631 /* Return true if cptype is a valid type field. This is used to try to 2632 * catch errors where the sentinel has been accidentally left off the end 2633 * of a list of registers. 2634 */ 2635 static inline bool cptype_valid(int cptype) 2636 { 2637 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2638 || ((cptype & ARM_CP_SPECIAL) && 2639 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2640 } 2641 2642 /* Access rights: 2643 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2644 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2645 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2646 * (ie any of the privileged modes in Secure state, or Monitor mode). 2647 * If a register is accessible in one privilege level it's always accessible 2648 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2649 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2650 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2651 * terminology a little and call this PL3. 2652 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2653 * with the ELx exception levels. 2654 * 2655 * If access permissions for a register are more complex than can be 2656 * described with these bits, then use a laxer set of restrictions, and 2657 * do the more restrictive/complex check inside a helper function. 2658 */ 2659 #define PL3_R 0x80 2660 #define PL3_W 0x40 2661 #define PL2_R (0x20 | PL3_R) 2662 #define PL2_W (0x10 | PL3_W) 2663 #define PL1_R (0x08 | PL2_R) 2664 #define PL1_W (0x04 | PL2_W) 2665 #define PL0_R (0x02 | PL1_R) 2666 #define PL0_W (0x01 | PL1_W) 2667 2668 /* 2669 * For user-mode some registers are accessible to EL0 via a kernel 2670 * trap-and-emulate ABI. In this case we define the read permissions 2671 * as actually being PL0_R. However some bits of any given register 2672 * may still be masked. 2673 */ 2674 #ifdef CONFIG_USER_ONLY 2675 #define PL0U_R PL0_R 2676 #else 2677 #define PL0U_R PL1_R 2678 #endif 2679 2680 #define PL3_RW (PL3_R | PL3_W) 2681 #define PL2_RW (PL2_R | PL2_W) 2682 #define PL1_RW (PL1_R | PL1_W) 2683 #define PL0_RW (PL0_R | PL0_W) 2684 2685 /* Return the highest implemented Exception Level */ 2686 static inline int arm_highest_el(CPUARMState *env) 2687 { 2688 if (arm_feature(env, ARM_FEATURE_EL3)) { 2689 return 3; 2690 } 2691 if (arm_feature(env, ARM_FEATURE_EL2)) { 2692 return 2; 2693 } 2694 return 1; 2695 } 2696 2697 /* Return true if a v7M CPU is in Handler mode */ 2698 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2699 { 2700 return env->v7m.exception != 0; 2701 } 2702 2703 /* Return the current Exception Level (as per ARMv8; note that this differs 2704 * from the ARMv7 Privilege Level). 2705 */ 2706 static inline int arm_current_el(CPUARMState *env) 2707 { 2708 if (arm_feature(env, ARM_FEATURE_M)) { 2709 return arm_v7m_is_handler_mode(env) || 2710 !(env->v7m.control[env->v7m.secure] & 1); 2711 } 2712 2713 if (is_a64(env)) { 2714 return extract32(env->pstate, 2, 2); 2715 } 2716 2717 switch (env->uncached_cpsr & 0x1f) { 2718 case ARM_CPU_MODE_USR: 2719 return 0; 2720 case ARM_CPU_MODE_HYP: 2721 return 2; 2722 case ARM_CPU_MODE_MON: 2723 return 3; 2724 default: 2725 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2726 /* If EL3 is 32-bit then all secure privileged modes run in 2727 * EL3 2728 */ 2729 return 3; 2730 } 2731 2732 return 1; 2733 } 2734 } 2735 2736 typedef struct ARMCPRegInfo ARMCPRegInfo; 2737 2738 typedef enum CPAccessResult { 2739 /* Access is permitted */ 2740 CP_ACCESS_OK = 0, 2741 /* Access fails due to a configurable trap or enable which would 2742 * result in a categorized exception syndrome giving information about 2743 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2744 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2745 * PL1 if in EL0, otherwise to the current EL). 2746 */ 2747 CP_ACCESS_TRAP = 1, 2748 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2749 * Note that this is not a catch-all case -- the set of cases which may 2750 * result in this failure is specifically defined by the architecture. 2751 */ 2752 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2753 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2754 CP_ACCESS_TRAP_EL2 = 3, 2755 CP_ACCESS_TRAP_EL3 = 4, 2756 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2757 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2758 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2759 /* Access fails and results in an exception syndrome for an FP access, 2760 * trapped directly to EL2 or EL3 2761 */ 2762 CP_ACCESS_TRAP_FP_EL2 = 7, 2763 CP_ACCESS_TRAP_FP_EL3 = 8, 2764 } CPAccessResult; 2765 2766 /* Access functions for coprocessor registers. These cannot fail and 2767 * may not raise exceptions. 2768 */ 2769 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2770 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2771 uint64_t value); 2772 /* Access permission check functions for coprocessor registers. */ 2773 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2774 const ARMCPRegInfo *opaque, 2775 bool isread); 2776 /* Hook function for register reset */ 2777 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2778 2779 #define CP_ANY 0xff 2780 2781 /* Definition of an ARM coprocessor register */ 2782 struct ARMCPRegInfo { 2783 /* Name of register (useful mainly for debugging, need not be unique) */ 2784 const char *name; 2785 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2786 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2787 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2788 * will be decoded to this register. The register read and write 2789 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2790 * used by the program, so it is possible to register a wildcard and 2791 * then behave differently on read/write if necessary. 2792 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2793 * must both be zero. 2794 * For AArch64-visible registers, opc0 is also used. 2795 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2796 * way to distinguish (for KVM's benefit) guest-visible system registers 2797 * from demuxed ones provided to preserve the "no side effects on 2798 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2799 * visible (to match KVM's encoding); cp==0 will be converted to 2800 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2801 */ 2802 uint8_t cp; 2803 uint8_t crn; 2804 uint8_t crm; 2805 uint8_t opc0; 2806 uint8_t opc1; 2807 uint8_t opc2; 2808 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2809 int state; 2810 /* Register type: ARM_CP_* bits/values */ 2811 int type; 2812 /* Access rights: PL*_[RW] */ 2813 int access; 2814 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2815 int secure; 2816 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2817 * this register was defined: can be used to hand data through to the 2818 * register read/write functions, since they are passed the ARMCPRegInfo*. 2819 */ 2820 void *opaque; 2821 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2822 * fieldoffset is non-zero, the reset value of the register. 2823 */ 2824 uint64_t resetvalue; 2825 /* Offset of the field in CPUARMState for this register. 2826 * 2827 * This is not needed if either: 2828 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2829 * 2. both readfn and writefn are specified 2830 */ 2831 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2832 2833 /* Offsets of the secure and non-secure fields in CPUARMState for the 2834 * register if it is banked. These fields are only used during the static 2835 * registration of a register. During hashing the bank associated 2836 * with a given security state is copied to fieldoffset which is used from 2837 * there on out. 2838 * 2839 * It is expected that register definitions use either fieldoffset or 2840 * bank_fieldoffsets in the definition but not both. It is also expected 2841 * that both bank offsets are set when defining a banked register. This 2842 * use indicates that a register is banked. 2843 */ 2844 ptrdiff_t bank_fieldoffsets[2]; 2845 2846 /* Function for making any access checks for this register in addition to 2847 * those specified by the 'access' permissions bits. If NULL, no extra 2848 * checks required. The access check is performed at runtime, not at 2849 * translate time. 2850 */ 2851 CPAccessFn *accessfn; 2852 /* Function for handling reads of this register. If NULL, then reads 2853 * will be done by loading from the offset into CPUARMState specified 2854 * by fieldoffset. 2855 */ 2856 CPReadFn *readfn; 2857 /* Function for handling writes of this register. If NULL, then writes 2858 * will be done by writing to the offset into CPUARMState specified 2859 * by fieldoffset. 2860 */ 2861 CPWriteFn *writefn; 2862 /* Function for doing a "raw" read; used when we need to copy 2863 * coprocessor state to the kernel for KVM or out for 2864 * migration. This only needs to be provided if there is also a 2865 * readfn and it has side effects (for instance clear-on-read bits). 2866 */ 2867 CPReadFn *raw_readfn; 2868 /* Function for doing a "raw" write; used when we need to copy KVM 2869 * kernel coprocessor state into userspace, or for inbound 2870 * migration. This only needs to be provided if there is also a 2871 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2872 * or similar behaviour. 2873 */ 2874 CPWriteFn *raw_writefn; 2875 /* Function for resetting the register. If NULL, then reset will be done 2876 * by writing resetvalue to the field specified in fieldoffset. If 2877 * fieldoffset is 0 then no reset will be done. 2878 */ 2879 CPResetFn *resetfn; 2880 2881 /* 2882 * "Original" writefn and readfn. 2883 * For ARMv8.1-VHE register aliases, we overwrite the read/write 2884 * accessor functions of various EL1/EL0 to perform the runtime 2885 * check for which sysreg should actually be modified, and then 2886 * forwards the operation. Before overwriting the accessors, 2887 * the original function is copied here, so that accesses that 2888 * really do go to the EL1/EL0 version proceed normally. 2889 * (The corresponding EL2 register is linked via opaque.) 2890 */ 2891 CPReadFn *orig_readfn; 2892 CPWriteFn *orig_writefn; 2893 }; 2894 2895 /* Macros which are lvalues for the field in CPUARMState for the 2896 * ARMCPRegInfo *ri. 2897 */ 2898 #define CPREG_FIELD32(env, ri) \ 2899 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2900 #define CPREG_FIELD64(env, ri) \ 2901 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2902 2903 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2904 2905 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2906 const ARMCPRegInfo *regs, void *opaque); 2907 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2908 const ARMCPRegInfo *regs, void *opaque); 2909 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2910 { 2911 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2912 } 2913 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2914 { 2915 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2916 } 2917 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2918 2919 /* 2920 * Definition of an ARM co-processor register as viewed from 2921 * userspace. This is used for presenting sanitised versions of 2922 * registers to userspace when emulating the Linux AArch64 CPU 2923 * ID/feature ABI (advertised as HWCAP_CPUID). 2924 */ 2925 typedef struct ARMCPRegUserSpaceInfo { 2926 /* Name of register */ 2927 const char *name; 2928 2929 /* Is the name actually a glob pattern */ 2930 bool is_glob; 2931 2932 /* Only some bits are exported to user space */ 2933 uint64_t exported_bits; 2934 2935 /* Fixed bits are applied after the mask */ 2936 uint64_t fixed_bits; 2937 } ARMCPRegUserSpaceInfo; 2938 2939 #define REGUSERINFO_SENTINEL { .name = NULL } 2940 2941 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2942 2943 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2944 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2945 uint64_t value); 2946 /* CPReadFn that can be used for read-as-zero behaviour */ 2947 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2948 2949 /* CPResetFn that does nothing, for use if no reset is required even 2950 * if fieldoffset is non zero. 2951 */ 2952 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2953 2954 /* Return true if this reginfo struct's field in the cpu state struct 2955 * is 64 bits wide. 2956 */ 2957 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2958 { 2959 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2960 } 2961 2962 static inline bool cp_access_ok(int current_el, 2963 const ARMCPRegInfo *ri, int isread) 2964 { 2965 return (ri->access >> ((current_el * 2) + isread)) & 1; 2966 } 2967 2968 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2969 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2970 2971 /** 2972 * write_list_to_cpustate 2973 * @cpu: ARMCPU 2974 * 2975 * For each register listed in the ARMCPU cpreg_indexes list, write 2976 * its value from the cpreg_values list into the ARMCPUState structure. 2977 * This updates TCG's working data structures from KVM data or 2978 * from incoming migration state. 2979 * 2980 * Returns: true if all register values were updated correctly, 2981 * false if some register was unknown or could not be written. 2982 * Note that we do not stop early on failure -- we will attempt 2983 * writing all registers in the list. 2984 */ 2985 bool write_list_to_cpustate(ARMCPU *cpu); 2986 2987 /** 2988 * write_cpustate_to_list: 2989 * @cpu: ARMCPU 2990 * @kvm_sync: true if this is for syncing back to KVM 2991 * 2992 * For each register listed in the ARMCPU cpreg_indexes list, write 2993 * its value from the ARMCPUState structure into the cpreg_values list. 2994 * This is used to copy info from TCG's working data structures into 2995 * KVM or for outbound migration. 2996 * 2997 * @kvm_sync is true if we are doing this in order to sync the 2998 * register state back to KVM. In this case we will only update 2999 * values in the list if the previous list->cpustate sync actually 3000 * successfully wrote the CPU state. Otherwise we will keep the value 3001 * that is in the list. 3002 * 3003 * Returns: true if all register values were read correctly, 3004 * false if some register was unknown or could not be read. 3005 * Note that we do not stop early on failure -- we will attempt 3006 * reading all registers in the list. 3007 */ 3008 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 3009 3010 #define ARM_CPUID_TI915T 0x54029152 3011 #define ARM_CPUID_TI925T 0x54029252 3012 3013 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 3014 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 3015 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 3016 3017 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 3018 3019 #define cpu_list arm_cpu_list 3020 3021 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 3022 * 3023 * If EL3 is 64-bit: 3024 * + NonSecure EL1 & 0 stage 1 3025 * + NonSecure EL1 & 0 stage 2 3026 * + NonSecure EL2 3027 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 3028 * + Secure EL1 & 0 3029 * + Secure EL3 3030 * If EL3 is 32-bit: 3031 * + NonSecure PL1 & 0 stage 1 3032 * + NonSecure PL1 & 0 stage 2 3033 * + NonSecure PL2 3034 * + Secure PL0 3035 * + Secure PL1 3036 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 3037 * 3038 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 3039 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 3040 * because they may differ in access permissions even if the VA->PA map is 3041 * the same 3042 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 3043 * translation, which means that we have one mmu_idx that deals with two 3044 * concatenated translation regimes [this sort of combined s1+2 TLB is 3045 * architecturally permitted] 3046 * 3. we don't need to allocate an mmu_idx to translations that we won't be 3047 * handling via the TLB. The only way to do a stage 1 translation without 3048 * the immediate stage 2 translation is via the ATS or AT system insns, 3049 * which can be slow-pathed and always do a page table walk. 3050 * The only use of stage 2 translations is either as part of an s1+2 3051 * lookup or when loading the descriptors during a stage 1 page table walk, 3052 * and in both those cases we don't use the TLB. 3053 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 3054 * translation regimes, because they map reasonably well to each other 3055 * and they can't both be active at the same time. 3056 * 5. we want to be able to use the TLB for accesses done as part of a 3057 * stage1 page table walk, rather than having to walk the stage2 page 3058 * table over and over. 3059 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 3060 * Never (PAN) bit within PSTATE. 3061 * 3062 * This gives us the following list of cases: 3063 * 3064 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 3065 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 3066 * NS EL1 EL1&0 stage 1+2 +PAN 3067 * NS EL0 EL2&0 3068 * NS EL2 EL2&0 3069 * NS EL2 EL2&0 +PAN 3070 * NS EL2 (aka NS PL2) 3071 * S EL0 EL1&0 (aka S PL0) 3072 * S EL1 EL1&0 (not used if EL3 is 32 bit) 3073 * S EL1 EL1&0 +PAN 3074 * S EL3 (aka S PL1) 3075 * 3076 * for a total of 11 different mmu_idx. 3077 * 3078 * R profile CPUs have an MPU, but can use the same set of MMU indexes 3079 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 3080 * NS EL2 if we ever model a Cortex-R52). 3081 * 3082 * M profile CPUs are rather different as they do not have a true MMU. 3083 * They have the following different MMU indexes: 3084 * User 3085 * Privileged 3086 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 3087 * Privileged, execution priority negative (ditto) 3088 * If the CPU supports the v8M Security Extension then there are also: 3089 * Secure User 3090 * Secure Privileged 3091 * Secure User, execution priority negative 3092 * Secure Privileged, execution priority negative 3093 * 3094 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 3095 * are not quite the same -- different CPU types (most notably M profile 3096 * vs A/R profile) would like to use MMU indexes with different semantics, 3097 * but since we don't ever need to use all of those in a single CPU we 3098 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 3099 * modes + total number of M profile MMU modes". The lower bits of 3100 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 3101 * the same for any particular CPU. 3102 * Variables of type ARMMUIdx are always full values, and the core 3103 * index values are in variables of type 'int'. 3104 * 3105 * Our enumeration includes at the end some entries which are not "true" 3106 * mmu_idx values in that they don't have corresponding TLBs and are only 3107 * valid for doing slow path page table walks. 3108 * 3109 * The constant names here are patterned after the general style of the names 3110 * of the AT/ATS operations. 3111 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 3112 * For M profile we arrange them to have a bit for priv, a bit for negpri 3113 * and a bit for secure. 3114 */ 3115 #define ARM_MMU_IDX_A 0x10 /* A profile */ 3116 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 3117 #define ARM_MMU_IDX_M 0x40 /* M profile */ 3118 3119 /* Meanings of the bits for A profile mmu idx values */ 3120 #define ARM_MMU_IDX_A_NS 0x8 3121 3122 /* Meanings of the bits for M profile mmu idx values */ 3123 #define ARM_MMU_IDX_M_PRIV 0x1 3124 #define ARM_MMU_IDX_M_NEGPRI 0x2 3125 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 3126 3127 #define ARM_MMU_IDX_TYPE_MASK \ 3128 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 3129 #define ARM_MMU_IDX_COREIDX_MASK 0xf 3130 3131 typedef enum ARMMMUIdx { 3132 /* 3133 * A-profile. 3134 */ 3135 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, 3136 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, 3137 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, 3138 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, 3139 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, 3140 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, 3141 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, 3142 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, 3143 3144 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, 3145 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, 3146 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, 3147 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, 3148 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, 3149 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, 3150 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, 3151 3152 /* 3153 * These are not allocated TLBs and are used only for AT system 3154 * instructions or for the first stage of an S12 page table walk. 3155 */ 3156 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 3157 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 3158 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 3159 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, 3160 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, 3161 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, 3162 /* 3163 * Not allocated a TLB: used only for second stage of an S12 page 3164 * table walk, or for descriptor loads during first stage of an S1 3165 * page table walk. Note that if we ever want to have a TLB for this 3166 * then various TLB flush insns which currently are no-ops or flush 3167 * only stage 1 MMU indexes will need to change to flush stage 2. 3168 */ 3169 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, 3170 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, 3171 3172 /* 3173 * M-profile. 3174 */ 3175 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 3176 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 3177 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 3178 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 3179 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 3180 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 3181 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 3182 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 3183 } ARMMMUIdx; 3184 3185 /* 3186 * Bit macros for the core-mmu-index values for each index, 3187 * for use when calling tlb_flush_by_mmuidx() and friends. 3188 */ 3189 #define TO_CORE_BIT(NAME) \ 3190 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 3191 3192 typedef enum ARMMMUIdxBit { 3193 TO_CORE_BIT(E10_0), 3194 TO_CORE_BIT(E20_0), 3195 TO_CORE_BIT(E10_1), 3196 TO_CORE_BIT(E10_1_PAN), 3197 TO_CORE_BIT(E2), 3198 TO_CORE_BIT(E20_2), 3199 TO_CORE_BIT(E20_2_PAN), 3200 TO_CORE_BIT(SE10_0), 3201 TO_CORE_BIT(SE20_0), 3202 TO_CORE_BIT(SE10_1), 3203 TO_CORE_BIT(SE20_2), 3204 TO_CORE_BIT(SE10_1_PAN), 3205 TO_CORE_BIT(SE20_2_PAN), 3206 TO_CORE_BIT(SE2), 3207 TO_CORE_BIT(SE3), 3208 3209 TO_CORE_BIT(MUser), 3210 TO_CORE_BIT(MPriv), 3211 TO_CORE_BIT(MUserNegPri), 3212 TO_CORE_BIT(MPrivNegPri), 3213 TO_CORE_BIT(MSUser), 3214 TO_CORE_BIT(MSPriv), 3215 TO_CORE_BIT(MSUserNegPri), 3216 TO_CORE_BIT(MSPrivNegPri), 3217 } ARMMMUIdxBit; 3218 3219 #undef TO_CORE_BIT 3220 3221 #define MMU_USER_IDX 0 3222 3223 /* Indexes used when registering address spaces with cpu_address_space_init */ 3224 typedef enum ARMASIdx { 3225 ARMASIdx_NS = 0, 3226 ARMASIdx_S = 1, 3227 ARMASIdx_TagNS = 2, 3228 ARMASIdx_TagS = 3, 3229 } ARMASIdx; 3230 3231 /* Return the Exception Level targeted by debug exceptions. */ 3232 static inline int arm_debug_target_el(CPUARMState *env) 3233 { 3234 bool secure = arm_is_secure(env); 3235 bool route_to_el2 = false; 3236 3237 if (arm_is_el2_enabled(env)) { 3238 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 3239 env->cp15.mdcr_el2 & MDCR_TDE; 3240 } 3241 3242 if (route_to_el2) { 3243 return 2; 3244 } else if (arm_feature(env, ARM_FEATURE_EL3) && 3245 !arm_el_is_aa64(env, 3) && secure) { 3246 return 3; 3247 } else { 3248 return 1; 3249 } 3250 } 3251 3252 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3253 { 3254 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3255 * CSSELR is RAZ/WI. 3256 */ 3257 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3258 } 3259 3260 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 3261 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 3262 { 3263 int cur_el = arm_current_el(env); 3264 int debug_el; 3265 3266 if (cur_el == 3) { 3267 return false; 3268 } 3269 3270 /* MDCR_EL3.SDD disables debug events from Secure state */ 3271 if (arm_is_secure_below_el3(env) 3272 && extract32(env->cp15.mdcr_el3, 16, 1)) { 3273 return false; 3274 } 3275 3276 /* 3277 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 3278 * while not masking the (D)ebug bit in DAIF. 3279 */ 3280 debug_el = arm_debug_target_el(env); 3281 3282 if (cur_el == debug_el) { 3283 return extract32(env->cp15.mdscr_el1, 13, 1) 3284 && !(env->daif & PSTATE_D); 3285 } 3286 3287 /* Otherwise the debug target needs to be a higher EL */ 3288 return debug_el > cur_el; 3289 } 3290 3291 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 3292 { 3293 int el = arm_current_el(env); 3294 3295 if (el == 0 && arm_el_is_aa64(env, 1)) { 3296 return aa64_generate_debug_exceptions(env); 3297 } 3298 3299 if (arm_is_secure(env)) { 3300 int spd; 3301 3302 if (el == 0 && (env->cp15.sder & 1)) { 3303 /* SDER.SUIDEN means debug exceptions from Secure EL0 3304 * are always enabled. Otherwise they are controlled by 3305 * SDCR.SPD like those from other Secure ELs. 3306 */ 3307 return true; 3308 } 3309 3310 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3311 switch (spd) { 3312 case 1: 3313 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3314 case 0: 3315 /* For 0b00 we return true if external secure invasive debug 3316 * is enabled. On real hardware this is controlled by external 3317 * signals to the core. QEMU always permits debug, and behaves 3318 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3319 */ 3320 return true; 3321 case 2: 3322 return false; 3323 case 3: 3324 return true; 3325 } 3326 } 3327 3328 return el != 2; 3329 } 3330 3331 /* Return true if debugging exceptions are currently enabled. 3332 * This corresponds to what in ARM ARM pseudocode would be 3333 * if UsingAArch32() then 3334 * return AArch32.GenerateDebugExceptions() 3335 * else 3336 * return AArch64.GenerateDebugExceptions() 3337 * We choose to push the if() down into this function for clarity, 3338 * since the pseudocode has it at all callsites except for the one in 3339 * CheckSoftwareStep(), where it is elided because both branches would 3340 * always return the same value. 3341 */ 3342 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3343 { 3344 if (env->aarch64) { 3345 return aa64_generate_debug_exceptions(env); 3346 } else { 3347 return aa32_generate_debug_exceptions(env); 3348 } 3349 } 3350 3351 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3352 * implicitly means this always returns false in pre-v8 CPUs.) 3353 */ 3354 static inline bool arm_singlestep_active(CPUARMState *env) 3355 { 3356 return extract32(env->cp15.mdscr_el1, 0, 1) 3357 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3358 && arm_generate_debug_exceptions(env); 3359 } 3360 3361 static inline bool arm_sctlr_b(CPUARMState *env) 3362 { 3363 return 3364 /* We need not implement SCTLR.ITD in user-mode emulation, so 3365 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3366 * This lets people run BE32 binaries with "-cpu any". 3367 */ 3368 #ifndef CONFIG_USER_ONLY 3369 !arm_feature(env, ARM_FEATURE_V7) && 3370 #endif 3371 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3372 } 3373 3374 uint64_t arm_sctlr(CPUARMState *env, int el); 3375 3376 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3377 bool sctlr_b) 3378 { 3379 #ifdef CONFIG_USER_ONLY 3380 /* 3381 * In system mode, BE32 is modelled in line with the 3382 * architecture (as word-invariant big-endianness), where loads 3383 * and stores are done little endian but from addresses which 3384 * are adjusted by XORing with the appropriate constant. So the 3385 * endianness to use for the raw data access is not affected by 3386 * SCTLR.B. 3387 * In user mode, however, we model BE32 as byte-invariant 3388 * big-endianness (because user-only code cannot tell the 3389 * difference), and so we need to use a data access endianness 3390 * that depends on SCTLR.B. 3391 */ 3392 if (sctlr_b) { 3393 return true; 3394 } 3395 #endif 3396 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3397 return env->uncached_cpsr & CPSR_E; 3398 } 3399 3400 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3401 { 3402 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3403 } 3404 3405 /* Return true if the processor is in big-endian mode. */ 3406 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3407 { 3408 if (!is_a64(env)) { 3409 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3410 } else { 3411 int cur_el = arm_current_el(env); 3412 uint64_t sctlr = arm_sctlr(env, cur_el); 3413 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3414 } 3415 } 3416 3417 #include "exec/cpu-all.h" 3418 3419 /* 3420 * We have more than 32-bits worth of state per TB, so we split the data 3421 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3422 * We collect these two parts in CPUARMTBFlags where they are named 3423 * flags and flags2 respectively. 3424 * 3425 * The flags that are shared between all execution modes, TBFLAG_ANY, 3426 * are stored in flags. The flags that are specific to a given mode 3427 * are stores in flags2. Since cs_base is sized on the configured 3428 * address size, flags2 always has 64-bits for A64, and a minimum of 3429 * 32-bits for A32 and M32. 3430 * 3431 * The bits for 32-bit A-profile and M-profile partially overlap: 3432 * 3433 * 31 23 11 10 0 3434 * +-------------+----------+----------------+ 3435 * | | | TBFLAG_A32 | 3436 * | TBFLAG_AM32 | +-----+----------+ 3437 * | | |TBFLAG_M32| 3438 * +-------------+----------------+----------+ 3439 * 31 23 6 5 0 3440 * 3441 * Unless otherwise noted, these bits are cached in env->hflags. 3442 */ 3443 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3444 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3445 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3446 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3447 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3448 /* Target EL if we take a floating-point-disabled exception */ 3449 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3450 /* For A-profile only, target EL for debug exceptions. */ 3451 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) 3452 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3453 FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) 3454 FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1) 3455 3456 /* 3457 * Bit usage when in AArch32 state, both A- and M-profile. 3458 */ 3459 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3460 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3461 3462 /* 3463 * Bit usage when in AArch32 state, for A-profile only. 3464 */ 3465 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3466 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3467 /* 3468 * We store the bottom two bits of the CPAR as TB flags and handle 3469 * checks on the other bits at runtime. This shares the same bits as 3470 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3471 * Not cached, because VECLEN+VECSTRIDE are not cached. 3472 */ 3473 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3474 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3475 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3476 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3477 /* 3478 * Indicates whether cp register reads and writes by guest code should access 3479 * the secure or nonsecure bank of banked registers; note that this is not 3480 * the same thing as the current security state of the processor! 3481 */ 3482 FIELD(TBFLAG_A32, NS, 10, 1) 3483 3484 /* 3485 * Bit usage when in AArch32 state, for M-profile only. 3486 */ 3487 /* Handler (ie not Thread) mode */ 3488 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3489 /* Whether we should generate stack-limit checks */ 3490 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3491 /* Set if FPCCR.LSPACT is set */ 3492 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3493 /* Set if we must create a new FP context */ 3494 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3495 /* Set if FPCCR.S does not match current security state */ 3496 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3497 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3498 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3499 3500 /* 3501 * Bit usage when in AArch64 state 3502 */ 3503 FIELD(TBFLAG_A64, TBII, 0, 2) 3504 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3505 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3506 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3507 FIELD(TBFLAG_A64, BT, 9, 1) 3508 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3509 FIELD(TBFLAG_A64, TBID, 12, 2) 3510 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3511 FIELD(TBFLAG_A64, ATA, 15, 1) 3512 FIELD(TBFLAG_A64, TCMA, 16, 2) 3513 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3514 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3515 3516 /* 3517 * Helpers for using the above. 3518 */ 3519 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3520 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3521 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3522 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3523 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3524 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3525 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3526 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3527 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3528 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3529 3530 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3531 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3532 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3533 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3534 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3535 3536 /** 3537 * cpu_mmu_index: 3538 * @env: The cpu environment 3539 * @ifetch: True for code access, false for data access. 3540 * 3541 * Return the core mmu index for the current translation regime. 3542 * This function is used by generic TCG code paths. 3543 */ 3544 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3545 { 3546 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3547 } 3548 3549 static inline bool bswap_code(bool sctlr_b) 3550 { 3551 #ifdef CONFIG_USER_ONLY 3552 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3553 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3554 * would also end up as a mixed-endian mode with BE code, LE data. 3555 */ 3556 return 3557 #ifdef TARGET_WORDS_BIGENDIAN 3558 1 ^ 3559 #endif 3560 sctlr_b; 3561 #else 3562 /* All code access in ARM is little endian, and there are no loaders 3563 * doing swaps that need to be reversed 3564 */ 3565 return 0; 3566 #endif 3567 } 3568 3569 #ifdef CONFIG_USER_ONLY 3570 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3571 { 3572 return 3573 #ifdef TARGET_WORDS_BIGENDIAN 3574 1 ^ 3575 #endif 3576 arm_cpu_data_is_big_endian(env); 3577 } 3578 #endif 3579 3580 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3581 target_ulong *cs_base, uint32_t *flags); 3582 3583 enum { 3584 QEMU_PSCI_CONDUIT_DISABLED = 0, 3585 QEMU_PSCI_CONDUIT_SMC = 1, 3586 QEMU_PSCI_CONDUIT_HVC = 2, 3587 }; 3588 3589 #ifndef CONFIG_USER_ONLY 3590 /* Return the address space index to use for a memory access */ 3591 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3592 { 3593 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3594 } 3595 3596 /* Return the AddressSpace to use for a memory access 3597 * (which depends on whether the access is S or NS, and whether 3598 * the board gave us a separate AddressSpace for S accesses). 3599 */ 3600 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3601 { 3602 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3603 } 3604 #endif 3605 3606 /** 3607 * arm_register_pre_el_change_hook: 3608 * Register a hook function which will be called immediately before this 3609 * CPU changes exception level or mode. The hook function will be 3610 * passed a pointer to the ARMCPU and the opaque data pointer passed 3611 * to this function when the hook was registered. 3612 * 3613 * Note that if a pre-change hook is called, any registered post-change hooks 3614 * are guaranteed to subsequently be called. 3615 */ 3616 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3617 void *opaque); 3618 /** 3619 * arm_register_el_change_hook: 3620 * Register a hook function which will be called immediately after this 3621 * CPU changes exception level or mode. The hook function will be 3622 * passed a pointer to the ARMCPU and the opaque data pointer passed 3623 * to this function when the hook was registered. 3624 * 3625 * Note that any registered hooks registered here are guaranteed to be called 3626 * if pre-change hooks have been. 3627 */ 3628 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3629 *opaque); 3630 3631 /** 3632 * arm_rebuild_hflags: 3633 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3634 */ 3635 void arm_rebuild_hflags(CPUARMState *env); 3636 3637 /** 3638 * aa32_vfp_dreg: 3639 * Return a pointer to the Dn register within env in 32-bit mode. 3640 */ 3641 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3642 { 3643 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3644 } 3645 3646 /** 3647 * aa32_vfp_qreg: 3648 * Return a pointer to the Qn register within env in 32-bit mode. 3649 */ 3650 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3651 { 3652 return &env->vfp.zregs[regno].d[0]; 3653 } 3654 3655 /** 3656 * aa64_vfp_qreg: 3657 * Return a pointer to the Qn register within env in 64-bit mode. 3658 */ 3659 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3660 { 3661 return &env->vfp.zregs[regno].d[0]; 3662 } 3663 3664 /* Shared between translate-sve.c and sve_helper.c. */ 3665 extern const uint64_t pred_esz_masks[4]; 3666 3667 /* Helper for the macros below, validating the argument type. */ 3668 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) 3669 { 3670 return x; 3671 } 3672 3673 /* 3674 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. 3675 * Using these should be a bit more self-documenting than using the 3676 * generic target bits directly. 3677 */ 3678 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) 3679 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) 3680 3681 /* 3682 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3683 */ 3684 #define PAGE_BTI PAGE_TARGET_1 3685 #define PAGE_MTE PAGE_TARGET_2 3686 3687 #ifdef TARGET_TAGGED_ADDRESSES 3688 /** 3689 * cpu_untagged_addr: 3690 * @cs: CPU context 3691 * @x: tagged address 3692 * 3693 * Remove any address tag from @x. This is explicitly related to the 3694 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3695 * 3696 * There should be a better place to put this, but we need this in 3697 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3698 */ 3699 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3700 { 3701 ARMCPU *cpu = ARM_CPU(cs); 3702 if (cpu->env.tagged_addr_enable) { 3703 /* 3704 * TBI is enabled for userspace but not kernelspace addresses. 3705 * Only clear the tag if bit 55 is clear. 3706 */ 3707 x &= sextract64(x, 0, 56); 3708 } 3709 return x; 3710 } 3711 #endif 3712 3713 /* 3714 * Naming convention for isar_feature functions: 3715 * Functions which test 32-bit ID registers should have _aa32_ in 3716 * their name. Functions which test 64-bit ID registers should have 3717 * _aa64_ in their name. These must only be used in code where we 3718 * know for certain that the CPU has AArch32 or AArch64 respectively 3719 * or where the correct answer for a CPU which doesn't implement that 3720 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3721 * system registers that are specific to that CPU state, for "should 3722 * we let this system register bit be set" tests where the 32-bit 3723 * flavour of the register doesn't have the bit, and so on). 3724 * Functions which simply ask "does this feature exist at all" have 3725 * _any_ in their name, and always return the logical OR of the _aa64_ 3726 * and the _aa32_ function. 3727 */ 3728 3729 /* 3730 * 32-bit feature tests via id registers. 3731 */ 3732 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3733 { 3734 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3735 } 3736 3737 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3738 { 3739 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3740 } 3741 3742 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3743 { 3744 /* (M-profile) low-overhead loops and branch future */ 3745 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3746 } 3747 3748 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3749 { 3750 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3751 } 3752 3753 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3754 { 3755 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3756 } 3757 3758 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3759 { 3760 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3761 } 3762 3763 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3764 { 3765 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3766 } 3767 3768 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3769 { 3770 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3771 } 3772 3773 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3774 { 3775 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3776 } 3777 3778 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3779 { 3780 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3781 } 3782 3783 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3784 { 3785 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3786 } 3787 3788 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3789 { 3790 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3791 } 3792 3793 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3794 { 3795 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3796 } 3797 3798 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3799 { 3800 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3801 } 3802 3803 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3804 { 3805 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3806 } 3807 3808 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3809 { 3810 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3811 } 3812 3813 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3814 { 3815 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3816 } 3817 3818 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3819 { 3820 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3821 } 3822 3823 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3824 { 3825 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3826 } 3827 3828 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3829 { 3830 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3831 } 3832 3833 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3834 { 3835 /* 3836 * Return true if M-profile state handling insns 3837 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3838 */ 3839 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3840 } 3841 3842 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3843 { 3844 /* Sadly this is encoded differently for A-profile and M-profile */ 3845 if (isar_feature_aa32_mprofile(id)) { 3846 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3847 } else { 3848 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3849 } 3850 } 3851 3852 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3853 { 3854 /* 3855 * Return true if MVE is supported (either integer or floating point). 3856 * We must check for M-profile as the MVFR1 field means something 3857 * else for A-profile. 3858 */ 3859 return isar_feature_aa32_mprofile(id) && 3860 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3861 } 3862 3863 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3864 { 3865 /* 3866 * Return true if MVE is supported (either integer or floating point). 3867 * We must check for M-profile as the MVFR1 field means something 3868 * else for A-profile. 3869 */ 3870 return isar_feature_aa32_mprofile(id) && 3871 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3872 } 3873 3874 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3875 { 3876 /* 3877 * Return true if either VFP or SIMD is implemented. 3878 * In this case, a minimum of VFP w/ D0-D15. 3879 */ 3880 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3881 } 3882 3883 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3884 { 3885 /* Return true if D16-D31 are implemented */ 3886 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3887 } 3888 3889 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3890 { 3891 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3892 } 3893 3894 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3895 { 3896 /* Return true if CPU supports single precision floating point, VFPv2 */ 3897 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3898 } 3899 3900 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3901 { 3902 /* Return true if CPU supports single precision floating point, VFPv3 */ 3903 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3904 } 3905 3906 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3907 { 3908 /* Return true if CPU supports double precision floating point, VFPv2 */ 3909 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3910 } 3911 3912 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3913 { 3914 /* Return true if CPU supports double precision floating point, VFPv3 */ 3915 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3916 } 3917 3918 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3919 { 3920 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3921 } 3922 3923 /* 3924 * We always set the FP and SIMD FP16 fields to indicate identical 3925 * levels of support (assuming SIMD is implemented at all), so 3926 * we only need one set of accessors. 3927 */ 3928 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3929 { 3930 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3931 } 3932 3933 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3934 { 3935 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3936 } 3937 3938 /* 3939 * Note that this ID register field covers both VFP and Neon FMAC, 3940 * so should usually be tested in combination with some other 3941 * check that confirms the presence of whichever of VFP or Neon is 3942 * relevant, to avoid accidentally enabling a Neon feature on 3943 * a VFP-no-Neon core or vice-versa. 3944 */ 3945 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3946 { 3947 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3948 } 3949 3950 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3951 { 3952 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3953 } 3954 3955 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3956 { 3957 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3958 } 3959 3960 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3961 { 3962 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3963 } 3964 3965 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3966 { 3967 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3968 } 3969 3970 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3971 { 3972 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3973 } 3974 3975 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3976 { 3977 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3978 } 3979 3980 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3981 { 3982 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3983 } 3984 3985 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3986 { 3987 /* 0xf means "non-standard IMPDEF PMU" */ 3988 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3989 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3990 } 3991 3992 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3993 { 3994 /* 0xf means "non-standard IMPDEF PMU" */ 3995 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3996 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3997 } 3998 3999 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 4000 { 4001 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 4002 } 4003 4004 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 4005 { 4006 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 4007 } 4008 4009 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 4010 { 4011 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 4012 } 4013 4014 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 4015 { 4016 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 4017 } 4018 4019 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 4020 { 4021 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 4022 } 4023 4024 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 4025 { 4026 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 4027 } 4028 4029 /* 4030 * 64-bit feature tests via id registers. 4031 */ 4032 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 4033 { 4034 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 4035 } 4036 4037 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 4038 { 4039 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 4040 } 4041 4042 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 4043 { 4044 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 4045 } 4046 4047 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 4048 { 4049 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 4050 } 4051 4052 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 4053 { 4054 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 4055 } 4056 4057 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 4058 { 4059 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 4060 } 4061 4062 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 4063 { 4064 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 4065 } 4066 4067 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 4068 { 4069 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 4070 } 4071 4072 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 4073 { 4074 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 4075 } 4076 4077 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 4078 { 4079 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 4080 } 4081 4082 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 4083 { 4084 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 4085 } 4086 4087 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 4088 { 4089 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 4090 } 4091 4092 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 4093 { 4094 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 4095 } 4096 4097 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 4098 { 4099 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 4100 } 4101 4102 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 4103 { 4104 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 4105 } 4106 4107 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 4108 { 4109 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 4110 } 4111 4112 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 4113 { 4114 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 4115 } 4116 4117 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 4118 { 4119 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 4120 } 4121 4122 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 4123 { 4124 /* 4125 * Return true if any form of pauth is enabled, as this 4126 * predicate controls migration of the 128-bit keys. 4127 */ 4128 return (id->id_aa64isar1 & 4129 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 4130 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 4131 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 4132 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 4133 } 4134 4135 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 4136 { 4137 /* 4138 * Return true if pauth is enabled with the architected QARMA algorithm. 4139 * QEMU will always set APA+GPA to the same value. 4140 */ 4141 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 4142 } 4143 4144 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 4145 { 4146 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 4147 } 4148 4149 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 4150 { 4151 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 4152 } 4153 4154 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 4155 { 4156 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 4157 } 4158 4159 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 4160 { 4161 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 4162 } 4163 4164 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 4165 { 4166 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 4167 } 4168 4169 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 4170 { 4171 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 4172 } 4173 4174 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 4175 { 4176 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 4177 } 4178 4179 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 4180 { 4181 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 4182 } 4183 4184 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 4185 { 4186 /* We always set the AdvSIMD and FP fields identically. */ 4187 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 4188 } 4189 4190 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 4191 { 4192 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 4193 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 4194 } 4195 4196 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 4197 { 4198 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 4199 } 4200 4201 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 4202 { 4203 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 4204 } 4205 4206 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 4207 { 4208 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 4209 } 4210 4211 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 4212 { 4213 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 4214 } 4215 4216 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 4217 { 4218 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 4219 } 4220 4221 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 4222 { 4223 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 4224 } 4225 4226 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 4227 { 4228 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 4229 } 4230 4231 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 4232 { 4233 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 4234 } 4235 4236 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 4237 { 4238 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 4239 } 4240 4241 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 4242 { 4243 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 4244 } 4245 4246 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 4247 { 4248 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 4249 } 4250 4251 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 4252 { 4253 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 4254 } 4255 4256 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 4257 { 4258 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 4259 } 4260 4261 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 4262 { 4263 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 4264 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4265 } 4266 4267 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 4268 { 4269 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 4270 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4271 } 4272 4273 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 4274 { 4275 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 4276 } 4277 4278 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 4279 { 4280 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 4281 } 4282 4283 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 4284 { 4285 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 4286 } 4287 4288 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 4289 { 4290 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 4291 } 4292 4293 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 4294 { 4295 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4296 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 4297 } 4298 4299 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 4300 { 4301 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 4302 } 4303 4304 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 4305 { 4306 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4307 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 4308 } 4309 4310 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4311 { 4312 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4313 } 4314 4315 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4316 { 4317 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4318 } 4319 4320 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4321 { 4322 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4323 } 4324 4325 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4326 { 4327 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4328 } 4329 4330 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4331 { 4332 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4333 } 4334 4335 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4336 { 4337 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4338 } 4339 4340 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4341 { 4342 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4343 } 4344 4345 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4346 { 4347 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4348 } 4349 4350 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4351 { 4352 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4353 } 4354 4355 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4356 { 4357 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4358 } 4359 4360 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4361 { 4362 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4363 } 4364 4365 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4366 { 4367 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4368 } 4369 4370 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4371 { 4372 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4373 } 4374 4375 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4376 { 4377 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4378 } 4379 4380 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4381 { 4382 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4383 } 4384 4385 /* 4386 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4387 */ 4388 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4389 { 4390 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4391 } 4392 4393 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4394 { 4395 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4396 } 4397 4398 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 4399 { 4400 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 4401 } 4402 4403 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 4404 { 4405 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 4406 } 4407 4408 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4409 { 4410 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4411 } 4412 4413 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4414 { 4415 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4416 } 4417 4418 /* 4419 * Forward to the above feature tests given an ARMCPU pointer. 4420 */ 4421 #define cpu_isar_feature(name, cpu) \ 4422 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4423 4424 #endif 4425