1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #define EXCP_UDEF 1 /* undefined instruction */ 43 #define EXCP_SWI 2 /* software interrupt */ 44 #define EXCP_PREFETCH_ABORT 3 45 #define EXCP_DATA_ABORT 4 46 #define EXCP_IRQ 5 47 #define EXCP_FIQ 6 48 #define EXCP_BKPT 7 49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 51 #define EXCP_HVC 11 /* HyperVisor Call */ 52 #define EXCP_HYP_TRAP 12 53 #define EXCP_SMC 13 /* Secure Monitor Call */ 54 #define EXCP_VIRQ 14 55 #define EXCP_VFIQ 15 56 #define EXCP_SEMIHOST 16 /* semihosting call */ 57 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 58 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 59 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 60 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 61 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 62 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 63 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 64 65 #define ARMV7M_EXCP_RESET 1 66 #define ARMV7M_EXCP_NMI 2 67 #define ARMV7M_EXCP_HARD 3 68 #define ARMV7M_EXCP_MEM 4 69 #define ARMV7M_EXCP_BUS 5 70 #define ARMV7M_EXCP_USAGE 6 71 #define ARMV7M_EXCP_SECURE 7 72 #define ARMV7M_EXCP_SVC 11 73 #define ARMV7M_EXCP_DEBUG 12 74 #define ARMV7M_EXCP_PENDSV 14 75 #define ARMV7M_EXCP_SYSTICK 15 76 77 /* For M profile, some registers are banked secure vs non-secure; 78 * these are represented as a 2-element array where the first element 79 * is the non-secure copy and the second is the secure copy. 80 * When the CPU does not have implement the security extension then 81 * only the first element is used. 82 * This means that the copy for the current security state can be 83 * accessed via env->registerfield[env->v7m.secure] (whether the security 84 * extension is implemented or not). 85 */ 86 enum { 87 M_REG_NS = 0, 88 M_REG_S = 1, 89 M_REG_NUM_BANKS = 2, 90 }; 91 92 /* ARM-specific interrupt pending bits. */ 93 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 94 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 95 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 96 97 /* The usual mapping for an AArch64 system register to its AArch32 98 * counterpart is for the 32 bit world to have access to the lower 99 * half only (with writes leaving the upper half untouched). It's 100 * therefore useful to be able to pass TCG the offset of the least 101 * significant half of a uint64_t struct member. 102 */ 103 #ifdef HOST_WORDS_BIGENDIAN 104 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 105 #define offsetofhigh32(S, M) offsetof(S, M) 106 #else 107 #define offsetoflow32(S, M) offsetof(S, M) 108 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 109 #endif 110 111 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 112 #define ARM_CPU_IRQ 0 113 #define ARM_CPU_FIQ 1 114 #define ARM_CPU_VIRQ 2 115 #define ARM_CPU_VFIQ 3 116 117 #define NB_MMU_MODES 8 118 /* ARM-specific extra insn start words: 119 * 1: Conditional execution bits 120 * 2: Partial exception syndrome for data aborts 121 */ 122 #define TARGET_INSN_START_EXTRA_WORDS 2 123 124 /* The 2nd extra word holding syndrome info for data aborts does not use 125 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 126 * help the sleb128 encoder do a better job. 127 * When restoring the CPU state, we shift it back up. 128 */ 129 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 130 #define ARM_INSN_START_WORD2_SHIFT 14 131 132 /* We currently assume float and double are IEEE single and double 133 precision respectively. 134 Doing runtime conversions is tricky because VFP registers may contain 135 integer values (eg. as the result of a FTOSI instruction). 136 s<2n> maps to the least significant half of d<n> 137 s<2n+1> maps to the most significant half of d<n> 138 */ 139 140 /** 141 * DynamicGDBXMLInfo: 142 * @desc: Contains the XML descriptions. 143 * @num_cpregs: Number of the Coprocessor registers seen by GDB. 144 * @cpregs_keys: Array that contains the corresponding Key of 145 * a given cpreg with the same order of the cpreg in the XML description. 146 */ 147 typedef struct DynamicGDBXMLInfo { 148 char *desc; 149 int num_cpregs; 150 uint32_t *cpregs_keys; 151 } DynamicGDBXMLInfo; 152 153 /* CPU state for each instance of a generic timer (in cp15 c14) */ 154 typedef struct ARMGenericTimer { 155 uint64_t cval; /* Timer CompareValue register */ 156 uint64_t ctl; /* Timer Control register */ 157 } ARMGenericTimer; 158 159 #define GTIMER_PHYS 0 160 #define GTIMER_VIRT 1 161 #define GTIMER_HYP 2 162 #define GTIMER_SEC 3 163 #define NUM_GTIMERS 4 164 165 typedef struct { 166 uint64_t raw_tcr; 167 uint32_t mask; 168 uint32_t base_mask; 169 } TCR; 170 171 /* Define a maximum sized vector register. 172 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 173 * For 64-bit, this is a 2048-bit SVE register. 174 * 175 * Note that the mapping between S, D, and Q views of the register bank 176 * differs between AArch64 and AArch32. 177 * In AArch32: 178 * Qn = regs[n].d[1]:regs[n].d[0] 179 * Dn = regs[n / 2].d[n & 1] 180 * Sn = regs[n / 4].d[n % 4 / 2], 181 * bits 31..0 for even n, and bits 63..32 for odd n 182 * (and regs[16] to regs[31] are inaccessible) 183 * In AArch64: 184 * Zn = regs[n].d[*] 185 * Qn = regs[n].d[1]:regs[n].d[0] 186 * Dn = regs[n].d[0] 187 * Sn = regs[n].d[0] bits 31..0 188 * Hn = regs[n].d[0] bits 15..0 189 * 190 * This corresponds to the architecturally defined mapping between 191 * the two execution states, and means we do not need to explicitly 192 * map these registers when changing states. 193 * 194 * Align the data for use with TCG host vector operations. 195 */ 196 197 #ifdef TARGET_AARCH64 198 # define ARM_MAX_VQ 16 199 #else 200 # define ARM_MAX_VQ 1 201 #endif 202 203 typedef struct ARMVectorReg { 204 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 205 } ARMVectorReg; 206 207 #ifdef TARGET_AARCH64 208 /* In AArch32 mode, predicate registers do not exist at all. */ 209 typedef struct ARMPredicateReg { 210 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); 211 } ARMPredicateReg; 212 213 /* In AArch32 mode, PAC keys do not exist at all. */ 214 typedef struct ARMPACKey { 215 uint64_t lo, hi; 216 } ARMPACKey; 217 #endif 218 219 220 typedef struct CPUARMState { 221 /* Regs for current mode. */ 222 uint32_t regs[16]; 223 224 /* 32/64 switch only happens when taking and returning from 225 * exceptions so the overlap semantics are taken care of then 226 * instead of having a complicated union. 227 */ 228 /* Regs for A64 mode. */ 229 uint64_t xregs[32]; 230 uint64_t pc; 231 /* PSTATE isn't an architectural register for ARMv8. However, it is 232 * convenient for us to assemble the underlying state into a 32 bit format 233 * identical to the architectural format used for the SPSR. (This is also 234 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 235 * 'pstate' register are.) Of the PSTATE bits: 236 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 237 * semantics as for AArch32, as described in the comments on each field) 238 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 239 * DAIF (exception masks) are kept in env->daif 240 * BTYPE is kept in env->btype 241 * all other bits are stored in their correct places in env->pstate 242 */ 243 uint32_t pstate; 244 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 245 246 /* Frequently accessed CPSR bits are stored separately for efficiency. 247 This contains all the other bits. Use cpsr_{read,write} to access 248 the whole CPSR. */ 249 uint32_t uncached_cpsr; 250 uint32_t spsr; 251 252 /* Banked registers. */ 253 uint64_t banked_spsr[8]; 254 uint32_t banked_r13[8]; 255 uint32_t banked_r14[8]; 256 257 /* These hold r8-r12. */ 258 uint32_t usr_regs[5]; 259 uint32_t fiq_regs[5]; 260 261 /* cpsr flag cache for faster execution */ 262 uint32_t CF; /* 0 or 1 */ 263 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 264 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 265 uint32_t ZF; /* Z set if zero. */ 266 uint32_t QF; /* 0 or 1 */ 267 uint32_t GE; /* cpsr[19:16] */ 268 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 269 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 270 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 271 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 272 273 uint64_t elr_el[4]; /* AArch64 exception link regs */ 274 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 275 276 /* System control coprocessor (cp15) */ 277 struct { 278 uint32_t c0_cpuid; 279 union { /* Cache size selection */ 280 struct { 281 uint64_t _unused_csselr0; 282 uint64_t csselr_ns; 283 uint64_t _unused_csselr1; 284 uint64_t csselr_s; 285 }; 286 uint64_t csselr_el[4]; 287 }; 288 union { /* System control register. */ 289 struct { 290 uint64_t _unused_sctlr; 291 uint64_t sctlr_ns; 292 uint64_t hsctlr; 293 uint64_t sctlr_s; 294 }; 295 uint64_t sctlr_el[4]; 296 }; 297 uint64_t cpacr_el1; /* Architectural feature access control register */ 298 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 299 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 300 uint64_t sder; /* Secure debug enable register. */ 301 uint32_t nsacr; /* Non-secure access control register. */ 302 union { /* MMU translation table base 0. */ 303 struct { 304 uint64_t _unused_ttbr0_0; 305 uint64_t ttbr0_ns; 306 uint64_t _unused_ttbr0_1; 307 uint64_t ttbr0_s; 308 }; 309 uint64_t ttbr0_el[4]; 310 }; 311 union { /* MMU translation table base 1. */ 312 struct { 313 uint64_t _unused_ttbr1_0; 314 uint64_t ttbr1_ns; 315 uint64_t _unused_ttbr1_1; 316 uint64_t ttbr1_s; 317 }; 318 uint64_t ttbr1_el[4]; 319 }; 320 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 321 /* MMU translation table base control. */ 322 TCR tcr_el[4]; 323 TCR vtcr_el2; /* Virtualization Translation Control. */ 324 uint32_t c2_data; /* MPU data cacheable bits. */ 325 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 326 union { /* MMU domain access control register 327 * MPU write buffer control. 328 */ 329 struct { 330 uint64_t dacr_ns; 331 uint64_t dacr_s; 332 }; 333 struct { 334 uint64_t dacr32_el2; 335 }; 336 }; 337 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 338 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 339 uint64_t hcr_el2; /* Hypervisor configuration register */ 340 uint64_t scr_el3; /* Secure configuration register. */ 341 union { /* Fault status registers. */ 342 struct { 343 uint64_t ifsr_ns; 344 uint64_t ifsr_s; 345 }; 346 struct { 347 uint64_t ifsr32_el2; 348 }; 349 }; 350 union { 351 struct { 352 uint64_t _unused_dfsr; 353 uint64_t dfsr_ns; 354 uint64_t hsr; 355 uint64_t dfsr_s; 356 }; 357 uint64_t esr_el[4]; 358 }; 359 uint32_t c6_region[8]; /* MPU base/size registers. */ 360 union { /* Fault address registers. */ 361 struct { 362 uint64_t _unused_far0; 363 #ifdef HOST_WORDS_BIGENDIAN 364 uint32_t ifar_ns; 365 uint32_t dfar_ns; 366 uint32_t ifar_s; 367 uint32_t dfar_s; 368 #else 369 uint32_t dfar_ns; 370 uint32_t ifar_ns; 371 uint32_t dfar_s; 372 uint32_t ifar_s; 373 #endif 374 uint64_t _unused_far3; 375 }; 376 uint64_t far_el[4]; 377 }; 378 uint64_t hpfar_el2; 379 uint64_t hstr_el2; 380 union { /* Translation result. */ 381 struct { 382 uint64_t _unused_par_0; 383 uint64_t par_ns; 384 uint64_t _unused_par_1; 385 uint64_t par_s; 386 }; 387 uint64_t par_el[4]; 388 }; 389 390 uint32_t c9_insn; /* Cache lockdown registers. */ 391 uint32_t c9_data; 392 uint64_t c9_pmcr; /* performance monitor control register */ 393 uint64_t c9_pmcnten; /* perf monitor counter enables */ 394 uint64_t c9_pmovsr; /* perf monitor overflow status */ 395 uint64_t c9_pmuserenr; /* perf monitor user enable */ 396 uint64_t c9_pmselr; /* perf monitor counter selection register */ 397 uint64_t c9_pminten; /* perf monitor interrupt enables */ 398 union { /* Memory attribute redirection */ 399 struct { 400 #ifdef HOST_WORDS_BIGENDIAN 401 uint64_t _unused_mair_0; 402 uint32_t mair1_ns; 403 uint32_t mair0_ns; 404 uint64_t _unused_mair_1; 405 uint32_t mair1_s; 406 uint32_t mair0_s; 407 #else 408 uint64_t _unused_mair_0; 409 uint32_t mair0_ns; 410 uint32_t mair1_ns; 411 uint64_t _unused_mair_1; 412 uint32_t mair0_s; 413 uint32_t mair1_s; 414 #endif 415 }; 416 uint64_t mair_el[4]; 417 }; 418 union { /* vector base address register */ 419 struct { 420 uint64_t _unused_vbar; 421 uint64_t vbar_ns; 422 uint64_t hvbar; 423 uint64_t vbar_s; 424 }; 425 uint64_t vbar_el[4]; 426 }; 427 uint32_t mvbar; /* (monitor) vector base address register */ 428 struct { /* FCSE PID. */ 429 uint32_t fcseidr_ns; 430 uint32_t fcseidr_s; 431 }; 432 union { /* Context ID. */ 433 struct { 434 uint64_t _unused_contextidr_0; 435 uint64_t contextidr_ns; 436 uint64_t _unused_contextidr_1; 437 uint64_t contextidr_s; 438 }; 439 uint64_t contextidr_el[4]; 440 }; 441 union { /* User RW Thread register. */ 442 struct { 443 uint64_t tpidrurw_ns; 444 uint64_t tpidrprw_ns; 445 uint64_t htpidr; 446 uint64_t _tpidr_el3; 447 }; 448 uint64_t tpidr_el[4]; 449 }; 450 /* The secure banks of these registers don't map anywhere */ 451 uint64_t tpidrurw_s; 452 uint64_t tpidrprw_s; 453 uint64_t tpidruro_s; 454 455 union { /* User RO Thread register. */ 456 uint64_t tpidruro_ns; 457 uint64_t tpidrro_el[1]; 458 }; 459 uint64_t c14_cntfrq; /* Counter Frequency register */ 460 uint64_t c14_cntkctl; /* Timer Control register */ 461 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 462 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 463 ARMGenericTimer c14_timer[NUM_GTIMERS]; 464 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 465 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 466 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 467 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 468 uint32_t c15_threadid; /* TI debugger thread-ID. */ 469 uint32_t c15_config_base_address; /* SCU base address. */ 470 uint32_t c15_diagnostic; /* diagnostic register */ 471 uint32_t c15_power_diagnostic; 472 uint32_t c15_power_control; /* power control */ 473 uint64_t dbgbvr[16]; /* breakpoint value registers */ 474 uint64_t dbgbcr[16]; /* breakpoint control registers */ 475 uint64_t dbgwvr[16]; /* watchpoint value registers */ 476 uint64_t dbgwcr[16]; /* watchpoint control registers */ 477 uint64_t mdscr_el1; 478 uint64_t oslsr_el1; /* OS Lock Status */ 479 uint64_t mdcr_el2; 480 uint64_t mdcr_el3; 481 /* Stores the architectural value of the counter *the last time it was 482 * updated* by pmccntr_op_start. Accesses should always be surrounded 483 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 484 * architecturally-correct value is being read/set. 485 */ 486 uint64_t c15_ccnt; 487 /* Stores the delta between the architectural value and the underlying 488 * cycle count during normal operation. It is used to update c15_ccnt 489 * to be the correct architectural value before accesses. During 490 * accesses, c15_ccnt_delta contains the underlying count being used 491 * for the access, after which it reverts to the delta value in 492 * pmccntr_op_finish. 493 */ 494 uint64_t c15_ccnt_delta; 495 uint64_t c14_pmevcntr[31]; 496 uint64_t c14_pmevcntr_delta[31]; 497 uint64_t c14_pmevtyper[31]; 498 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 499 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 500 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 501 } cp15; 502 503 struct { 504 /* M profile has up to 4 stack pointers: 505 * a Main Stack Pointer and a Process Stack Pointer for each 506 * of the Secure and Non-Secure states. (If the CPU doesn't support 507 * the security extension then it has only two SPs.) 508 * In QEMU we always store the currently active SP in regs[13], 509 * and the non-active SP for the current security state in 510 * v7m.other_sp. The stack pointers for the inactive security state 511 * are stored in other_ss_msp and other_ss_psp. 512 * switch_v7m_security_state() is responsible for rearranging them 513 * when we change security state. 514 */ 515 uint32_t other_sp; 516 uint32_t other_ss_msp; 517 uint32_t other_ss_psp; 518 uint32_t vecbase[M_REG_NUM_BANKS]; 519 uint32_t basepri[M_REG_NUM_BANKS]; 520 uint32_t control[M_REG_NUM_BANKS]; 521 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 522 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 523 uint32_t hfsr; /* HardFault Status */ 524 uint32_t dfsr; /* Debug Fault Status Register */ 525 uint32_t sfsr; /* Secure Fault Status Register */ 526 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 527 uint32_t bfar; /* BusFault Address */ 528 uint32_t sfar; /* Secure Fault Address Register */ 529 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 530 int exception; 531 uint32_t primask[M_REG_NUM_BANKS]; 532 uint32_t faultmask[M_REG_NUM_BANKS]; 533 uint32_t aircr; /* only holds r/w state if security extn implemented */ 534 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 535 uint32_t csselr[M_REG_NUM_BANKS]; 536 uint32_t scr[M_REG_NUM_BANKS]; 537 uint32_t msplim[M_REG_NUM_BANKS]; 538 uint32_t psplim[M_REG_NUM_BANKS]; 539 uint32_t fpcar[M_REG_NUM_BANKS]; 540 uint32_t fpccr[M_REG_NUM_BANKS]; 541 uint32_t fpdscr[M_REG_NUM_BANKS]; 542 uint32_t cpacr[M_REG_NUM_BANKS]; 543 uint32_t nsacr; 544 } v7m; 545 546 /* Information associated with an exception about to be taken: 547 * code which raises an exception must set cs->exception_index and 548 * the relevant parts of this structure; the cpu_do_interrupt function 549 * will then set the guest-visible registers as part of the exception 550 * entry process. 551 */ 552 struct { 553 uint32_t syndrome; /* AArch64 format syndrome register */ 554 uint32_t fsr; /* AArch32 format fault status register info */ 555 uint64_t vaddress; /* virtual addr associated with exception, if any */ 556 uint32_t target_el; /* EL the exception should be targeted for */ 557 /* If we implement EL2 we will also need to store information 558 * about the intermediate physical address for stage 2 faults. 559 */ 560 } exception; 561 562 /* Information associated with an SError */ 563 struct { 564 uint8_t pending; 565 uint8_t has_esr; 566 uint64_t esr; 567 } serror; 568 569 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 570 uint32_t irq_line_state; 571 572 /* Thumb-2 EE state. */ 573 uint32_t teecr; 574 uint32_t teehbr; 575 576 /* VFP coprocessor state. */ 577 struct { 578 ARMVectorReg zregs[32]; 579 580 #ifdef TARGET_AARCH64 581 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 582 #define FFR_PRED_NUM 16 583 ARMPredicateReg pregs[17]; 584 /* Scratch space for aa64 sve predicate temporary. */ 585 ARMPredicateReg preg_tmp; 586 #endif 587 588 /* We store these fpcsr fields separately for convenience. */ 589 uint32_t qc[4] QEMU_ALIGNED(16); 590 int vec_len; 591 int vec_stride; 592 593 uint32_t xregs[16]; 594 595 /* Scratch space for aa32 neon expansion. */ 596 uint32_t scratch[8]; 597 598 /* There are a number of distinct float control structures: 599 * 600 * fp_status: is the "normal" fp status. 601 * fp_status_fp16: used for half-precision calculations 602 * standard_fp_status : the ARM "Standard FPSCR Value" 603 * 604 * Half-precision operations are governed by a separate 605 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 606 * status structure to control this. 607 * 608 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 609 * round-to-nearest and is used by any operations (generally 610 * Neon) which the architecture defines as controlled by the 611 * standard FPSCR value rather than the FPSCR. 612 * 613 * To avoid having to transfer exception bits around, we simply 614 * say that the FPSCR cumulative exception flags are the logical 615 * OR of the flags in the three fp statuses. This relies on the 616 * only thing which needs to read the exception flags being 617 * an explicit FPSCR read. 618 */ 619 float_status fp_status; 620 float_status fp_status_f16; 621 float_status standard_fp_status; 622 623 /* ZCR_EL[1-3] */ 624 uint64_t zcr_el[4]; 625 } vfp; 626 uint64_t exclusive_addr; 627 uint64_t exclusive_val; 628 uint64_t exclusive_high; 629 630 /* iwMMXt coprocessor state. */ 631 struct { 632 uint64_t regs[16]; 633 uint64_t val; 634 635 uint32_t cregs[16]; 636 } iwmmxt; 637 638 #ifdef TARGET_AARCH64 639 ARMPACKey apia_key; 640 ARMPACKey apib_key; 641 ARMPACKey apda_key; 642 ARMPACKey apdb_key; 643 ARMPACKey apga_key; 644 #endif 645 646 #if defined(CONFIG_USER_ONLY) 647 /* For usermode syscall translation. */ 648 int eabi; 649 #endif 650 651 struct CPUBreakpoint *cpu_breakpoint[16]; 652 struct CPUWatchpoint *cpu_watchpoint[16]; 653 654 /* Fields up to this point are cleared by a CPU reset */ 655 struct {} end_reset_fields; 656 657 CPU_COMMON 658 659 /* Fields after CPU_COMMON are preserved across CPU reset. */ 660 661 /* Internal CPU feature flags. */ 662 uint64_t features; 663 664 /* PMSAv7 MPU */ 665 struct { 666 uint32_t *drbar; 667 uint32_t *drsr; 668 uint32_t *dracr; 669 uint32_t rnr[M_REG_NUM_BANKS]; 670 } pmsav7; 671 672 /* PMSAv8 MPU */ 673 struct { 674 /* The PMSAv8 implementation also shares some PMSAv7 config 675 * and state: 676 * pmsav7.rnr (region number register) 677 * pmsav7_dregion (number of configured regions) 678 */ 679 uint32_t *rbar[M_REG_NUM_BANKS]; 680 uint32_t *rlar[M_REG_NUM_BANKS]; 681 uint32_t mair0[M_REG_NUM_BANKS]; 682 uint32_t mair1[M_REG_NUM_BANKS]; 683 } pmsav8; 684 685 /* v8M SAU */ 686 struct { 687 uint32_t *rbar; 688 uint32_t *rlar; 689 uint32_t rnr; 690 uint32_t ctrl; 691 } sau; 692 693 void *nvic; 694 const struct arm_boot_info *boot_info; 695 /* Store GICv3CPUState to access from this struct */ 696 void *gicv3state; 697 } CPUARMState; 698 699 /** 700 * ARMELChangeHookFn: 701 * type of a function which can be registered via arm_register_el_change_hook() 702 * to get callbacks when the CPU changes its exception level or mode. 703 */ 704 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 705 typedef struct ARMELChangeHook ARMELChangeHook; 706 struct ARMELChangeHook { 707 ARMELChangeHookFn *hook; 708 void *opaque; 709 QLIST_ENTRY(ARMELChangeHook) node; 710 }; 711 712 /* These values map onto the return values for 713 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 714 typedef enum ARMPSCIState { 715 PSCI_ON = 0, 716 PSCI_OFF = 1, 717 PSCI_ON_PENDING = 2 718 } ARMPSCIState; 719 720 typedef struct ARMISARegisters ARMISARegisters; 721 722 /** 723 * ARMCPU: 724 * @env: #CPUARMState 725 * 726 * An ARM CPU core. 727 */ 728 struct ARMCPU { 729 /*< private >*/ 730 CPUState parent_obj; 731 /*< public >*/ 732 733 CPUARMState env; 734 735 /* Coprocessor information */ 736 GHashTable *cp_regs; 737 /* For marshalling (mostly coprocessor) register state between the 738 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 739 * we use these arrays. 740 */ 741 /* List of register indexes managed via these arrays; (full KVM style 742 * 64 bit indexes, not CPRegInfo 32 bit indexes) 743 */ 744 uint64_t *cpreg_indexes; 745 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 746 uint64_t *cpreg_values; 747 /* Length of the indexes, values, reset_values arrays */ 748 int32_t cpreg_array_len; 749 /* These are used only for migration: incoming data arrives in 750 * these fields and is sanity checked in post_load before copying 751 * to the working data structures above. 752 */ 753 uint64_t *cpreg_vmstate_indexes; 754 uint64_t *cpreg_vmstate_values; 755 int32_t cpreg_vmstate_array_len; 756 757 DynamicGDBXMLInfo dyn_xml; 758 759 /* Timers used by the generic (architected) timer */ 760 QEMUTimer *gt_timer[NUM_GTIMERS]; 761 /* 762 * Timer used by the PMU. Its state is restored after migration by 763 * pmu_op_finish() - it does not need other handling during migration 764 */ 765 QEMUTimer *pmu_timer; 766 /* GPIO outputs for generic timer */ 767 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 768 /* GPIO output for GICv3 maintenance interrupt signal */ 769 qemu_irq gicv3_maintenance_interrupt; 770 /* GPIO output for the PMU interrupt */ 771 qemu_irq pmu_interrupt; 772 773 /* MemoryRegion to use for secure physical accesses */ 774 MemoryRegion *secure_memory; 775 776 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 777 Object *idau; 778 779 /* 'compatible' string for this CPU for Linux device trees */ 780 const char *dtb_compatible; 781 782 /* PSCI version for this CPU 783 * Bits[31:16] = Major Version 784 * Bits[15:0] = Minor Version 785 */ 786 uint32_t psci_version; 787 788 /* Should CPU start in PSCI powered-off state? */ 789 bool start_powered_off; 790 791 /* Current power state, access guarded by BQL */ 792 ARMPSCIState power_state; 793 794 /* CPU has virtualization extension */ 795 bool has_el2; 796 /* CPU has security extension */ 797 bool has_el3; 798 /* CPU has PMU (Performance Monitor Unit) */ 799 bool has_pmu; 800 801 /* CPU has memory protection unit */ 802 bool has_mpu; 803 /* PMSAv7 MPU number of supported regions */ 804 uint32_t pmsav7_dregion; 805 /* v8M SAU number of supported regions */ 806 uint32_t sau_sregion; 807 808 /* PSCI conduit used to invoke PSCI methods 809 * 0 - disabled, 1 - smc, 2 - hvc 810 */ 811 uint32_t psci_conduit; 812 813 /* For v8M, initial value of the Secure VTOR */ 814 uint32_t init_svtor; 815 816 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 817 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 818 */ 819 uint32_t kvm_target; 820 821 /* KVM init features for this CPU */ 822 uint32_t kvm_init_features[7]; 823 824 /* Uniprocessor system with MP extensions */ 825 bool mp_is_up; 826 827 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 828 * and the probe failed (so we need to report the error in realize) 829 */ 830 bool host_cpu_probe_failed; 831 832 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 833 * register. 834 */ 835 int32_t core_count; 836 837 /* The instance init functions for implementation-specific subclasses 838 * set these fields to specify the implementation-dependent values of 839 * various constant registers and reset values of non-constant 840 * registers. 841 * Some of these might become QOM properties eventually. 842 * Field names match the official register names as defined in the 843 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 844 * is used for reset values of non-constant registers; no reset_ 845 * prefix means a constant register. 846 * Some of these registers are split out into a substructure that 847 * is shared with the translators to control the ISA. 848 */ 849 struct ARMISARegisters { 850 uint32_t id_isar0; 851 uint32_t id_isar1; 852 uint32_t id_isar2; 853 uint32_t id_isar3; 854 uint32_t id_isar4; 855 uint32_t id_isar5; 856 uint32_t id_isar6; 857 uint32_t mvfr0; 858 uint32_t mvfr1; 859 uint32_t mvfr2; 860 uint64_t id_aa64isar0; 861 uint64_t id_aa64isar1; 862 uint64_t id_aa64pfr0; 863 uint64_t id_aa64pfr1; 864 uint64_t id_aa64mmfr0; 865 uint64_t id_aa64mmfr1; 866 } isar; 867 uint32_t midr; 868 uint32_t revidr; 869 uint32_t reset_fpsid; 870 uint32_t ctr; 871 uint32_t reset_sctlr; 872 uint32_t id_pfr0; 873 uint32_t id_pfr1; 874 uint32_t id_dfr0; 875 uint64_t pmceid0; 876 uint64_t pmceid1; 877 uint32_t id_afr0; 878 uint32_t id_mmfr0; 879 uint32_t id_mmfr1; 880 uint32_t id_mmfr2; 881 uint32_t id_mmfr3; 882 uint32_t id_mmfr4; 883 uint64_t id_aa64dfr0; 884 uint64_t id_aa64dfr1; 885 uint64_t id_aa64afr0; 886 uint64_t id_aa64afr1; 887 uint32_t dbgdidr; 888 uint32_t clidr; 889 uint64_t mp_affinity; /* MP ID without feature bits */ 890 /* The elements of this array are the CCSIDR values for each cache, 891 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 892 */ 893 uint32_t ccsidr[16]; 894 uint64_t reset_cbar; 895 uint32_t reset_auxcr; 896 bool reset_hivecs; 897 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 898 uint32_t dcz_blocksize; 899 uint64_t rvbar; 900 901 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 902 int gic_num_lrs; /* number of list registers */ 903 int gic_vpribits; /* number of virtual priority bits */ 904 int gic_vprebits; /* number of virtual preemption bits */ 905 906 /* Whether the cfgend input is high (i.e. this CPU should reset into 907 * big-endian mode). This setting isn't used directly: instead it modifies 908 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 909 * architecture version. 910 */ 911 bool cfgend; 912 913 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 914 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 915 916 int32_t node_id; /* NUMA node this CPU belongs to */ 917 918 /* Used to synchronize KVM and QEMU in-kernel device levels */ 919 uint8_t device_irq_level; 920 921 /* Used to set the maximum vector length the cpu will support. */ 922 uint32_t sve_max_vq; 923 }; 924 925 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 926 { 927 return container_of(env, ARMCPU, env); 928 } 929 930 void arm_cpu_post_init(Object *obj); 931 932 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 933 934 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 935 936 #define ENV_OFFSET offsetof(ARMCPU, env) 937 938 #ifndef CONFIG_USER_ONLY 939 extern const struct VMStateDescription vmstate_arm_cpu; 940 #endif 941 942 void arm_cpu_do_interrupt(CPUState *cpu); 943 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 944 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 945 946 void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags); 947 948 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 949 MemTxAttrs *attrs); 950 951 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 952 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 953 954 /* Dynamically generates for gdb stub an XML description of the sysregs from 955 * the cp_regs hashtable. Returns the registered sysregs number. 956 */ 957 int arm_gen_dynamic_xml(CPUState *cpu); 958 959 /* Returns the dynamically generated XML for the gdb stub. 960 * Returns a pointer to the XML contents for the specified XML file or NULL 961 * if the XML name doesn't match the predefined one. 962 */ 963 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 964 965 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 966 int cpuid, void *opaque); 967 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 968 int cpuid, void *opaque); 969 970 #ifdef TARGET_AARCH64 971 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 972 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 973 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 974 void aarch64_sve_change_el(CPUARMState *env, int old_el, 975 int new_el, bool el0_a64); 976 #else 977 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 978 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 979 int n, bool a) 980 { } 981 #endif 982 983 target_ulong do_arm_semihosting(CPUARMState *env); 984 void aarch64_sync_32_to_64(CPUARMState *env); 985 void aarch64_sync_64_to_32(CPUARMState *env); 986 987 int fp_exception_el(CPUARMState *env, int cur_el); 988 int sve_exception_el(CPUARMState *env, int cur_el); 989 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 990 991 static inline bool is_a64(CPUARMState *env) 992 { 993 return env->aarch64; 994 } 995 996 /* you can call this signal handler from your SIGBUS and SIGSEGV 997 signal handlers to inform the virtual CPU of exceptions. non zero 998 is returned if the signal was handled by the virtual CPU. */ 999 int cpu_arm_signal_handler(int host_signum, void *pinfo, 1000 void *puc); 1001 1002 /** 1003 * pmu_op_start/finish 1004 * @env: CPUARMState 1005 * 1006 * Convert all PMU counters between their delta form (the typical mode when 1007 * they are enabled) and the guest-visible values. These two calls must 1008 * surround any action which might affect the counters. 1009 */ 1010 void pmu_op_start(CPUARMState *env); 1011 void pmu_op_finish(CPUARMState *env); 1012 1013 /* 1014 * Called when a PMU counter is due to overflow 1015 */ 1016 void arm_pmu_timer_cb(void *opaque); 1017 1018 /** 1019 * Functions to register as EL change hooks for PMU mode filtering 1020 */ 1021 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1022 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1023 1024 /* 1025 * pmu_init 1026 * @cpu: ARMCPU 1027 * 1028 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1029 * for the current configuration 1030 */ 1031 void pmu_init(ARMCPU *cpu); 1032 1033 /* SCTLR bit meanings. Several bits have been reused in newer 1034 * versions of the architecture; in that case we define constants 1035 * for both old and new bit meanings. Code which tests against those 1036 * bits should probably check or otherwise arrange that the CPU 1037 * is the architectural version it expects. 1038 */ 1039 #define SCTLR_M (1U << 0) 1040 #define SCTLR_A (1U << 1) 1041 #define SCTLR_C (1U << 2) 1042 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1043 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1044 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1045 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1046 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1047 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1048 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1049 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1050 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1051 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1052 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1053 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1054 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1055 #define SCTLR_SED (1U << 8) /* v8 onward */ 1056 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1057 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1058 #define SCTLR_F (1U << 10) /* up to v6 */ 1059 #define SCTLR_SW (1U << 10) /* v7 */ 1060 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1061 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1062 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1063 #define SCTLR_I (1U << 12) 1064 #define SCTLR_V (1U << 13) /* AArch32 only */ 1065 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1066 #define SCTLR_RR (1U << 14) /* up to v7 */ 1067 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1068 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1069 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1070 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1071 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1072 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1073 #define SCTLR_BR (1U << 17) /* PMSA only */ 1074 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1075 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1076 #define SCTLR_WXN (1U << 19) 1077 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1078 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1079 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1080 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1081 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1082 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1083 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1084 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1085 #define SCTLR_VE (1U << 24) /* up to v7 */ 1086 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1087 #define SCTLR_EE (1U << 25) 1088 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1089 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1090 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1091 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1092 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1093 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1094 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1095 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1096 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1097 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1098 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1099 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1100 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1101 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1102 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1103 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1104 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1105 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1106 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1107 1108 #define CPTR_TCPAC (1U << 31) 1109 #define CPTR_TTA (1U << 20) 1110 #define CPTR_TFP (1U << 10) 1111 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1112 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1113 1114 #define MDCR_EPMAD (1U << 21) 1115 #define MDCR_EDAD (1U << 20) 1116 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1117 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1118 #define MDCR_SDD (1U << 16) 1119 #define MDCR_SPD (3U << 14) 1120 #define MDCR_TDRA (1U << 11) 1121 #define MDCR_TDOSA (1U << 10) 1122 #define MDCR_TDA (1U << 9) 1123 #define MDCR_TDE (1U << 8) 1124 #define MDCR_HPME (1U << 7) 1125 #define MDCR_TPM (1U << 6) 1126 #define MDCR_TPMCR (1U << 5) 1127 #define MDCR_HPMN (0x1fU) 1128 1129 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1130 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1131 1132 #define CPSR_M (0x1fU) 1133 #define CPSR_T (1U << 5) 1134 #define CPSR_F (1U << 6) 1135 #define CPSR_I (1U << 7) 1136 #define CPSR_A (1U << 8) 1137 #define CPSR_E (1U << 9) 1138 #define CPSR_IT_2_7 (0xfc00U) 1139 #define CPSR_GE (0xfU << 16) 1140 #define CPSR_IL (1U << 20) 1141 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 1142 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 1143 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 1144 * where it is live state but not accessible to the AArch32 code. 1145 */ 1146 #define CPSR_RESERVED (0x7U << 21) 1147 #define CPSR_J (1U << 24) 1148 #define CPSR_IT_0_1 (3U << 25) 1149 #define CPSR_Q (1U << 27) 1150 #define CPSR_V (1U << 28) 1151 #define CPSR_C (1U << 29) 1152 #define CPSR_Z (1U << 30) 1153 #define CPSR_N (1U << 31) 1154 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1155 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1156 1157 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1158 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1159 | CPSR_NZCV) 1160 /* Bits writable in user mode. */ 1161 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1162 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1163 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1164 /* Mask of bits which may be set by exception return copying them from SPSR */ 1165 #define CPSR_ERET_MASK (~CPSR_RESERVED) 1166 1167 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1168 #define XPSR_EXCP 0x1ffU 1169 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1170 #define XPSR_IT_2_7 CPSR_IT_2_7 1171 #define XPSR_GE CPSR_GE 1172 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1173 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1174 #define XPSR_IT_0_1 CPSR_IT_0_1 1175 #define XPSR_Q CPSR_Q 1176 #define XPSR_V CPSR_V 1177 #define XPSR_C CPSR_C 1178 #define XPSR_Z CPSR_Z 1179 #define XPSR_N CPSR_N 1180 #define XPSR_NZCV CPSR_NZCV 1181 #define XPSR_IT CPSR_IT 1182 1183 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1184 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1185 #define TTBCR_PD0 (1U << 4) 1186 #define TTBCR_PD1 (1U << 5) 1187 #define TTBCR_EPD0 (1U << 7) 1188 #define TTBCR_IRGN0 (3U << 8) 1189 #define TTBCR_ORGN0 (3U << 10) 1190 #define TTBCR_SH0 (3U << 12) 1191 #define TTBCR_T1SZ (3U << 16) 1192 #define TTBCR_A1 (1U << 22) 1193 #define TTBCR_EPD1 (1U << 23) 1194 #define TTBCR_IRGN1 (3U << 24) 1195 #define TTBCR_ORGN1 (3U << 26) 1196 #define TTBCR_SH1 (1U << 28) 1197 #define TTBCR_EAE (1U << 31) 1198 1199 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1200 * Only these are valid when in AArch64 mode; in 1201 * AArch32 mode SPSRs are basically CPSR-format. 1202 */ 1203 #define PSTATE_SP (1U) 1204 #define PSTATE_M (0xFU) 1205 #define PSTATE_nRW (1U << 4) 1206 #define PSTATE_F (1U << 6) 1207 #define PSTATE_I (1U << 7) 1208 #define PSTATE_A (1U << 8) 1209 #define PSTATE_D (1U << 9) 1210 #define PSTATE_BTYPE (3U << 10) 1211 #define PSTATE_IL (1U << 20) 1212 #define PSTATE_SS (1U << 21) 1213 #define PSTATE_V (1U << 28) 1214 #define PSTATE_C (1U << 29) 1215 #define PSTATE_Z (1U << 30) 1216 #define PSTATE_N (1U << 31) 1217 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1218 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1219 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1220 /* Mode values for AArch64 */ 1221 #define PSTATE_MODE_EL3h 13 1222 #define PSTATE_MODE_EL3t 12 1223 #define PSTATE_MODE_EL2h 9 1224 #define PSTATE_MODE_EL2t 8 1225 #define PSTATE_MODE_EL1h 5 1226 #define PSTATE_MODE_EL1t 4 1227 #define PSTATE_MODE_EL0t 0 1228 1229 /* Write a new value to v7m.exception, thus transitioning into or out 1230 * of Handler mode; this may result in a change of active stack pointer. 1231 */ 1232 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1233 1234 /* Map EL and handler into a PSTATE_MODE. */ 1235 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1236 { 1237 return (el << 2) | handler; 1238 } 1239 1240 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1241 * interprocessing, so we don't attempt to sync with the cpsr state used by 1242 * the 32 bit decoder. 1243 */ 1244 static inline uint32_t pstate_read(CPUARMState *env) 1245 { 1246 int ZF; 1247 1248 ZF = (env->ZF == 0); 1249 return (env->NF & 0x80000000) | (ZF << 30) 1250 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1251 | env->pstate | env->daif | (env->btype << 10); 1252 } 1253 1254 static inline void pstate_write(CPUARMState *env, uint32_t val) 1255 { 1256 env->ZF = (~val) & PSTATE_Z; 1257 env->NF = val; 1258 env->CF = (val >> 29) & 1; 1259 env->VF = (val << 3) & 0x80000000; 1260 env->daif = val & PSTATE_DAIF; 1261 env->btype = (val >> 10) & 3; 1262 env->pstate = val & ~CACHED_PSTATE_BITS; 1263 } 1264 1265 /* Return the current CPSR value. */ 1266 uint32_t cpsr_read(CPUARMState *env); 1267 1268 typedef enum CPSRWriteType { 1269 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1270 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1271 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1272 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1273 } CPSRWriteType; 1274 1275 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1276 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1277 CPSRWriteType write_type); 1278 1279 /* Return the current xPSR value. */ 1280 static inline uint32_t xpsr_read(CPUARMState *env) 1281 { 1282 int ZF; 1283 ZF = (env->ZF == 0); 1284 return (env->NF & 0x80000000) | (ZF << 30) 1285 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1286 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1287 | ((env->condexec_bits & 0xfc) << 8) 1288 | env->v7m.exception; 1289 } 1290 1291 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1292 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1293 { 1294 if (mask & XPSR_NZCV) { 1295 env->ZF = (~val) & XPSR_Z; 1296 env->NF = val; 1297 env->CF = (val >> 29) & 1; 1298 env->VF = (val << 3) & 0x80000000; 1299 } 1300 if (mask & XPSR_Q) { 1301 env->QF = ((val & XPSR_Q) != 0); 1302 } 1303 if (mask & XPSR_T) { 1304 env->thumb = ((val & XPSR_T) != 0); 1305 } 1306 if (mask & XPSR_IT_0_1) { 1307 env->condexec_bits &= ~3; 1308 env->condexec_bits |= (val >> 25) & 3; 1309 } 1310 if (mask & XPSR_IT_2_7) { 1311 env->condexec_bits &= 3; 1312 env->condexec_bits |= (val >> 8) & 0xfc; 1313 } 1314 if (mask & XPSR_EXCP) { 1315 /* Note that this only happens on exception exit */ 1316 write_v7m_exception(env, val & XPSR_EXCP); 1317 } 1318 } 1319 1320 #define HCR_VM (1ULL << 0) 1321 #define HCR_SWIO (1ULL << 1) 1322 #define HCR_PTW (1ULL << 2) 1323 #define HCR_FMO (1ULL << 3) 1324 #define HCR_IMO (1ULL << 4) 1325 #define HCR_AMO (1ULL << 5) 1326 #define HCR_VF (1ULL << 6) 1327 #define HCR_VI (1ULL << 7) 1328 #define HCR_VSE (1ULL << 8) 1329 #define HCR_FB (1ULL << 9) 1330 #define HCR_BSU_MASK (3ULL << 10) 1331 #define HCR_DC (1ULL << 12) 1332 #define HCR_TWI (1ULL << 13) 1333 #define HCR_TWE (1ULL << 14) 1334 #define HCR_TID0 (1ULL << 15) 1335 #define HCR_TID1 (1ULL << 16) 1336 #define HCR_TID2 (1ULL << 17) 1337 #define HCR_TID3 (1ULL << 18) 1338 #define HCR_TSC (1ULL << 19) 1339 #define HCR_TIDCP (1ULL << 20) 1340 #define HCR_TACR (1ULL << 21) 1341 #define HCR_TSW (1ULL << 22) 1342 #define HCR_TPCP (1ULL << 23) 1343 #define HCR_TPU (1ULL << 24) 1344 #define HCR_TTLB (1ULL << 25) 1345 #define HCR_TVM (1ULL << 26) 1346 #define HCR_TGE (1ULL << 27) 1347 #define HCR_TDZ (1ULL << 28) 1348 #define HCR_HCD (1ULL << 29) 1349 #define HCR_TRVM (1ULL << 30) 1350 #define HCR_RW (1ULL << 31) 1351 #define HCR_CD (1ULL << 32) 1352 #define HCR_ID (1ULL << 33) 1353 #define HCR_E2H (1ULL << 34) 1354 #define HCR_TLOR (1ULL << 35) 1355 #define HCR_TERR (1ULL << 36) 1356 #define HCR_TEA (1ULL << 37) 1357 #define HCR_MIOCNCE (1ULL << 38) 1358 #define HCR_APK (1ULL << 40) 1359 #define HCR_API (1ULL << 41) 1360 #define HCR_NV (1ULL << 42) 1361 #define HCR_NV1 (1ULL << 43) 1362 #define HCR_AT (1ULL << 44) 1363 #define HCR_NV2 (1ULL << 45) 1364 #define HCR_FWB (1ULL << 46) 1365 #define HCR_FIEN (1ULL << 47) 1366 #define HCR_TID4 (1ULL << 49) 1367 #define HCR_TICAB (1ULL << 50) 1368 #define HCR_TOCU (1ULL << 52) 1369 #define HCR_TTLBIS (1ULL << 54) 1370 #define HCR_TTLBOS (1ULL << 55) 1371 #define HCR_ATA (1ULL << 56) 1372 #define HCR_DCT (1ULL << 57) 1373 1374 /* 1375 * When we actually implement ARMv8.1-VHE we should add HCR_E2H to 1376 * HCR_MASK and then clear it again if the feature bit is not set in 1377 * hcr_write(). 1378 */ 1379 #define HCR_MASK ((1ULL << 34) - 1) 1380 1381 #define SCR_NS (1U << 0) 1382 #define SCR_IRQ (1U << 1) 1383 #define SCR_FIQ (1U << 2) 1384 #define SCR_EA (1U << 3) 1385 #define SCR_FW (1U << 4) 1386 #define SCR_AW (1U << 5) 1387 #define SCR_NET (1U << 6) 1388 #define SCR_SMD (1U << 7) 1389 #define SCR_HCE (1U << 8) 1390 #define SCR_SIF (1U << 9) 1391 #define SCR_RW (1U << 10) 1392 #define SCR_ST (1U << 11) 1393 #define SCR_TWI (1U << 12) 1394 #define SCR_TWE (1U << 13) 1395 #define SCR_TLOR (1U << 14) 1396 #define SCR_TERR (1U << 15) 1397 #define SCR_APK (1U << 16) 1398 #define SCR_API (1U << 17) 1399 #define SCR_EEL2 (1U << 18) 1400 #define SCR_EASE (1U << 19) 1401 #define SCR_NMEA (1U << 20) 1402 #define SCR_FIEN (1U << 21) 1403 #define SCR_ENSCXT (1U << 25) 1404 #define SCR_ATA (1U << 26) 1405 1406 /* Return the current FPSCR value. */ 1407 uint32_t vfp_get_fpscr(CPUARMState *env); 1408 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1409 1410 /* FPCR, Floating Point Control Register 1411 * FPSR, Floating Poiht Status Register 1412 * 1413 * For A64 the FPSCR is split into two logically distinct registers, 1414 * FPCR and FPSR. However since they still use non-overlapping bits 1415 * we store the underlying state in fpscr and just mask on read/write. 1416 */ 1417 #define FPSR_MASK 0xf800009f 1418 #define FPCR_MASK 0x07ff9f00 1419 1420 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1421 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1422 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1423 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1424 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1425 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1426 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1427 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1428 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1429 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1430 1431 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1432 { 1433 return vfp_get_fpscr(env) & FPSR_MASK; 1434 } 1435 1436 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1437 { 1438 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1439 vfp_set_fpscr(env, new_fpscr); 1440 } 1441 1442 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1443 { 1444 return vfp_get_fpscr(env) & FPCR_MASK; 1445 } 1446 1447 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1448 { 1449 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1450 vfp_set_fpscr(env, new_fpscr); 1451 } 1452 1453 enum arm_cpu_mode { 1454 ARM_CPU_MODE_USR = 0x10, 1455 ARM_CPU_MODE_FIQ = 0x11, 1456 ARM_CPU_MODE_IRQ = 0x12, 1457 ARM_CPU_MODE_SVC = 0x13, 1458 ARM_CPU_MODE_MON = 0x16, 1459 ARM_CPU_MODE_ABT = 0x17, 1460 ARM_CPU_MODE_HYP = 0x1a, 1461 ARM_CPU_MODE_UND = 0x1b, 1462 ARM_CPU_MODE_SYS = 0x1f 1463 }; 1464 1465 /* VFP system registers. */ 1466 #define ARM_VFP_FPSID 0 1467 #define ARM_VFP_FPSCR 1 1468 #define ARM_VFP_MVFR2 5 1469 #define ARM_VFP_MVFR1 6 1470 #define ARM_VFP_MVFR0 7 1471 #define ARM_VFP_FPEXC 8 1472 #define ARM_VFP_FPINST 9 1473 #define ARM_VFP_FPINST2 10 1474 1475 /* iwMMXt coprocessor control registers. */ 1476 #define ARM_IWMMXT_wCID 0 1477 #define ARM_IWMMXT_wCon 1 1478 #define ARM_IWMMXT_wCSSF 2 1479 #define ARM_IWMMXT_wCASF 3 1480 #define ARM_IWMMXT_wCGR0 8 1481 #define ARM_IWMMXT_wCGR1 9 1482 #define ARM_IWMMXT_wCGR2 10 1483 #define ARM_IWMMXT_wCGR3 11 1484 1485 /* V7M CCR bits */ 1486 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1487 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1488 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1489 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1490 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1491 FIELD(V7M_CCR, STKALIGN, 9, 1) 1492 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1493 FIELD(V7M_CCR, DC, 16, 1) 1494 FIELD(V7M_CCR, IC, 17, 1) 1495 FIELD(V7M_CCR, BP, 18, 1) 1496 1497 /* V7M SCR bits */ 1498 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1499 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1500 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1501 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1502 1503 /* V7M AIRCR bits */ 1504 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1505 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1506 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1507 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1508 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1509 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1510 FIELD(V7M_AIRCR, PRIS, 14, 1) 1511 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1512 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1513 1514 /* V7M CFSR bits for MMFSR */ 1515 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1516 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1517 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1518 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1519 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1520 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1521 1522 /* V7M CFSR bits for BFSR */ 1523 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1524 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1525 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1526 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1527 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1528 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1529 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1530 1531 /* V7M CFSR bits for UFSR */ 1532 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1533 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1534 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1535 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1536 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1537 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1538 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1539 1540 /* V7M CFSR bit masks covering all of the subregister bits */ 1541 FIELD(V7M_CFSR, MMFSR, 0, 8) 1542 FIELD(V7M_CFSR, BFSR, 8, 8) 1543 FIELD(V7M_CFSR, UFSR, 16, 16) 1544 1545 /* V7M HFSR bits */ 1546 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1547 FIELD(V7M_HFSR, FORCED, 30, 1) 1548 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1549 1550 /* V7M DFSR bits */ 1551 FIELD(V7M_DFSR, HALTED, 0, 1) 1552 FIELD(V7M_DFSR, BKPT, 1, 1) 1553 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1554 FIELD(V7M_DFSR, VCATCH, 3, 1) 1555 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1556 1557 /* V7M SFSR bits */ 1558 FIELD(V7M_SFSR, INVEP, 0, 1) 1559 FIELD(V7M_SFSR, INVIS, 1, 1) 1560 FIELD(V7M_SFSR, INVER, 2, 1) 1561 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1562 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1563 FIELD(V7M_SFSR, LSPERR, 5, 1) 1564 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1565 FIELD(V7M_SFSR, LSERR, 7, 1) 1566 1567 /* v7M MPU_CTRL bits */ 1568 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1569 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1570 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1571 1572 /* v7M CLIDR bits */ 1573 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1574 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1575 FIELD(V7M_CLIDR, LOC, 24, 3) 1576 FIELD(V7M_CLIDR, LOUU, 27, 3) 1577 FIELD(V7M_CLIDR, ICB, 30, 2) 1578 1579 FIELD(V7M_CSSELR, IND, 0, 1) 1580 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1581 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1582 * define a mask for this and check that it doesn't permit running off 1583 * the end of the array. 1584 */ 1585 FIELD(V7M_CSSELR, INDEX, 0, 4) 1586 1587 /* v7M FPCCR bits */ 1588 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1589 FIELD(V7M_FPCCR, USER, 1, 1) 1590 FIELD(V7M_FPCCR, S, 2, 1) 1591 FIELD(V7M_FPCCR, THREAD, 3, 1) 1592 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1593 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1594 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1595 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1596 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1597 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1598 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1599 FIELD(V7M_FPCCR, RES0, 11, 15) 1600 FIELD(V7M_FPCCR, TS, 26, 1) 1601 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1602 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1603 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1604 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1605 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1606 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1607 #define R_V7M_FPCCR_BANKED_MASK \ 1608 (R_V7M_FPCCR_LSPACT_MASK | \ 1609 R_V7M_FPCCR_USER_MASK | \ 1610 R_V7M_FPCCR_THREAD_MASK | \ 1611 R_V7M_FPCCR_MMRDY_MASK | \ 1612 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1613 R_V7M_FPCCR_UFRDY_MASK | \ 1614 R_V7M_FPCCR_ASPEN_MASK) 1615 1616 /* 1617 * System register ID fields. 1618 */ 1619 FIELD(ID_ISAR0, SWAP, 0, 4) 1620 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1621 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1622 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1623 FIELD(ID_ISAR0, COPROC, 16, 4) 1624 FIELD(ID_ISAR0, DEBUG, 20, 4) 1625 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1626 1627 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1628 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1629 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1630 FIELD(ID_ISAR1, EXTEND, 12, 4) 1631 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1632 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1633 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1634 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1635 1636 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1637 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1638 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1639 FIELD(ID_ISAR2, MULT, 12, 4) 1640 FIELD(ID_ISAR2, MULTS, 16, 4) 1641 FIELD(ID_ISAR2, MULTU, 20, 4) 1642 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1643 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1644 1645 FIELD(ID_ISAR3, SATURATE, 0, 4) 1646 FIELD(ID_ISAR3, SIMD, 4, 4) 1647 FIELD(ID_ISAR3, SVC, 8, 4) 1648 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1649 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1650 FIELD(ID_ISAR3, T32COPY, 20, 4) 1651 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1652 FIELD(ID_ISAR3, T32EE, 28, 4) 1653 1654 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1655 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1656 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1657 FIELD(ID_ISAR4, SMC, 12, 4) 1658 FIELD(ID_ISAR4, BARRIER, 16, 4) 1659 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1660 FIELD(ID_ISAR4, PSR_M, 24, 4) 1661 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1662 1663 FIELD(ID_ISAR5, SEVL, 0, 4) 1664 FIELD(ID_ISAR5, AES, 4, 4) 1665 FIELD(ID_ISAR5, SHA1, 8, 4) 1666 FIELD(ID_ISAR5, SHA2, 12, 4) 1667 FIELD(ID_ISAR5, CRC32, 16, 4) 1668 FIELD(ID_ISAR5, RDM, 24, 4) 1669 FIELD(ID_ISAR5, VCMA, 28, 4) 1670 1671 FIELD(ID_ISAR6, JSCVT, 0, 4) 1672 FIELD(ID_ISAR6, DP, 4, 4) 1673 FIELD(ID_ISAR6, FHM, 8, 4) 1674 FIELD(ID_ISAR6, SB, 12, 4) 1675 FIELD(ID_ISAR6, SPECRES, 16, 4) 1676 1677 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1678 FIELD(ID_MMFR4, AC2, 4, 4) 1679 FIELD(ID_MMFR4, XNX, 8, 4) 1680 FIELD(ID_MMFR4, CNP, 12, 4) 1681 FIELD(ID_MMFR4, HPDS, 16, 4) 1682 FIELD(ID_MMFR4, LSM, 20, 4) 1683 FIELD(ID_MMFR4, CCIDX, 24, 4) 1684 FIELD(ID_MMFR4, EVT, 28, 4) 1685 1686 FIELD(ID_AA64ISAR0, AES, 4, 4) 1687 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1688 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1689 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1690 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1691 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1692 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1693 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1694 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1695 FIELD(ID_AA64ISAR0, DP, 44, 4) 1696 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1697 FIELD(ID_AA64ISAR0, TS, 52, 4) 1698 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1699 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1700 1701 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1702 FIELD(ID_AA64ISAR1, APA, 4, 4) 1703 FIELD(ID_AA64ISAR1, API, 8, 4) 1704 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1705 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1706 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1707 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1708 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1709 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1710 FIELD(ID_AA64ISAR1, SB, 36, 4) 1711 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1712 1713 FIELD(ID_AA64PFR0, EL0, 0, 4) 1714 FIELD(ID_AA64PFR0, EL1, 4, 4) 1715 FIELD(ID_AA64PFR0, EL2, 8, 4) 1716 FIELD(ID_AA64PFR0, EL3, 12, 4) 1717 FIELD(ID_AA64PFR0, FP, 16, 4) 1718 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1719 FIELD(ID_AA64PFR0, GIC, 24, 4) 1720 FIELD(ID_AA64PFR0, RAS, 28, 4) 1721 FIELD(ID_AA64PFR0, SVE, 32, 4) 1722 1723 FIELD(ID_AA64PFR1, BT, 0, 4) 1724 FIELD(ID_AA64PFR1, SBSS, 4, 4) 1725 FIELD(ID_AA64PFR1, MTE, 8, 4) 1726 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1727 1728 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1729 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1730 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1731 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1732 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1733 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1734 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1735 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1736 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1737 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1738 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1739 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1740 1741 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1742 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1743 FIELD(ID_AA64MMFR1, VH, 8, 4) 1744 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1745 FIELD(ID_AA64MMFR1, LO, 16, 4) 1746 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1747 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1748 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1749 1750 FIELD(ID_DFR0, COPDBG, 0, 4) 1751 FIELD(ID_DFR0, COPSDBG, 4, 4) 1752 FIELD(ID_DFR0, MMAPDBG, 8, 4) 1753 FIELD(ID_DFR0, COPTRC, 12, 4) 1754 FIELD(ID_DFR0, MMAPTRC, 16, 4) 1755 FIELD(ID_DFR0, MPROFDBG, 20, 4) 1756 FIELD(ID_DFR0, PERFMON, 24, 4) 1757 FIELD(ID_DFR0, TRACEFILT, 28, 4) 1758 1759 FIELD(MVFR0, SIMDREG, 0, 4) 1760 FIELD(MVFR0, FPSP, 4, 4) 1761 FIELD(MVFR0, FPDP, 8, 4) 1762 FIELD(MVFR0, FPTRAP, 12, 4) 1763 FIELD(MVFR0, FPDIVIDE, 16, 4) 1764 FIELD(MVFR0, FPSQRT, 20, 4) 1765 FIELD(MVFR0, FPSHVEC, 24, 4) 1766 FIELD(MVFR0, FPROUND, 28, 4) 1767 1768 FIELD(MVFR1, FPFTZ, 0, 4) 1769 FIELD(MVFR1, FPDNAN, 4, 4) 1770 FIELD(MVFR1, SIMDLS, 8, 4) 1771 FIELD(MVFR1, SIMDINT, 12, 4) 1772 FIELD(MVFR1, SIMDSP, 16, 4) 1773 FIELD(MVFR1, SIMDHP, 20, 4) 1774 FIELD(MVFR1, FPHP, 24, 4) 1775 FIELD(MVFR1, SIMDFMAC, 28, 4) 1776 1777 FIELD(MVFR2, SIMDMISC, 0, 4) 1778 FIELD(MVFR2, FPMISC, 4, 4) 1779 1780 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1781 1782 /* If adding a feature bit which corresponds to a Linux ELF 1783 * HWCAP bit, remember to update the feature-bit-to-hwcap 1784 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1785 */ 1786 enum arm_features { 1787 ARM_FEATURE_VFP, 1788 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1789 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1790 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1791 ARM_FEATURE_V6, 1792 ARM_FEATURE_V6K, 1793 ARM_FEATURE_V7, 1794 ARM_FEATURE_THUMB2, 1795 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1796 ARM_FEATURE_VFP3, 1797 ARM_FEATURE_NEON, 1798 ARM_FEATURE_M, /* Microcontroller profile. */ 1799 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1800 ARM_FEATURE_THUMB2EE, 1801 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1802 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1803 ARM_FEATURE_V4T, 1804 ARM_FEATURE_V5, 1805 ARM_FEATURE_STRONGARM, 1806 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1807 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1808 ARM_FEATURE_GENERIC_TIMER, 1809 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1810 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1811 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1812 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1813 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1814 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1815 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1816 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1817 ARM_FEATURE_V8, 1818 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1819 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1820 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1821 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1822 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1823 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1824 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1825 ARM_FEATURE_PMU, /* has PMU support */ 1826 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1827 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1828 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1829 }; 1830 1831 static inline int arm_feature(CPUARMState *env, int feature) 1832 { 1833 return (env->features & (1ULL << feature)) != 0; 1834 } 1835 1836 #if !defined(CONFIG_USER_ONLY) 1837 /* Return true if exception levels below EL3 are in secure state, 1838 * or would be following an exception return to that level. 1839 * Unlike arm_is_secure() (which is always a question about the 1840 * _current_ state of the CPU) this doesn't care about the current 1841 * EL or mode. 1842 */ 1843 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1844 { 1845 if (arm_feature(env, ARM_FEATURE_EL3)) { 1846 return !(env->cp15.scr_el3 & SCR_NS); 1847 } else { 1848 /* If EL3 is not supported then the secure state is implementation 1849 * defined, in which case QEMU defaults to non-secure. 1850 */ 1851 return false; 1852 } 1853 } 1854 1855 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1856 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1857 { 1858 if (arm_feature(env, ARM_FEATURE_EL3)) { 1859 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1860 /* CPU currently in AArch64 state and EL3 */ 1861 return true; 1862 } else if (!is_a64(env) && 1863 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1864 /* CPU currently in AArch32 state and monitor mode */ 1865 return true; 1866 } 1867 } 1868 return false; 1869 } 1870 1871 /* Return true if the processor is in secure state */ 1872 static inline bool arm_is_secure(CPUARMState *env) 1873 { 1874 if (arm_is_el3_or_mon(env)) { 1875 return true; 1876 } 1877 return arm_is_secure_below_el3(env); 1878 } 1879 1880 #else 1881 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1882 { 1883 return false; 1884 } 1885 1886 static inline bool arm_is_secure(CPUARMState *env) 1887 { 1888 return false; 1889 } 1890 #endif 1891 1892 /** 1893 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 1894 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 1895 * "for all purposes other than a direct read or write access of HCR_EL2." 1896 * Not included here is HCR_RW. 1897 */ 1898 uint64_t arm_hcr_el2_eff(CPUARMState *env); 1899 1900 /* Return true if the specified exception level is running in AArch64 state. */ 1901 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1902 { 1903 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1904 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1905 */ 1906 assert(el >= 1 && el <= 3); 1907 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1908 1909 /* The highest exception level is always at the maximum supported 1910 * register width, and then lower levels have a register width controlled 1911 * by bits in the SCR or HCR registers. 1912 */ 1913 if (el == 3) { 1914 return aa64; 1915 } 1916 1917 if (arm_feature(env, ARM_FEATURE_EL3)) { 1918 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1919 } 1920 1921 if (el == 2) { 1922 return aa64; 1923 } 1924 1925 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1926 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1927 } 1928 1929 return aa64; 1930 } 1931 1932 /* Function for determing whether guest cp register reads and writes should 1933 * access the secure or non-secure bank of a cp register. When EL3 is 1934 * operating in AArch32 state, the NS-bit determines whether the secure 1935 * instance of a cp register should be used. When EL3 is AArch64 (or if 1936 * it doesn't exist at all) then there is no register banking, and all 1937 * accesses are to the non-secure version. 1938 */ 1939 static inline bool access_secure_reg(CPUARMState *env) 1940 { 1941 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1942 !arm_el_is_aa64(env, 3) && 1943 !(env->cp15.scr_el3 & SCR_NS)); 1944 1945 return ret; 1946 } 1947 1948 /* Macros for accessing a specified CP register bank */ 1949 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1950 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1951 1952 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1953 do { \ 1954 if (_secure) { \ 1955 (_env)->cp15._regname##_s = (_val); \ 1956 } else { \ 1957 (_env)->cp15._regname##_ns = (_val); \ 1958 } \ 1959 } while (0) 1960 1961 /* Macros for automatically accessing a specific CP register bank depending on 1962 * the current secure state of the system. These macros are not intended for 1963 * supporting instruction translation reads/writes as these are dependent 1964 * solely on the SCR.NS bit and not the mode. 1965 */ 1966 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1967 A32_BANKED_REG_GET((_env), _regname, \ 1968 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1969 1970 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1971 A32_BANKED_REG_SET((_env), _regname, \ 1972 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1973 (_val)) 1974 1975 void arm_cpu_list(void); 1976 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1977 uint32_t cur_el, bool secure); 1978 1979 /* Interface between CPU and Interrupt controller. */ 1980 #ifndef CONFIG_USER_ONLY 1981 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1982 #else 1983 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1984 { 1985 return true; 1986 } 1987 #endif 1988 /** 1989 * armv7m_nvic_set_pending: mark the specified exception as pending 1990 * @opaque: the NVIC 1991 * @irq: the exception number to mark pending 1992 * @secure: false for non-banked exceptions or for the nonsecure 1993 * version of a banked exception, true for the secure version of a banked 1994 * exception. 1995 * 1996 * Marks the specified exception as pending. Note that we will assert() 1997 * if @secure is true and @irq does not specify one of the fixed set 1998 * of architecturally banked exceptions. 1999 */ 2000 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2001 /** 2002 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2003 * @opaque: the NVIC 2004 * @irq: the exception number to mark pending 2005 * @secure: false for non-banked exceptions or for the nonsecure 2006 * version of a banked exception, true for the secure version of a banked 2007 * exception. 2008 * 2009 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2010 * exceptions (exceptions generated in the course of trying to take 2011 * a different exception). 2012 */ 2013 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2014 /** 2015 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2016 * @opaque: the NVIC 2017 * @irq: the exception number to mark pending 2018 * @secure: false for non-banked exceptions or for the nonsecure 2019 * version of a banked exception, true for the secure version of a banked 2020 * exception. 2021 * 2022 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2023 * generated in the course of lazy stacking of FP registers. 2024 */ 2025 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2026 /** 2027 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2028 * exception, and whether it targets Secure state 2029 * @opaque: the NVIC 2030 * @pirq: set to pending exception number 2031 * @ptargets_secure: set to whether pending exception targets Secure 2032 * 2033 * This function writes the number of the highest priority pending 2034 * exception (the one which would be made active by 2035 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2036 * to true if the current highest priority pending exception should 2037 * be taken to Secure state, false for NS. 2038 */ 2039 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2040 bool *ptargets_secure); 2041 /** 2042 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2043 * @opaque: the NVIC 2044 * 2045 * Move the current highest priority pending exception from the pending 2046 * state to the active state, and update v7m.exception to indicate that 2047 * it is the exception currently being handled. 2048 */ 2049 void armv7m_nvic_acknowledge_irq(void *opaque); 2050 /** 2051 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2052 * @opaque: the NVIC 2053 * @irq: the exception number to complete 2054 * @secure: true if this exception was secure 2055 * 2056 * Returns: -1 if the irq was not active 2057 * 1 if completing this irq brought us back to base (no active irqs) 2058 * 0 if there is still an irq active after this one was completed 2059 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2060 */ 2061 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2062 /** 2063 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2064 * @opaque: the NVIC 2065 * @irq: the exception number to mark pending 2066 * @secure: false for non-banked exceptions or for the nonsecure 2067 * version of a banked exception, true for the secure version of a banked 2068 * exception. 2069 * 2070 * Return whether an exception is "ready", i.e. whether the exception is 2071 * enabled and is configured at a priority which would allow it to 2072 * interrupt the current execution priority. This controls whether the 2073 * RDY bit for it in the FPCCR is set. 2074 */ 2075 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2076 /** 2077 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2078 * @opaque: the NVIC 2079 * 2080 * Returns: the raw execution priority as defined by the v8M architecture. 2081 * This is the execution priority minus the effects of AIRCR.PRIS, 2082 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2083 * (v8M ARM ARM I_PKLD.) 2084 */ 2085 int armv7m_nvic_raw_execution_priority(void *opaque); 2086 /** 2087 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2088 * priority is negative for the specified security state. 2089 * @opaque: the NVIC 2090 * @secure: the security state to test 2091 * This corresponds to the pseudocode IsReqExecPriNeg(). 2092 */ 2093 #ifndef CONFIG_USER_ONLY 2094 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2095 #else 2096 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2097 { 2098 return false; 2099 } 2100 #endif 2101 2102 /* Interface for defining coprocessor registers. 2103 * Registers are defined in tables of arm_cp_reginfo structs 2104 * which are passed to define_arm_cp_regs(). 2105 */ 2106 2107 /* When looking up a coprocessor register we look for it 2108 * via an integer which encodes all of: 2109 * coprocessor number 2110 * Crn, Crm, opc1, opc2 fields 2111 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2112 * or via MRRC/MCRR?) 2113 * non-secure/secure bank (AArch32 only) 2114 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2115 * (In this case crn and opc2 should be zero.) 2116 * For AArch64, there is no 32/64 bit size distinction; 2117 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2118 * and 4 bit CRn and CRm. The encoding patterns are chosen 2119 * to be easy to convert to and from the KVM encodings, and also 2120 * so that the hashtable can contain both AArch32 and AArch64 2121 * registers (to allow for interprocessing where we might run 2122 * 32 bit code on a 64 bit core). 2123 */ 2124 /* This bit is private to our hashtable cpreg; in KVM register 2125 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2126 * in the upper bits of the 64 bit ID. 2127 */ 2128 #define CP_REG_AA64_SHIFT 28 2129 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2130 2131 /* To enable banking of coprocessor registers depending on ns-bit we 2132 * add a bit to distinguish between secure and non-secure cpregs in the 2133 * hashtable. 2134 */ 2135 #define CP_REG_NS_SHIFT 29 2136 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2137 2138 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2139 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2140 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2141 2142 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2143 (CP_REG_AA64_MASK | \ 2144 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2145 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2146 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2147 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2148 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2149 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2150 2151 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2152 * version used as a key for the coprocessor register hashtable 2153 */ 2154 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2155 { 2156 uint32_t cpregid = kvmid; 2157 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2158 cpregid |= CP_REG_AA64_MASK; 2159 } else { 2160 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2161 cpregid |= (1 << 15); 2162 } 2163 2164 /* KVM is always non-secure so add the NS flag on AArch32 register 2165 * entries. 2166 */ 2167 cpregid |= 1 << CP_REG_NS_SHIFT; 2168 } 2169 return cpregid; 2170 } 2171 2172 /* Convert a truncated 32 bit hashtable key into the full 2173 * 64 bit KVM register ID. 2174 */ 2175 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2176 { 2177 uint64_t kvmid; 2178 2179 if (cpregid & CP_REG_AA64_MASK) { 2180 kvmid = cpregid & ~CP_REG_AA64_MASK; 2181 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2182 } else { 2183 kvmid = cpregid & ~(1 << 15); 2184 if (cpregid & (1 << 15)) { 2185 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2186 } else { 2187 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2188 } 2189 } 2190 return kvmid; 2191 } 2192 2193 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2194 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2195 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2196 * TCG can assume the value to be constant (ie load at translate time) 2197 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2198 * indicates that the TB should not be ended after a write to this register 2199 * (the default is that the TB ends after cp writes). OVERRIDE permits 2200 * a register definition to override a previous definition for the 2201 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2202 * old must have the OVERRIDE bit set. 2203 * ALIAS indicates that this register is an alias view of some underlying 2204 * state which is also visible via another register, and that the other 2205 * register is handling migration and reset; registers marked ALIAS will not be 2206 * migrated but may have their state set by syncing of register state from KVM. 2207 * NO_RAW indicates that this register has no underlying state and does not 2208 * support raw access for state saving/loading; it will not be used for either 2209 * migration or KVM state synchronization. (Typically this is for "registers" 2210 * which are actually used as instructions for cache maintenance and so on.) 2211 * IO indicates that this register does I/O and therefore its accesses 2212 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2213 * registers which implement clocks or timers require this. 2214 */ 2215 #define ARM_CP_SPECIAL 0x0001 2216 #define ARM_CP_CONST 0x0002 2217 #define ARM_CP_64BIT 0x0004 2218 #define ARM_CP_SUPPRESS_TB_END 0x0008 2219 #define ARM_CP_OVERRIDE 0x0010 2220 #define ARM_CP_ALIAS 0x0020 2221 #define ARM_CP_IO 0x0040 2222 #define ARM_CP_NO_RAW 0x0080 2223 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2224 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2225 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2226 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2227 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2228 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2229 #define ARM_CP_FPU 0x1000 2230 #define ARM_CP_SVE 0x2000 2231 #define ARM_CP_NO_GDB 0x4000 2232 /* Used only as a terminator for ARMCPRegInfo lists */ 2233 #define ARM_CP_SENTINEL 0xffff 2234 /* Mask of only the flag bits in a type field */ 2235 #define ARM_CP_FLAG_MASK 0x70ff 2236 2237 /* Valid values for ARMCPRegInfo state field, indicating which of 2238 * the AArch32 and AArch64 execution states this register is visible in. 2239 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2240 * If the reginfo is declared to be visible in both states then a second 2241 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2242 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2243 * Note that we rely on the values of these enums as we iterate through 2244 * the various states in some places. 2245 */ 2246 enum { 2247 ARM_CP_STATE_AA32 = 0, 2248 ARM_CP_STATE_AA64 = 1, 2249 ARM_CP_STATE_BOTH = 2, 2250 }; 2251 2252 /* ARM CP register secure state flags. These flags identify security state 2253 * attributes for a given CP register entry. 2254 * The existence of both or neither secure and non-secure flags indicates that 2255 * the register has both a secure and non-secure hash entry. A single one of 2256 * these flags causes the register to only be hashed for the specified 2257 * security state. 2258 * Although definitions may have any combination of the S/NS bits, each 2259 * registered entry will only have one to identify whether the entry is secure 2260 * or non-secure. 2261 */ 2262 enum { 2263 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2264 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2265 }; 2266 2267 /* Return true if cptype is a valid type field. This is used to try to 2268 * catch errors where the sentinel has been accidentally left off the end 2269 * of a list of registers. 2270 */ 2271 static inline bool cptype_valid(int cptype) 2272 { 2273 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2274 || ((cptype & ARM_CP_SPECIAL) && 2275 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2276 } 2277 2278 /* Access rights: 2279 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2280 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2281 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2282 * (ie any of the privileged modes in Secure state, or Monitor mode). 2283 * If a register is accessible in one privilege level it's always accessible 2284 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2285 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2286 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2287 * terminology a little and call this PL3. 2288 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2289 * with the ELx exception levels. 2290 * 2291 * If access permissions for a register are more complex than can be 2292 * described with these bits, then use a laxer set of restrictions, and 2293 * do the more restrictive/complex check inside a helper function. 2294 */ 2295 #define PL3_R 0x80 2296 #define PL3_W 0x40 2297 #define PL2_R (0x20 | PL3_R) 2298 #define PL2_W (0x10 | PL3_W) 2299 #define PL1_R (0x08 | PL2_R) 2300 #define PL1_W (0x04 | PL2_W) 2301 #define PL0_R (0x02 | PL1_R) 2302 #define PL0_W (0x01 | PL1_W) 2303 2304 /* 2305 * For user-mode some registers are accessible to EL0 via a kernel 2306 * trap-and-emulate ABI. In this case we define the read permissions 2307 * as actually being PL0_R. However some bits of any given register 2308 * may still be masked. 2309 */ 2310 #ifdef CONFIG_USER_ONLY 2311 #define PL0U_R PL0_R 2312 #else 2313 #define PL0U_R PL1_R 2314 #endif 2315 2316 #define PL3_RW (PL3_R | PL3_W) 2317 #define PL2_RW (PL2_R | PL2_W) 2318 #define PL1_RW (PL1_R | PL1_W) 2319 #define PL0_RW (PL0_R | PL0_W) 2320 2321 /* Return the highest implemented Exception Level */ 2322 static inline int arm_highest_el(CPUARMState *env) 2323 { 2324 if (arm_feature(env, ARM_FEATURE_EL3)) { 2325 return 3; 2326 } 2327 if (arm_feature(env, ARM_FEATURE_EL2)) { 2328 return 2; 2329 } 2330 return 1; 2331 } 2332 2333 /* Return true if a v7M CPU is in Handler mode */ 2334 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2335 { 2336 return env->v7m.exception != 0; 2337 } 2338 2339 /* Return the current Exception Level (as per ARMv8; note that this differs 2340 * from the ARMv7 Privilege Level). 2341 */ 2342 static inline int arm_current_el(CPUARMState *env) 2343 { 2344 if (arm_feature(env, ARM_FEATURE_M)) { 2345 return arm_v7m_is_handler_mode(env) || 2346 !(env->v7m.control[env->v7m.secure] & 1); 2347 } 2348 2349 if (is_a64(env)) { 2350 return extract32(env->pstate, 2, 2); 2351 } 2352 2353 switch (env->uncached_cpsr & 0x1f) { 2354 case ARM_CPU_MODE_USR: 2355 return 0; 2356 case ARM_CPU_MODE_HYP: 2357 return 2; 2358 case ARM_CPU_MODE_MON: 2359 return 3; 2360 default: 2361 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2362 /* If EL3 is 32-bit then all secure privileged modes run in 2363 * EL3 2364 */ 2365 return 3; 2366 } 2367 2368 return 1; 2369 } 2370 } 2371 2372 typedef struct ARMCPRegInfo ARMCPRegInfo; 2373 2374 typedef enum CPAccessResult { 2375 /* Access is permitted */ 2376 CP_ACCESS_OK = 0, 2377 /* Access fails due to a configurable trap or enable which would 2378 * result in a categorized exception syndrome giving information about 2379 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2380 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2381 * PL1 if in EL0, otherwise to the current EL). 2382 */ 2383 CP_ACCESS_TRAP = 1, 2384 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2385 * Note that this is not a catch-all case -- the set of cases which may 2386 * result in this failure is specifically defined by the architecture. 2387 */ 2388 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2389 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2390 CP_ACCESS_TRAP_EL2 = 3, 2391 CP_ACCESS_TRAP_EL3 = 4, 2392 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2393 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2394 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2395 /* Access fails and results in an exception syndrome for an FP access, 2396 * trapped directly to EL2 or EL3 2397 */ 2398 CP_ACCESS_TRAP_FP_EL2 = 7, 2399 CP_ACCESS_TRAP_FP_EL3 = 8, 2400 } CPAccessResult; 2401 2402 /* Access functions for coprocessor registers. These cannot fail and 2403 * may not raise exceptions. 2404 */ 2405 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2406 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2407 uint64_t value); 2408 /* Access permission check functions for coprocessor registers. */ 2409 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2410 const ARMCPRegInfo *opaque, 2411 bool isread); 2412 /* Hook function for register reset */ 2413 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2414 2415 #define CP_ANY 0xff 2416 2417 /* Definition of an ARM coprocessor register */ 2418 struct ARMCPRegInfo { 2419 /* Name of register (useful mainly for debugging, need not be unique) */ 2420 const char *name; 2421 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2422 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2423 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2424 * will be decoded to this register. The register read and write 2425 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2426 * used by the program, so it is possible to register a wildcard and 2427 * then behave differently on read/write if necessary. 2428 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2429 * must both be zero. 2430 * For AArch64-visible registers, opc0 is also used. 2431 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2432 * way to distinguish (for KVM's benefit) guest-visible system registers 2433 * from demuxed ones provided to preserve the "no side effects on 2434 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2435 * visible (to match KVM's encoding); cp==0 will be converted to 2436 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2437 */ 2438 uint8_t cp; 2439 uint8_t crn; 2440 uint8_t crm; 2441 uint8_t opc0; 2442 uint8_t opc1; 2443 uint8_t opc2; 2444 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2445 int state; 2446 /* Register type: ARM_CP_* bits/values */ 2447 int type; 2448 /* Access rights: PL*_[RW] */ 2449 int access; 2450 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2451 int secure; 2452 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2453 * this register was defined: can be used to hand data through to the 2454 * register read/write functions, since they are passed the ARMCPRegInfo*. 2455 */ 2456 void *opaque; 2457 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2458 * fieldoffset is non-zero, the reset value of the register. 2459 */ 2460 uint64_t resetvalue; 2461 /* Offset of the field in CPUARMState for this register. 2462 * 2463 * This is not needed if either: 2464 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2465 * 2. both readfn and writefn are specified 2466 */ 2467 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2468 2469 /* Offsets of the secure and non-secure fields in CPUARMState for the 2470 * register if it is banked. These fields are only used during the static 2471 * registration of a register. During hashing the bank associated 2472 * with a given security state is copied to fieldoffset which is used from 2473 * there on out. 2474 * 2475 * It is expected that register definitions use either fieldoffset or 2476 * bank_fieldoffsets in the definition but not both. It is also expected 2477 * that both bank offsets are set when defining a banked register. This 2478 * use indicates that a register is banked. 2479 */ 2480 ptrdiff_t bank_fieldoffsets[2]; 2481 2482 /* Function for making any access checks for this register in addition to 2483 * those specified by the 'access' permissions bits. If NULL, no extra 2484 * checks required. The access check is performed at runtime, not at 2485 * translate time. 2486 */ 2487 CPAccessFn *accessfn; 2488 /* Function for handling reads of this register. If NULL, then reads 2489 * will be done by loading from the offset into CPUARMState specified 2490 * by fieldoffset. 2491 */ 2492 CPReadFn *readfn; 2493 /* Function for handling writes of this register. If NULL, then writes 2494 * will be done by writing to the offset into CPUARMState specified 2495 * by fieldoffset. 2496 */ 2497 CPWriteFn *writefn; 2498 /* Function for doing a "raw" read; used when we need to copy 2499 * coprocessor state to the kernel for KVM or out for 2500 * migration. This only needs to be provided if there is also a 2501 * readfn and it has side effects (for instance clear-on-read bits). 2502 */ 2503 CPReadFn *raw_readfn; 2504 /* Function for doing a "raw" write; used when we need to copy KVM 2505 * kernel coprocessor state into userspace, or for inbound 2506 * migration. This only needs to be provided if there is also a 2507 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2508 * or similar behaviour. 2509 */ 2510 CPWriteFn *raw_writefn; 2511 /* Function for resetting the register. If NULL, then reset will be done 2512 * by writing resetvalue to the field specified in fieldoffset. If 2513 * fieldoffset is 0 then no reset will be done. 2514 */ 2515 CPResetFn *resetfn; 2516 }; 2517 2518 /* Macros which are lvalues for the field in CPUARMState for the 2519 * ARMCPRegInfo *ri. 2520 */ 2521 #define CPREG_FIELD32(env, ri) \ 2522 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2523 #define CPREG_FIELD64(env, ri) \ 2524 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2525 2526 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2527 2528 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2529 const ARMCPRegInfo *regs, void *opaque); 2530 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2531 const ARMCPRegInfo *regs, void *opaque); 2532 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2533 { 2534 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2535 } 2536 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2537 { 2538 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2539 } 2540 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2541 2542 /* 2543 * Definition of an ARM co-processor register as viewed from 2544 * userspace. This is used for presenting sanitised versions of 2545 * registers to userspace when emulating the Linux AArch64 CPU 2546 * ID/feature ABI (advertised as HWCAP_CPUID). 2547 */ 2548 typedef struct ARMCPRegUserSpaceInfo { 2549 /* Name of register */ 2550 const char *name; 2551 2552 /* Is the name actually a glob pattern */ 2553 bool is_glob; 2554 2555 /* Only some bits are exported to user space */ 2556 uint64_t exported_bits; 2557 2558 /* Fixed bits are applied after the mask */ 2559 uint64_t fixed_bits; 2560 } ARMCPRegUserSpaceInfo; 2561 2562 #define REGUSERINFO_SENTINEL { .name = NULL } 2563 2564 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2565 2566 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2567 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2568 uint64_t value); 2569 /* CPReadFn that can be used for read-as-zero behaviour */ 2570 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2571 2572 /* CPResetFn that does nothing, for use if no reset is required even 2573 * if fieldoffset is non zero. 2574 */ 2575 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2576 2577 /* Return true if this reginfo struct's field in the cpu state struct 2578 * is 64 bits wide. 2579 */ 2580 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2581 { 2582 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2583 } 2584 2585 static inline bool cp_access_ok(int current_el, 2586 const ARMCPRegInfo *ri, int isread) 2587 { 2588 return (ri->access >> ((current_el * 2) + isread)) & 1; 2589 } 2590 2591 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2592 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2593 2594 /** 2595 * write_list_to_cpustate 2596 * @cpu: ARMCPU 2597 * 2598 * For each register listed in the ARMCPU cpreg_indexes list, write 2599 * its value from the cpreg_values list into the ARMCPUState structure. 2600 * This updates TCG's working data structures from KVM data or 2601 * from incoming migration state. 2602 * 2603 * Returns: true if all register values were updated correctly, 2604 * false if some register was unknown or could not be written. 2605 * Note that we do not stop early on failure -- we will attempt 2606 * writing all registers in the list. 2607 */ 2608 bool write_list_to_cpustate(ARMCPU *cpu); 2609 2610 /** 2611 * write_cpustate_to_list: 2612 * @cpu: ARMCPU 2613 * @kvm_sync: true if this is for syncing back to KVM 2614 * 2615 * For each register listed in the ARMCPU cpreg_indexes list, write 2616 * its value from the ARMCPUState structure into the cpreg_values list. 2617 * This is used to copy info from TCG's working data structures into 2618 * KVM or for outbound migration. 2619 * 2620 * @kvm_sync is true if we are doing this in order to sync the 2621 * register state back to KVM. In this case we will only update 2622 * values in the list if the previous list->cpustate sync actually 2623 * successfully wrote the CPU state. Otherwise we will keep the value 2624 * that is in the list. 2625 * 2626 * Returns: true if all register values were read correctly, 2627 * false if some register was unknown or could not be read. 2628 * Note that we do not stop early on failure -- we will attempt 2629 * reading all registers in the list. 2630 */ 2631 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2632 2633 #define ARM_CPUID_TI915T 0x54029152 2634 #define ARM_CPUID_TI925T 0x54029252 2635 2636 #if defined(CONFIG_USER_ONLY) 2637 #define TARGET_PAGE_BITS 12 2638 #else 2639 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2640 * have to support 1K tiny pages. 2641 */ 2642 #define TARGET_PAGE_BITS_VARY 2643 #define TARGET_PAGE_BITS_MIN 10 2644 #endif 2645 2646 #if defined(TARGET_AARCH64) 2647 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2648 # define TARGET_VIRT_ADDR_SPACE_BITS 48 2649 #else 2650 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2651 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2652 #endif 2653 2654 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2655 unsigned int target_el) 2656 { 2657 CPUARMState *env = cs->env_ptr; 2658 unsigned int cur_el = arm_current_el(env); 2659 bool secure = arm_is_secure(env); 2660 bool pstate_unmasked; 2661 int8_t unmasked = 0; 2662 uint64_t hcr_el2; 2663 2664 /* Don't take exceptions if they target a lower EL. 2665 * This check should catch any exceptions that would not be taken but left 2666 * pending. 2667 */ 2668 if (cur_el > target_el) { 2669 return false; 2670 } 2671 2672 hcr_el2 = arm_hcr_el2_eff(env); 2673 2674 switch (excp_idx) { 2675 case EXCP_FIQ: 2676 pstate_unmasked = !(env->daif & PSTATE_F); 2677 break; 2678 2679 case EXCP_IRQ: 2680 pstate_unmasked = !(env->daif & PSTATE_I); 2681 break; 2682 2683 case EXCP_VFIQ: 2684 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 2685 /* VFIQs are only taken when hypervized and non-secure. */ 2686 return false; 2687 } 2688 return !(env->daif & PSTATE_F); 2689 case EXCP_VIRQ: 2690 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 2691 /* VIRQs are only taken when hypervized and non-secure. */ 2692 return false; 2693 } 2694 return !(env->daif & PSTATE_I); 2695 default: 2696 g_assert_not_reached(); 2697 } 2698 2699 /* Use the target EL, current execution state and SCR/HCR settings to 2700 * determine whether the corresponding CPSR bit is used to mask the 2701 * interrupt. 2702 */ 2703 if ((target_el > cur_el) && (target_el != 1)) { 2704 /* Exceptions targeting a higher EL may not be maskable */ 2705 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2706 /* 64-bit masking rules are simple: exceptions to EL3 2707 * can't be masked, and exceptions to EL2 can only be 2708 * masked from Secure state. The HCR and SCR settings 2709 * don't affect the masking logic, only the interrupt routing. 2710 */ 2711 if (target_el == 3 || !secure) { 2712 unmasked = 1; 2713 } 2714 } else { 2715 /* The old 32-bit-only environment has a more complicated 2716 * masking setup. HCR and SCR bits not only affect interrupt 2717 * routing but also change the behaviour of masking. 2718 */ 2719 bool hcr, scr; 2720 2721 switch (excp_idx) { 2722 case EXCP_FIQ: 2723 /* If FIQs are routed to EL3 or EL2 then there are cases where 2724 * we override the CPSR.F in determining if the exception is 2725 * masked or not. If neither of these are set then we fall back 2726 * to the CPSR.F setting otherwise we further assess the state 2727 * below. 2728 */ 2729 hcr = hcr_el2 & HCR_FMO; 2730 scr = (env->cp15.scr_el3 & SCR_FIQ); 2731 2732 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2733 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2734 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2735 * when non-secure but only when FIQs are only routed to EL3. 2736 */ 2737 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2738 break; 2739 case EXCP_IRQ: 2740 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2741 * we may override the CPSR.I masking when in non-secure state. 2742 * The SCR.IRQ setting has already been taken into consideration 2743 * when setting the target EL, so it does not have a further 2744 * affect here. 2745 */ 2746 hcr = hcr_el2 & HCR_IMO; 2747 scr = false; 2748 break; 2749 default: 2750 g_assert_not_reached(); 2751 } 2752 2753 if ((scr || hcr) && !secure) { 2754 unmasked = 1; 2755 } 2756 } 2757 } 2758 2759 /* The PSTATE bits only mask the interrupt if we have not overriden the 2760 * ability above. 2761 */ 2762 return unmasked || pstate_unmasked; 2763 } 2764 2765 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2766 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2767 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2768 2769 #define cpu_signal_handler cpu_arm_signal_handler 2770 #define cpu_list arm_cpu_list 2771 2772 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2773 * 2774 * If EL3 is 64-bit: 2775 * + NonSecure EL1 & 0 stage 1 2776 * + NonSecure EL1 & 0 stage 2 2777 * + NonSecure EL2 2778 * + Secure EL1 & EL0 2779 * + Secure EL3 2780 * If EL3 is 32-bit: 2781 * + NonSecure PL1 & 0 stage 1 2782 * + NonSecure PL1 & 0 stage 2 2783 * + NonSecure PL2 2784 * + Secure PL0 & PL1 2785 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2786 * 2787 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2788 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2789 * may differ in access permissions even if the VA->PA map is the same 2790 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2791 * translation, which means that we have one mmu_idx that deals with two 2792 * concatenated translation regimes [this sort of combined s1+2 TLB is 2793 * architecturally permitted] 2794 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2795 * handling via the TLB. The only way to do a stage 1 translation without 2796 * the immediate stage 2 translation is via the ATS or AT system insns, 2797 * which can be slow-pathed and always do a page table walk. 2798 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2799 * translation regimes, because they map reasonably well to each other 2800 * and they can't both be active at the same time. 2801 * This gives us the following list of mmu_idx values: 2802 * 2803 * NS EL0 (aka NS PL0) stage 1+2 2804 * NS EL1 (aka NS PL1) stage 1+2 2805 * NS EL2 (aka NS PL2) 2806 * S EL3 (aka S PL1) 2807 * S EL0 (aka S PL0) 2808 * S EL1 (not used if EL3 is 32 bit) 2809 * NS EL0+1 stage 2 2810 * 2811 * (The last of these is an mmu_idx because we want to be able to use the TLB 2812 * for the accesses done as part of a stage 1 page table walk, rather than 2813 * having to walk the stage 2 page table over and over.) 2814 * 2815 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2816 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2817 * NS EL2 if we ever model a Cortex-R52). 2818 * 2819 * M profile CPUs are rather different as they do not have a true MMU. 2820 * They have the following different MMU indexes: 2821 * User 2822 * Privileged 2823 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2824 * Privileged, execution priority negative (ditto) 2825 * If the CPU supports the v8M Security Extension then there are also: 2826 * Secure User 2827 * Secure Privileged 2828 * Secure User, execution priority negative 2829 * Secure Privileged, execution priority negative 2830 * 2831 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2832 * are not quite the same -- different CPU types (most notably M profile 2833 * vs A/R profile) would like to use MMU indexes with different semantics, 2834 * but since we don't ever need to use all of those in a single CPU we 2835 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2836 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2837 * the same for any particular CPU. 2838 * Variables of type ARMMUIdx are always full values, and the core 2839 * index values are in variables of type 'int'. 2840 * 2841 * Our enumeration includes at the end some entries which are not "true" 2842 * mmu_idx values in that they don't have corresponding TLBs and are only 2843 * valid for doing slow path page table walks. 2844 * 2845 * The constant names here are patterned after the general style of the names 2846 * of the AT/ATS operations. 2847 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2848 * For M profile we arrange them to have a bit for priv, a bit for negpri 2849 * and a bit for secure. 2850 */ 2851 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2852 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2853 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2854 2855 /* meanings of the bits for M profile mmu idx values */ 2856 #define ARM_MMU_IDX_M_PRIV 0x1 2857 #define ARM_MMU_IDX_M_NEGPRI 0x2 2858 #define ARM_MMU_IDX_M_S 0x4 2859 2860 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2861 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2862 2863 typedef enum ARMMMUIdx { 2864 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2865 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2866 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2867 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2868 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2869 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2870 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2871 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2872 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2873 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2874 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2875 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2876 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2877 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2878 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2879 /* Indexes below here don't have TLBs and are used only for AT system 2880 * instructions or for the first stage of an S12 page table walk. 2881 */ 2882 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2883 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2884 } ARMMMUIdx; 2885 2886 /* Bit macros for the core-mmu-index values for each index, 2887 * for use when calling tlb_flush_by_mmuidx() and friends. 2888 */ 2889 typedef enum ARMMMUIdxBit { 2890 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2891 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2892 ARMMMUIdxBit_S1E2 = 1 << 2, 2893 ARMMMUIdxBit_S1E3 = 1 << 3, 2894 ARMMMUIdxBit_S1SE0 = 1 << 4, 2895 ARMMMUIdxBit_S1SE1 = 1 << 5, 2896 ARMMMUIdxBit_S2NS = 1 << 6, 2897 ARMMMUIdxBit_MUser = 1 << 0, 2898 ARMMMUIdxBit_MPriv = 1 << 1, 2899 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2900 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2901 ARMMMUIdxBit_MSUser = 1 << 4, 2902 ARMMMUIdxBit_MSPriv = 1 << 5, 2903 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2904 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2905 } ARMMMUIdxBit; 2906 2907 #define MMU_USER_IDX 0 2908 2909 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2910 { 2911 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2912 } 2913 2914 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2915 { 2916 if (arm_feature(env, ARM_FEATURE_M)) { 2917 return mmu_idx | ARM_MMU_IDX_M; 2918 } else { 2919 return mmu_idx | ARM_MMU_IDX_A; 2920 } 2921 } 2922 2923 /* Return the exception level we're running at if this is our mmu_idx */ 2924 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2925 { 2926 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2927 case ARM_MMU_IDX_A: 2928 return mmu_idx & 3; 2929 case ARM_MMU_IDX_M: 2930 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2931 default: 2932 g_assert_not_reached(); 2933 } 2934 } 2935 2936 /* 2937 * Return the MMU index for a v7M CPU with all relevant information 2938 * manually specified. 2939 */ 2940 ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, 2941 bool secstate, bool priv, bool negpri); 2942 2943 /* Return the MMU index for a v7M CPU in the specified security and 2944 * privilege state. 2945 */ 2946 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2947 bool secstate, bool priv); 2948 2949 /* Return the MMU index for a v7M CPU in the specified security state */ 2950 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); 2951 2952 /** 2953 * cpu_mmu_index: 2954 * @env: The cpu environment 2955 * @ifetch: True for code access, false for data access. 2956 * 2957 * Return the core mmu index for the current translation regime. 2958 * This function is used by generic TCG code paths. 2959 */ 2960 int cpu_mmu_index(CPUARMState *env, bool ifetch); 2961 2962 /* Indexes used when registering address spaces with cpu_address_space_init */ 2963 typedef enum ARMASIdx { 2964 ARMASIdx_NS = 0, 2965 ARMASIdx_S = 1, 2966 } ARMASIdx; 2967 2968 /* Return the Exception Level targeted by debug exceptions. */ 2969 static inline int arm_debug_target_el(CPUARMState *env) 2970 { 2971 bool secure = arm_is_secure(env); 2972 bool route_to_el2 = false; 2973 2974 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2975 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2976 env->cp15.mdcr_el2 & MDCR_TDE; 2977 } 2978 2979 if (route_to_el2) { 2980 return 2; 2981 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2982 !arm_el_is_aa64(env, 3) && secure) { 2983 return 3; 2984 } else { 2985 return 1; 2986 } 2987 } 2988 2989 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2990 { 2991 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2992 * CSSELR is RAZ/WI. 2993 */ 2994 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2995 } 2996 2997 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 2998 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2999 { 3000 int cur_el = arm_current_el(env); 3001 int debug_el; 3002 3003 if (cur_el == 3) { 3004 return false; 3005 } 3006 3007 /* MDCR_EL3.SDD disables debug events from Secure state */ 3008 if (arm_is_secure_below_el3(env) 3009 && extract32(env->cp15.mdcr_el3, 16, 1)) { 3010 return false; 3011 } 3012 3013 /* 3014 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 3015 * while not masking the (D)ebug bit in DAIF. 3016 */ 3017 debug_el = arm_debug_target_el(env); 3018 3019 if (cur_el == debug_el) { 3020 return extract32(env->cp15.mdscr_el1, 13, 1) 3021 && !(env->daif & PSTATE_D); 3022 } 3023 3024 /* Otherwise the debug target needs to be a higher EL */ 3025 return debug_el > cur_el; 3026 } 3027 3028 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 3029 { 3030 int el = arm_current_el(env); 3031 3032 if (el == 0 && arm_el_is_aa64(env, 1)) { 3033 return aa64_generate_debug_exceptions(env); 3034 } 3035 3036 if (arm_is_secure(env)) { 3037 int spd; 3038 3039 if (el == 0 && (env->cp15.sder & 1)) { 3040 /* SDER.SUIDEN means debug exceptions from Secure EL0 3041 * are always enabled. Otherwise they are controlled by 3042 * SDCR.SPD like those from other Secure ELs. 3043 */ 3044 return true; 3045 } 3046 3047 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3048 switch (spd) { 3049 case 1: 3050 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3051 case 0: 3052 /* For 0b00 we return true if external secure invasive debug 3053 * is enabled. On real hardware this is controlled by external 3054 * signals to the core. QEMU always permits debug, and behaves 3055 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3056 */ 3057 return true; 3058 case 2: 3059 return false; 3060 case 3: 3061 return true; 3062 } 3063 } 3064 3065 return el != 2; 3066 } 3067 3068 /* Return true if debugging exceptions are currently enabled. 3069 * This corresponds to what in ARM ARM pseudocode would be 3070 * if UsingAArch32() then 3071 * return AArch32.GenerateDebugExceptions() 3072 * else 3073 * return AArch64.GenerateDebugExceptions() 3074 * We choose to push the if() down into this function for clarity, 3075 * since the pseudocode has it at all callsites except for the one in 3076 * CheckSoftwareStep(), where it is elided because both branches would 3077 * always return the same value. 3078 */ 3079 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3080 { 3081 if (env->aarch64) { 3082 return aa64_generate_debug_exceptions(env); 3083 } else { 3084 return aa32_generate_debug_exceptions(env); 3085 } 3086 } 3087 3088 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3089 * implicitly means this always returns false in pre-v8 CPUs.) 3090 */ 3091 static inline bool arm_singlestep_active(CPUARMState *env) 3092 { 3093 return extract32(env->cp15.mdscr_el1, 0, 1) 3094 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3095 && arm_generate_debug_exceptions(env); 3096 } 3097 3098 static inline bool arm_sctlr_b(CPUARMState *env) 3099 { 3100 return 3101 /* We need not implement SCTLR.ITD in user-mode emulation, so 3102 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3103 * This lets people run BE32 binaries with "-cpu any". 3104 */ 3105 #ifndef CONFIG_USER_ONLY 3106 !arm_feature(env, ARM_FEATURE_V7) && 3107 #endif 3108 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3109 } 3110 3111 static inline uint64_t arm_sctlr(CPUARMState *env, int el) 3112 { 3113 if (el == 0) { 3114 /* FIXME: ARMv8.1-VHE S2 translation regime. */ 3115 return env->cp15.sctlr_el[1]; 3116 } else { 3117 return env->cp15.sctlr_el[el]; 3118 } 3119 } 3120 3121 3122 /* Return true if the processor is in big-endian mode. */ 3123 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3124 { 3125 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3126 if (!is_a64(env)) { 3127 return 3128 #ifdef CONFIG_USER_ONLY 3129 /* In system mode, BE32 is modelled in line with the 3130 * architecture (as word-invariant big-endianness), where loads 3131 * and stores are done little endian but from addresses which 3132 * are adjusted by XORing with the appropriate constant. So the 3133 * endianness to use for the raw data access is not affected by 3134 * SCTLR.B. 3135 * In user mode, however, we model BE32 as byte-invariant 3136 * big-endianness (because user-only code cannot tell the 3137 * difference), and so we need to use a data access endianness 3138 * that depends on SCTLR.B. 3139 */ 3140 arm_sctlr_b(env) || 3141 #endif 3142 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 3143 } else { 3144 int cur_el = arm_current_el(env); 3145 uint64_t sctlr = arm_sctlr(env, cur_el); 3146 3147 return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; 3148 } 3149 } 3150 3151 #include "exec/cpu-all.h" 3152 3153 /* Bit usage in the TB flags field: bit 31 indicates whether we are 3154 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 3155 * We put flags which are shared between 32 and 64 bit mode at the top 3156 * of the word, and flags which apply to only one mode at the bottom. 3157 */ 3158 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3159 FIELD(TBFLAG_ANY, MMUIDX, 28, 3) 3160 FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) 3161 FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) 3162 /* Target EL if we take a floating-point-disabled exception */ 3163 FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) 3164 FIELD(TBFLAG_ANY, BE_DATA, 23, 1) 3165 3166 /* Bit usage when in AArch32 state: */ 3167 FIELD(TBFLAG_A32, THUMB, 0, 1) 3168 FIELD(TBFLAG_A32, VECLEN, 1, 3) 3169 FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) 3170 /* 3171 * We store the bottom two bits of the CPAR as TB flags and handle 3172 * checks on the other bits at runtime. This shares the same bits as 3173 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3174 */ 3175 FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) 3176 /* 3177 * Indicates whether cp register reads and writes by guest code should access 3178 * the secure or nonsecure bank of banked registers; note that this is not 3179 * the same thing as the current security state of the processor! 3180 */ 3181 FIELD(TBFLAG_A32, NS, 6, 1) 3182 FIELD(TBFLAG_A32, VFPEN, 7, 1) 3183 FIELD(TBFLAG_A32, CONDEXEC, 8, 8) 3184 FIELD(TBFLAG_A32, SCTLR_B, 16, 1) 3185 /* For M profile only, set if FPCCR.LSPACT is set */ 3186 FIELD(TBFLAG_A32, LSPACT, 18, 1) 3187 /* For M profile only, set if we must create a new FP context */ 3188 FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) 3189 /* For M profile only, set if FPCCR.S does not match current security state */ 3190 FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) 3191 /* For M profile only, Handler (ie not Thread) mode */ 3192 FIELD(TBFLAG_A32, HANDLER, 21, 1) 3193 /* For M profile only, whether we should generate stack-limit checks */ 3194 FIELD(TBFLAG_A32, STACKCHECK, 22, 1) 3195 3196 /* Bit usage when in AArch64 state */ 3197 FIELD(TBFLAG_A64, TBII, 0, 2) 3198 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3199 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3200 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3201 FIELD(TBFLAG_A64, BT, 9, 1) 3202 FIELD(TBFLAG_A64, BTYPE, 10, 2) 3203 FIELD(TBFLAG_A64, TBID, 12, 2) 3204 3205 static inline bool bswap_code(bool sctlr_b) 3206 { 3207 #ifdef CONFIG_USER_ONLY 3208 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3209 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3210 * would also end up as a mixed-endian mode with BE code, LE data. 3211 */ 3212 return 3213 #ifdef TARGET_WORDS_BIGENDIAN 3214 1 ^ 3215 #endif 3216 sctlr_b; 3217 #else 3218 /* All code access in ARM is little endian, and there are no loaders 3219 * doing swaps that need to be reversed 3220 */ 3221 return 0; 3222 #endif 3223 } 3224 3225 #ifdef CONFIG_USER_ONLY 3226 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3227 { 3228 return 3229 #ifdef TARGET_WORDS_BIGENDIAN 3230 1 ^ 3231 #endif 3232 arm_cpu_data_is_big_endian(env); 3233 } 3234 #endif 3235 3236 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3237 target_ulong *cs_base, uint32_t *flags); 3238 3239 enum { 3240 QEMU_PSCI_CONDUIT_DISABLED = 0, 3241 QEMU_PSCI_CONDUIT_SMC = 1, 3242 QEMU_PSCI_CONDUIT_HVC = 2, 3243 }; 3244 3245 #ifndef CONFIG_USER_ONLY 3246 /* Return the address space index to use for a memory access */ 3247 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3248 { 3249 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3250 } 3251 3252 /* Return the AddressSpace to use for a memory access 3253 * (which depends on whether the access is S or NS, and whether 3254 * the board gave us a separate AddressSpace for S accesses). 3255 */ 3256 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3257 { 3258 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3259 } 3260 #endif 3261 3262 /** 3263 * arm_register_pre_el_change_hook: 3264 * Register a hook function which will be called immediately before this 3265 * CPU changes exception level or mode. The hook function will be 3266 * passed a pointer to the ARMCPU and the opaque data pointer passed 3267 * to this function when the hook was registered. 3268 * 3269 * Note that if a pre-change hook is called, any registered post-change hooks 3270 * are guaranteed to subsequently be called. 3271 */ 3272 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3273 void *opaque); 3274 /** 3275 * arm_register_el_change_hook: 3276 * Register a hook function which will be called immediately after this 3277 * CPU changes exception level or mode. The hook function will be 3278 * passed a pointer to the ARMCPU and the opaque data pointer passed 3279 * to this function when the hook was registered. 3280 * 3281 * Note that any registered hooks registered here are guaranteed to be called 3282 * if pre-change hooks have been. 3283 */ 3284 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3285 *opaque); 3286 3287 /** 3288 * aa32_vfp_dreg: 3289 * Return a pointer to the Dn register within env in 32-bit mode. 3290 */ 3291 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3292 { 3293 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3294 } 3295 3296 /** 3297 * aa32_vfp_qreg: 3298 * Return a pointer to the Qn register within env in 32-bit mode. 3299 */ 3300 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3301 { 3302 return &env->vfp.zregs[regno].d[0]; 3303 } 3304 3305 /** 3306 * aa64_vfp_qreg: 3307 * Return a pointer to the Qn register within env in 64-bit mode. 3308 */ 3309 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3310 { 3311 return &env->vfp.zregs[regno].d[0]; 3312 } 3313 3314 /* Shared between translate-sve.c and sve_helper.c. */ 3315 extern const uint64_t pred_esz_masks[4]; 3316 3317 /* 3318 * 32-bit feature tests via id registers. 3319 */ 3320 static inline bool isar_feature_thumb_div(const ARMISARegisters *id) 3321 { 3322 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3323 } 3324 3325 static inline bool isar_feature_arm_div(const ARMISARegisters *id) 3326 { 3327 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3328 } 3329 3330 static inline bool isar_feature_jazelle(const ARMISARegisters *id) 3331 { 3332 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3333 } 3334 3335 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3336 { 3337 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3338 } 3339 3340 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3341 { 3342 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3343 } 3344 3345 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3346 { 3347 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3348 } 3349 3350 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3351 { 3352 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3353 } 3354 3355 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3356 { 3357 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3358 } 3359 3360 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3361 { 3362 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3363 } 3364 3365 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3366 { 3367 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3368 } 3369 3370 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3371 { 3372 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3373 } 3374 3375 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3376 { 3377 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3378 } 3379 3380 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3381 { 3382 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3383 } 3384 3385 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3386 { 3387 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3388 } 3389 3390 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3391 { 3392 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3393 } 3394 3395 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3396 { 3397 /* 3398 * This is a placeholder for use by VCMA until the rest of 3399 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3400 * At which point we can properly set and check MVFR1.FPHP. 3401 */ 3402 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3403 } 3404 3405 /* 3406 * We always set the FP and SIMD FP16 fields to indicate identical 3407 * levels of support (assuming SIMD is implemented at all), so 3408 * we only need one set of accessors. 3409 */ 3410 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3411 { 3412 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0; 3413 } 3414 3415 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3416 { 3417 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; 3418 } 3419 3420 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3421 { 3422 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1; 3423 } 3424 3425 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3426 { 3427 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2; 3428 } 3429 3430 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3431 { 3432 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3; 3433 } 3434 3435 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3436 { 3437 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; 3438 } 3439 3440 /* 3441 * 64-bit feature tests via id registers. 3442 */ 3443 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3444 { 3445 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3446 } 3447 3448 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3449 { 3450 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3451 } 3452 3453 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3454 { 3455 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3456 } 3457 3458 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3459 { 3460 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3461 } 3462 3463 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3464 { 3465 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3466 } 3467 3468 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3469 { 3470 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3471 } 3472 3473 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3474 { 3475 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3476 } 3477 3478 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3479 { 3480 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3481 } 3482 3483 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3484 { 3485 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3486 } 3487 3488 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3489 { 3490 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3491 } 3492 3493 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3494 { 3495 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3496 } 3497 3498 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3499 { 3500 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3501 } 3502 3503 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3504 { 3505 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3506 } 3507 3508 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3509 { 3510 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3511 } 3512 3513 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3514 { 3515 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3516 } 3517 3518 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3519 { 3520 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3521 } 3522 3523 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3524 { 3525 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3526 } 3527 3528 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3529 { 3530 /* 3531 * Note that while QEMU will only implement the architected algorithm 3532 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation 3533 * defined algorithms, and thus API+GPI, and this predicate controls 3534 * migration of the 128-bit keys. 3535 */ 3536 return (id->id_aa64isar1 & 3537 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3538 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3539 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3540 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3541 } 3542 3543 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3544 { 3545 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3546 } 3547 3548 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3549 { 3550 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3551 } 3552 3553 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3554 { 3555 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3556 } 3557 3558 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3559 { 3560 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3561 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3562 } 3563 3564 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3565 { 3566 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3567 } 3568 3569 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3570 { 3571 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3572 } 3573 3574 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3575 { 3576 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3577 } 3578 3579 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3580 { 3581 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3582 } 3583 3584 /* 3585 * Forward to the above feature tests given an ARMCPU pointer. 3586 */ 3587 #define cpu_isar_feature(name, cpu) \ 3588 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3589 3590 #endif 3591