1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 61 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 62 63 #define ARMV7M_EXCP_RESET 1 64 #define ARMV7M_EXCP_NMI 2 65 #define ARMV7M_EXCP_HARD 3 66 #define ARMV7M_EXCP_MEM 4 67 #define ARMV7M_EXCP_BUS 5 68 #define ARMV7M_EXCP_USAGE 6 69 #define ARMV7M_EXCP_SECURE 7 70 #define ARMV7M_EXCP_SVC 11 71 #define ARMV7M_EXCP_DEBUG 12 72 #define ARMV7M_EXCP_PENDSV 14 73 #define ARMV7M_EXCP_SYSTICK 15 74 75 /* For M profile, some registers are banked secure vs non-secure; 76 * these are represented as a 2-element array where the first element 77 * is the non-secure copy and the second is the secure copy. 78 * When the CPU does not have implement the security extension then 79 * only the first element is used. 80 * This means that the copy for the current security state can be 81 * accessed via env->registerfield[env->v7m.secure] (whether the security 82 * extension is implemented or not). 83 */ 84 enum { 85 M_REG_NS = 0, 86 M_REG_S = 1, 87 M_REG_NUM_BANKS = 2, 88 }; 89 90 /* ARM-specific interrupt pending bits. */ 91 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 92 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 93 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 94 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 95 96 /* The usual mapping for an AArch64 system register to its AArch32 97 * counterpart is for the 32 bit world to have access to the lower 98 * half only (with writes leaving the upper half untouched). It's 99 * therefore useful to be able to pass TCG the offset of the least 100 * significant half of a uint64_t struct member. 101 */ 102 #if HOST_BIG_ENDIAN 103 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 104 #define offsetofhigh32(S, M) offsetof(S, M) 105 #else 106 #define offsetoflow32(S, M) offsetof(S, M) 107 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 108 #endif 109 110 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 111 #define ARM_CPU_IRQ 0 112 #define ARM_CPU_FIQ 1 113 #define ARM_CPU_VIRQ 2 114 #define ARM_CPU_VFIQ 3 115 116 /* ARM-specific extra insn start words: 117 * 1: Conditional execution bits 118 * 2: Partial exception syndrome for data aborts 119 */ 120 #define TARGET_INSN_START_EXTRA_WORDS 2 121 122 /* The 2nd extra word holding syndrome info for data aborts does not use 123 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 124 * help the sleb128 encoder do a better job. 125 * When restoring the CPU state, we shift it back up. 126 */ 127 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 128 #define ARM_INSN_START_WORD2_SHIFT 14 129 130 /* We currently assume float and double are IEEE single and double 131 precision respectively. 132 Doing runtime conversions is tricky because VFP registers may contain 133 integer values (eg. as the result of a FTOSI instruction). 134 s<2n> maps to the least significant half of d<n> 135 s<2n+1> maps to the most significant half of d<n> 136 */ 137 138 /** 139 * DynamicGDBXMLInfo: 140 * @desc: Contains the XML descriptions. 141 * @num: Number of the registers in this XML seen by GDB. 142 * @data: A union with data specific to the set of registers 143 * @cpregs_keys: Array that contains the corresponding Key of 144 * a given cpreg with the same order of the cpreg 145 * in the XML description. 146 */ 147 typedef struct DynamicGDBXMLInfo { 148 char *desc; 149 int num; 150 union { 151 struct { 152 uint32_t *keys; 153 } cpregs; 154 } data; 155 } DynamicGDBXMLInfo; 156 157 /* CPU state for each instance of a generic timer (in cp15 c14) */ 158 typedef struct ARMGenericTimer { 159 uint64_t cval; /* Timer CompareValue register */ 160 uint64_t ctl; /* Timer Control register */ 161 } ARMGenericTimer; 162 163 #define GTIMER_PHYS 0 164 #define GTIMER_VIRT 1 165 #define GTIMER_HYP 2 166 #define GTIMER_SEC 3 167 #define GTIMER_HYPVIRT 4 168 #define NUM_GTIMERS 5 169 170 #define VTCR_NSW (1u << 29) 171 #define VTCR_NSA (1u << 30) 172 #define VSTCR_SW VTCR_NSW 173 #define VSTCR_SA VTCR_NSA 174 175 /* Define a maximum sized vector register. 176 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 177 * For 64-bit, this is a 2048-bit SVE register. 178 * 179 * Note that the mapping between S, D, and Q views of the register bank 180 * differs between AArch64 and AArch32. 181 * In AArch32: 182 * Qn = regs[n].d[1]:regs[n].d[0] 183 * Dn = regs[n / 2].d[n & 1] 184 * Sn = regs[n / 4].d[n % 4 / 2], 185 * bits 31..0 for even n, and bits 63..32 for odd n 186 * (and regs[16] to regs[31] are inaccessible) 187 * In AArch64: 188 * Zn = regs[n].d[*] 189 * Qn = regs[n].d[1]:regs[n].d[0] 190 * Dn = regs[n].d[0] 191 * Sn = regs[n].d[0] bits 31..0 192 * Hn = regs[n].d[0] bits 15..0 193 * 194 * This corresponds to the architecturally defined mapping between 195 * the two execution states, and means we do not need to explicitly 196 * map these registers when changing states. 197 * 198 * Align the data for use with TCG host vector operations. 199 */ 200 201 #ifdef TARGET_AARCH64 202 # define ARM_MAX_VQ 16 203 #else 204 # define ARM_MAX_VQ 1 205 #endif 206 207 typedef struct ARMVectorReg { 208 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 209 } ARMVectorReg; 210 211 #ifdef TARGET_AARCH64 212 /* In AArch32 mode, predicate registers do not exist at all. */ 213 typedef struct ARMPredicateReg { 214 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 215 } ARMPredicateReg; 216 217 /* In AArch32 mode, PAC keys do not exist at all. */ 218 typedef struct ARMPACKey { 219 uint64_t lo, hi; 220 } ARMPACKey; 221 #endif 222 223 /* See the commentary above the TBFLAG field definitions. */ 224 typedef struct CPUARMTBFlags { 225 uint32_t flags; 226 target_ulong flags2; 227 } CPUARMTBFlags; 228 229 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 230 231 typedef struct NVICState NVICState; 232 233 typedef struct CPUArchState { 234 /* Regs for current mode. */ 235 uint32_t regs[16]; 236 237 /* 32/64 switch only happens when taking and returning from 238 * exceptions so the overlap semantics are taken care of then 239 * instead of having a complicated union. 240 */ 241 /* Regs for A64 mode. */ 242 uint64_t xregs[32]; 243 uint64_t pc; 244 /* PSTATE isn't an architectural register for ARMv8. However, it is 245 * convenient for us to assemble the underlying state into a 32 bit format 246 * identical to the architectural format used for the SPSR. (This is also 247 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 248 * 'pstate' register are.) Of the PSTATE bits: 249 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 250 * semantics as for AArch32, as described in the comments on each field) 251 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 252 * DAIF (exception masks) are kept in env->daif 253 * BTYPE is kept in env->btype 254 * SM and ZA are kept in env->svcr 255 * all other bits are stored in their correct places in env->pstate 256 */ 257 uint32_t pstate; 258 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 259 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 260 261 /* Cached TBFLAGS state. See below for which bits are included. */ 262 CPUARMTBFlags hflags; 263 264 /* Frequently accessed CPSR bits are stored separately for efficiency. 265 This contains all the other bits. Use cpsr_{read,write} to access 266 the whole CPSR. */ 267 uint32_t uncached_cpsr; 268 uint32_t spsr; 269 270 /* Banked registers. */ 271 uint64_t banked_spsr[8]; 272 uint32_t banked_r13[8]; 273 uint32_t banked_r14[8]; 274 275 /* These hold r8-r12. */ 276 uint32_t usr_regs[5]; 277 uint32_t fiq_regs[5]; 278 279 /* cpsr flag cache for faster execution */ 280 uint32_t CF; /* 0 or 1 */ 281 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 282 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 283 uint32_t ZF; /* Z set if zero. */ 284 uint32_t QF; /* 0 or 1 */ 285 uint32_t GE; /* cpsr[19:16] */ 286 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 287 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 288 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 289 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 290 291 uint64_t elr_el[4]; /* AArch64 exception link regs */ 292 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 293 294 /* System control coprocessor (cp15) */ 295 struct { 296 uint32_t c0_cpuid; 297 union { /* Cache size selection */ 298 struct { 299 uint64_t _unused_csselr0; 300 uint64_t csselr_ns; 301 uint64_t _unused_csselr1; 302 uint64_t csselr_s; 303 }; 304 uint64_t csselr_el[4]; 305 }; 306 union { /* System control register. */ 307 struct { 308 uint64_t _unused_sctlr; 309 uint64_t sctlr_ns; 310 uint64_t hsctlr; 311 uint64_t sctlr_s; 312 }; 313 uint64_t sctlr_el[4]; 314 }; 315 uint64_t vsctlr; /* Virtualization System control register. */ 316 uint64_t cpacr_el1; /* Architectural feature access control register */ 317 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 318 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 319 uint64_t sder; /* Secure debug enable register. */ 320 uint32_t nsacr; /* Non-secure access control register. */ 321 union { /* MMU translation table base 0. */ 322 struct { 323 uint64_t _unused_ttbr0_0; 324 uint64_t ttbr0_ns; 325 uint64_t _unused_ttbr0_1; 326 uint64_t ttbr0_s; 327 }; 328 uint64_t ttbr0_el[4]; 329 }; 330 union { /* MMU translation table base 1. */ 331 struct { 332 uint64_t _unused_ttbr1_0; 333 uint64_t ttbr1_ns; 334 uint64_t _unused_ttbr1_1; 335 uint64_t ttbr1_s; 336 }; 337 uint64_t ttbr1_el[4]; 338 }; 339 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 340 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 341 /* MMU translation table base control. */ 342 uint64_t tcr_el[4]; 343 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 344 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 345 uint32_t c2_data; /* MPU data cacheable bits. */ 346 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 347 union { /* MMU domain access control register 348 * MPU write buffer control. 349 */ 350 struct { 351 uint64_t dacr_ns; 352 uint64_t dacr_s; 353 }; 354 struct { 355 uint64_t dacr32_el2; 356 }; 357 }; 358 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 359 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 360 uint64_t hcr_el2; /* Hypervisor configuration register */ 361 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 362 uint64_t scr_el3; /* Secure configuration register. */ 363 union { /* Fault status registers. */ 364 struct { 365 uint64_t ifsr_ns; 366 uint64_t ifsr_s; 367 }; 368 struct { 369 uint64_t ifsr32_el2; 370 }; 371 }; 372 union { 373 struct { 374 uint64_t _unused_dfsr; 375 uint64_t dfsr_ns; 376 uint64_t hsr; 377 uint64_t dfsr_s; 378 }; 379 uint64_t esr_el[4]; 380 }; 381 uint32_t c6_region[8]; /* MPU base/size registers. */ 382 union { /* Fault address registers. */ 383 struct { 384 uint64_t _unused_far0; 385 #if HOST_BIG_ENDIAN 386 uint32_t ifar_ns; 387 uint32_t dfar_ns; 388 uint32_t ifar_s; 389 uint32_t dfar_s; 390 #else 391 uint32_t dfar_ns; 392 uint32_t ifar_ns; 393 uint32_t dfar_s; 394 uint32_t ifar_s; 395 #endif 396 uint64_t _unused_far3; 397 }; 398 uint64_t far_el[4]; 399 }; 400 uint64_t hpfar_el2; 401 uint64_t hstr_el2; 402 union { /* Translation result. */ 403 struct { 404 uint64_t _unused_par_0; 405 uint64_t par_ns; 406 uint64_t _unused_par_1; 407 uint64_t par_s; 408 }; 409 uint64_t par_el[4]; 410 }; 411 412 uint32_t c9_insn; /* Cache lockdown registers. */ 413 uint32_t c9_data; 414 uint64_t c9_pmcr; /* performance monitor control register */ 415 uint64_t c9_pmcnten; /* perf monitor counter enables */ 416 uint64_t c9_pmovsr; /* perf monitor overflow status */ 417 uint64_t c9_pmuserenr; /* perf monitor user enable */ 418 uint64_t c9_pmselr; /* perf monitor counter selection register */ 419 uint64_t c9_pminten; /* perf monitor interrupt enables */ 420 union { /* Memory attribute redirection */ 421 struct { 422 #if HOST_BIG_ENDIAN 423 uint64_t _unused_mair_0; 424 uint32_t mair1_ns; 425 uint32_t mair0_ns; 426 uint64_t _unused_mair_1; 427 uint32_t mair1_s; 428 uint32_t mair0_s; 429 #else 430 uint64_t _unused_mair_0; 431 uint32_t mair0_ns; 432 uint32_t mair1_ns; 433 uint64_t _unused_mair_1; 434 uint32_t mair0_s; 435 uint32_t mair1_s; 436 #endif 437 }; 438 uint64_t mair_el[4]; 439 }; 440 union { /* vector base address register */ 441 struct { 442 uint64_t _unused_vbar; 443 uint64_t vbar_ns; 444 uint64_t hvbar; 445 uint64_t vbar_s; 446 }; 447 uint64_t vbar_el[4]; 448 }; 449 uint32_t mvbar; /* (monitor) vector base address register */ 450 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 451 struct { /* FCSE PID. */ 452 uint32_t fcseidr_ns; 453 uint32_t fcseidr_s; 454 }; 455 union { /* Context ID. */ 456 struct { 457 uint64_t _unused_contextidr_0; 458 uint64_t contextidr_ns; 459 uint64_t _unused_contextidr_1; 460 uint64_t contextidr_s; 461 }; 462 uint64_t contextidr_el[4]; 463 }; 464 union { /* User RW Thread register. */ 465 struct { 466 uint64_t tpidrurw_ns; 467 uint64_t tpidrprw_ns; 468 uint64_t htpidr; 469 uint64_t _tpidr_el3; 470 }; 471 uint64_t tpidr_el[4]; 472 }; 473 uint64_t tpidr2_el0; 474 /* The secure banks of these registers don't map anywhere */ 475 uint64_t tpidrurw_s; 476 uint64_t tpidrprw_s; 477 uint64_t tpidruro_s; 478 479 union { /* User RO Thread register. */ 480 uint64_t tpidruro_ns; 481 uint64_t tpidrro_el[1]; 482 }; 483 uint64_t c14_cntfrq; /* Counter Frequency register */ 484 uint64_t c14_cntkctl; /* Timer Control register */ 485 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 486 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 487 ARMGenericTimer c14_timer[NUM_GTIMERS]; 488 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 489 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 490 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 491 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 492 uint32_t c15_threadid; /* TI debugger thread-ID. */ 493 uint32_t c15_config_base_address; /* SCU base address. */ 494 uint32_t c15_diagnostic; /* diagnostic register */ 495 uint32_t c15_power_diagnostic; 496 uint32_t c15_power_control; /* power control */ 497 uint64_t dbgbvr[16]; /* breakpoint value registers */ 498 uint64_t dbgbcr[16]; /* breakpoint control registers */ 499 uint64_t dbgwvr[16]; /* watchpoint value registers */ 500 uint64_t dbgwcr[16]; /* watchpoint control registers */ 501 uint64_t dbgclaim; /* DBGCLAIM bits */ 502 uint64_t mdscr_el1; 503 uint64_t oslsr_el1; /* OS Lock Status */ 504 uint64_t osdlr_el1; /* OS DoubleLock status */ 505 uint64_t mdcr_el2; 506 uint64_t mdcr_el3; 507 /* Stores the architectural value of the counter *the last time it was 508 * updated* by pmccntr_op_start. Accesses should always be surrounded 509 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 510 * architecturally-correct value is being read/set. 511 */ 512 uint64_t c15_ccnt; 513 /* Stores the delta between the architectural value and the underlying 514 * cycle count during normal operation. It is used to update c15_ccnt 515 * to be the correct architectural value before accesses. During 516 * accesses, c15_ccnt_delta contains the underlying count being used 517 * for the access, after which it reverts to the delta value in 518 * pmccntr_op_finish. 519 */ 520 uint64_t c15_ccnt_delta; 521 uint64_t c14_pmevcntr[31]; 522 uint64_t c14_pmevcntr_delta[31]; 523 uint64_t c14_pmevtyper[31]; 524 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 525 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 526 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 527 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 528 uint64_t gcr_el1; 529 uint64_t rgsr_el1; 530 531 /* Minimal RAS registers */ 532 uint64_t disr_el1; 533 uint64_t vdisr_el2; 534 uint64_t vsesr_el2; 535 536 /* 537 * Fine-Grained Trap registers. We store these as arrays so the 538 * access checking code doesn't have to manually select 539 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 540 * FEAT_FGT2 will add more elements to these arrays. 541 */ 542 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 543 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 544 uint64_t fgt_exec[1]; /* HFGITR */ 545 546 /* RME registers */ 547 uint64_t gpccr_el3; 548 uint64_t gptbr_el3; 549 uint64_t mfar_el3; 550 } cp15; 551 552 struct { 553 /* M profile has up to 4 stack pointers: 554 * a Main Stack Pointer and a Process Stack Pointer for each 555 * of the Secure and Non-Secure states. (If the CPU doesn't support 556 * the security extension then it has only two SPs.) 557 * In QEMU we always store the currently active SP in regs[13], 558 * and the non-active SP for the current security state in 559 * v7m.other_sp. The stack pointers for the inactive security state 560 * are stored in other_ss_msp and other_ss_psp. 561 * switch_v7m_security_state() is responsible for rearranging them 562 * when we change security state. 563 */ 564 uint32_t other_sp; 565 uint32_t other_ss_msp; 566 uint32_t other_ss_psp; 567 uint32_t vecbase[M_REG_NUM_BANKS]; 568 uint32_t basepri[M_REG_NUM_BANKS]; 569 uint32_t control[M_REG_NUM_BANKS]; 570 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 571 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 572 uint32_t hfsr; /* HardFault Status */ 573 uint32_t dfsr; /* Debug Fault Status Register */ 574 uint32_t sfsr; /* Secure Fault Status Register */ 575 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 576 uint32_t bfar; /* BusFault Address */ 577 uint32_t sfar; /* Secure Fault Address Register */ 578 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 579 int exception; 580 uint32_t primask[M_REG_NUM_BANKS]; 581 uint32_t faultmask[M_REG_NUM_BANKS]; 582 uint32_t aircr; /* only holds r/w state if security extn implemented */ 583 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 584 uint32_t csselr[M_REG_NUM_BANKS]; 585 uint32_t scr[M_REG_NUM_BANKS]; 586 uint32_t msplim[M_REG_NUM_BANKS]; 587 uint32_t psplim[M_REG_NUM_BANKS]; 588 uint32_t fpcar[M_REG_NUM_BANKS]; 589 uint32_t fpccr[M_REG_NUM_BANKS]; 590 uint32_t fpdscr[M_REG_NUM_BANKS]; 591 uint32_t cpacr[M_REG_NUM_BANKS]; 592 uint32_t nsacr; 593 uint32_t ltpsize; 594 uint32_t vpr; 595 } v7m; 596 597 /* Information associated with an exception about to be taken: 598 * code which raises an exception must set cs->exception_index and 599 * the relevant parts of this structure; the cpu_do_interrupt function 600 * will then set the guest-visible registers as part of the exception 601 * entry process. 602 */ 603 struct { 604 uint32_t syndrome; /* AArch64 format syndrome register */ 605 uint32_t fsr; /* AArch32 format fault status register info */ 606 uint64_t vaddress; /* virtual addr associated with exception, if any */ 607 uint32_t target_el; /* EL the exception should be targeted for */ 608 /* If we implement EL2 we will also need to store information 609 * about the intermediate physical address for stage 2 faults. 610 */ 611 } exception; 612 613 /* Information associated with an SError */ 614 struct { 615 uint8_t pending; 616 uint8_t has_esr; 617 uint64_t esr; 618 } serror; 619 620 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 621 622 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 623 uint32_t irq_line_state; 624 625 /* Thumb-2 EE state. */ 626 uint32_t teecr; 627 uint32_t teehbr; 628 629 /* VFP coprocessor state. */ 630 struct { 631 ARMVectorReg zregs[32]; 632 633 #ifdef TARGET_AARCH64 634 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 635 #define FFR_PRED_NUM 16 636 ARMPredicateReg pregs[17]; 637 /* Scratch space for aa64 sve predicate temporary. */ 638 ARMPredicateReg preg_tmp; 639 #endif 640 641 /* We store these fpcsr fields separately for convenience. */ 642 uint32_t qc[4] QEMU_ALIGNED(16); 643 int vec_len; 644 int vec_stride; 645 646 uint32_t xregs[16]; 647 648 /* Scratch space for aa32 neon expansion. */ 649 uint32_t scratch[8]; 650 651 /* There are a number of distinct float control structures: 652 * 653 * fp_status: is the "normal" fp status. 654 * fp_status_fp16: used for half-precision calculations 655 * standard_fp_status : the ARM "Standard FPSCR Value" 656 * standard_fp_status_fp16 : used for half-precision 657 * calculations with the ARM "Standard FPSCR Value" 658 * 659 * Half-precision operations are governed by a separate 660 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 661 * status structure to control this. 662 * 663 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 664 * round-to-nearest and is used by any operations (generally 665 * Neon) which the architecture defines as controlled by the 666 * standard FPSCR value rather than the FPSCR. 667 * 668 * The "standard FPSCR but for fp16 ops" is needed because 669 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 670 * using a fixed value for it. 671 * 672 * To avoid having to transfer exception bits around, we simply 673 * say that the FPSCR cumulative exception flags are the logical 674 * OR of the flags in the four fp statuses. This relies on the 675 * only thing which needs to read the exception flags being 676 * an explicit FPSCR read. 677 */ 678 float_status fp_status; 679 float_status fp_status_f16; 680 float_status standard_fp_status; 681 float_status standard_fp_status_f16; 682 683 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 684 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 685 } vfp; 686 687 uint64_t exclusive_addr; 688 uint64_t exclusive_val; 689 /* 690 * Contains the 'val' for the second 64-bit register of LDXP, which comes 691 * from the higher address, not the high part of a complete 128-bit value. 692 * In some ways it might be more convenient to record the exclusive value 693 * as the low and high halves of a 128 bit data value, but the current 694 * semantics of these fields are baked into the migration format. 695 */ 696 uint64_t exclusive_high; 697 698 /* iwMMXt coprocessor state. */ 699 struct { 700 uint64_t regs[16]; 701 uint64_t val; 702 703 uint32_t cregs[16]; 704 } iwmmxt; 705 706 #ifdef TARGET_AARCH64 707 struct { 708 ARMPACKey apia; 709 ARMPACKey apib; 710 ARMPACKey apda; 711 ARMPACKey apdb; 712 ARMPACKey apga; 713 } keys; 714 715 uint64_t scxtnum_el[4]; 716 717 /* 718 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 719 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 720 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 721 * When SVL is less than the architectural maximum, the accessible 722 * storage is restricted, such that if the SVL is X bytes the guest can 723 * see only the bottom X elements of zarray[], and only the least 724 * significant X bytes of each element of the array. (In other words, 725 * the observable part is always square.) 726 * 727 * The ZA storage can also be considered as a set of square tiles of 728 * elements of different sizes. The mapping from tiles to the ZA array 729 * is architecturally defined, such that for tiles of elements of esz 730 * bytes, the Nth row (or "horizontal slice") of tile T is in 731 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 732 * in the ZA storage, because its rows are striped through the ZA array. 733 * 734 * Because this is so large, keep this toward the end of the reset area, 735 * to keep the offsets into the rest of the structure smaller. 736 */ 737 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 738 #endif 739 740 struct CPUBreakpoint *cpu_breakpoint[16]; 741 struct CPUWatchpoint *cpu_watchpoint[16]; 742 743 /* Optional fault info across tlb lookup. */ 744 ARMMMUFaultInfo *tlb_fi; 745 746 /* Fields up to this point are cleared by a CPU reset */ 747 struct {} end_reset_fields; 748 749 /* Fields after this point are preserved across CPU reset. */ 750 751 /* Internal CPU feature flags. */ 752 uint64_t features; 753 754 /* PMSAv7 MPU */ 755 struct { 756 uint32_t *drbar; 757 uint32_t *drsr; 758 uint32_t *dracr; 759 uint32_t rnr[M_REG_NUM_BANKS]; 760 } pmsav7; 761 762 /* PMSAv8 MPU */ 763 struct { 764 /* The PMSAv8 implementation also shares some PMSAv7 config 765 * and state: 766 * pmsav7.rnr (region number register) 767 * pmsav7_dregion (number of configured regions) 768 */ 769 uint32_t *rbar[M_REG_NUM_BANKS]; 770 uint32_t *rlar[M_REG_NUM_BANKS]; 771 uint32_t *hprbar; 772 uint32_t *hprlar; 773 uint32_t mair0[M_REG_NUM_BANKS]; 774 uint32_t mair1[M_REG_NUM_BANKS]; 775 uint32_t hprselr; 776 } pmsav8; 777 778 /* v8M SAU */ 779 struct { 780 uint32_t *rbar; 781 uint32_t *rlar; 782 uint32_t rnr; 783 uint32_t ctrl; 784 } sau; 785 786 #if !defined(CONFIG_USER_ONLY) 787 NVICState *nvic; 788 const struct arm_boot_info *boot_info; 789 /* Store GICv3CPUState to access from this struct */ 790 void *gicv3state; 791 #else /* CONFIG_USER_ONLY */ 792 /* For usermode syscall translation. */ 793 bool eabi; 794 #endif /* CONFIG_USER_ONLY */ 795 796 #ifdef TARGET_TAGGED_ADDRESSES 797 /* Linux syscall tagged address support */ 798 bool tagged_addr_enable; 799 #endif 800 } CPUARMState; 801 802 static inline void set_feature(CPUARMState *env, int feature) 803 { 804 env->features |= 1ULL << feature; 805 } 806 807 static inline void unset_feature(CPUARMState *env, int feature) 808 { 809 env->features &= ~(1ULL << feature); 810 } 811 812 /** 813 * ARMELChangeHookFn: 814 * type of a function which can be registered via arm_register_el_change_hook() 815 * to get callbacks when the CPU changes its exception level or mode. 816 */ 817 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 818 typedef struct ARMELChangeHook ARMELChangeHook; 819 struct ARMELChangeHook { 820 ARMELChangeHookFn *hook; 821 void *opaque; 822 QLIST_ENTRY(ARMELChangeHook) node; 823 }; 824 825 /* These values map onto the return values for 826 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 827 typedef enum ARMPSCIState { 828 PSCI_ON = 0, 829 PSCI_OFF = 1, 830 PSCI_ON_PENDING = 2 831 } ARMPSCIState; 832 833 typedef struct ARMISARegisters ARMISARegisters; 834 835 /* 836 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 837 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 838 * 839 * While processing properties during initialization, corresponding init bits 840 * are set for bits in sve_vq_map that have been set by properties. 841 * 842 * Bits set in supported represent valid vector lengths for the CPU type. 843 */ 844 typedef struct { 845 uint32_t map, init, supported; 846 } ARMVQMap; 847 848 /** 849 * ARMCPU: 850 * @env: #CPUARMState 851 * 852 * An ARM CPU core. 853 */ 854 struct ArchCPU { 855 /*< private >*/ 856 CPUState parent_obj; 857 /*< public >*/ 858 859 CPUARMState env; 860 861 /* Coprocessor information */ 862 GHashTable *cp_regs; 863 /* For marshalling (mostly coprocessor) register state between the 864 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 865 * we use these arrays. 866 */ 867 /* List of register indexes managed via these arrays; (full KVM style 868 * 64 bit indexes, not CPRegInfo 32 bit indexes) 869 */ 870 uint64_t *cpreg_indexes; 871 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 872 uint64_t *cpreg_values; 873 /* Length of the indexes, values, reset_values arrays */ 874 int32_t cpreg_array_len; 875 /* These are used only for migration: incoming data arrives in 876 * these fields and is sanity checked in post_load before copying 877 * to the working data structures above. 878 */ 879 uint64_t *cpreg_vmstate_indexes; 880 uint64_t *cpreg_vmstate_values; 881 int32_t cpreg_vmstate_array_len; 882 883 DynamicGDBXMLInfo dyn_sysreg_xml; 884 DynamicGDBXMLInfo dyn_svereg_xml; 885 DynamicGDBXMLInfo dyn_m_systemreg_xml; 886 DynamicGDBXMLInfo dyn_m_secextreg_xml; 887 888 /* Timers used by the generic (architected) timer */ 889 QEMUTimer *gt_timer[NUM_GTIMERS]; 890 /* 891 * Timer used by the PMU. Its state is restored after migration by 892 * pmu_op_finish() - it does not need other handling during migration 893 */ 894 QEMUTimer *pmu_timer; 895 /* GPIO outputs for generic timer */ 896 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 897 /* GPIO output for GICv3 maintenance interrupt signal */ 898 qemu_irq gicv3_maintenance_interrupt; 899 /* GPIO output for the PMU interrupt */ 900 qemu_irq pmu_interrupt; 901 902 /* MemoryRegion to use for secure physical accesses */ 903 MemoryRegion *secure_memory; 904 905 /* MemoryRegion to use for allocation tag accesses */ 906 MemoryRegion *tag_memory; 907 MemoryRegion *secure_tag_memory; 908 909 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 910 Object *idau; 911 912 /* 'compatible' string for this CPU for Linux device trees */ 913 const char *dtb_compatible; 914 915 /* PSCI version for this CPU 916 * Bits[31:16] = Major Version 917 * Bits[15:0] = Minor Version 918 */ 919 uint32_t psci_version; 920 921 /* Current power state, access guarded by BQL */ 922 ARMPSCIState power_state; 923 924 /* CPU has virtualization extension */ 925 bool has_el2; 926 /* CPU has security extension */ 927 bool has_el3; 928 /* CPU has PMU (Performance Monitor Unit) */ 929 bool has_pmu; 930 /* CPU has VFP */ 931 bool has_vfp; 932 /* CPU has 32 VFP registers */ 933 bool has_vfp_d32; 934 /* CPU has Neon */ 935 bool has_neon; 936 /* CPU has M-profile DSP extension */ 937 bool has_dsp; 938 939 /* CPU has memory protection unit */ 940 bool has_mpu; 941 /* PMSAv7 MPU number of supported regions */ 942 uint32_t pmsav7_dregion; 943 /* PMSAv8 MPU number of supported hyp regions */ 944 uint32_t pmsav8r_hdregion; 945 /* v8M SAU number of supported regions */ 946 uint32_t sau_sregion; 947 948 /* PSCI conduit used to invoke PSCI methods 949 * 0 - disabled, 1 - smc, 2 - hvc 950 */ 951 uint32_t psci_conduit; 952 953 /* For v8M, initial value of the Secure VTOR */ 954 uint32_t init_svtor; 955 /* For v8M, initial value of the Non-secure VTOR */ 956 uint32_t init_nsvtor; 957 958 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 959 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 960 */ 961 uint32_t kvm_target; 962 963 #ifdef CONFIG_KVM 964 /* KVM init features for this CPU */ 965 uint32_t kvm_init_features[7]; 966 967 /* KVM CPU state */ 968 969 /* KVM virtual time adjustment */ 970 bool kvm_adjvtime; 971 bool kvm_vtime_dirty; 972 uint64_t kvm_vtime; 973 974 /* KVM steal time */ 975 OnOffAuto kvm_steal_time; 976 #endif /* CONFIG_KVM */ 977 978 /* Uniprocessor system with MP extensions */ 979 bool mp_is_up; 980 981 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 982 * and the probe failed (so we need to report the error in realize) 983 */ 984 bool host_cpu_probe_failed; 985 986 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 987 * register. 988 */ 989 int32_t core_count; 990 991 /* The instance init functions for implementation-specific subclasses 992 * set these fields to specify the implementation-dependent values of 993 * various constant registers and reset values of non-constant 994 * registers. 995 * Some of these might become QOM properties eventually. 996 * Field names match the official register names as defined in the 997 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 998 * is used for reset values of non-constant registers; no reset_ 999 * prefix means a constant register. 1000 * Some of these registers are split out into a substructure that 1001 * is shared with the translators to control the ISA. 1002 * 1003 * Note that if you add an ID register to the ARMISARegisters struct 1004 * you need to also update the 32-bit and 64-bit versions of the 1005 * kvm_arm_get_host_cpu_features() function to correctly populate the 1006 * field by reading the value from the KVM vCPU. 1007 */ 1008 struct ARMISARegisters { 1009 uint32_t id_isar0; 1010 uint32_t id_isar1; 1011 uint32_t id_isar2; 1012 uint32_t id_isar3; 1013 uint32_t id_isar4; 1014 uint32_t id_isar5; 1015 uint32_t id_isar6; 1016 uint32_t id_mmfr0; 1017 uint32_t id_mmfr1; 1018 uint32_t id_mmfr2; 1019 uint32_t id_mmfr3; 1020 uint32_t id_mmfr4; 1021 uint32_t id_mmfr5; 1022 uint32_t id_pfr0; 1023 uint32_t id_pfr1; 1024 uint32_t id_pfr2; 1025 uint32_t mvfr0; 1026 uint32_t mvfr1; 1027 uint32_t mvfr2; 1028 uint32_t id_dfr0; 1029 uint32_t id_dfr1; 1030 uint32_t dbgdidr; 1031 uint32_t dbgdevid; 1032 uint32_t dbgdevid1; 1033 uint64_t id_aa64isar0; 1034 uint64_t id_aa64isar1; 1035 uint64_t id_aa64isar2; 1036 uint64_t id_aa64pfr0; 1037 uint64_t id_aa64pfr1; 1038 uint64_t id_aa64mmfr0; 1039 uint64_t id_aa64mmfr1; 1040 uint64_t id_aa64mmfr2; 1041 uint64_t id_aa64dfr0; 1042 uint64_t id_aa64dfr1; 1043 uint64_t id_aa64zfr0; 1044 uint64_t id_aa64smfr0; 1045 uint64_t reset_pmcr_el0; 1046 } isar; 1047 uint64_t midr; 1048 uint32_t revidr; 1049 uint32_t reset_fpsid; 1050 uint64_t ctr; 1051 uint32_t reset_sctlr; 1052 uint64_t pmceid0; 1053 uint64_t pmceid1; 1054 uint32_t id_afr0; 1055 uint64_t id_aa64afr0; 1056 uint64_t id_aa64afr1; 1057 uint64_t clidr; 1058 uint64_t mp_affinity; /* MP ID without feature bits */ 1059 /* The elements of this array are the CCSIDR values for each cache, 1060 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1061 */ 1062 uint64_t ccsidr[16]; 1063 uint64_t reset_cbar; 1064 uint32_t reset_auxcr; 1065 bool reset_hivecs; 1066 uint8_t reset_l0gptsz; 1067 1068 /* 1069 * Intermediate values used during property parsing. 1070 * Once finalized, the values should be read from ID_AA64*. 1071 */ 1072 bool prop_pauth; 1073 bool prop_pauth_impdef; 1074 bool prop_pauth_qarma3; 1075 bool prop_lpa2; 1076 1077 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1078 uint8_t dcz_blocksize; 1079 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1080 uint8_t gm_blocksize; 1081 1082 uint64_t rvbar_prop; /* Property/input signals. */ 1083 1084 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1085 int gic_num_lrs; /* number of list registers */ 1086 int gic_vpribits; /* number of virtual priority bits */ 1087 int gic_vprebits; /* number of virtual preemption bits */ 1088 int gic_pribits; /* number of physical priority bits */ 1089 1090 /* Whether the cfgend input is high (i.e. this CPU should reset into 1091 * big-endian mode). This setting isn't used directly: instead it modifies 1092 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1093 * architecture version. 1094 */ 1095 bool cfgend; 1096 1097 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1098 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1099 1100 int32_t node_id; /* NUMA node this CPU belongs to */ 1101 1102 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1103 uint8_t device_irq_level; 1104 1105 /* Used to set the maximum vector length the cpu will support. */ 1106 uint32_t sve_max_vq; 1107 1108 #ifdef CONFIG_USER_ONLY 1109 /* Used to set the default vector length at process start. */ 1110 uint32_t sve_default_vq; 1111 uint32_t sme_default_vq; 1112 #endif 1113 1114 ARMVQMap sve_vq; 1115 ARMVQMap sme_vq; 1116 1117 /* Generic timer counter frequency, in Hz */ 1118 uint64_t gt_cntfrq_hz; 1119 }; 1120 1121 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1122 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1123 1124 void arm_cpu_post_init(Object *obj); 1125 1126 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1127 1128 #ifndef CONFIG_USER_ONLY 1129 extern const VMStateDescription vmstate_arm_cpu; 1130 1131 void arm_cpu_do_interrupt(CPUState *cpu); 1132 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1133 1134 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1135 MemTxAttrs *attrs); 1136 #endif /* !CONFIG_USER_ONLY */ 1137 1138 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1139 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1140 1141 /* Returns the dynamically generated XML for the gdb stub. 1142 * Returns a pointer to the XML contents for the specified XML file or NULL 1143 * if the XML name doesn't match the predefined one. 1144 */ 1145 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1146 1147 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1148 int cpuid, DumpState *s); 1149 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1150 int cpuid, DumpState *s); 1151 1152 /** 1153 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1154 * @cpu: CPU (which must have been freshly reset) 1155 * @target_el: exception level to put the CPU into 1156 * @secure: whether to put the CPU in secure state 1157 * 1158 * When QEMU is directly running a guest kernel at a lower level than 1159 * EL3 it implicitly emulates some aspects of the guest firmware. 1160 * This includes that on reset we need to configure the parts of the 1161 * CPU corresponding to EL3 so that the real guest code can run at its 1162 * lower exception level. This function does that post-reset CPU setup, 1163 * for when we do direct boot of a guest kernel, and for when we 1164 * emulate PSCI and similar firmware interfaces starting a CPU at a 1165 * lower exception level. 1166 * 1167 * @target_el must be an EL implemented by the CPU between 1 and 3. 1168 * We do not support dropping into a Secure EL other than 3. 1169 * 1170 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1171 */ 1172 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1173 1174 #ifdef TARGET_AARCH64 1175 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1176 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1177 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1178 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1179 int new_el, bool el0_a64); 1180 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1181 1182 /* 1183 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1184 * The byte at offset i from the start of the in-memory representation contains 1185 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1186 * lowest offsets are stored in the lowest memory addresses, then that nearly 1187 * matches QEMU's representation, which is to use an array of host-endian 1188 * uint64_t's, where the lower offsets are at the lower indices. To complete 1189 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1190 */ 1191 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1192 { 1193 #if HOST_BIG_ENDIAN 1194 int i; 1195 1196 for (i = 0; i < nr; ++i) { 1197 dst[i] = bswap64(src[i]); 1198 } 1199 1200 return dst; 1201 #else 1202 return src; 1203 #endif 1204 } 1205 1206 #else 1207 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1208 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1209 int n, bool a) 1210 { } 1211 #endif 1212 1213 void aarch64_sync_32_to_64(CPUARMState *env); 1214 void aarch64_sync_64_to_32(CPUARMState *env); 1215 1216 int fp_exception_el(CPUARMState *env, int cur_el); 1217 int sve_exception_el(CPUARMState *env, int cur_el); 1218 int sme_exception_el(CPUARMState *env, int cur_el); 1219 1220 /** 1221 * sve_vqm1_for_el_sm: 1222 * @env: CPUARMState 1223 * @el: exception level 1224 * @sm: streaming mode 1225 * 1226 * Compute the current vector length for @el & @sm, in units of 1227 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1228 * If @sm, compute for SVL, otherwise NVL. 1229 */ 1230 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1231 1232 /* Likewise, but using @sm = PSTATE.SM. */ 1233 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1234 1235 static inline bool is_a64(CPUARMState *env) 1236 { 1237 return env->aarch64; 1238 } 1239 1240 /** 1241 * pmu_op_start/finish 1242 * @env: CPUARMState 1243 * 1244 * Convert all PMU counters between their delta form (the typical mode when 1245 * they are enabled) and the guest-visible values. These two calls must 1246 * surround any action which might affect the counters. 1247 */ 1248 void pmu_op_start(CPUARMState *env); 1249 void pmu_op_finish(CPUARMState *env); 1250 1251 /* 1252 * Called when a PMU counter is due to overflow 1253 */ 1254 void arm_pmu_timer_cb(void *opaque); 1255 1256 /** 1257 * Functions to register as EL change hooks for PMU mode filtering 1258 */ 1259 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1260 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1261 1262 /* 1263 * pmu_init 1264 * @cpu: ARMCPU 1265 * 1266 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1267 * for the current configuration 1268 */ 1269 void pmu_init(ARMCPU *cpu); 1270 1271 /* SCTLR bit meanings. Several bits have been reused in newer 1272 * versions of the architecture; in that case we define constants 1273 * for both old and new bit meanings. Code which tests against those 1274 * bits should probably check or otherwise arrange that the CPU 1275 * is the architectural version it expects. 1276 */ 1277 #define SCTLR_M (1U << 0) 1278 #define SCTLR_A (1U << 1) 1279 #define SCTLR_C (1U << 2) 1280 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1281 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1282 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1283 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1284 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1285 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1286 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1287 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1288 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1289 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1290 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1291 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1292 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1293 #define SCTLR_SED (1U << 8) /* v8 onward */ 1294 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1295 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1296 #define SCTLR_F (1U << 10) /* up to v6 */ 1297 #define SCTLR_SW (1U << 10) /* v7 */ 1298 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1299 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1300 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1301 #define SCTLR_I (1U << 12) 1302 #define SCTLR_V (1U << 13) /* AArch32 only */ 1303 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1304 #define SCTLR_RR (1U << 14) /* up to v7 */ 1305 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1306 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1307 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1308 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1309 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1310 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1311 #define SCTLR_BR (1U << 17) /* PMSA only */ 1312 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1313 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1314 #define SCTLR_WXN (1U << 19) 1315 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1316 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1317 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1318 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1319 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1320 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1321 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1322 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1323 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1324 #define SCTLR_VE (1U << 24) /* up to v7 */ 1325 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1326 #define SCTLR_EE (1U << 25) 1327 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1328 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1329 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1330 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1331 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1332 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1333 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1334 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1335 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1336 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1337 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1338 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1339 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1340 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1341 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1342 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1343 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1344 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1345 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1346 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1347 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1348 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1349 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1350 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1351 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1352 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1353 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1354 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1355 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1356 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1357 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1358 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1359 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1360 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1361 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1362 1363 /* Bit definitions for CPACR (AArch32 only) */ 1364 FIELD(CPACR, CP10, 20, 2) 1365 FIELD(CPACR, CP11, 22, 2) 1366 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1367 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1368 FIELD(CPACR, ASEDIS, 31, 1) 1369 1370 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1371 FIELD(CPACR_EL1, ZEN, 16, 2) 1372 FIELD(CPACR_EL1, FPEN, 20, 2) 1373 FIELD(CPACR_EL1, SMEN, 24, 2) 1374 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1375 1376 /* Bit definitions for HCPTR (AArch32 only) */ 1377 FIELD(HCPTR, TCP10, 10, 1) 1378 FIELD(HCPTR, TCP11, 11, 1) 1379 FIELD(HCPTR, TASE, 15, 1) 1380 FIELD(HCPTR, TTA, 20, 1) 1381 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1382 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1383 1384 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1385 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1386 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1387 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1388 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1389 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1390 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1391 FIELD(CPTR_EL2, TTA, 28, 1) 1392 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1393 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1394 1395 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1396 FIELD(CPTR_EL3, EZ, 8, 1) 1397 FIELD(CPTR_EL3, TFP, 10, 1) 1398 FIELD(CPTR_EL3, ESM, 12, 1) 1399 FIELD(CPTR_EL3, TTA, 20, 1) 1400 FIELD(CPTR_EL3, TAM, 30, 1) 1401 FIELD(CPTR_EL3, TCPAC, 31, 1) 1402 1403 #define MDCR_MTPME (1U << 28) 1404 #define MDCR_TDCC (1U << 27) 1405 #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ 1406 #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ 1407 #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ 1408 #define MDCR_EPMAD (1U << 21) 1409 #define MDCR_EDAD (1U << 20) 1410 #define MDCR_TTRF (1U << 19) 1411 #define MDCR_STE (1U << 18) /* MDCR_EL3 */ 1412 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1413 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1414 #define MDCR_SDD (1U << 16) 1415 #define MDCR_SPD (3U << 14) 1416 #define MDCR_TDRA (1U << 11) 1417 #define MDCR_TDOSA (1U << 10) 1418 #define MDCR_TDA (1U << 9) 1419 #define MDCR_TDE (1U << 8) 1420 #define MDCR_HPME (1U << 7) 1421 #define MDCR_TPM (1U << 6) 1422 #define MDCR_TPMCR (1U << 5) 1423 #define MDCR_HPMN (0x1fU) 1424 1425 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1426 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ 1427 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ 1428 MDCR_STE | MDCR_SPME | MDCR_SPD) 1429 1430 #define CPSR_M (0x1fU) 1431 #define CPSR_T (1U << 5) 1432 #define CPSR_F (1U << 6) 1433 #define CPSR_I (1U << 7) 1434 #define CPSR_A (1U << 8) 1435 #define CPSR_E (1U << 9) 1436 #define CPSR_IT_2_7 (0xfc00U) 1437 #define CPSR_GE (0xfU << 16) 1438 #define CPSR_IL (1U << 20) 1439 #define CPSR_DIT (1U << 21) 1440 #define CPSR_PAN (1U << 22) 1441 #define CPSR_SSBS (1U << 23) 1442 #define CPSR_J (1U << 24) 1443 #define CPSR_IT_0_1 (3U << 25) 1444 #define CPSR_Q (1U << 27) 1445 #define CPSR_V (1U << 28) 1446 #define CPSR_C (1U << 29) 1447 #define CPSR_Z (1U << 30) 1448 #define CPSR_N (1U << 31) 1449 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1450 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1451 1452 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1453 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1454 | CPSR_NZCV) 1455 /* Bits writable in user mode. */ 1456 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1457 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1458 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1459 1460 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1461 #define XPSR_EXCP 0x1ffU 1462 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1463 #define XPSR_IT_2_7 CPSR_IT_2_7 1464 #define XPSR_GE CPSR_GE 1465 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1466 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1467 #define XPSR_IT_0_1 CPSR_IT_0_1 1468 #define XPSR_Q CPSR_Q 1469 #define XPSR_V CPSR_V 1470 #define XPSR_C CPSR_C 1471 #define XPSR_Z CPSR_Z 1472 #define XPSR_N CPSR_N 1473 #define XPSR_NZCV CPSR_NZCV 1474 #define XPSR_IT CPSR_IT 1475 1476 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1477 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1478 #define TTBCR_PD0 (1U << 4) 1479 #define TTBCR_PD1 (1U << 5) 1480 #define TTBCR_EPD0 (1U << 7) 1481 #define TTBCR_IRGN0 (3U << 8) 1482 #define TTBCR_ORGN0 (3U << 10) 1483 #define TTBCR_SH0 (3U << 12) 1484 #define TTBCR_T1SZ (3U << 16) 1485 #define TTBCR_A1 (1U << 22) 1486 #define TTBCR_EPD1 (1U << 23) 1487 #define TTBCR_IRGN1 (3U << 24) 1488 #define TTBCR_ORGN1 (3U << 26) 1489 #define TTBCR_SH1 (1U << 28) 1490 #define TTBCR_EAE (1U << 31) 1491 1492 FIELD(VTCR, T0SZ, 0, 6) 1493 FIELD(VTCR, SL0, 6, 2) 1494 FIELD(VTCR, IRGN0, 8, 2) 1495 FIELD(VTCR, ORGN0, 10, 2) 1496 FIELD(VTCR, SH0, 12, 2) 1497 FIELD(VTCR, TG0, 14, 2) 1498 FIELD(VTCR, PS, 16, 3) 1499 FIELD(VTCR, VS, 19, 1) 1500 FIELD(VTCR, HA, 21, 1) 1501 FIELD(VTCR, HD, 22, 1) 1502 FIELD(VTCR, HWU59, 25, 1) 1503 FIELD(VTCR, HWU60, 26, 1) 1504 FIELD(VTCR, HWU61, 27, 1) 1505 FIELD(VTCR, HWU62, 28, 1) 1506 FIELD(VTCR, NSW, 29, 1) 1507 FIELD(VTCR, NSA, 30, 1) 1508 FIELD(VTCR, DS, 32, 1) 1509 FIELD(VTCR, SL2, 33, 1) 1510 1511 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1512 * Only these are valid when in AArch64 mode; in 1513 * AArch32 mode SPSRs are basically CPSR-format. 1514 */ 1515 #define PSTATE_SP (1U) 1516 #define PSTATE_M (0xFU) 1517 #define PSTATE_nRW (1U << 4) 1518 #define PSTATE_F (1U << 6) 1519 #define PSTATE_I (1U << 7) 1520 #define PSTATE_A (1U << 8) 1521 #define PSTATE_D (1U << 9) 1522 #define PSTATE_BTYPE (3U << 10) 1523 #define PSTATE_SSBS (1U << 12) 1524 #define PSTATE_IL (1U << 20) 1525 #define PSTATE_SS (1U << 21) 1526 #define PSTATE_PAN (1U << 22) 1527 #define PSTATE_UAO (1U << 23) 1528 #define PSTATE_DIT (1U << 24) 1529 #define PSTATE_TCO (1U << 25) 1530 #define PSTATE_V (1U << 28) 1531 #define PSTATE_C (1U << 29) 1532 #define PSTATE_Z (1U << 30) 1533 #define PSTATE_N (1U << 31) 1534 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1535 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1536 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1537 /* Mode values for AArch64 */ 1538 #define PSTATE_MODE_EL3h 13 1539 #define PSTATE_MODE_EL3t 12 1540 #define PSTATE_MODE_EL2h 9 1541 #define PSTATE_MODE_EL2t 8 1542 #define PSTATE_MODE_EL1h 5 1543 #define PSTATE_MODE_EL1t 4 1544 #define PSTATE_MODE_EL0t 0 1545 1546 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1547 FIELD(SVCR, SM, 0, 1) 1548 FIELD(SVCR, ZA, 1, 1) 1549 1550 /* Fields for SMCR_ELx. */ 1551 FIELD(SMCR, LEN, 0, 4) 1552 FIELD(SMCR, FA64, 31, 1) 1553 1554 /* Write a new value to v7m.exception, thus transitioning into or out 1555 * of Handler mode; this may result in a change of active stack pointer. 1556 */ 1557 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1558 1559 /* Map EL and handler into a PSTATE_MODE. */ 1560 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1561 { 1562 return (el << 2) | handler; 1563 } 1564 1565 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1566 * interprocessing, so we don't attempt to sync with the cpsr state used by 1567 * the 32 bit decoder. 1568 */ 1569 static inline uint32_t pstate_read(CPUARMState *env) 1570 { 1571 int ZF; 1572 1573 ZF = (env->ZF == 0); 1574 return (env->NF & 0x80000000) | (ZF << 30) 1575 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1576 | env->pstate | env->daif | (env->btype << 10); 1577 } 1578 1579 static inline void pstate_write(CPUARMState *env, uint32_t val) 1580 { 1581 env->ZF = (~val) & PSTATE_Z; 1582 env->NF = val; 1583 env->CF = (val >> 29) & 1; 1584 env->VF = (val << 3) & 0x80000000; 1585 env->daif = val & PSTATE_DAIF; 1586 env->btype = (val >> 10) & 3; 1587 env->pstate = val & ~CACHED_PSTATE_BITS; 1588 } 1589 1590 /* Return the current CPSR value. */ 1591 uint32_t cpsr_read(CPUARMState *env); 1592 1593 typedef enum CPSRWriteType { 1594 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1595 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1596 CPSRWriteRaw = 2, 1597 /* trust values, no reg bank switch, no hflags rebuild */ 1598 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1599 } CPSRWriteType; 1600 1601 /* 1602 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1603 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1604 * correspond to TB flags bits cached in the hflags, unless @write_type 1605 * is CPSRWriteRaw. 1606 */ 1607 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1608 CPSRWriteType write_type); 1609 1610 /* Return the current xPSR value. */ 1611 static inline uint32_t xpsr_read(CPUARMState *env) 1612 { 1613 int ZF; 1614 ZF = (env->ZF == 0); 1615 return (env->NF & 0x80000000) | (ZF << 30) 1616 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1617 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1618 | ((env->condexec_bits & 0xfc) << 8) 1619 | (env->GE << 16) 1620 | env->v7m.exception; 1621 } 1622 1623 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1624 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1625 { 1626 if (mask & XPSR_NZCV) { 1627 env->ZF = (~val) & XPSR_Z; 1628 env->NF = val; 1629 env->CF = (val >> 29) & 1; 1630 env->VF = (val << 3) & 0x80000000; 1631 } 1632 if (mask & XPSR_Q) { 1633 env->QF = ((val & XPSR_Q) != 0); 1634 } 1635 if (mask & XPSR_GE) { 1636 env->GE = (val & XPSR_GE) >> 16; 1637 } 1638 #ifndef CONFIG_USER_ONLY 1639 if (mask & XPSR_T) { 1640 env->thumb = ((val & XPSR_T) != 0); 1641 } 1642 if (mask & XPSR_IT_0_1) { 1643 env->condexec_bits &= ~3; 1644 env->condexec_bits |= (val >> 25) & 3; 1645 } 1646 if (mask & XPSR_IT_2_7) { 1647 env->condexec_bits &= 3; 1648 env->condexec_bits |= (val >> 8) & 0xfc; 1649 } 1650 if (mask & XPSR_EXCP) { 1651 /* Note that this only happens on exception exit */ 1652 write_v7m_exception(env, val & XPSR_EXCP); 1653 } 1654 #endif 1655 } 1656 1657 #define HCR_VM (1ULL << 0) 1658 #define HCR_SWIO (1ULL << 1) 1659 #define HCR_PTW (1ULL << 2) 1660 #define HCR_FMO (1ULL << 3) 1661 #define HCR_IMO (1ULL << 4) 1662 #define HCR_AMO (1ULL << 5) 1663 #define HCR_VF (1ULL << 6) 1664 #define HCR_VI (1ULL << 7) 1665 #define HCR_VSE (1ULL << 8) 1666 #define HCR_FB (1ULL << 9) 1667 #define HCR_BSU_MASK (3ULL << 10) 1668 #define HCR_DC (1ULL << 12) 1669 #define HCR_TWI (1ULL << 13) 1670 #define HCR_TWE (1ULL << 14) 1671 #define HCR_TID0 (1ULL << 15) 1672 #define HCR_TID1 (1ULL << 16) 1673 #define HCR_TID2 (1ULL << 17) 1674 #define HCR_TID3 (1ULL << 18) 1675 #define HCR_TSC (1ULL << 19) 1676 #define HCR_TIDCP (1ULL << 20) 1677 #define HCR_TACR (1ULL << 21) 1678 #define HCR_TSW (1ULL << 22) 1679 #define HCR_TPCP (1ULL << 23) 1680 #define HCR_TPU (1ULL << 24) 1681 #define HCR_TTLB (1ULL << 25) 1682 #define HCR_TVM (1ULL << 26) 1683 #define HCR_TGE (1ULL << 27) 1684 #define HCR_TDZ (1ULL << 28) 1685 #define HCR_HCD (1ULL << 29) 1686 #define HCR_TRVM (1ULL << 30) 1687 #define HCR_RW (1ULL << 31) 1688 #define HCR_CD (1ULL << 32) 1689 #define HCR_ID (1ULL << 33) 1690 #define HCR_E2H (1ULL << 34) 1691 #define HCR_TLOR (1ULL << 35) 1692 #define HCR_TERR (1ULL << 36) 1693 #define HCR_TEA (1ULL << 37) 1694 #define HCR_MIOCNCE (1ULL << 38) 1695 #define HCR_TME (1ULL << 39) 1696 #define HCR_APK (1ULL << 40) 1697 #define HCR_API (1ULL << 41) 1698 #define HCR_NV (1ULL << 42) 1699 #define HCR_NV1 (1ULL << 43) 1700 #define HCR_AT (1ULL << 44) 1701 #define HCR_NV2 (1ULL << 45) 1702 #define HCR_FWB (1ULL << 46) 1703 #define HCR_FIEN (1ULL << 47) 1704 #define HCR_GPF (1ULL << 48) 1705 #define HCR_TID4 (1ULL << 49) 1706 #define HCR_TICAB (1ULL << 50) 1707 #define HCR_AMVOFFEN (1ULL << 51) 1708 #define HCR_TOCU (1ULL << 52) 1709 #define HCR_ENSCXT (1ULL << 53) 1710 #define HCR_TTLBIS (1ULL << 54) 1711 #define HCR_TTLBOS (1ULL << 55) 1712 #define HCR_ATA (1ULL << 56) 1713 #define HCR_DCT (1ULL << 57) 1714 #define HCR_TID5 (1ULL << 58) 1715 #define HCR_TWEDEN (1ULL << 59) 1716 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1717 1718 #define HCRX_ENAS0 (1ULL << 0) 1719 #define HCRX_ENALS (1ULL << 1) 1720 #define HCRX_ENASR (1ULL << 2) 1721 #define HCRX_FNXS (1ULL << 3) 1722 #define HCRX_FGTNXS (1ULL << 4) 1723 #define HCRX_SMPME (1ULL << 5) 1724 #define HCRX_TALLINT (1ULL << 6) 1725 #define HCRX_VINMI (1ULL << 7) 1726 #define HCRX_VFNMI (1ULL << 8) 1727 #define HCRX_CMOW (1ULL << 9) 1728 #define HCRX_MCE2 (1ULL << 10) 1729 #define HCRX_MSCEN (1ULL << 11) 1730 1731 #define HPFAR_NS (1ULL << 63) 1732 1733 #define SCR_NS (1ULL << 0) 1734 #define SCR_IRQ (1ULL << 1) 1735 #define SCR_FIQ (1ULL << 2) 1736 #define SCR_EA (1ULL << 3) 1737 #define SCR_FW (1ULL << 4) 1738 #define SCR_AW (1ULL << 5) 1739 #define SCR_NET (1ULL << 6) 1740 #define SCR_SMD (1ULL << 7) 1741 #define SCR_HCE (1ULL << 8) 1742 #define SCR_SIF (1ULL << 9) 1743 #define SCR_RW (1ULL << 10) 1744 #define SCR_ST (1ULL << 11) 1745 #define SCR_TWI (1ULL << 12) 1746 #define SCR_TWE (1ULL << 13) 1747 #define SCR_TLOR (1ULL << 14) 1748 #define SCR_TERR (1ULL << 15) 1749 #define SCR_APK (1ULL << 16) 1750 #define SCR_API (1ULL << 17) 1751 #define SCR_EEL2 (1ULL << 18) 1752 #define SCR_EASE (1ULL << 19) 1753 #define SCR_NMEA (1ULL << 20) 1754 #define SCR_FIEN (1ULL << 21) 1755 #define SCR_ENSCXT (1ULL << 25) 1756 #define SCR_ATA (1ULL << 26) 1757 #define SCR_FGTEN (1ULL << 27) 1758 #define SCR_ECVEN (1ULL << 28) 1759 #define SCR_TWEDEN (1ULL << 29) 1760 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1761 #define SCR_TME (1ULL << 34) 1762 #define SCR_AMVOFFEN (1ULL << 35) 1763 #define SCR_ENAS0 (1ULL << 36) 1764 #define SCR_ADEN (1ULL << 37) 1765 #define SCR_HXEN (1ULL << 38) 1766 #define SCR_TRNDR (1ULL << 40) 1767 #define SCR_ENTP2 (1ULL << 41) 1768 #define SCR_GPF (1ULL << 48) 1769 #define SCR_NSE (1ULL << 62) 1770 1771 #define HSTR_TTEE (1 << 16) 1772 #define HSTR_TJDBX (1 << 17) 1773 1774 #define CNTHCTL_CNTVMASK (1 << 18) 1775 #define CNTHCTL_CNTPMASK (1 << 19) 1776 1777 /* Return the current FPSCR value. */ 1778 uint32_t vfp_get_fpscr(CPUARMState *env); 1779 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1780 1781 /* FPCR, Floating Point Control Register 1782 * FPSR, Floating Poiht Status Register 1783 * 1784 * For A64 the FPSCR is split into two logically distinct registers, 1785 * FPCR and FPSR. However since they still use non-overlapping bits 1786 * we store the underlying state in fpscr and just mask on read/write. 1787 */ 1788 #define FPSR_MASK 0xf800009f 1789 #define FPCR_MASK 0x07ff9f00 1790 1791 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1792 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1793 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1794 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1795 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1796 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1797 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1798 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1799 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1800 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1801 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1802 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1803 #define FPCR_V (1 << 28) /* FP overflow flag */ 1804 #define FPCR_C (1 << 29) /* FP carry flag */ 1805 #define FPCR_Z (1 << 30) /* FP zero flag */ 1806 #define FPCR_N (1 << 31) /* FP negative flag */ 1807 1808 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1809 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1810 #define FPCR_LTPSIZE_LENGTH 3 1811 1812 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1813 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1814 1815 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1816 { 1817 return vfp_get_fpscr(env) & FPSR_MASK; 1818 } 1819 1820 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1821 { 1822 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1823 vfp_set_fpscr(env, new_fpscr); 1824 } 1825 1826 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1827 { 1828 return vfp_get_fpscr(env) & FPCR_MASK; 1829 } 1830 1831 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1832 { 1833 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1834 vfp_set_fpscr(env, new_fpscr); 1835 } 1836 1837 enum arm_cpu_mode { 1838 ARM_CPU_MODE_USR = 0x10, 1839 ARM_CPU_MODE_FIQ = 0x11, 1840 ARM_CPU_MODE_IRQ = 0x12, 1841 ARM_CPU_MODE_SVC = 0x13, 1842 ARM_CPU_MODE_MON = 0x16, 1843 ARM_CPU_MODE_ABT = 0x17, 1844 ARM_CPU_MODE_HYP = 0x1a, 1845 ARM_CPU_MODE_UND = 0x1b, 1846 ARM_CPU_MODE_SYS = 0x1f 1847 }; 1848 1849 /* VFP system registers. */ 1850 #define ARM_VFP_FPSID 0 1851 #define ARM_VFP_FPSCR 1 1852 #define ARM_VFP_MVFR2 5 1853 #define ARM_VFP_MVFR1 6 1854 #define ARM_VFP_MVFR0 7 1855 #define ARM_VFP_FPEXC 8 1856 #define ARM_VFP_FPINST 9 1857 #define ARM_VFP_FPINST2 10 1858 /* These ones are M-profile only */ 1859 #define ARM_VFP_FPSCR_NZCVQC 2 1860 #define ARM_VFP_VPR 12 1861 #define ARM_VFP_P0 13 1862 #define ARM_VFP_FPCXT_NS 14 1863 #define ARM_VFP_FPCXT_S 15 1864 1865 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1866 #define QEMU_VFP_FPSCR_NZCV 0xffff 1867 1868 /* iwMMXt coprocessor control registers. */ 1869 #define ARM_IWMMXT_wCID 0 1870 #define ARM_IWMMXT_wCon 1 1871 #define ARM_IWMMXT_wCSSF 2 1872 #define ARM_IWMMXT_wCASF 3 1873 #define ARM_IWMMXT_wCGR0 8 1874 #define ARM_IWMMXT_wCGR1 9 1875 #define ARM_IWMMXT_wCGR2 10 1876 #define ARM_IWMMXT_wCGR3 11 1877 1878 /* V7M CCR bits */ 1879 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1880 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1881 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1882 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1883 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1884 FIELD(V7M_CCR, STKALIGN, 9, 1) 1885 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1886 FIELD(V7M_CCR, DC, 16, 1) 1887 FIELD(V7M_CCR, IC, 17, 1) 1888 FIELD(V7M_CCR, BP, 18, 1) 1889 FIELD(V7M_CCR, LOB, 19, 1) 1890 FIELD(V7M_CCR, TRD, 20, 1) 1891 1892 /* V7M SCR bits */ 1893 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1894 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1895 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1896 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1897 1898 /* V7M AIRCR bits */ 1899 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1900 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1901 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1902 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1903 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1904 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1905 FIELD(V7M_AIRCR, PRIS, 14, 1) 1906 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1907 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1908 1909 /* V7M CFSR bits for MMFSR */ 1910 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1911 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1912 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1913 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1914 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1915 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1916 1917 /* V7M CFSR bits for BFSR */ 1918 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1919 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1920 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1921 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1922 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1923 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1924 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1925 1926 /* V7M CFSR bits for UFSR */ 1927 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1928 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1929 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1930 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1931 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1932 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1933 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1934 1935 /* V7M CFSR bit masks covering all of the subregister bits */ 1936 FIELD(V7M_CFSR, MMFSR, 0, 8) 1937 FIELD(V7M_CFSR, BFSR, 8, 8) 1938 FIELD(V7M_CFSR, UFSR, 16, 16) 1939 1940 /* V7M HFSR bits */ 1941 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1942 FIELD(V7M_HFSR, FORCED, 30, 1) 1943 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1944 1945 /* V7M DFSR bits */ 1946 FIELD(V7M_DFSR, HALTED, 0, 1) 1947 FIELD(V7M_DFSR, BKPT, 1, 1) 1948 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1949 FIELD(V7M_DFSR, VCATCH, 3, 1) 1950 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1951 1952 /* V7M SFSR bits */ 1953 FIELD(V7M_SFSR, INVEP, 0, 1) 1954 FIELD(V7M_SFSR, INVIS, 1, 1) 1955 FIELD(V7M_SFSR, INVER, 2, 1) 1956 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1957 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1958 FIELD(V7M_SFSR, LSPERR, 5, 1) 1959 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1960 FIELD(V7M_SFSR, LSERR, 7, 1) 1961 1962 /* v7M MPU_CTRL bits */ 1963 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1964 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1965 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1966 1967 /* v7M CLIDR bits */ 1968 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1969 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1970 FIELD(V7M_CLIDR, LOC, 24, 3) 1971 FIELD(V7M_CLIDR, LOUU, 27, 3) 1972 FIELD(V7M_CLIDR, ICB, 30, 2) 1973 1974 FIELD(V7M_CSSELR, IND, 0, 1) 1975 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1976 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1977 * define a mask for this and check that it doesn't permit running off 1978 * the end of the array. 1979 */ 1980 FIELD(V7M_CSSELR, INDEX, 0, 4) 1981 1982 /* v7M FPCCR bits */ 1983 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1984 FIELD(V7M_FPCCR, USER, 1, 1) 1985 FIELD(V7M_FPCCR, S, 2, 1) 1986 FIELD(V7M_FPCCR, THREAD, 3, 1) 1987 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1988 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1989 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1990 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1991 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1992 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1993 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1994 FIELD(V7M_FPCCR, RES0, 11, 15) 1995 FIELD(V7M_FPCCR, TS, 26, 1) 1996 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1997 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1998 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1999 FIELD(V7M_FPCCR, LSPEN, 30, 1) 2000 FIELD(V7M_FPCCR, ASPEN, 31, 1) 2001 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 2002 #define R_V7M_FPCCR_BANKED_MASK \ 2003 (R_V7M_FPCCR_LSPACT_MASK | \ 2004 R_V7M_FPCCR_USER_MASK | \ 2005 R_V7M_FPCCR_THREAD_MASK | \ 2006 R_V7M_FPCCR_MMRDY_MASK | \ 2007 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 2008 R_V7M_FPCCR_UFRDY_MASK | \ 2009 R_V7M_FPCCR_ASPEN_MASK) 2010 2011 /* v7M VPR bits */ 2012 FIELD(V7M_VPR, P0, 0, 16) 2013 FIELD(V7M_VPR, MASK01, 16, 4) 2014 FIELD(V7M_VPR, MASK23, 20, 4) 2015 2016 /* 2017 * System register ID fields. 2018 */ 2019 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 2020 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 2021 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 2022 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 2023 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 2024 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 2025 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 2026 FIELD(CLIDR_EL1, LOUIS, 21, 3) 2027 FIELD(CLIDR_EL1, LOC, 24, 3) 2028 FIELD(CLIDR_EL1, LOUU, 27, 3) 2029 FIELD(CLIDR_EL1, ICB, 30, 3) 2030 2031 /* When FEAT_CCIDX is implemented */ 2032 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 2033 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 2034 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 2035 2036 /* When FEAT_CCIDX is not implemented */ 2037 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 2038 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 2039 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 2040 2041 FIELD(CTR_EL0, IMINLINE, 0, 4) 2042 FIELD(CTR_EL0, L1IP, 14, 2) 2043 FIELD(CTR_EL0, DMINLINE, 16, 4) 2044 FIELD(CTR_EL0, ERG, 20, 4) 2045 FIELD(CTR_EL0, CWG, 24, 4) 2046 FIELD(CTR_EL0, IDC, 28, 1) 2047 FIELD(CTR_EL0, DIC, 29, 1) 2048 FIELD(CTR_EL0, TMINLINE, 32, 6) 2049 2050 FIELD(MIDR_EL1, REVISION, 0, 4) 2051 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2052 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2053 FIELD(MIDR_EL1, VARIANT, 20, 4) 2054 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2055 2056 FIELD(ID_ISAR0, SWAP, 0, 4) 2057 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2058 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2059 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2060 FIELD(ID_ISAR0, COPROC, 16, 4) 2061 FIELD(ID_ISAR0, DEBUG, 20, 4) 2062 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2063 2064 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2065 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2066 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2067 FIELD(ID_ISAR1, EXTEND, 12, 4) 2068 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2069 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2070 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2071 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2072 2073 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2074 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2075 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2076 FIELD(ID_ISAR2, MULT, 12, 4) 2077 FIELD(ID_ISAR2, MULTS, 16, 4) 2078 FIELD(ID_ISAR2, MULTU, 20, 4) 2079 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2080 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2081 2082 FIELD(ID_ISAR3, SATURATE, 0, 4) 2083 FIELD(ID_ISAR3, SIMD, 4, 4) 2084 FIELD(ID_ISAR3, SVC, 8, 4) 2085 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2086 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2087 FIELD(ID_ISAR3, T32COPY, 20, 4) 2088 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2089 FIELD(ID_ISAR3, T32EE, 28, 4) 2090 2091 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2092 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2093 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2094 FIELD(ID_ISAR4, SMC, 12, 4) 2095 FIELD(ID_ISAR4, BARRIER, 16, 4) 2096 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2097 FIELD(ID_ISAR4, PSR_M, 24, 4) 2098 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2099 2100 FIELD(ID_ISAR5, SEVL, 0, 4) 2101 FIELD(ID_ISAR5, AES, 4, 4) 2102 FIELD(ID_ISAR5, SHA1, 8, 4) 2103 FIELD(ID_ISAR5, SHA2, 12, 4) 2104 FIELD(ID_ISAR5, CRC32, 16, 4) 2105 FIELD(ID_ISAR5, RDM, 24, 4) 2106 FIELD(ID_ISAR5, VCMA, 28, 4) 2107 2108 FIELD(ID_ISAR6, JSCVT, 0, 4) 2109 FIELD(ID_ISAR6, DP, 4, 4) 2110 FIELD(ID_ISAR6, FHM, 8, 4) 2111 FIELD(ID_ISAR6, SB, 12, 4) 2112 FIELD(ID_ISAR6, SPECRES, 16, 4) 2113 FIELD(ID_ISAR6, BF16, 20, 4) 2114 FIELD(ID_ISAR6, I8MM, 24, 4) 2115 2116 FIELD(ID_MMFR0, VMSA, 0, 4) 2117 FIELD(ID_MMFR0, PMSA, 4, 4) 2118 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2119 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2120 FIELD(ID_MMFR0, TCM, 16, 4) 2121 FIELD(ID_MMFR0, AUXREG, 20, 4) 2122 FIELD(ID_MMFR0, FCSE, 24, 4) 2123 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2124 2125 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2126 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2127 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2128 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2129 FIELD(ID_MMFR1, L1HVD, 16, 4) 2130 FIELD(ID_MMFR1, L1UNI, 20, 4) 2131 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2132 FIELD(ID_MMFR1, BPRED, 28, 4) 2133 2134 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2135 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2136 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2137 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2138 FIELD(ID_MMFR2, UNITLB, 16, 4) 2139 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2140 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2141 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2142 2143 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2144 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2145 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2146 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2147 FIELD(ID_MMFR3, PAN, 16, 4) 2148 FIELD(ID_MMFR3, COHWALK, 20, 4) 2149 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2150 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2151 2152 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2153 FIELD(ID_MMFR4, AC2, 4, 4) 2154 FIELD(ID_MMFR4, XNX, 8, 4) 2155 FIELD(ID_MMFR4, CNP, 12, 4) 2156 FIELD(ID_MMFR4, HPDS, 16, 4) 2157 FIELD(ID_MMFR4, LSM, 20, 4) 2158 FIELD(ID_MMFR4, CCIDX, 24, 4) 2159 FIELD(ID_MMFR4, EVT, 28, 4) 2160 2161 FIELD(ID_MMFR5, ETS, 0, 4) 2162 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2163 2164 FIELD(ID_PFR0, STATE0, 0, 4) 2165 FIELD(ID_PFR0, STATE1, 4, 4) 2166 FIELD(ID_PFR0, STATE2, 8, 4) 2167 FIELD(ID_PFR0, STATE3, 12, 4) 2168 FIELD(ID_PFR0, CSV2, 16, 4) 2169 FIELD(ID_PFR0, AMU, 20, 4) 2170 FIELD(ID_PFR0, DIT, 24, 4) 2171 FIELD(ID_PFR0, RAS, 28, 4) 2172 2173 FIELD(ID_PFR1, PROGMOD, 0, 4) 2174 FIELD(ID_PFR1, SECURITY, 4, 4) 2175 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2176 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2177 FIELD(ID_PFR1, GENTIMER, 16, 4) 2178 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2179 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2180 FIELD(ID_PFR1, GIC, 28, 4) 2181 2182 FIELD(ID_PFR2, CSV3, 0, 4) 2183 FIELD(ID_PFR2, SSBS, 4, 4) 2184 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2185 2186 FIELD(ID_AA64ISAR0, AES, 4, 4) 2187 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2188 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2189 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2190 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2191 FIELD(ID_AA64ISAR0, TME, 24, 4) 2192 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2193 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2194 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2195 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2196 FIELD(ID_AA64ISAR0, DP, 44, 4) 2197 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2198 FIELD(ID_AA64ISAR0, TS, 52, 4) 2199 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2200 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2201 2202 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2203 FIELD(ID_AA64ISAR1, APA, 4, 4) 2204 FIELD(ID_AA64ISAR1, API, 8, 4) 2205 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2206 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2207 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2208 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2209 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2210 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2211 FIELD(ID_AA64ISAR1, SB, 36, 4) 2212 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2213 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2214 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2215 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2216 FIELD(ID_AA64ISAR1, XS, 56, 4) 2217 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2218 2219 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2220 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2221 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2222 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2223 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2224 FIELD(ID_AA64ISAR2, BC, 20, 4) 2225 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2226 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2227 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2228 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2229 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2230 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2231 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2232 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2233 2234 FIELD(ID_AA64PFR0, EL0, 0, 4) 2235 FIELD(ID_AA64PFR0, EL1, 4, 4) 2236 FIELD(ID_AA64PFR0, EL2, 8, 4) 2237 FIELD(ID_AA64PFR0, EL3, 12, 4) 2238 FIELD(ID_AA64PFR0, FP, 16, 4) 2239 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2240 FIELD(ID_AA64PFR0, GIC, 24, 4) 2241 FIELD(ID_AA64PFR0, RAS, 28, 4) 2242 FIELD(ID_AA64PFR0, SVE, 32, 4) 2243 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2244 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2245 FIELD(ID_AA64PFR0, AMU, 44, 4) 2246 FIELD(ID_AA64PFR0, DIT, 48, 4) 2247 FIELD(ID_AA64PFR0, RME, 52, 4) 2248 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2249 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2250 2251 FIELD(ID_AA64PFR1, BT, 0, 4) 2252 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2253 FIELD(ID_AA64PFR1, MTE, 8, 4) 2254 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2255 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2256 FIELD(ID_AA64PFR1, SME, 24, 4) 2257 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2258 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2259 FIELD(ID_AA64PFR1, NMI, 36, 4) 2260 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2261 FIELD(ID_AA64PFR1, GCS, 44, 4) 2262 FIELD(ID_AA64PFR1, THE, 48, 4) 2263 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2264 FIELD(ID_AA64PFR1, DF2, 56, 4) 2265 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2266 2267 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2268 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2269 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2270 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2271 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2272 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2273 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2274 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2275 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2276 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2277 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2278 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2279 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2280 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2281 2282 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2283 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2284 FIELD(ID_AA64MMFR1, VH, 8, 4) 2285 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2286 FIELD(ID_AA64MMFR1, LO, 16, 4) 2287 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2288 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2289 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2290 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2291 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2292 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2293 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2294 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2295 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2296 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2297 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2298 2299 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2300 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2301 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2302 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2303 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2304 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2305 FIELD(ID_AA64MMFR2, NV, 24, 4) 2306 FIELD(ID_AA64MMFR2, ST, 28, 4) 2307 FIELD(ID_AA64MMFR2, AT, 32, 4) 2308 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2309 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2310 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2311 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2312 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2313 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2314 2315 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2316 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2317 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2318 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2319 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2320 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2321 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2322 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2323 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2324 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2325 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2326 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2327 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2328 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2329 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2330 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2331 2332 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2333 FIELD(ID_AA64ZFR0, AES, 4, 4) 2334 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2335 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2336 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2337 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2338 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2339 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2340 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2341 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2342 2343 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2344 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2345 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2346 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2347 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2348 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2349 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2350 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2351 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2352 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2353 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2354 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2355 2356 FIELD(ID_DFR0, COPDBG, 0, 4) 2357 FIELD(ID_DFR0, COPSDBG, 4, 4) 2358 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2359 FIELD(ID_DFR0, COPTRC, 12, 4) 2360 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2361 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2362 FIELD(ID_DFR0, PERFMON, 24, 4) 2363 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2364 2365 FIELD(ID_DFR1, MTPMU, 0, 4) 2366 FIELD(ID_DFR1, HPMN0, 4, 4) 2367 2368 FIELD(DBGDIDR, SE_IMP, 12, 1) 2369 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2370 FIELD(DBGDIDR, VERSION, 16, 4) 2371 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2372 FIELD(DBGDIDR, BRPS, 24, 4) 2373 FIELD(DBGDIDR, WRPS, 28, 4) 2374 2375 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2376 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2377 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2378 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2379 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2380 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2381 FIELD(DBGDEVID, AUXREGS, 24, 4) 2382 FIELD(DBGDEVID, CIDMASK, 28, 4) 2383 2384 FIELD(MVFR0, SIMDREG, 0, 4) 2385 FIELD(MVFR0, FPSP, 4, 4) 2386 FIELD(MVFR0, FPDP, 8, 4) 2387 FIELD(MVFR0, FPTRAP, 12, 4) 2388 FIELD(MVFR0, FPDIVIDE, 16, 4) 2389 FIELD(MVFR0, FPSQRT, 20, 4) 2390 FIELD(MVFR0, FPSHVEC, 24, 4) 2391 FIELD(MVFR0, FPROUND, 28, 4) 2392 2393 FIELD(MVFR1, FPFTZ, 0, 4) 2394 FIELD(MVFR1, FPDNAN, 4, 4) 2395 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2396 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2397 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2398 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2399 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2400 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2401 FIELD(MVFR1, FPHP, 24, 4) 2402 FIELD(MVFR1, SIMDFMAC, 28, 4) 2403 2404 FIELD(MVFR2, SIMDMISC, 0, 4) 2405 FIELD(MVFR2, FPMISC, 4, 4) 2406 2407 FIELD(GPCCR, PPS, 0, 3) 2408 FIELD(GPCCR, IRGN, 8, 2) 2409 FIELD(GPCCR, ORGN, 10, 2) 2410 FIELD(GPCCR, SH, 12, 2) 2411 FIELD(GPCCR, PGS, 14, 2) 2412 FIELD(GPCCR, GPC, 16, 1) 2413 FIELD(GPCCR, GPCP, 17, 1) 2414 FIELD(GPCCR, L0GPTSZ, 20, 4) 2415 2416 FIELD(MFAR, FPA, 12, 40) 2417 FIELD(MFAR, NSE, 62, 1) 2418 FIELD(MFAR, NS, 63, 1) 2419 2420 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2421 2422 /* If adding a feature bit which corresponds to a Linux ELF 2423 * HWCAP bit, remember to update the feature-bit-to-hwcap 2424 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2425 */ 2426 enum arm_features { 2427 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2428 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2429 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2430 ARM_FEATURE_V6, 2431 ARM_FEATURE_V6K, 2432 ARM_FEATURE_V7, 2433 ARM_FEATURE_THUMB2, 2434 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2435 ARM_FEATURE_NEON, 2436 ARM_FEATURE_M, /* Microcontroller profile. */ 2437 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2438 ARM_FEATURE_THUMB2EE, 2439 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2440 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2441 ARM_FEATURE_V4T, 2442 ARM_FEATURE_V5, 2443 ARM_FEATURE_STRONGARM, 2444 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2445 ARM_FEATURE_GENERIC_TIMER, 2446 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2447 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2448 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2449 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2450 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2451 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2452 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2453 ARM_FEATURE_V8, 2454 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2455 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2456 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2457 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2458 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2459 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2460 ARM_FEATURE_PMU, /* has PMU support */ 2461 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2462 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2463 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2464 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2465 }; 2466 2467 static inline int arm_feature(CPUARMState *env, int feature) 2468 { 2469 return (env->features & (1ULL << feature)) != 0; 2470 } 2471 2472 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2473 2474 /* 2475 * ARM v9 security states. 2476 * The ordering of the enumeration corresponds to the low 2 bits 2477 * of the GPI value, and (except for Root) the concat of NSE:NS. 2478 */ 2479 2480 typedef enum ARMSecuritySpace { 2481 ARMSS_Secure = 0, 2482 ARMSS_NonSecure = 1, 2483 ARMSS_Root = 2, 2484 ARMSS_Realm = 3, 2485 } ARMSecuritySpace; 2486 2487 /* Return true if @space is secure, in the pre-v9 sense. */ 2488 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2489 { 2490 return space == ARMSS_Secure || space == ARMSS_Root; 2491 } 2492 2493 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2494 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2495 { 2496 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2497 } 2498 2499 #if !defined(CONFIG_USER_ONLY) 2500 /** 2501 * arm_security_space_below_el3: 2502 * @env: cpu context 2503 * 2504 * Return the security space of exception levels below EL3, following 2505 * an exception return to those levels. Unlike arm_security_space, 2506 * this doesn't care about the current EL. 2507 */ 2508 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2509 2510 /** 2511 * arm_is_secure_below_el3: 2512 * @env: cpu context 2513 * 2514 * Return true if exception levels below EL3 are in secure state, 2515 * or would be following an exception return to those levels. 2516 */ 2517 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2518 { 2519 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2520 return ss == ARMSS_Secure; 2521 } 2522 2523 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2524 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2525 { 2526 assert(!arm_feature(env, ARM_FEATURE_M)); 2527 if (arm_feature(env, ARM_FEATURE_EL3)) { 2528 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2529 /* CPU currently in AArch64 state and EL3 */ 2530 return true; 2531 } else if (!is_a64(env) && 2532 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2533 /* CPU currently in AArch32 state and monitor mode */ 2534 return true; 2535 } 2536 } 2537 return false; 2538 } 2539 2540 /** 2541 * arm_security_space: 2542 * @env: cpu context 2543 * 2544 * Return the current security space of the cpu. 2545 */ 2546 ARMSecuritySpace arm_security_space(CPUARMState *env); 2547 2548 /** 2549 * arm_is_secure: 2550 * @env: cpu context 2551 * 2552 * Return true if the processor is in secure state. 2553 */ 2554 static inline bool arm_is_secure(CPUARMState *env) 2555 { 2556 return arm_space_is_secure(arm_security_space(env)); 2557 } 2558 2559 /* 2560 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2561 * This corresponds to the pseudocode EL2Enabled(). 2562 */ 2563 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2564 ARMSecuritySpace space) 2565 { 2566 assert(space != ARMSS_Root); 2567 return arm_feature(env, ARM_FEATURE_EL2) 2568 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2569 } 2570 2571 static inline bool arm_is_el2_enabled(CPUARMState *env) 2572 { 2573 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2574 } 2575 2576 #else 2577 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2578 { 2579 return ARMSS_NonSecure; 2580 } 2581 2582 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2583 { 2584 return false; 2585 } 2586 2587 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2588 { 2589 return ARMSS_NonSecure; 2590 } 2591 2592 static inline bool arm_is_secure(CPUARMState *env) 2593 { 2594 return false; 2595 } 2596 2597 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2598 ARMSecuritySpace space) 2599 { 2600 return false; 2601 } 2602 2603 static inline bool arm_is_el2_enabled(CPUARMState *env) 2604 { 2605 return false; 2606 } 2607 #endif 2608 2609 /** 2610 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2611 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2612 * "for all purposes other than a direct read or write access of HCR_EL2." 2613 * Not included here is HCR_RW. 2614 */ 2615 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2616 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2617 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2618 2619 /* Return true if the specified exception level is running in AArch64 state. */ 2620 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2621 { 2622 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2623 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2624 */ 2625 assert(el >= 1 && el <= 3); 2626 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2627 2628 /* The highest exception level is always at the maximum supported 2629 * register width, and then lower levels have a register width controlled 2630 * by bits in the SCR or HCR registers. 2631 */ 2632 if (el == 3) { 2633 return aa64; 2634 } 2635 2636 if (arm_feature(env, ARM_FEATURE_EL3) && 2637 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2638 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2639 } 2640 2641 if (el == 2) { 2642 return aa64; 2643 } 2644 2645 if (arm_is_el2_enabled(env)) { 2646 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2647 } 2648 2649 return aa64; 2650 } 2651 2652 /* Function for determining whether guest cp register reads and writes should 2653 * access the secure or non-secure bank of a cp register. When EL3 is 2654 * operating in AArch32 state, the NS-bit determines whether the secure 2655 * instance of a cp register should be used. When EL3 is AArch64 (or if 2656 * it doesn't exist at all) then there is no register banking, and all 2657 * accesses are to the non-secure version. 2658 */ 2659 static inline bool access_secure_reg(CPUARMState *env) 2660 { 2661 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2662 !arm_el_is_aa64(env, 3) && 2663 !(env->cp15.scr_el3 & SCR_NS)); 2664 2665 return ret; 2666 } 2667 2668 /* Macros for accessing a specified CP register bank */ 2669 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2670 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2671 2672 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2673 do { \ 2674 if (_secure) { \ 2675 (_env)->cp15._regname##_s = (_val); \ 2676 } else { \ 2677 (_env)->cp15._regname##_ns = (_val); \ 2678 } \ 2679 } while (0) 2680 2681 /* Macros for automatically accessing a specific CP register bank depending on 2682 * the current secure state of the system. These macros are not intended for 2683 * supporting instruction translation reads/writes as these are dependent 2684 * solely on the SCR.NS bit and not the mode. 2685 */ 2686 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2687 A32_BANKED_REG_GET((_env), _regname, \ 2688 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2689 2690 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2691 A32_BANKED_REG_SET((_env), _regname, \ 2692 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2693 (_val)) 2694 2695 void arm_cpu_list(void); 2696 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2697 uint32_t cur_el, bool secure); 2698 2699 /* Return the highest implemented Exception Level */ 2700 static inline int arm_highest_el(CPUARMState *env) 2701 { 2702 if (arm_feature(env, ARM_FEATURE_EL3)) { 2703 return 3; 2704 } 2705 if (arm_feature(env, ARM_FEATURE_EL2)) { 2706 return 2; 2707 } 2708 return 1; 2709 } 2710 2711 /* Return true if a v7M CPU is in Handler mode */ 2712 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2713 { 2714 return env->v7m.exception != 0; 2715 } 2716 2717 /* Return the current Exception Level (as per ARMv8; note that this differs 2718 * from the ARMv7 Privilege Level). 2719 */ 2720 static inline int arm_current_el(CPUARMState *env) 2721 { 2722 if (arm_feature(env, ARM_FEATURE_M)) { 2723 return arm_v7m_is_handler_mode(env) || 2724 !(env->v7m.control[env->v7m.secure] & 1); 2725 } 2726 2727 if (is_a64(env)) { 2728 return extract32(env->pstate, 2, 2); 2729 } 2730 2731 switch (env->uncached_cpsr & 0x1f) { 2732 case ARM_CPU_MODE_USR: 2733 return 0; 2734 case ARM_CPU_MODE_HYP: 2735 return 2; 2736 case ARM_CPU_MODE_MON: 2737 return 3; 2738 default: 2739 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2740 /* If EL3 is 32-bit then all secure privileged modes run in 2741 * EL3 2742 */ 2743 return 3; 2744 } 2745 2746 return 1; 2747 } 2748 } 2749 2750 /** 2751 * write_list_to_cpustate 2752 * @cpu: ARMCPU 2753 * 2754 * For each register listed in the ARMCPU cpreg_indexes list, write 2755 * its value from the cpreg_values list into the ARMCPUState structure. 2756 * This updates TCG's working data structures from KVM data or 2757 * from incoming migration state. 2758 * 2759 * Returns: true if all register values were updated correctly, 2760 * false if some register was unknown or could not be written. 2761 * Note that we do not stop early on failure -- we will attempt 2762 * writing all registers in the list. 2763 */ 2764 bool write_list_to_cpustate(ARMCPU *cpu); 2765 2766 /** 2767 * write_cpustate_to_list: 2768 * @cpu: ARMCPU 2769 * @kvm_sync: true if this is for syncing back to KVM 2770 * 2771 * For each register listed in the ARMCPU cpreg_indexes list, write 2772 * its value from the ARMCPUState structure into the cpreg_values list. 2773 * This is used to copy info from TCG's working data structures into 2774 * KVM or for outbound migration. 2775 * 2776 * @kvm_sync is true if we are doing this in order to sync the 2777 * register state back to KVM. In this case we will only update 2778 * values in the list if the previous list->cpustate sync actually 2779 * successfully wrote the CPU state. Otherwise we will keep the value 2780 * that is in the list. 2781 * 2782 * Returns: true if all register values were read correctly, 2783 * false if some register was unknown or could not be read. 2784 * Note that we do not stop early on failure -- we will attempt 2785 * reading all registers in the list. 2786 */ 2787 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2788 2789 #define ARM_CPUID_TI915T 0x54029152 2790 #define ARM_CPUID_TI925T 0x54029252 2791 2792 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2793 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2794 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2795 2796 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2797 2798 #define cpu_list arm_cpu_list 2799 2800 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2801 * 2802 * If EL3 is 64-bit: 2803 * + NonSecure EL1 & 0 stage 1 2804 * + NonSecure EL1 & 0 stage 2 2805 * + NonSecure EL2 2806 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2807 * + Secure EL1 & 0 2808 * + Secure EL3 2809 * If EL3 is 32-bit: 2810 * + NonSecure PL1 & 0 stage 1 2811 * + NonSecure PL1 & 0 stage 2 2812 * + NonSecure PL2 2813 * + Secure PL0 2814 * + Secure PL1 2815 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2816 * 2817 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2818 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2819 * because they may differ in access permissions even if the VA->PA map is 2820 * the same 2821 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2822 * translation, which means that we have one mmu_idx that deals with two 2823 * concatenated translation regimes [this sort of combined s1+2 TLB is 2824 * architecturally permitted] 2825 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2826 * handling via the TLB. The only way to do a stage 1 translation without 2827 * the immediate stage 2 translation is via the ATS or AT system insns, 2828 * which can be slow-pathed and always do a page table walk. 2829 * The only use of stage 2 translations is either as part of an s1+2 2830 * lookup or when loading the descriptors during a stage 1 page table walk, 2831 * and in both those cases we don't use the TLB. 2832 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2833 * translation regimes, because they map reasonably well to each other 2834 * and they can't both be active at the same time. 2835 * 5. we want to be able to use the TLB for accesses done as part of a 2836 * stage1 page table walk, rather than having to walk the stage2 page 2837 * table over and over. 2838 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2839 * Never (PAN) bit within PSTATE. 2840 * 7. we fold together the secure and non-secure regimes for A-profile, 2841 * because there are no banked system registers for aarch64, so the 2842 * process of switching between secure and non-secure is 2843 * already heavyweight. 2844 * 2845 * This gives us the following list of cases: 2846 * 2847 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2848 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2849 * EL1 EL1&0 stage 1+2 +PAN 2850 * EL0 EL2&0 2851 * EL2 EL2&0 2852 * EL2 EL2&0 +PAN 2853 * EL2 (aka NS PL2) 2854 * EL3 (aka S PL1) 2855 * Physical (NS & S) 2856 * Stage2 (NS & S) 2857 * 2858 * for a total of 12 different mmu_idx. 2859 * 2860 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2861 * as A profile. They only need to distinguish EL0 and EL1 (and 2862 * EL2 if we ever model a Cortex-R52). 2863 * 2864 * M profile CPUs are rather different as they do not have a true MMU. 2865 * They have the following different MMU indexes: 2866 * User 2867 * Privileged 2868 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2869 * Privileged, execution priority negative (ditto) 2870 * If the CPU supports the v8M Security Extension then there are also: 2871 * Secure User 2872 * Secure Privileged 2873 * Secure User, execution priority negative 2874 * Secure Privileged, execution priority negative 2875 * 2876 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2877 * are not quite the same -- different CPU types (most notably M profile 2878 * vs A/R profile) would like to use MMU indexes with different semantics, 2879 * but since we don't ever need to use all of those in a single CPU we 2880 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2881 * modes + total number of M profile MMU modes". The lower bits of 2882 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2883 * the same for any particular CPU. 2884 * Variables of type ARMMUIdx are always full values, and the core 2885 * index values are in variables of type 'int'. 2886 * 2887 * Our enumeration includes at the end some entries which are not "true" 2888 * mmu_idx values in that they don't have corresponding TLBs and are only 2889 * valid for doing slow path page table walks. 2890 * 2891 * The constant names here are patterned after the general style of the names 2892 * of the AT/ATS operations. 2893 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2894 * For M profile we arrange them to have a bit for priv, a bit for negpri 2895 * and a bit for secure. 2896 */ 2897 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2898 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2899 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2900 2901 /* Meanings of the bits for M profile mmu idx values */ 2902 #define ARM_MMU_IDX_M_PRIV 0x1 2903 #define ARM_MMU_IDX_M_NEGPRI 0x2 2904 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2905 2906 #define ARM_MMU_IDX_TYPE_MASK \ 2907 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2908 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2909 2910 typedef enum ARMMMUIdx { 2911 /* 2912 * A-profile. 2913 */ 2914 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2915 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2916 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2917 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2918 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2919 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2920 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2921 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2922 2923 /* 2924 * Used for second stage of an S12 page table walk, or for descriptor 2925 * loads during first stage of an S1 page table walk. Note that both 2926 * are in use simultaneously for SecureEL2: the security state for 2927 * the S2 ptw is selected by the NS bit from the S1 ptw. 2928 */ 2929 ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A, 2930 ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, 2931 2932 /* TLBs with 1-1 mapping to the physical address spaces. */ 2933 ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, 2934 ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, 2935 ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, 2936 ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, 2937 2938 /* 2939 * These are not allocated TLBs and are used only for AT system 2940 * instructions or for the first stage of an S12 page table walk. 2941 */ 2942 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2943 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2944 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2945 2946 /* 2947 * M-profile. 2948 */ 2949 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2950 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2951 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2952 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2953 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2954 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2955 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2956 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2957 } ARMMMUIdx; 2958 2959 /* 2960 * Bit macros for the core-mmu-index values for each index, 2961 * for use when calling tlb_flush_by_mmuidx() and friends. 2962 */ 2963 #define TO_CORE_BIT(NAME) \ 2964 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2965 2966 typedef enum ARMMMUIdxBit { 2967 TO_CORE_BIT(E10_0), 2968 TO_CORE_BIT(E20_0), 2969 TO_CORE_BIT(E10_1), 2970 TO_CORE_BIT(E10_1_PAN), 2971 TO_CORE_BIT(E2), 2972 TO_CORE_BIT(E20_2), 2973 TO_CORE_BIT(E20_2_PAN), 2974 TO_CORE_BIT(E3), 2975 TO_CORE_BIT(Stage2), 2976 TO_CORE_BIT(Stage2_S), 2977 2978 TO_CORE_BIT(MUser), 2979 TO_CORE_BIT(MPriv), 2980 TO_CORE_BIT(MUserNegPri), 2981 TO_CORE_BIT(MPrivNegPri), 2982 TO_CORE_BIT(MSUser), 2983 TO_CORE_BIT(MSPriv), 2984 TO_CORE_BIT(MSUserNegPri), 2985 TO_CORE_BIT(MSPrivNegPri), 2986 } ARMMMUIdxBit; 2987 2988 #undef TO_CORE_BIT 2989 2990 #define MMU_USER_IDX 0 2991 2992 /* Indexes used when registering address spaces with cpu_address_space_init */ 2993 typedef enum ARMASIdx { 2994 ARMASIdx_NS = 0, 2995 ARMASIdx_S = 1, 2996 ARMASIdx_TagNS = 2, 2997 ARMASIdx_TagS = 3, 2998 } ARMASIdx; 2999 3000 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 3001 { 3002 /* Assert the relative order of the physical mmu indexes. */ 3003 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 3004 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 3005 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 3006 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 3007 3008 return ARMMMUIdx_Phys_S + space; 3009 } 3010 3011 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 3012 { 3013 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 3014 return idx - ARMMMUIdx_Phys_S; 3015 } 3016 3017 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3018 { 3019 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3020 * CSSELR is RAZ/WI. 3021 */ 3022 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3023 } 3024 3025 static inline bool arm_sctlr_b(CPUARMState *env) 3026 { 3027 return 3028 /* We need not implement SCTLR.ITD in user-mode emulation, so 3029 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3030 * This lets people run BE32 binaries with "-cpu any". 3031 */ 3032 #ifndef CONFIG_USER_ONLY 3033 !arm_feature(env, ARM_FEATURE_V7) && 3034 #endif 3035 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3036 } 3037 3038 uint64_t arm_sctlr(CPUARMState *env, int el); 3039 3040 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3041 bool sctlr_b) 3042 { 3043 #ifdef CONFIG_USER_ONLY 3044 /* 3045 * In system mode, BE32 is modelled in line with the 3046 * architecture (as word-invariant big-endianness), where loads 3047 * and stores are done little endian but from addresses which 3048 * are adjusted by XORing with the appropriate constant. So the 3049 * endianness to use for the raw data access is not affected by 3050 * SCTLR.B. 3051 * In user mode, however, we model BE32 as byte-invariant 3052 * big-endianness (because user-only code cannot tell the 3053 * difference), and so we need to use a data access endianness 3054 * that depends on SCTLR.B. 3055 */ 3056 if (sctlr_b) { 3057 return true; 3058 } 3059 #endif 3060 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3061 return env->uncached_cpsr & CPSR_E; 3062 } 3063 3064 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3065 { 3066 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3067 } 3068 3069 /* Return true if the processor is in big-endian mode. */ 3070 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3071 { 3072 if (!is_a64(env)) { 3073 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3074 } else { 3075 int cur_el = arm_current_el(env); 3076 uint64_t sctlr = arm_sctlr(env, cur_el); 3077 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3078 } 3079 } 3080 3081 #include "exec/cpu-all.h" 3082 3083 /* 3084 * We have more than 32-bits worth of state per TB, so we split the data 3085 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3086 * We collect these two parts in CPUARMTBFlags where they are named 3087 * flags and flags2 respectively. 3088 * 3089 * The flags that are shared between all execution modes, TBFLAG_ANY, 3090 * are stored in flags. The flags that are specific to a given mode 3091 * are stores in flags2. Since cs_base is sized on the configured 3092 * address size, flags2 always has 64-bits for A64, and a minimum of 3093 * 32-bits for A32 and M32. 3094 * 3095 * The bits for 32-bit A-profile and M-profile partially overlap: 3096 * 3097 * 31 23 11 10 0 3098 * +-------------+----------+----------------+ 3099 * | | | TBFLAG_A32 | 3100 * | TBFLAG_AM32 | +-----+----------+ 3101 * | | |TBFLAG_M32| 3102 * +-------------+----------------+----------+ 3103 * 31 23 6 5 0 3104 * 3105 * Unless otherwise noted, these bits are cached in env->hflags. 3106 */ 3107 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3108 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3109 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3110 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3111 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3112 /* Target EL if we take a floating-point-disabled exception */ 3113 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3114 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3115 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3116 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3117 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3118 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3119 3120 /* 3121 * Bit usage when in AArch32 state, both A- and M-profile. 3122 */ 3123 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3124 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3125 3126 /* 3127 * Bit usage when in AArch32 state, for A-profile only. 3128 */ 3129 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3130 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3131 /* 3132 * We store the bottom two bits of the CPAR as TB flags and handle 3133 * checks on the other bits at runtime. This shares the same bits as 3134 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3135 * Not cached, because VECLEN+VECSTRIDE are not cached. 3136 */ 3137 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3138 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3139 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3140 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3141 /* 3142 * Indicates whether cp register reads and writes by guest code should access 3143 * the secure or nonsecure bank of banked registers; note that this is not 3144 * the same thing as the current security state of the processor! 3145 */ 3146 FIELD(TBFLAG_A32, NS, 10, 1) 3147 /* 3148 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3149 * This requires an SME trap from AArch32 mode when using NEON. 3150 */ 3151 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3152 3153 /* 3154 * Bit usage when in AArch32 state, for M-profile only. 3155 */ 3156 /* Handler (ie not Thread) mode */ 3157 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3158 /* Whether we should generate stack-limit checks */ 3159 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3160 /* Set if FPCCR.LSPACT is set */ 3161 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3162 /* Set if we must create a new FP context */ 3163 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3164 /* Set if FPCCR.S does not match current security state */ 3165 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3166 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3167 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3168 /* Set if in secure mode */ 3169 FIELD(TBFLAG_M32, SECURE, 6, 1) 3170 3171 /* 3172 * Bit usage when in AArch64 state 3173 */ 3174 FIELD(TBFLAG_A64, TBII, 0, 2) 3175 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3176 /* The current vector length, either NVL or SVL. */ 3177 FIELD(TBFLAG_A64, VL, 4, 4) 3178 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3179 FIELD(TBFLAG_A64, BT, 9, 1) 3180 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3181 FIELD(TBFLAG_A64, TBID, 12, 2) 3182 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3183 FIELD(TBFLAG_A64, ATA, 15, 1) 3184 FIELD(TBFLAG_A64, TCMA, 16, 2) 3185 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3186 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3187 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3188 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3189 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3190 FIELD(TBFLAG_A64, SVL, 24, 4) 3191 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3192 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3193 FIELD(TBFLAG_A64, FGT_ERET, 29, 1) 3194 FIELD(TBFLAG_A64, NAA, 30, 1) 3195 FIELD(TBFLAG_A64, ATA0, 31, 1) 3196 3197 /* 3198 * Helpers for using the above. 3199 */ 3200 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3201 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3202 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3203 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3204 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3205 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3206 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3207 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3208 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3209 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3210 3211 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3212 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3213 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3214 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3215 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3216 3217 /** 3218 * cpu_mmu_index: 3219 * @env: The cpu environment 3220 * @ifetch: True for code access, false for data access. 3221 * 3222 * Return the core mmu index for the current translation regime. 3223 * This function is used by generic TCG code paths. 3224 */ 3225 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3226 { 3227 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3228 } 3229 3230 /** 3231 * sve_vq 3232 * @env: the cpu context 3233 * 3234 * Return the VL cached within env->hflags, in units of quadwords. 3235 */ 3236 static inline int sve_vq(CPUARMState *env) 3237 { 3238 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3239 } 3240 3241 /** 3242 * sme_vq 3243 * @env: the cpu context 3244 * 3245 * Return the SVL cached within env->hflags, in units of quadwords. 3246 */ 3247 static inline int sme_vq(CPUARMState *env) 3248 { 3249 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3250 } 3251 3252 static inline bool bswap_code(bool sctlr_b) 3253 { 3254 #ifdef CONFIG_USER_ONLY 3255 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3256 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3257 * would also end up as a mixed-endian mode with BE code, LE data. 3258 */ 3259 return TARGET_BIG_ENDIAN ^ sctlr_b; 3260 #else 3261 /* All code access in ARM is little endian, and there are no loaders 3262 * doing swaps that need to be reversed 3263 */ 3264 return 0; 3265 #endif 3266 } 3267 3268 #ifdef CONFIG_USER_ONLY 3269 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3270 { 3271 return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); 3272 } 3273 #endif 3274 3275 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, 3276 uint64_t *cs_base, uint32_t *flags); 3277 3278 enum { 3279 QEMU_PSCI_CONDUIT_DISABLED = 0, 3280 QEMU_PSCI_CONDUIT_SMC = 1, 3281 QEMU_PSCI_CONDUIT_HVC = 2, 3282 }; 3283 3284 #ifndef CONFIG_USER_ONLY 3285 /* Return the address space index to use for a memory access */ 3286 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3287 { 3288 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3289 } 3290 3291 /* Return the AddressSpace to use for a memory access 3292 * (which depends on whether the access is S or NS, and whether 3293 * the board gave us a separate AddressSpace for S accesses). 3294 */ 3295 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3296 { 3297 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3298 } 3299 #endif 3300 3301 /** 3302 * arm_register_pre_el_change_hook: 3303 * Register a hook function which will be called immediately before this 3304 * CPU changes exception level or mode. The hook function will be 3305 * passed a pointer to the ARMCPU and the opaque data pointer passed 3306 * to this function when the hook was registered. 3307 * 3308 * Note that if a pre-change hook is called, any registered post-change hooks 3309 * are guaranteed to subsequently be called. 3310 */ 3311 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3312 void *opaque); 3313 /** 3314 * arm_register_el_change_hook: 3315 * Register a hook function which will be called immediately after this 3316 * CPU changes exception level or mode. The hook function will be 3317 * passed a pointer to the ARMCPU and the opaque data pointer passed 3318 * to this function when the hook was registered. 3319 * 3320 * Note that any registered hooks registered here are guaranteed to be called 3321 * if pre-change hooks have been. 3322 */ 3323 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3324 *opaque); 3325 3326 /** 3327 * arm_rebuild_hflags: 3328 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3329 */ 3330 void arm_rebuild_hflags(CPUARMState *env); 3331 3332 /** 3333 * aa32_vfp_dreg: 3334 * Return a pointer to the Dn register within env in 32-bit mode. 3335 */ 3336 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3337 { 3338 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3339 } 3340 3341 /** 3342 * aa32_vfp_qreg: 3343 * Return a pointer to the Qn register within env in 32-bit mode. 3344 */ 3345 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3346 { 3347 return &env->vfp.zregs[regno].d[0]; 3348 } 3349 3350 /** 3351 * aa64_vfp_qreg: 3352 * Return a pointer to the Qn register within env in 64-bit mode. 3353 */ 3354 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3355 { 3356 return &env->vfp.zregs[regno].d[0]; 3357 } 3358 3359 /* Shared between translate-sve.c and sve_helper.c. */ 3360 extern const uint64_t pred_esz_masks[5]; 3361 3362 /* 3363 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3364 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3365 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3366 */ 3367 #define PAGE_BTI PAGE_TARGET_1 3368 #define PAGE_MTE PAGE_TARGET_2 3369 #define PAGE_TARGET_STICKY PAGE_MTE 3370 3371 /* We associate one allocation tag per 16 bytes, the minimum. */ 3372 #define LOG2_TAG_GRANULE 4 3373 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3374 3375 #ifdef CONFIG_USER_ONLY 3376 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3377 #endif 3378 3379 #ifdef TARGET_TAGGED_ADDRESSES 3380 /** 3381 * cpu_untagged_addr: 3382 * @cs: CPU context 3383 * @x: tagged address 3384 * 3385 * Remove any address tag from @x. This is explicitly related to the 3386 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3387 * 3388 * There should be a better place to put this, but we need this in 3389 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3390 */ 3391 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3392 { 3393 ARMCPU *cpu = ARM_CPU(cs); 3394 if (cpu->env.tagged_addr_enable) { 3395 /* 3396 * TBI is enabled for userspace but not kernelspace addresses. 3397 * Only clear the tag if bit 55 is clear. 3398 */ 3399 x &= sextract64(x, 0, 56); 3400 } 3401 return x; 3402 } 3403 #endif 3404 3405 #endif 3406