1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 #include "cpu-qom.h" 26 #include "exec/cpu-defs.h" 27 28 /* ARM processors have a weak memory model */ 29 #define TCG_GUEST_DEFAULT_MO (0) 30 31 #define EXCP_UDEF 1 /* undefined instruction */ 32 #define EXCP_SWI 2 /* software interrupt */ 33 #define EXCP_PREFETCH_ABORT 3 34 #define EXCP_DATA_ABORT 4 35 #define EXCP_IRQ 5 36 #define EXCP_FIQ 6 37 #define EXCP_BKPT 7 38 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 39 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 40 #define EXCP_HVC 11 /* HyperVisor Call */ 41 #define EXCP_HYP_TRAP 12 42 #define EXCP_SMC 13 /* Secure Monitor Call */ 43 #define EXCP_VIRQ 14 44 #define EXCP_VFIQ 15 45 #define EXCP_SEMIHOST 16 /* semihosting call */ 46 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 47 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 48 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 49 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 50 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 51 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 52 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 53 54 #define ARMV7M_EXCP_RESET 1 55 #define ARMV7M_EXCP_NMI 2 56 #define ARMV7M_EXCP_HARD 3 57 #define ARMV7M_EXCP_MEM 4 58 #define ARMV7M_EXCP_BUS 5 59 #define ARMV7M_EXCP_USAGE 6 60 #define ARMV7M_EXCP_SECURE 7 61 #define ARMV7M_EXCP_SVC 11 62 #define ARMV7M_EXCP_DEBUG 12 63 #define ARMV7M_EXCP_PENDSV 14 64 #define ARMV7M_EXCP_SYSTICK 15 65 66 /* For M profile, some registers are banked secure vs non-secure; 67 * these are represented as a 2-element array where the first element 68 * is the non-secure copy and the second is the secure copy. 69 * When the CPU does not have implement the security extension then 70 * only the first element is used. 71 * This means that the copy for the current security state can be 72 * accessed via env->registerfield[env->v7m.secure] (whether the security 73 * extension is implemented or not). 74 */ 75 enum { 76 M_REG_NS = 0, 77 M_REG_S = 1, 78 M_REG_NUM_BANKS = 2, 79 }; 80 81 /* ARM-specific interrupt pending bits. */ 82 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 83 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 84 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 85 86 /* The usual mapping for an AArch64 system register to its AArch32 87 * counterpart is for the 32 bit world to have access to the lower 88 * half only (with writes leaving the upper half untouched). It's 89 * therefore useful to be able to pass TCG the offset of the least 90 * significant half of a uint64_t struct member. 91 */ 92 #ifdef HOST_WORDS_BIGENDIAN 93 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 94 #define offsetofhigh32(S, M) offsetof(S, M) 95 #else 96 #define offsetoflow32(S, M) offsetof(S, M) 97 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 98 #endif 99 100 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 101 #define ARM_CPU_IRQ 0 102 #define ARM_CPU_FIQ 1 103 #define ARM_CPU_VIRQ 2 104 #define ARM_CPU_VFIQ 3 105 106 /* ARM-specific extra insn start words: 107 * 1: Conditional execution bits 108 * 2: Partial exception syndrome for data aborts 109 */ 110 #define TARGET_INSN_START_EXTRA_WORDS 2 111 112 /* The 2nd extra word holding syndrome info for data aborts does not use 113 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 114 * help the sleb128 encoder do a better job. 115 * When restoring the CPU state, we shift it back up. 116 */ 117 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 118 #define ARM_INSN_START_WORD2_SHIFT 14 119 120 /* We currently assume float and double are IEEE single and double 121 precision respectively. 122 Doing runtime conversions is tricky because VFP registers may contain 123 integer values (eg. as the result of a FTOSI instruction). 124 s<2n> maps to the least significant half of d<n> 125 s<2n+1> maps to the most significant half of d<n> 126 */ 127 128 /** 129 * DynamicGDBXMLInfo: 130 * @desc: Contains the XML descriptions. 131 * @num_cpregs: Number of the Coprocessor registers seen by GDB. 132 * @cpregs_keys: Array that contains the corresponding Key of 133 * a given cpreg with the same order of the cpreg in the XML description. 134 */ 135 typedef struct DynamicGDBXMLInfo { 136 char *desc; 137 int num_cpregs; 138 uint32_t *cpregs_keys; 139 } DynamicGDBXMLInfo; 140 141 /* CPU state for each instance of a generic timer (in cp15 c14) */ 142 typedef struct ARMGenericTimer { 143 uint64_t cval; /* Timer CompareValue register */ 144 uint64_t ctl; /* Timer Control register */ 145 } ARMGenericTimer; 146 147 #define GTIMER_PHYS 0 148 #define GTIMER_VIRT 1 149 #define GTIMER_HYP 2 150 #define GTIMER_SEC 3 151 #define GTIMER_HYPVIRT 4 152 #define NUM_GTIMERS 5 153 154 typedef struct { 155 uint64_t raw_tcr; 156 uint32_t mask; 157 uint32_t base_mask; 158 } TCR; 159 160 /* Define a maximum sized vector register. 161 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 162 * For 64-bit, this is a 2048-bit SVE register. 163 * 164 * Note that the mapping between S, D, and Q views of the register bank 165 * differs between AArch64 and AArch32. 166 * In AArch32: 167 * Qn = regs[n].d[1]:regs[n].d[0] 168 * Dn = regs[n / 2].d[n & 1] 169 * Sn = regs[n / 4].d[n % 4 / 2], 170 * bits 31..0 for even n, and bits 63..32 for odd n 171 * (and regs[16] to regs[31] are inaccessible) 172 * In AArch64: 173 * Zn = regs[n].d[*] 174 * Qn = regs[n].d[1]:regs[n].d[0] 175 * Dn = regs[n].d[0] 176 * Sn = regs[n].d[0] bits 31..0 177 * Hn = regs[n].d[0] bits 15..0 178 * 179 * This corresponds to the architecturally defined mapping between 180 * the two execution states, and means we do not need to explicitly 181 * map these registers when changing states. 182 * 183 * Align the data for use with TCG host vector operations. 184 */ 185 186 #ifdef TARGET_AARCH64 187 # define ARM_MAX_VQ 16 188 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 189 #else 190 # define ARM_MAX_VQ 1 191 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 192 #endif 193 194 typedef struct ARMVectorReg { 195 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 196 } ARMVectorReg; 197 198 #ifdef TARGET_AARCH64 199 /* In AArch32 mode, predicate registers do not exist at all. */ 200 typedef struct ARMPredicateReg { 201 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 202 } ARMPredicateReg; 203 204 /* In AArch32 mode, PAC keys do not exist at all. */ 205 typedef struct ARMPACKey { 206 uint64_t lo, hi; 207 } ARMPACKey; 208 #endif 209 210 211 typedef struct CPUARMState { 212 /* Regs for current mode. */ 213 uint32_t regs[16]; 214 215 /* 32/64 switch only happens when taking and returning from 216 * exceptions so the overlap semantics are taken care of then 217 * instead of having a complicated union. 218 */ 219 /* Regs for A64 mode. */ 220 uint64_t xregs[32]; 221 uint64_t pc; 222 /* PSTATE isn't an architectural register for ARMv8. However, it is 223 * convenient for us to assemble the underlying state into a 32 bit format 224 * identical to the architectural format used for the SPSR. (This is also 225 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 226 * 'pstate' register are.) Of the PSTATE bits: 227 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 228 * semantics as for AArch32, as described in the comments on each field) 229 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 230 * DAIF (exception masks) are kept in env->daif 231 * BTYPE is kept in env->btype 232 * all other bits are stored in their correct places in env->pstate 233 */ 234 uint32_t pstate; 235 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 236 237 /* Cached TBFLAGS state. See below for which bits are included. */ 238 uint32_t hflags; 239 240 /* Frequently accessed CPSR bits are stored separately for efficiency. 241 This contains all the other bits. Use cpsr_{read,write} to access 242 the whole CPSR. */ 243 uint32_t uncached_cpsr; 244 uint32_t spsr; 245 246 /* Banked registers. */ 247 uint64_t banked_spsr[8]; 248 uint32_t banked_r13[8]; 249 uint32_t banked_r14[8]; 250 251 /* These hold r8-r12. */ 252 uint32_t usr_regs[5]; 253 uint32_t fiq_regs[5]; 254 255 /* cpsr flag cache for faster execution */ 256 uint32_t CF; /* 0 or 1 */ 257 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 258 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 259 uint32_t ZF; /* Z set if zero. */ 260 uint32_t QF; /* 0 or 1 */ 261 uint32_t GE; /* cpsr[19:16] */ 262 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 263 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 264 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 265 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 266 267 uint64_t elr_el[4]; /* AArch64 exception link regs */ 268 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 269 270 /* System control coprocessor (cp15) */ 271 struct { 272 uint32_t c0_cpuid; 273 union { /* Cache size selection */ 274 struct { 275 uint64_t _unused_csselr0; 276 uint64_t csselr_ns; 277 uint64_t _unused_csselr1; 278 uint64_t csselr_s; 279 }; 280 uint64_t csselr_el[4]; 281 }; 282 union { /* System control register. */ 283 struct { 284 uint64_t _unused_sctlr; 285 uint64_t sctlr_ns; 286 uint64_t hsctlr; 287 uint64_t sctlr_s; 288 }; 289 uint64_t sctlr_el[4]; 290 }; 291 uint64_t cpacr_el1; /* Architectural feature access control register */ 292 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 293 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 294 uint64_t sder; /* Secure debug enable register. */ 295 uint32_t nsacr; /* Non-secure access control register. */ 296 union { /* MMU translation table base 0. */ 297 struct { 298 uint64_t _unused_ttbr0_0; 299 uint64_t ttbr0_ns; 300 uint64_t _unused_ttbr0_1; 301 uint64_t ttbr0_s; 302 }; 303 uint64_t ttbr0_el[4]; 304 }; 305 union { /* MMU translation table base 1. */ 306 struct { 307 uint64_t _unused_ttbr1_0; 308 uint64_t ttbr1_ns; 309 uint64_t _unused_ttbr1_1; 310 uint64_t ttbr1_s; 311 }; 312 uint64_t ttbr1_el[4]; 313 }; 314 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 315 /* MMU translation table base control. */ 316 TCR tcr_el[4]; 317 TCR vtcr_el2; /* Virtualization Translation Control. */ 318 uint32_t c2_data; /* MPU data cacheable bits. */ 319 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 320 union { /* MMU domain access control register 321 * MPU write buffer control. 322 */ 323 struct { 324 uint64_t dacr_ns; 325 uint64_t dacr_s; 326 }; 327 struct { 328 uint64_t dacr32_el2; 329 }; 330 }; 331 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 332 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 333 uint64_t hcr_el2; /* Hypervisor configuration register */ 334 uint64_t scr_el3; /* Secure configuration register. */ 335 union { /* Fault status registers. */ 336 struct { 337 uint64_t ifsr_ns; 338 uint64_t ifsr_s; 339 }; 340 struct { 341 uint64_t ifsr32_el2; 342 }; 343 }; 344 union { 345 struct { 346 uint64_t _unused_dfsr; 347 uint64_t dfsr_ns; 348 uint64_t hsr; 349 uint64_t dfsr_s; 350 }; 351 uint64_t esr_el[4]; 352 }; 353 uint32_t c6_region[8]; /* MPU base/size registers. */ 354 union { /* Fault address registers. */ 355 struct { 356 uint64_t _unused_far0; 357 #ifdef HOST_WORDS_BIGENDIAN 358 uint32_t ifar_ns; 359 uint32_t dfar_ns; 360 uint32_t ifar_s; 361 uint32_t dfar_s; 362 #else 363 uint32_t dfar_ns; 364 uint32_t ifar_ns; 365 uint32_t dfar_s; 366 uint32_t ifar_s; 367 #endif 368 uint64_t _unused_far3; 369 }; 370 uint64_t far_el[4]; 371 }; 372 uint64_t hpfar_el2; 373 uint64_t hstr_el2; 374 union { /* Translation result. */ 375 struct { 376 uint64_t _unused_par_0; 377 uint64_t par_ns; 378 uint64_t _unused_par_1; 379 uint64_t par_s; 380 }; 381 uint64_t par_el[4]; 382 }; 383 384 uint32_t c9_insn; /* Cache lockdown registers. */ 385 uint32_t c9_data; 386 uint64_t c9_pmcr; /* performance monitor control register */ 387 uint64_t c9_pmcnten; /* perf monitor counter enables */ 388 uint64_t c9_pmovsr; /* perf monitor overflow status */ 389 uint64_t c9_pmuserenr; /* perf monitor user enable */ 390 uint64_t c9_pmselr; /* perf monitor counter selection register */ 391 uint64_t c9_pminten; /* perf monitor interrupt enables */ 392 union { /* Memory attribute redirection */ 393 struct { 394 #ifdef HOST_WORDS_BIGENDIAN 395 uint64_t _unused_mair_0; 396 uint32_t mair1_ns; 397 uint32_t mair0_ns; 398 uint64_t _unused_mair_1; 399 uint32_t mair1_s; 400 uint32_t mair0_s; 401 #else 402 uint64_t _unused_mair_0; 403 uint32_t mair0_ns; 404 uint32_t mair1_ns; 405 uint64_t _unused_mair_1; 406 uint32_t mair0_s; 407 uint32_t mair1_s; 408 #endif 409 }; 410 uint64_t mair_el[4]; 411 }; 412 union { /* vector base address register */ 413 struct { 414 uint64_t _unused_vbar; 415 uint64_t vbar_ns; 416 uint64_t hvbar; 417 uint64_t vbar_s; 418 }; 419 uint64_t vbar_el[4]; 420 }; 421 uint32_t mvbar; /* (monitor) vector base address register */ 422 struct { /* FCSE PID. */ 423 uint32_t fcseidr_ns; 424 uint32_t fcseidr_s; 425 }; 426 union { /* Context ID. */ 427 struct { 428 uint64_t _unused_contextidr_0; 429 uint64_t contextidr_ns; 430 uint64_t _unused_contextidr_1; 431 uint64_t contextidr_s; 432 }; 433 uint64_t contextidr_el[4]; 434 }; 435 union { /* User RW Thread register. */ 436 struct { 437 uint64_t tpidrurw_ns; 438 uint64_t tpidrprw_ns; 439 uint64_t htpidr; 440 uint64_t _tpidr_el3; 441 }; 442 uint64_t tpidr_el[4]; 443 }; 444 /* The secure banks of these registers don't map anywhere */ 445 uint64_t tpidrurw_s; 446 uint64_t tpidrprw_s; 447 uint64_t tpidruro_s; 448 449 union { /* User RO Thread register. */ 450 uint64_t tpidruro_ns; 451 uint64_t tpidrro_el[1]; 452 }; 453 uint64_t c14_cntfrq; /* Counter Frequency register */ 454 uint64_t c14_cntkctl; /* Timer Control register */ 455 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 456 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 457 ARMGenericTimer c14_timer[NUM_GTIMERS]; 458 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 459 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 460 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 461 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 462 uint32_t c15_threadid; /* TI debugger thread-ID. */ 463 uint32_t c15_config_base_address; /* SCU base address. */ 464 uint32_t c15_diagnostic; /* diagnostic register */ 465 uint32_t c15_power_diagnostic; 466 uint32_t c15_power_control; /* power control */ 467 uint64_t dbgbvr[16]; /* breakpoint value registers */ 468 uint64_t dbgbcr[16]; /* breakpoint control registers */ 469 uint64_t dbgwvr[16]; /* watchpoint value registers */ 470 uint64_t dbgwcr[16]; /* watchpoint control registers */ 471 uint64_t mdscr_el1; 472 uint64_t oslsr_el1; /* OS Lock Status */ 473 uint64_t mdcr_el2; 474 uint64_t mdcr_el3; 475 /* Stores the architectural value of the counter *the last time it was 476 * updated* by pmccntr_op_start. Accesses should always be surrounded 477 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 478 * architecturally-correct value is being read/set. 479 */ 480 uint64_t c15_ccnt; 481 /* Stores the delta between the architectural value and the underlying 482 * cycle count during normal operation. It is used to update c15_ccnt 483 * to be the correct architectural value before accesses. During 484 * accesses, c15_ccnt_delta contains the underlying count being used 485 * for the access, after which it reverts to the delta value in 486 * pmccntr_op_finish. 487 */ 488 uint64_t c15_ccnt_delta; 489 uint64_t c14_pmevcntr[31]; 490 uint64_t c14_pmevcntr_delta[31]; 491 uint64_t c14_pmevtyper[31]; 492 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 493 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 494 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 495 } cp15; 496 497 struct { 498 /* M profile has up to 4 stack pointers: 499 * a Main Stack Pointer and a Process Stack Pointer for each 500 * of the Secure and Non-Secure states. (If the CPU doesn't support 501 * the security extension then it has only two SPs.) 502 * In QEMU we always store the currently active SP in regs[13], 503 * and the non-active SP for the current security state in 504 * v7m.other_sp. The stack pointers for the inactive security state 505 * are stored in other_ss_msp and other_ss_psp. 506 * switch_v7m_security_state() is responsible for rearranging them 507 * when we change security state. 508 */ 509 uint32_t other_sp; 510 uint32_t other_ss_msp; 511 uint32_t other_ss_psp; 512 uint32_t vecbase[M_REG_NUM_BANKS]; 513 uint32_t basepri[M_REG_NUM_BANKS]; 514 uint32_t control[M_REG_NUM_BANKS]; 515 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 516 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 517 uint32_t hfsr; /* HardFault Status */ 518 uint32_t dfsr; /* Debug Fault Status Register */ 519 uint32_t sfsr; /* Secure Fault Status Register */ 520 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 521 uint32_t bfar; /* BusFault Address */ 522 uint32_t sfar; /* Secure Fault Address Register */ 523 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 524 int exception; 525 uint32_t primask[M_REG_NUM_BANKS]; 526 uint32_t faultmask[M_REG_NUM_BANKS]; 527 uint32_t aircr; /* only holds r/w state if security extn implemented */ 528 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 529 uint32_t csselr[M_REG_NUM_BANKS]; 530 uint32_t scr[M_REG_NUM_BANKS]; 531 uint32_t msplim[M_REG_NUM_BANKS]; 532 uint32_t psplim[M_REG_NUM_BANKS]; 533 uint32_t fpcar[M_REG_NUM_BANKS]; 534 uint32_t fpccr[M_REG_NUM_BANKS]; 535 uint32_t fpdscr[M_REG_NUM_BANKS]; 536 uint32_t cpacr[M_REG_NUM_BANKS]; 537 uint32_t nsacr; 538 } v7m; 539 540 /* Information associated with an exception about to be taken: 541 * code which raises an exception must set cs->exception_index and 542 * the relevant parts of this structure; the cpu_do_interrupt function 543 * will then set the guest-visible registers as part of the exception 544 * entry process. 545 */ 546 struct { 547 uint32_t syndrome; /* AArch64 format syndrome register */ 548 uint32_t fsr; /* AArch32 format fault status register info */ 549 uint64_t vaddress; /* virtual addr associated with exception, if any */ 550 uint32_t target_el; /* EL the exception should be targeted for */ 551 /* If we implement EL2 we will also need to store information 552 * about the intermediate physical address for stage 2 faults. 553 */ 554 } exception; 555 556 /* Information associated with an SError */ 557 struct { 558 uint8_t pending; 559 uint8_t has_esr; 560 uint64_t esr; 561 } serror; 562 563 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 564 uint32_t irq_line_state; 565 566 /* Thumb-2 EE state. */ 567 uint32_t teecr; 568 uint32_t teehbr; 569 570 /* VFP coprocessor state. */ 571 struct { 572 ARMVectorReg zregs[32]; 573 574 #ifdef TARGET_AARCH64 575 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 576 #define FFR_PRED_NUM 16 577 ARMPredicateReg pregs[17]; 578 /* Scratch space for aa64 sve predicate temporary. */ 579 ARMPredicateReg preg_tmp; 580 #endif 581 582 /* We store these fpcsr fields separately for convenience. */ 583 uint32_t qc[4] QEMU_ALIGNED(16); 584 int vec_len; 585 int vec_stride; 586 587 uint32_t xregs[16]; 588 589 /* Scratch space for aa32 neon expansion. */ 590 uint32_t scratch[8]; 591 592 /* There are a number of distinct float control structures: 593 * 594 * fp_status: is the "normal" fp status. 595 * fp_status_fp16: used for half-precision calculations 596 * standard_fp_status : the ARM "Standard FPSCR Value" 597 * 598 * Half-precision operations are governed by a separate 599 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 600 * status structure to control this. 601 * 602 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 603 * round-to-nearest and is used by any operations (generally 604 * Neon) which the architecture defines as controlled by the 605 * standard FPSCR value rather than the FPSCR. 606 * 607 * To avoid having to transfer exception bits around, we simply 608 * say that the FPSCR cumulative exception flags are the logical 609 * OR of the flags in the three fp statuses. This relies on the 610 * only thing which needs to read the exception flags being 611 * an explicit FPSCR read. 612 */ 613 float_status fp_status; 614 float_status fp_status_f16; 615 float_status standard_fp_status; 616 617 /* ZCR_EL[1-3] */ 618 uint64_t zcr_el[4]; 619 } vfp; 620 uint64_t exclusive_addr; 621 uint64_t exclusive_val; 622 uint64_t exclusive_high; 623 624 /* iwMMXt coprocessor state. */ 625 struct { 626 uint64_t regs[16]; 627 uint64_t val; 628 629 uint32_t cregs[16]; 630 } iwmmxt; 631 632 #ifdef TARGET_AARCH64 633 struct { 634 ARMPACKey apia; 635 ARMPACKey apib; 636 ARMPACKey apda; 637 ARMPACKey apdb; 638 ARMPACKey apga; 639 } keys; 640 #endif 641 642 #if defined(CONFIG_USER_ONLY) 643 /* For usermode syscall translation. */ 644 int eabi; 645 #endif 646 647 struct CPUBreakpoint *cpu_breakpoint[16]; 648 struct CPUWatchpoint *cpu_watchpoint[16]; 649 650 /* Fields up to this point are cleared by a CPU reset */ 651 struct {} end_reset_fields; 652 653 /* Fields after this point are preserved across CPU reset. */ 654 655 /* Internal CPU feature flags. */ 656 uint64_t features; 657 658 /* PMSAv7 MPU */ 659 struct { 660 uint32_t *drbar; 661 uint32_t *drsr; 662 uint32_t *dracr; 663 uint32_t rnr[M_REG_NUM_BANKS]; 664 } pmsav7; 665 666 /* PMSAv8 MPU */ 667 struct { 668 /* The PMSAv8 implementation also shares some PMSAv7 config 669 * and state: 670 * pmsav7.rnr (region number register) 671 * pmsav7_dregion (number of configured regions) 672 */ 673 uint32_t *rbar[M_REG_NUM_BANKS]; 674 uint32_t *rlar[M_REG_NUM_BANKS]; 675 uint32_t mair0[M_REG_NUM_BANKS]; 676 uint32_t mair1[M_REG_NUM_BANKS]; 677 } pmsav8; 678 679 /* v8M SAU */ 680 struct { 681 uint32_t *rbar; 682 uint32_t *rlar; 683 uint32_t rnr; 684 uint32_t ctrl; 685 } sau; 686 687 void *nvic; 688 const struct arm_boot_info *boot_info; 689 /* Store GICv3CPUState to access from this struct */ 690 void *gicv3state; 691 } CPUARMState; 692 693 /** 694 * ARMELChangeHookFn: 695 * type of a function which can be registered via arm_register_el_change_hook() 696 * to get callbacks when the CPU changes its exception level or mode. 697 */ 698 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 699 typedef struct ARMELChangeHook ARMELChangeHook; 700 struct ARMELChangeHook { 701 ARMELChangeHookFn *hook; 702 void *opaque; 703 QLIST_ENTRY(ARMELChangeHook) node; 704 }; 705 706 /* These values map onto the return values for 707 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 708 typedef enum ARMPSCIState { 709 PSCI_ON = 0, 710 PSCI_OFF = 1, 711 PSCI_ON_PENDING = 2 712 } ARMPSCIState; 713 714 typedef struct ARMISARegisters ARMISARegisters; 715 716 /** 717 * ARMCPU: 718 * @env: #CPUARMState 719 * 720 * An ARM CPU core. 721 */ 722 struct ARMCPU { 723 /*< private >*/ 724 CPUState parent_obj; 725 /*< public >*/ 726 727 CPUNegativeOffsetState neg; 728 CPUARMState env; 729 730 /* Coprocessor information */ 731 GHashTable *cp_regs; 732 /* For marshalling (mostly coprocessor) register state between the 733 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 734 * we use these arrays. 735 */ 736 /* List of register indexes managed via these arrays; (full KVM style 737 * 64 bit indexes, not CPRegInfo 32 bit indexes) 738 */ 739 uint64_t *cpreg_indexes; 740 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 741 uint64_t *cpreg_values; 742 /* Length of the indexes, values, reset_values arrays */ 743 int32_t cpreg_array_len; 744 /* These are used only for migration: incoming data arrives in 745 * these fields and is sanity checked in post_load before copying 746 * to the working data structures above. 747 */ 748 uint64_t *cpreg_vmstate_indexes; 749 uint64_t *cpreg_vmstate_values; 750 int32_t cpreg_vmstate_array_len; 751 752 DynamicGDBXMLInfo dyn_xml; 753 754 /* Timers used by the generic (architected) timer */ 755 QEMUTimer *gt_timer[NUM_GTIMERS]; 756 /* 757 * Timer used by the PMU. Its state is restored after migration by 758 * pmu_op_finish() - it does not need other handling during migration 759 */ 760 QEMUTimer *pmu_timer; 761 /* GPIO outputs for generic timer */ 762 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 763 /* GPIO output for GICv3 maintenance interrupt signal */ 764 qemu_irq gicv3_maintenance_interrupt; 765 /* GPIO output for the PMU interrupt */ 766 qemu_irq pmu_interrupt; 767 768 /* MemoryRegion to use for secure physical accesses */ 769 MemoryRegion *secure_memory; 770 771 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 772 Object *idau; 773 774 /* 'compatible' string for this CPU for Linux device trees */ 775 const char *dtb_compatible; 776 777 /* PSCI version for this CPU 778 * Bits[31:16] = Major Version 779 * Bits[15:0] = Minor Version 780 */ 781 uint32_t psci_version; 782 783 /* Should CPU start in PSCI powered-off state? */ 784 bool start_powered_off; 785 786 /* Current power state, access guarded by BQL */ 787 ARMPSCIState power_state; 788 789 /* CPU has virtualization extension */ 790 bool has_el2; 791 /* CPU has security extension */ 792 bool has_el3; 793 /* CPU has PMU (Performance Monitor Unit) */ 794 bool has_pmu; 795 /* CPU has VFP */ 796 bool has_vfp; 797 /* CPU has Neon */ 798 bool has_neon; 799 /* CPU has M-profile DSP extension */ 800 bool has_dsp; 801 802 /* CPU has memory protection unit */ 803 bool has_mpu; 804 /* PMSAv7 MPU number of supported regions */ 805 uint32_t pmsav7_dregion; 806 /* v8M SAU number of supported regions */ 807 uint32_t sau_sregion; 808 809 /* PSCI conduit used to invoke PSCI methods 810 * 0 - disabled, 1 - smc, 2 - hvc 811 */ 812 uint32_t psci_conduit; 813 814 /* For v8M, initial value of the Secure VTOR */ 815 uint32_t init_svtor; 816 817 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 818 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 819 */ 820 uint32_t kvm_target; 821 822 /* KVM init features for this CPU */ 823 uint32_t kvm_init_features[7]; 824 825 /* KVM CPU state */ 826 827 /* KVM virtual time adjustment */ 828 bool kvm_adjvtime; 829 bool kvm_vtime_dirty; 830 uint64_t kvm_vtime; 831 832 /* Uniprocessor system with MP extensions */ 833 bool mp_is_up; 834 835 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 836 * and the probe failed (so we need to report the error in realize) 837 */ 838 bool host_cpu_probe_failed; 839 840 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 841 * register. 842 */ 843 int32_t core_count; 844 845 /* The instance init functions for implementation-specific subclasses 846 * set these fields to specify the implementation-dependent values of 847 * various constant registers and reset values of non-constant 848 * registers. 849 * Some of these might become QOM properties eventually. 850 * Field names match the official register names as defined in the 851 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 852 * is used for reset values of non-constant registers; no reset_ 853 * prefix means a constant register. 854 * Some of these registers are split out into a substructure that 855 * is shared with the translators to control the ISA. 856 */ 857 struct ARMISARegisters { 858 uint32_t id_isar0; 859 uint32_t id_isar1; 860 uint32_t id_isar2; 861 uint32_t id_isar3; 862 uint32_t id_isar4; 863 uint32_t id_isar5; 864 uint32_t id_isar6; 865 uint32_t mvfr0; 866 uint32_t mvfr1; 867 uint32_t mvfr2; 868 uint32_t id_dfr0; 869 uint64_t id_aa64isar0; 870 uint64_t id_aa64isar1; 871 uint64_t id_aa64pfr0; 872 uint64_t id_aa64pfr1; 873 uint64_t id_aa64mmfr0; 874 uint64_t id_aa64mmfr1; 875 uint64_t id_aa64mmfr2; 876 } isar; 877 uint32_t midr; 878 uint32_t revidr; 879 uint32_t reset_fpsid; 880 uint32_t ctr; 881 uint32_t reset_sctlr; 882 uint32_t id_pfr0; 883 uint32_t id_pfr1; 884 uint64_t pmceid0; 885 uint64_t pmceid1; 886 uint32_t id_afr0; 887 uint32_t id_mmfr0; 888 uint32_t id_mmfr1; 889 uint32_t id_mmfr2; 890 uint32_t id_mmfr3; 891 uint32_t id_mmfr4; 892 uint64_t id_aa64dfr0; 893 uint64_t id_aa64dfr1; 894 uint64_t id_aa64afr0; 895 uint64_t id_aa64afr1; 896 uint32_t dbgdidr; 897 uint32_t clidr; 898 uint64_t mp_affinity; /* MP ID without feature bits */ 899 /* The elements of this array are the CCSIDR values for each cache, 900 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 901 */ 902 uint32_t ccsidr[16]; 903 uint64_t reset_cbar; 904 uint32_t reset_auxcr; 905 bool reset_hivecs; 906 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 907 uint32_t dcz_blocksize; 908 uint64_t rvbar; 909 910 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 911 int gic_num_lrs; /* number of list registers */ 912 int gic_vpribits; /* number of virtual priority bits */ 913 int gic_vprebits; /* number of virtual preemption bits */ 914 915 /* Whether the cfgend input is high (i.e. this CPU should reset into 916 * big-endian mode). This setting isn't used directly: instead it modifies 917 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 918 * architecture version. 919 */ 920 bool cfgend; 921 922 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 923 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 924 925 int32_t node_id; /* NUMA node this CPU belongs to */ 926 927 /* Used to synchronize KVM and QEMU in-kernel device levels */ 928 uint8_t device_irq_level; 929 930 /* Used to set the maximum vector length the cpu will support. */ 931 uint32_t sve_max_vq; 932 933 /* 934 * In sve_vq_map each set bit is a supported vector length of 935 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 936 * length in quadwords. 937 * 938 * While processing properties during initialization, corresponding 939 * sve_vq_init bits are set for bits in sve_vq_map that have been 940 * set by properties. 941 */ 942 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 943 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 944 945 /* Generic timer counter frequency, in Hz */ 946 uint64_t gt_cntfrq_hz; 947 }; 948 949 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 950 951 void arm_cpu_post_init(Object *obj); 952 953 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 954 955 #ifndef CONFIG_USER_ONLY 956 extern const VMStateDescription vmstate_arm_cpu; 957 #endif 958 959 void arm_cpu_do_interrupt(CPUState *cpu); 960 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 961 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 962 963 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 964 MemTxAttrs *attrs); 965 966 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 967 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 968 969 /* Dynamically generates for gdb stub an XML description of the sysregs from 970 * the cp_regs hashtable. Returns the registered sysregs number. 971 */ 972 int arm_gen_dynamic_xml(CPUState *cpu); 973 974 /* Returns the dynamically generated XML for the gdb stub. 975 * Returns a pointer to the XML contents for the specified XML file or NULL 976 * if the XML name doesn't match the predefined one. 977 */ 978 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 979 980 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 981 int cpuid, void *opaque); 982 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 983 int cpuid, void *opaque); 984 985 #ifdef TARGET_AARCH64 986 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 987 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 988 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 989 void aarch64_sve_change_el(CPUARMState *env, int old_el, 990 int new_el, bool el0_a64); 991 void aarch64_add_sve_properties(Object *obj); 992 993 /* 994 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 995 * The byte at offset i from the start of the in-memory representation contains 996 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 997 * lowest offsets are stored in the lowest memory addresses, then that nearly 998 * matches QEMU's representation, which is to use an array of host-endian 999 * uint64_t's, where the lower offsets are at the lower indices. To complete 1000 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1001 */ 1002 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1003 { 1004 #ifdef HOST_WORDS_BIGENDIAN 1005 int i; 1006 1007 for (i = 0; i < nr; ++i) { 1008 dst[i] = bswap64(src[i]); 1009 } 1010 1011 return dst; 1012 #else 1013 return src; 1014 #endif 1015 } 1016 1017 #else 1018 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1019 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1020 int n, bool a) 1021 { } 1022 static inline void aarch64_add_sve_properties(Object *obj) { } 1023 #endif 1024 1025 #if !defined(CONFIG_TCG) 1026 static inline target_ulong do_arm_semihosting(CPUARMState *env) 1027 { 1028 g_assert_not_reached(); 1029 } 1030 #else 1031 target_ulong do_arm_semihosting(CPUARMState *env); 1032 #endif 1033 void aarch64_sync_32_to_64(CPUARMState *env); 1034 void aarch64_sync_64_to_32(CPUARMState *env); 1035 1036 int fp_exception_el(CPUARMState *env, int cur_el); 1037 int sve_exception_el(CPUARMState *env, int cur_el); 1038 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1039 1040 static inline bool is_a64(CPUARMState *env) 1041 { 1042 return env->aarch64; 1043 } 1044 1045 /* you can call this signal handler from your SIGBUS and SIGSEGV 1046 signal handlers to inform the virtual CPU of exceptions. non zero 1047 is returned if the signal was handled by the virtual CPU. */ 1048 int cpu_arm_signal_handler(int host_signum, void *pinfo, 1049 void *puc); 1050 1051 /** 1052 * pmu_op_start/finish 1053 * @env: CPUARMState 1054 * 1055 * Convert all PMU counters between their delta form (the typical mode when 1056 * they are enabled) and the guest-visible values. These two calls must 1057 * surround any action which might affect the counters. 1058 */ 1059 void pmu_op_start(CPUARMState *env); 1060 void pmu_op_finish(CPUARMState *env); 1061 1062 /* 1063 * Called when a PMU counter is due to overflow 1064 */ 1065 void arm_pmu_timer_cb(void *opaque); 1066 1067 /** 1068 * Functions to register as EL change hooks for PMU mode filtering 1069 */ 1070 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1071 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1072 1073 /* 1074 * pmu_init 1075 * @cpu: ARMCPU 1076 * 1077 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1078 * for the current configuration 1079 */ 1080 void pmu_init(ARMCPU *cpu); 1081 1082 /* SCTLR bit meanings. Several bits have been reused in newer 1083 * versions of the architecture; in that case we define constants 1084 * for both old and new bit meanings. Code which tests against those 1085 * bits should probably check or otherwise arrange that the CPU 1086 * is the architectural version it expects. 1087 */ 1088 #define SCTLR_M (1U << 0) 1089 #define SCTLR_A (1U << 1) 1090 #define SCTLR_C (1U << 2) 1091 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1092 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1093 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1094 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1095 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1096 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1097 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1098 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1099 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1100 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1101 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1102 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1103 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1104 #define SCTLR_SED (1U << 8) /* v8 onward */ 1105 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1106 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1107 #define SCTLR_F (1U << 10) /* up to v6 */ 1108 #define SCTLR_SW (1U << 10) /* v7 */ 1109 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1110 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1111 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1112 #define SCTLR_I (1U << 12) 1113 #define SCTLR_V (1U << 13) /* AArch32 only */ 1114 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1115 #define SCTLR_RR (1U << 14) /* up to v7 */ 1116 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1117 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1118 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1119 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1120 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1121 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1122 #define SCTLR_BR (1U << 17) /* PMSA only */ 1123 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1124 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1125 #define SCTLR_WXN (1U << 19) 1126 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1127 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1128 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1129 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1130 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1131 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1132 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1133 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1134 #define SCTLR_VE (1U << 24) /* up to v7 */ 1135 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1136 #define SCTLR_EE (1U << 25) 1137 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1138 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1139 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1140 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1141 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1142 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1143 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1144 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1145 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1146 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1147 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1148 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1149 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1150 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1151 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1152 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1153 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1154 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1155 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1156 1157 #define CPTR_TCPAC (1U << 31) 1158 #define CPTR_TTA (1U << 20) 1159 #define CPTR_TFP (1U << 10) 1160 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1161 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1162 1163 #define MDCR_EPMAD (1U << 21) 1164 #define MDCR_EDAD (1U << 20) 1165 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1166 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1167 #define MDCR_SDD (1U << 16) 1168 #define MDCR_SPD (3U << 14) 1169 #define MDCR_TDRA (1U << 11) 1170 #define MDCR_TDOSA (1U << 10) 1171 #define MDCR_TDA (1U << 9) 1172 #define MDCR_TDE (1U << 8) 1173 #define MDCR_HPME (1U << 7) 1174 #define MDCR_TPM (1U << 6) 1175 #define MDCR_TPMCR (1U << 5) 1176 #define MDCR_HPMN (0x1fU) 1177 1178 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1179 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1180 1181 #define CPSR_M (0x1fU) 1182 #define CPSR_T (1U << 5) 1183 #define CPSR_F (1U << 6) 1184 #define CPSR_I (1U << 7) 1185 #define CPSR_A (1U << 8) 1186 #define CPSR_E (1U << 9) 1187 #define CPSR_IT_2_7 (0xfc00U) 1188 #define CPSR_GE (0xfU << 16) 1189 #define CPSR_IL (1U << 20) 1190 #define CPSR_PAN (1U << 22) 1191 #define CPSR_J (1U << 24) 1192 #define CPSR_IT_0_1 (3U << 25) 1193 #define CPSR_Q (1U << 27) 1194 #define CPSR_V (1U << 28) 1195 #define CPSR_C (1U << 29) 1196 #define CPSR_Z (1U << 30) 1197 #define CPSR_N (1U << 31) 1198 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1199 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1200 1201 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1202 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1203 | CPSR_NZCV) 1204 /* Bits writable in user mode. */ 1205 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1206 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1207 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1208 1209 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1210 #define XPSR_EXCP 0x1ffU 1211 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1212 #define XPSR_IT_2_7 CPSR_IT_2_7 1213 #define XPSR_GE CPSR_GE 1214 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1215 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1216 #define XPSR_IT_0_1 CPSR_IT_0_1 1217 #define XPSR_Q CPSR_Q 1218 #define XPSR_V CPSR_V 1219 #define XPSR_C CPSR_C 1220 #define XPSR_Z CPSR_Z 1221 #define XPSR_N CPSR_N 1222 #define XPSR_NZCV CPSR_NZCV 1223 #define XPSR_IT CPSR_IT 1224 1225 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1226 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1227 #define TTBCR_PD0 (1U << 4) 1228 #define TTBCR_PD1 (1U << 5) 1229 #define TTBCR_EPD0 (1U << 7) 1230 #define TTBCR_IRGN0 (3U << 8) 1231 #define TTBCR_ORGN0 (3U << 10) 1232 #define TTBCR_SH0 (3U << 12) 1233 #define TTBCR_T1SZ (3U << 16) 1234 #define TTBCR_A1 (1U << 22) 1235 #define TTBCR_EPD1 (1U << 23) 1236 #define TTBCR_IRGN1 (3U << 24) 1237 #define TTBCR_ORGN1 (3U << 26) 1238 #define TTBCR_SH1 (1U << 28) 1239 #define TTBCR_EAE (1U << 31) 1240 1241 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1242 * Only these are valid when in AArch64 mode; in 1243 * AArch32 mode SPSRs are basically CPSR-format. 1244 */ 1245 #define PSTATE_SP (1U) 1246 #define PSTATE_M (0xFU) 1247 #define PSTATE_nRW (1U << 4) 1248 #define PSTATE_F (1U << 6) 1249 #define PSTATE_I (1U << 7) 1250 #define PSTATE_A (1U << 8) 1251 #define PSTATE_D (1U << 9) 1252 #define PSTATE_BTYPE (3U << 10) 1253 #define PSTATE_IL (1U << 20) 1254 #define PSTATE_SS (1U << 21) 1255 #define PSTATE_PAN (1U << 22) 1256 #define PSTATE_UAO (1U << 23) 1257 #define PSTATE_V (1U << 28) 1258 #define PSTATE_C (1U << 29) 1259 #define PSTATE_Z (1U << 30) 1260 #define PSTATE_N (1U << 31) 1261 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1262 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1263 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1264 /* Mode values for AArch64 */ 1265 #define PSTATE_MODE_EL3h 13 1266 #define PSTATE_MODE_EL3t 12 1267 #define PSTATE_MODE_EL2h 9 1268 #define PSTATE_MODE_EL2t 8 1269 #define PSTATE_MODE_EL1h 5 1270 #define PSTATE_MODE_EL1t 4 1271 #define PSTATE_MODE_EL0t 0 1272 1273 /* Write a new value to v7m.exception, thus transitioning into or out 1274 * of Handler mode; this may result in a change of active stack pointer. 1275 */ 1276 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1277 1278 /* Map EL and handler into a PSTATE_MODE. */ 1279 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1280 { 1281 return (el << 2) | handler; 1282 } 1283 1284 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1285 * interprocessing, so we don't attempt to sync with the cpsr state used by 1286 * the 32 bit decoder. 1287 */ 1288 static inline uint32_t pstate_read(CPUARMState *env) 1289 { 1290 int ZF; 1291 1292 ZF = (env->ZF == 0); 1293 return (env->NF & 0x80000000) | (ZF << 30) 1294 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1295 | env->pstate | env->daif | (env->btype << 10); 1296 } 1297 1298 static inline void pstate_write(CPUARMState *env, uint32_t val) 1299 { 1300 env->ZF = (~val) & PSTATE_Z; 1301 env->NF = val; 1302 env->CF = (val >> 29) & 1; 1303 env->VF = (val << 3) & 0x80000000; 1304 env->daif = val & PSTATE_DAIF; 1305 env->btype = (val >> 10) & 3; 1306 env->pstate = val & ~CACHED_PSTATE_BITS; 1307 } 1308 1309 /* Return the current CPSR value. */ 1310 uint32_t cpsr_read(CPUARMState *env); 1311 1312 typedef enum CPSRWriteType { 1313 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1314 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1315 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1316 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1317 } CPSRWriteType; 1318 1319 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1320 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1321 CPSRWriteType write_type); 1322 1323 /* Return the current xPSR value. */ 1324 static inline uint32_t xpsr_read(CPUARMState *env) 1325 { 1326 int ZF; 1327 ZF = (env->ZF == 0); 1328 return (env->NF & 0x80000000) | (ZF << 30) 1329 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1330 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1331 | ((env->condexec_bits & 0xfc) << 8) 1332 | (env->GE << 16) 1333 | env->v7m.exception; 1334 } 1335 1336 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1337 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1338 { 1339 if (mask & XPSR_NZCV) { 1340 env->ZF = (~val) & XPSR_Z; 1341 env->NF = val; 1342 env->CF = (val >> 29) & 1; 1343 env->VF = (val << 3) & 0x80000000; 1344 } 1345 if (mask & XPSR_Q) { 1346 env->QF = ((val & XPSR_Q) != 0); 1347 } 1348 if (mask & XPSR_GE) { 1349 env->GE = (val & XPSR_GE) >> 16; 1350 } 1351 #ifndef CONFIG_USER_ONLY 1352 if (mask & XPSR_T) { 1353 env->thumb = ((val & XPSR_T) != 0); 1354 } 1355 if (mask & XPSR_IT_0_1) { 1356 env->condexec_bits &= ~3; 1357 env->condexec_bits |= (val >> 25) & 3; 1358 } 1359 if (mask & XPSR_IT_2_7) { 1360 env->condexec_bits &= 3; 1361 env->condexec_bits |= (val >> 8) & 0xfc; 1362 } 1363 if (mask & XPSR_EXCP) { 1364 /* Note that this only happens on exception exit */ 1365 write_v7m_exception(env, val & XPSR_EXCP); 1366 } 1367 #endif 1368 } 1369 1370 #define HCR_VM (1ULL << 0) 1371 #define HCR_SWIO (1ULL << 1) 1372 #define HCR_PTW (1ULL << 2) 1373 #define HCR_FMO (1ULL << 3) 1374 #define HCR_IMO (1ULL << 4) 1375 #define HCR_AMO (1ULL << 5) 1376 #define HCR_VF (1ULL << 6) 1377 #define HCR_VI (1ULL << 7) 1378 #define HCR_VSE (1ULL << 8) 1379 #define HCR_FB (1ULL << 9) 1380 #define HCR_BSU_MASK (3ULL << 10) 1381 #define HCR_DC (1ULL << 12) 1382 #define HCR_TWI (1ULL << 13) 1383 #define HCR_TWE (1ULL << 14) 1384 #define HCR_TID0 (1ULL << 15) 1385 #define HCR_TID1 (1ULL << 16) 1386 #define HCR_TID2 (1ULL << 17) 1387 #define HCR_TID3 (1ULL << 18) 1388 #define HCR_TSC (1ULL << 19) 1389 #define HCR_TIDCP (1ULL << 20) 1390 #define HCR_TACR (1ULL << 21) 1391 #define HCR_TSW (1ULL << 22) 1392 #define HCR_TPCP (1ULL << 23) 1393 #define HCR_TPU (1ULL << 24) 1394 #define HCR_TTLB (1ULL << 25) 1395 #define HCR_TVM (1ULL << 26) 1396 #define HCR_TGE (1ULL << 27) 1397 #define HCR_TDZ (1ULL << 28) 1398 #define HCR_HCD (1ULL << 29) 1399 #define HCR_TRVM (1ULL << 30) 1400 #define HCR_RW (1ULL << 31) 1401 #define HCR_CD (1ULL << 32) 1402 #define HCR_ID (1ULL << 33) 1403 #define HCR_E2H (1ULL << 34) 1404 #define HCR_TLOR (1ULL << 35) 1405 #define HCR_TERR (1ULL << 36) 1406 #define HCR_TEA (1ULL << 37) 1407 #define HCR_MIOCNCE (1ULL << 38) 1408 #define HCR_APK (1ULL << 40) 1409 #define HCR_API (1ULL << 41) 1410 #define HCR_NV (1ULL << 42) 1411 #define HCR_NV1 (1ULL << 43) 1412 #define HCR_AT (1ULL << 44) 1413 #define HCR_NV2 (1ULL << 45) 1414 #define HCR_FWB (1ULL << 46) 1415 #define HCR_FIEN (1ULL << 47) 1416 #define HCR_TID4 (1ULL << 49) 1417 #define HCR_TICAB (1ULL << 50) 1418 #define HCR_TOCU (1ULL << 52) 1419 #define HCR_TTLBIS (1ULL << 54) 1420 #define HCR_TTLBOS (1ULL << 55) 1421 #define HCR_ATA (1ULL << 56) 1422 #define HCR_DCT (1ULL << 57) 1423 1424 #define SCR_NS (1U << 0) 1425 #define SCR_IRQ (1U << 1) 1426 #define SCR_FIQ (1U << 2) 1427 #define SCR_EA (1U << 3) 1428 #define SCR_FW (1U << 4) 1429 #define SCR_AW (1U << 5) 1430 #define SCR_NET (1U << 6) 1431 #define SCR_SMD (1U << 7) 1432 #define SCR_HCE (1U << 8) 1433 #define SCR_SIF (1U << 9) 1434 #define SCR_RW (1U << 10) 1435 #define SCR_ST (1U << 11) 1436 #define SCR_TWI (1U << 12) 1437 #define SCR_TWE (1U << 13) 1438 #define SCR_TLOR (1U << 14) 1439 #define SCR_TERR (1U << 15) 1440 #define SCR_APK (1U << 16) 1441 #define SCR_API (1U << 17) 1442 #define SCR_EEL2 (1U << 18) 1443 #define SCR_EASE (1U << 19) 1444 #define SCR_NMEA (1U << 20) 1445 #define SCR_FIEN (1U << 21) 1446 #define SCR_ENSCXT (1U << 25) 1447 #define SCR_ATA (1U << 26) 1448 1449 /* Return the current FPSCR value. */ 1450 uint32_t vfp_get_fpscr(CPUARMState *env); 1451 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1452 1453 /* FPCR, Floating Point Control Register 1454 * FPSR, Floating Poiht Status Register 1455 * 1456 * For A64 the FPSCR is split into two logically distinct registers, 1457 * FPCR and FPSR. However since they still use non-overlapping bits 1458 * we store the underlying state in fpscr and just mask on read/write. 1459 */ 1460 #define FPSR_MASK 0xf800009f 1461 #define FPCR_MASK 0x07ff9f00 1462 1463 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1464 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1465 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1466 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1467 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1468 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1469 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1470 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1471 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1472 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1473 1474 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1475 { 1476 return vfp_get_fpscr(env) & FPSR_MASK; 1477 } 1478 1479 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1480 { 1481 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1482 vfp_set_fpscr(env, new_fpscr); 1483 } 1484 1485 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1486 { 1487 return vfp_get_fpscr(env) & FPCR_MASK; 1488 } 1489 1490 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1491 { 1492 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1493 vfp_set_fpscr(env, new_fpscr); 1494 } 1495 1496 enum arm_cpu_mode { 1497 ARM_CPU_MODE_USR = 0x10, 1498 ARM_CPU_MODE_FIQ = 0x11, 1499 ARM_CPU_MODE_IRQ = 0x12, 1500 ARM_CPU_MODE_SVC = 0x13, 1501 ARM_CPU_MODE_MON = 0x16, 1502 ARM_CPU_MODE_ABT = 0x17, 1503 ARM_CPU_MODE_HYP = 0x1a, 1504 ARM_CPU_MODE_UND = 0x1b, 1505 ARM_CPU_MODE_SYS = 0x1f 1506 }; 1507 1508 /* VFP system registers. */ 1509 #define ARM_VFP_FPSID 0 1510 #define ARM_VFP_FPSCR 1 1511 #define ARM_VFP_MVFR2 5 1512 #define ARM_VFP_MVFR1 6 1513 #define ARM_VFP_MVFR0 7 1514 #define ARM_VFP_FPEXC 8 1515 #define ARM_VFP_FPINST 9 1516 #define ARM_VFP_FPINST2 10 1517 1518 /* iwMMXt coprocessor control registers. */ 1519 #define ARM_IWMMXT_wCID 0 1520 #define ARM_IWMMXT_wCon 1 1521 #define ARM_IWMMXT_wCSSF 2 1522 #define ARM_IWMMXT_wCASF 3 1523 #define ARM_IWMMXT_wCGR0 8 1524 #define ARM_IWMMXT_wCGR1 9 1525 #define ARM_IWMMXT_wCGR2 10 1526 #define ARM_IWMMXT_wCGR3 11 1527 1528 /* V7M CCR bits */ 1529 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1530 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1531 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1532 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1533 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1534 FIELD(V7M_CCR, STKALIGN, 9, 1) 1535 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1536 FIELD(V7M_CCR, DC, 16, 1) 1537 FIELD(V7M_CCR, IC, 17, 1) 1538 FIELD(V7M_CCR, BP, 18, 1) 1539 1540 /* V7M SCR bits */ 1541 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1542 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1543 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1544 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1545 1546 /* V7M AIRCR bits */ 1547 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1548 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1549 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1550 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1551 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1552 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1553 FIELD(V7M_AIRCR, PRIS, 14, 1) 1554 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1555 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1556 1557 /* V7M CFSR bits for MMFSR */ 1558 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1559 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1560 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1561 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1562 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1563 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1564 1565 /* V7M CFSR bits for BFSR */ 1566 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1567 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1568 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1569 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1570 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1571 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1572 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1573 1574 /* V7M CFSR bits for UFSR */ 1575 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1576 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1577 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1578 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1579 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1580 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1581 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1582 1583 /* V7M CFSR bit masks covering all of the subregister bits */ 1584 FIELD(V7M_CFSR, MMFSR, 0, 8) 1585 FIELD(V7M_CFSR, BFSR, 8, 8) 1586 FIELD(V7M_CFSR, UFSR, 16, 16) 1587 1588 /* V7M HFSR bits */ 1589 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1590 FIELD(V7M_HFSR, FORCED, 30, 1) 1591 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1592 1593 /* V7M DFSR bits */ 1594 FIELD(V7M_DFSR, HALTED, 0, 1) 1595 FIELD(V7M_DFSR, BKPT, 1, 1) 1596 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1597 FIELD(V7M_DFSR, VCATCH, 3, 1) 1598 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1599 1600 /* V7M SFSR bits */ 1601 FIELD(V7M_SFSR, INVEP, 0, 1) 1602 FIELD(V7M_SFSR, INVIS, 1, 1) 1603 FIELD(V7M_SFSR, INVER, 2, 1) 1604 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1605 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1606 FIELD(V7M_SFSR, LSPERR, 5, 1) 1607 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1608 FIELD(V7M_SFSR, LSERR, 7, 1) 1609 1610 /* v7M MPU_CTRL bits */ 1611 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1612 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1613 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1614 1615 /* v7M CLIDR bits */ 1616 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1617 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1618 FIELD(V7M_CLIDR, LOC, 24, 3) 1619 FIELD(V7M_CLIDR, LOUU, 27, 3) 1620 FIELD(V7M_CLIDR, ICB, 30, 2) 1621 1622 FIELD(V7M_CSSELR, IND, 0, 1) 1623 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1624 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1625 * define a mask for this and check that it doesn't permit running off 1626 * the end of the array. 1627 */ 1628 FIELD(V7M_CSSELR, INDEX, 0, 4) 1629 1630 /* v7M FPCCR bits */ 1631 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1632 FIELD(V7M_FPCCR, USER, 1, 1) 1633 FIELD(V7M_FPCCR, S, 2, 1) 1634 FIELD(V7M_FPCCR, THREAD, 3, 1) 1635 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1636 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1637 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1638 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1639 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1640 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1641 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1642 FIELD(V7M_FPCCR, RES0, 11, 15) 1643 FIELD(V7M_FPCCR, TS, 26, 1) 1644 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1645 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1646 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1647 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1648 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1649 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1650 #define R_V7M_FPCCR_BANKED_MASK \ 1651 (R_V7M_FPCCR_LSPACT_MASK | \ 1652 R_V7M_FPCCR_USER_MASK | \ 1653 R_V7M_FPCCR_THREAD_MASK | \ 1654 R_V7M_FPCCR_MMRDY_MASK | \ 1655 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1656 R_V7M_FPCCR_UFRDY_MASK | \ 1657 R_V7M_FPCCR_ASPEN_MASK) 1658 1659 /* 1660 * System register ID fields. 1661 */ 1662 FIELD(MIDR_EL1, REVISION, 0, 4) 1663 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1664 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1665 FIELD(MIDR_EL1, VARIANT, 20, 4) 1666 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1667 1668 FIELD(ID_ISAR0, SWAP, 0, 4) 1669 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1670 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1671 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1672 FIELD(ID_ISAR0, COPROC, 16, 4) 1673 FIELD(ID_ISAR0, DEBUG, 20, 4) 1674 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1675 1676 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1677 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1678 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1679 FIELD(ID_ISAR1, EXTEND, 12, 4) 1680 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1681 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1682 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1683 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1684 1685 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1686 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1687 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1688 FIELD(ID_ISAR2, MULT, 12, 4) 1689 FIELD(ID_ISAR2, MULTS, 16, 4) 1690 FIELD(ID_ISAR2, MULTU, 20, 4) 1691 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1692 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1693 1694 FIELD(ID_ISAR3, SATURATE, 0, 4) 1695 FIELD(ID_ISAR3, SIMD, 4, 4) 1696 FIELD(ID_ISAR3, SVC, 8, 4) 1697 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1698 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1699 FIELD(ID_ISAR3, T32COPY, 20, 4) 1700 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1701 FIELD(ID_ISAR3, T32EE, 28, 4) 1702 1703 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1704 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1705 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1706 FIELD(ID_ISAR4, SMC, 12, 4) 1707 FIELD(ID_ISAR4, BARRIER, 16, 4) 1708 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1709 FIELD(ID_ISAR4, PSR_M, 24, 4) 1710 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1711 1712 FIELD(ID_ISAR5, SEVL, 0, 4) 1713 FIELD(ID_ISAR5, AES, 4, 4) 1714 FIELD(ID_ISAR5, SHA1, 8, 4) 1715 FIELD(ID_ISAR5, SHA2, 12, 4) 1716 FIELD(ID_ISAR5, CRC32, 16, 4) 1717 FIELD(ID_ISAR5, RDM, 24, 4) 1718 FIELD(ID_ISAR5, VCMA, 28, 4) 1719 1720 FIELD(ID_ISAR6, JSCVT, 0, 4) 1721 FIELD(ID_ISAR6, DP, 4, 4) 1722 FIELD(ID_ISAR6, FHM, 8, 4) 1723 FIELD(ID_ISAR6, SB, 12, 4) 1724 FIELD(ID_ISAR6, SPECRES, 16, 4) 1725 1726 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 1727 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 1728 FIELD(ID_MMFR3, BPMAINT, 8, 4) 1729 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 1730 FIELD(ID_MMFR3, PAN, 16, 4) 1731 FIELD(ID_MMFR3, COHWALK, 20, 4) 1732 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 1733 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 1734 1735 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1736 FIELD(ID_MMFR4, AC2, 4, 4) 1737 FIELD(ID_MMFR4, XNX, 8, 4) 1738 FIELD(ID_MMFR4, CNP, 12, 4) 1739 FIELD(ID_MMFR4, HPDS, 16, 4) 1740 FIELD(ID_MMFR4, LSM, 20, 4) 1741 FIELD(ID_MMFR4, CCIDX, 24, 4) 1742 FIELD(ID_MMFR4, EVT, 28, 4) 1743 1744 FIELD(ID_AA64ISAR0, AES, 4, 4) 1745 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1746 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1747 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1748 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1749 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1750 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1751 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1752 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1753 FIELD(ID_AA64ISAR0, DP, 44, 4) 1754 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1755 FIELD(ID_AA64ISAR0, TS, 52, 4) 1756 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1757 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1758 1759 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1760 FIELD(ID_AA64ISAR1, APA, 4, 4) 1761 FIELD(ID_AA64ISAR1, API, 8, 4) 1762 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1763 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1764 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1765 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1766 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1767 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1768 FIELD(ID_AA64ISAR1, SB, 36, 4) 1769 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1770 1771 FIELD(ID_AA64PFR0, EL0, 0, 4) 1772 FIELD(ID_AA64PFR0, EL1, 4, 4) 1773 FIELD(ID_AA64PFR0, EL2, 8, 4) 1774 FIELD(ID_AA64PFR0, EL3, 12, 4) 1775 FIELD(ID_AA64PFR0, FP, 16, 4) 1776 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1777 FIELD(ID_AA64PFR0, GIC, 24, 4) 1778 FIELD(ID_AA64PFR0, RAS, 28, 4) 1779 FIELD(ID_AA64PFR0, SVE, 32, 4) 1780 1781 FIELD(ID_AA64PFR1, BT, 0, 4) 1782 FIELD(ID_AA64PFR1, SBSS, 4, 4) 1783 FIELD(ID_AA64PFR1, MTE, 8, 4) 1784 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1785 1786 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1787 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1788 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1789 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1790 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1791 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1792 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1793 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1794 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1795 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1796 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1797 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1798 1799 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1800 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1801 FIELD(ID_AA64MMFR1, VH, 8, 4) 1802 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1803 FIELD(ID_AA64MMFR1, LO, 16, 4) 1804 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1805 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1806 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1807 1808 FIELD(ID_AA64MMFR2, CNP, 0, 4) 1809 FIELD(ID_AA64MMFR2, UAO, 4, 4) 1810 FIELD(ID_AA64MMFR2, LSM, 8, 4) 1811 FIELD(ID_AA64MMFR2, IESB, 12, 4) 1812 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 1813 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 1814 FIELD(ID_AA64MMFR2, NV, 24, 4) 1815 FIELD(ID_AA64MMFR2, ST, 28, 4) 1816 FIELD(ID_AA64MMFR2, AT, 32, 4) 1817 FIELD(ID_AA64MMFR2, IDS, 36, 4) 1818 FIELD(ID_AA64MMFR2, FWB, 40, 4) 1819 FIELD(ID_AA64MMFR2, TTL, 48, 4) 1820 FIELD(ID_AA64MMFR2, BBM, 52, 4) 1821 FIELD(ID_AA64MMFR2, EVT, 56, 4) 1822 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 1823 1824 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 1825 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 1826 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 1827 FIELD(ID_AA64DFR0, BRPS, 12, 4) 1828 FIELD(ID_AA64DFR0, WRPS, 20, 4) 1829 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 1830 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 1831 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 1832 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 1833 1834 FIELD(ID_DFR0, COPDBG, 0, 4) 1835 FIELD(ID_DFR0, COPSDBG, 4, 4) 1836 FIELD(ID_DFR0, MMAPDBG, 8, 4) 1837 FIELD(ID_DFR0, COPTRC, 12, 4) 1838 FIELD(ID_DFR0, MMAPTRC, 16, 4) 1839 FIELD(ID_DFR0, MPROFDBG, 20, 4) 1840 FIELD(ID_DFR0, PERFMON, 24, 4) 1841 FIELD(ID_DFR0, TRACEFILT, 28, 4) 1842 1843 FIELD(MVFR0, SIMDREG, 0, 4) 1844 FIELD(MVFR0, FPSP, 4, 4) 1845 FIELD(MVFR0, FPDP, 8, 4) 1846 FIELD(MVFR0, FPTRAP, 12, 4) 1847 FIELD(MVFR0, FPDIVIDE, 16, 4) 1848 FIELD(MVFR0, FPSQRT, 20, 4) 1849 FIELD(MVFR0, FPSHVEC, 24, 4) 1850 FIELD(MVFR0, FPROUND, 28, 4) 1851 1852 FIELD(MVFR1, FPFTZ, 0, 4) 1853 FIELD(MVFR1, FPDNAN, 4, 4) 1854 FIELD(MVFR1, SIMDLS, 8, 4) 1855 FIELD(MVFR1, SIMDINT, 12, 4) 1856 FIELD(MVFR1, SIMDSP, 16, 4) 1857 FIELD(MVFR1, SIMDHP, 20, 4) 1858 FIELD(MVFR1, FPHP, 24, 4) 1859 FIELD(MVFR1, SIMDFMAC, 28, 4) 1860 1861 FIELD(MVFR2, SIMDMISC, 0, 4) 1862 FIELD(MVFR2, FPMISC, 4, 4) 1863 1864 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1865 1866 /* If adding a feature bit which corresponds to a Linux ELF 1867 * HWCAP bit, remember to update the feature-bit-to-hwcap 1868 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1869 */ 1870 enum arm_features { 1871 ARM_FEATURE_VFP, 1872 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1873 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1874 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1875 ARM_FEATURE_V6, 1876 ARM_FEATURE_V6K, 1877 ARM_FEATURE_V7, 1878 ARM_FEATURE_THUMB2, 1879 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1880 ARM_FEATURE_VFP3, 1881 ARM_FEATURE_NEON, 1882 ARM_FEATURE_M, /* Microcontroller profile. */ 1883 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1884 ARM_FEATURE_THUMB2EE, 1885 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1886 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1887 ARM_FEATURE_V4T, 1888 ARM_FEATURE_V5, 1889 ARM_FEATURE_STRONGARM, 1890 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1891 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1892 ARM_FEATURE_GENERIC_TIMER, 1893 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1894 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1895 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1896 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1897 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1898 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1899 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1900 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1901 ARM_FEATURE_V8, 1902 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1903 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1904 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1905 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1906 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1907 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1908 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1909 ARM_FEATURE_PMU, /* has PMU support */ 1910 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1911 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1912 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1913 }; 1914 1915 static inline int arm_feature(CPUARMState *env, int feature) 1916 { 1917 return (env->features & (1ULL << feature)) != 0; 1918 } 1919 1920 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 1921 1922 #if !defined(CONFIG_USER_ONLY) 1923 /* Return true if exception levels below EL3 are in secure state, 1924 * or would be following an exception return to that level. 1925 * Unlike arm_is_secure() (which is always a question about the 1926 * _current_ state of the CPU) this doesn't care about the current 1927 * EL or mode. 1928 */ 1929 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1930 { 1931 if (arm_feature(env, ARM_FEATURE_EL3)) { 1932 return !(env->cp15.scr_el3 & SCR_NS); 1933 } else { 1934 /* If EL3 is not supported then the secure state is implementation 1935 * defined, in which case QEMU defaults to non-secure. 1936 */ 1937 return false; 1938 } 1939 } 1940 1941 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1942 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1943 { 1944 if (arm_feature(env, ARM_FEATURE_EL3)) { 1945 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1946 /* CPU currently in AArch64 state and EL3 */ 1947 return true; 1948 } else if (!is_a64(env) && 1949 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1950 /* CPU currently in AArch32 state and monitor mode */ 1951 return true; 1952 } 1953 } 1954 return false; 1955 } 1956 1957 /* Return true if the processor is in secure state */ 1958 static inline bool arm_is_secure(CPUARMState *env) 1959 { 1960 if (arm_is_el3_or_mon(env)) { 1961 return true; 1962 } 1963 return arm_is_secure_below_el3(env); 1964 } 1965 1966 #else 1967 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1968 { 1969 return false; 1970 } 1971 1972 static inline bool arm_is_secure(CPUARMState *env) 1973 { 1974 return false; 1975 } 1976 #endif 1977 1978 /** 1979 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 1980 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 1981 * "for all purposes other than a direct read or write access of HCR_EL2." 1982 * Not included here is HCR_RW. 1983 */ 1984 uint64_t arm_hcr_el2_eff(CPUARMState *env); 1985 1986 /* Return true if the specified exception level is running in AArch64 state. */ 1987 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1988 { 1989 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1990 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1991 */ 1992 assert(el >= 1 && el <= 3); 1993 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1994 1995 /* The highest exception level is always at the maximum supported 1996 * register width, and then lower levels have a register width controlled 1997 * by bits in the SCR or HCR registers. 1998 */ 1999 if (el == 3) { 2000 return aa64; 2001 } 2002 2003 if (arm_feature(env, ARM_FEATURE_EL3)) { 2004 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2005 } 2006 2007 if (el == 2) { 2008 return aa64; 2009 } 2010 2011 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 2012 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2013 } 2014 2015 return aa64; 2016 } 2017 2018 /* Function for determing whether guest cp register reads and writes should 2019 * access the secure or non-secure bank of a cp register. When EL3 is 2020 * operating in AArch32 state, the NS-bit determines whether the secure 2021 * instance of a cp register should be used. When EL3 is AArch64 (or if 2022 * it doesn't exist at all) then there is no register banking, and all 2023 * accesses are to the non-secure version. 2024 */ 2025 static inline bool access_secure_reg(CPUARMState *env) 2026 { 2027 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2028 !arm_el_is_aa64(env, 3) && 2029 !(env->cp15.scr_el3 & SCR_NS)); 2030 2031 return ret; 2032 } 2033 2034 /* Macros for accessing a specified CP register bank */ 2035 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2036 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2037 2038 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2039 do { \ 2040 if (_secure) { \ 2041 (_env)->cp15._regname##_s = (_val); \ 2042 } else { \ 2043 (_env)->cp15._regname##_ns = (_val); \ 2044 } \ 2045 } while (0) 2046 2047 /* Macros for automatically accessing a specific CP register bank depending on 2048 * the current secure state of the system. These macros are not intended for 2049 * supporting instruction translation reads/writes as these are dependent 2050 * solely on the SCR.NS bit and not the mode. 2051 */ 2052 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2053 A32_BANKED_REG_GET((_env), _regname, \ 2054 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2055 2056 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2057 A32_BANKED_REG_SET((_env), _regname, \ 2058 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2059 (_val)) 2060 2061 void arm_cpu_list(void); 2062 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2063 uint32_t cur_el, bool secure); 2064 2065 /* Interface between CPU and Interrupt controller. */ 2066 #ifndef CONFIG_USER_ONLY 2067 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2068 #else 2069 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2070 { 2071 return true; 2072 } 2073 #endif 2074 /** 2075 * armv7m_nvic_set_pending: mark the specified exception as pending 2076 * @opaque: the NVIC 2077 * @irq: the exception number to mark pending 2078 * @secure: false for non-banked exceptions or for the nonsecure 2079 * version of a banked exception, true for the secure version of a banked 2080 * exception. 2081 * 2082 * Marks the specified exception as pending. Note that we will assert() 2083 * if @secure is true and @irq does not specify one of the fixed set 2084 * of architecturally banked exceptions. 2085 */ 2086 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2087 /** 2088 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2089 * @opaque: the NVIC 2090 * @irq: the exception number to mark pending 2091 * @secure: false for non-banked exceptions or for the nonsecure 2092 * version of a banked exception, true for the secure version of a banked 2093 * exception. 2094 * 2095 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2096 * exceptions (exceptions generated in the course of trying to take 2097 * a different exception). 2098 */ 2099 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2100 /** 2101 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2102 * @opaque: the NVIC 2103 * @irq: the exception number to mark pending 2104 * @secure: false for non-banked exceptions or for the nonsecure 2105 * version of a banked exception, true for the secure version of a banked 2106 * exception. 2107 * 2108 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2109 * generated in the course of lazy stacking of FP registers. 2110 */ 2111 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2112 /** 2113 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2114 * exception, and whether it targets Secure state 2115 * @opaque: the NVIC 2116 * @pirq: set to pending exception number 2117 * @ptargets_secure: set to whether pending exception targets Secure 2118 * 2119 * This function writes the number of the highest priority pending 2120 * exception (the one which would be made active by 2121 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2122 * to true if the current highest priority pending exception should 2123 * be taken to Secure state, false for NS. 2124 */ 2125 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2126 bool *ptargets_secure); 2127 /** 2128 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2129 * @opaque: the NVIC 2130 * 2131 * Move the current highest priority pending exception from the pending 2132 * state to the active state, and update v7m.exception to indicate that 2133 * it is the exception currently being handled. 2134 */ 2135 void armv7m_nvic_acknowledge_irq(void *opaque); 2136 /** 2137 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2138 * @opaque: the NVIC 2139 * @irq: the exception number to complete 2140 * @secure: true if this exception was secure 2141 * 2142 * Returns: -1 if the irq was not active 2143 * 1 if completing this irq brought us back to base (no active irqs) 2144 * 0 if there is still an irq active after this one was completed 2145 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2146 */ 2147 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2148 /** 2149 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2150 * @opaque: the NVIC 2151 * @irq: the exception number to mark pending 2152 * @secure: false for non-banked exceptions or for the nonsecure 2153 * version of a banked exception, true for the secure version of a banked 2154 * exception. 2155 * 2156 * Return whether an exception is "ready", i.e. whether the exception is 2157 * enabled and is configured at a priority which would allow it to 2158 * interrupt the current execution priority. This controls whether the 2159 * RDY bit for it in the FPCCR is set. 2160 */ 2161 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2162 /** 2163 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2164 * @opaque: the NVIC 2165 * 2166 * Returns: the raw execution priority as defined by the v8M architecture. 2167 * This is the execution priority minus the effects of AIRCR.PRIS, 2168 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2169 * (v8M ARM ARM I_PKLD.) 2170 */ 2171 int armv7m_nvic_raw_execution_priority(void *opaque); 2172 /** 2173 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2174 * priority is negative for the specified security state. 2175 * @opaque: the NVIC 2176 * @secure: the security state to test 2177 * This corresponds to the pseudocode IsReqExecPriNeg(). 2178 */ 2179 #ifndef CONFIG_USER_ONLY 2180 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2181 #else 2182 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2183 { 2184 return false; 2185 } 2186 #endif 2187 2188 /* Interface for defining coprocessor registers. 2189 * Registers are defined in tables of arm_cp_reginfo structs 2190 * which are passed to define_arm_cp_regs(). 2191 */ 2192 2193 /* When looking up a coprocessor register we look for it 2194 * via an integer which encodes all of: 2195 * coprocessor number 2196 * Crn, Crm, opc1, opc2 fields 2197 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2198 * or via MRRC/MCRR?) 2199 * non-secure/secure bank (AArch32 only) 2200 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2201 * (In this case crn and opc2 should be zero.) 2202 * For AArch64, there is no 32/64 bit size distinction; 2203 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2204 * and 4 bit CRn and CRm. The encoding patterns are chosen 2205 * to be easy to convert to and from the KVM encodings, and also 2206 * so that the hashtable can contain both AArch32 and AArch64 2207 * registers (to allow for interprocessing where we might run 2208 * 32 bit code on a 64 bit core). 2209 */ 2210 /* This bit is private to our hashtable cpreg; in KVM register 2211 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2212 * in the upper bits of the 64 bit ID. 2213 */ 2214 #define CP_REG_AA64_SHIFT 28 2215 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2216 2217 /* To enable banking of coprocessor registers depending on ns-bit we 2218 * add a bit to distinguish between secure and non-secure cpregs in the 2219 * hashtable. 2220 */ 2221 #define CP_REG_NS_SHIFT 29 2222 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2223 2224 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2225 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2226 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2227 2228 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2229 (CP_REG_AA64_MASK | \ 2230 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2231 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2232 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2233 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2234 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2235 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2236 2237 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2238 * version used as a key for the coprocessor register hashtable 2239 */ 2240 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2241 { 2242 uint32_t cpregid = kvmid; 2243 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2244 cpregid |= CP_REG_AA64_MASK; 2245 } else { 2246 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2247 cpregid |= (1 << 15); 2248 } 2249 2250 /* KVM is always non-secure so add the NS flag on AArch32 register 2251 * entries. 2252 */ 2253 cpregid |= 1 << CP_REG_NS_SHIFT; 2254 } 2255 return cpregid; 2256 } 2257 2258 /* Convert a truncated 32 bit hashtable key into the full 2259 * 64 bit KVM register ID. 2260 */ 2261 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2262 { 2263 uint64_t kvmid; 2264 2265 if (cpregid & CP_REG_AA64_MASK) { 2266 kvmid = cpregid & ~CP_REG_AA64_MASK; 2267 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2268 } else { 2269 kvmid = cpregid & ~(1 << 15); 2270 if (cpregid & (1 << 15)) { 2271 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2272 } else { 2273 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2274 } 2275 } 2276 return kvmid; 2277 } 2278 2279 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2280 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2281 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2282 * TCG can assume the value to be constant (ie load at translate time) 2283 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2284 * indicates that the TB should not be ended after a write to this register 2285 * (the default is that the TB ends after cp writes). OVERRIDE permits 2286 * a register definition to override a previous definition for the 2287 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2288 * old must have the OVERRIDE bit set. 2289 * ALIAS indicates that this register is an alias view of some underlying 2290 * state which is also visible via another register, and that the other 2291 * register is handling migration and reset; registers marked ALIAS will not be 2292 * migrated but may have their state set by syncing of register state from KVM. 2293 * NO_RAW indicates that this register has no underlying state and does not 2294 * support raw access for state saving/loading; it will not be used for either 2295 * migration or KVM state synchronization. (Typically this is for "registers" 2296 * which are actually used as instructions for cache maintenance and so on.) 2297 * IO indicates that this register does I/O and therefore its accesses 2298 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2299 * registers which implement clocks or timers require this. 2300 * RAISES_EXC is for when the read or write hook might raise an exception; 2301 * the generated code will synchronize the CPU state before calling the hook 2302 * so that it is safe for the hook to call raise_exception(). 2303 * NEWEL is for writes to registers that might change the exception 2304 * level - typically on older ARM chips. For those cases we need to 2305 * re-read the new el when recomputing the translation flags. 2306 */ 2307 #define ARM_CP_SPECIAL 0x0001 2308 #define ARM_CP_CONST 0x0002 2309 #define ARM_CP_64BIT 0x0004 2310 #define ARM_CP_SUPPRESS_TB_END 0x0008 2311 #define ARM_CP_OVERRIDE 0x0010 2312 #define ARM_CP_ALIAS 0x0020 2313 #define ARM_CP_IO 0x0040 2314 #define ARM_CP_NO_RAW 0x0080 2315 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2316 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2317 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2318 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2319 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2320 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2321 #define ARM_CP_FPU 0x1000 2322 #define ARM_CP_SVE 0x2000 2323 #define ARM_CP_NO_GDB 0x4000 2324 #define ARM_CP_RAISES_EXC 0x8000 2325 #define ARM_CP_NEWEL 0x10000 2326 /* Used only as a terminator for ARMCPRegInfo lists */ 2327 #define ARM_CP_SENTINEL 0xfffff 2328 /* Mask of only the flag bits in a type field */ 2329 #define ARM_CP_FLAG_MASK 0x1f0ff 2330 2331 /* Valid values for ARMCPRegInfo state field, indicating which of 2332 * the AArch32 and AArch64 execution states this register is visible in. 2333 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2334 * If the reginfo is declared to be visible in both states then a second 2335 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2336 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2337 * Note that we rely on the values of these enums as we iterate through 2338 * the various states in some places. 2339 */ 2340 enum { 2341 ARM_CP_STATE_AA32 = 0, 2342 ARM_CP_STATE_AA64 = 1, 2343 ARM_CP_STATE_BOTH = 2, 2344 }; 2345 2346 /* ARM CP register secure state flags. These flags identify security state 2347 * attributes for a given CP register entry. 2348 * The existence of both or neither secure and non-secure flags indicates that 2349 * the register has both a secure and non-secure hash entry. A single one of 2350 * these flags causes the register to only be hashed for the specified 2351 * security state. 2352 * Although definitions may have any combination of the S/NS bits, each 2353 * registered entry will only have one to identify whether the entry is secure 2354 * or non-secure. 2355 */ 2356 enum { 2357 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2358 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2359 }; 2360 2361 /* Return true if cptype is a valid type field. This is used to try to 2362 * catch errors where the sentinel has been accidentally left off the end 2363 * of a list of registers. 2364 */ 2365 static inline bool cptype_valid(int cptype) 2366 { 2367 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2368 || ((cptype & ARM_CP_SPECIAL) && 2369 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2370 } 2371 2372 /* Access rights: 2373 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2374 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2375 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2376 * (ie any of the privileged modes in Secure state, or Monitor mode). 2377 * If a register is accessible in one privilege level it's always accessible 2378 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2379 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2380 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2381 * terminology a little and call this PL3. 2382 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2383 * with the ELx exception levels. 2384 * 2385 * If access permissions for a register are more complex than can be 2386 * described with these bits, then use a laxer set of restrictions, and 2387 * do the more restrictive/complex check inside a helper function. 2388 */ 2389 #define PL3_R 0x80 2390 #define PL3_W 0x40 2391 #define PL2_R (0x20 | PL3_R) 2392 #define PL2_W (0x10 | PL3_W) 2393 #define PL1_R (0x08 | PL2_R) 2394 #define PL1_W (0x04 | PL2_W) 2395 #define PL0_R (0x02 | PL1_R) 2396 #define PL0_W (0x01 | PL1_W) 2397 2398 /* 2399 * For user-mode some registers are accessible to EL0 via a kernel 2400 * trap-and-emulate ABI. In this case we define the read permissions 2401 * as actually being PL0_R. However some bits of any given register 2402 * may still be masked. 2403 */ 2404 #ifdef CONFIG_USER_ONLY 2405 #define PL0U_R PL0_R 2406 #else 2407 #define PL0U_R PL1_R 2408 #endif 2409 2410 #define PL3_RW (PL3_R | PL3_W) 2411 #define PL2_RW (PL2_R | PL2_W) 2412 #define PL1_RW (PL1_R | PL1_W) 2413 #define PL0_RW (PL0_R | PL0_W) 2414 2415 /* Return the highest implemented Exception Level */ 2416 static inline int arm_highest_el(CPUARMState *env) 2417 { 2418 if (arm_feature(env, ARM_FEATURE_EL3)) { 2419 return 3; 2420 } 2421 if (arm_feature(env, ARM_FEATURE_EL2)) { 2422 return 2; 2423 } 2424 return 1; 2425 } 2426 2427 /* Return true if a v7M CPU is in Handler mode */ 2428 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2429 { 2430 return env->v7m.exception != 0; 2431 } 2432 2433 /* Return the current Exception Level (as per ARMv8; note that this differs 2434 * from the ARMv7 Privilege Level). 2435 */ 2436 static inline int arm_current_el(CPUARMState *env) 2437 { 2438 if (arm_feature(env, ARM_FEATURE_M)) { 2439 return arm_v7m_is_handler_mode(env) || 2440 !(env->v7m.control[env->v7m.secure] & 1); 2441 } 2442 2443 if (is_a64(env)) { 2444 return extract32(env->pstate, 2, 2); 2445 } 2446 2447 switch (env->uncached_cpsr & 0x1f) { 2448 case ARM_CPU_MODE_USR: 2449 return 0; 2450 case ARM_CPU_MODE_HYP: 2451 return 2; 2452 case ARM_CPU_MODE_MON: 2453 return 3; 2454 default: 2455 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2456 /* If EL3 is 32-bit then all secure privileged modes run in 2457 * EL3 2458 */ 2459 return 3; 2460 } 2461 2462 return 1; 2463 } 2464 } 2465 2466 typedef struct ARMCPRegInfo ARMCPRegInfo; 2467 2468 typedef enum CPAccessResult { 2469 /* Access is permitted */ 2470 CP_ACCESS_OK = 0, 2471 /* Access fails due to a configurable trap or enable which would 2472 * result in a categorized exception syndrome giving information about 2473 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2474 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2475 * PL1 if in EL0, otherwise to the current EL). 2476 */ 2477 CP_ACCESS_TRAP = 1, 2478 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2479 * Note that this is not a catch-all case -- the set of cases which may 2480 * result in this failure is specifically defined by the architecture. 2481 */ 2482 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2483 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2484 CP_ACCESS_TRAP_EL2 = 3, 2485 CP_ACCESS_TRAP_EL3 = 4, 2486 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2487 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2488 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2489 /* Access fails and results in an exception syndrome for an FP access, 2490 * trapped directly to EL2 or EL3 2491 */ 2492 CP_ACCESS_TRAP_FP_EL2 = 7, 2493 CP_ACCESS_TRAP_FP_EL3 = 8, 2494 } CPAccessResult; 2495 2496 /* Access functions for coprocessor registers. These cannot fail and 2497 * may not raise exceptions. 2498 */ 2499 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2500 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2501 uint64_t value); 2502 /* Access permission check functions for coprocessor registers. */ 2503 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2504 const ARMCPRegInfo *opaque, 2505 bool isread); 2506 /* Hook function for register reset */ 2507 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2508 2509 #define CP_ANY 0xff 2510 2511 /* Definition of an ARM coprocessor register */ 2512 struct ARMCPRegInfo { 2513 /* Name of register (useful mainly for debugging, need not be unique) */ 2514 const char *name; 2515 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2516 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2517 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2518 * will be decoded to this register. The register read and write 2519 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2520 * used by the program, so it is possible to register a wildcard and 2521 * then behave differently on read/write if necessary. 2522 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2523 * must both be zero. 2524 * For AArch64-visible registers, opc0 is also used. 2525 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2526 * way to distinguish (for KVM's benefit) guest-visible system registers 2527 * from demuxed ones provided to preserve the "no side effects on 2528 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2529 * visible (to match KVM's encoding); cp==0 will be converted to 2530 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2531 */ 2532 uint8_t cp; 2533 uint8_t crn; 2534 uint8_t crm; 2535 uint8_t opc0; 2536 uint8_t opc1; 2537 uint8_t opc2; 2538 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2539 int state; 2540 /* Register type: ARM_CP_* bits/values */ 2541 int type; 2542 /* Access rights: PL*_[RW] */ 2543 int access; 2544 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2545 int secure; 2546 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2547 * this register was defined: can be used to hand data through to the 2548 * register read/write functions, since they are passed the ARMCPRegInfo*. 2549 */ 2550 void *opaque; 2551 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2552 * fieldoffset is non-zero, the reset value of the register. 2553 */ 2554 uint64_t resetvalue; 2555 /* Offset of the field in CPUARMState for this register. 2556 * 2557 * This is not needed if either: 2558 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2559 * 2. both readfn and writefn are specified 2560 */ 2561 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2562 2563 /* Offsets of the secure and non-secure fields in CPUARMState for the 2564 * register if it is banked. These fields are only used during the static 2565 * registration of a register. During hashing the bank associated 2566 * with a given security state is copied to fieldoffset which is used from 2567 * there on out. 2568 * 2569 * It is expected that register definitions use either fieldoffset or 2570 * bank_fieldoffsets in the definition but not both. It is also expected 2571 * that both bank offsets are set when defining a banked register. This 2572 * use indicates that a register is banked. 2573 */ 2574 ptrdiff_t bank_fieldoffsets[2]; 2575 2576 /* Function for making any access checks for this register in addition to 2577 * those specified by the 'access' permissions bits. If NULL, no extra 2578 * checks required. The access check is performed at runtime, not at 2579 * translate time. 2580 */ 2581 CPAccessFn *accessfn; 2582 /* Function for handling reads of this register. If NULL, then reads 2583 * will be done by loading from the offset into CPUARMState specified 2584 * by fieldoffset. 2585 */ 2586 CPReadFn *readfn; 2587 /* Function for handling writes of this register. If NULL, then writes 2588 * will be done by writing to the offset into CPUARMState specified 2589 * by fieldoffset. 2590 */ 2591 CPWriteFn *writefn; 2592 /* Function for doing a "raw" read; used when we need to copy 2593 * coprocessor state to the kernel for KVM or out for 2594 * migration. This only needs to be provided if there is also a 2595 * readfn and it has side effects (for instance clear-on-read bits). 2596 */ 2597 CPReadFn *raw_readfn; 2598 /* Function for doing a "raw" write; used when we need to copy KVM 2599 * kernel coprocessor state into userspace, or for inbound 2600 * migration. This only needs to be provided if there is also a 2601 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2602 * or similar behaviour. 2603 */ 2604 CPWriteFn *raw_writefn; 2605 /* Function for resetting the register. If NULL, then reset will be done 2606 * by writing resetvalue to the field specified in fieldoffset. If 2607 * fieldoffset is 0 then no reset will be done. 2608 */ 2609 CPResetFn *resetfn; 2610 2611 /* 2612 * "Original" writefn and readfn. 2613 * For ARMv8.1-VHE register aliases, we overwrite the read/write 2614 * accessor functions of various EL1/EL0 to perform the runtime 2615 * check for which sysreg should actually be modified, and then 2616 * forwards the operation. Before overwriting the accessors, 2617 * the original function is copied here, so that accesses that 2618 * really do go to the EL1/EL0 version proceed normally. 2619 * (The corresponding EL2 register is linked via opaque.) 2620 */ 2621 CPReadFn *orig_readfn; 2622 CPWriteFn *orig_writefn; 2623 }; 2624 2625 /* Macros which are lvalues for the field in CPUARMState for the 2626 * ARMCPRegInfo *ri. 2627 */ 2628 #define CPREG_FIELD32(env, ri) \ 2629 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2630 #define CPREG_FIELD64(env, ri) \ 2631 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2632 2633 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2634 2635 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2636 const ARMCPRegInfo *regs, void *opaque); 2637 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2638 const ARMCPRegInfo *regs, void *opaque); 2639 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2640 { 2641 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2642 } 2643 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2644 { 2645 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2646 } 2647 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2648 2649 /* 2650 * Definition of an ARM co-processor register as viewed from 2651 * userspace. This is used for presenting sanitised versions of 2652 * registers to userspace when emulating the Linux AArch64 CPU 2653 * ID/feature ABI (advertised as HWCAP_CPUID). 2654 */ 2655 typedef struct ARMCPRegUserSpaceInfo { 2656 /* Name of register */ 2657 const char *name; 2658 2659 /* Is the name actually a glob pattern */ 2660 bool is_glob; 2661 2662 /* Only some bits are exported to user space */ 2663 uint64_t exported_bits; 2664 2665 /* Fixed bits are applied after the mask */ 2666 uint64_t fixed_bits; 2667 } ARMCPRegUserSpaceInfo; 2668 2669 #define REGUSERINFO_SENTINEL { .name = NULL } 2670 2671 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2672 2673 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2674 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2675 uint64_t value); 2676 /* CPReadFn that can be used for read-as-zero behaviour */ 2677 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2678 2679 /* CPResetFn that does nothing, for use if no reset is required even 2680 * if fieldoffset is non zero. 2681 */ 2682 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2683 2684 /* Return true if this reginfo struct's field in the cpu state struct 2685 * is 64 bits wide. 2686 */ 2687 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2688 { 2689 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2690 } 2691 2692 static inline bool cp_access_ok(int current_el, 2693 const ARMCPRegInfo *ri, int isread) 2694 { 2695 return (ri->access >> ((current_el * 2) + isread)) & 1; 2696 } 2697 2698 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2699 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2700 2701 /** 2702 * write_list_to_cpustate 2703 * @cpu: ARMCPU 2704 * 2705 * For each register listed in the ARMCPU cpreg_indexes list, write 2706 * its value from the cpreg_values list into the ARMCPUState structure. 2707 * This updates TCG's working data structures from KVM data or 2708 * from incoming migration state. 2709 * 2710 * Returns: true if all register values were updated correctly, 2711 * false if some register was unknown or could not be written. 2712 * Note that we do not stop early on failure -- we will attempt 2713 * writing all registers in the list. 2714 */ 2715 bool write_list_to_cpustate(ARMCPU *cpu); 2716 2717 /** 2718 * write_cpustate_to_list: 2719 * @cpu: ARMCPU 2720 * @kvm_sync: true if this is for syncing back to KVM 2721 * 2722 * For each register listed in the ARMCPU cpreg_indexes list, write 2723 * its value from the ARMCPUState structure into the cpreg_values list. 2724 * This is used to copy info from TCG's working data structures into 2725 * KVM or for outbound migration. 2726 * 2727 * @kvm_sync is true if we are doing this in order to sync the 2728 * register state back to KVM. In this case we will only update 2729 * values in the list if the previous list->cpustate sync actually 2730 * successfully wrote the CPU state. Otherwise we will keep the value 2731 * that is in the list. 2732 * 2733 * Returns: true if all register values were read correctly, 2734 * false if some register was unknown or could not be read. 2735 * Note that we do not stop early on failure -- we will attempt 2736 * reading all registers in the list. 2737 */ 2738 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2739 2740 #define ARM_CPUID_TI915T 0x54029152 2741 #define ARM_CPUID_TI925T 0x54029252 2742 2743 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2744 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2745 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2746 2747 #define cpu_signal_handler cpu_arm_signal_handler 2748 #define cpu_list arm_cpu_list 2749 2750 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2751 * 2752 * If EL3 is 64-bit: 2753 * + NonSecure EL1 & 0 stage 1 2754 * + NonSecure EL1 & 0 stage 2 2755 * + NonSecure EL2 2756 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2757 * + Secure EL1 & 0 2758 * + Secure EL3 2759 * If EL3 is 32-bit: 2760 * + NonSecure PL1 & 0 stage 1 2761 * + NonSecure PL1 & 0 stage 2 2762 * + NonSecure PL2 2763 * + Secure PL0 2764 * + Secure PL1 2765 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2766 * 2767 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2768 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2769 * because they may differ in access permissions even if the VA->PA map is 2770 * the same 2771 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2772 * translation, which means that we have one mmu_idx that deals with two 2773 * concatenated translation regimes [this sort of combined s1+2 TLB is 2774 * architecturally permitted] 2775 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2776 * handling via the TLB. The only way to do a stage 1 translation without 2777 * the immediate stage 2 translation is via the ATS or AT system insns, 2778 * which can be slow-pathed and always do a page table walk. 2779 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2780 * translation regimes, because they map reasonably well to each other 2781 * and they can't both be active at the same time. 2782 * 5. we want to be able to use the TLB for accesses done as part of a 2783 * stage1 page table walk, rather than having to walk the stage2 page 2784 * table over and over. 2785 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2786 * Never (PAN) bit within PSTATE. 2787 * 2788 * This gives us the following list of cases: 2789 * 2790 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 2791 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 2792 * NS EL1 EL1&0 stage 1+2 +PAN 2793 * NS EL0 EL2&0 2794 * NS EL2 EL2&0 +PAN 2795 * NS EL2 (aka NS PL2) 2796 * S EL0 EL1&0 (aka S PL0) 2797 * S EL1 EL1&0 (not used if EL3 is 32 bit) 2798 * S EL1 EL1&0 +PAN 2799 * S EL3 (aka S PL1) 2800 * NS EL1&0 stage 2 2801 * 2802 * for a total of 12 different mmu_idx. 2803 * 2804 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2805 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2806 * NS EL2 if we ever model a Cortex-R52). 2807 * 2808 * M profile CPUs are rather different as they do not have a true MMU. 2809 * They have the following different MMU indexes: 2810 * User 2811 * Privileged 2812 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2813 * Privileged, execution priority negative (ditto) 2814 * If the CPU supports the v8M Security Extension then there are also: 2815 * Secure User 2816 * Secure Privileged 2817 * Secure User, execution priority negative 2818 * Secure Privileged, execution priority negative 2819 * 2820 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2821 * are not quite the same -- different CPU types (most notably M profile 2822 * vs A/R profile) would like to use MMU indexes with different semantics, 2823 * but since we don't ever need to use all of those in a single CPU we 2824 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2825 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2826 * the same for any particular CPU. 2827 * Variables of type ARMMUIdx are always full values, and the core 2828 * index values are in variables of type 'int'. 2829 * 2830 * Our enumeration includes at the end some entries which are not "true" 2831 * mmu_idx values in that they don't have corresponding TLBs and are only 2832 * valid for doing slow path page table walks. 2833 * 2834 * The constant names here are patterned after the general style of the names 2835 * of the AT/ATS operations. 2836 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2837 * For M profile we arrange them to have a bit for priv, a bit for negpri 2838 * and a bit for secure. 2839 */ 2840 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2841 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2842 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2843 2844 /* Meanings of the bits for M profile mmu idx values */ 2845 #define ARM_MMU_IDX_M_PRIV 0x1 2846 #define ARM_MMU_IDX_M_NEGPRI 0x2 2847 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2848 2849 #define ARM_MMU_IDX_TYPE_MASK \ 2850 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2851 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2852 2853 typedef enum ARMMMUIdx { 2854 /* 2855 * A-profile. 2856 */ 2857 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2858 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2859 2860 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2861 ARMMMUIdx_E10_1_PAN = 3 | ARM_MMU_IDX_A, 2862 2863 ARMMMUIdx_E2 = 4 | ARM_MMU_IDX_A, 2864 ARMMMUIdx_E20_2 = 5 | ARM_MMU_IDX_A, 2865 ARMMMUIdx_E20_2_PAN = 6 | ARM_MMU_IDX_A, 2866 2867 ARMMMUIdx_SE10_0 = 7 | ARM_MMU_IDX_A, 2868 ARMMMUIdx_SE10_1 = 8 | ARM_MMU_IDX_A, 2869 ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A, 2870 ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A, 2871 2872 ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A, 2873 2874 /* 2875 * These are not allocated TLBs and are used only for AT system 2876 * instructions or for the first stage of an S12 page table walk. 2877 */ 2878 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2879 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2880 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2881 2882 /* 2883 * M-profile. 2884 */ 2885 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2886 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2887 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2888 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2889 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2890 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2891 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2892 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2893 } ARMMMUIdx; 2894 2895 /* 2896 * Bit macros for the core-mmu-index values for each index, 2897 * for use when calling tlb_flush_by_mmuidx() and friends. 2898 */ 2899 #define TO_CORE_BIT(NAME) \ 2900 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2901 2902 typedef enum ARMMMUIdxBit { 2903 TO_CORE_BIT(E10_0), 2904 TO_CORE_BIT(E20_0), 2905 TO_CORE_BIT(E10_1), 2906 TO_CORE_BIT(E10_1_PAN), 2907 TO_CORE_BIT(E2), 2908 TO_CORE_BIT(E20_2), 2909 TO_CORE_BIT(E20_2_PAN), 2910 TO_CORE_BIT(SE10_0), 2911 TO_CORE_BIT(SE10_1), 2912 TO_CORE_BIT(SE10_1_PAN), 2913 TO_CORE_BIT(SE3), 2914 TO_CORE_BIT(Stage2), 2915 2916 TO_CORE_BIT(MUser), 2917 TO_CORE_BIT(MPriv), 2918 TO_CORE_BIT(MUserNegPri), 2919 TO_CORE_BIT(MPrivNegPri), 2920 TO_CORE_BIT(MSUser), 2921 TO_CORE_BIT(MSPriv), 2922 TO_CORE_BIT(MSUserNegPri), 2923 TO_CORE_BIT(MSPrivNegPri), 2924 } ARMMMUIdxBit; 2925 2926 #undef TO_CORE_BIT 2927 2928 #define MMU_USER_IDX 0 2929 2930 /** 2931 * cpu_mmu_index: 2932 * @env: The cpu environment 2933 * @ifetch: True for code access, false for data access. 2934 * 2935 * Return the core mmu index for the current translation regime. 2936 * This function is used by generic TCG code paths. 2937 */ 2938 int cpu_mmu_index(CPUARMState *env, bool ifetch); 2939 2940 /* Indexes used when registering address spaces with cpu_address_space_init */ 2941 typedef enum ARMASIdx { 2942 ARMASIdx_NS = 0, 2943 ARMASIdx_S = 1, 2944 } ARMASIdx; 2945 2946 /* Return the Exception Level targeted by debug exceptions. */ 2947 static inline int arm_debug_target_el(CPUARMState *env) 2948 { 2949 bool secure = arm_is_secure(env); 2950 bool route_to_el2 = false; 2951 2952 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2953 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2954 env->cp15.mdcr_el2 & MDCR_TDE; 2955 } 2956 2957 if (route_to_el2) { 2958 return 2; 2959 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2960 !arm_el_is_aa64(env, 3) && secure) { 2961 return 3; 2962 } else { 2963 return 1; 2964 } 2965 } 2966 2967 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2968 { 2969 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2970 * CSSELR is RAZ/WI. 2971 */ 2972 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2973 } 2974 2975 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 2976 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2977 { 2978 int cur_el = arm_current_el(env); 2979 int debug_el; 2980 2981 if (cur_el == 3) { 2982 return false; 2983 } 2984 2985 /* MDCR_EL3.SDD disables debug events from Secure state */ 2986 if (arm_is_secure_below_el3(env) 2987 && extract32(env->cp15.mdcr_el3, 16, 1)) { 2988 return false; 2989 } 2990 2991 /* 2992 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 2993 * while not masking the (D)ebug bit in DAIF. 2994 */ 2995 debug_el = arm_debug_target_el(env); 2996 2997 if (cur_el == debug_el) { 2998 return extract32(env->cp15.mdscr_el1, 13, 1) 2999 && !(env->daif & PSTATE_D); 3000 } 3001 3002 /* Otherwise the debug target needs to be a higher EL */ 3003 return debug_el > cur_el; 3004 } 3005 3006 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 3007 { 3008 int el = arm_current_el(env); 3009 3010 if (el == 0 && arm_el_is_aa64(env, 1)) { 3011 return aa64_generate_debug_exceptions(env); 3012 } 3013 3014 if (arm_is_secure(env)) { 3015 int spd; 3016 3017 if (el == 0 && (env->cp15.sder & 1)) { 3018 /* SDER.SUIDEN means debug exceptions from Secure EL0 3019 * are always enabled. Otherwise they are controlled by 3020 * SDCR.SPD like those from other Secure ELs. 3021 */ 3022 return true; 3023 } 3024 3025 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3026 switch (spd) { 3027 case 1: 3028 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3029 case 0: 3030 /* For 0b00 we return true if external secure invasive debug 3031 * is enabled. On real hardware this is controlled by external 3032 * signals to the core. QEMU always permits debug, and behaves 3033 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3034 */ 3035 return true; 3036 case 2: 3037 return false; 3038 case 3: 3039 return true; 3040 } 3041 } 3042 3043 return el != 2; 3044 } 3045 3046 /* Return true if debugging exceptions are currently enabled. 3047 * This corresponds to what in ARM ARM pseudocode would be 3048 * if UsingAArch32() then 3049 * return AArch32.GenerateDebugExceptions() 3050 * else 3051 * return AArch64.GenerateDebugExceptions() 3052 * We choose to push the if() down into this function for clarity, 3053 * since the pseudocode has it at all callsites except for the one in 3054 * CheckSoftwareStep(), where it is elided because both branches would 3055 * always return the same value. 3056 */ 3057 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3058 { 3059 if (env->aarch64) { 3060 return aa64_generate_debug_exceptions(env); 3061 } else { 3062 return aa32_generate_debug_exceptions(env); 3063 } 3064 } 3065 3066 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3067 * implicitly means this always returns false in pre-v8 CPUs.) 3068 */ 3069 static inline bool arm_singlestep_active(CPUARMState *env) 3070 { 3071 return extract32(env->cp15.mdscr_el1, 0, 1) 3072 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3073 && arm_generate_debug_exceptions(env); 3074 } 3075 3076 static inline bool arm_sctlr_b(CPUARMState *env) 3077 { 3078 return 3079 /* We need not implement SCTLR.ITD in user-mode emulation, so 3080 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3081 * This lets people run BE32 binaries with "-cpu any". 3082 */ 3083 #ifndef CONFIG_USER_ONLY 3084 !arm_feature(env, ARM_FEATURE_V7) && 3085 #endif 3086 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3087 } 3088 3089 uint64_t arm_sctlr(CPUARMState *env, int el); 3090 3091 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3092 bool sctlr_b) 3093 { 3094 #ifdef CONFIG_USER_ONLY 3095 /* 3096 * In system mode, BE32 is modelled in line with the 3097 * architecture (as word-invariant big-endianness), where loads 3098 * and stores are done little endian but from addresses which 3099 * are adjusted by XORing with the appropriate constant. So the 3100 * endianness to use for the raw data access is not affected by 3101 * SCTLR.B. 3102 * In user mode, however, we model BE32 as byte-invariant 3103 * big-endianness (because user-only code cannot tell the 3104 * difference), and so we need to use a data access endianness 3105 * that depends on SCTLR.B. 3106 */ 3107 if (sctlr_b) { 3108 return true; 3109 } 3110 #endif 3111 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3112 return env->uncached_cpsr & CPSR_E; 3113 } 3114 3115 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3116 { 3117 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3118 } 3119 3120 /* Return true if the processor is in big-endian mode. */ 3121 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3122 { 3123 if (!is_a64(env)) { 3124 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3125 } else { 3126 int cur_el = arm_current_el(env); 3127 uint64_t sctlr = arm_sctlr(env, cur_el); 3128 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3129 } 3130 } 3131 3132 typedef CPUARMState CPUArchState; 3133 typedef ARMCPU ArchCPU; 3134 3135 #include "exec/cpu-all.h" 3136 3137 /* 3138 * Bit usage in the TB flags field: bit 31 indicates whether we are 3139 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 3140 * We put flags which are shared between 32 and 64 bit mode at the top 3141 * of the word, and flags which apply to only one mode at the bottom. 3142 * 3143 * 31 20 18 14 9 0 3144 * +--------------+-----+-----+----------+--------------+ 3145 * | | | TBFLAG_A32 | | 3146 * | | +-----+----------+ TBFLAG_AM32 | 3147 * | TBFLAG_ANY | |TBFLAG_M32| | 3148 * | | +-+----------+--------------| 3149 * | | | TBFLAG_A64 | 3150 * +--------------+---------+---------------------------+ 3151 * 31 20 15 0 3152 * 3153 * Unless otherwise noted, these bits are cached in env->hflags. 3154 */ 3155 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3156 FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) 3157 FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */ 3158 FIELD(TBFLAG_ANY, BE_DATA, 28, 1) 3159 FIELD(TBFLAG_ANY, MMUIDX, 24, 4) 3160 /* Target EL if we take a floating-point-disabled exception */ 3161 FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2) 3162 /* For A-profile only, target EL for debug exceptions. */ 3163 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) 3164 3165 /* 3166 * Bit usage when in AArch32 state, both A- and M-profile. 3167 */ 3168 FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */ 3169 FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */ 3170 3171 /* 3172 * Bit usage when in AArch32 state, for A-profile only. 3173 */ 3174 FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */ 3175 FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ 3176 /* 3177 * We store the bottom two bits of the CPAR as TB flags and handle 3178 * checks on the other bits at runtime. This shares the same bits as 3179 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3180 * Not cached, because VECLEN+VECSTRIDE are not cached. 3181 */ 3182 FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) 3183 FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */ 3184 FIELD(TBFLAG_A32, SCTLR_B, 15, 1) 3185 FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) 3186 /* 3187 * Indicates whether cp register reads and writes by guest code should access 3188 * the secure or nonsecure bank of banked registers; note that this is not 3189 * the same thing as the current security state of the processor! 3190 */ 3191 FIELD(TBFLAG_A32, NS, 17, 1) 3192 3193 /* 3194 * Bit usage when in AArch32 state, for M-profile only. 3195 */ 3196 /* Handler (ie not Thread) mode */ 3197 FIELD(TBFLAG_M32, HANDLER, 9, 1) 3198 /* Whether we should generate stack-limit checks */ 3199 FIELD(TBFLAG_M32, STACKCHECK, 10, 1) 3200 /* Set if FPCCR.LSPACT is set */ 3201 FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */ 3202 /* Set if we must create a new FP context */ 3203 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */ 3204 /* Set if FPCCR.S does not match current security state */ 3205 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */ 3206 3207 /* 3208 * Bit usage when in AArch64 state 3209 */ 3210 FIELD(TBFLAG_A64, TBII, 0, 2) 3211 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3212 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3213 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3214 FIELD(TBFLAG_A64, BT, 9, 1) 3215 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3216 FIELD(TBFLAG_A64, TBID, 12, 2) 3217 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3218 3219 static inline bool bswap_code(bool sctlr_b) 3220 { 3221 #ifdef CONFIG_USER_ONLY 3222 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3223 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3224 * would also end up as a mixed-endian mode with BE code, LE data. 3225 */ 3226 return 3227 #ifdef TARGET_WORDS_BIGENDIAN 3228 1 ^ 3229 #endif 3230 sctlr_b; 3231 #else 3232 /* All code access in ARM is little endian, and there are no loaders 3233 * doing swaps that need to be reversed 3234 */ 3235 return 0; 3236 #endif 3237 } 3238 3239 #ifdef CONFIG_USER_ONLY 3240 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3241 { 3242 return 3243 #ifdef TARGET_WORDS_BIGENDIAN 3244 1 ^ 3245 #endif 3246 arm_cpu_data_is_big_endian(env); 3247 } 3248 #endif 3249 3250 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3251 target_ulong *cs_base, uint32_t *flags); 3252 3253 enum { 3254 QEMU_PSCI_CONDUIT_DISABLED = 0, 3255 QEMU_PSCI_CONDUIT_SMC = 1, 3256 QEMU_PSCI_CONDUIT_HVC = 2, 3257 }; 3258 3259 #ifndef CONFIG_USER_ONLY 3260 /* Return the address space index to use for a memory access */ 3261 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3262 { 3263 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3264 } 3265 3266 /* Return the AddressSpace to use for a memory access 3267 * (which depends on whether the access is S or NS, and whether 3268 * the board gave us a separate AddressSpace for S accesses). 3269 */ 3270 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3271 { 3272 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3273 } 3274 #endif 3275 3276 /** 3277 * arm_register_pre_el_change_hook: 3278 * Register a hook function which will be called immediately before this 3279 * CPU changes exception level or mode. The hook function will be 3280 * passed a pointer to the ARMCPU and the opaque data pointer passed 3281 * to this function when the hook was registered. 3282 * 3283 * Note that if a pre-change hook is called, any registered post-change hooks 3284 * are guaranteed to subsequently be called. 3285 */ 3286 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3287 void *opaque); 3288 /** 3289 * arm_register_el_change_hook: 3290 * Register a hook function which will be called immediately after this 3291 * CPU changes exception level or mode. The hook function will be 3292 * passed a pointer to the ARMCPU and the opaque data pointer passed 3293 * to this function when the hook was registered. 3294 * 3295 * Note that any registered hooks registered here are guaranteed to be called 3296 * if pre-change hooks have been. 3297 */ 3298 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3299 *opaque); 3300 3301 /** 3302 * arm_rebuild_hflags: 3303 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3304 */ 3305 void arm_rebuild_hflags(CPUARMState *env); 3306 3307 /** 3308 * aa32_vfp_dreg: 3309 * Return a pointer to the Dn register within env in 32-bit mode. 3310 */ 3311 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3312 { 3313 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3314 } 3315 3316 /** 3317 * aa32_vfp_qreg: 3318 * Return a pointer to the Qn register within env in 32-bit mode. 3319 */ 3320 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3321 { 3322 return &env->vfp.zregs[regno].d[0]; 3323 } 3324 3325 /** 3326 * aa64_vfp_qreg: 3327 * Return a pointer to the Qn register within env in 64-bit mode. 3328 */ 3329 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3330 { 3331 return &env->vfp.zregs[regno].d[0]; 3332 } 3333 3334 /* Shared between translate-sve.c and sve_helper.c. */ 3335 extern const uint64_t pred_esz_masks[4]; 3336 3337 /* 3338 * Naming convention for isar_feature functions: 3339 * Functions which test 32-bit ID registers should have _aa32_ in 3340 * their name. Functions which test 64-bit ID registers should have 3341 * _aa64_ in their name. These must only be used in code where we 3342 * know for certain that the CPU has AArch32 or AArch64 respectively 3343 * or where the correct answer for a CPU which doesn't implement that 3344 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3345 * system registers that are specific to that CPU state, for "should 3346 * we let this system register bit be set" tests where the 32-bit 3347 * flavour of the register doesn't have the bit, and so on). 3348 * Functions which simply ask "does this feature exist at all" have 3349 * _any_ in their name, and always return the logical OR of the _aa64_ 3350 * and the _aa32_ function. 3351 */ 3352 3353 /* 3354 * 32-bit feature tests via id registers. 3355 */ 3356 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3357 { 3358 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3359 } 3360 3361 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3362 { 3363 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3364 } 3365 3366 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3367 { 3368 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3369 } 3370 3371 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3372 { 3373 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3374 } 3375 3376 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3377 { 3378 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3379 } 3380 3381 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3382 { 3383 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3384 } 3385 3386 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3387 { 3388 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3389 } 3390 3391 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3392 { 3393 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3394 } 3395 3396 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3397 { 3398 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3399 } 3400 3401 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3402 { 3403 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3404 } 3405 3406 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3407 { 3408 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3409 } 3410 3411 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3412 { 3413 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3414 } 3415 3416 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3417 { 3418 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3419 } 3420 3421 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3422 { 3423 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3424 } 3425 3426 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3427 { 3428 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3429 } 3430 3431 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3432 { 3433 /* 3434 * This is a placeholder for use by VCMA until the rest of 3435 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3436 * At which point we can properly set and check MVFR1.FPHP. 3437 */ 3438 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3439 } 3440 3441 static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id) 3442 { 3443 /* Return true if D16-D31 are implemented */ 3444 return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >= 2; 3445 } 3446 3447 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3448 { 3449 return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0; 3450 } 3451 3452 static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) 3453 { 3454 /* Return true if CPU supports double precision floating point */ 3455 return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0; 3456 } 3457 3458 /* 3459 * We always set the FP and SIMD FP16 fields to indicate identical 3460 * levels of support (assuming SIMD is implemented at all), so 3461 * we only need one set of accessors. 3462 */ 3463 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3464 { 3465 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0; 3466 } 3467 3468 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3469 { 3470 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; 3471 } 3472 3473 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3474 { 3475 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1; 3476 } 3477 3478 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3479 { 3480 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2; 3481 } 3482 3483 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3484 { 3485 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3; 3486 } 3487 3488 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3489 { 3490 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; 3491 } 3492 3493 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3494 { 3495 return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0; 3496 } 3497 3498 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3499 { 3500 return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2; 3501 } 3502 3503 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3504 { 3505 /* 0xf means "non-standard IMPDEF PMU" */ 3506 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3507 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3508 } 3509 3510 /* 3511 * 64-bit feature tests via id registers. 3512 */ 3513 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3514 { 3515 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3516 } 3517 3518 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3519 { 3520 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3521 } 3522 3523 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3524 { 3525 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3526 } 3527 3528 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3529 { 3530 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3531 } 3532 3533 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3534 { 3535 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3536 } 3537 3538 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3539 { 3540 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3541 } 3542 3543 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3544 { 3545 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3546 } 3547 3548 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3549 { 3550 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3551 } 3552 3553 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3554 { 3555 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3556 } 3557 3558 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3559 { 3560 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3561 } 3562 3563 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3564 { 3565 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3566 } 3567 3568 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3569 { 3570 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3571 } 3572 3573 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3574 { 3575 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3576 } 3577 3578 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3579 { 3580 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3581 } 3582 3583 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3584 { 3585 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3586 } 3587 3588 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3589 { 3590 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3591 } 3592 3593 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3594 { 3595 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3596 } 3597 3598 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3599 { 3600 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3601 } 3602 3603 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3604 { 3605 /* 3606 * Note that while QEMU will only implement the architected algorithm 3607 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation 3608 * defined algorithms, and thus API+GPI, and this predicate controls 3609 * migration of the 128-bit keys. 3610 */ 3611 return (id->id_aa64isar1 & 3612 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3613 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3614 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3615 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3616 } 3617 3618 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3619 { 3620 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3621 } 3622 3623 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3624 { 3625 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3626 } 3627 3628 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3629 { 3630 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3631 } 3632 3633 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3634 { 3635 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3636 } 3637 3638 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3639 { 3640 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3641 } 3642 3643 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3644 { 3645 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3646 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3647 } 3648 3649 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3650 { 3651 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3652 } 3653 3654 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3655 { 3656 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3657 } 3658 3659 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3660 { 3661 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3662 } 3663 3664 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3665 { 3666 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3667 } 3668 3669 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3670 { 3671 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3672 } 3673 3674 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3675 { 3676 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3677 } 3678 3679 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 3680 { 3681 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 3682 } 3683 3684 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3685 { 3686 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3687 } 3688 3689 /* 3690 * Feature tests for "does this exist in either 32-bit or 64-bit?" 3691 */ 3692 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 3693 { 3694 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 3695 } 3696 3697 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 3698 { 3699 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 3700 } 3701 3702 /* 3703 * Forward to the above feature tests given an ARMCPU pointer. 3704 */ 3705 #define cpu_isar_feature(name, cpu) \ 3706 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3707 3708 #endif 3709