xref: /openbmc/qemu/target/arm/cpu.h (revision 9ea2e69f)
1 /*
2  * ARM virtual CPU header
3  *
4  *  Copyright (c) 2003 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef ARM_CPU_H
21 #define ARM_CPU_H
22 
23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
25 #include "hw/registerfields.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-defs.h"
28 #include "qapi/qapi-types-common.h"
29 
30 /* ARM processors have a weak memory model */
31 #define TCG_GUEST_DEFAULT_MO      (0)
32 
33 #ifdef TARGET_AARCH64
34 #define KVM_HAVE_MCE_INJECTION 1
35 #endif
36 
37 #define EXCP_UDEF            1   /* undefined instruction */
38 #define EXCP_SWI             2   /* software interrupt */
39 #define EXCP_PREFETCH_ABORT  3
40 #define EXCP_DATA_ABORT      4
41 #define EXCP_IRQ             5
42 #define EXCP_FIQ             6
43 #define EXCP_BKPT            7
44 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
45 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
46 #define EXCP_HVC            11   /* HyperVisor Call */
47 #define EXCP_HYP_TRAP       12
48 #define EXCP_SMC            13   /* Secure Monitor Call */
49 #define EXCP_VIRQ           14
50 #define EXCP_VFIQ           15
51 #define EXCP_SEMIHOST       16   /* semihosting call */
52 #define EXCP_NOCP           17   /* v7M NOCP UsageFault */
53 #define EXCP_INVSTATE       18   /* v7M INVSTATE UsageFault */
54 #define EXCP_STKOF          19   /* v8M STKOF UsageFault */
55 #define EXCP_LAZYFP         20   /* v7M fault during lazy FP stacking */
56 #define EXCP_LSERR          21   /* v8M LSERR SecureFault */
57 #define EXCP_UNALIGNED      22   /* v7M UNALIGNED UsageFault */
58 #define EXCP_DIVBYZERO      23   /* v7M DIVBYZERO UsageFault */
59 #define EXCP_VSERR          24
60 #define EXCP_GPC            25   /* v9 Granule Protection Check Fault */
61 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
62 
63 #define ARMV7M_EXCP_RESET   1
64 #define ARMV7M_EXCP_NMI     2
65 #define ARMV7M_EXCP_HARD    3
66 #define ARMV7M_EXCP_MEM     4
67 #define ARMV7M_EXCP_BUS     5
68 #define ARMV7M_EXCP_USAGE   6
69 #define ARMV7M_EXCP_SECURE  7
70 #define ARMV7M_EXCP_SVC     11
71 #define ARMV7M_EXCP_DEBUG   12
72 #define ARMV7M_EXCP_PENDSV  14
73 #define ARMV7M_EXCP_SYSTICK 15
74 
75 /* For M profile, some registers are banked secure vs non-secure;
76  * these are represented as a 2-element array where the first element
77  * is the non-secure copy and the second is the secure copy.
78  * When the CPU does not have implement the security extension then
79  * only the first element is used.
80  * This means that the copy for the current security state can be
81  * accessed via env->registerfield[env->v7m.secure] (whether the security
82  * extension is implemented or not).
83  */
84 enum {
85     M_REG_NS = 0,
86     M_REG_S = 1,
87     M_REG_NUM_BANKS = 2,
88 };
89 
90 /* ARM-specific interrupt pending bits.  */
91 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
92 #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
93 #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
94 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
95 
96 /* The usual mapping for an AArch64 system register to its AArch32
97  * counterpart is for the 32 bit world to have access to the lower
98  * half only (with writes leaving the upper half untouched). It's
99  * therefore useful to be able to pass TCG the offset of the least
100  * significant half of a uint64_t struct member.
101  */
102 #if HOST_BIG_ENDIAN
103 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
104 #define offsetofhigh32(S, M) offsetof(S, M)
105 #else
106 #define offsetoflow32(S, M) offsetof(S, M)
107 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
108 #endif
109 
110 /* Meanings of the ARMCPU object's four inbound GPIO lines */
111 #define ARM_CPU_IRQ 0
112 #define ARM_CPU_FIQ 1
113 #define ARM_CPU_VIRQ 2
114 #define ARM_CPU_VFIQ 3
115 
116 /* ARM-specific extra insn start words:
117  * 1: Conditional execution bits
118  * 2: Partial exception syndrome for data aborts
119  */
120 #define TARGET_INSN_START_EXTRA_WORDS 2
121 
122 /* The 2nd extra word holding syndrome info for data aborts does not use
123  * the upper 6 bits nor the lower 14 bits. We mask and shift it down to
124  * help the sleb128 encoder do a better job.
125  * When restoring the CPU state, we shift it back up.
126  */
127 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
128 #define ARM_INSN_START_WORD2_SHIFT 14
129 
130 /* We currently assume float and double are IEEE single and double
131    precision respectively.
132    Doing runtime conversions is tricky because VFP registers may contain
133    integer values (eg. as the result of a FTOSI instruction).
134    s<2n> maps to the least significant half of d<n>
135    s<2n+1> maps to the most significant half of d<n>
136  */
137 
138 /**
139  * DynamicGDBXMLInfo:
140  * @desc: Contains the XML descriptions.
141  * @num: Number of the registers in this XML seen by GDB.
142  * @data: A union with data specific to the set of registers
143  *    @cpregs_keys: Array that contains the corresponding Key of
144  *                  a given cpreg with the same order of the cpreg
145  *                  in the XML description.
146  */
147 typedef struct DynamicGDBXMLInfo {
148     char *desc;
149     int num;
150     union {
151         struct {
152             uint32_t *keys;
153         } cpregs;
154     } data;
155 } DynamicGDBXMLInfo;
156 
157 /* CPU state for each instance of a generic timer (in cp15 c14) */
158 typedef struct ARMGenericTimer {
159     uint64_t cval; /* Timer CompareValue register */
160     uint64_t ctl; /* Timer Control register */
161 } ARMGenericTimer;
162 
163 #define GTIMER_PHYS     0
164 #define GTIMER_VIRT     1
165 #define GTIMER_HYP      2
166 #define GTIMER_SEC      3
167 #define GTIMER_HYPVIRT  4
168 #define NUM_GTIMERS     5
169 
170 #define VTCR_NSW (1u << 29)
171 #define VTCR_NSA (1u << 30)
172 #define VSTCR_SW VTCR_NSW
173 #define VSTCR_SA VTCR_NSA
174 
175 /* Define a maximum sized vector register.
176  * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
177  * For 64-bit, this is a 2048-bit SVE register.
178  *
179  * Note that the mapping between S, D, and Q views of the register bank
180  * differs between AArch64 and AArch32.
181  * In AArch32:
182  *  Qn = regs[n].d[1]:regs[n].d[0]
183  *  Dn = regs[n / 2].d[n & 1]
184  *  Sn = regs[n / 4].d[n % 4 / 2],
185  *       bits 31..0 for even n, and bits 63..32 for odd n
186  *       (and regs[16] to regs[31] are inaccessible)
187  * In AArch64:
188  *  Zn = regs[n].d[*]
189  *  Qn = regs[n].d[1]:regs[n].d[0]
190  *  Dn = regs[n].d[0]
191  *  Sn = regs[n].d[0] bits 31..0
192  *  Hn = regs[n].d[0] bits 15..0
193  *
194  * This corresponds to the architecturally defined mapping between
195  * the two execution states, and means we do not need to explicitly
196  * map these registers when changing states.
197  *
198  * Align the data for use with TCG host vector operations.
199  */
200 
201 #ifdef TARGET_AARCH64
202 # define ARM_MAX_VQ    16
203 #else
204 # define ARM_MAX_VQ    1
205 #endif
206 
207 typedef struct ARMVectorReg {
208     uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
209 } ARMVectorReg;
210 
211 #ifdef TARGET_AARCH64
212 /* In AArch32 mode, predicate registers do not exist at all.  */
213 typedef struct ARMPredicateReg {
214     uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
215 } ARMPredicateReg;
216 
217 /* In AArch32 mode, PAC keys do not exist at all.  */
218 typedef struct ARMPACKey {
219     uint64_t lo, hi;
220 } ARMPACKey;
221 #endif
222 
223 /* See the commentary above the TBFLAG field definitions.  */
224 typedef struct CPUARMTBFlags {
225     uint32_t flags;
226     target_ulong flags2;
227 } CPUARMTBFlags;
228 
229 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
230 
231 typedef struct NVICState NVICState;
232 
233 typedef struct CPUArchState {
234     /* Regs for current mode.  */
235     uint32_t regs[16];
236 
237     /* 32/64 switch only happens when taking and returning from
238      * exceptions so the overlap semantics are taken care of then
239      * instead of having a complicated union.
240      */
241     /* Regs for A64 mode.  */
242     uint64_t xregs[32];
243     uint64_t pc;
244     /* PSTATE isn't an architectural register for ARMv8. However, it is
245      * convenient for us to assemble the underlying state into a 32 bit format
246      * identical to the architectural format used for the SPSR. (This is also
247      * what the Linux kernel's 'pstate' field in signal handlers and KVM's
248      * 'pstate' register are.) Of the PSTATE bits:
249      *  NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
250      *    semantics as for AArch32, as described in the comments on each field)
251      *  nRW (also known as M[4]) is kept, inverted, in env->aarch64
252      *  DAIF (exception masks) are kept in env->daif
253      *  BTYPE is kept in env->btype
254      *  SM and ZA are kept in env->svcr
255      *  all other bits are stored in their correct places in env->pstate
256      */
257     uint32_t pstate;
258     bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */
259     bool thumb;   /* True if CPU is in thumb mode; cpsr[5] */
260 
261     /* Cached TBFLAGS state.  See below for which bits are included.  */
262     CPUARMTBFlags hflags;
263 
264     /* Frequently accessed CPSR bits are stored separately for efficiency.
265        This contains all the other bits.  Use cpsr_{read,write} to access
266        the whole CPSR.  */
267     uint32_t uncached_cpsr;
268     uint32_t spsr;
269 
270     /* Banked registers.  */
271     uint64_t banked_spsr[8];
272     uint32_t banked_r13[8];
273     uint32_t banked_r14[8];
274 
275     /* These hold r8-r12.  */
276     uint32_t usr_regs[5];
277     uint32_t fiq_regs[5];
278 
279     /* cpsr flag cache for faster execution */
280     uint32_t CF; /* 0 or 1 */
281     uint32_t VF; /* V is the bit 31. All other bits are undefined */
282     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
283     uint32_t ZF; /* Z set if zero.  */
284     uint32_t QF; /* 0 or 1 */
285     uint32_t GE; /* cpsr[19:16] */
286     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
287     uint32_t btype;  /* BTI branch type.  spsr[11:10].  */
288     uint64_t daif; /* exception masks, in the bits they are in PSTATE */
289     uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */
290 
291     uint64_t elr_el[4]; /* AArch64 exception link regs  */
292     uint64_t sp_el[4]; /* AArch64 banked stack pointers */
293 
294     /* System control coprocessor (cp15) */
295     struct {
296         uint32_t c0_cpuid;
297         union { /* Cache size selection */
298             struct {
299                 uint64_t _unused_csselr0;
300                 uint64_t csselr_ns;
301                 uint64_t _unused_csselr1;
302                 uint64_t csselr_s;
303             };
304             uint64_t csselr_el[4];
305         };
306         union { /* System control register. */
307             struct {
308                 uint64_t _unused_sctlr;
309                 uint64_t sctlr_ns;
310                 uint64_t hsctlr;
311                 uint64_t sctlr_s;
312             };
313             uint64_t sctlr_el[4];
314         };
315         uint64_t vsctlr; /* Virtualization System control register. */
316         uint64_t cpacr_el1; /* Architectural feature access control register */
317         uint64_t cptr_el[4];  /* ARMv8 feature trap registers */
318         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
319         uint64_t sder; /* Secure debug enable register. */
320         uint32_t nsacr; /* Non-secure access control register. */
321         union { /* MMU translation table base 0. */
322             struct {
323                 uint64_t _unused_ttbr0_0;
324                 uint64_t ttbr0_ns;
325                 uint64_t _unused_ttbr0_1;
326                 uint64_t ttbr0_s;
327             };
328             uint64_t ttbr0_el[4];
329         };
330         union { /* MMU translation table base 1. */
331             struct {
332                 uint64_t _unused_ttbr1_0;
333                 uint64_t ttbr1_ns;
334                 uint64_t _unused_ttbr1_1;
335                 uint64_t ttbr1_s;
336             };
337             uint64_t ttbr1_el[4];
338         };
339         uint64_t vttbr_el2; /* Virtualization Translation Table Base.  */
340         uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */
341         /* MMU translation table base control. */
342         uint64_t tcr_el[4];
343         uint64_t vtcr_el2; /* Virtualization Translation Control.  */
344         uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */
345         uint32_t c2_data; /* MPU data cacheable bits.  */
346         uint32_t c2_insn; /* MPU instruction cacheable bits.  */
347         union { /* MMU domain access control register
348                  * MPU write buffer control.
349                  */
350             struct {
351                 uint64_t dacr_ns;
352                 uint64_t dacr_s;
353             };
354             struct {
355                 uint64_t dacr32_el2;
356             };
357         };
358         uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
359         uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
360         uint64_t hcr_el2; /* Hypervisor configuration register */
361         uint64_t hcrx_el2; /* Extended Hypervisor configuration register */
362         uint64_t scr_el3; /* Secure configuration register.  */
363         union { /* Fault status registers.  */
364             struct {
365                 uint64_t ifsr_ns;
366                 uint64_t ifsr_s;
367             };
368             struct {
369                 uint64_t ifsr32_el2;
370             };
371         };
372         union {
373             struct {
374                 uint64_t _unused_dfsr;
375                 uint64_t dfsr_ns;
376                 uint64_t hsr;
377                 uint64_t dfsr_s;
378             };
379             uint64_t esr_el[4];
380         };
381         uint32_t c6_region[8]; /* MPU base/size registers.  */
382         union { /* Fault address registers. */
383             struct {
384                 uint64_t _unused_far0;
385 #if HOST_BIG_ENDIAN
386                 uint32_t ifar_ns;
387                 uint32_t dfar_ns;
388                 uint32_t ifar_s;
389                 uint32_t dfar_s;
390 #else
391                 uint32_t dfar_ns;
392                 uint32_t ifar_ns;
393                 uint32_t dfar_s;
394                 uint32_t ifar_s;
395 #endif
396                 uint64_t _unused_far3;
397             };
398             uint64_t far_el[4];
399         };
400         uint64_t hpfar_el2;
401         uint64_t hstr_el2;
402         union { /* Translation result. */
403             struct {
404                 uint64_t _unused_par_0;
405                 uint64_t par_ns;
406                 uint64_t _unused_par_1;
407                 uint64_t par_s;
408             };
409             uint64_t par_el[4];
410         };
411 
412         uint32_t c9_insn; /* Cache lockdown registers.  */
413         uint32_t c9_data;
414         uint64_t c9_pmcr; /* performance monitor control register */
415         uint64_t c9_pmcnten; /* perf monitor counter enables */
416         uint64_t c9_pmovsr; /* perf monitor overflow status */
417         uint64_t c9_pmuserenr; /* perf monitor user enable */
418         uint64_t c9_pmselr; /* perf monitor counter selection register */
419         uint64_t c9_pminten; /* perf monitor interrupt enables */
420         union { /* Memory attribute redirection */
421             struct {
422 #if HOST_BIG_ENDIAN
423                 uint64_t _unused_mair_0;
424                 uint32_t mair1_ns;
425                 uint32_t mair0_ns;
426                 uint64_t _unused_mair_1;
427                 uint32_t mair1_s;
428                 uint32_t mair0_s;
429 #else
430                 uint64_t _unused_mair_0;
431                 uint32_t mair0_ns;
432                 uint32_t mair1_ns;
433                 uint64_t _unused_mair_1;
434                 uint32_t mair0_s;
435                 uint32_t mair1_s;
436 #endif
437             };
438             uint64_t mair_el[4];
439         };
440         union { /* vector base address register */
441             struct {
442                 uint64_t _unused_vbar;
443                 uint64_t vbar_ns;
444                 uint64_t hvbar;
445                 uint64_t vbar_s;
446             };
447             uint64_t vbar_el[4];
448         };
449         uint32_t mvbar; /* (monitor) vector base address register */
450         uint64_t rvbar; /* rvbar sampled from rvbar property at reset */
451         struct { /* FCSE PID. */
452             uint32_t fcseidr_ns;
453             uint32_t fcseidr_s;
454         };
455         union { /* Context ID. */
456             struct {
457                 uint64_t _unused_contextidr_0;
458                 uint64_t contextidr_ns;
459                 uint64_t _unused_contextidr_1;
460                 uint64_t contextidr_s;
461             };
462             uint64_t contextidr_el[4];
463         };
464         union { /* User RW Thread register. */
465             struct {
466                 uint64_t tpidrurw_ns;
467                 uint64_t tpidrprw_ns;
468                 uint64_t htpidr;
469                 uint64_t _tpidr_el3;
470             };
471             uint64_t tpidr_el[4];
472         };
473         uint64_t tpidr2_el0;
474         /* The secure banks of these registers don't map anywhere */
475         uint64_t tpidrurw_s;
476         uint64_t tpidrprw_s;
477         uint64_t tpidruro_s;
478 
479         union { /* User RO Thread register. */
480             uint64_t tpidruro_ns;
481             uint64_t tpidrro_el[1];
482         };
483         uint64_t c14_cntfrq; /* Counter Frequency register */
484         uint64_t c14_cntkctl; /* Timer Control register */
485         uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
486         uint64_t cntvoff_el2; /* Counter Virtual Offset register */
487         ARMGenericTimer c14_timer[NUM_GTIMERS];
488         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
489         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
490         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
491         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
492         uint32_t c15_threadid; /* TI debugger thread-ID.  */
493         uint32_t c15_config_base_address; /* SCU base address.  */
494         uint32_t c15_diagnostic; /* diagnostic register */
495         uint32_t c15_power_diagnostic;
496         uint32_t c15_power_control; /* power control */
497         uint64_t dbgbvr[16]; /* breakpoint value registers */
498         uint64_t dbgbcr[16]; /* breakpoint control registers */
499         uint64_t dbgwvr[16]; /* watchpoint value registers */
500         uint64_t dbgwcr[16]; /* watchpoint control registers */
501         uint64_t dbgclaim;   /* DBGCLAIM bits */
502         uint64_t mdscr_el1;
503         uint64_t oslsr_el1; /* OS Lock Status */
504         uint64_t osdlr_el1; /* OS DoubleLock status */
505         uint64_t mdcr_el2;
506         uint64_t mdcr_el3;
507         /* Stores the architectural value of the counter *the last time it was
508          * updated* by pmccntr_op_start. Accesses should always be surrounded
509          * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
510          * architecturally-correct value is being read/set.
511          */
512         uint64_t c15_ccnt;
513         /* Stores the delta between the architectural value and the underlying
514          * cycle count during normal operation. It is used to update c15_ccnt
515          * to be the correct architectural value before accesses. During
516          * accesses, c15_ccnt_delta contains the underlying count being used
517          * for the access, after which it reverts to the delta value in
518          * pmccntr_op_finish.
519          */
520         uint64_t c15_ccnt_delta;
521         uint64_t c14_pmevcntr[31];
522         uint64_t c14_pmevcntr_delta[31];
523         uint64_t c14_pmevtyper[31];
524         uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
525         uint64_t vpidr_el2; /* Virtualization Processor ID Register */
526         uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
527         uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0.  */
528         uint64_t gcr_el1;
529         uint64_t rgsr_el1;
530 
531         /* Minimal RAS registers */
532         uint64_t disr_el1;
533         uint64_t vdisr_el2;
534         uint64_t vsesr_el2;
535 
536         /*
537          * Fine-Grained Trap registers. We store these as arrays so the
538          * access checking code doesn't have to manually select
539          * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test.
540          * FEAT_FGT2 will add more elements to these arrays.
541          */
542         uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
543         uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
544         uint64_t fgt_exec[1]; /* HFGITR */
545 
546         /* RME registers */
547         uint64_t gpccr_el3;
548         uint64_t gptbr_el3;
549         uint64_t mfar_el3;
550     } cp15;
551 
552     struct {
553         /* M profile has up to 4 stack pointers:
554          * a Main Stack Pointer and a Process Stack Pointer for each
555          * of the Secure and Non-Secure states. (If the CPU doesn't support
556          * the security extension then it has only two SPs.)
557          * In QEMU we always store the currently active SP in regs[13],
558          * and the non-active SP for the current security state in
559          * v7m.other_sp. The stack pointers for the inactive security state
560          * are stored in other_ss_msp and other_ss_psp.
561          * switch_v7m_security_state() is responsible for rearranging them
562          * when we change security state.
563          */
564         uint32_t other_sp;
565         uint32_t other_ss_msp;
566         uint32_t other_ss_psp;
567         uint32_t vecbase[M_REG_NUM_BANKS];
568         uint32_t basepri[M_REG_NUM_BANKS];
569         uint32_t control[M_REG_NUM_BANKS];
570         uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
571         uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
572         uint32_t hfsr; /* HardFault Status */
573         uint32_t dfsr; /* Debug Fault Status Register */
574         uint32_t sfsr; /* Secure Fault Status Register */
575         uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
576         uint32_t bfar; /* BusFault Address */
577         uint32_t sfar; /* Secure Fault Address Register */
578         unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
579         int exception;
580         uint32_t primask[M_REG_NUM_BANKS];
581         uint32_t faultmask[M_REG_NUM_BANKS];
582         uint32_t aircr; /* only holds r/w state if security extn implemented */
583         uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
584         uint32_t csselr[M_REG_NUM_BANKS];
585         uint32_t scr[M_REG_NUM_BANKS];
586         uint32_t msplim[M_REG_NUM_BANKS];
587         uint32_t psplim[M_REG_NUM_BANKS];
588         uint32_t fpcar[M_REG_NUM_BANKS];
589         uint32_t fpccr[M_REG_NUM_BANKS];
590         uint32_t fpdscr[M_REG_NUM_BANKS];
591         uint32_t cpacr[M_REG_NUM_BANKS];
592         uint32_t nsacr;
593         uint32_t ltpsize;
594         uint32_t vpr;
595     } v7m;
596 
597     /* Information associated with an exception about to be taken:
598      * code which raises an exception must set cs->exception_index and
599      * the relevant parts of this structure; the cpu_do_interrupt function
600      * will then set the guest-visible registers as part of the exception
601      * entry process.
602      */
603     struct {
604         uint32_t syndrome; /* AArch64 format syndrome register */
605         uint32_t fsr; /* AArch32 format fault status register info */
606         uint64_t vaddress; /* virtual addr associated with exception, if any */
607         uint32_t target_el; /* EL the exception should be targeted for */
608         /* If we implement EL2 we will also need to store information
609          * about the intermediate physical address for stage 2 faults.
610          */
611     } exception;
612 
613     /* Information associated with an SError */
614     struct {
615         uint8_t pending;
616         uint8_t has_esr;
617         uint64_t esr;
618     } serror;
619 
620     uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
621 
622     /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
623     uint32_t irq_line_state;
624 
625     /* Thumb-2 EE state.  */
626     uint32_t teecr;
627     uint32_t teehbr;
628 
629     /* VFP coprocessor state.  */
630     struct {
631         ARMVectorReg zregs[32];
632 
633 #ifdef TARGET_AARCH64
634         /* Store FFR as pregs[16] to make it easier to treat as any other.  */
635 #define FFR_PRED_NUM 16
636         ARMPredicateReg pregs[17];
637         /* Scratch space for aa64 sve predicate temporary.  */
638         ARMPredicateReg preg_tmp;
639 #endif
640 
641         /* We store these fpcsr fields separately for convenience.  */
642         uint32_t qc[4] QEMU_ALIGNED(16);
643         int vec_len;
644         int vec_stride;
645 
646         uint32_t xregs[16];
647 
648         /* Scratch space for aa32 neon expansion.  */
649         uint32_t scratch[8];
650 
651         /* There are a number of distinct float control structures:
652          *
653          *  fp_status: is the "normal" fp status.
654          *  fp_status_fp16: used for half-precision calculations
655          *  standard_fp_status : the ARM "Standard FPSCR Value"
656          *  standard_fp_status_fp16 : used for half-precision
657          *       calculations with the ARM "Standard FPSCR Value"
658          *
659          * Half-precision operations are governed by a separate
660          * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
661          * status structure to control this.
662          *
663          * The "Standard FPSCR", ie default-NaN, flush-to-zero,
664          * round-to-nearest and is used by any operations (generally
665          * Neon) which the architecture defines as controlled by the
666          * standard FPSCR value rather than the FPSCR.
667          *
668          * The "standard FPSCR but for fp16 ops" is needed because
669          * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than
670          * using a fixed value for it.
671          *
672          * To avoid having to transfer exception bits around, we simply
673          * say that the FPSCR cumulative exception flags are the logical
674          * OR of the flags in the four fp statuses. This relies on the
675          * only thing which needs to read the exception flags being
676          * an explicit FPSCR read.
677          */
678         float_status fp_status;
679         float_status fp_status_f16;
680         float_status standard_fp_status;
681         float_status standard_fp_status_f16;
682 
683         uint64_t zcr_el[4];   /* ZCR_EL[1-3] */
684         uint64_t smcr_el[4];  /* SMCR_EL[1-3] */
685     } vfp;
686 
687     uint64_t exclusive_addr;
688     uint64_t exclusive_val;
689     /*
690      * Contains the 'val' for the second 64-bit register of LDXP, which comes
691      * from the higher address, not the high part of a complete 128-bit value.
692      * In some ways it might be more convenient to record the exclusive value
693      * as the low and high halves of a 128 bit data value, but the current
694      * semantics of these fields are baked into the migration format.
695      */
696     uint64_t exclusive_high;
697 
698     /* iwMMXt coprocessor state.  */
699     struct {
700         uint64_t regs[16];
701         uint64_t val;
702 
703         uint32_t cregs[16];
704     } iwmmxt;
705 
706 #ifdef TARGET_AARCH64
707     struct {
708         ARMPACKey apia;
709         ARMPACKey apib;
710         ARMPACKey apda;
711         ARMPACKey apdb;
712         ARMPACKey apga;
713     } keys;
714 
715     uint64_t scxtnum_el[4];
716 
717     /*
718      * SME ZA storage -- 256 x 256 byte array, with bytes in host word order,
719      * as we do with vfp.zregs[].  This corresponds to the architectural ZA
720      * array, where ZA[N] is in the least-significant bytes of env->zarray[N].
721      * When SVL is less than the architectural maximum, the accessible
722      * storage is restricted, such that if the SVL is X bytes the guest can
723      * see only the bottom X elements of zarray[], and only the least
724      * significant X bytes of each element of the array. (In other words,
725      * the observable part is always square.)
726      *
727      * The ZA storage can also be considered as a set of square tiles of
728      * elements of different sizes. The mapping from tiles to the ZA array
729      * is architecturally defined, such that for tiles of elements of esz
730      * bytes, the Nth row (or "horizontal slice") of tile T is in
731      * ZA[T + N * esz]. Note that this means that each tile is not contiguous
732      * in the ZA storage, because its rows are striped through the ZA array.
733      *
734      * Because this is so large, keep this toward the end of the reset area,
735      * to keep the offsets into the rest of the structure smaller.
736      */
737     ARMVectorReg zarray[ARM_MAX_VQ * 16];
738 #endif
739 
740     struct CPUBreakpoint *cpu_breakpoint[16];
741     struct CPUWatchpoint *cpu_watchpoint[16];
742 
743     /* Optional fault info across tlb lookup. */
744     ARMMMUFaultInfo *tlb_fi;
745 
746     /* Fields up to this point are cleared by a CPU reset */
747     struct {} end_reset_fields;
748 
749     /* Fields after this point are preserved across CPU reset. */
750 
751     /* Internal CPU feature flags.  */
752     uint64_t features;
753 
754     /* PMSAv7 MPU */
755     struct {
756         uint32_t *drbar;
757         uint32_t *drsr;
758         uint32_t *dracr;
759         uint32_t rnr[M_REG_NUM_BANKS];
760     } pmsav7;
761 
762     /* PMSAv8 MPU */
763     struct {
764         /* The PMSAv8 implementation also shares some PMSAv7 config
765          * and state:
766          *  pmsav7.rnr (region number register)
767          *  pmsav7_dregion (number of configured regions)
768          */
769         uint32_t *rbar[M_REG_NUM_BANKS];
770         uint32_t *rlar[M_REG_NUM_BANKS];
771         uint32_t *hprbar;
772         uint32_t *hprlar;
773         uint32_t mair0[M_REG_NUM_BANKS];
774         uint32_t mair1[M_REG_NUM_BANKS];
775         uint32_t hprselr;
776     } pmsav8;
777 
778     /* v8M SAU */
779     struct {
780         uint32_t *rbar;
781         uint32_t *rlar;
782         uint32_t rnr;
783         uint32_t ctrl;
784     } sau;
785 
786 #if !defined(CONFIG_USER_ONLY)
787     NVICState *nvic;
788     const struct arm_boot_info *boot_info;
789     /* Store GICv3CPUState to access from this struct */
790     void *gicv3state;
791 #else /* CONFIG_USER_ONLY */
792     /* For usermode syscall translation.  */
793     bool eabi;
794 #endif /* CONFIG_USER_ONLY */
795 
796 #ifdef TARGET_TAGGED_ADDRESSES
797     /* Linux syscall tagged address support */
798     bool tagged_addr_enable;
799 #endif
800 } CPUARMState;
801 
802 static inline void set_feature(CPUARMState *env, int feature)
803 {
804     env->features |= 1ULL << feature;
805 }
806 
807 static inline void unset_feature(CPUARMState *env, int feature)
808 {
809     env->features &= ~(1ULL << feature);
810 }
811 
812 /**
813  * ARMELChangeHookFn:
814  * type of a function which can be registered via arm_register_el_change_hook()
815  * to get callbacks when the CPU changes its exception level or mode.
816  */
817 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
818 typedef struct ARMELChangeHook ARMELChangeHook;
819 struct ARMELChangeHook {
820     ARMELChangeHookFn *hook;
821     void *opaque;
822     QLIST_ENTRY(ARMELChangeHook) node;
823 };
824 
825 /* These values map onto the return values for
826  * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
827 typedef enum ARMPSCIState {
828     PSCI_ON = 0,
829     PSCI_OFF = 1,
830     PSCI_ON_PENDING = 2
831 } ARMPSCIState;
832 
833 typedef struct ARMISARegisters ARMISARegisters;
834 
835 /*
836  * In map, each set bit is a supported vector length of (bit-number + 1) * 16
837  * bytes, i.e. each bit number + 1 is the vector length in quadwords.
838  *
839  * While processing properties during initialization, corresponding init bits
840  * are set for bits in sve_vq_map that have been set by properties.
841  *
842  * Bits set in supported represent valid vector lengths for the CPU type.
843  */
844 typedef struct {
845     uint32_t map, init, supported;
846 } ARMVQMap;
847 
848 /**
849  * ARMCPU:
850  * @env: #CPUARMState
851  *
852  * An ARM CPU core.
853  */
854 struct ArchCPU {
855     /*< private >*/
856     CPUState parent_obj;
857     /*< public >*/
858 
859     CPUNegativeOffsetState neg;
860     CPUARMState env;
861 
862     /* Coprocessor information */
863     GHashTable *cp_regs;
864     /* For marshalling (mostly coprocessor) register state between the
865      * kernel and QEMU (for KVM) and between two QEMUs (for migration),
866      * we use these arrays.
867      */
868     /* List of register indexes managed via these arrays; (full KVM style
869      * 64 bit indexes, not CPRegInfo 32 bit indexes)
870      */
871     uint64_t *cpreg_indexes;
872     /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
873     uint64_t *cpreg_values;
874     /* Length of the indexes, values, reset_values arrays */
875     int32_t cpreg_array_len;
876     /* These are used only for migration: incoming data arrives in
877      * these fields and is sanity checked in post_load before copying
878      * to the working data structures above.
879      */
880     uint64_t *cpreg_vmstate_indexes;
881     uint64_t *cpreg_vmstate_values;
882     int32_t cpreg_vmstate_array_len;
883 
884     DynamicGDBXMLInfo dyn_sysreg_xml;
885     DynamicGDBXMLInfo dyn_svereg_xml;
886     DynamicGDBXMLInfo dyn_m_systemreg_xml;
887     DynamicGDBXMLInfo dyn_m_secextreg_xml;
888 
889     /* Timers used by the generic (architected) timer */
890     QEMUTimer *gt_timer[NUM_GTIMERS];
891     /*
892      * Timer used by the PMU. Its state is restored after migration by
893      * pmu_op_finish() - it does not need other handling during migration
894      */
895     QEMUTimer *pmu_timer;
896     /* GPIO outputs for generic timer */
897     qemu_irq gt_timer_outputs[NUM_GTIMERS];
898     /* GPIO output for GICv3 maintenance interrupt signal */
899     qemu_irq gicv3_maintenance_interrupt;
900     /* GPIO output for the PMU interrupt */
901     qemu_irq pmu_interrupt;
902 
903     /* MemoryRegion to use for secure physical accesses */
904     MemoryRegion *secure_memory;
905 
906     /* MemoryRegion to use for allocation tag accesses */
907     MemoryRegion *tag_memory;
908     MemoryRegion *secure_tag_memory;
909 
910     /* For v8M, pointer to the IDAU interface provided by board/SoC */
911     Object *idau;
912 
913     /* 'compatible' string for this CPU for Linux device trees */
914     const char *dtb_compatible;
915 
916     /* PSCI version for this CPU
917      * Bits[31:16] = Major Version
918      * Bits[15:0] = Minor Version
919      */
920     uint32_t psci_version;
921 
922     /* Current power state, access guarded by BQL */
923     ARMPSCIState power_state;
924 
925     /* CPU has virtualization extension */
926     bool has_el2;
927     /* CPU has security extension */
928     bool has_el3;
929     /* CPU has PMU (Performance Monitor Unit) */
930     bool has_pmu;
931     /* CPU has VFP */
932     bool has_vfp;
933     /* CPU has 32 VFP registers */
934     bool has_vfp_d32;
935     /* CPU has Neon */
936     bool has_neon;
937     /* CPU has M-profile DSP extension */
938     bool has_dsp;
939 
940     /* CPU has memory protection unit */
941     bool has_mpu;
942     /* PMSAv7 MPU number of supported regions */
943     uint32_t pmsav7_dregion;
944     /* PMSAv8 MPU number of supported hyp regions */
945     uint32_t pmsav8r_hdregion;
946     /* v8M SAU number of supported regions */
947     uint32_t sau_sregion;
948 
949     /* PSCI conduit used to invoke PSCI methods
950      * 0 - disabled, 1 - smc, 2 - hvc
951      */
952     uint32_t psci_conduit;
953 
954     /* For v8M, initial value of the Secure VTOR */
955     uint32_t init_svtor;
956     /* For v8M, initial value of the Non-secure VTOR */
957     uint32_t init_nsvtor;
958 
959     /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
960      * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
961      */
962     uint32_t kvm_target;
963 
964 #ifdef CONFIG_KVM
965     /* KVM init features for this CPU */
966     uint32_t kvm_init_features[7];
967 
968     /* KVM CPU state */
969 
970     /* KVM virtual time adjustment */
971     bool kvm_adjvtime;
972     bool kvm_vtime_dirty;
973     uint64_t kvm_vtime;
974 
975     /* KVM steal time */
976     OnOffAuto kvm_steal_time;
977 #endif /* CONFIG_KVM */
978 
979     /* Uniprocessor system with MP extensions */
980     bool mp_is_up;
981 
982     /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init
983      * and the probe failed (so we need to report the error in realize)
984      */
985     bool host_cpu_probe_failed;
986 
987     /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
988      * register.
989      */
990     int32_t core_count;
991 
992     /* The instance init functions for implementation-specific subclasses
993      * set these fields to specify the implementation-dependent values of
994      * various constant registers and reset values of non-constant
995      * registers.
996      * Some of these might become QOM properties eventually.
997      * Field names match the official register names as defined in the
998      * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
999      * is used for reset values of non-constant registers; no reset_
1000      * prefix means a constant register.
1001      * Some of these registers are split out into a substructure that
1002      * is shared with the translators to control the ISA.
1003      *
1004      * Note that if you add an ID register to the ARMISARegisters struct
1005      * you need to also update the 32-bit and 64-bit versions of the
1006      * kvm_arm_get_host_cpu_features() function to correctly populate the
1007      * field by reading the value from the KVM vCPU.
1008      */
1009     struct ARMISARegisters {
1010         uint32_t id_isar0;
1011         uint32_t id_isar1;
1012         uint32_t id_isar2;
1013         uint32_t id_isar3;
1014         uint32_t id_isar4;
1015         uint32_t id_isar5;
1016         uint32_t id_isar6;
1017         uint32_t id_mmfr0;
1018         uint32_t id_mmfr1;
1019         uint32_t id_mmfr2;
1020         uint32_t id_mmfr3;
1021         uint32_t id_mmfr4;
1022         uint32_t id_mmfr5;
1023         uint32_t id_pfr0;
1024         uint32_t id_pfr1;
1025         uint32_t id_pfr2;
1026         uint32_t mvfr0;
1027         uint32_t mvfr1;
1028         uint32_t mvfr2;
1029         uint32_t id_dfr0;
1030         uint32_t id_dfr1;
1031         uint32_t dbgdidr;
1032         uint32_t dbgdevid;
1033         uint32_t dbgdevid1;
1034         uint64_t id_aa64isar0;
1035         uint64_t id_aa64isar1;
1036         uint64_t id_aa64pfr0;
1037         uint64_t id_aa64pfr1;
1038         uint64_t id_aa64mmfr0;
1039         uint64_t id_aa64mmfr1;
1040         uint64_t id_aa64mmfr2;
1041         uint64_t id_aa64dfr0;
1042         uint64_t id_aa64dfr1;
1043         uint64_t id_aa64zfr0;
1044         uint64_t id_aa64smfr0;
1045         uint64_t reset_pmcr_el0;
1046     } isar;
1047     uint64_t midr;
1048     uint32_t revidr;
1049     uint32_t reset_fpsid;
1050     uint64_t ctr;
1051     uint32_t reset_sctlr;
1052     uint64_t pmceid0;
1053     uint64_t pmceid1;
1054     uint32_t id_afr0;
1055     uint64_t id_aa64afr0;
1056     uint64_t id_aa64afr1;
1057     uint64_t clidr;
1058     uint64_t mp_affinity; /* MP ID without feature bits */
1059     /* The elements of this array are the CCSIDR values for each cache,
1060      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
1061      */
1062     uint64_t ccsidr[16];
1063     uint64_t reset_cbar;
1064     uint32_t reset_auxcr;
1065     bool reset_hivecs;
1066     uint8_t reset_l0gptsz;
1067 
1068     /*
1069      * Intermediate values used during property parsing.
1070      * Once finalized, the values should be read from ID_AA64*.
1071      */
1072     bool prop_pauth;
1073     bool prop_pauth_impdef;
1074     bool prop_lpa2;
1075 
1076     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
1077     uint32_t dcz_blocksize;
1078     uint64_t rvbar_prop; /* Property/input signals.  */
1079 
1080     /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
1081     int gic_num_lrs; /* number of list registers */
1082     int gic_vpribits; /* number of virtual priority bits */
1083     int gic_vprebits; /* number of virtual preemption bits */
1084     int gic_pribits; /* number of physical priority bits */
1085 
1086     /* Whether the cfgend input is high (i.e. this CPU should reset into
1087      * big-endian mode).  This setting isn't used directly: instead it modifies
1088      * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
1089      * architecture version.
1090      */
1091     bool cfgend;
1092 
1093     QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
1094     QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
1095 
1096     int32_t node_id; /* NUMA node this CPU belongs to */
1097 
1098     /* Used to synchronize KVM and QEMU in-kernel device levels */
1099     uint8_t device_irq_level;
1100 
1101     /* Used to set the maximum vector length the cpu will support.  */
1102     uint32_t sve_max_vq;
1103 
1104 #ifdef CONFIG_USER_ONLY
1105     /* Used to set the default vector length at process start. */
1106     uint32_t sve_default_vq;
1107     uint32_t sme_default_vq;
1108 #endif
1109 
1110     ARMVQMap sve_vq;
1111     ARMVQMap sme_vq;
1112 
1113     /* Generic timer counter frequency, in Hz */
1114     uint64_t gt_cntfrq_hz;
1115 };
1116 
1117 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
1118 
1119 void arm_cpu_post_init(Object *obj);
1120 
1121 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
1122 
1123 #ifndef CONFIG_USER_ONLY
1124 extern const VMStateDescription vmstate_arm_cpu;
1125 
1126 void arm_cpu_do_interrupt(CPUState *cpu);
1127 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1128 
1129 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1130                                          MemTxAttrs *attrs);
1131 #endif /* !CONFIG_USER_ONLY */
1132 
1133 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1134 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1135 
1136 /* Returns the dynamically generated XML for the gdb stub.
1137  * Returns a pointer to the XML contents for the specified XML file or NULL
1138  * if the XML name doesn't match the predefined one.
1139  */
1140 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1141 
1142 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1143                              int cpuid, DumpState *s);
1144 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1145                              int cpuid, DumpState *s);
1146 
1147 #ifdef TARGET_AARCH64
1148 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1149 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1150 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1151 void aarch64_sve_change_el(CPUARMState *env, int old_el,
1152                            int new_el, bool el0_a64);
1153 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask);
1154 
1155 /*
1156  * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1157  * The byte at offset i from the start of the in-memory representation contains
1158  * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
1159  * lowest offsets are stored in the lowest memory addresses, then that nearly
1160  * matches QEMU's representation, which is to use an array of host-endian
1161  * uint64_t's, where the lower offsets are at the lower indices. To complete
1162  * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1163  */
1164 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1165 {
1166 #if HOST_BIG_ENDIAN
1167     int i;
1168 
1169     for (i = 0; i < nr; ++i) {
1170         dst[i] = bswap64(src[i]);
1171     }
1172 
1173     return dst;
1174 #else
1175     return src;
1176 #endif
1177 }
1178 
1179 #else
1180 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1181 static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1182                                          int n, bool a)
1183 { }
1184 #endif
1185 
1186 void aarch64_sync_32_to_64(CPUARMState *env);
1187 void aarch64_sync_64_to_32(CPUARMState *env);
1188 
1189 int fp_exception_el(CPUARMState *env, int cur_el);
1190 int sve_exception_el(CPUARMState *env, int cur_el);
1191 int sme_exception_el(CPUARMState *env, int cur_el);
1192 
1193 /**
1194  * sve_vqm1_for_el_sm:
1195  * @env: CPUARMState
1196  * @el: exception level
1197  * @sm: streaming mode
1198  *
1199  * Compute the current vector length for @el & @sm, in units of
1200  * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
1201  * If @sm, compute for SVL, otherwise NVL.
1202  */
1203 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm);
1204 
1205 /* Likewise, but using @sm = PSTATE.SM. */
1206 uint32_t sve_vqm1_for_el(CPUARMState *env, int el);
1207 
1208 static inline bool is_a64(CPUARMState *env)
1209 {
1210     return env->aarch64;
1211 }
1212 
1213 /**
1214  * pmu_op_start/finish
1215  * @env: CPUARMState
1216  *
1217  * Convert all PMU counters between their delta form (the typical mode when
1218  * they are enabled) and the guest-visible values. These two calls must
1219  * surround any action which might affect the counters.
1220  */
1221 void pmu_op_start(CPUARMState *env);
1222 void pmu_op_finish(CPUARMState *env);
1223 
1224 /*
1225  * Called when a PMU counter is due to overflow
1226  */
1227 void arm_pmu_timer_cb(void *opaque);
1228 
1229 /**
1230  * Functions to register as EL change hooks for PMU mode filtering
1231  */
1232 void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1233 void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1234 
1235 /*
1236  * pmu_init
1237  * @cpu: ARMCPU
1238  *
1239  * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state
1240  * for the current configuration
1241  */
1242 void pmu_init(ARMCPU *cpu);
1243 
1244 /* SCTLR bit meanings. Several bits have been reused in newer
1245  * versions of the architecture; in that case we define constants
1246  * for both old and new bit meanings. Code which tests against those
1247  * bits should probably check or otherwise arrange that the CPU
1248  * is the architectural version it expects.
1249  */
1250 #define SCTLR_M       (1U << 0)
1251 #define SCTLR_A       (1U << 1)
1252 #define SCTLR_C       (1U << 2)
1253 #define SCTLR_W       (1U << 3) /* up to v6; RAO in v7 */
1254 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1255 #define SCTLR_SA      (1U << 3) /* AArch64 only */
1256 #define SCTLR_P       (1U << 4) /* up to v5; RAO in v6 and v7 */
1257 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1258 #define SCTLR_SA0     (1U << 4) /* v8 onward, AArch64 only */
1259 #define SCTLR_D       (1U << 5) /* up to v5; RAO in v6 */
1260 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1261 #define SCTLR_L       (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1262 #define SCTLR_nAA     (1U << 6) /* when FEAT_LSE2 is implemented */
1263 #define SCTLR_B       (1U << 7) /* up to v6; RAZ in v7 */
1264 #define SCTLR_ITD     (1U << 7) /* v8 onward */
1265 #define SCTLR_S       (1U << 8) /* up to v6; RAZ in v7 */
1266 #define SCTLR_SED     (1U << 8) /* v8 onward */
1267 #define SCTLR_R       (1U << 9) /* up to v6; RAZ in v7 */
1268 #define SCTLR_UMA     (1U << 9) /* v8 onward, AArch64 only */
1269 #define SCTLR_F       (1U << 10) /* up to v6 */
1270 #define SCTLR_SW      (1U << 10) /* v7 */
1271 #define SCTLR_EnRCTX  (1U << 10) /* in v8.0-PredInv */
1272 #define SCTLR_Z       (1U << 11) /* in v7, RES1 in v8 */
1273 #define SCTLR_EOS     (1U << 11) /* v8.5-ExS */
1274 #define SCTLR_I       (1U << 12)
1275 #define SCTLR_V       (1U << 13) /* AArch32 only */
1276 #define SCTLR_EnDB    (1U << 13) /* v8.3, AArch64 only */
1277 #define SCTLR_RR      (1U << 14) /* up to v7 */
1278 #define SCTLR_DZE     (1U << 14) /* v8 onward, AArch64 only */
1279 #define SCTLR_L4      (1U << 15) /* up to v6; RAZ in v7 */
1280 #define SCTLR_UCT     (1U << 15) /* v8 onward, AArch64 only */
1281 #define SCTLR_DT      (1U << 16) /* up to ??, RAO in v6 and v7 */
1282 #define SCTLR_nTWI    (1U << 16) /* v8 onward */
1283 #define SCTLR_HA      (1U << 17) /* up to v7, RES0 in v8 */
1284 #define SCTLR_BR      (1U << 17) /* PMSA only */
1285 #define SCTLR_IT      (1U << 18) /* up to ??, RAO in v6 and v7 */
1286 #define SCTLR_nTWE    (1U << 18) /* v8 onward */
1287 #define SCTLR_WXN     (1U << 19)
1288 #define SCTLR_ST      (1U << 20) /* up to ??, RAZ in v6 */
1289 #define SCTLR_UWXN    (1U << 20) /* v7 onward, AArch32 only */
1290 #define SCTLR_TSCXT   (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
1291 #define SCTLR_FI      (1U << 21) /* up to v7, v8 RES0 */
1292 #define SCTLR_IESB    (1U << 21) /* v8.2-IESB, AArch64 only */
1293 #define SCTLR_U       (1U << 22) /* up to v6, RAO in v7 */
1294 #define SCTLR_EIS     (1U << 22) /* v8.5-ExS */
1295 #define SCTLR_XP      (1U << 23) /* up to v6; v7 onward RAO */
1296 #define SCTLR_SPAN    (1U << 23) /* v8.1-PAN */
1297 #define SCTLR_VE      (1U << 24) /* up to v7 */
1298 #define SCTLR_E0E     (1U << 24) /* v8 onward, AArch64 only */
1299 #define SCTLR_EE      (1U << 25)
1300 #define SCTLR_L2      (1U << 26) /* up to v6, RAZ in v7 */
1301 #define SCTLR_UCI     (1U << 26) /* v8 onward, AArch64 only */
1302 #define SCTLR_NMFI    (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1303 #define SCTLR_EnDA    (1U << 27) /* v8.3, AArch64 only */
1304 #define SCTLR_TRE     (1U << 28) /* AArch32 only */
1305 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1306 #define SCTLR_AFE     (1U << 29) /* AArch32 only */
1307 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1308 #define SCTLR_TE      (1U << 30) /* AArch32 only */
1309 #define SCTLR_EnIB    (1U << 30) /* v8.3, AArch64 only */
1310 #define SCTLR_EnIA    (1U << 31) /* v8.3, AArch64 only */
1311 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
1312 #define SCTLR_BT0     (1ULL << 35) /* v8.5-BTI */
1313 #define SCTLR_BT1     (1ULL << 36) /* v8.5-BTI */
1314 #define SCTLR_ITFSB   (1ULL << 37) /* v8.5-MemTag */
1315 #define SCTLR_TCF0    (3ULL << 38) /* v8.5-MemTag */
1316 #define SCTLR_TCF     (3ULL << 40) /* v8.5-MemTag */
1317 #define SCTLR_ATA0    (1ULL << 42) /* v8.5-MemTag */
1318 #define SCTLR_ATA     (1ULL << 43) /* v8.5-MemTag */
1319 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
1320 #define SCTLR_TWEDEn  (1ULL << 45)  /* FEAT_TWED */
1321 #define SCTLR_TWEDEL  MAKE_64_MASK(46, 4)  /* FEAT_TWED */
1322 #define SCTLR_TMT0    (1ULL << 50) /* FEAT_TME */
1323 #define SCTLR_TMT     (1ULL << 51) /* FEAT_TME */
1324 #define SCTLR_TME0    (1ULL << 52) /* FEAT_TME */
1325 #define SCTLR_TME     (1ULL << 53) /* FEAT_TME */
1326 #define SCTLR_EnASR   (1ULL << 54) /* FEAT_LS64_V */
1327 #define SCTLR_EnAS0   (1ULL << 55) /* FEAT_LS64_ACCDATA */
1328 #define SCTLR_EnALS   (1ULL << 56) /* FEAT_LS64 */
1329 #define SCTLR_EPAN    (1ULL << 57) /* FEAT_PAN3 */
1330 #define SCTLR_EnTP2   (1ULL << 60) /* FEAT_SME */
1331 #define SCTLR_NMI     (1ULL << 61) /* FEAT_NMI */
1332 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
1333 #define SCTLR_TIDCP   (1ULL << 63) /* FEAT_TIDCP1 */
1334 
1335 /* Bit definitions for CPACR (AArch32 only) */
1336 FIELD(CPACR, CP10, 20, 2)
1337 FIELD(CPACR, CP11, 22, 2)
1338 FIELD(CPACR, TRCDIS, 28, 1)    /* matches CPACR_EL1.TTA */
1339 FIELD(CPACR, D32DIS, 30, 1)    /* up to v7; RAZ in v8 */
1340 FIELD(CPACR, ASEDIS, 31, 1)
1341 
1342 /* Bit definitions for CPACR_EL1 (AArch64 only) */
1343 FIELD(CPACR_EL1, ZEN, 16, 2)
1344 FIELD(CPACR_EL1, FPEN, 20, 2)
1345 FIELD(CPACR_EL1, SMEN, 24, 2)
1346 FIELD(CPACR_EL1, TTA, 28, 1)   /* matches CPACR.TRCDIS */
1347 
1348 /* Bit definitions for HCPTR (AArch32 only) */
1349 FIELD(HCPTR, TCP10, 10, 1)
1350 FIELD(HCPTR, TCP11, 11, 1)
1351 FIELD(HCPTR, TASE, 15, 1)
1352 FIELD(HCPTR, TTA, 20, 1)
1353 FIELD(HCPTR, TAM, 30, 1)       /* matches CPTR_EL2.TAM */
1354 FIELD(HCPTR, TCPAC, 31, 1)     /* matches CPTR_EL2.TCPAC */
1355 
1356 /* Bit definitions for CPTR_EL2 (AArch64 only) */
1357 FIELD(CPTR_EL2, TZ, 8, 1)      /* !E2H */
1358 FIELD(CPTR_EL2, TFP, 10, 1)    /* !E2H, matches HCPTR.TCP10 */
1359 FIELD(CPTR_EL2, TSM, 12, 1)    /* !E2H */
1360 FIELD(CPTR_EL2, ZEN, 16, 2)    /* E2H */
1361 FIELD(CPTR_EL2, FPEN, 20, 2)   /* E2H */
1362 FIELD(CPTR_EL2, SMEN, 24, 2)   /* E2H */
1363 FIELD(CPTR_EL2, TTA, 28, 1)
1364 FIELD(CPTR_EL2, TAM, 30, 1)    /* matches HCPTR.TAM */
1365 FIELD(CPTR_EL2, TCPAC, 31, 1)  /* matches HCPTR.TCPAC */
1366 
1367 /* Bit definitions for CPTR_EL3 (AArch64 only) */
1368 FIELD(CPTR_EL3, EZ, 8, 1)
1369 FIELD(CPTR_EL3, TFP, 10, 1)
1370 FIELD(CPTR_EL3, ESM, 12, 1)
1371 FIELD(CPTR_EL3, TTA, 20, 1)
1372 FIELD(CPTR_EL3, TAM, 30, 1)
1373 FIELD(CPTR_EL3, TCPAC, 31, 1)
1374 
1375 #define MDCR_MTPME    (1U << 28)
1376 #define MDCR_TDCC     (1U << 27)
1377 #define MDCR_HLP      (1U << 26)  /* MDCR_EL2 */
1378 #define MDCR_SCCD     (1U << 23)  /* MDCR_EL3 */
1379 #define MDCR_HCCD     (1U << 23)  /* MDCR_EL2 */
1380 #define MDCR_EPMAD    (1U << 21)
1381 #define MDCR_EDAD     (1U << 20)
1382 #define MDCR_TTRF     (1U << 19)
1383 #define MDCR_STE      (1U << 18)  /* MDCR_EL3 */
1384 #define MDCR_SPME     (1U << 17)  /* MDCR_EL3 */
1385 #define MDCR_HPMD     (1U << 17)  /* MDCR_EL2 */
1386 #define MDCR_SDD      (1U << 16)
1387 #define MDCR_SPD      (3U << 14)
1388 #define MDCR_TDRA     (1U << 11)
1389 #define MDCR_TDOSA    (1U << 10)
1390 #define MDCR_TDA      (1U << 9)
1391 #define MDCR_TDE      (1U << 8)
1392 #define MDCR_HPME     (1U << 7)
1393 #define MDCR_TPM      (1U << 6)
1394 #define MDCR_TPMCR    (1U << 5)
1395 #define MDCR_HPMN     (0x1fU)
1396 
1397 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
1398 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
1399                          MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
1400                          MDCR_STE | MDCR_SPME | MDCR_SPD)
1401 
1402 #define CPSR_M (0x1fU)
1403 #define CPSR_T (1U << 5)
1404 #define CPSR_F (1U << 6)
1405 #define CPSR_I (1U << 7)
1406 #define CPSR_A (1U << 8)
1407 #define CPSR_E (1U << 9)
1408 #define CPSR_IT_2_7 (0xfc00U)
1409 #define CPSR_GE (0xfU << 16)
1410 #define CPSR_IL (1U << 20)
1411 #define CPSR_DIT (1U << 21)
1412 #define CPSR_PAN (1U << 22)
1413 #define CPSR_SSBS (1U << 23)
1414 #define CPSR_J (1U << 24)
1415 #define CPSR_IT_0_1 (3U << 25)
1416 #define CPSR_Q (1U << 27)
1417 #define CPSR_V (1U << 28)
1418 #define CPSR_C (1U << 29)
1419 #define CPSR_Z (1U << 30)
1420 #define CPSR_N (1U << 31)
1421 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1422 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1423 
1424 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1425 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1426     | CPSR_NZCV)
1427 /* Bits writable in user mode.  */
1428 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1429 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
1430 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1431 
1432 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1433 #define XPSR_EXCP 0x1ffU
1434 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1435 #define XPSR_IT_2_7 CPSR_IT_2_7
1436 #define XPSR_GE CPSR_GE
1437 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1438 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1439 #define XPSR_IT_0_1 CPSR_IT_0_1
1440 #define XPSR_Q CPSR_Q
1441 #define XPSR_V CPSR_V
1442 #define XPSR_C CPSR_C
1443 #define XPSR_Z CPSR_Z
1444 #define XPSR_N CPSR_N
1445 #define XPSR_NZCV CPSR_NZCV
1446 #define XPSR_IT CPSR_IT
1447 
1448 #define TTBCR_N      (7U << 0) /* TTBCR.EAE==0 */
1449 #define TTBCR_T0SZ   (7U << 0) /* TTBCR.EAE==1 */
1450 #define TTBCR_PD0    (1U << 4)
1451 #define TTBCR_PD1    (1U << 5)
1452 #define TTBCR_EPD0   (1U << 7)
1453 #define TTBCR_IRGN0  (3U << 8)
1454 #define TTBCR_ORGN0  (3U << 10)
1455 #define TTBCR_SH0    (3U << 12)
1456 #define TTBCR_T1SZ   (3U << 16)
1457 #define TTBCR_A1     (1U << 22)
1458 #define TTBCR_EPD1   (1U << 23)
1459 #define TTBCR_IRGN1  (3U << 24)
1460 #define TTBCR_ORGN1  (3U << 26)
1461 #define TTBCR_SH1    (1U << 28)
1462 #define TTBCR_EAE    (1U << 31)
1463 
1464 FIELD(VTCR, T0SZ, 0, 6)
1465 FIELD(VTCR, SL0, 6, 2)
1466 FIELD(VTCR, IRGN0, 8, 2)
1467 FIELD(VTCR, ORGN0, 10, 2)
1468 FIELD(VTCR, SH0, 12, 2)
1469 FIELD(VTCR, TG0, 14, 2)
1470 FIELD(VTCR, PS, 16, 3)
1471 FIELD(VTCR, VS, 19, 1)
1472 FIELD(VTCR, HA, 21, 1)
1473 FIELD(VTCR, HD, 22, 1)
1474 FIELD(VTCR, HWU59, 25, 1)
1475 FIELD(VTCR, HWU60, 26, 1)
1476 FIELD(VTCR, HWU61, 27, 1)
1477 FIELD(VTCR, HWU62, 28, 1)
1478 FIELD(VTCR, NSW, 29, 1)
1479 FIELD(VTCR, NSA, 30, 1)
1480 FIELD(VTCR, DS, 32, 1)
1481 FIELD(VTCR, SL2, 33, 1)
1482 
1483 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1484  * Only these are valid when in AArch64 mode; in
1485  * AArch32 mode SPSRs are basically CPSR-format.
1486  */
1487 #define PSTATE_SP (1U)
1488 #define PSTATE_M (0xFU)
1489 #define PSTATE_nRW (1U << 4)
1490 #define PSTATE_F (1U << 6)
1491 #define PSTATE_I (1U << 7)
1492 #define PSTATE_A (1U << 8)
1493 #define PSTATE_D (1U << 9)
1494 #define PSTATE_BTYPE (3U << 10)
1495 #define PSTATE_SSBS (1U << 12)
1496 #define PSTATE_IL (1U << 20)
1497 #define PSTATE_SS (1U << 21)
1498 #define PSTATE_PAN (1U << 22)
1499 #define PSTATE_UAO (1U << 23)
1500 #define PSTATE_DIT (1U << 24)
1501 #define PSTATE_TCO (1U << 25)
1502 #define PSTATE_V (1U << 28)
1503 #define PSTATE_C (1U << 29)
1504 #define PSTATE_Z (1U << 30)
1505 #define PSTATE_N (1U << 31)
1506 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1507 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1508 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1509 /* Mode values for AArch64 */
1510 #define PSTATE_MODE_EL3h 13
1511 #define PSTATE_MODE_EL3t 12
1512 #define PSTATE_MODE_EL2h 9
1513 #define PSTATE_MODE_EL2t 8
1514 #define PSTATE_MODE_EL1h 5
1515 #define PSTATE_MODE_EL1t 4
1516 #define PSTATE_MODE_EL0t 0
1517 
1518 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */
1519 FIELD(SVCR, SM, 0, 1)
1520 FIELD(SVCR, ZA, 1, 1)
1521 
1522 /* Fields for SMCR_ELx. */
1523 FIELD(SMCR, LEN, 0, 4)
1524 FIELD(SMCR, FA64, 31, 1)
1525 
1526 /* Write a new value to v7m.exception, thus transitioning into or out
1527  * of Handler mode; this may result in a change of active stack pointer.
1528  */
1529 void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1530 
1531 /* Map EL and handler into a PSTATE_MODE.  */
1532 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1533 {
1534     return (el << 2) | handler;
1535 }
1536 
1537 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1538  * interprocessing, so we don't attempt to sync with the cpsr state used by
1539  * the 32 bit decoder.
1540  */
1541 static inline uint32_t pstate_read(CPUARMState *env)
1542 {
1543     int ZF;
1544 
1545     ZF = (env->ZF == 0);
1546     return (env->NF & 0x80000000) | (ZF << 30)
1547         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1548         | env->pstate | env->daif | (env->btype << 10);
1549 }
1550 
1551 static inline void pstate_write(CPUARMState *env, uint32_t val)
1552 {
1553     env->ZF = (~val) & PSTATE_Z;
1554     env->NF = val;
1555     env->CF = (val >> 29) & 1;
1556     env->VF = (val << 3) & 0x80000000;
1557     env->daif = val & PSTATE_DAIF;
1558     env->btype = (val >> 10) & 3;
1559     env->pstate = val & ~CACHED_PSTATE_BITS;
1560 }
1561 
1562 /* Return the current CPSR value.  */
1563 uint32_t cpsr_read(CPUARMState *env);
1564 
1565 typedef enum CPSRWriteType {
1566     CPSRWriteByInstr = 0,         /* from guest MSR or CPS */
1567     CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1568     CPSRWriteRaw = 2,
1569         /* trust values, no reg bank switch, no hflags rebuild */
1570     CPSRWriteByGDBStub = 3,       /* from the GDB stub */
1571 } CPSRWriteType;
1572 
1573 /*
1574  * Set the CPSR.  Note that some bits of mask must be all-set or all-clear.
1575  * This will do an arm_rebuild_hflags() if any of the bits in @mask
1576  * correspond to TB flags bits cached in the hflags, unless @write_type
1577  * is CPSRWriteRaw.
1578  */
1579 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1580                 CPSRWriteType write_type);
1581 
1582 /* Return the current xPSR value.  */
1583 static inline uint32_t xpsr_read(CPUARMState *env)
1584 {
1585     int ZF;
1586     ZF = (env->ZF == 0);
1587     return (env->NF & 0x80000000) | (ZF << 30)
1588         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1589         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1590         | ((env->condexec_bits & 0xfc) << 8)
1591         | (env->GE << 16)
1592         | env->v7m.exception;
1593 }
1594 
1595 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
1596 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1597 {
1598     if (mask & XPSR_NZCV) {
1599         env->ZF = (~val) & XPSR_Z;
1600         env->NF = val;
1601         env->CF = (val >> 29) & 1;
1602         env->VF = (val << 3) & 0x80000000;
1603     }
1604     if (mask & XPSR_Q) {
1605         env->QF = ((val & XPSR_Q) != 0);
1606     }
1607     if (mask & XPSR_GE) {
1608         env->GE = (val & XPSR_GE) >> 16;
1609     }
1610 #ifndef CONFIG_USER_ONLY
1611     if (mask & XPSR_T) {
1612         env->thumb = ((val & XPSR_T) != 0);
1613     }
1614     if (mask & XPSR_IT_0_1) {
1615         env->condexec_bits &= ~3;
1616         env->condexec_bits |= (val >> 25) & 3;
1617     }
1618     if (mask & XPSR_IT_2_7) {
1619         env->condexec_bits &= 3;
1620         env->condexec_bits |= (val >> 8) & 0xfc;
1621     }
1622     if (mask & XPSR_EXCP) {
1623         /* Note that this only happens on exception exit */
1624         write_v7m_exception(env, val & XPSR_EXCP);
1625     }
1626 #endif
1627 }
1628 
1629 #define HCR_VM        (1ULL << 0)
1630 #define HCR_SWIO      (1ULL << 1)
1631 #define HCR_PTW       (1ULL << 2)
1632 #define HCR_FMO       (1ULL << 3)
1633 #define HCR_IMO       (1ULL << 4)
1634 #define HCR_AMO       (1ULL << 5)
1635 #define HCR_VF        (1ULL << 6)
1636 #define HCR_VI        (1ULL << 7)
1637 #define HCR_VSE       (1ULL << 8)
1638 #define HCR_FB        (1ULL << 9)
1639 #define HCR_BSU_MASK  (3ULL << 10)
1640 #define HCR_DC        (1ULL << 12)
1641 #define HCR_TWI       (1ULL << 13)
1642 #define HCR_TWE       (1ULL << 14)
1643 #define HCR_TID0      (1ULL << 15)
1644 #define HCR_TID1      (1ULL << 16)
1645 #define HCR_TID2      (1ULL << 17)
1646 #define HCR_TID3      (1ULL << 18)
1647 #define HCR_TSC       (1ULL << 19)
1648 #define HCR_TIDCP     (1ULL << 20)
1649 #define HCR_TACR      (1ULL << 21)
1650 #define HCR_TSW       (1ULL << 22)
1651 #define HCR_TPCP      (1ULL << 23)
1652 #define HCR_TPU       (1ULL << 24)
1653 #define HCR_TTLB      (1ULL << 25)
1654 #define HCR_TVM       (1ULL << 26)
1655 #define HCR_TGE       (1ULL << 27)
1656 #define HCR_TDZ       (1ULL << 28)
1657 #define HCR_HCD       (1ULL << 29)
1658 #define HCR_TRVM      (1ULL << 30)
1659 #define HCR_RW        (1ULL << 31)
1660 #define HCR_CD        (1ULL << 32)
1661 #define HCR_ID        (1ULL << 33)
1662 #define HCR_E2H       (1ULL << 34)
1663 #define HCR_TLOR      (1ULL << 35)
1664 #define HCR_TERR      (1ULL << 36)
1665 #define HCR_TEA       (1ULL << 37)
1666 #define HCR_MIOCNCE   (1ULL << 38)
1667 #define HCR_TME       (1ULL << 39)
1668 #define HCR_APK       (1ULL << 40)
1669 #define HCR_API       (1ULL << 41)
1670 #define HCR_NV        (1ULL << 42)
1671 #define HCR_NV1       (1ULL << 43)
1672 #define HCR_AT        (1ULL << 44)
1673 #define HCR_NV2       (1ULL << 45)
1674 #define HCR_FWB       (1ULL << 46)
1675 #define HCR_FIEN      (1ULL << 47)
1676 #define HCR_GPF       (1ULL << 48)
1677 #define HCR_TID4      (1ULL << 49)
1678 #define HCR_TICAB     (1ULL << 50)
1679 #define HCR_AMVOFFEN  (1ULL << 51)
1680 #define HCR_TOCU      (1ULL << 52)
1681 #define HCR_ENSCXT    (1ULL << 53)
1682 #define HCR_TTLBIS    (1ULL << 54)
1683 #define HCR_TTLBOS    (1ULL << 55)
1684 #define HCR_ATA       (1ULL << 56)
1685 #define HCR_DCT       (1ULL << 57)
1686 #define HCR_TID5      (1ULL << 58)
1687 #define HCR_TWEDEN    (1ULL << 59)
1688 #define HCR_TWEDEL    MAKE_64BIT_MASK(60, 4)
1689 
1690 #define HCRX_ENAS0    (1ULL << 0)
1691 #define HCRX_ENALS    (1ULL << 1)
1692 #define HCRX_ENASR    (1ULL << 2)
1693 #define HCRX_FNXS     (1ULL << 3)
1694 #define HCRX_FGTNXS   (1ULL << 4)
1695 #define HCRX_SMPME    (1ULL << 5)
1696 #define HCRX_TALLINT  (1ULL << 6)
1697 #define HCRX_VINMI    (1ULL << 7)
1698 #define HCRX_VFNMI    (1ULL << 8)
1699 #define HCRX_CMOW     (1ULL << 9)
1700 #define HCRX_MCE2     (1ULL << 10)
1701 #define HCRX_MSCEN    (1ULL << 11)
1702 
1703 #define HPFAR_NS      (1ULL << 63)
1704 
1705 #define SCR_NS                (1ULL << 0)
1706 #define SCR_IRQ               (1ULL << 1)
1707 #define SCR_FIQ               (1ULL << 2)
1708 #define SCR_EA                (1ULL << 3)
1709 #define SCR_FW                (1ULL << 4)
1710 #define SCR_AW                (1ULL << 5)
1711 #define SCR_NET               (1ULL << 6)
1712 #define SCR_SMD               (1ULL << 7)
1713 #define SCR_HCE               (1ULL << 8)
1714 #define SCR_SIF               (1ULL << 9)
1715 #define SCR_RW                (1ULL << 10)
1716 #define SCR_ST                (1ULL << 11)
1717 #define SCR_TWI               (1ULL << 12)
1718 #define SCR_TWE               (1ULL << 13)
1719 #define SCR_TLOR              (1ULL << 14)
1720 #define SCR_TERR              (1ULL << 15)
1721 #define SCR_APK               (1ULL << 16)
1722 #define SCR_API               (1ULL << 17)
1723 #define SCR_EEL2              (1ULL << 18)
1724 #define SCR_EASE              (1ULL << 19)
1725 #define SCR_NMEA              (1ULL << 20)
1726 #define SCR_FIEN              (1ULL << 21)
1727 #define SCR_ENSCXT            (1ULL << 25)
1728 #define SCR_ATA               (1ULL << 26)
1729 #define SCR_FGTEN             (1ULL << 27)
1730 #define SCR_ECVEN             (1ULL << 28)
1731 #define SCR_TWEDEN            (1ULL << 29)
1732 #define SCR_TWEDEL            MAKE_64BIT_MASK(30, 4)
1733 #define SCR_TME               (1ULL << 34)
1734 #define SCR_AMVOFFEN          (1ULL << 35)
1735 #define SCR_ENAS0             (1ULL << 36)
1736 #define SCR_ADEN              (1ULL << 37)
1737 #define SCR_HXEN              (1ULL << 38)
1738 #define SCR_TRNDR             (1ULL << 40)
1739 #define SCR_ENTP2             (1ULL << 41)
1740 #define SCR_GPF               (1ULL << 48)
1741 #define SCR_NSE               (1ULL << 62)
1742 
1743 #define HSTR_TTEE (1 << 16)
1744 #define HSTR_TJDBX (1 << 17)
1745 
1746 /* Return the current FPSCR value.  */
1747 uint32_t vfp_get_fpscr(CPUARMState *env);
1748 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1749 
1750 /* FPCR, Floating Point Control Register
1751  * FPSR, Floating Poiht Status Register
1752  *
1753  * For A64 the FPSCR is split into two logically distinct registers,
1754  * FPCR and FPSR. However since they still use non-overlapping bits
1755  * we store the underlying state in fpscr and just mask on read/write.
1756  */
1757 #define FPSR_MASK 0xf800009f
1758 #define FPCR_MASK 0x07ff9f00
1759 
1760 #define FPCR_IOE    (1 << 8)    /* Invalid Operation exception trap enable */
1761 #define FPCR_DZE    (1 << 9)    /* Divide by Zero exception trap enable */
1762 #define FPCR_OFE    (1 << 10)   /* Overflow exception trap enable */
1763 #define FPCR_UFE    (1 << 11)   /* Underflow exception trap enable */
1764 #define FPCR_IXE    (1 << 12)   /* Inexact exception trap enable */
1765 #define FPCR_IDE    (1 << 15)   /* Input Denormal exception trap enable */
1766 #define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
1767 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
1768 #define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
1769 #define FPCR_DN     (1 << 25)   /* Default NaN enable bit */
1770 #define FPCR_AHP    (1 << 26)   /* Alternative half-precision */
1771 #define FPCR_QC     (1 << 27)   /* Cumulative saturation bit */
1772 #define FPCR_V      (1 << 28)   /* FP overflow flag */
1773 #define FPCR_C      (1 << 29)   /* FP carry flag */
1774 #define FPCR_Z      (1 << 30)   /* FP zero flag */
1775 #define FPCR_N      (1 << 31)   /* FP negative flag */
1776 
1777 #define FPCR_LTPSIZE_SHIFT 16   /* LTPSIZE, M-profile only */
1778 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
1779 #define FPCR_LTPSIZE_LENGTH 3
1780 
1781 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
1782 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
1783 
1784 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1785 {
1786     return vfp_get_fpscr(env) & FPSR_MASK;
1787 }
1788 
1789 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1790 {
1791     uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1792     vfp_set_fpscr(env, new_fpscr);
1793 }
1794 
1795 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1796 {
1797     return vfp_get_fpscr(env) & FPCR_MASK;
1798 }
1799 
1800 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1801 {
1802     uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1803     vfp_set_fpscr(env, new_fpscr);
1804 }
1805 
1806 enum arm_cpu_mode {
1807   ARM_CPU_MODE_USR = 0x10,
1808   ARM_CPU_MODE_FIQ = 0x11,
1809   ARM_CPU_MODE_IRQ = 0x12,
1810   ARM_CPU_MODE_SVC = 0x13,
1811   ARM_CPU_MODE_MON = 0x16,
1812   ARM_CPU_MODE_ABT = 0x17,
1813   ARM_CPU_MODE_HYP = 0x1a,
1814   ARM_CPU_MODE_UND = 0x1b,
1815   ARM_CPU_MODE_SYS = 0x1f
1816 };
1817 
1818 /* VFP system registers.  */
1819 #define ARM_VFP_FPSID   0
1820 #define ARM_VFP_FPSCR   1
1821 #define ARM_VFP_MVFR2   5
1822 #define ARM_VFP_MVFR1   6
1823 #define ARM_VFP_MVFR0   7
1824 #define ARM_VFP_FPEXC   8
1825 #define ARM_VFP_FPINST  9
1826 #define ARM_VFP_FPINST2 10
1827 /* These ones are M-profile only */
1828 #define ARM_VFP_FPSCR_NZCVQC 2
1829 #define ARM_VFP_VPR 12
1830 #define ARM_VFP_P0 13
1831 #define ARM_VFP_FPCXT_NS 14
1832 #define ARM_VFP_FPCXT_S 15
1833 
1834 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
1835 #define QEMU_VFP_FPSCR_NZCV 0xffff
1836 
1837 /* iwMMXt coprocessor control registers.  */
1838 #define ARM_IWMMXT_wCID  0
1839 #define ARM_IWMMXT_wCon  1
1840 #define ARM_IWMMXT_wCSSF 2
1841 #define ARM_IWMMXT_wCASF 3
1842 #define ARM_IWMMXT_wCGR0 8
1843 #define ARM_IWMMXT_wCGR1 9
1844 #define ARM_IWMMXT_wCGR2 10
1845 #define ARM_IWMMXT_wCGR3 11
1846 
1847 /* V7M CCR bits */
1848 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1849 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1850 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1851 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1852 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1853 FIELD(V7M_CCR, STKALIGN, 9, 1)
1854 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1855 FIELD(V7M_CCR, DC, 16, 1)
1856 FIELD(V7M_CCR, IC, 17, 1)
1857 FIELD(V7M_CCR, BP, 18, 1)
1858 FIELD(V7M_CCR, LOB, 19, 1)
1859 FIELD(V7M_CCR, TRD, 20, 1)
1860 
1861 /* V7M SCR bits */
1862 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1863 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1864 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1865 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1866 
1867 /* V7M AIRCR bits */
1868 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1869 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1870 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1871 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1872 FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1873 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1874 FIELD(V7M_AIRCR, PRIS, 14, 1)
1875 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1876 FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1877 
1878 /* V7M CFSR bits for MMFSR */
1879 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1880 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1881 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1882 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1883 FIELD(V7M_CFSR, MLSPERR, 5, 1)
1884 FIELD(V7M_CFSR, MMARVALID, 7, 1)
1885 
1886 /* V7M CFSR bits for BFSR */
1887 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1888 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1889 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1890 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1891 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1892 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1893 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1894 
1895 /* V7M CFSR bits for UFSR */
1896 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1897 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1898 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1899 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1900 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1901 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1902 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1903 
1904 /* V7M CFSR bit masks covering all of the subregister bits */
1905 FIELD(V7M_CFSR, MMFSR, 0, 8)
1906 FIELD(V7M_CFSR, BFSR, 8, 8)
1907 FIELD(V7M_CFSR, UFSR, 16, 16)
1908 
1909 /* V7M HFSR bits */
1910 FIELD(V7M_HFSR, VECTTBL, 1, 1)
1911 FIELD(V7M_HFSR, FORCED, 30, 1)
1912 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1913 
1914 /* V7M DFSR bits */
1915 FIELD(V7M_DFSR, HALTED, 0, 1)
1916 FIELD(V7M_DFSR, BKPT, 1, 1)
1917 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1918 FIELD(V7M_DFSR, VCATCH, 3, 1)
1919 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1920 
1921 /* V7M SFSR bits */
1922 FIELD(V7M_SFSR, INVEP, 0, 1)
1923 FIELD(V7M_SFSR, INVIS, 1, 1)
1924 FIELD(V7M_SFSR, INVER, 2, 1)
1925 FIELD(V7M_SFSR, AUVIOL, 3, 1)
1926 FIELD(V7M_SFSR, INVTRAN, 4, 1)
1927 FIELD(V7M_SFSR, LSPERR, 5, 1)
1928 FIELD(V7M_SFSR, SFARVALID, 6, 1)
1929 FIELD(V7M_SFSR, LSERR, 7, 1)
1930 
1931 /* v7M MPU_CTRL bits */
1932 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1933 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1934 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1935 
1936 /* v7M CLIDR bits */
1937 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1938 FIELD(V7M_CLIDR, LOUIS, 21, 3)
1939 FIELD(V7M_CLIDR, LOC, 24, 3)
1940 FIELD(V7M_CLIDR, LOUU, 27, 3)
1941 FIELD(V7M_CLIDR, ICB, 30, 2)
1942 
1943 FIELD(V7M_CSSELR, IND, 0, 1)
1944 FIELD(V7M_CSSELR, LEVEL, 1, 3)
1945 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1946  * define a mask for this and check that it doesn't permit running off
1947  * the end of the array.
1948  */
1949 FIELD(V7M_CSSELR, INDEX, 0, 4)
1950 
1951 /* v7M FPCCR bits */
1952 FIELD(V7M_FPCCR, LSPACT, 0, 1)
1953 FIELD(V7M_FPCCR, USER, 1, 1)
1954 FIELD(V7M_FPCCR, S, 2, 1)
1955 FIELD(V7M_FPCCR, THREAD, 3, 1)
1956 FIELD(V7M_FPCCR, HFRDY, 4, 1)
1957 FIELD(V7M_FPCCR, MMRDY, 5, 1)
1958 FIELD(V7M_FPCCR, BFRDY, 6, 1)
1959 FIELD(V7M_FPCCR, SFRDY, 7, 1)
1960 FIELD(V7M_FPCCR, MONRDY, 8, 1)
1961 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1962 FIELD(V7M_FPCCR, UFRDY, 10, 1)
1963 FIELD(V7M_FPCCR, RES0, 11, 15)
1964 FIELD(V7M_FPCCR, TS, 26, 1)
1965 FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1966 FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1967 FIELD(V7M_FPCCR, LSPENS, 29, 1)
1968 FIELD(V7M_FPCCR, LSPEN, 30, 1)
1969 FIELD(V7M_FPCCR, ASPEN, 31, 1)
1970 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
1971 #define R_V7M_FPCCR_BANKED_MASK                 \
1972     (R_V7M_FPCCR_LSPACT_MASK |                  \
1973      R_V7M_FPCCR_USER_MASK |                    \
1974      R_V7M_FPCCR_THREAD_MASK |                  \
1975      R_V7M_FPCCR_MMRDY_MASK |                   \
1976      R_V7M_FPCCR_SPLIMVIOL_MASK |               \
1977      R_V7M_FPCCR_UFRDY_MASK |                   \
1978      R_V7M_FPCCR_ASPEN_MASK)
1979 
1980 /* v7M VPR bits */
1981 FIELD(V7M_VPR, P0, 0, 16)
1982 FIELD(V7M_VPR, MASK01, 16, 4)
1983 FIELD(V7M_VPR, MASK23, 20, 4)
1984 
1985 /*
1986  * System register ID fields.
1987  */
1988 FIELD(CLIDR_EL1, CTYPE1, 0, 3)
1989 FIELD(CLIDR_EL1, CTYPE2, 3, 3)
1990 FIELD(CLIDR_EL1, CTYPE3, 6, 3)
1991 FIELD(CLIDR_EL1, CTYPE4, 9, 3)
1992 FIELD(CLIDR_EL1, CTYPE5, 12, 3)
1993 FIELD(CLIDR_EL1, CTYPE6, 15, 3)
1994 FIELD(CLIDR_EL1, CTYPE7, 18, 3)
1995 FIELD(CLIDR_EL1, LOUIS, 21, 3)
1996 FIELD(CLIDR_EL1, LOC, 24, 3)
1997 FIELD(CLIDR_EL1, LOUU, 27, 3)
1998 FIELD(CLIDR_EL1, ICB, 30, 3)
1999 
2000 /* When FEAT_CCIDX is implemented */
2001 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
2002 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
2003 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
2004 
2005 /* When FEAT_CCIDX is not implemented */
2006 FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
2007 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
2008 FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
2009 
2010 FIELD(CTR_EL0,  IMINLINE, 0, 4)
2011 FIELD(CTR_EL0,  L1IP, 14, 2)
2012 FIELD(CTR_EL0,  DMINLINE, 16, 4)
2013 FIELD(CTR_EL0,  ERG, 20, 4)
2014 FIELD(CTR_EL0,  CWG, 24, 4)
2015 FIELD(CTR_EL0,  IDC, 28, 1)
2016 FIELD(CTR_EL0,  DIC, 29, 1)
2017 FIELD(CTR_EL0,  TMINLINE, 32, 6)
2018 
2019 FIELD(MIDR_EL1, REVISION, 0, 4)
2020 FIELD(MIDR_EL1, PARTNUM, 4, 12)
2021 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
2022 FIELD(MIDR_EL1, VARIANT, 20, 4)
2023 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
2024 
2025 FIELD(ID_ISAR0, SWAP, 0, 4)
2026 FIELD(ID_ISAR0, BITCOUNT, 4, 4)
2027 FIELD(ID_ISAR0, BITFIELD, 8, 4)
2028 FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
2029 FIELD(ID_ISAR0, COPROC, 16, 4)
2030 FIELD(ID_ISAR0, DEBUG, 20, 4)
2031 FIELD(ID_ISAR0, DIVIDE, 24, 4)
2032 
2033 FIELD(ID_ISAR1, ENDIAN, 0, 4)
2034 FIELD(ID_ISAR1, EXCEPT, 4, 4)
2035 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
2036 FIELD(ID_ISAR1, EXTEND, 12, 4)
2037 FIELD(ID_ISAR1, IFTHEN, 16, 4)
2038 FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
2039 FIELD(ID_ISAR1, INTERWORK, 24, 4)
2040 FIELD(ID_ISAR1, JAZELLE, 28, 4)
2041 
2042 FIELD(ID_ISAR2, LOADSTORE, 0, 4)
2043 FIELD(ID_ISAR2, MEMHINT, 4, 4)
2044 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
2045 FIELD(ID_ISAR2, MULT, 12, 4)
2046 FIELD(ID_ISAR2, MULTS, 16, 4)
2047 FIELD(ID_ISAR2, MULTU, 20, 4)
2048 FIELD(ID_ISAR2, PSR_AR, 24, 4)
2049 FIELD(ID_ISAR2, REVERSAL, 28, 4)
2050 
2051 FIELD(ID_ISAR3, SATURATE, 0, 4)
2052 FIELD(ID_ISAR3, SIMD, 4, 4)
2053 FIELD(ID_ISAR3, SVC, 8, 4)
2054 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
2055 FIELD(ID_ISAR3, TABBRANCH, 16, 4)
2056 FIELD(ID_ISAR3, T32COPY, 20, 4)
2057 FIELD(ID_ISAR3, TRUENOP, 24, 4)
2058 FIELD(ID_ISAR3, T32EE, 28, 4)
2059 
2060 FIELD(ID_ISAR4, UNPRIV, 0, 4)
2061 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
2062 FIELD(ID_ISAR4, WRITEBACK, 8, 4)
2063 FIELD(ID_ISAR4, SMC, 12, 4)
2064 FIELD(ID_ISAR4, BARRIER, 16, 4)
2065 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
2066 FIELD(ID_ISAR4, PSR_M, 24, 4)
2067 FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
2068 
2069 FIELD(ID_ISAR5, SEVL, 0, 4)
2070 FIELD(ID_ISAR5, AES, 4, 4)
2071 FIELD(ID_ISAR5, SHA1, 8, 4)
2072 FIELD(ID_ISAR5, SHA2, 12, 4)
2073 FIELD(ID_ISAR5, CRC32, 16, 4)
2074 FIELD(ID_ISAR5, RDM, 24, 4)
2075 FIELD(ID_ISAR5, VCMA, 28, 4)
2076 
2077 FIELD(ID_ISAR6, JSCVT, 0, 4)
2078 FIELD(ID_ISAR6, DP, 4, 4)
2079 FIELD(ID_ISAR6, FHM, 8, 4)
2080 FIELD(ID_ISAR6, SB, 12, 4)
2081 FIELD(ID_ISAR6, SPECRES, 16, 4)
2082 FIELD(ID_ISAR6, BF16, 20, 4)
2083 FIELD(ID_ISAR6, I8MM, 24, 4)
2084 
2085 FIELD(ID_MMFR0, VMSA, 0, 4)
2086 FIELD(ID_MMFR0, PMSA, 4, 4)
2087 FIELD(ID_MMFR0, OUTERSHR, 8, 4)
2088 FIELD(ID_MMFR0, SHARELVL, 12, 4)
2089 FIELD(ID_MMFR0, TCM, 16, 4)
2090 FIELD(ID_MMFR0, AUXREG, 20, 4)
2091 FIELD(ID_MMFR0, FCSE, 24, 4)
2092 FIELD(ID_MMFR0, INNERSHR, 28, 4)
2093 
2094 FIELD(ID_MMFR1, L1HVDVA, 0, 4)
2095 FIELD(ID_MMFR1, L1UNIVA, 4, 4)
2096 FIELD(ID_MMFR1, L1HVDSW, 8, 4)
2097 FIELD(ID_MMFR1, L1UNISW, 12, 4)
2098 FIELD(ID_MMFR1, L1HVD, 16, 4)
2099 FIELD(ID_MMFR1, L1UNI, 20, 4)
2100 FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
2101 FIELD(ID_MMFR1, BPRED, 28, 4)
2102 
2103 FIELD(ID_MMFR2, L1HVDFG, 0, 4)
2104 FIELD(ID_MMFR2, L1HVDBG, 4, 4)
2105 FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
2106 FIELD(ID_MMFR2, HVDTLB, 12, 4)
2107 FIELD(ID_MMFR2, UNITLB, 16, 4)
2108 FIELD(ID_MMFR2, MEMBARR, 20, 4)
2109 FIELD(ID_MMFR2, WFISTALL, 24, 4)
2110 FIELD(ID_MMFR2, HWACCFLG, 28, 4)
2111 
2112 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
2113 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
2114 FIELD(ID_MMFR3, BPMAINT, 8, 4)
2115 FIELD(ID_MMFR3, MAINTBCST, 12, 4)
2116 FIELD(ID_MMFR3, PAN, 16, 4)
2117 FIELD(ID_MMFR3, COHWALK, 20, 4)
2118 FIELD(ID_MMFR3, CMEMSZ, 24, 4)
2119 FIELD(ID_MMFR3, SUPERSEC, 28, 4)
2120 
2121 FIELD(ID_MMFR4, SPECSEI, 0, 4)
2122 FIELD(ID_MMFR4, AC2, 4, 4)
2123 FIELD(ID_MMFR4, XNX, 8, 4)
2124 FIELD(ID_MMFR4, CNP, 12, 4)
2125 FIELD(ID_MMFR4, HPDS, 16, 4)
2126 FIELD(ID_MMFR4, LSM, 20, 4)
2127 FIELD(ID_MMFR4, CCIDX, 24, 4)
2128 FIELD(ID_MMFR4, EVT, 28, 4)
2129 
2130 FIELD(ID_MMFR5, ETS, 0, 4)
2131 FIELD(ID_MMFR5, NTLBPA, 4, 4)
2132 
2133 FIELD(ID_PFR0, STATE0, 0, 4)
2134 FIELD(ID_PFR0, STATE1, 4, 4)
2135 FIELD(ID_PFR0, STATE2, 8, 4)
2136 FIELD(ID_PFR0, STATE3, 12, 4)
2137 FIELD(ID_PFR0, CSV2, 16, 4)
2138 FIELD(ID_PFR0, AMU, 20, 4)
2139 FIELD(ID_PFR0, DIT, 24, 4)
2140 FIELD(ID_PFR0, RAS, 28, 4)
2141 
2142 FIELD(ID_PFR1, PROGMOD, 0, 4)
2143 FIELD(ID_PFR1, SECURITY, 4, 4)
2144 FIELD(ID_PFR1, MPROGMOD, 8, 4)
2145 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
2146 FIELD(ID_PFR1, GENTIMER, 16, 4)
2147 FIELD(ID_PFR1, SEC_FRAC, 20, 4)
2148 FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
2149 FIELD(ID_PFR1, GIC, 28, 4)
2150 
2151 FIELD(ID_PFR2, CSV3, 0, 4)
2152 FIELD(ID_PFR2, SSBS, 4, 4)
2153 FIELD(ID_PFR2, RAS_FRAC, 8, 4)
2154 
2155 FIELD(ID_AA64ISAR0, AES, 4, 4)
2156 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
2157 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
2158 FIELD(ID_AA64ISAR0, CRC32, 16, 4)
2159 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
2160 FIELD(ID_AA64ISAR0, RDM, 28, 4)
2161 FIELD(ID_AA64ISAR0, SHA3, 32, 4)
2162 FIELD(ID_AA64ISAR0, SM3, 36, 4)
2163 FIELD(ID_AA64ISAR0, SM4, 40, 4)
2164 FIELD(ID_AA64ISAR0, DP, 44, 4)
2165 FIELD(ID_AA64ISAR0, FHM, 48, 4)
2166 FIELD(ID_AA64ISAR0, TS, 52, 4)
2167 FIELD(ID_AA64ISAR0, TLB, 56, 4)
2168 FIELD(ID_AA64ISAR0, RNDR, 60, 4)
2169 
2170 FIELD(ID_AA64ISAR1, DPB, 0, 4)
2171 FIELD(ID_AA64ISAR1, APA, 4, 4)
2172 FIELD(ID_AA64ISAR1, API, 8, 4)
2173 FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
2174 FIELD(ID_AA64ISAR1, FCMA, 16, 4)
2175 FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
2176 FIELD(ID_AA64ISAR1, GPA, 24, 4)
2177 FIELD(ID_AA64ISAR1, GPI, 28, 4)
2178 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
2179 FIELD(ID_AA64ISAR1, SB, 36, 4)
2180 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
2181 FIELD(ID_AA64ISAR1, BF16, 44, 4)
2182 FIELD(ID_AA64ISAR1, DGH, 48, 4)
2183 FIELD(ID_AA64ISAR1, I8MM, 52, 4)
2184 FIELD(ID_AA64ISAR1, XS, 56, 4)
2185 FIELD(ID_AA64ISAR1, LS64, 60, 4)
2186 
2187 FIELD(ID_AA64ISAR2, WFXT, 0, 4)
2188 FIELD(ID_AA64ISAR2, RPRES, 4, 4)
2189 FIELD(ID_AA64ISAR2, GPA3, 8, 4)
2190 FIELD(ID_AA64ISAR2, APA3, 12, 4)
2191 FIELD(ID_AA64ISAR2, MOPS, 16, 4)
2192 FIELD(ID_AA64ISAR2, BC, 20, 4)
2193 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4)
2194 
2195 FIELD(ID_AA64PFR0, EL0, 0, 4)
2196 FIELD(ID_AA64PFR0, EL1, 4, 4)
2197 FIELD(ID_AA64PFR0, EL2, 8, 4)
2198 FIELD(ID_AA64PFR0, EL3, 12, 4)
2199 FIELD(ID_AA64PFR0, FP, 16, 4)
2200 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
2201 FIELD(ID_AA64PFR0, GIC, 24, 4)
2202 FIELD(ID_AA64PFR0, RAS, 28, 4)
2203 FIELD(ID_AA64PFR0, SVE, 32, 4)
2204 FIELD(ID_AA64PFR0, SEL2, 36, 4)
2205 FIELD(ID_AA64PFR0, MPAM, 40, 4)
2206 FIELD(ID_AA64PFR0, AMU, 44, 4)
2207 FIELD(ID_AA64PFR0, DIT, 48, 4)
2208 FIELD(ID_AA64PFR0, RME, 52, 4)
2209 FIELD(ID_AA64PFR0, CSV2, 56, 4)
2210 FIELD(ID_AA64PFR0, CSV3, 60, 4)
2211 
2212 FIELD(ID_AA64PFR1, BT, 0, 4)
2213 FIELD(ID_AA64PFR1, SSBS, 4, 4)
2214 FIELD(ID_AA64PFR1, MTE, 8, 4)
2215 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
2216 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
2217 FIELD(ID_AA64PFR1, SME, 24, 4)
2218 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4)
2219 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4)
2220 FIELD(ID_AA64PFR1, NMI, 36, 4)
2221 
2222 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
2223 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
2224 FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
2225 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
2226 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
2227 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
2228 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
2229 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
2230 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
2231 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
2232 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
2233 FIELD(ID_AA64MMFR0, EXS, 44, 4)
2234 FIELD(ID_AA64MMFR0, FGT, 56, 4)
2235 FIELD(ID_AA64MMFR0, ECV, 60, 4)
2236 
2237 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
2238 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
2239 FIELD(ID_AA64MMFR1, VH, 8, 4)
2240 FIELD(ID_AA64MMFR1, HPDS, 12, 4)
2241 FIELD(ID_AA64MMFR1, LO, 16, 4)
2242 FIELD(ID_AA64MMFR1, PAN, 20, 4)
2243 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
2244 FIELD(ID_AA64MMFR1, XNX, 28, 4)
2245 FIELD(ID_AA64MMFR1, TWED, 32, 4)
2246 FIELD(ID_AA64MMFR1, ETS, 36, 4)
2247 FIELD(ID_AA64MMFR1, HCX, 40, 4)
2248 FIELD(ID_AA64MMFR1, AFP, 44, 4)
2249 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4)
2250 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4)
2251 FIELD(ID_AA64MMFR1, CMOW, 56, 4)
2252 
2253 FIELD(ID_AA64MMFR2, CNP, 0, 4)
2254 FIELD(ID_AA64MMFR2, UAO, 4, 4)
2255 FIELD(ID_AA64MMFR2, LSM, 8, 4)
2256 FIELD(ID_AA64MMFR2, IESB, 12, 4)
2257 FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
2258 FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
2259 FIELD(ID_AA64MMFR2, NV, 24, 4)
2260 FIELD(ID_AA64MMFR2, ST, 28, 4)
2261 FIELD(ID_AA64MMFR2, AT, 32, 4)
2262 FIELD(ID_AA64MMFR2, IDS, 36, 4)
2263 FIELD(ID_AA64MMFR2, FWB, 40, 4)
2264 FIELD(ID_AA64MMFR2, TTL, 48, 4)
2265 FIELD(ID_AA64MMFR2, BBM, 52, 4)
2266 FIELD(ID_AA64MMFR2, EVT, 56, 4)
2267 FIELD(ID_AA64MMFR2, E0PD, 60, 4)
2268 
2269 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
2270 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
2271 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
2272 FIELD(ID_AA64DFR0, BRPS, 12, 4)
2273 FIELD(ID_AA64DFR0, WRPS, 20, 4)
2274 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
2275 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
2276 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
2277 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
2278 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4)
2279 FIELD(ID_AA64DFR0, MTPMU, 48, 4)
2280 FIELD(ID_AA64DFR0, BRBE, 52, 4)
2281 FIELD(ID_AA64DFR0, HPMN0, 60, 4)
2282 
2283 FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
2284 FIELD(ID_AA64ZFR0, AES, 4, 4)
2285 FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
2286 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
2287 FIELD(ID_AA64ZFR0, SHA3, 32, 4)
2288 FIELD(ID_AA64ZFR0, SM4, 40, 4)
2289 FIELD(ID_AA64ZFR0, I8MM, 44, 4)
2290 FIELD(ID_AA64ZFR0, F32MM, 52, 4)
2291 FIELD(ID_AA64ZFR0, F64MM, 56, 4)
2292 
2293 FIELD(ID_AA64SMFR0, F32F32, 32, 1)
2294 FIELD(ID_AA64SMFR0, B16F32, 34, 1)
2295 FIELD(ID_AA64SMFR0, F16F32, 35, 1)
2296 FIELD(ID_AA64SMFR0, I8I32, 36, 4)
2297 FIELD(ID_AA64SMFR0, F64F64, 48, 1)
2298 FIELD(ID_AA64SMFR0, I16I64, 52, 4)
2299 FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
2300 FIELD(ID_AA64SMFR0, FA64, 63, 1)
2301 
2302 FIELD(ID_DFR0, COPDBG, 0, 4)
2303 FIELD(ID_DFR0, COPSDBG, 4, 4)
2304 FIELD(ID_DFR0, MMAPDBG, 8, 4)
2305 FIELD(ID_DFR0, COPTRC, 12, 4)
2306 FIELD(ID_DFR0, MMAPTRC, 16, 4)
2307 FIELD(ID_DFR0, MPROFDBG, 20, 4)
2308 FIELD(ID_DFR0, PERFMON, 24, 4)
2309 FIELD(ID_DFR0, TRACEFILT, 28, 4)
2310 
2311 FIELD(ID_DFR1, MTPMU, 0, 4)
2312 FIELD(ID_DFR1, HPMN0, 4, 4)
2313 
2314 FIELD(DBGDIDR, SE_IMP, 12, 1)
2315 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
2316 FIELD(DBGDIDR, VERSION, 16, 4)
2317 FIELD(DBGDIDR, CTX_CMPS, 20, 4)
2318 FIELD(DBGDIDR, BRPS, 24, 4)
2319 FIELD(DBGDIDR, WRPS, 28, 4)
2320 
2321 FIELD(DBGDEVID, PCSAMPLE, 0, 4)
2322 FIELD(DBGDEVID, WPADDRMASK, 4, 4)
2323 FIELD(DBGDEVID, BPADDRMASK, 8, 4)
2324 FIELD(DBGDEVID, VECTORCATCH, 12, 4)
2325 FIELD(DBGDEVID, VIRTEXTNS, 16, 4)
2326 FIELD(DBGDEVID, DOUBLELOCK, 20, 4)
2327 FIELD(DBGDEVID, AUXREGS, 24, 4)
2328 FIELD(DBGDEVID, CIDMASK, 28, 4)
2329 
2330 FIELD(MVFR0, SIMDREG, 0, 4)
2331 FIELD(MVFR0, FPSP, 4, 4)
2332 FIELD(MVFR0, FPDP, 8, 4)
2333 FIELD(MVFR0, FPTRAP, 12, 4)
2334 FIELD(MVFR0, FPDIVIDE, 16, 4)
2335 FIELD(MVFR0, FPSQRT, 20, 4)
2336 FIELD(MVFR0, FPSHVEC, 24, 4)
2337 FIELD(MVFR0, FPROUND, 28, 4)
2338 
2339 FIELD(MVFR1, FPFTZ, 0, 4)
2340 FIELD(MVFR1, FPDNAN, 4, 4)
2341 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
2342 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
2343 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
2344 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
2345 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
2346 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
2347 FIELD(MVFR1, FPHP, 24, 4)
2348 FIELD(MVFR1, SIMDFMAC, 28, 4)
2349 
2350 FIELD(MVFR2, SIMDMISC, 0, 4)
2351 FIELD(MVFR2, FPMISC, 4, 4)
2352 
2353 FIELD(GPCCR, PPS, 0, 3)
2354 FIELD(GPCCR, IRGN, 8, 2)
2355 FIELD(GPCCR, ORGN, 10, 2)
2356 FIELD(GPCCR, SH, 12, 2)
2357 FIELD(GPCCR, PGS, 14, 2)
2358 FIELD(GPCCR, GPC, 16, 1)
2359 FIELD(GPCCR, GPCP, 17, 1)
2360 FIELD(GPCCR, L0GPTSZ, 20, 4)
2361 
2362 FIELD(MFAR, FPA, 12, 40)
2363 FIELD(MFAR, NSE, 62, 1)
2364 FIELD(MFAR, NS, 63, 1)
2365 
2366 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2367 
2368 /* If adding a feature bit which corresponds to a Linux ELF
2369  * HWCAP bit, remember to update the feature-bit-to-hwcap
2370  * mapping in linux-user/elfload.c:get_elf_hwcap().
2371  */
2372 enum arm_features {
2373     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
2374     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
2375     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
2376     ARM_FEATURE_V6,
2377     ARM_FEATURE_V6K,
2378     ARM_FEATURE_V7,
2379     ARM_FEATURE_THUMB2,
2380     ARM_FEATURE_PMSA,   /* no MMU; may have Memory Protection Unit */
2381     ARM_FEATURE_NEON,
2382     ARM_FEATURE_M, /* Microcontroller profile.  */
2383     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
2384     ARM_FEATURE_THUMB2EE,
2385     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
2386     ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
2387     ARM_FEATURE_V4T,
2388     ARM_FEATURE_V5,
2389     ARM_FEATURE_STRONGARM,
2390     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
2391     ARM_FEATURE_GENERIC_TIMER,
2392     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
2393     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
2394     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
2395     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
2396     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
2397     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
2398     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
2399     ARM_FEATURE_V8,
2400     ARM_FEATURE_AARCH64, /* supports 64 bit mode */
2401     ARM_FEATURE_CBAR, /* has cp15 CBAR */
2402     ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
2403     ARM_FEATURE_EL2, /* has EL2 Virtualization support */
2404     ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
2405     ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
2406     ARM_FEATURE_PMU, /* has PMU support */
2407     ARM_FEATURE_VBAR, /* has cp15 VBAR */
2408     ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
2409     ARM_FEATURE_M_MAIN, /* M profile Main Extension */
2410     ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
2411 };
2412 
2413 static inline int arm_feature(CPUARMState *env, int feature)
2414 {
2415     return (env->features & (1ULL << feature)) != 0;
2416 }
2417 
2418 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
2419 
2420 /*
2421  * ARM v9 security states.
2422  * The ordering of the enumeration corresponds to the low 2 bits
2423  * of the GPI value, and (except for Root) the concat of NSE:NS.
2424  */
2425 
2426 typedef enum ARMSecuritySpace {
2427     ARMSS_Secure     = 0,
2428     ARMSS_NonSecure  = 1,
2429     ARMSS_Root       = 2,
2430     ARMSS_Realm      = 3,
2431 } ARMSecuritySpace;
2432 
2433 /* Return true if @space is secure, in the pre-v9 sense. */
2434 static inline bool arm_space_is_secure(ARMSecuritySpace space)
2435 {
2436     return space == ARMSS_Secure || space == ARMSS_Root;
2437 }
2438 
2439 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */
2440 static inline ARMSecuritySpace arm_secure_to_space(bool secure)
2441 {
2442     return secure ? ARMSS_Secure : ARMSS_NonSecure;
2443 }
2444 
2445 #if !defined(CONFIG_USER_ONLY)
2446 /**
2447  * arm_security_space_below_el3:
2448  * @env: cpu context
2449  *
2450  * Return the security space of exception levels below EL3, following
2451  * an exception return to those levels.  Unlike arm_security_space,
2452  * this doesn't care about the current EL.
2453  */
2454 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env);
2455 
2456 /**
2457  * arm_is_secure_below_el3:
2458  * @env: cpu context
2459  *
2460  * Return true if exception levels below EL3 are in secure state,
2461  * or would be following an exception return to those levels.
2462  */
2463 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2464 {
2465     ARMSecuritySpace ss = arm_security_space_below_el3(env);
2466     return ss == ARMSS_Secure;
2467 }
2468 
2469 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
2470 static inline bool arm_is_el3_or_mon(CPUARMState *env)
2471 {
2472     assert(!arm_feature(env, ARM_FEATURE_M));
2473     if (arm_feature(env, ARM_FEATURE_EL3)) {
2474         if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2475             /* CPU currently in AArch64 state and EL3 */
2476             return true;
2477         } else if (!is_a64(env) &&
2478                 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2479             /* CPU currently in AArch32 state and monitor mode */
2480             return true;
2481         }
2482     }
2483     return false;
2484 }
2485 
2486 /**
2487  * arm_security_space:
2488  * @env: cpu context
2489  *
2490  * Return the current security space of the cpu.
2491  */
2492 ARMSecuritySpace arm_security_space(CPUARMState *env);
2493 
2494 /**
2495  * arm_is_secure:
2496  * @env: cpu context
2497  *
2498  * Return true if the processor is in secure state.
2499  */
2500 static inline bool arm_is_secure(CPUARMState *env)
2501 {
2502     return arm_space_is_secure(arm_security_space(env));
2503 }
2504 
2505 /*
2506  * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
2507  * This corresponds to the pseudocode EL2Enabled()
2508  */
2509 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
2510 {
2511     return arm_feature(env, ARM_FEATURE_EL2)
2512            && (!secure || (env->cp15.scr_el3 & SCR_EEL2));
2513 }
2514 
2515 static inline bool arm_is_el2_enabled(CPUARMState *env)
2516 {
2517     return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env));
2518 }
2519 
2520 #else
2521 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env)
2522 {
2523     return ARMSS_NonSecure;
2524 }
2525 
2526 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2527 {
2528     return false;
2529 }
2530 
2531 static inline ARMSecuritySpace arm_security_space(CPUARMState *env)
2532 {
2533     return ARMSS_NonSecure;
2534 }
2535 
2536 static inline bool arm_is_secure(CPUARMState *env)
2537 {
2538     return false;
2539 }
2540 
2541 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
2542 {
2543     return false;
2544 }
2545 
2546 static inline bool arm_is_el2_enabled(CPUARMState *env)
2547 {
2548     return false;
2549 }
2550 #endif
2551 
2552 /**
2553  * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
2554  * E.g. when in secure state, fields in HCR_EL2 are suppressed,
2555  * "for all purposes other than a direct read or write access of HCR_EL2."
2556  * Not included here is HCR_RW.
2557  */
2558 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure);
2559 uint64_t arm_hcr_el2_eff(CPUARMState *env);
2560 uint64_t arm_hcrx_el2_eff(CPUARMState *env);
2561 
2562 /* Return true if the specified exception level is running in AArch64 state. */
2563 static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2564 {
2565     /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
2566      * and if we're not in EL0 then the state of EL0 isn't well defined.)
2567      */
2568     assert(el >= 1 && el <= 3);
2569     bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2570 
2571     /* The highest exception level is always at the maximum supported
2572      * register width, and then lower levels have a register width controlled
2573      * by bits in the SCR or HCR registers.
2574      */
2575     if (el == 3) {
2576         return aa64;
2577     }
2578 
2579     if (arm_feature(env, ARM_FEATURE_EL3) &&
2580         ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
2581         aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2582     }
2583 
2584     if (el == 2) {
2585         return aa64;
2586     }
2587 
2588     if (arm_is_el2_enabled(env)) {
2589         aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2590     }
2591 
2592     return aa64;
2593 }
2594 
2595 /* Function for determing whether guest cp register reads and writes should
2596  * access the secure or non-secure bank of a cp register.  When EL3 is
2597  * operating in AArch32 state, the NS-bit determines whether the secure
2598  * instance of a cp register should be used. When EL3 is AArch64 (or if
2599  * it doesn't exist at all) then there is no register banking, and all
2600  * accesses are to the non-secure version.
2601  */
2602 static inline bool access_secure_reg(CPUARMState *env)
2603 {
2604     bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2605                 !arm_el_is_aa64(env, 3) &&
2606                 !(env->cp15.scr_el3 & SCR_NS));
2607 
2608     return ret;
2609 }
2610 
2611 /* Macros for accessing a specified CP register bank */
2612 #define A32_BANKED_REG_GET(_env, _regname, _secure)    \
2613     ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2614 
2615 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val)   \
2616     do {                                                \
2617         if (_secure) {                                   \
2618             (_env)->cp15._regname##_s = (_val);            \
2619         } else {                                        \
2620             (_env)->cp15._regname##_ns = (_val);           \
2621         }                                               \
2622     } while (0)
2623 
2624 /* Macros for automatically accessing a specific CP register bank depending on
2625  * the current secure state of the system.  These macros are not intended for
2626  * supporting instruction translation reads/writes as these are dependent
2627  * solely on the SCR.NS bit and not the mode.
2628  */
2629 #define A32_BANKED_CURRENT_REG_GET(_env, _regname)        \
2630     A32_BANKED_REG_GET((_env), _regname,                \
2631                        (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2632 
2633 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val)                       \
2634     A32_BANKED_REG_SET((_env), _regname,                                    \
2635                        (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2636                        (_val))
2637 
2638 void arm_cpu_list(void);
2639 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2640                                  uint32_t cur_el, bool secure);
2641 
2642 /* Return the highest implemented Exception Level */
2643 static inline int arm_highest_el(CPUARMState *env)
2644 {
2645     if (arm_feature(env, ARM_FEATURE_EL3)) {
2646         return 3;
2647     }
2648     if (arm_feature(env, ARM_FEATURE_EL2)) {
2649         return 2;
2650     }
2651     return 1;
2652 }
2653 
2654 /* Return true if a v7M CPU is in Handler mode */
2655 static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2656 {
2657     return env->v7m.exception != 0;
2658 }
2659 
2660 /* Return the current Exception Level (as per ARMv8; note that this differs
2661  * from the ARMv7 Privilege Level).
2662  */
2663 static inline int arm_current_el(CPUARMState *env)
2664 {
2665     if (arm_feature(env, ARM_FEATURE_M)) {
2666         return arm_v7m_is_handler_mode(env) ||
2667             !(env->v7m.control[env->v7m.secure] & 1);
2668     }
2669 
2670     if (is_a64(env)) {
2671         return extract32(env->pstate, 2, 2);
2672     }
2673 
2674     switch (env->uncached_cpsr & 0x1f) {
2675     case ARM_CPU_MODE_USR:
2676         return 0;
2677     case ARM_CPU_MODE_HYP:
2678         return 2;
2679     case ARM_CPU_MODE_MON:
2680         return 3;
2681     default:
2682         if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2683             /* If EL3 is 32-bit then all secure privileged modes run in
2684              * EL3
2685              */
2686             return 3;
2687         }
2688 
2689         return 1;
2690     }
2691 }
2692 
2693 /**
2694  * write_list_to_cpustate
2695  * @cpu: ARMCPU
2696  *
2697  * For each register listed in the ARMCPU cpreg_indexes list, write
2698  * its value from the cpreg_values list into the ARMCPUState structure.
2699  * This updates TCG's working data structures from KVM data or
2700  * from incoming migration state.
2701  *
2702  * Returns: true if all register values were updated correctly,
2703  * false if some register was unknown or could not be written.
2704  * Note that we do not stop early on failure -- we will attempt
2705  * writing all registers in the list.
2706  */
2707 bool write_list_to_cpustate(ARMCPU *cpu);
2708 
2709 /**
2710  * write_cpustate_to_list:
2711  * @cpu: ARMCPU
2712  * @kvm_sync: true if this is for syncing back to KVM
2713  *
2714  * For each register listed in the ARMCPU cpreg_indexes list, write
2715  * its value from the ARMCPUState structure into the cpreg_values list.
2716  * This is used to copy info from TCG's working data structures into
2717  * KVM or for outbound migration.
2718  *
2719  * @kvm_sync is true if we are doing this in order to sync the
2720  * register state back to KVM. In this case we will only update
2721  * values in the list if the previous list->cpustate sync actually
2722  * successfully wrote the CPU state. Otherwise we will keep the value
2723  * that is in the list.
2724  *
2725  * Returns: true if all register values were read correctly,
2726  * false if some register was unknown or could not be read.
2727  * Note that we do not stop early on failure -- we will attempt
2728  * reading all registers in the list.
2729  */
2730 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2731 
2732 #define ARM_CPUID_TI915T      0x54029152
2733 #define ARM_CPUID_TI925T      0x54029252
2734 
2735 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2736 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2737 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2738 
2739 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
2740 
2741 #define cpu_list arm_cpu_list
2742 
2743 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
2744  *
2745  * If EL3 is 64-bit:
2746  *  + NonSecure EL1 & 0 stage 1
2747  *  + NonSecure EL1 & 0 stage 2
2748  *  + NonSecure EL2
2749  *  + NonSecure EL2 & 0   (ARMv8.1-VHE)
2750  *  + Secure EL1 & 0
2751  *  + Secure EL3
2752  * If EL3 is 32-bit:
2753  *  + NonSecure PL1 & 0 stage 1
2754  *  + NonSecure PL1 & 0 stage 2
2755  *  + NonSecure PL2
2756  *  + Secure PL0
2757  *  + Secure PL1
2758  * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2759  *
2760  * For QEMU, an mmu_idx is not quite the same as a translation regime because:
2761  *  1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
2762  *     because they may differ in access permissions even if the VA->PA map is
2763  *     the same
2764  *  2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2765  *     translation, which means that we have one mmu_idx that deals with two
2766  *     concatenated translation regimes [this sort of combined s1+2 TLB is
2767  *     architecturally permitted]
2768  *  3. we don't need to allocate an mmu_idx to translations that we won't be
2769  *     handling via the TLB. The only way to do a stage 1 translation without
2770  *     the immediate stage 2 translation is via the ATS or AT system insns,
2771  *     which can be slow-pathed and always do a page table walk.
2772  *     The only use of stage 2 translations is either as part of an s1+2
2773  *     lookup or when loading the descriptors during a stage 1 page table walk,
2774  *     and in both those cases we don't use the TLB.
2775  *  4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2776  *     translation regimes, because they map reasonably well to each other
2777  *     and they can't both be active at the same time.
2778  *  5. we want to be able to use the TLB for accesses done as part of a
2779  *     stage1 page table walk, rather than having to walk the stage2 page
2780  *     table over and over.
2781  *  6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
2782  *     Never (PAN) bit within PSTATE.
2783  *  7. we fold together the secure and non-secure regimes for A-profile,
2784  *     because there are no banked system registers for aarch64, so the
2785  *     process of switching between secure and non-secure is
2786  *     already heavyweight.
2787  *
2788  * This gives us the following list of cases:
2789  *
2790  * EL0 EL1&0 stage 1+2 (aka NS PL0)
2791  * EL1 EL1&0 stage 1+2 (aka NS PL1)
2792  * EL1 EL1&0 stage 1+2 +PAN
2793  * EL0 EL2&0
2794  * EL2 EL2&0
2795  * EL2 EL2&0 +PAN
2796  * EL2 (aka NS PL2)
2797  * EL3 (aka S PL1)
2798  * Physical (NS & S)
2799  * Stage2 (NS & S)
2800  *
2801  * for a total of 12 different mmu_idx.
2802  *
2803  * R profile CPUs have an MPU, but can use the same set of MMU indexes
2804  * as A profile. They only need to distinguish EL0 and EL1 (and
2805  * EL2 if we ever model a Cortex-R52).
2806  *
2807  * M profile CPUs are rather different as they do not have a true MMU.
2808  * They have the following different MMU indexes:
2809  *  User
2810  *  Privileged
2811  *  User, execution priority negative (ie the MPU HFNMIENA bit may apply)
2812  *  Privileged, execution priority negative (ditto)
2813  * If the CPU supports the v8M Security Extension then there are also:
2814  *  Secure User
2815  *  Secure Privileged
2816  *  Secure User, execution priority negative
2817  *  Secure Privileged, execution priority negative
2818  *
2819  * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
2820  * are not quite the same -- different CPU types (most notably M profile
2821  * vs A/R profile) would like to use MMU indexes with different semantics,
2822  * but since we don't ever need to use all of those in a single CPU we
2823  * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
2824  * modes + total number of M profile MMU modes". The lower bits of
2825  * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
2826  * the same for any particular CPU.
2827  * Variables of type ARMMUIdx are always full values, and the core
2828  * index values are in variables of type 'int'.
2829  *
2830  * Our enumeration includes at the end some entries which are not "true"
2831  * mmu_idx values in that they don't have corresponding TLBs and are only
2832  * valid for doing slow path page table walks.
2833  *
2834  * The constant names here are patterned after the general style of the names
2835  * of the AT/ATS operations.
2836  * The values used are carefully arranged to make mmu_idx => EL lookup easy.
2837  * For M profile we arrange them to have a bit for priv, a bit for negpri
2838  * and a bit for secure.
2839  */
2840 #define ARM_MMU_IDX_A     0x10  /* A profile */
2841 #define ARM_MMU_IDX_NOTLB 0x20  /* does not have a TLB */
2842 #define ARM_MMU_IDX_M     0x40  /* M profile */
2843 
2844 /* Meanings of the bits for M profile mmu idx values */
2845 #define ARM_MMU_IDX_M_PRIV   0x1
2846 #define ARM_MMU_IDX_M_NEGPRI 0x2
2847 #define ARM_MMU_IDX_M_S      0x4  /* Secure */
2848 
2849 #define ARM_MMU_IDX_TYPE_MASK \
2850     (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
2851 #define ARM_MMU_IDX_COREIDX_MASK 0xf
2852 
2853 typedef enum ARMMMUIdx {
2854     /*
2855      * A-profile.
2856      */
2857     ARMMMUIdx_E10_0     = 0 | ARM_MMU_IDX_A,
2858     ARMMMUIdx_E20_0     = 1 | ARM_MMU_IDX_A,
2859     ARMMMUIdx_E10_1     = 2 | ARM_MMU_IDX_A,
2860     ARMMMUIdx_E20_2     = 3 | ARM_MMU_IDX_A,
2861     ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A,
2862     ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A,
2863     ARMMMUIdx_E2        = 6 | ARM_MMU_IDX_A,
2864     ARMMMUIdx_E3        = 7 | ARM_MMU_IDX_A,
2865 
2866     /*
2867      * Used for second stage of an S12 page table walk, or for descriptor
2868      * loads during first stage of an S1 page table walk.  Note that both
2869      * are in use simultaneously for SecureEL2: the security state for
2870      * the S2 ptw is selected by the NS bit from the S1 ptw.
2871      */
2872     ARMMMUIdx_Stage2_S  = 8 | ARM_MMU_IDX_A,
2873     ARMMMUIdx_Stage2    = 9 | ARM_MMU_IDX_A,
2874 
2875     /* TLBs with 1-1 mapping to the physical address spaces. */
2876     ARMMMUIdx_Phys_S     = 10 | ARM_MMU_IDX_A,
2877     ARMMMUIdx_Phys_NS    = 11 | ARM_MMU_IDX_A,
2878     ARMMMUIdx_Phys_Root  = 12 | ARM_MMU_IDX_A,
2879     ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A,
2880 
2881     /*
2882      * These are not allocated TLBs and are used only for AT system
2883      * instructions or for the first stage of an S12 page table walk.
2884      */
2885     ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
2886     ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
2887     ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
2888 
2889     /*
2890      * M-profile.
2891      */
2892     ARMMMUIdx_MUser = ARM_MMU_IDX_M,
2893     ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
2894     ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
2895     ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
2896     ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
2897     ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
2898     ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
2899     ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
2900 } ARMMMUIdx;
2901 
2902 /*
2903  * Bit macros for the core-mmu-index values for each index,
2904  * for use when calling tlb_flush_by_mmuidx() and friends.
2905  */
2906 #define TO_CORE_BIT(NAME) \
2907     ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
2908 
2909 typedef enum ARMMMUIdxBit {
2910     TO_CORE_BIT(E10_0),
2911     TO_CORE_BIT(E20_0),
2912     TO_CORE_BIT(E10_1),
2913     TO_CORE_BIT(E10_1_PAN),
2914     TO_CORE_BIT(E2),
2915     TO_CORE_BIT(E20_2),
2916     TO_CORE_BIT(E20_2_PAN),
2917     TO_CORE_BIT(E3),
2918     TO_CORE_BIT(Stage2),
2919     TO_CORE_BIT(Stage2_S),
2920 
2921     TO_CORE_BIT(MUser),
2922     TO_CORE_BIT(MPriv),
2923     TO_CORE_BIT(MUserNegPri),
2924     TO_CORE_BIT(MPrivNegPri),
2925     TO_CORE_BIT(MSUser),
2926     TO_CORE_BIT(MSPriv),
2927     TO_CORE_BIT(MSUserNegPri),
2928     TO_CORE_BIT(MSPrivNegPri),
2929 } ARMMMUIdxBit;
2930 
2931 #undef TO_CORE_BIT
2932 
2933 #define MMU_USER_IDX 0
2934 
2935 /* Indexes used when registering address spaces with cpu_address_space_init */
2936 typedef enum ARMASIdx {
2937     ARMASIdx_NS = 0,
2938     ARMASIdx_S = 1,
2939     ARMASIdx_TagNS = 2,
2940     ARMASIdx_TagS = 3,
2941 } ARMASIdx;
2942 
2943 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space)
2944 {
2945     /* Assert the relative order of the physical mmu indexes. */
2946     QEMU_BUILD_BUG_ON(ARMSS_Secure != 0);
2947     QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure);
2948     QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root);
2949     QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm);
2950 
2951     return ARMMMUIdx_Phys_S + space;
2952 }
2953 
2954 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx)
2955 {
2956     assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm);
2957     return idx - ARMMMUIdx_Phys_S;
2958 }
2959 
2960 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
2961 {
2962     /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
2963      * CSSELR is RAZ/WI.
2964      */
2965     return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
2966 }
2967 
2968 static inline bool arm_sctlr_b(CPUARMState *env)
2969 {
2970     return
2971         /* We need not implement SCTLR.ITD in user-mode emulation, so
2972          * let linux-user ignore the fact that it conflicts with SCTLR_B.
2973          * This lets people run BE32 binaries with "-cpu any".
2974          */
2975 #ifndef CONFIG_USER_ONLY
2976         !arm_feature(env, ARM_FEATURE_V7) &&
2977 #endif
2978         (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
2979 }
2980 
2981 uint64_t arm_sctlr(CPUARMState *env, int el);
2982 
2983 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
2984                                                   bool sctlr_b)
2985 {
2986 #ifdef CONFIG_USER_ONLY
2987     /*
2988      * In system mode, BE32 is modelled in line with the
2989      * architecture (as word-invariant big-endianness), where loads
2990      * and stores are done little endian but from addresses which
2991      * are adjusted by XORing with the appropriate constant. So the
2992      * endianness to use for the raw data access is not affected by
2993      * SCTLR.B.
2994      * In user mode, however, we model BE32 as byte-invariant
2995      * big-endianness (because user-only code cannot tell the
2996      * difference), and so we need to use a data access endianness
2997      * that depends on SCTLR.B.
2998      */
2999     if (sctlr_b) {
3000         return true;
3001     }
3002 #endif
3003     /* In 32bit endianness is determined by looking at CPSR's E bit */
3004     return env->uncached_cpsr & CPSR_E;
3005 }
3006 
3007 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3008 {
3009     return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3010 }
3011 
3012 /* Return true if the processor is in big-endian mode. */
3013 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3014 {
3015     if (!is_a64(env)) {
3016         return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3017     } else {
3018         int cur_el = arm_current_el(env);
3019         uint64_t sctlr = arm_sctlr(env, cur_el);
3020         return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3021     }
3022 }
3023 
3024 #include "exec/cpu-all.h"
3025 
3026 /*
3027  * We have more than 32-bits worth of state per TB, so we split the data
3028  * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
3029  * We collect these two parts in CPUARMTBFlags where they are named
3030  * flags and flags2 respectively.
3031  *
3032  * The flags that are shared between all execution modes, TBFLAG_ANY,
3033  * are stored in flags.  The flags that are specific to a given mode
3034  * are stores in flags2.  Since cs_base is sized on the configured
3035  * address size, flags2 always has 64-bits for A64, and a minimum of
3036  * 32-bits for A32 and M32.
3037  *
3038  * The bits for 32-bit A-profile and M-profile partially overlap:
3039  *
3040  *  31         23         11 10             0
3041  * +-------------+----------+----------------+
3042  * |             |          |   TBFLAG_A32   |
3043  * | TBFLAG_AM32 |          +-----+----------+
3044  * |             |                |TBFLAG_M32|
3045  * +-------------+----------------+----------+
3046  *  31         23                6 5        0
3047  *
3048  * Unless otherwise noted, these bits are cached in env->hflags.
3049  */
3050 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
3051 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
3052 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1)      /* Not cached. */
3053 FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
3054 FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
3055 /* Target EL if we take a floating-point-disabled exception */
3056 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
3057 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
3058 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
3059 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
3060 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
3061 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
3062 
3063 /*
3064  * Bit usage when in AArch32 state, both A- and M-profile.
3065  */
3066 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8)      /* Not cached. */
3067 FIELD(TBFLAG_AM32, THUMB, 23, 1)         /* Not cached. */
3068 
3069 /*
3070  * Bit usage when in AArch32 state, for A-profile only.
3071  */
3072 FIELD(TBFLAG_A32, VECLEN, 0, 3)         /* Not cached. */
3073 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2)     /* Not cached. */
3074 /*
3075  * We store the bottom two bits of the CPAR as TB flags and handle
3076  * checks on the other bits at runtime. This shares the same bits as
3077  * VECSTRIDE, which is OK as no XScale CPU has VFP.
3078  * Not cached, because VECLEN+VECSTRIDE are not cached.
3079  */
3080 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2)
3081 FIELD(TBFLAG_A32, VFPEN, 7, 1)         /* Partially cached, minus FPEXC. */
3082 FIELD(TBFLAG_A32, SCTLR__B, 8, 1)      /* Cannot overlap with SCTLR_B */
3083 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
3084 /*
3085  * Indicates whether cp register reads and writes by guest code should access
3086  * the secure or nonsecure bank of banked registers; note that this is not
3087  * the same thing as the current security state of the processor!
3088  */
3089 FIELD(TBFLAG_A32, NS, 10, 1)
3090 /*
3091  * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not.
3092  * This requires an SME trap from AArch32 mode when using NEON.
3093  */
3094 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
3095 
3096 /*
3097  * Bit usage when in AArch32 state, for M-profile only.
3098  */
3099 /* Handler (ie not Thread) mode */
3100 FIELD(TBFLAG_M32, HANDLER, 0, 1)
3101 /* Whether we should generate stack-limit checks */
3102 FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
3103 /* Set if FPCCR.LSPACT is set */
3104 FIELD(TBFLAG_M32, LSPACT, 2, 1)                 /* Not cached. */
3105 /* Set if we must create a new FP context */
3106 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1)     /* Not cached. */
3107 /* Set if FPCCR.S does not match current security state */
3108 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1)          /* Not cached. */
3109 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */
3110 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1)            /* Not cached. */
3111 /* Set if in secure mode */
3112 FIELD(TBFLAG_M32, SECURE, 6, 1)
3113 
3114 /*
3115  * Bit usage when in AArch64 state
3116  */
3117 FIELD(TBFLAG_A64, TBII, 0, 2)
3118 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3119 /* The current vector length, either NVL or SVL. */
3120 FIELD(TBFLAG_A64, VL, 4, 4)
3121 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3122 FIELD(TBFLAG_A64, BT, 9, 1)
3123 FIELD(TBFLAG_A64, BTYPE, 10, 2)         /* Not cached. */
3124 FIELD(TBFLAG_A64, TBID, 12, 2)
3125 FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3126 FIELD(TBFLAG_A64, ATA, 15, 1)
3127 FIELD(TBFLAG_A64, TCMA, 16, 2)
3128 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3129 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3130 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
3131 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
3132 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
3133 FIELD(TBFLAG_A64, SVL, 24, 4)
3134 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
3135 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
3136 FIELD(TBFLAG_A64, FGT_ERET, 29, 1)
3137 FIELD(TBFLAG_A64, NAA, 30, 1)
3138 
3139 /*
3140  * Helpers for using the above.
3141  */
3142 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \
3143     (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
3144 #define DP_TBFLAG_A64(DST, WHICH, VAL) \
3145     (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL))
3146 #define DP_TBFLAG_A32(DST, WHICH, VAL) \
3147     (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
3148 #define DP_TBFLAG_M32(DST, WHICH, VAL) \
3149     (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
3150 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \
3151     (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
3152 
3153 #define EX_TBFLAG_ANY(IN, WHICH)   FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
3154 #define EX_TBFLAG_A64(IN, WHICH)   FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH)
3155 #define EX_TBFLAG_A32(IN, WHICH)   FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
3156 #define EX_TBFLAG_M32(IN, WHICH)   FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
3157 #define EX_TBFLAG_AM32(IN, WHICH)  FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
3158 
3159 /**
3160  * cpu_mmu_index:
3161  * @env: The cpu environment
3162  * @ifetch: True for code access, false for data access.
3163  *
3164  * Return the core mmu index for the current translation regime.
3165  * This function is used by generic TCG code paths.
3166  */
3167 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3168 {
3169     return EX_TBFLAG_ANY(env->hflags, MMUIDX);
3170 }
3171 
3172 /**
3173  * sve_vq
3174  * @env: the cpu context
3175  *
3176  * Return the VL cached within env->hflags, in units of quadwords.
3177  */
3178 static inline int sve_vq(CPUARMState *env)
3179 {
3180     return EX_TBFLAG_A64(env->hflags, VL) + 1;
3181 }
3182 
3183 /**
3184  * sme_vq
3185  * @env: the cpu context
3186  *
3187  * Return the SVL cached within env->hflags, in units of quadwords.
3188  */
3189 static inline int sme_vq(CPUARMState *env)
3190 {
3191     return EX_TBFLAG_A64(env->hflags, SVL) + 1;
3192 }
3193 
3194 static inline bool bswap_code(bool sctlr_b)
3195 {
3196 #ifdef CONFIG_USER_ONLY
3197     /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian.
3198      * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0
3199      * would also end up as a mixed-endian mode with BE code, LE data.
3200      */
3201     return
3202 #if TARGET_BIG_ENDIAN
3203         1 ^
3204 #endif
3205         sctlr_b;
3206 #else
3207     /* All code access in ARM is little endian, and there are no loaders
3208      * doing swaps that need to be reversed
3209      */
3210     return 0;
3211 #endif
3212 }
3213 
3214 #ifdef CONFIG_USER_ONLY
3215 static inline bool arm_cpu_bswap_data(CPUARMState *env)
3216 {
3217     return
3218 #if TARGET_BIG_ENDIAN
3219        1 ^
3220 #endif
3221        arm_cpu_data_is_big_endian(env);
3222 }
3223 #endif
3224 
3225 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
3226                           uint64_t *cs_base, uint32_t *flags);
3227 
3228 enum {
3229     QEMU_PSCI_CONDUIT_DISABLED = 0,
3230     QEMU_PSCI_CONDUIT_SMC = 1,
3231     QEMU_PSCI_CONDUIT_HVC = 2,
3232 };
3233 
3234 #ifndef CONFIG_USER_ONLY
3235 /* Return the address space index to use for a memory access */
3236 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3237 {
3238     return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3239 }
3240 
3241 /* Return the AddressSpace to use for a memory access
3242  * (which depends on whether the access is S or NS, and whether
3243  * the board gave us a separate AddressSpace for S accesses).
3244  */
3245 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3246 {
3247     return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3248 }
3249 #endif
3250 
3251 /**
3252  * arm_register_pre_el_change_hook:
3253  * Register a hook function which will be called immediately before this
3254  * CPU changes exception level or mode. The hook function will be
3255  * passed a pointer to the ARMCPU and the opaque data pointer passed
3256  * to this function when the hook was registered.
3257  *
3258  * Note that if a pre-change hook is called, any registered post-change hooks
3259  * are guaranteed to subsequently be called.
3260  */
3261 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3262                                  void *opaque);
3263 /**
3264  * arm_register_el_change_hook:
3265  * Register a hook function which will be called immediately after this
3266  * CPU changes exception level or mode. The hook function will be
3267  * passed a pointer to the ARMCPU and the opaque data pointer passed
3268  * to this function when the hook was registered.
3269  *
3270  * Note that any registered hooks registered here are guaranteed to be called
3271  * if pre-change hooks have been.
3272  */
3273 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3274         *opaque);
3275 
3276 /**
3277  * arm_rebuild_hflags:
3278  * Rebuild the cached TBFLAGS for arbitrary changed processor state.
3279  */
3280 void arm_rebuild_hflags(CPUARMState *env);
3281 
3282 /**
3283  * aa32_vfp_dreg:
3284  * Return a pointer to the Dn register within env in 32-bit mode.
3285  */
3286 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3287 {
3288     return &env->vfp.zregs[regno >> 1].d[regno & 1];
3289 }
3290 
3291 /**
3292  * aa32_vfp_qreg:
3293  * Return a pointer to the Qn register within env in 32-bit mode.
3294  */
3295 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3296 {
3297     return &env->vfp.zregs[regno].d[0];
3298 }
3299 
3300 /**
3301  * aa64_vfp_qreg:
3302  * Return a pointer to the Qn register within env in 64-bit mode.
3303  */
3304 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3305 {
3306     return &env->vfp.zregs[regno].d[0];
3307 }
3308 
3309 /* Shared between translate-sve.c and sve_helper.c.  */
3310 extern const uint64_t pred_esz_masks[5];
3311 
3312 /*
3313  * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
3314  * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect
3315  * mprotect but PROT_BTI may be cleared.  C.f. the kernel's VM_ARCH_CLEAR.
3316  */
3317 #define PAGE_BTI            PAGE_TARGET_1
3318 #define PAGE_MTE            PAGE_TARGET_2
3319 #define PAGE_TARGET_STICKY  PAGE_MTE
3320 
3321 /* We associate one allocation tag per 16 bytes, the minimum.  */
3322 #define LOG2_TAG_GRANULE 4
3323 #define TAG_GRANULE      (1 << LOG2_TAG_GRANULE)
3324 
3325 #ifdef CONFIG_USER_ONLY
3326 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1))
3327 #endif
3328 
3329 #ifdef TARGET_TAGGED_ADDRESSES
3330 /**
3331  * cpu_untagged_addr:
3332  * @cs: CPU context
3333  * @x: tagged address
3334  *
3335  * Remove any address tag from @x.  This is explicitly related to the
3336  * linux syscall TIF_TAGGED_ADDR setting, not TBI in general.
3337  *
3338  * There should be a better place to put this, but we need this in
3339  * include/exec/cpu_ldst.h, and not some place linux-user specific.
3340  */
3341 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x)
3342 {
3343     ARMCPU *cpu = ARM_CPU(cs);
3344     if (cpu->env.tagged_addr_enable) {
3345         /*
3346          * TBI is enabled for userspace but not kernelspace addresses.
3347          * Only clear the tag if bit 55 is clear.
3348          */
3349         x &= sextract64(x, 0, 56);
3350     }
3351     return x;
3352 }
3353 #endif
3354 
3355 /*
3356  * Naming convention for isar_feature functions:
3357  * Functions which test 32-bit ID registers should have _aa32_ in
3358  * their name. Functions which test 64-bit ID registers should have
3359  * _aa64_ in their name. These must only be used in code where we
3360  * know for certain that the CPU has AArch32 or AArch64 respectively
3361  * or where the correct answer for a CPU which doesn't implement that
3362  * CPU state is "false" (eg when generating A32 or A64 code, if adding
3363  * system registers that are specific to that CPU state, for "should
3364  * we let this system register bit be set" tests where the 32-bit
3365  * flavour of the register doesn't have the bit, and so on).
3366  * Functions which simply ask "does this feature exist at all" have
3367  * _any_ in their name, and always return the logical OR of the _aa64_
3368  * and the _aa32_ function.
3369  */
3370 
3371 /*
3372  * 32-bit feature tests via id registers.
3373  */
3374 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
3375 {
3376     return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3377 }
3378 
3379 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
3380 {
3381     return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3382 }
3383 
3384 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
3385 {
3386     /* (M-profile) low-overhead loops and branch future */
3387     return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
3388 }
3389 
3390 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
3391 {
3392     return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3393 }
3394 
3395 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3396 {
3397     return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3398 }
3399 
3400 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3401 {
3402     return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3403 }
3404 
3405 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3406 {
3407     return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3408 }
3409 
3410 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3411 {
3412     return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3413 }
3414 
3415 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3416 {
3417     return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3418 }
3419 
3420 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3421 {
3422     return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3423 }
3424 
3425 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3426 {
3427     return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3428 }
3429 
3430 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
3431 {
3432     return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
3433 }
3434 
3435 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3436 {
3437     return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3438 }
3439 
3440 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
3441 {
3442     return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
3443 }
3444 
3445 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
3446 {
3447     return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
3448 }
3449 
3450 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
3451 {
3452     return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
3453 }
3454 
3455 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id)
3456 {
3457     return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0;
3458 }
3459 
3460 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
3461 {
3462     return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
3463 }
3464 
3465 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
3466 {
3467     return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
3468 }
3469 
3470 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
3471 {
3472     return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
3473 }
3474 
3475 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
3476 {
3477     /*
3478      * Return true if M-profile state handling insns
3479      * (VSCCLRM, CLRM, FPCTX access insns) are implemented
3480      */
3481     return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
3482 }
3483 
3484 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
3485 {
3486     /* Sadly this is encoded differently for A-profile and M-profile */
3487     if (isar_feature_aa32_mprofile(id)) {
3488         return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
3489     } else {
3490         return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
3491     }
3492 }
3493 
3494 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id)
3495 {
3496     /*
3497      * Return true if MVE is supported (either integer or floating point).
3498      * We must check for M-profile as the MVFR1 field means something
3499      * else for A-profile.
3500      */
3501     return isar_feature_aa32_mprofile(id) &&
3502         FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0;
3503 }
3504 
3505 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id)
3506 {
3507     /*
3508      * Return true if MVE is supported (either integer or floating point).
3509      * We must check for M-profile as the MVFR1 field means something
3510      * else for A-profile.
3511      */
3512     return isar_feature_aa32_mprofile(id) &&
3513         FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2;
3514 }
3515 
3516 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
3517 {
3518     /*
3519      * Return true if either VFP or SIMD is implemented.
3520      * In this case, a minimum of VFP w/ D0-D15.
3521      */
3522     return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
3523 }
3524 
3525 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
3526 {
3527     /* Return true if D16-D31 are implemented */
3528     return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
3529 }
3530 
3531 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3532 {
3533     return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
3534 }
3535 
3536 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
3537 {
3538     /* Return true if CPU supports single precision floating point, VFPv2 */
3539     return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
3540 }
3541 
3542 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
3543 {
3544     /* Return true if CPU supports single precision floating point, VFPv3 */
3545     return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
3546 }
3547 
3548 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
3549 {
3550     /* Return true if CPU supports double precision floating point, VFPv2 */
3551     return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
3552 }
3553 
3554 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
3555 {
3556     /* Return true if CPU supports double precision floating point, VFPv3 */
3557     return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
3558 }
3559 
3560 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
3561 {
3562     return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
3563 }
3564 
3565 /*
3566  * We always set the FP and SIMD FP16 fields to indicate identical
3567  * levels of support (assuming SIMD is implemented at all), so
3568  * we only need one set of accessors.
3569  */
3570 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
3571 {
3572     return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
3573 }
3574 
3575 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
3576 {
3577     return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
3578 }
3579 
3580 /*
3581  * Note that this ID register field covers both VFP and Neon FMAC,
3582  * so should usually be tested in combination with some other
3583  * check that confirms the presence of whichever of VFP or Neon is
3584  * relevant, to avoid accidentally enabling a Neon feature on
3585  * a VFP-no-Neon core or vice-versa.
3586  */
3587 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
3588 {
3589     return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
3590 }
3591 
3592 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
3593 {
3594     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
3595 }
3596 
3597 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
3598 {
3599     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
3600 }
3601 
3602 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
3603 {
3604     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
3605 }
3606 
3607 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
3608 {
3609     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
3610 }
3611 
3612 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
3613 {
3614     return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
3615 }
3616 
3617 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
3618 {
3619     return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
3620 }
3621 
3622 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
3623 {
3624     return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
3625 }
3626 
3627 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id)
3628 {
3629     /* 0xf means "non-standard IMPDEF PMU" */
3630     return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
3631         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3632 }
3633 
3634 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id)
3635 {
3636     /* 0xf means "non-standard IMPDEF PMU" */
3637     return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
3638         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3639 }
3640 
3641 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id)
3642 {
3643     /* 0xf means "non-standard IMPDEF PMU" */
3644     return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 &&
3645         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3646 }
3647 
3648 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
3649 {
3650     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
3651 }
3652 
3653 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
3654 {
3655     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
3656 }
3657 
3658 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
3659 {
3660     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
3661 }
3662 
3663 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
3664 {
3665     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
3666 }
3667 
3668 static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id)
3669 {
3670     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1;
3671 }
3672 
3673 static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
3674 {
3675     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2;
3676 }
3677 
3678 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
3679 {
3680     return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
3681 }
3682 
3683 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
3684 {
3685     return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
3686 }
3687 
3688 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id)
3689 {
3690     return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5;
3691 }
3692 
3693 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
3694 {
3695     return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
3696 }
3697 
3698 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id)
3699 {
3700     return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0;
3701 }
3702 
3703 /*
3704  * 64-bit feature tests via id registers.
3705  */
3706 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
3707 {
3708     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
3709 }
3710 
3711 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
3712 {
3713     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
3714 }
3715 
3716 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
3717 {
3718     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
3719 }
3720 
3721 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
3722 {
3723     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
3724 }
3725 
3726 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
3727 {
3728     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
3729 }
3730 
3731 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
3732 {
3733     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
3734 }
3735 
3736 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
3737 {
3738     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
3739 }
3740 
3741 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
3742 {
3743     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
3744 }
3745 
3746 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
3747 {
3748     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
3749 }
3750 
3751 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
3752 {
3753     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
3754 }
3755 
3756 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
3757 {
3758     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
3759 }
3760 
3761 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
3762 {
3763     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
3764 }
3765 
3766 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
3767 {
3768     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
3769 }
3770 
3771 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
3772 {
3773     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
3774 }
3775 
3776 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
3777 {
3778     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
3779 }
3780 
3781 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
3782 {
3783     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
3784 }
3785 
3786 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
3787 {
3788     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
3789 }
3790 
3791 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
3792 {
3793     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
3794 }
3795 
3796 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
3797 {
3798     /*
3799      * Return true if any form of pauth is enabled, as this
3800      * predicate controls migration of the 128-bit keys.
3801      */
3802     return (id->id_aa64isar1 &
3803             (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
3804              FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
3805              FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
3806              FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
3807 }
3808 
3809 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
3810 {
3811     /*
3812      * Return true if pauth is enabled with the architected QARMA algorithm.
3813      * QEMU will always set APA+GPA to the same value.
3814      */
3815     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
3816 }
3817 
3818 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
3819 {
3820     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
3821 }
3822 
3823 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
3824 {
3825     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
3826 }
3827 
3828 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
3829 {
3830     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
3831 }
3832 
3833 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
3834 {
3835     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
3836 }
3837 
3838 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
3839 {
3840     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
3841 }
3842 
3843 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
3844 {
3845     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
3846 }
3847 
3848 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
3849 {
3850     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
3851 }
3852 
3853 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
3854 {
3855     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
3856 }
3857 
3858 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
3859 {
3860     /* We always set the AdvSIMD and FP fields identically.  */
3861     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
3862 }
3863 
3864 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
3865 {
3866     /* We always set the AdvSIMD and FP fields identically wrt FP16.  */
3867     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3868 }
3869 
3870 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
3871 {
3872     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
3873 }
3874 
3875 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
3876 {
3877     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
3878 }
3879 
3880 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
3881 {
3882     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
3883 }
3884 
3885 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
3886 {
3887     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
3888 }
3889 
3890 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id)
3891 {
3892     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2;
3893 }
3894 
3895 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
3896 {
3897     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
3898 }
3899 
3900 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
3901 {
3902     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
3903 }
3904 
3905 static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
3906 {
3907     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
3908 }
3909 
3910 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
3911 {
3912     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
3913 }
3914 
3915 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
3916 {
3917     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
3918 }
3919 
3920 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
3921 {
3922     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
3923 }
3924 
3925 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
3926 {
3927     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
3928 }
3929 
3930 static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id)
3931 {
3932     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3;
3933 }
3934 
3935 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
3936 {
3937     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
3938 }
3939 
3940 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
3941 {
3942     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
3943 }
3944 
3945 static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
3946 {
3947     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
3948 }
3949 
3950 static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id)
3951 {
3952     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) != 0;
3953 }
3954 
3955 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
3956 {
3957     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
3958 }
3959 
3960 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
3961 {
3962     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
3963 }
3964 
3965 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
3966 {
3967     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
3968 }
3969 
3970 static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
3971 {
3972     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
3973 }
3974 
3975 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
3976 {
3977     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
3978 }
3979 
3980 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
3981 {
3982     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
3983 }
3984 
3985 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
3986 {
3987     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
3988 }
3989 
3990 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
3991 {
3992     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
3993 }
3994 
3995 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
3996 {
3997     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
3998         FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
3999 }
4000 
4001 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id)
4002 {
4003     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
4004         FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4005 }
4006 
4007 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
4008 {
4009     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 &&
4010         FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4011 }
4012 
4013 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
4014 {
4015     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
4016 }
4017 
4018 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
4019 {
4020     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
4021 }
4022 
4023 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
4024 {
4025     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
4026 }
4027 
4028 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
4029 {
4030     return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
4031 }
4032 
4033 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
4034 {
4035     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
4036     return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
4037 }
4038 
4039 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
4040 {
4041     return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
4042 }
4043 
4044 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
4045 {
4046     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
4047     return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
4048 }
4049 
4050 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
4051 {
4052     return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
4053 }
4054 
4055 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
4056 {
4057     return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
4058 }
4059 
4060 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
4061 {
4062     return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
4063 }
4064 
4065 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
4066 {
4067     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
4068     return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
4069 }
4070 
4071 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
4072 {
4073     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
4074     return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
4075 }
4076 
4077 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
4078 {
4079     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
4080     return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
4081 }
4082 
4083 static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
4084 {
4085     return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
4086 }
4087 
4088 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
4089 {
4090     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
4091 }
4092 
4093 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
4094 {
4095     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
4096 }
4097 
4098 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
4099 {
4100     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
4101 }
4102 
4103 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
4104 {
4105     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
4106 }
4107 
4108 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
4109 {
4110     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
4111 }
4112 
4113 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
4114 {
4115     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
4116 }
4117 
4118 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
4119 {
4120     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
4121 }
4122 
4123 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
4124 {
4125     int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
4126     if (key >= 2) {
4127         return true;      /* FEAT_CSV2_2 */
4128     }
4129     if (key == 1) {
4130         key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
4131         return key >= 2;  /* FEAT_CSV2_1p2 */
4132     }
4133     return false;
4134 }
4135 
4136 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
4137 {
4138     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
4139 }
4140 
4141 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
4142 {
4143     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
4144 }
4145 
4146 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
4147 {
4148     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
4149 }
4150 
4151 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
4152 {
4153     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
4154 }
4155 
4156 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
4157 {
4158     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
4159 }
4160 
4161 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
4162 {
4163     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
4164 }
4165 
4166 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
4167 {
4168     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0;
4169 }
4170 
4171 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
4172 {
4173     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
4174 }
4175 
4176 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
4177 {
4178     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
4179 }
4180 
4181 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
4182 {
4183     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
4184 }
4185 
4186 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
4187 {
4188     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
4189 }
4190 
4191 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
4192 {
4193     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
4194 }
4195 
4196 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
4197 {
4198     return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64);
4199 }
4200 
4201 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id)
4202 {
4203     return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf;
4204 }
4205 
4206 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
4207 {
4208     return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
4209 }
4210 
4211 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
4212 {
4213     return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
4214 }
4215 
4216 /*
4217  * Feature tests for "does this exist in either 32-bit or 64-bit?"
4218  */
4219 static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
4220 {
4221     return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
4222 }
4223 
4224 static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
4225 {
4226     return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
4227 }
4228 
4229 static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id)
4230 {
4231     return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id);
4232 }
4233 
4234 static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id)
4235 {
4236     return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id);
4237 }
4238 
4239 static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id)
4240 {
4241     return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id);
4242 }
4243 
4244 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
4245 {
4246     return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
4247 }
4248 
4249 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
4250 {
4251     return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
4252 }
4253 
4254 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
4255 {
4256     return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
4257 }
4258 
4259 static inline bool isar_feature_any_ras(const ARMISARegisters *id)
4260 {
4261     return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
4262 }
4263 
4264 static inline bool isar_feature_any_half_evt(const ARMISARegisters *id)
4265 {
4266     return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id);
4267 }
4268 
4269 static inline bool isar_feature_any_evt(const ARMISARegisters *id)
4270 {
4271     return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id);
4272 }
4273 
4274 /*
4275  * Forward to the above feature tests given an ARMCPU pointer.
4276  */
4277 #define cpu_isar_feature(name, cpu) \
4278     ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
4279 
4280 #endif
4281