1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 #define VTCR_NSW (1u << 29) 170 #define VTCR_NSA (1u << 30) 171 #define VSTCR_SW VTCR_NSW 172 #define VSTCR_SA VTCR_NSA 173 174 /* Define a maximum sized vector register. 175 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 176 * For 64-bit, this is a 2048-bit SVE register. 177 * 178 * Note that the mapping between S, D, and Q views of the register bank 179 * differs between AArch64 and AArch32. 180 * In AArch32: 181 * Qn = regs[n].d[1]:regs[n].d[0] 182 * Dn = regs[n / 2].d[n & 1] 183 * Sn = regs[n / 4].d[n % 4 / 2], 184 * bits 31..0 for even n, and bits 63..32 for odd n 185 * (and regs[16] to regs[31] are inaccessible) 186 * In AArch64: 187 * Zn = regs[n].d[*] 188 * Qn = regs[n].d[1]:regs[n].d[0] 189 * Dn = regs[n].d[0] 190 * Sn = regs[n].d[0] bits 31..0 191 * Hn = regs[n].d[0] bits 15..0 192 * 193 * This corresponds to the architecturally defined mapping between 194 * the two execution states, and means we do not need to explicitly 195 * map these registers when changing states. 196 * 197 * Align the data for use with TCG host vector operations. 198 */ 199 200 #ifdef TARGET_AARCH64 201 # define ARM_MAX_VQ 16 202 #else 203 # define ARM_MAX_VQ 1 204 #endif 205 206 typedef struct ARMVectorReg { 207 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 208 } ARMVectorReg; 209 210 #ifdef TARGET_AARCH64 211 /* In AArch32 mode, predicate registers do not exist at all. */ 212 typedef struct ARMPredicateReg { 213 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 214 } ARMPredicateReg; 215 216 /* In AArch32 mode, PAC keys do not exist at all. */ 217 typedef struct ARMPACKey { 218 uint64_t lo, hi; 219 } ARMPACKey; 220 #endif 221 222 /* See the commentary above the TBFLAG field definitions. */ 223 typedef struct CPUARMTBFlags { 224 uint32_t flags; 225 target_ulong flags2; 226 } CPUARMTBFlags; 227 228 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 229 230 typedef struct CPUArchState { 231 /* Regs for current mode. */ 232 uint32_t regs[16]; 233 234 /* 32/64 switch only happens when taking and returning from 235 * exceptions so the overlap semantics are taken care of then 236 * instead of having a complicated union. 237 */ 238 /* Regs for A64 mode. */ 239 uint64_t xregs[32]; 240 uint64_t pc; 241 /* PSTATE isn't an architectural register for ARMv8. However, it is 242 * convenient for us to assemble the underlying state into a 32 bit format 243 * identical to the architectural format used for the SPSR. (This is also 244 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 245 * 'pstate' register are.) Of the PSTATE bits: 246 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 247 * semantics as for AArch32, as described in the comments on each field) 248 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 249 * DAIF (exception masks) are kept in env->daif 250 * BTYPE is kept in env->btype 251 * SM and ZA are kept in env->svcr 252 * all other bits are stored in their correct places in env->pstate 253 */ 254 uint32_t pstate; 255 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 256 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 257 258 /* Cached TBFLAGS state. See below for which bits are included. */ 259 CPUARMTBFlags hflags; 260 261 /* Frequently accessed CPSR bits are stored separately for efficiency. 262 This contains all the other bits. Use cpsr_{read,write} to access 263 the whole CPSR. */ 264 uint32_t uncached_cpsr; 265 uint32_t spsr; 266 267 /* Banked registers. */ 268 uint64_t banked_spsr[8]; 269 uint32_t banked_r13[8]; 270 uint32_t banked_r14[8]; 271 272 /* These hold r8-r12. */ 273 uint32_t usr_regs[5]; 274 uint32_t fiq_regs[5]; 275 276 /* cpsr flag cache for faster execution */ 277 uint32_t CF; /* 0 or 1 */ 278 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 279 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 280 uint32_t ZF; /* Z set if zero. */ 281 uint32_t QF; /* 0 or 1 */ 282 uint32_t GE; /* cpsr[19:16] */ 283 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 284 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 285 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 286 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 287 288 uint64_t elr_el[4]; /* AArch64 exception link regs */ 289 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 290 291 /* System control coprocessor (cp15) */ 292 struct { 293 uint32_t c0_cpuid; 294 union { /* Cache size selection */ 295 struct { 296 uint64_t _unused_csselr0; 297 uint64_t csselr_ns; 298 uint64_t _unused_csselr1; 299 uint64_t csselr_s; 300 }; 301 uint64_t csselr_el[4]; 302 }; 303 union { /* System control register. */ 304 struct { 305 uint64_t _unused_sctlr; 306 uint64_t sctlr_ns; 307 uint64_t hsctlr; 308 uint64_t sctlr_s; 309 }; 310 uint64_t sctlr_el[4]; 311 }; 312 uint64_t vsctlr; /* Virtualization System control register. */ 313 uint64_t cpacr_el1; /* Architectural feature access control register */ 314 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 315 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 316 uint64_t sder; /* Secure debug enable register. */ 317 uint32_t nsacr; /* Non-secure access control register. */ 318 union { /* MMU translation table base 0. */ 319 struct { 320 uint64_t _unused_ttbr0_0; 321 uint64_t ttbr0_ns; 322 uint64_t _unused_ttbr0_1; 323 uint64_t ttbr0_s; 324 }; 325 uint64_t ttbr0_el[4]; 326 }; 327 union { /* MMU translation table base 1. */ 328 struct { 329 uint64_t _unused_ttbr1_0; 330 uint64_t ttbr1_ns; 331 uint64_t _unused_ttbr1_1; 332 uint64_t ttbr1_s; 333 }; 334 uint64_t ttbr1_el[4]; 335 }; 336 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 337 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 338 /* MMU translation table base control. */ 339 uint64_t tcr_el[4]; 340 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 341 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 342 uint32_t c2_data; /* MPU data cacheable bits. */ 343 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 344 union { /* MMU domain access control register 345 * MPU write buffer control. 346 */ 347 struct { 348 uint64_t dacr_ns; 349 uint64_t dacr_s; 350 }; 351 struct { 352 uint64_t dacr32_el2; 353 }; 354 }; 355 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 356 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 357 uint64_t hcr_el2; /* Hypervisor configuration register */ 358 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 359 uint64_t scr_el3; /* Secure configuration register. */ 360 union { /* Fault status registers. */ 361 struct { 362 uint64_t ifsr_ns; 363 uint64_t ifsr_s; 364 }; 365 struct { 366 uint64_t ifsr32_el2; 367 }; 368 }; 369 union { 370 struct { 371 uint64_t _unused_dfsr; 372 uint64_t dfsr_ns; 373 uint64_t hsr; 374 uint64_t dfsr_s; 375 }; 376 uint64_t esr_el[4]; 377 }; 378 uint32_t c6_region[8]; /* MPU base/size registers. */ 379 union { /* Fault address registers. */ 380 struct { 381 uint64_t _unused_far0; 382 #if HOST_BIG_ENDIAN 383 uint32_t ifar_ns; 384 uint32_t dfar_ns; 385 uint32_t ifar_s; 386 uint32_t dfar_s; 387 #else 388 uint32_t dfar_ns; 389 uint32_t ifar_ns; 390 uint32_t dfar_s; 391 uint32_t ifar_s; 392 #endif 393 uint64_t _unused_far3; 394 }; 395 uint64_t far_el[4]; 396 }; 397 uint64_t hpfar_el2; 398 uint64_t hstr_el2; 399 union { /* Translation result. */ 400 struct { 401 uint64_t _unused_par_0; 402 uint64_t par_ns; 403 uint64_t _unused_par_1; 404 uint64_t par_s; 405 }; 406 uint64_t par_el[4]; 407 }; 408 409 uint32_t c9_insn; /* Cache lockdown registers. */ 410 uint32_t c9_data; 411 uint64_t c9_pmcr; /* performance monitor control register */ 412 uint64_t c9_pmcnten; /* perf monitor counter enables */ 413 uint64_t c9_pmovsr; /* perf monitor overflow status */ 414 uint64_t c9_pmuserenr; /* perf monitor user enable */ 415 uint64_t c9_pmselr; /* perf monitor counter selection register */ 416 uint64_t c9_pminten; /* perf monitor interrupt enables */ 417 union { /* Memory attribute redirection */ 418 struct { 419 #if HOST_BIG_ENDIAN 420 uint64_t _unused_mair_0; 421 uint32_t mair1_ns; 422 uint32_t mair0_ns; 423 uint64_t _unused_mair_1; 424 uint32_t mair1_s; 425 uint32_t mair0_s; 426 #else 427 uint64_t _unused_mair_0; 428 uint32_t mair0_ns; 429 uint32_t mair1_ns; 430 uint64_t _unused_mair_1; 431 uint32_t mair0_s; 432 uint32_t mair1_s; 433 #endif 434 }; 435 uint64_t mair_el[4]; 436 }; 437 union { /* vector base address register */ 438 struct { 439 uint64_t _unused_vbar; 440 uint64_t vbar_ns; 441 uint64_t hvbar; 442 uint64_t vbar_s; 443 }; 444 uint64_t vbar_el[4]; 445 }; 446 uint32_t mvbar; /* (monitor) vector base address register */ 447 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 448 struct { /* FCSE PID. */ 449 uint32_t fcseidr_ns; 450 uint32_t fcseidr_s; 451 }; 452 union { /* Context ID. */ 453 struct { 454 uint64_t _unused_contextidr_0; 455 uint64_t contextidr_ns; 456 uint64_t _unused_contextidr_1; 457 uint64_t contextidr_s; 458 }; 459 uint64_t contextidr_el[4]; 460 }; 461 union { /* User RW Thread register. */ 462 struct { 463 uint64_t tpidrurw_ns; 464 uint64_t tpidrprw_ns; 465 uint64_t htpidr; 466 uint64_t _tpidr_el3; 467 }; 468 uint64_t tpidr_el[4]; 469 }; 470 uint64_t tpidr2_el0; 471 /* The secure banks of these registers don't map anywhere */ 472 uint64_t tpidrurw_s; 473 uint64_t tpidrprw_s; 474 uint64_t tpidruro_s; 475 476 union { /* User RO Thread register. */ 477 uint64_t tpidruro_ns; 478 uint64_t tpidrro_el[1]; 479 }; 480 uint64_t c14_cntfrq; /* Counter Frequency register */ 481 uint64_t c14_cntkctl; /* Timer Control register */ 482 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 483 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 484 ARMGenericTimer c14_timer[NUM_GTIMERS]; 485 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 486 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 487 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 488 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 489 uint32_t c15_threadid; /* TI debugger thread-ID. */ 490 uint32_t c15_config_base_address; /* SCU base address. */ 491 uint32_t c15_diagnostic; /* diagnostic register */ 492 uint32_t c15_power_diagnostic; 493 uint32_t c15_power_control; /* power control */ 494 uint64_t dbgbvr[16]; /* breakpoint value registers */ 495 uint64_t dbgbcr[16]; /* breakpoint control registers */ 496 uint64_t dbgwvr[16]; /* watchpoint value registers */ 497 uint64_t dbgwcr[16]; /* watchpoint control registers */ 498 uint64_t dbgclaim; /* DBGCLAIM bits */ 499 uint64_t mdscr_el1; 500 uint64_t oslsr_el1; /* OS Lock Status */ 501 uint64_t osdlr_el1; /* OS DoubleLock status */ 502 uint64_t mdcr_el2; 503 uint64_t mdcr_el3; 504 /* Stores the architectural value of the counter *the last time it was 505 * updated* by pmccntr_op_start. Accesses should always be surrounded 506 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 507 * architecturally-correct value is being read/set. 508 */ 509 uint64_t c15_ccnt; 510 /* Stores the delta between the architectural value and the underlying 511 * cycle count during normal operation. It is used to update c15_ccnt 512 * to be the correct architectural value before accesses. During 513 * accesses, c15_ccnt_delta contains the underlying count being used 514 * for the access, after which it reverts to the delta value in 515 * pmccntr_op_finish. 516 */ 517 uint64_t c15_ccnt_delta; 518 uint64_t c14_pmevcntr[31]; 519 uint64_t c14_pmevcntr_delta[31]; 520 uint64_t c14_pmevtyper[31]; 521 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 522 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 523 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 524 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 525 uint64_t gcr_el1; 526 uint64_t rgsr_el1; 527 528 /* Minimal RAS registers */ 529 uint64_t disr_el1; 530 uint64_t vdisr_el2; 531 uint64_t vsesr_el2; 532 } cp15; 533 534 struct { 535 /* M profile has up to 4 stack pointers: 536 * a Main Stack Pointer and a Process Stack Pointer for each 537 * of the Secure and Non-Secure states. (If the CPU doesn't support 538 * the security extension then it has only two SPs.) 539 * In QEMU we always store the currently active SP in regs[13], 540 * and the non-active SP for the current security state in 541 * v7m.other_sp. The stack pointers for the inactive security state 542 * are stored in other_ss_msp and other_ss_psp. 543 * switch_v7m_security_state() is responsible for rearranging them 544 * when we change security state. 545 */ 546 uint32_t other_sp; 547 uint32_t other_ss_msp; 548 uint32_t other_ss_psp; 549 uint32_t vecbase[M_REG_NUM_BANKS]; 550 uint32_t basepri[M_REG_NUM_BANKS]; 551 uint32_t control[M_REG_NUM_BANKS]; 552 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 553 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 554 uint32_t hfsr; /* HardFault Status */ 555 uint32_t dfsr; /* Debug Fault Status Register */ 556 uint32_t sfsr; /* Secure Fault Status Register */ 557 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 558 uint32_t bfar; /* BusFault Address */ 559 uint32_t sfar; /* Secure Fault Address Register */ 560 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 561 int exception; 562 uint32_t primask[M_REG_NUM_BANKS]; 563 uint32_t faultmask[M_REG_NUM_BANKS]; 564 uint32_t aircr; /* only holds r/w state if security extn implemented */ 565 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 566 uint32_t csselr[M_REG_NUM_BANKS]; 567 uint32_t scr[M_REG_NUM_BANKS]; 568 uint32_t msplim[M_REG_NUM_BANKS]; 569 uint32_t psplim[M_REG_NUM_BANKS]; 570 uint32_t fpcar[M_REG_NUM_BANKS]; 571 uint32_t fpccr[M_REG_NUM_BANKS]; 572 uint32_t fpdscr[M_REG_NUM_BANKS]; 573 uint32_t cpacr[M_REG_NUM_BANKS]; 574 uint32_t nsacr; 575 uint32_t ltpsize; 576 uint32_t vpr; 577 } v7m; 578 579 /* Information associated with an exception about to be taken: 580 * code which raises an exception must set cs->exception_index and 581 * the relevant parts of this structure; the cpu_do_interrupt function 582 * will then set the guest-visible registers as part of the exception 583 * entry process. 584 */ 585 struct { 586 uint32_t syndrome; /* AArch64 format syndrome register */ 587 uint32_t fsr; /* AArch32 format fault status register info */ 588 uint64_t vaddress; /* virtual addr associated with exception, if any */ 589 uint32_t target_el; /* EL the exception should be targeted for */ 590 /* If we implement EL2 we will also need to store information 591 * about the intermediate physical address for stage 2 faults. 592 */ 593 } exception; 594 595 /* Information associated with an SError */ 596 struct { 597 uint8_t pending; 598 uint8_t has_esr; 599 uint64_t esr; 600 } serror; 601 602 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 603 604 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 605 uint32_t irq_line_state; 606 607 /* Thumb-2 EE state. */ 608 uint32_t teecr; 609 uint32_t teehbr; 610 611 /* VFP coprocessor state. */ 612 struct { 613 ARMVectorReg zregs[32]; 614 615 #ifdef TARGET_AARCH64 616 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 617 #define FFR_PRED_NUM 16 618 ARMPredicateReg pregs[17]; 619 /* Scratch space for aa64 sve predicate temporary. */ 620 ARMPredicateReg preg_tmp; 621 #endif 622 623 /* We store these fpcsr fields separately for convenience. */ 624 uint32_t qc[4] QEMU_ALIGNED(16); 625 int vec_len; 626 int vec_stride; 627 628 uint32_t xregs[16]; 629 630 /* Scratch space for aa32 neon expansion. */ 631 uint32_t scratch[8]; 632 633 /* There are a number of distinct float control structures: 634 * 635 * fp_status: is the "normal" fp status. 636 * fp_status_fp16: used for half-precision calculations 637 * standard_fp_status : the ARM "Standard FPSCR Value" 638 * standard_fp_status_fp16 : used for half-precision 639 * calculations with the ARM "Standard FPSCR Value" 640 * 641 * Half-precision operations are governed by a separate 642 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 643 * status structure to control this. 644 * 645 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 646 * round-to-nearest and is used by any operations (generally 647 * Neon) which the architecture defines as controlled by the 648 * standard FPSCR value rather than the FPSCR. 649 * 650 * The "standard FPSCR but for fp16 ops" is needed because 651 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 652 * using a fixed value for it. 653 * 654 * To avoid having to transfer exception bits around, we simply 655 * say that the FPSCR cumulative exception flags are the logical 656 * OR of the flags in the four fp statuses. This relies on the 657 * only thing which needs to read the exception flags being 658 * an explicit FPSCR read. 659 */ 660 float_status fp_status; 661 float_status fp_status_f16; 662 float_status standard_fp_status; 663 float_status standard_fp_status_f16; 664 665 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 666 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 667 } vfp; 668 uint64_t exclusive_addr; 669 uint64_t exclusive_val; 670 uint64_t exclusive_high; 671 672 /* iwMMXt coprocessor state. */ 673 struct { 674 uint64_t regs[16]; 675 uint64_t val; 676 677 uint32_t cregs[16]; 678 } iwmmxt; 679 680 #ifdef TARGET_AARCH64 681 struct { 682 ARMPACKey apia; 683 ARMPACKey apib; 684 ARMPACKey apda; 685 ARMPACKey apdb; 686 ARMPACKey apga; 687 } keys; 688 689 uint64_t scxtnum_el[4]; 690 691 /* 692 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 693 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 694 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 695 * When SVL is less than the architectural maximum, the accessible 696 * storage is restricted, such that if the SVL is X bytes the guest can 697 * see only the bottom X elements of zarray[], and only the least 698 * significant X bytes of each element of the array. (In other words, 699 * the observable part is always square.) 700 * 701 * The ZA storage can also be considered as a set of square tiles of 702 * elements of different sizes. The mapping from tiles to the ZA array 703 * is architecturally defined, such that for tiles of elements of esz 704 * bytes, the Nth row (or "horizontal slice") of tile T is in 705 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 706 * in the ZA storage, because its rows are striped through the ZA array. 707 * 708 * Because this is so large, keep this toward the end of the reset area, 709 * to keep the offsets into the rest of the structure smaller. 710 */ 711 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 712 #endif 713 714 #if defined(CONFIG_USER_ONLY) 715 /* For usermode syscall translation. */ 716 int eabi; 717 #endif 718 719 struct CPUBreakpoint *cpu_breakpoint[16]; 720 struct CPUWatchpoint *cpu_watchpoint[16]; 721 722 /* Optional fault info across tlb lookup. */ 723 ARMMMUFaultInfo *tlb_fi; 724 725 /* Fields up to this point are cleared by a CPU reset */ 726 struct {} end_reset_fields; 727 728 /* Fields after this point are preserved across CPU reset. */ 729 730 /* Internal CPU feature flags. */ 731 uint64_t features; 732 733 /* PMSAv7 MPU */ 734 struct { 735 uint32_t *drbar; 736 uint32_t *drsr; 737 uint32_t *dracr; 738 uint32_t rnr[M_REG_NUM_BANKS]; 739 } pmsav7; 740 741 /* PMSAv8 MPU */ 742 struct { 743 /* The PMSAv8 implementation also shares some PMSAv7 config 744 * and state: 745 * pmsav7.rnr (region number register) 746 * pmsav7_dregion (number of configured regions) 747 */ 748 uint32_t *rbar[M_REG_NUM_BANKS]; 749 uint32_t *rlar[M_REG_NUM_BANKS]; 750 uint32_t *hprbar; 751 uint32_t *hprlar; 752 uint32_t mair0[M_REG_NUM_BANKS]; 753 uint32_t mair1[M_REG_NUM_BANKS]; 754 uint32_t hprselr; 755 } pmsav8; 756 757 /* v8M SAU */ 758 struct { 759 uint32_t *rbar; 760 uint32_t *rlar; 761 uint32_t rnr; 762 uint32_t ctrl; 763 } sau; 764 765 void *nvic; 766 const struct arm_boot_info *boot_info; 767 /* Store GICv3CPUState to access from this struct */ 768 void *gicv3state; 769 770 #ifdef TARGET_TAGGED_ADDRESSES 771 /* Linux syscall tagged address support */ 772 bool tagged_addr_enable; 773 #endif 774 } CPUARMState; 775 776 static inline void set_feature(CPUARMState *env, int feature) 777 { 778 env->features |= 1ULL << feature; 779 } 780 781 static inline void unset_feature(CPUARMState *env, int feature) 782 { 783 env->features &= ~(1ULL << feature); 784 } 785 786 /** 787 * ARMELChangeHookFn: 788 * type of a function which can be registered via arm_register_el_change_hook() 789 * to get callbacks when the CPU changes its exception level or mode. 790 */ 791 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 792 typedef struct ARMELChangeHook ARMELChangeHook; 793 struct ARMELChangeHook { 794 ARMELChangeHookFn *hook; 795 void *opaque; 796 QLIST_ENTRY(ARMELChangeHook) node; 797 }; 798 799 /* These values map onto the return values for 800 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 801 typedef enum ARMPSCIState { 802 PSCI_ON = 0, 803 PSCI_OFF = 1, 804 PSCI_ON_PENDING = 2 805 } ARMPSCIState; 806 807 typedef struct ARMISARegisters ARMISARegisters; 808 809 /* 810 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 811 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 812 * 813 * While processing properties during initialization, corresponding init bits 814 * are set for bits in sve_vq_map that have been set by properties. 815 * 816 * Bits set in supported represent valid vector lengths for the CPU type. 817 */ 818 typedef struct { 819 uint32_t map, init, supported; 820 } ARMVQMap; 821 822 /** 823 * ARMCPU: 824 * @env: #CPUARMState 825 * 826 * An ARM CPU core. 827 */ 828 struct ArchCPU { 829 /*< private >*/ 830 CPUState parent_obj; 831 /*< public >*/ 832 833 CPUNegativeOffsetState neg; 834 CPUARMState env; 835 836 /* Coprocessor information */ 837 GHashTable *cp_regs; 838 /* For marshalling (mostly coprocessor) register state between the 839 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 840 * we use these arrays. 841 */ 842 /* List of register indexes managed via these arrays; (full KVM style 843 * 64 bit indexes, not CPRegInfo 32 bit indexes) 844 */ 845 uint64_t *cpreg_indexes; 846 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 847 uint64_t *cpreg_values; 848 /* Length of the indexes, values, reset_values arrays */ 849 int32_t cpreg_array_len; 850 /* These are used only for migration: incoming data arrives in 851 * these fields and is sanity checked in post_load before copying 852 * to the working data structures above. 853 */ 854 uint64_t *cpreg_vmstate_indexes; 855 uint64_t *cpreg_vmstate_values; 856 int32_t cpreg_vmstate_array_len; 857 858 DynamicGDBXMLInfo dyn_sysreg_xml; 859 DynamicGDBXMLInfo dyn_svereg_xml; 860 861 /* Timers used by the generic (architected) timer */ 862 QEMUTimer *gt_timer[NUM_GTIMERS]; 863 /* 864 * Timer used by the PMU. Its state is restored after migration by 865 * pmu_op_finish() - it does not need other handling during migration 866 */ 867 QEMUTimer *pmu_timer; 868 /* GPIO outputs for generic timer */ 869 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 870 /* GPIO output for GICv3 maintenance interrupt signal */ 871 qemu_irq gicv3_maintenance_interrupt; 872 /* GPIO output for the PMU interrupt */ 873 qemu_irq pmu_interrupt; 874 875 /* MemoryRegion to use for secure physical accesses */ 876 MemoryRegion *secure_memory; 877 878 /* MemoryRegion to use for allocation tag accesses */ 879 MemoryRegion *tag_memory; 880 MemoryRegion *secure_tag_memory; 881 882 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 883 Object *idau; 884 885 /* 'compatible' string for this CPU for Linux device trees */ 886 const char *dtb_compatible; 887 888 /* PSCI version for this CPU 889 * Bits[31:16] = Major Version 890 * Bits[15:0] = Minor Version 891 */ 892 uint32_t psci_version; 893 894 /* Current power state, access guarded by BQL */ 895 ARMPSCIState power_state; 896 897 /* CPU has virtualization extension */ 898 bool has_el2; 899 /* CPU has security extension */ 900 bool has_el3; 901 /* CPU has PMU (Performance Monitor Unit) */ 902 bool has_pmu; 903 /* CPU has VFP */ 904 bool has_vfp; 905 /* CPU has Neon */ 906 bool has_neon; 907 /* CPU has M-profile DSP extension */ 908 bool has_dsp; 909 910 /* CPU has memory protection unit */ 911 bool has_mpu; 912 /* PMSAv7 MPU number of supported regions */ 913 uint32_t pmsav7_dregion; 914 /* PMSAv8 MPU number of supported hyp regions */ 915 uint32_t pmsav8r_hdregion; 916 /* v8M SAU number of supported regions */ 917 uint32_t sau_sregion; 918 919 /* PSCI conduit used to invoke PSCI methods 920 * 0 - disabled, 1 - smc, 2 - hvc 921 */ 922 uint32_t psci_conduit; 923 924 /* For v8M, initial value of the Secure VTOR */ 925 uint32_t init_svtor; 926 /* For v8M, initial value of the Non-secure VTOR */ 927 uint32_t init_nsvtor; 928 929 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 930 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 931 */ 932 uint32_t kvm_target; 933 934 /* KVM init features for this CPU */ 935 uint32_t kvm_init_features[7]; 936 937 /* KVM CPU state */ 938 939 /* KVM virtual time adjustment */ 940 bool kvm_adjvtime; 941 bool kvm_vtime_dirty; 942 uint64_t kvm_vtime; 943 944 /* KVM steal time */ 945 OnOffAuto kvm_steal_time; 946 947 /* Uniprocessor system with MP extensions */ 948 bool mp_is_up; 949 950 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 951 * and the probe failed (so we need to report the error in realize) 952 */ 953 bool host_cpu_probe_failed; 954 955 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 956 * register. 957 */ 958 int32_t core_count; 959 960 /* The instance init functions for implementation-specific subclasses 961 * set these fields to specify the implementation-dependent values of 962 * various constant registers and reset values of non-constant 963 * registers. 964 * Some of these might become QOM properties eventually. 965 * Field names match the official register names as defined in the 966 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 967 * is used for reset values of non-constant registers; no reset_ 968 * prefix means a constant register. 969 * Some of these registers are split out into a substructure that 970 * is shared with the translators to control the ISA. 971 * 972 * Note that if you add an ID register to the ARMISARegisters struct 973 * you need to also update the 32-bit and 64-bit versions of the 974 * kvm_arm_get_host_cpu_features() function to correctly populate the 975 * field by reading the value from the KVM vCPU. 976 */ 977 struct ARMISARegisters { 978 uint32_t id_isar0; 979 uint32_t id_isar1; 980 uint32_t id_isar2; 981 uint32_t id_isar3; 982 uint32_t id_isar4; 983 uint32_t id_isar5; 984 uint32_t id_isar6; 985 uint32_t id_mmfr0; 986 uint32_t id_mmfr1; 987 uint32_t id_mmfr2; 988 uint32_t id_mmfr3; 989 uint32_t id_mmfr4; 990 uint32_t id_mmfr5; 991 uint32_t id_pfr0; 992 uint32_t id_pfr1; 993 uint32_t id_pfr2; 994 uint32_t mvfr0; 995 uint32_t mvfr1; 996 uint32_t mvfr2; 997 uint32_t id_dfr0; 998 uint32_t id_dfr1; 999 uint32_t dbgdidr; 1000 uint32_t dbgdevid; 1001 uint32_t dbgdevid1; 1002 uint64_t id_aa64isar0; 1003 uint64_t id_aa64isar1; 1004 uint64_t id_aa64pfr0; 1005 uint64_t id_aa64pfr1; 1006 uint64_t id_aa64mmfr0; 1007 uint64_t id_aa64mmfr1; 1008 uint64_t id_aa64mmfr2; 1009 uint64_t id_aa64dfr0; 1010 uint64_t id_aa64dfr1; 1011 uint64_t id_aa64zfr0; 1012 uint64_t id_aa64smfr0; 1013 uint64_t reset_pmcr_el0; 1014 } isar; 1015 uint64_t midr; 1016 uint32_t revidr; 1017 uint32_t reset_fpsid; 1018 uint64_t ctr; 1019 uint32_t reset_sctlr; 1020 uint64_t pmceid0; 1021 uint64_t pmceid1; 1022 uint32_t id_afr0; 1023 uint64_t id_aa64afr0; 1024 uint64_t id_aa64afr1; 1025 uint64_t clidr; 1026 uint64_t mp_affinity; /* MP ID without feature bits */ 1027 /* The elements of this array are the CCSIDR values for each cache, 1028 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1029 */ 1030 uint64_t ccsidr[16]; 1031 uint64_t reset_cbar; 1032 uint32_t reset_auxcr; 1033 bool reset_hivecs; 1034 1035 /* 1036 * Intermediate values used during property parsing. 1037 * Once finalized, the values should be read from ID_AA64*. 1038 */ 1039 bool prop_pauth; 1040 bool prop_pauth_impdef; 1041 bool prop_lpa2; 1042 1043 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1044 uint32_t dcz_blocksize; 1045 uint64_t rvbar_prop; /* Property/input signals. */ 1046 1047 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1048 int gic_num_lrs; /* number of list registers */ 1049 int gic_vpribits; /* number of virtual priority bits */ 1050 int gic_vprebits; /* number of virtual preemption bits */ 1051 int gic_pribits; /* number of physical priority bits */ 1052 1053 /* Whether the cfgend input is high (i.e. this CPU should reset into 1054 * big-endian mode). This setting isn't used directly: instead it modifies 1055 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1056 * architecture version. 1057 */ 1058 bool cfgend; 1059 1060 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1061 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1062 1063 int32_t node_id; /* NUMA node this CPU belongs to */ 1064 1065 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1066 uint8_t device_irq_level; 1067 1068 /* Used to set the maximum vector length the cpu will support. */ 1069 uint32_t sve_max_vq; 1070 1071 #ifdef CONFIG_USER_ONLY 1072 /* Used to set the default vector length at process start. */ 1073 uint32_t sve_default_vq; 1074 uint32_t sme_default_vq; 1075 #endif 1076 1077 ARMVQMap sve_vq; 1078 ARMVQMap sme_vq; 1079 1080 /* Generic timer counter frequency, in Hz */ 1081 uint64_t gt_cntfrq_hz; 1082 }; 1083 1084 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1085 1086 void arm_cpu_post_init(Object *obj); 1087 1088 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1089 1090 #ifndef CONFIG_USER_ONLY 1091 extern const VMStateDescription vmstate_arm_cpu; 1092 1093 void arm_cpu_do_interrupt(CPUState *cpu); 1094 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1095 #endif /* !CONFIG_USER_ONLY */ 1096 1097 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1098 MemTxAttrs *attrs); 1099 1100 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1101 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1102 1103 /* 1104 * Helpers to dynamically generates XML descriptions of the sysregs 1105 * and SVE registers. Returns the number of registers in each set. 1106 */ 1107 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1108 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1109 1110 /* Returns the dynamically generated XML for the gdb stub. 1111 * Returns a pointer to the XML contents for the specified XML file or NULL 1112 * if the XML name doesn't match the predefined one. 1113 */ 1114 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1115 1116 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1117 int cpuid, DumpState *s); 1118 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1119 int cpuid, DumpState *s); 1120 1121 #ifdef TARGET_AARCH64 1122 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1123 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1124 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1125 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1126 int new_el, bool el0_a64); 1127 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1128 1129 /* 1130 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1131 * The byte at offset i from the start of the in-memory representation contains 1132 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1133 * lowest offsets are stored in the lowest memory addresses, then that nearly 1134 * matches QEMU's representation, which is to use an array of host-endian 1135 * uint64_t's, where the lower offsets are at the lower indices. To complete 1136 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1137 */ 1138 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1139 { 1140 #if HOST_BIG_ENDIAN 1141 int i; 1142 1143 for (i = 0; i < nr; ++i) { 1144 dst[i] = bswap64(src[i]); 1145 } 1146 1147 return dst; 1148 #else 1149 return src; 1150 #endif 1151 } 1152 1153 #else 1154 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1155 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1156 int n, bool a) 1157 { } 1158 #endif 1159 1160 void aarch64_sync_32_to_64(CPUARMState *env); 1161 void aarch64_sync_64_to_32(CPUARMState *env); 1162 1163 int fp_exception_el(CPUARMState *env, int cur_el); 1164 int sve_exception_el(CPUARMState *env, int cur_el); 1165 int sme_exception_el(CPUARMState *env, int cur_el); 1166 1167 /** 1168 * sve_vqm1_for_el_sm: 1169 * @env: CPUARMState 1170 * @el: exception level 1171 * @sm: streaming mode 1172 * 1173 * Compute the current vector length for @el & @sm, in units of 1174 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1175 * If @sm, compute for SVL, otherwise NVL. 1176 */ 1177 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1178 1179 /* Likewise, but using @sm = PSTATE.SM. */ 1180 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1181 1182 static inline bool is_a64(CPUARMState *env) 1183 { 1184 return env->aarch64; 1185 } 1186 1187 /** 1188 * pmu_op_start/finish 1189 * @env: CPUARMState 1190 * 1191 * Convert all PMU counters between their delta form (the typical mode when 1192 * they are enabled) and the guest-visible values. These two calls must 1193 * surround any action which might affect the counters. 1194 */ 1195 void pmu_op_start(CPUARMState *env); 1196 void pmu_op_finish(CPUARMState *env); 1197 1198 /* 1199 * Called when a PMU counter is due to overflow 1200 */ 1201 void arm_pmu_timer_cb(void *opaque); 1202 1203 /** 1204 * Functions to register as EL change hooks for PMU mode filtering 1205 */ 1206 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1207 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1208 1209 /* 1210 * pmu_init 1211 * @cpu: ARMCPU 1212 * 1213 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1214 * for the current configuration 1215 */ 1216 void pmu_init(ARMCPU *cpu); 1217 1218 /* SCTLR bit meanings. Several bits have been reused in newer 1219 * versions of the architecture; in that case we define constants 1220 * for both old and new bit meanings. Code which tests against those 1221 * bits should probably check or otherwise arrange that the CPU 1222 * is the architectural version it expects. 1223 */ 1224 #define SCTLR_M (1U << 0) 1225 #define SCTLR_A (1U << 1) 1226 #define SCTLR_C (1U << 2) 1227 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1228 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1229 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1230 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1231 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1232 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1233 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1234 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1235 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1236 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1237 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1238 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1239 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1240 #define SCTLR_SED (1U << 8) /* v8 onward */ 1241 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1242 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1243 #define SCTLR_F (1U << 10) /* up to v6 */ 1244 #define SCTLR_SW (1U << 10) /* v7 */ 1245 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1246 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1247 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1248 #define SCTLR_I (1U << 12) 1249 #define SCTLR_V (1U << 13) /* AArch32 only */ 1250 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1251 #define SCTLR_RR (1U << 14) /* up to v7 */ 1252 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1253 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1254 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1255 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1256 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1257 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1258 #define SCTLR_BR (1U << 17) /* PMSA only */ 1259 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1260 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1261 #define SCTLR_WXN (1U << 19) 1262 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1263 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1264 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1265 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1266 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1267 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1268 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1269 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1270 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1271 #define SCTLR_VE (1U << 24) /* up to v7 */ 1272 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1273 #define SCTLR_EE (1U << 25) 1274 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1275 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1276 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1277 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1278 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1279 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1280 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1281 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1282 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1283 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1284 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1285 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1286 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1287 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1288 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1289 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1290 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1291 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1292 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1293 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1294 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1295 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1296 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1297 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1298 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1299 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1300 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1301 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1302 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1303 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1304 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1305 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1306 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1307 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1308 1309 /* Bit definitions for CPACR (AArch32 only) */ 1310 FIELD(CPACR, CP10, 20, 2) 1311 FIELD(CPACR, CP11, 22, 2) 1312 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1313 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1314 FIELD(CPACR, ASEDIS, 31, 1) 1315 1316 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1317 FIELD(CPACR_EL1, ZEN, 16, 2) 1318 FIELD(CPACR_EL1, FPEN, 20, 2) 1319 FIELD(CPACR_EL1, SMEN, 24, 2) 1320 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1321 1322 /* Bit definitions for HCPTR (AArch32 only) */ 1323 FIELD(HCPTR, TCP10, 10, 1) 1324 FIELD(HCPTR, TCP11, 11, 1) 1325 FIELD(HCPTR, TASE, 15, 1) 1326 FIELD(HCPTR, TTA, 20, 1) 1327 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1328 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1329 1330 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1331 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1332 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1333 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1334 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1335 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1336 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1337 FIELD(CPTR_EL2, TTA, 28, 1) 1338 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1339 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1340 1341 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1342 FIELD(CPTR_EL3, EZ, 8, 1) 1343 FIELD(CPTR_EL3, TFP, 10, 1) 1344 FIELD(CPTR_EL3, ESM, 12, 1) 1345 FIELD(CPTR_EL3, TTA, 20, 1) 1346 FIELD(CPTR_EL3, TAM, 30, 1) 1347 FIELD(CPTR_EL3, TCPAC, 31, 1) 1348 1349 #define MDCR_MTPME (1U << 28) 1350 #define MDCR_TDCC (1U << 27) 1351 #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ 1352 #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ 1353 #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ 1354 #define MDCR_EPMAD (1U << 21) 1355 #define MDCR_EDAD (1U << 20) 1356 #define MDCR_TTRF (1U << 19) 1357 #define MDCR_STE (1U << 18) /* MDCR_EL3 */ 1358 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1359 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1360 #define MDCR_SDD (1U << 16) 1361 #define MDCR_SPD (3U << 14) 1362 #define MDCR_TDRA (1U << 11) 1363 #define MDCR_TDOSA (1U << 10) 1364 #define MDCR_TDA (1U << 9) 1365 #define MDCR_TDE (1U << 8) 1366 #define MDCR_HPME (1U << 7) 1367 #define MDCR_TPM (1U << 6) 1368 #define MDCR_TPMCR (1U << 5) 1369 #define MDCR_HPMN (0x1fU) 1370 1371 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1372 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ 1373 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ 1374 MDCR_STE | MDCR_SPME | MDCR_SPD) 1375 1376 #define CPSR_M (0x1fU) 1377 #define CPSR_T (1U << 5) 1378 #define CPSR_F (1U << 6) 1379 #define CPSR_I (1U << 7) 1380 #define CPSR_A (1U << 8) 1381 #define CPSR_E (1U << 9) 1382 #define CPSR_IT_2_7 (0xfc00U) 1383 #define CPSR_GE (0xfU << 16) 1384 #define CPSR_IL (1U << 20) 1385 #define CPSR_DIT (1U << 21) 1386 #define CPSR_PAN (1U << 22) 1387 #define CPSR_SSBS (1U << 23) 1388 #define CPSR_J (1U << 24) 1389 #define CPSR_IT_0_1 (3U << 25) 1390 #define CPSR_Q (1U << 27) 1391 #define CPSR_V (1U << 28) 1392 #define CPSR_C (1U << 29) 1393 #define CPSR_Z (1U << 30) 1394 #define CPSR_N (1U << 31) 1395 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1396 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1397 1398 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1399 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1400 | CPSR_NZCV) 1401 /* Bits writable in user mode. */ 1402 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1403 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1404 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1405 1406 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1407 #define XPSR_EXCP 0x1ffU 1408 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1409 #define XPSR_IT_2_7 CPSR_IT_2_7 1410 #define XPSR_GE CPSR_GE 1411 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1412 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1413 #define XPSR_IT_0_1 CPSR_IT_0_1 1414 #define XPSR_Q CPSR_Q 1415 #define XPSR_V CPSR_V 1416 #define XPSR_C CPSR_C 1417 #define XPSR_Z CPSR_Z 1418 #define XPSR_N CPSR_N 1419 #define XPSR_NZCV CPSR_NZCV 1420 #define XPSR_IT CPSR_IT 1421 1422 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1423 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1424 #define TTBCR_PD0 (1U << 4) 1425 #define TTBCR_PD1 (1U << 5) 1426 #define TTBCR_EPD0 (1U << 7) 1427 #define TTBCR_IRGN0 (3U << 8) 1428 #define TTBCR_ORGN0 (3U << 10) 1429 #define TTBCR_SH0 (3U << 12) 1430 #define TTBCR_T1SZ (3U << 16) 1431 #define TTBCR_A1 (1U << 22) 1432 #define TTBCR_EPD1 (1U << 23) 1433 #define TTBCR_IRGN1 (3U << 24) 1434 #define TTBCR_ORGN1 (3U << 26) 1435 #define TTBCR_SH1 (1U << 28) 1436 #define TTBCR_EAE (1U << 31) 1437 1438 FIELD(VTCR, T0SZ, 0, 6) 1439 FIELD(VTCR, SL0, 6, 2) 1440 FIELD(VTCR, IRGN0, 8, 2) 1441 FIELD(VTCR, ORGN0, 10, 2) 1442 FIELD(VTCR, SH0, 12, 2) 1443 FIELD(VTCR, TG0, 14, 2) 1444 FIELD(VTCR, PS, 16, 3) 1445 FIELD(VTCR, VS, 19, 1) 1446 FIELD(VTCR, HA, 21, 1) 1447 FIELD(VTCR, HD, 22, 1) 1448 FIELD(VTCR, HWU59, 25, 1) 1449 FIELD(VTCR, HWU60, 26, 1) 1450 FIELD(VTCR, HWU61, 27, 1) 1451 FIELD(VTCR, HWU62, 28, 1) 1452 FIELD(VTCR, NSW, 29, 1) 1453 FIELD(VTCR, NSA, 30, 1) 1454 FIELD(VTCR, DS, 32, 1) 1455 FIELD(VTCR, SL2, 33, 1) 1456 1457 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1458 * Only these are valid when in AArch64 mode; in 1459 * AArch32 mode SPSRs are basically CPSR-format. 1460 */ 1461 #define PSTATE_SP (1U) 1462 #define PSTATE_M (0xFU) 1463 #define PSTATE_nRW (1U << 4) 1464 #define PSTATE_F (1U << 6) 1465 #define PSTATE_I (1U << 7) 1466 #define PSTATE_A (1U << 8) 1467 #define PSTATE_D (1U << 9) 1468 #define PSTATE_BTYPE (3U << 10) 1469 #define PSTATE_SSBS (1U << 12) 1470 #define PSTATE_IL (1U << 20) 1471 #define PSTATE_SS (1U << 21) 1472 #define PSTATE_PAN (1U << 22) 1473 #define PSTATE_UAO (1U << 23) 1474 #define PSTATE_DIT (1U << 24) 1475 #define PSTATE_TCO (1U << 25) 1476 #define PSTATE_V (1U << 28) 1477 #define PSTATE_C (1U << 29) 1478 #define PSTATE_Z (1U << 30) 1479 #define PSTATE_N (1U << 31) 1480 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1481 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1482 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1483 /* Mode values for AArch64 */ 1484 #define PSTATE_MODE_EL3h 13 1485 #define PSTATE_MODE_EL3t 12 1486 #define PSTATE_MODE_EL2h 9 1487 #define PSTATE_MODE_EL2t 8 1488 #define PSTATE_MODE_EL1h 5 1489 #define PSTATE_MODE_EL1t 4 1490 #define PSTATE_MODE_EL0t 0 1491 1492 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1493 FIELD(SVCR, SM, 0, 1) 1494 FIELD(SVCR, ZA, 1, 1) 1495 1496 /* Fields for SMCR_ELx. */ 1497 FIELD(SMCR, LEN, 0, 4) 1498 FIELD(SMCR, FA64, 31, 1) 1499 1500 /* Write a new value to v7m.exception, thus transitioning into or out 1501 * of Handler mode; this may result in a change of active stack pointer. 1502 */ 1503 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1504 1505 /* Map EL and handler into a PSTATE_MODE. */ 1506 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1507 { 1508 return (el << 2) | handler; 1509 } 1510 1511 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1512 * interprocessing, so we don't attempt to sync with the cpsr state used by 1513 * the 32 bit decoder. 1514 */ 1515 static inline uint32_t pstate_read(CPUARMState *env) 1516 { 1517 int ZF; 1518 1519 ZF = (env->ZF == 0); 1520 return (env->NF & 0x80000000) | (ZF << 30) 1521 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1522 | env->pstate | env->daif | (env->btype << 10); 1523 } 1524 1525 static inline void pstate_write(CPUARMState *env, uint32_t val) 1526 { 1527 env->ZF = (~val) & PSTATE_Z; 1528 env->NF = val; 1529 env->CF = (val >> 29) & 1; 1530 env->VF = (val << 3) & 0x80000000; 1531 env->daif = val & PSTATE_DAIF; 1532 env->btype = (val >> 10) & 3; 1533 env->pstate = val & ~CACHED_PSTATE_BITS; 1534 } 1535 1536 /* Return the current CPSR value. */ 1537 uint32_t cpsr_read(CPUARMState *env); 1538 1539 typedef enum CPSRWriteType { 1540 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1541 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1542 CPSRWriteRaw = 2, 1543 /* trust values, no reg bank switch, no hflags rebuild */ 1544 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1545 } CPSRWriteType; 1546 1547 /* 1548 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1549 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1550 * correspond to TB flags bits cached in the hflags, unless @write_type 1551 * is CPSRWriteRaw. 1552 */ 1553 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1554 CPSRWriteType write_type); 1555 1556 /* Return the current xPSR value. */ 1557 static inline uint32_t xpsr_read(CPUARMState *env) 1558 { 1559 int ZF; 1560 ZF = (env->ZF == 0); 1561 return (env->NF & 0x80000000) | (ZF << 30) 1562 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1563 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1564 | ((env->condexec_bits & 0xfc) << 8) 1565 | (env->GE << 16) 1566 | env->v7m.exception; 1567 } 1568 1569 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1570 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1571 { 1572 if (mask & XPSR_NZCV) { 1573 env->ZF = (~val) & XPSR_Z; 1574 env->NF = val; 1575 env->CF = (val >> 29) & 1; 1576 env->VF = (val << 3) & 0x80000000; 1577 } 1578 if (mask & XPSR_Q) { 1579 env->QF = ((val & XPSR_Q) != 0); 1580 } 1581 if (mask & XPSR_GE) { 1582 env->GE = (val & XPSR_GE) >> 16; 1583 } 1584 #ifndef CONFIG_USER_ONLY 1585 if (mask & XPSR_T) { 1586 env->thumb = ((val & XPSR_T) != 0); 1587 } 1588 if (mask & XPSR_IT_0_1) { 1589 env->condexec_bits &= ~3; 1590 env->condexec_bits |= (val >> 25) & 3; 1591 } 1592 if (mask & XPSR_IT_2_7) { 1593 env->condexec_bits &= 3; 1594 env->condexec_bits |= (val >> 8) & 0xfc; 1595 } 1596 if (mask & XPSR_EXCP) { 1597 /* Note that this only happens on exception exit */ 1598 write_v7m_exception(env, val & XPSR_EXCP); 1599 } 1600 #endif 1601 } 1602 1603 #define HCR_VM (1ULL << 0) 1604 #define HCR_SWIO (1ULL << 1) 1605 #define HCR_PTW (1ULL << 2) 1606 #define HCR_FMO (1ULL << 3) 1607 #define HCR_IMO (1ULL << 4) 1608 #define HCR_AMO (1ULL << 5) 1609 #define HCR_VF (1ULL << 6) 1610 #define HCR_VI (1ULL << 7) 1611 #define HCR_VSE (1ULL << 8) 1612 #define HCR_FB (1ULL << 9) 1613 #define HCR_BSU_MASK (3ULL << 10) 1614 #define HCR_DC (1ULL << 12) 1615 #define HCR_TWI (1ULL << 13) 1616 #define HCR_TWE (1ULL << 14) 1617 #define HCR_TID0 (1ULL << 15) 1618 #define HCR_TID1 (1ULL << 16) 1619 #define HCR_TID2 (1ULL << 17) 1620 #define HCR_TID3 (1ULL << 18) 1621 #define HCR_TSC (1ULL << 19) 1622 #define HCR_TIDCP (1ULL << 20) 1623 #define HCR_TACR (1ULL << 21) 1624 #define HCR_TSW (1ULL << 22) 1625 #define HCR_TPCP (1ULL << 23) 1626 #define HCR_TPU (1ULL << 24) 1627 #define HCR_TTLB (1ULL << 25) 1628 #define HCR_TVM (1ULL << 26) 1629 #define HCR_TGE (1ULL << 27) 1630 #define HCR_TDZ (1ULL << 28) 1631 #define HCR_HCD (1ULL << 29) 1632 #define HCR_TRVM (1ULL << 30) 1633 #define HCR_RW (1ULL << 31) 1634 #define HCR_CD (1ULL << 32) 1635 #define HCR_ID (1ULL << 33) 1636 #define HCR_E2H (1ULL << 34) 1637 #define HCR_TLOR (1ULL << 35) 1638 #define HCR_TERR (1ULL << 36) 1639 #define HCR_TEA (1ULL << 37) 1640 #define HCR_MIOCNCE (1ULL << 38) 1641 /* RES0 bit 39 */ 1642 #define HCR_APK (1ULL << 40) 1643 #define HCR_API (1ULL << 41) 1644 #define HCR_NV (1ULL << 42) 1645 #define HCR_NV1 (1ULL << 43) 1646 #define HCR_AT (1ULL << 44) 1647 #define HCR_NV2 (1ULL << 45) 1648 #define HCR_FWB (1ULL << 46) 1649 #define HCR_FIEN (1ULL << 47) 1650 /* RES0 bit 48 */ 1651 #define HCR_TID4 (1ULL << 49) 1652 #define HCR_TICAB (1ULL << 50) 1653 #define HCR_AMVOFFEN (1ULL << 51) 1654 #define HCR_TOCU (1ULL << 52) 1655 #define HCR_ENSCXT (1ULL << 53) 1656 #define HCR_TTLBIS (1ULL << 54) 1657 #define HCR_TTLBOS (1ULL << 55) 1658 #define HCR_ATA (1ULL << 56) 1659 #define HCR_DCT (1ULL << 57) 1660 #define HCR_TID5 (1ULL << 58) 1661 #define HCR_TWEDEN (1ULL << 59) 1662 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1663 1664 #define HCRX_ENAS0 (1ULL << 0) 1665 #define HCRX_ENALS (1ULL << 1) 1666 #define HCRX_ENASR (1ULL << 2) 1667 #define HCRX_FNXS (1ULL << 3) 1668 #define HCRX_FGTNXS (1ULL << 4) 1669 #define HCRX_SMPME (1ULL << 5) 1670 #define HCRX_TALLINT (1ULL << 6) 1671 #define HCRX_VINMI (1ULL << 7) 1672 #define HCRX_VFNMI (1ULL << 8) 1673 #define HCRX_CMOW (1ULL << 9) 1674 #define HCRX_MCE2 (1ULL << 10) 1675 #define HCRX_MSCEN (1ULL << 11) 1676 1677 #define HPFAR_NS (1ULL << 63) 1678 1679 #define SCR_NS (1ULL << 0) 1680 #define SCR_IRQ (1ULL << 1) 1681 #define SCR_FIQ (1ULL << 2) 1682 #define SCR_EA (1ULL << 3) 1683 #define SCR_FW (1ULL << 4) 1684 #define SCR_AW (1ULL << 5) 1685 #define SCR_NET (1ULL << 6) 1686 #define SCR_SMD (1ULL << 7) 1687 #define SCR_HCE (1ULL << 8) 1688 #define SCR_SIF (1ULL << 9) 1689 #define SCR_RW (1ULL << 10) 1690 #define SCR_ST (1ULL << 11) 1691 #define SCR_TWI (1ULL << 12) 1692 #define SCR_TWE (1ULL << 13) 1693 #define SCR_TLOR (1ULL << 14) 1694 #define SCR_TERR (1ULL << 15) 1695 #define SCR_APK (1ULL << 16) 1696 #define SCR_API (1ULL << 17) 1697 #define SCR_EEL2 (1ULL << 18) 1698 #define SCR_EASE (1ULL << 19) 1699 #define SCR_NMEA (1ULL << 20) 1700 #define SCR_FIEN (1ULL << 21) 1701 #define SCR_ENSCXT (1ULL << 25) 1702 #define SCR_ATA (1ULL << 26) 1703 #define SCR_FGTEN (1ULL << 27) 1704 #define SCR_ECVEN (1ULL << 28) 1705 #define SCR_TWEDEN (1ULL << 29) 1706 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1707 #define SCR_TME (1ULL << 34) 1708 #define SCR_AMVOFFEN (1ULL << 35) 1709 #define SCR_ENAS0 (1ULL << 36) 1710 #define SCR_ADEN (1ULL << 37) 1711 #define SCR_HXEN (1ULL << 38) 1712 #define SCR_TRNDR (1ULL << 40) 1713 #define SCR_ENTP2 (1ULL << 41) 1714 #define SCR_GPF (1ULL << 48) 1715 1716 #define HSTR_TTEE (1 << 16) 1717 #define HSTR_TJDBX (1 << 17) 1718 1719 /* Return the current FPSCR value. */ 1720 uint32_t vfp_get_fpscr(CPUARMState *env); 1721 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1722 1723 /* FPCR, Floating Point Control Register 1724 * FPSR, Floating Poiht Status Register 1725 * 1726 * For A64 the FPSCR is split into two logically distinct registers, 1727 * FPCR and FPSR. However since they still use non-overlapping bits 1728 * we store the underlying state in fpscr and just mask on read/write. 1729 */ 1730 #define FPSR_MASK 0xf800009f 1731 #define FPCR_MASK 0x07ff9f00 1732 1733 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1734 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1735 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1736 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1737 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1738 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1739 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1740 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1741 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1742 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1743 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1744 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1745 #define FPCR_V (1 << 28) /* FP overflow flag */ 1746 #define FPCR_C (1 << 29) /* FP carry flag */ 1747 #define FPCR_Z (1 << 30) /* FP zero flag */ 1748 #define FPCR_N (1 << 31) /* FP negative flag */ 1749 1750 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1751 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1752 #define FPCR_LTPSIZE_LENGTH 3 1753 1754 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1755 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1756 1757 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1758 { 1759 return vfp_get_fpscr(env) & FPSR_MASK; 1760 } 1761 1762 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1763 { 1764 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1765 vfp_set_fpscr(env, new_fpscr); 1766 } 1767 1768 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1769 { 1770 return vfp_get_fpscr(env) & FPCR_MASK; 1771 } 1772 1773 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1774 { 1775 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1776 vfp_set_fpscr(env, new_fpscr); 1777 } 1778 1779 enum arm_cpu_mode { 1780 ARM_CPU_MODE_USR = 0x10, 1781 ARM_CPU_MODE_FIQ = 0x11, 1782 ARM_CPU_MODE_IRQ = 0x12, 1783 ARM_CPU_MODE_SVC = 0x13, 1784 ARM_CPU_MODE_MON = 0x16, 1785 ARM_CPU_MODE_ABT = 0x17, 1786 ARM_CPU_MODE_HYP = 0x1a, 1787 ARM_CPU_MODE_UND = 0x1b, 1788 ARM_CPU_MODE_SYS = 0x1f 1789 }; 1790 1791 /* VFP system registers. */ 1792 #define ARM_VFP_FPSID 0 1793 #define ARM_VFP_FPSCR 1 1794 #define ARM_VFP_MVFR2 5 1795 #define ARM_VFP_MVFR1 6 1796 #define ARM_VFP_MVFR0 7 1797 #define ARM_VFP_FPEXC 8 1798 #define ARM_VFP_FPINST 9 1799 #define ARM_VFP_FPINST2 10 1800 /* These ones are M-profile only */ 1801 #define ARM_VFP_FPSCR_NZCVQC 2 1802 #define ARM_VFP_VPR 12 1803 #define ARM_VFP_P0 13 1804 #define ARM_VFP_FPCXT_NS 14 1805 #define ARM_VFP_FPCXT_S 15 1806 1807 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1808 #define QEMU_VFP_FPSCR_NZCV 0xffff 1809 1810 /* iwMMXt coprocessor control registers. */ 1811 #define ARM_IWMMXT_wCID 0 1812 #define ARM_IWMMXT_wCon 1 1813 #define ARM_IWMMXT_wCSSF 2 1814 #define ARM_IWMMXT_wCASF 3 1815 #define ARM_IWMMXT_wCGR0 8 1816 #define ARM_IWMMXT_wCGR1 9 1817 #define ARM_IWMMXT_wCGR2 10 1818 #define ARM_IWMMXT_wCGR3 11 1819 1820 /* V7M CCR bits */ 1821 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1822 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1823 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1824 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1825 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1826 FIELD(V7M_CCR, STKALIGN, 9, 1) 1827 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1828 FIELD(V7M_CCR, DC, 16, 1) 1829 FIELD(V7M_CCR, IC, 17, 1) 1830 FIELD(V7M_CCR, BP, 18, 1) 1831 FIELD(V7M_CCR, LOB, 19, 1) 1832 FIELD(V7M_CCR, TRD, 20, 1) 1833 1834 /* V7M SCR bits */ 1835 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1836 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1837 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1838 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1839 1840 /* V7M AIRCR bits */ 1841 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1842 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1843 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1844 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1845 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1846 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1847 FIELD(V7M_AIRCR, PRIS, 14, 1) 1848 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1849 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1850 1851 /* V7M CFSR bits for MMFSR */ 1852 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1853 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1854 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1855 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1856 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1857 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1858 1859 /* V7M CFSR bits for BFSR */ 1860 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1861 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1862 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1863 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1864 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1865 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1866 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1867 1868 /* V7M CFSR bits for UFSR */ 1869 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1870 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1871 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1872 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1873 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1874 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1875 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1876 1877 /* V7M CFSR bit masks covering all of the subregister bits */ 1878 FIELD(V7M_CFSR, MMFSR, 0, 8) 1879 FIELD(V7M_CFSR, BFSR, 8, 8) 1880 FIELD(V7M_CFSR, UFSR, 16, 16) 1881 1882 /* V7M HFSR bits */ 1883 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1884 FIELD(V7M_HFSR, FORCED, 30, 1) 1885 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1886 1887 /* V7M DFSR bits */ 1888 FIELD(V7M_DFSR, HALTED, 0, 1) 1889 FIELD(V7M_DFSR, BKPT, 1, 1) 1890 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1891 FIELD(V7M_DFSR, VCATCH, 3, 1) 1892 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1893 1894 /* V7M SFSR bits */ 1895 FIELD(V7M_SFSR, INVEP, 0, 1) 1896 FIELD(V7M_SFSR, INVIS, 1, 1) 1897 FIELD(V7M_SFSR, INVER, 2, 1) 1898 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1899 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1900 FIELD(V7M_SFSR, LSPERR, 5, 1) 1901 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1902 FIELD(V7M_SFSR, LSERR, 7, 1) 1903 1904 /* v7M MPU_CTRL bits */ 1905 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1906 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1907 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1908 1909 /* v7M CLIDR bits */ 1910 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1911 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1912 FIELD(V7M_CLIDR, LOC, 24, 3) 1913 FIELD(V7M_CLIDR, LOUU, 27, 3) 1914 FIELD(V7M_CLIDR, ICB, 30, 2) 1915 1916 FIELD(V7M_CSSELR, IND, 0, 1) 1917 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1918 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1919 * define a mask for this and check that it doesn't permit running off 1920 * the end of the array. 1921 */ 1922 FIELD(V7M_CSSELR, INDEX, 0, 4) 1923 1924 /* v7M FPCCR bits */ 1925 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1926 FIELD(V7M_FPCCR, USER, 1, 1) 1927 FIELD(V7M_FPCCR, S, 2, 1) 1928 FIELD(V7M_FPCCR, THREAD, 3, 1) 1929 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1930 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1931 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1932 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1933 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1934 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1935 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1936 FIELD(V7M_FPCCR, RES0, 11, 15) 1937 FIELD(V7M_FPCCR, TS, 26, 1) 1938 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1939 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1940 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1941 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1942 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1943 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1944 #define R_V7M_FPCCR_BANKED_MASK \ 1945 (R_V7M_FPCCR_LSPACT_MASK | \ 1946 R_V7M_FPCCR_USER_MASK | \ 1947 R_V7M_FPCCR_THREAD_MASK | \ 1948 R_V7M_FPCCR_MMRDY_MASK | \ 1949 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1950 R_V7M_FPCCR_UFRDY_MASK | \ 1951 R_V7M_FPCCR_ASPEN_MASK) 1952 1953 /* v7M VPR bits */ 1954 FIELD(V7M_VPR, P0, 0, 16) 1955 FIELD(V7M_VPR, MASK01, 16, 4) 1956 FIELD(V7M_VPR, MASK23, 20, 4) 1957 1958 /* 1959 * System register ID fields. 1960 */ 1961 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1962 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1963 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1964 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1965 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1966 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1967 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1968 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1969 FIELD(CLIDR_EL1, LOC, 24, 3) 1970 FIELD(CLIDR_EL1, LOUU, 27, 3) 1971 FIELD(CLIDR_EL1, ICB, 30, 3) 1972 1973 /* When FEAT_CCIDX is implemented */ 1974 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1975 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1976 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1977 1978 /* When FEAT_CCIDX is not implemented */ 1979 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1980 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1981 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1982 1983 FIELD(CTR_EL0, IMINLINE, 0, 4) 1984 FIELD(CTR_EL0, L1IP, 14, 2) 1985 FIELD(CTR_EL0, DMINLINE, 16, 4) 1986 FIELD(CTR_EL0, ERG, 20, 4) 1987 FIELD(CTR_EL0, CWG, 24, 4) 1988 FIELD(CTR_EL0, IDC, 28, 1) 1989 FIELD(CTR_EL0, DIC, 29, 1) 1990 FIELD(CTR_EL0, TMINLINE, 32, 6) 1991 1992 FIELD(MIDR_EL1, REVISION, 0, 4) 1993 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1994 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1995 FIELD(MIDR_EL1, VARIANT, 20, 4) 1996 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1997 1998 FIELD(ID_ISAR0, SWAP, 0, 4) 1999 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2000 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2001 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2002 FIELD(ID_ISAR0, COPROC, 16, 4) 2003 FIELD(ID_ISAR0, DEBUG, 20, 4) 2004 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2005 2006 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2007 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2008 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2009 FIELD(ID_ISAR1, EXTEND, 12, 4) 2010 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2011 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2012 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2013 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2014 2015 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2016 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2017 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2018 FIELD(ID_ISAR2, MULT, 12, 4) 2019 FIELD(ID_ISAR2, MULTS, 16, 4) 2020 FIELD(ID_ISAR2, MULTU, 20, 4) 2021 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2022 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2023 2024 FIELD(ID_ISAR3, SATURATE, 0, 4) 2025 FIELD(ID_ISAR3, SIMD, 4, 4) 2026 FIELD(ID_ISAR3, SVC, 8, 4) 2027 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2028 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2029 FIELD(ID_ISAR3, T32COPY, 20, 4) 2030 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2031 FIELD(ID_ISAR3, T32EE, 28, 4) 2032 2033 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2034 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2035 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2036 FIELD(ID_ISAR4, SMC, 12, 4) 2037 FIELD(ID_ISAR4, BARRIER, 16, 4) 2038 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2039 FIELD(ID_ISAR4, PSR_M, 24, 4) 2040 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2041 2042 FIELD(ID_ISAR5, SEVL, 0, 4) 2043 FIELD(ID_ISAR5, AES, 4, 4) 2044 FIELD(ID_ISAR5, SHA1, 8, 4) 2045 FIELD(ID_ISAR5, SHA2, 12, 4) 2046 FIELD(ID_ISAR5, CRC32, 16, 4) 2047 FIELD(ID_ISAR5, RDM, 24, 4) 2048 FIELD(ID_ISAR5, VCMA, 28, 4) 2049 2050 FIELD(ID_ISAR6, JSCVT, 0, 4) 2051 FIELD(ID_ISAR6, DP, 4, 4) 2052 FIELD(ID_ISAR6, FHM, 8, 4) 2053 FIELD(ID_ISAR6, SB, 12, 4) 2054 FIELD(ID_ISAR6, SPECRES, 16, 4) 2055 FIELD(ID_ISAR6, BF16, 20, 4) 2056 FIELD(ID_ISAR6, I8MM, 24, 4) 2057 2058 FIELD(ID_MMFR0, VMSA, 0, 4) 2059 FIELD(ID_MMFR0, PMSA, 4, 4) 2060 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2061 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2062 FIELD(ID_MMFR0, TCM, 16, 4) 2063 FIELD(ID_MMFR0, AUXREG, 20, 4) 2064 FIELD(ID_MMFR0, FCSE, 24, 4) 2065 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2066 2067 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2068 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2069 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2070 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2071 FIELD(ID_MMFR1, L1HVD, 16, 4) 2072 FIELD(ID_MMFR1, L1UNI, 20, 4) 2073 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2074 FIELD(ID_MMFR1, BPRED, 28, 4) 2075 2076 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2077 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2078 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2079 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2080 FIELD(ID_MMFR2, UNITLB, 16, 4) 2081 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2082 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2083 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2084 2085 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2086 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2087 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2088 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2089 FIELD(ID_MMFR3, PAN, 16, 4) 2090 FIELD(ID_MMFR3, COHWALK, 20, 4) 2091 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2092 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2093 2094 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2095 FIELD(ID_MMFR4, AC2, 4, 4) 2096 FIELD(ID_MMFR4, XNX, 8, 4) 2097 FIELD(ID_MMFR4, CNP, 12, 4) 2098 FIELD(ID_MMFR4, HPDS, 16, 4) 2099 FIELD(ID_MMFR4, LSM, 20, 4) 2100 FIELD(ID_MMFR4, CCIDX, 24, 4) 2101 FIELD(ID_MMFR4, EVT, 28, 4) 2102 2103 FIELD(ID_MMFR5, ETS, 0, 4) 2104 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2105 2106 FIELD(ID_PFR0, STATE0, 0, 4) 2107 FIELD(ID_PFR0, STATE1, 4, 4) 2108 FIELD(ID_PFR0, STATE2, 8, 4) 2109 FIELD(ID_PFR0, STATE3, 12, 4) 2110 FIELD(ID_PFR0, CSV2, 16, 4) 2111 FIELD(ID_PFR0, AMU, 20, 4) 2112 FIELD(ID_PFR0, DIT, 24, 4) 2113 FIELD(ID_PFR0, RAS, 28, 4) 2114 2115 FIELD(ID_PFR1, PROGMOD, 0, 4) 2116 FIELD(ID_PFR1, SECURITY, 4, 4) 2117 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2118 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2119 FIELD(ID_PFR1, GENTIMER, 16, 4) 2120 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2121 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2122 FIELD(ID_PFR1, GIC, 28, 4) 2123 2124 FIELD(ID_PFR2, CSV3, 0, 4) 2125 FIELD(ID_PFR2, SSBS, 4, 4) 2126 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2127 2128 FIELD(ID_AA64ISAR0, AES, 4, 4) 2129 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2130 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2131 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2132 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2133 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2134 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2135 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2136 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2137 FIELD(ID_AA64ISAR0, DP, 44, 4) 2138 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2139 FIELD(ID_AA64ISAR0, TS, 52, 4) 2140 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2141 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2142 2143 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2144 FIELD(ID_AA64ISAR1, APA, 4, 4) 2145 FIELD(ID_AA64ISAR1, API, 8, 4) 2146 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2147 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2148 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2149 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2150 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2151 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2152 FIELD(ID_AA64ISAR1, SB, 36, 4) 2153 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2154 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2155 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2156 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2157 FIELD(ID_AA64ISAR1, XS, 56, 4) 2158 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2159 2160 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2161 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2162 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2163 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2164 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2165 FIELD(ID_AA64ISAR2, BC, 20, 4) 2166 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2167 2168 FIELD(ID_AA64PFR0, EL0, 0, 4) 2169 FIELD(ID_AA64PFR0, EL1, 4, 4) 2170 FIELD(ID_AA64PFR0, EL2, 8, 4) 2171 FIELD(ID_AA64PFR0, EL3, 12, 4) 2172 FIELD(ID_AA64PFR0, FP, 16, 4) 2173 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2174 FIELD(ID_AA64PFR0, GIC, 24, 4) 2175 FIELD(ID_AA64PFR0, RAS, 28, 4) 2176 FIELD(ID_AA64PFR0, SVE, 32, 4) 2177 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2178 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2179 FIELD(ID_AA64PFR0, AMU, 44, 4) 2180 FIELD(ID_AA64PFR0, DIT, 48, 4) 2181 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2182 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2183 2184 FIELD(ID_AA64PFR1, BT, 0, 4) 2185 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2186 FIELD(ID_AA64PFR1, MTE, 8, 4) 2187 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2188 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2189 FIELD(ID_AA64PFR1, SME, 24, 4) 2190 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2191 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2192 FIELD(ID_AA64PFR1, NMI, 36, 4) 2193 2194 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2195 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2196 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2197 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2198 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2199 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2200 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2201 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2202 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2203 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2204 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2205 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2206 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2207 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2208 2209 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2210 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2211 FIELD(ID_AA64MMFR1, VH, 8, 4) 2212 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2213 FIELD(ID_AA64MMFR1, LO, 16, 4) 2214 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2215 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2216 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2217 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2218 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2219 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2220 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2221 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2222 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2223 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2224 2225 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2226 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2227 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2228 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2229 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2230 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2231 FIELD(ID_AA64MMFR2, NV, 24, 4) 2232 FIELD(ID_AA64MMFR2, ST, 28, 4) 2233 FIELD(ID_AA64MMFR2, AT, 32, 4) 2234 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2235 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2236 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2237 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2238 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2239 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2240 2241 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2242 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2243 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2244 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2245 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2246 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2247 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2248 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2249 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2250 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2251 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2252 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2253 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2254 2255 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2256 FIELD(ID_AA64ZFR0, AES, 4, 4) 2257 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2258 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2259 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2260 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2261 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2262 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2263 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2264 2265 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2266 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2267 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2268 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2269 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2270 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2271 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2272 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2273 2274 FIELD(ID_DFR0, COPDBG, 0, 4) 2275 FIELD(ID_DFR0, COPSDBG, 4, 4) 2276 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2277 FIELD(ID_DFR0, COPTRC, 12, 4) 2278 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2279 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2280 FIELD(ID_DFR0, PERFMON, 24, 4) 2281 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2282 2283 FIELD(ID_DFR1, MTPMU, 0, 4) 2284 FIELD(ID_DFR1, HPMN0, 4, 4) 2285 2286 FIELD(DBGDIDR, SE_IMP, 12, 1) 2287 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2288 FIELD(DBGDIDR, VERSION, 16, 4) 2289 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2290 FIELD(DBGDIDR, BRPS, 24, 4) 2291 FIELD(DBGDIDR, WRPS, 28, 4) 2292 2293 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2294 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2295 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2296 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2297 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2298 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2299 FIELD(DBGDEVID, AUXREGS, 24, 4) 2300 FIELD(DBGDEVID, CIDMASK, 28, 4) 2301 2302 FIELD(MVFR0, SIMDREG, 0, 4) 2303 FIELD(MVFR0, FPSP, 4, 4) 2304 FIELD(MVFR0, FPDP, 8, 4) 2305 FIELD(MVFR0, FPTRAP, 12, 4) 2306 FIELD(MVFR0, FPDIVIDE, 16, 4) 2307 FIELD(MVFR0, FPSQRT, 20, 4) 2308 FIELD(MVFR0, FPSHVEC, 24, 4) 2309 FIELD(MVFR0, FPROUND, 28, 4) 2310 2311 FIELD(MVFR1, FPFTZ, 0, 4) 2312 FIELD(MVFR1, FPDNAN, 4, 4) 2313 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2314 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2315 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2316 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2317 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2318 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2319 FIELD(MVFR1, FPHP, 24, 4) 2320 FIELD(MVFR1, SIMDFMAC, 28, 4) 2321 2322 FIELD(MVFR2, SIMDMISC, 0, 4) 2323 FIELD(MVFR2, FPMISC, 4, 4) 2324 2325 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2326 2327 /* If adding a feature bit which corresponds to a Linux ELF 2328 * HWCAP bit, remember to update the feature-bit-to-hwcap 2329 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2330 */ 2331 enum arm_features { 2332 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2333 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2334 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2335 ARM_FEATURE_V6, 2336 ARM_FEATURE_V6K, 2337 ARM_FEATURE_V7, 2338 ARM_FEATURE_THUMB2, 2339 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2340 ARM_FEATURE_NEON, 2341 ARM_FEATURE_M, /* Microcontroller profile. */ 2342 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2343 ARM_FEATURE_THUMB2EE, 2344 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2345 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2346 ARM_FEATURE_V4T, 2347 ARM_FEATURE_V5, 2348 ARM_FEATURE_STRONGARM, 2349 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2350 ARM_FEATURE_GENERIC_TIMER, 2351 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2352 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2353 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2354 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2355 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2356 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2357 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2358 ARM_FEATURE_V8, 2359 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2360 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2361 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2362 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2363 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2364 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2365 ARM_FEATURE_PMU, /* has PMU support */ 2366 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2367 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2368 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2369 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2370 }; 2371 2372 static inline int arm_feature(CPUARMState *env, int feature) 2373 { 2374 return (env->features & (1ULL << feature)) != 0; 2375 } 2376 2377 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2378 2379 #if !defined(CONFIG_USER_ONLY) 2380 /* Return true if exception levels below EL3 are in secure state, 2381 * or would be following an exception return to that level. 2382 * Unlike arm_is_secure() (which is always a question about the 2383 * _current_ state of the CPU) this doesn't care about the current 2384 * EL or mode. 2385 */ 2386 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2387 { 2388 if (arm_feature(env, ARM_FEATURE_EL3)) { 2389 return !(env->cp15.scr_el3 & SCR_NS); 2390 } else { 2391 /* If EL3 is not supported then the secure state is implementation 2392 * defined, in which case QEMU defaults to non-secure. 2393 */ 2394 return false; 2395 } 2396 } 2397 2398 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2399 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2400 { 2401 if (arm_feature(env, ARM_FEATURE_EL3)) { 2402 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2403 /* CPU currently in AArch64 state and EL3 */ 2404 return true; 2405 } else if (!is_a64(env) && 2406 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2407 /* CPU currently in AArch32 state and monitor mode */ 2408 return true; 2409 } 2410 } 2411 return false; 2412 } 2413 2414 /* Return true if the processor is in secure state */ 2415 static inline bool arm_is_secure(CPUARMState *env) 2416 { 2417 if (arm_is_el3_or_mon(env)) { 2418 return true; 2419 } 2420 return arm_is_secure_below_el3(env); 2421 } 2422 2423 /* 2424 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2425 * This corresponds to the pseudocode EL2Enabled() 2426 */ 2427 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2428 { 2429 return arm_feature(env, ARM_FEATURE_EL2) 2430 && (!secure || (env->cp15.scr_el3 & SCR_EEL2)); 2431 } 2432 2433 static inline bool arm_is_el2_enabled(CPUARMState *env) 2434 { 2435 return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env)); 2436 } 2437 2438 #else 2439 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2440 { 2441 return false; 2442 } 2443 2444 static inline bool arm_is_secure(CPUARMState *env) 2445 { 2446 return false; 2447 } 2448 2449 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2450 { 2451 return false; 2452 } 2453 2454 static inline bool arm_is_el2_enabled(CPUARMState *env) 2455 { 2456 return false; 2457 } 2458 #endif 2459 2460 /** 2461 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2462 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2463 * "for all purposes other than a direct read or write access of HCR_EL2." 2464 * Not included here is HCR_RW. 2465 */ 2466 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); 2467 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2468 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2469 2470 /* Return true if the specified exception level is running in AArch64 state. */ 2471 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2472 { 2473 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2474 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2475 */ 2476 assert(el >= 1 && el <= 3); 2477 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2478 2479 /* The highest exception level is always at the maximum supported 2480 * register width, and then lower levels have a register width controlled 2481 * by bits in the SCR or HCR registers. 2482 */ 2483 if (el == 3) { 2484 return aa64; 2485 } 2486 2487 if (arm_feature(env, ARM_FEATURE_EL3) && 2488 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2489 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2490 } 2491 2492 if (el == 2) { 2493 return aa64; 2494 } 2495 2496 if (arm_is_el2_enabled(env)) { 2497 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2498 } 2499 2500 return aa64; 2501 } 2502 2503 /* Function for determing whether guest cp register reads and writes should 2504 * access the secure or non-secure bank of a cp register. When EL3 is 2505 * operating in AArch32 state, the NS-bit determines whether the secure 2506 * instance of a cp register should be used. When EL3 is AArch64 (or if 2507 * it doesn't exist at all) then there is no register banking, and all 2508 * accesses are to the non-secure version. 2509 */ 2510 static inline bool access_secure_reg(CPUARMState *env) 2511 { 2512 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2513 !arm_el_is_aa64(env, 3) && 2514 !(env->cp15.scr_el3 & SCR_NS)); 2515 2516 return ret; 2517 } 2518 2519 /* Macros for accessing a specified CP register bank */ 2520 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2521 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2522 2523 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2524 do { \ 2525 if (_secure) { \ 2526 (_env)->cp15._regname##_s = (_val); \ 2527 } else { \ 2528 (_env)->cp15._regname##_ns = (_val); \ 2529 } \ 2530 } while (0) 2531 2532 /* Macros for automatically accessing a specific CP register bank depending on 2533 * the current secure state of the system. These macros are not intended for 2534 * supporting instruction translation reads/writes as these are dependent 2535 * solely on the SCR.NS bit and not the mode. 2536 */ 2537 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2538 A32_BANKED_REG_GET((_env), _regname, \ 2539 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2540 2541 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2542 A32_BANKED_REG_SET((_env), _regname, \ 2543 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2544 (_val)) 2545 2546 void arm_cpu_list(void); 2547 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2548 uint32_t cur_el, bool secure); 2549 2550 /* Interface between CPU and Interrupt controller. */ 2551 #ifndef CONFIG_USER_ONLY 2552 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2553 #else 2554 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2555 { 2556 return true; 2557 } 2558 #endif 2559 /** 2560 * armv7m_nvic_set_pending: mark the specified exception as pending 2561 * @opaque: the NVIC 2562 * @irq: the exception number to mark pending 2563 * @secure: false for non-banked exceptions or for the nonsecure 2564 * version of a banked exception, true for the secure version of a banked 2565 * exception. 2566 * 2567 * Marks the specified exception as pending. Note that we will assert() 2568 * if @secure is true and @irq does not specify one of the fixed set 2569 * of architecturally banked exceptions. 2570 */ 2571 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2572 /** 2573 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2574 * @opaque: the NVIC 2575 * @irq: the exception number to mark pending 2576 * @secure: false for non-banked exceptions or for the nonsecure 2577 * version of a banked exception, true for the secure version of a banked 2578 * exception. 2579 * 2580 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2581 * exceptions (exceptions generated in the course of trying to take 2582 * a different exception). 2583 */ 2584 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2585 /** 2586 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2587 * @opaque: the NVIC 2588 * @irq: the exception number to mark pending 2589 * @secure: false for non-banked exceptions or for the nonsecure 2590 * version of a banked exception, true for the secure version of a banked 2591 * exception. 2592 * 2593 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2594 * generated in the course of lazy stacking of FP registers. 2595 */ 2596 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2597 /** 2598 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2599 * exception, and whether it targets Secure state 2600 * @opaque: the NVIC 2601 * @pirq: set to pending exception number 2602 * @ptargets_secure: set to whether pending exception targets Secure 2603 * 2604 * This function writes the number of the highest priority pending 2605 * exception (the one which would be made active by 2606 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2607 * to true if the current highest priority pending exception should 2608 * be taken to Secure state, false for NS. 2609 */ 2610 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2611 bool *ptargets_secure); 2612 /** 2613 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2614 * @opaque: the NVIC 2615 * 2616 * Move the current highest priority pending exception from the pending 2617 * state to the active state, and update v7m.exception to indicate that 2618 * it is the exception currently being handled. 2619 */ 2620 void armv7m_nvic_acknowledge_irq(void *opaque); 2621 /** 2622 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2623 * @opaque: the NVIC 2624 * @irq: the exception number to complete 2625 * @secure: true if this exception was secure 2626 * 2627 * Returns: -1 if the irq was not active 2628 * 1 if completing this irq brought us back to base (no active irqs) 2629 * 0 if there is still an irq active after this one was completed 2630 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2631 */ 2632 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2633 /** 2634 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2635 * @opaque: the NVIC 2636 * @irq: the exception number to mark pending 2637 * @secure: false for non-banked exceptions or for the nonsecure 2638 * version of a banked exception, true for the secure version of a banked 2639 * exception. 2640 * 2641 * Return whether an exception is "ready", i.e. whether the exception is 2642 * enabled and is configured at a priority which would allow it to 2643 * interrupt the current execution priority. This controls whether the 2644 * RDY bit for it in the FPCCR is set. 2645 */ 2646 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2647 /** 2648 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2649 * @opaque: the NVIC 2650 * 2651 * Returns: the raw execution priority as defined by the v8M architecture. 2652 * This is the execution priority minus the effects of AIRCR.PRIS, 2653 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2654 * (v8M ARM ARM I_PKLD.) 2655 */ 2656 int armv7m_nvic_raw_execution_priority(void *opaque); 2657 /** 2658 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2659 * priority is negative for the specified security state. 2660 * @opaque: the NVIC 2661 * @secure: the security state to test 2662 * This corresponds to the pseudocode IsReqExecPriNeg(). 2663 */ 2664 #ifndef CONFIG_USER_ONLY 2665 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2666 #else 2667 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2668 { 2669 return false; 2670 } 2671 #endif 2672 2673 /* Interface for defining coprocessor registers. 2674 * Registers are defined in tables of arm_cp_reginfo structs 2675 * which are passed to define_arm_cp_regs(). 2676 */ 2677 2678 /* When looking up a coprocessor register we look for it 2679 * via an integer which encodes all of: 2680 * coprocessor number 2681 * Crn, Crm, opc1, opc2 fields 2682 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2683 * or via MRRC/MCRR?) 2684 * non-secure/secure bank (AArch32 only) 2685 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2686 * (In this case crn and opc2 should be zero.) 2687 * For AArch64, there is no 32/64 bit size distinction; 2688 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2689 * and 4 bit CRn and CRm. The encoding patterns are chosen 2690 * to be easy to convert to and from the KVM encodings, and also 2691 * so that the hashtable can contain both AArch32 and AArch64 2692 * registers (to allow for interprocessing where we might run 2693 * 32 bit code on a 64 bit core). 2694 */ 2695 /* This bit is private to our hashtable cpreg; in KVM register 2696 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2697 * in the upper bits of the 64 bit ID. 2698 */ 2699 #define CP_REG_AA64_SHIFT 28 2700 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2701 2702 /* To enable banking of coprocessor registers depending on ns-bit we 2703 * add a bit to distinguish between secure and non-secure cpregs in the 2704 * hashtable. 2705 */ 2706 #define CP_REG_NS_SHIFT 29 2707 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2708 2709 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2710 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2711 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2712 2713 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2714 (CP_REG_AA64_MASK | \ 2715 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2716 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2717 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2718 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2719 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2720 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2721 2722 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2723 * version used as a key for the coprocessor register hashtable 2724 */ 2725 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2726 { 2727 uint32_t cpregid = kvmid; 2728 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2729 cpregid |= CP_REG_AA64_MASK; 2730 } else { 2731 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2732 cpregid |= (1 << 15); 2733 } 2734 2735 /* KVM is always non-secure so add the NS flag on AArch32 register 2736 * entries. 2737 */ 2738 cpregid |= 1 << CP_REG_NS_SHIFT; 2739 } 2740 return cpregid; 2741 } 2742 2743 /* Convert a truncated 32 bit hashtable key into the full 2744 * 64 bit KVM register ID. 2745 */ 2746 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2747 { 2748 uint64_t kvmid; 2749 2750 if (cpregid & CP_REG_AA64_MASK) { 2751 kvmid = cpregid & ~CP_REG_AA64_MASK; 2752 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2753 } else { 2754 kvmid = cpregid & ~(1 << 15); 2755 if (cpregid & (1 << 15)) { 2756 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2757 } else { 2758 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2759 } 2760 } 2761 return kvmid; 2762 } 2763 2764 /* Return the highest implemented Exception Level */ 2765 static inline int arm_highest_el(CPUARMState *env) 2766 { 2767 if (arm_feature(env, ARM_FEATURE_EL3)) { 2768 return 3; 2769 } 2770 if (arm_feature(env, ARM_FEATURE_EL2)) { 2771 return 2; 2772 } 2773 return 1; 2774 } 2775 2776 /* Return true if a v7M CPU is in Handler mode */ 2777 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2778 { 2779 return env->v7m.exception != 0; 2780 } 2781 2782 /* Return the current Exception Level (as per ARMv8; note that this differs 2783 * from the ARMv7 Privilege Level). 2784 */ 2785 static inline int arm_current_el(CPUARMState *env) 2786 { 2787 if (arm_feature(env, ARM_FEATURE_M)) { 2788 return arm_v7m_is_handler_mode(env) || 2789 !(env->v7m.control[env->v7m.secure] & 1); 2790 } 2791 2792 if (is_a64(env)) { 2793 return extract32(env->pstate, 2, 2); 2794 } 2795 2796 switch (env->uncached_cpsr & 0x1f) { 2797 case ARM_CPU_MODE_USR: 2798 return 0; 2799 case ARM_CPU_MODE_HYP: 2800 return 2; 2801 case ARM_CPU_MODE_MON: 2802 return 3; 2803 default: 2804 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2805 /* If EL3 is 32-bit then all secure privileged modes run in 2806 * EL3 2807 */ 2808 return 3; 2809 } 2810 2811 return 1; 2812 } 2813 } 2814 2815 /** 2816 * write_list_to_cpustate 2817 * @cpu: ARMCPU 2818 * 2819 * For each register listed in the ARMCPU cpreg_indexes list, write 2820 * its value from the cpreg_values list into the ARMCPUState structure. 2821 * This updates TCG's working data structures from KVM data or 2822 * from incoming migration state. 2823 * 2824 * Returns: true if all register values were updated correctly, 2825 * false if some register was unknown or could not be written. 2826 * Note that we do not stop early on failure -- we will attempt 2827 * writing all registers in the list. 2828 */ 2829 bool write_list_to_cpustate(ARMCPU *cpu); 2830 2831 /** 2832 * write_cpustate_to_list: 2833 * @cpu: ARMCPU 2834 * @kvm_sync: true if this is for syncing back to KVM 2835 * 2836 * For each register listed in the ARMCPU cpreg_indexes list, write 2837 * its value from the ARMCPUState structure into the cpreg_values list. 2838 * This is used to copy info from TCG's working data structures into 2839 * KVM or for outbound migration. 2840 * 2841 * @kvm_sync is true if we are doing this in order to sync the 2842 * register state back to KVM. In this case we will only update 2843 * values in the list if the previous list->cpustate sync actually 2844 * successfully wrote the CPU state. Otherwise we will keep the value 2845 * that is in the list. 2846 * 2847 * Returns: true if all register values were read correctly, 2848 * false if some register was unknown or could not be read. 2849 * Note that we do not stop early on failure -- we will attempt 2850 * reading all registers in the list. 2851 */ 2852 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2853 2854 #define ARM_CPUID_TI915T 0x54029152 2855 #define ARM_CPUID_TI925T 0x54029252 2856 2857 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2858 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2859 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2860 2861 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2862 2863 #define cpu_list arm_cpu_list 2864 2865 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2866 * 2867 * If EL3 is 64-bit: 2868 * + NonSecure EL1 & 0 stage 1 2869 * + NonSecure EL1 & 0 stage 2 2870 * + NonSecure EL2 2871 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2872 * + Secure EL1 & 0 2873 * + Secure EL3 2874 * If EL3 is 32-bit: 2875 * + NonSecure PL1 & 0 stage 1 2876 * + NonSecure PL1 & 0 stage 2 2877 * + NonSecure PL2 2878 * + Secure PL0 2879 * + Secure PL1 2880 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2881 * 2882 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2883 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2884 * because they may differ in access permissions even if the VA->PA map is 2885 * the same 2886 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2887 * translation, which means that we have one mmu_idx that deals with two 2888 * concatenated translation regimes [this sort of combined s1+2 TLB is 2889 * architecturally permitted] 2890 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2891 * handling via the TLB. The only way to do a stage 1 translation without 2892 * the immediate stage 2 translation is via the ATS or AT system insns, 2893 * which can be slow-pathed and always do a page table walk. 2894 * The only use of stage 2 translations is either as part of an s1+2 2895 * lookup or when loading the descriptors during a stage 1 page table walk, 2896 * and in both those cases we don't use the TLB. 2897 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2898 * translation regimes, because they map reasonably well to each other 2899 * and they can't both be active at the same time. 2900 * 5. we want to be able to use the TLB for accesses done as part of a 2901 * stage1 page table walk, rather than having to walk the stage2 page 2902 * table over and over. 2903 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2904 * Never (PAN) bit within PSTATE. 2905 * 7. we fold together the secure and non-secure regimes for A-profile, 2906 * because there are no banked system registers for aarch64, so the 2907 * process of switching between secure and non-secure is 2908 * already heavyweight. 2909 * 2910 * This gives us the following list of cases: 2911 * 2912 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2913 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2914 * EL1 EL1&0 stage 1+2 +PAN 2915 * EL0 EL2&0 2916 * EL2 EL2&0 2917 * EL2 EL2&0 +PAN 2918 * EL2 (aka NS PL2) 2919 * EL3 (aka S PL1) 2920 * Physical (NS & S) 2921 * Stage2 (NS & S) 2922 * 2923 * for a total of 12 different mmu_idx. 2924 * 2925 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2926 * as A profile. They only need to distinguish EL0 and EL1 (and 2927 * EL2 if we ever model a Cortex-R52). 2928 * 2929 * M profile CPUs are rather different as they do not have a true MMU. 2930 * They have the following different MMU indexes: 2931 * User 2932 * Privileged 2933 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2934 * Privileged, execution priority negative (ditto) 2935 * If the CPU supports the v8M Security Extension then there are also: 2936 * Secure User 2937 * Secure Privileged 2938 * Secure User, execution priority negative 2939 * Secure Privileged, execution priority negative 2940 * 2941 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2942 * are not quite the same -- different CPU types (most notably M profile 2943 * vs A/R profile) would like to use MMU indexes with different semantics, 2944 * but since we don't ever need to use all of those in a single CPU we 2945 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2946 * modes + total number of M profile MMU modes". The lower bits of 2947 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2948 * the same for any particular CPU. 2949 * Variables of type ARMMUIdx are always full values, and the core 2950 * index values are in variables of type 'int'. 2951 * 2952 * Our enumeration includes at the end some entries which are not "true" 2953 * mmu_idx values in that they don't have corresponding TLBs and are only 2954 * valid for doing slow path page table walks. 2955 * 2956 * The constant names here are patterned after the general style of the names 2957 * of the AT/ATS operations. 2958 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2959 * For M profile we arrange them to have a bit for priv, a bit for negpri 2960 * and a bit for secure. 2961 */ 2962 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2963 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2964 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2965 2966 /* Meanings of the bits for M profile mmu idx values */ 2967 #define ARM_MMU_IDX_M_PRIV 0x1 2968 #define ARM_MMU_IDX_M_NEGPRI 0x2 2969 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2970 2971 #define ARM_MMU_IDX_TYPE_MASK \ 2972 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2973 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2974 2975 typedef enum ARMMMUIdx { 2976 /* 2977 * A-profile. 2978 */ 2979 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2980 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2981 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2982 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2983 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2984 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2985 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2986 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2987 2988 /* TLBs with 1-1 mapping to the physical address spaces. */ 2989 ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A, 2990 ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A, 2991 2992 /* 2993 * Used for second stage of an S12 page table walk, or for descriptor 2994 * loads during first stage of an S1 page table walk. Note that both 2995 * are in use simultaneously for SecureEL2: the security state for 2996 * the S2 ptw is selected by the NS bit from the S1 ptw. 2997 */ 2998 ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A, 2999 ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A, 3000 3001 /* 3002 * These are not allocated TLBs and are used only for AT system 3003 * instructions or for the first stage of an S12 page table walk. 3004 */ 3005 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 3006 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 3007 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 3008 3009 /* 3010 * M-profile. 3011 */ 3012 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 3013 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 3014 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 3015 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 3016 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 3017 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 3018 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 3019 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 3020 } ARMMMUIdx; 3021 3022 /* 3023 * Bit macros for the core-mmu-index values for each index, 3024 * for use when calling tlb_flush_by_mmuidx() and friends. 3025 */ 3026 #define TO_CORE_BIT(NAME) \ 3027 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 3028 3029 typedef enum ARMMMUIdxBit { 3030 TO_CORE_BIT(E10_0), 3031 TO_CORE_BIT(E20_0), 3032 TO_CORE_BIT(E10_1), 3033 TO_CORE_BIT(E10_1_PAN), 3034 TO_CORE_BIT(E2), 3035 TO_CORE_BIT(E20_2), 3036 TO_CORE_BIT(E20_2_PAN), 3037 TO_CORE_BIT(E3), 3038 TO_CORE_BIT(Stage2), 3039 TO_CORE_BIT(Stage2_S), 3040 3041 TO_CORE_BIT(MUser), 3042 TO_CORE_BIT(MPriv), 3043 TO_CORE_BIT(MUserNegPri), 3044 TO_CORE_BIT(MPrivNegPri), 3045 TO_CORE_BIT(MSUser), 3046 TO_CORE_BIT(MSPriv), 3047 TO_CORE_BIT(MSUserNegPri), 3048 TO_CORE_BIT(MSPrivNegPri), 3049 } ARMMMUIdxBit; 3050 3051 #undef TO_CORE_BIT 3052 3053 #define MMU_USER_IDX 0 3054 3055 /* Indexes used when registering address spaces with cpu_address_space_init */ 3056 typedef enum ARMASIdx { 3057 ARMASIdx_NS = 0, 3058 ARMASIdx_S = 1, 3059 ARMASIdx_TagNS = 2, 3060 ARMASIdx_TagS = 3, 3061 } ARMASIdx; 3062 3063 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3064 { 3065 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3066 * CSSELR is RAZ/WI. 3067 */ 3068 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3069 } 3070 3071 static inline bool arm_sctlr_b(CPUARMState *env) 3072 { 3073 return 3074 /* We need not implement SCTLR.ITD in user-mode emulation, so 3075 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3076 * This lets people run BE32 binaries with "-cpu any". 3077 */ 3078 #ifndef CONFIG_USER_ONLY 3079 !arm_feature(env, ARM_FEATURE_V7) && 3080 #endif 3081 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3082 } 3083 3084 uint64_t arm_sctlr(CPUARMState *env, int el); 3085 3086 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3087 bool sctlr_b) 3088 { 3089 #ifdef CONFIG_USER_ONLY 3090 /* 3091 * In system mode, BE32 is modelled in line with the 3092 * architecture (as word-invariant big-endianness), where loads 3093 * and stores are done little endian but from addresses which 3094 * are adjusted by XORing with the appropriate constant. So the 3095 * endianness to use for the raw data access is not affected by 3096 * SCTLR.B. 3097 * In user mode, however, we model BE32 as byte-invariant 3098 * big-endianness (because user-only code cannot tell the 3099 * difference), and so we need to use a data access endianness 3100 * that depends on SCTLR.B. 3101 */ 3102 if (sctlr_b) { 3103 return true; 3104 } 3105 #endif 3106 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3107 return env->uncached_cpsr & CPSR_E; 3108 } 3109 3110 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3111 { 3112 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3113 } 3114 3115 /* Return true if the processor is in big-endian mode. */ 3116 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3117 { 3118 if (!is_a64(env)) { 3119 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3120 } else { 3121 int cur_el = arm_current_el(env); 3122 uint64_t sctlr = arm_sctlr(env, cur_el); 3123 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3124 } 3125 } 3126 3127 #include "exec/cpu-all.h" 3128 3129 /* 3130 * We have more than 32-bits worth of state per TB, so we split the data 3131 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3132 * We collect these two parts in CPUARMTBFlags where they are named 3133 * flags and flags2 respectively. 3134 * 3135 * The flags that are shared between all execution modes, TBFLAG_ANY, 3136 * are stored in flags. The flags that are specific to a given mode 3137 * are stores in flags2. Since cs_base is sized on the configured 3138 * address size, flags2 always has 64-bits for A64, and a minimum of 3139 * 32-bits for A32 and M32. 3140 * 3141 * The bits for 32-bit A-profile and M-profile partially overlap: 3142 * 3143 * 31 23 11 10 0 3144 * +-------------+----------+----------------+ 3145 * | | | TBFLAG_A32 | 3146 * | TBFLAG_AM32 | +-----+----------+ 3147 * | | |TBFLAG_M32| 3148 * +-------------+----------------+----------+ 3149 * 31 23 6 5 0 3150 * 3151 * Unless otherwise noted, these bits are cached in env->hflags. 3152 */ 3153 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3154 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3155 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3156 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3157 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3158 /* Target EL if we take a floating-point-disabled exception */ 3159 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3160 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3161 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3162 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3163 3164 /* 3165 * Bit usage when in AArch32 state, both A- and M-profile. 3166 */ 3167 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3168 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3169 3170 /* 3171 * Bit usage when in AArch32 state, for A-profile only. 3172 */ 3173 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3174 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3175 /* 3176 * We store the bottom two bits of the CPAR as TB flags and handle 3177 * checks on the other bits at runtime. This shares the same bits as 3178 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3179 * Not cached, because VECLEN+VECSTRIDE are not cached. 3180 */ 3181 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3182 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3183 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3184 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3185 /* 3186 * Indicates whether cp register reads and writes by guest code should access 3187 * the secure or nonsecure bank of banked registers; note that this is not 3188 * the same thing as the current security state of the processor! 3189 */ 3190 FIELD(TBFLAG_A32, NS, 10, 1) 3191 /* 3192 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3193 * This requires an SME trap from AArch32 mode when using NEON. 3194 */ 3195 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3196 3197 /* 3198 * Bit usage when in AArch32 state, for M-profile only. 3199 */ 3200 /* Handler (ie not Thread) mode */ 3201 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3202 /* Whether we should generate stack-limit checks */ 3203 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3204 /* Set if FPCCR.LSPACT is set */ 3205 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3206 /* Set if we must create a new FP context */ 3207 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3208 /* Set if FPCCR.S does not match current security state */ 3209 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3210 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3211 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3212 /* Set if in secure mode */ 3213 FIELD(TBFLAG_M32, SECURE, 6, 1) 3214 3215 /* 3216 * Bit usage when in AArch64 state 3217 */ 3218 FIELD(TBFLAG_A64, TBII, 0, 2) 3219 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3220 /* The current vector length, either NVL or SVL. */ 3221 FIELD(TBFLAG_A64, VL, 4, 4) 3222 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3223 FIELD(TBFLAG_A64, BT, 9, 1) 3224 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3225 FIELD(TBFLAG_A64, TBID, 12, 2) 3226 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3227 FIELD(TBFLAG_A64, ATA, 15, 1) 3228 FIELD(TBFLAG_A64, TCMA, 16, 2) 3229 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3230 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3231 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3232 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3233 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3234 FIELD(TBFLAG_A64, SVL, 24, 4) 3235 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3236 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3237 3238 /* 3239 * Helpers for using the above. 3240 */ 3241 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3242 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3243 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3244 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3245 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3246 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3247 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3248 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3249 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3250 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3251 3252 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3253 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3254 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3255 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3256 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3257 3258 /** 3259 * cpu_mmu_index: 3260 * @env: The cpu environment 3261 * @ifetch: True for code access, false for data access. 3262 * 3263 * Return the core mmu index for the current translation regime. 3264 * This function is used by generic TCG code paths. 3265 */ 3266 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3267 { 3268 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3269 } 3270 3271 /** 3272 * sve_vq 3273 * @env: the cpu context 3274 * 3275 * Return the VL cached within env->hflags, in units of quadwords. 3276 */ 3277 static inline int sve_vq(CPUARMState *env) 3278 { 3279 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3280 } 3281 3282 /** 3283 * sme_vq 3284 * @env: the cpu context 3285 * 3286 * Return the SVL cached within env->hflags, in units of quadwords. 3287 */ 3288 static inline int sme_vq(CPUARMState *env) 3289 { 3290 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3291 } 3292 3293 static inline bool bswap_code(bool sctlr_b) 3294 { 3295 #ifdef CONFIG_USER_ONLY 3296 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3297 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3298 * would also end up as a mixed-endian mode with BE code, LE data. 3299 */ 3300 return 3301 #if TARGET_BIG_ENDIAN 3302 1 ^ 3303 #endif 3304 sctlr_b; 3305 #else 3306 /* All code access in ARM is little endian, and there are no loaders 3307 * doing swaps that need to be reversed 3308 */ 3309 return 0; 3310 #endif 3311 } 3312 3313 #ifdef CONFIG_USER_ONLY 3314 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3315 { 3316 return 3317 #if TARGET_BIG_ENDIAN 3318 1 ^ 3319 #endif 3320 arm_cpu_data_is_big_endian(env); 3321 } 3322 #endif 3323 3324 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3325 target_ulong *cs_base, uint32_t *flags); 3326 3327 enum { 3328 QEMU_PSCI_CONDUIT_DISABLED = 0, 3329 QEMU_PSCI_CONDUIT_SMC = 1, 3330 QEMU_PSCI_CONDUIT_HVC = 2, 3331 }; 3332 3333 #ifndef CONFIG_USER_ONLY 3334 /* Return the address space index to use for a memory access */ 3335 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3336 { 3337 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3338 } 3339 3340 /* Return the AddressSpace to use for a memory access 3341 * (which depends on whether the access is S or NS, and whether 3342 * the board gave us a separate AddressSpace for S accesses). 3343 */ 3344 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3345 { 3346 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3347 } 3348 #endif 3349 3350 /** 3351 * arm_register_pre_el_change_hook: 3352 * Register a hook function which will be called immediately before this 3353 * CPU changes exception level or mode. The hook function will be 3354 * passed a pointer to the ARMCPU and the opaque data pointer passed 3355 * to this function when the hook was registered. 3356 * 3357 * Note that if a pre-change hook is called, any registered post-change hooks 3358 * are guaranteed to subsequently be called. 3359 */ 3360 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3361 void *opaque); 3362 /** 3363 * arm_register_el_change_hook: 3364 * Register a hook function which will be called immediately after this 3365 * CPU changes exception level or mode. The hook function will be 3366 * passed a pointer to the ARMCPU and the opaque data pointer passed 3367 * to this function when the hook was registered. 3368 * 3369 * Note that any registered hooks registered here are guaranteed to be called 3370 * if pre-change hooks have been. 3371 */ 3372 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3373 *opaque); 3374 3375 /** 3376 * arm_rebuild_hflags: 3377 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3378 */ 3379 void arm_rebuild_hflags(CPUARMState *env); 3380 3381 /** 3382 * aa32_vfp_dreg: 3383 * Return a pointer to the Dn register within env in 32-bit mode. 3384 */ 3385 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3386 { 3387 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3388 } 3389 3390 /** 3391 * aa32_vfp_qreg: 3392 * Return a pointer to the Qn register within env in 32-bit mode. 3393 */ 3394 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3395 { 3396 return &env->vfp.zregs[regno].d[0]; 3397 } 3398 3399 /** 3400 * aa64_vfp_qreg: 3401 * Return a pointer to the Qn register within env in 64-bit mode. 3402 */ 3403 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3404 { 3405 return &env->vfp.zregs[regno].d[0]; 3406 } 3407 3408 /* Shared between translate-sve.c and sve_helper.c. */ 3409 extern const uint64_t pred_esz_masks[5]; 3410 3411 /* 3412 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3413 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3414 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3415 */ 3416 #define PAGE_BTI PAGE_TARGET_1 3417 #define PAGE_MTE PAGE_TARGET_2 3418 #define PAGE_TARGET_STICKY PAGE_MTE 3419 3420 /* We associate one allocation tag per 16 bytes, the minimum. */ 3421 #define LOG2_TAG_GRANULE 4 3422 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3423 3424 #ifdef CONFIG_USER_ONLY 3425 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3426 #endif 3427 3428 #ifdef TARGET_TAGGED_ADDRESSES 3429 /** 3430 * cpu_untagged_addr: 3431 * @cs: CPU context 3432 * @x: tagged address 3433 * 3434 * Remove any address tag from @x. This is explicitly related to the 3435 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3436 * 3437 * There should be a better place to put this, but we need this in 3438 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3439 */ 3440 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3441 { 3442 ARMCPU *cpu = ARM_CPU(cs); 3443 if (cpu->env.tagged_addr_enable) { 3444 /* 3445 * TBI is enabled for userspace but not kernelspace addresses. 3446 * Only clear the tag if bit 55 is clear. 3447 */ 3448 x &= sextract64(x, 0, 56); 3449 } 3450 return x; 3451 } 3452 #endif 3453 3454 /* 3455 * Naming convention for isar_feature functions: 3456 * Functions which test 32-bit ID registers should have _aa32_ in 3457 * their name. Functions which test 64-bit ID registers should have 3458 * _aa64_ in their name. These must only be used in code where we 3459 * know for certain that the CPU has AArch32 or AArch64 respectively 3460 * or where the correct answer for a CPU which doesn't implement that 3461 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3462 * system registers that are specific to that CPU state, for "should 3463 * we let this system register bit be set" tests where the 32-bit 3464 * flavour of the register doesn't have the bit, and so on). 3465 * Functions which simply ask "does this feature exist at all" have 3466 * _any_ in their name, and always return the logical OR of the _aa64_ 3467 * and the _aa32_ function. 3468 */ 3469 3470 /* 3471 * 32-bit feature tests via id registers. 3472 */ 3473 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3474 { 3475 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3476 } 3477 3478 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3479 { 3480 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3481 } 3482 3483 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3484 { 3485 /* (M-profile) low-overhead loops and branch future */ 3486 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3487 } 3488 3489 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3490 { 3491 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3492 } 3493 3494 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3495 { 3496 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3497 } 3498 3499 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3500 { 3501 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3502 } 3503 3504 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3505 { 3506 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3507 } 3508 3509 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3510 { 3511 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3512 } 3513 3514 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3515 { 3516 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3517 } 3518 3519 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3520 { 3521 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3522 } 3523 3524 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3525 { 3526 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3527 } 3528 3529 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3530 { 3531 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3532 } 3533 3534 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3535 { 3536 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3537 } 3538 3539 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3540 { 3541 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3542 } 3543 3544 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3545 { 3546 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3547 } 3548 3549 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3550 { 3551 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3552 } 3553 3554 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3555 { 3556 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3557 } 3558 3559 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3560 { 3561 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3562 } 3563 3564 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3565 { 3566 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3567 } 3568 3569 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3570 { 3571 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3572 } 3573 3574 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3575 { 3576 /* 3577 * Return true if M-profile state handling insns 3578 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3579 */ 3580 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3581 } 3582 3583 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3584 { 3585 /* Sadly this is encoded differently for A-profile and M-profile */ 3586 if (isar_feature_aa32_mprofile(id)) { 3587 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3588 } else { 3589 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3590 } 3591 } 3592 3593 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3594 { 3595 /* 3596 * Return true if MVE is supported (either integer or floating point). 3597 * We must check for M-profile as the MVFR1 field means something 3598 * else for A-profile. 3599 */ 3600 return isar_feature_aa32_mprofile(id) && 3601 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3602 } 3603 3604 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3605 { 3606 /* 3607 * Return true if MVE is supported (either integer or floating point). 3608 * We must check for M-profile as the MVFR1 field means something 3609 * else for A-profile. 3610 */ 3611 return isar_feature_aa32_mprofile(id) && 3612 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3613 } 3614 3615 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3616 { 3617 /* 3618 * Return true if either VFP or SIMD is implemented. 3619 * In this case, a minimum of VFP w/ D0-D15. 3620 */ 3621 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3622 } 3623 3624 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3625 { 3626 /* Return true if D16-D31 are implemented */ 3627 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3628 } 3629 3630 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3631 { 3632 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3633 } 3634 3635 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3636 { 3637 /* Return true if CPU supports single precision floating point, VFPv2 */ 3638 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3639 } 3640 3641 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3642 { 3643 /* Return true if CPU supports single precision floating point, VFPv3 */ 3644 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3645 } 3646 3647 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3648 { 3649 /* Return true if CPU supports double precision floating point, VFPv2 */ 3650 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3651 } 3652 3653 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3654 { 3655 /* Return true if CPU supports double precision floating point, VFPv3 */ 3656 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3657 } 3658 3659 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3660 { 3661 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3662 } 3663 3664 /* 3665 * We always set the FP and SIMD FP16 fields to indicate identical 3666 * levels of support (assuming SIMD is implemented at all), so 3667 * we only need one set of accessors. 3668 */ 3669 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3670 { 3671 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3672 } 3673 3674 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3675 { 3676 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3677 } 3678 3679 /* 3680 * Note that this ID register field covers both VFP and Neon FMAC, 3681 * so should usually be tested in combination with some other 3682 * check that confirms the presence of whichever of VFP or Neon is 3683 * relevant, to avoid accidentally enabling a Neon feature on 3684 * a VFP-no-Neon core or vice-versa. 3685 */ 3686 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3687 { 3688 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3689 } 3690 3691 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3692 { 3693 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3694 } 3695 3696 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3697 { 3698 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3699 } 3700 3701 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3702 { 3703 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3704 } 3705 3706 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3707 { 3708 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3709 } 3710 3711 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3712 { 3713 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3714 } 3715 3716 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3717 { 3718 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3719 } 3720 3721 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3722 { 3723 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3724 } 3725 3726 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) 3727 { 3728 /* 0xf means "non-standard IMPDEF PMU" */ 3729 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3730 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3731 } 3732 3733 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) 3734 { 3735 /* 0xf means "non-standard IMPDEF PMU" */ 3736 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3737 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3738 } 3739 3740 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) 3741 { 3742 /* 0xf means "non-standard IMPDEF PMU" */ 3743 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 && 3744 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3745 } 3746 3747 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3748 { 3749 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3750 } 3751 3752 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3753 { 3754 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3755 } 3756 3757 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3758 { 3759 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3760 } 3761 3762 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3763 { 3764 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3765 } 3766 3767 static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) 3768 { 3769 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1; 3770 } 3771 3772 static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) 3773 { 3774 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2; 3775 } 3776 3777 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3778 { 3779 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3780 } 3781 3782 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3783 { 3784 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3785 } 3786 3787 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) 3788 { 3789 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5; 3790 } 3791 3792 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3793 { 3794 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3795 } 3796 3797 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) 3798 { 3799 return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0; 3800 } 3801 3802 /* 3803 * 64-bit feature tests via id registers. 3804 */ 3805 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3806 { 3807 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3808 } 3809 3810 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3811 { 3812 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3813 } 3814 3815 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3816 { 3817 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3818 } 3819 3820 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3821 { 3822 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3823 } 3824 3825 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3826 { 3827 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3828 } 3829 3830 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3831 { 3832 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3833 } 3834 3835 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3836 { 3837 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3838 } 3839 3840 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3841 { 3842 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3843 } 3844 3845 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3846 { 3847 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3848 } 3849 3850 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3851 { 3852 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3853 } 3854 3855 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3856 { 3857 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3858 } 3859 3860 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3861 { 3862 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3863 } 3864 3865 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3866 { 3867 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3868 } 3869 3870 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3871 { 3872 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3873 } 3874 3875 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3876 { 3877 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3878 } 3879 3880 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3881 { 3882 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3883 } 3884 3885 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3886 { 3887 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3888 } 3889 3890 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3891 { 3892 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3893 } 3894 3895 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3896 { 3897 /* 3898 * Return true if any form of pauth is enabled, as this 3899 * predicate controls migration of the 128-bit keys. 3900 */ 3901 return (id->id_aa64isar1 & 3902 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3903 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3904 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3905 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3906 } 3907 3908 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3909 { 3910 /* 3911 * Return true if pauth is enabled with the architected QARMA algorithm. 3912 * QEMU will always set APA+GPA to the same value. 3913 */ 3914 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3915 } 3916 3917 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3918 { 3919 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3920 } 3921 3922 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3923 { 3924 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3925 } 3926 3927 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3928 { 3929 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3930 } 3931 3932 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3933 { 3934 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3935 } 3936 3937 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3938 { 3939 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3940 } 3941 3942 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3943 { 3944 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3945 } 3946 3947 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3948 { 3949 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3950 } 3951 3952 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3953 { 3954 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3955 } 3956 3957 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3958 { 3959 /* We always set the AdvSIMD and FP fields identically. */ 3960 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3961 } 3962 3963 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3964 { 3965 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3966 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3967 } 3968 3969 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3970 { 3971 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3972 } 3973 3974 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3975 { 3976 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3977 } 3978 3979 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) 3980 { 3981 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; 3982 } 3983 3984 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3985 { 3986 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 3987 } 3988 3989 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) 3990 { 3991 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2; 3992 } 3993 3994 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3995 { 3996 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3997 } 3998 3999 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 4000 { 4001 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 4002 } 4003 4004 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 4005 { 4006 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 4007 } 4008 4009 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 4010 { 4011 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 4012 } 4013 4014 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 4015 { 4016 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 4017 } 4018 4019 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 4020 { 4021 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 4022 } 4023 4024 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) 4025 { 4026 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; 4027 } 4028 4029 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 4030 { 4031 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 4032 } 4033 4034 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 4035 { 4036 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 4037 } 4038 4039 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) 4040 { 4041 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; 4042 } 4043 4044 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) 4045 { 4046 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; 4047 } 4048 4049 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) 4050 { 4051 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1; 4052 } 4053 4054 static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) 4055 { 4056 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2; 4057 } 4058 4059 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 4060 { 4061 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 4062 } 4063 4064 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 4065 { 4066 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 4067 } 4068 4069 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 4070 { 4071 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 4072 } 4073 4074 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) 4075 { 4076 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; 4077 } 4078 4079 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) 4080 { 4081 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 4082 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4083 } 4084 4085 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) 4086 { 4087 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 4088 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4089 } 4090 4091 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) 4092 { 4093 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 && 4094 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4095 } 4096 4097 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 4098 { 4099 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 4100 } 4101 4102 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 4103 { 4104 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 4105 } 4106 4107 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 4108 { 4109 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 4110 } 4111 4112 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 4113 { 4114 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 4115 } 4116 4117 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 4118 { 4119 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4120 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 4121 } 4122 4123 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 4124 { 4125 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 4126 } 4127 4128 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 4129 { 4130 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4131 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 4132 } 4133 4134 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) 4135 { 4136 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0; 4137 } 4138 4139 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) 4140 { 4141 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1; 4142 } 4143 4144 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) 4145 { 4146 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0; 4147 } 4148 4149 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) 4150 { 4151 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4152 return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id)); 4153 } 4154 4155 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) 4156 { 4157 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4158 return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id)); 4159 } 4160 4161 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) 4162 { 4163 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); 4164 return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); 4165 } 4166 4167 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4168 { 4169 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4170 } 4171 4172 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4173 { 4174 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4175 } 4176 4177 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) 4178 { 4179 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; 4180 } 4181 4182 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) 4183 { 4184 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0; 4185 } 4186 4187 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) 4188 { 4189 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2; 4190 } 4191 4192 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4193 { 4194 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4195 } 4196 4197 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4198 { 4199 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4200 } 4201 4202 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 4203 { 4204 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); 4205 if (key >= 2) { 4206 return true; /* FEAT_CSV2_2 */ 4207 } 4208 if (key == 1) { 4209 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); 4210 return key >= 2; /* FEAT_CSV2_1p2 */ 4211 } 4212 return false; 4213 } 4214 4215 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4216 { 4217 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4218 } 4219 4220 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4221 { 4222 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4223 } 4224 4225 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4226 { 4227 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4228 } 4229 4230 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4231 { 4232 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4233 } 4234 4235 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4236 { 4237 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4238 } 4239 4240 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4241 { 4242 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4243 } 4244 4245 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4246 { 4247 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4248 } 4249 4250 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4251 { 4252 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4253 } 4254 4255 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4256 { 4257 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4258 } 4259 4260 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4261 { 4262 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4263 } 4264 4265 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4266 { 4267 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4268 } 4269 4270 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4271 { 4272 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4273 } 4274 4275 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) 4276 { 4277 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); 4278 } 4279 4280 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) 4281 { 4282 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; 4283 } 4284 4285 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) 4286 { 4287 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); 4288 } 4289 4290 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) 4291 { 4292 return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; 4293 } 4294 4295 /* 4296 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4297 */ 4298 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4299 { 4300 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4301 } 4302 4303 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4304 { 4305 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4306 } 4307 4308 static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id) 4309 { 4310 return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id); 4311 } 4312 4313 static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) 4314 { 4315 return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); 4316 } 4317 4318 static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) 4319 { 4320 return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); 4321 } 4322 4323 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4324 { 4325 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4326 } 4327 4328 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4329 { 4330 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4331 } 4332 4333 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4334 { 4335 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4336 } 4337 4338 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4339 { 4340 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4341 } 4342 4343 static inline bool isar_feature_any_half_evt(const ARMISARegisters *id) 4344 { 4345 return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id); 4346 } 4347 4348 static inline bool isar_feature_any_evt(const ARMISARegisters *id) 4349 { 4350 return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); 4351 } 4352 4353 /* 4354 * Forward to the above feature tests given an ARMCPU pointer. 4355 */ 4356 #define cpu_isar_feature(name, cpu) \ 4357 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4358 4359 #endif 4360