1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #define EXCP_UDEF 1 /* undefined instruction */ 43 #define EXCP_SWI 2 /* software interrupt */ 44 #define EXCP_PREFETCH_ABORT 3 45 #define EXCP_DATA_ABORT 4 46 #define EXCP_IRQ 5 47 #define EXCP_FIQ 6 48 #define EXCP_BKPT 7 49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 51 #define EXCP_HVC 11 /* HyperVisor Call */ 52 #define EXCP_HYP_TRAP 12 53 #define EXCP_SMC 13 /* Secure Monitor Call */ 54 #define EXCP_VIRQ 14 55 #define EXCP_VFIQ 15 56 #define EXCP_SEMIHOST 16 /* semihosting call */ 57 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 58 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 59 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 60 61 #define ARMV7M_EXCP_RESET 1 62 #define ARMV7M_EXCP_NMI 2 63 #define ARMV7M_EXCP_HARD 3 64 #define ARMV7M_EXCP_MEM 4 65 #define ARMV7M_EXCP_BUS 5 66 #define ARMV7M_EXCP_USAGE 6 67 #define ARMV7M_EXCP_SECURE 7 68 #define ARMV7M_EXCP_SVC 11 69 #define ARMV7M_EXCP_DEBUG 12 70 #define ARMV7M_EXCP_PENDSV 14 71 #define ARMV7M_EXCP_SYSTICK 15 72 73 /* For M profile, some registers are banked secure vs non-secure; 74 * these are represented as a 2-element array where the first element 75 * is the non-secure copy and the second is the secure copy. 76 * When the CPU does not have implement the security extension then 77 * only the first element is used. 78 * This means that the copy for the current security state can be 79 * accessed via env->registerfield[env->v7m.secure] (whether the security 80 * extension is implemented or not). 81 */ 82 enum { 83 M_REG_NS = 0, 84 M_REG_S = 1, 85 M_REG_NUM_BANKS = 2, 86 }; 87 88 /* ARM-specific interrupt pending bits. */ 89 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 90 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 91 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 92 93 /* The usual mapping for an AArch64 system register to its AArch32 94 * counterpart is for the 32 bit world to have access to the lower 95 * half only (with writes leaving the upper half untouched). It's 96 * therefore useful to be able to pass TCG the offset of the least 97 * significant half of a uint64_t struct member. 98 */ 99 #ifdef HOST_WORDS_BIGENDIAN 100 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 101 #define offsetofhigh32(S, M) offsetof(S, M) 102 #else 103 #define offsetoflow32(S, M) offsetof(S, M) 104 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 105 #endif 106 107 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 108 #define ARM_CPU_IRQ 0 109 #define ARM_CPU_FIQ 1 110 #define ARM_CPU_VIRQ 2 111 #define ARM_CPU_VFIQ 3 112 113 #define NB_MMU_MODES 8 114 /* ARM-specific extra insn start words: 115 * 1: Conditional execution bits 116 * 2: Partial exception syndrome for data aborts 117 */ 118 #define TARGET_INSN_START_EXTRA_WORDS 2 119 120 /* The 2nd extra word holding syndrome info for data aborts does not use 121 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 122 * help the sleb128 encoder do a better job. 123 * When restoring the CPU state, we shift it back up. 124 */ 125 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 126 #define ARM_INSN_START_WORD2_SHIFT 14 127 128 /* We currently assume float and double are IEEE single and double 129 precision respectively. 130 Doing runtime conversions is tricky because VFP registers may contain 131 integer values (eg. as the result of a FTOSI instruction). 132 s<2n> maps to the least significant half of d<n> 133 s<2n+1> maps to the most significant half of d<n> 134 */ 135 136 /* CPU state for each instance of a generic timer (in cp15 c14) */ 137 typedef struct ARMGenericTimer { 138 uint64_t cval; /* Timer CompareValue register */ 139 uint64_t ctl; /* Timer Control register */ 140 } ARMGenericTimer; 141 142 #define GTIMER_PHYS 0 143 #define GTIMER_VIRT 1 144 #define GTIMER_HYP 2 145 #define GTIMER_SEC 3 146 #define NUM_GTIMERS 4 147 148 typedef struct { 149 uint64_t raw_tcr; 150 uint32_t mask; 151 uint32_t base_mask; 152 } TCR; 153 154 /* Define a maximum sized vector register. 155 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 156 * For 64-bit, this is a 2048-bit SVE register. 157 * 158 * Note that the mapping between S, D, and Q views of the register bank 159 * differs between AArch64 and AArch32. 160 * In AArch32: 161 * Qn = regs[n].d[1]:regs[n].d[0] 162 * Dn = regs[n / 2].d[n & 1] 163 * Sn = regs[n / 4].d[n % 4 / 2], 164 * bits 31..0 for even n, and bits 63..32 for odd n 165 * (and regs[16] to regs[31] are inaccessible) 166 * In AArch64: 167 * Zn = regs[n].d[*] 168 * Qn = regs[n].d[1]:regs[n].d[0] 169 * Dn = regs[n].d[0] 170 * Sn = regs[n].d[0] bits 31..0 171 * Hn = regs[n].d[0] bits 15..0 172 * 173 * This corresponds to the architecturally defined mapping between 174 * the two execution states, and means we do not need to explicitly 175 * map these registers when changing states. 176 * 177 * Align the data for use with TCG host vector operations. 178 */ 179 180 #ifdef TARGET_AARCH64 181 # define ARM_MAX_VQ 16 182 #else 183 # define ARM_MAX_VQ 1 184 #endif 185 186 typedef struct ARMVectorReg { 187 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 188 } ARMVectorReg; 189 190 /* In AArch32 mode, predicate registers do not exist at all. */ 191 #ifdef TARGET_AARCH64 192 typedef struct ARMPredicateReg { 193 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); 194 } ARMPredicateReg; 195 #endif 196 197 198 typedef struct CPUARMState { 199 /* Regs for current mode. */ 200 uint32_t regs[16]; 201 202 /* 32/64 switch only happens when taking and returning from 203 * exceptions so the overlap semantics are taken care of then 204 * instead of having a complicated union. 205 */ 206 /* Regs for A64 mode. */ 207 uint64_t xregs[32]; 208 uint64_t pc; 209 /* PSTATE isn't an architectural register for ARMv8. However, it is 210 * convenient for us to assemble the underlying state into a 32 bit format 211 * identical to the architectural format used for the SPSR. (This is also 212 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 213 * 'pstate' register are.) Of the PSTATE bits: 214 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 215 * semantics as for AArch32, as described in the comments on each field) 216 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 217 * DAIF (exception masks) are kept in env->daif 218 * all other bits are stored in their correct places in env->pstate 219 */ 220 uint32_t pstate; 221 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 222 223 /* Frequently accessed CPSR bits are stored separately for efficiency. 224 This contains all the other bits. Use cpsr_{read,write} to access 225 the whole CPSR. */ 226 uint32_t uncached_cpsr; 227 uint32_t spsr; 228 229 /* Banked registers. */ 230 uint64_t banked_spsr[8]; 231 uint32_t banked_r13[8]; 232 uint32_t banked_r14[8]; 233 234 /* These hold r8-r12. */ 235 uint32_t usr_regs[5]; 236 uint32_t fiq_regs[5]; 237 238 /* cpsr flag cache for faster execution */ 239 uint32_t CF; /* 0 or 1 */ 240 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 241 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 242 uint32_t ZF; /* Z set if zero. */ 243 uint32_t QF; /* 0 or 1 */ 244 uint32_t GE; /* cpsr[19:16] */ 245 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 246 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 247 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 248 249 uint64_t elr_el[4]; /* AArch64 exception link regs */ 250 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 251 252 /* System control coprocessor (cp15) */ 253 struct { 254 uint32_t c0_cpuid; 255 union { /* Cache size selection */ 256 struct { 257 uint64_t _unused_csselr0; 258 uint64_t csselr_ns; 259 uint64_t _unused_csselr1; 260 uint64_t csselr_s; 261 }; 262 uint64_t csselr_el[4]; 263 }; 264 union { /* System control register. */ 265 struct { 266 uint64_t _unused_sctlr; 267 uint64_t sctlr_ns; 268 uint64_t hsctlr; 269 uint64_t sctlr_s; 270 }; 271 uint64_t sctlr_el[4]; 272 }; 273 uint64_t cpacr_el1; /* Architectural feature access control register */ 274 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 275 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 276 uint64_t sder; /* Secure debug enable register. */ 277 uint32_t nsacr; /* Non-secure access control register. */ 278 union { /* MMU translation table base 0. */ 279 struct { 280 uint64_t _unused_ttbr0_0; 281 uint64_t ttbr0_ns; 282 uint64_t _unused_ttbr0_1; 283 uint64_t ttbr0_s; 284 }; 285 uint64_t ttbr0_el[4]; 286 }; 287 union { /* MMU translation table base 1. */ 288 struct { 289 uint64_t _unused_ttbr1_0; 290 uint64_t ttbr1_ns; 291 uint64_t _unused_ttbr1_1; 292 uint64_t ttbr1_s; 293 }; 294 uint64_t ttbr1_el[4]; 295 }; 296 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 297 /* MMU translation table base control. */ 298 TCR tcr_el[4]; 299 TCR vtcr_el2; /* Virtualization Translation Control. */ 300 uint32_t c2_data; /* MPU data cacheable bits. */ 301 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 302 union { /* MMU domain access control register 303 * MPU write buffer control. 304 */ 305 struct { 306 uint64_t dacr_ns; 307 uint64_t dacr_s; 308 }; 309 struct { 310 uint64_t dacr32_el2; 311 }; 312 }; 313 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 314 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 315 uint64_t hcr_el2; /* Hypervisor configuration register */ 316 uint64_t scr_el3; /* Secure configuration register. */ 317 union { /* Fault status registers. */ 318 struct { 319 uint64_t ifsr_ns; 320 uint64_t ifsr_s; 321 }; 322 struct { 323 uint64_t ifsr32_el2; 324 }; 325 }; 326 union { 327 struct { 328 uint64_t _unused_dfsr; 329 uint64_t dfsr_ns; 330 uint64_t hsr; 331 uint64_t dfsr_s; 332 }; 333 uint64_t esr_el[4]; 334 }; 335 uint32_t c6_region[8]; /* MPU base/size registers. */ 336 union { /* Fault address registers. */ 337 struct { 338 uint64_t _unused_far0; 339 #ifdef HOST_WORDS_BIGENDIAN 340 uint32_t ifar_ns; 341 uint32_t dfar_ns; 342 uint32_t ifar_s; 343 uint32_t dfar_s; 344 #else 345 uint32_t dfar_ns; 346 uint32_t ifar_ns; 347 uint32_t dfar_s; 348 uint32_t ifar_s; 349 #endif 350 uint64_t _unused_far3; 351 }; 352 uint64_t far_el[4]; 353 }; 354 uint64_t hpfar_el2; 355 uint64_t hstr_el2; 356 union { /* Translation result. */ 357 struct { 358 uint64_t _unused_par_0; 359 uint64_t par_ns; 360 uint64_t _unused_par_1; 361 uint64_t par_s; 362 }; 363 uint64_t par_el[4]; 364 }; 365 366 uint32_t c9_insn; /* Cache lockdown registers. */ 367 uint32_t c9_data; 368 uint64_t c9_pmcr; /* performance monitor control register */ 369 uint64_t c9_pmcnten; /* perf monitor counter enables */ 370 uint32_t c9_pmovsr; /* perf monitor overflow status */ 371 uint32_t c9_pmuserenr; /* perf monitor user enable */ 372 uint64_t c9_pmselr; /* perf monitor counter selection register */ 373 uint64_t c9_pminten; /* perf monitor interrupt enables */ 374 union { /* Memory attribute redirection */ 375 struct { 376 #ifdef HOST_WORDS_BIGENDIAN 377 uint64_t _unused_mair_0; 378 uint32_t mair1_ns; 379 uint32_t mair0_ns; 380 uint64_t _unused_mair_1; 381 uint32_t mair1_s; 382 uint32_t mair0_s; 383 #else 384 uint64_t _unused_mair_0; 385 uint32_t mair0_ns; 386 uint32_t mair1_ns; 387 uint64_t _unused_mair_1; 388 uint32_t mair0_s; 389 uint32_t mair1_s; 390 #endif 391 }; 392 uint64_t mair_el[4]; 393 }; 394 union { /* vector base address register */ 395 struct { 396 uint64_t _unused_vbar; 397 uint64_t vbar_ns; 398 uint64_t hvbar; 399 uint64_t vbar_s; 400 }; 401 uint64_t vbar_el[4]; 402 }; 403 uint32_t mvbar; /* (monitor) vector base address register */ 404 struct { /* FCSE PID. */ 405 uint32_t fcseidr_ns; 406 uint32_t fcseidr_s; 407 }; 408 union { /* Context ID. */ 409 struct { 410 uint64_t _unused_contextidr_0; 411 uint64_t contextidr_ns; 412 uint64_t _unused_contextidr_1; 413 uint64_t contextidr_s; 414 }; 415 uint64_t contextidr_el[4]; 416 }; 417 union { /* User RW Thread register. */ 418 struct { 419 uint64_t tpidrurw_ns; 420 uint64_t tpidrprw_ns; 421 uint64_t htpidr; 422 uint64_t _tpidr_el3; 423 }; 424 uint64_t tpidr_el[4]; 425 }; 426 /* The secure banks of these registers don't map anywhere */ 427 uint64_t tpidrurw_s; 428 uint64_t tpidrprw_s; 429 uint64_t tpidruro_s; 430 431 union { /* User RO Thread register. */ 432 uint64_t tpidruro_ns; 433 uint64_t tpidrro_el[1]; 434 }; 435 uint64_t c14_cntfrq; /* Counter Frequency register */ 436 uint64_t c14_cntkctl; /* Timer Control register */ 437 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 438 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 439 ARMGenericTimer c14_timer[NUM_GTIMERS]; 440 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 441 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 442 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 443 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 444 uint32_t c15_threadid; /* TI debugger thread-ID. */ 445 uint32_t c15_config_base_address; /* SCU base address. */ 446 uint32_t c15_diagnostic; /* diagnostic register */ 447 uint32_t c15_power_diagnostic; 448 uint32_t c15_power_control; /* power control */ 449 uint64_t dbgbvr[16]; /* breakpoint value registers */ 450 uint64_t dbgbcr[16]; /* breakpoint control registers */ 451 uint64_t dbgwvr[16]; /* watchpoint value registers */ 452 uint64_t dbgwcr[16]; /* watchpoint control registers */ 453 uint64_t mdscr_el1; 454 uint64_t oslsr_el1; /* OS Lock Status */ 455 uint64_t mdcr_el2; 456 uint64_t mdcr_el3; 457 /* If the counter is enabled, this stores the last time the counter 458 * was reset. Otherwise it stores the counter value 459 */ 460 uint64_t c15_ccnt; 461 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 462 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 463 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 464 } cp15; 465 466 struct { 467 /* M profile has up to 4 stack pointers: 468 * a Main Stack Pointer and a Process Stack Pointer for each 469 * of the Secure and Non-Secure states. (If the CPU doesn't support 470 * the security extension then it has only two SPs.) 471 * In QEMU we always store the currently active SP in regs[13], 472 * and the non-active SP for the current security state in 473 * v7m.other_sp. The stack pointers for the inactive security state 474 * are stored in other_ss_msp and other_ss_psp. 475 * switch_v7m_security_state() is responsible for rearranging them 476 * when we change security state. 477 */ 478 uint32_t other_sp; 479 uint32_t other_ss_msp; 480 uint32_t other_ss_psp; 481 uint32_t vecbase[M_REG_NUM_BANKS]; 482 uint32_t basepri[M_REG_NUM_BANKS]; 483 uint32_t control[M_REG_NUM_BANKS]; 484 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 485 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 486 uint32_t hfsr; /* HardFault Status */ 487 uint32_t dfsr; /* Debug Fault Status Register */ 488 uint32_t sfsr; /* Secure Fault Status Register */ 489 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 490 uint32_t bfar; /* BusFault Address */ 491 uint32_t sfar; /* Secure Fault Address Register */ 492 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 493 int exception; 494 uint32_t primask[M_REG_NUM_BANKS]; 495 uint32_t faultmask[M_REG_NUM_BANKS]; 496 uint32_t aircr; /* only holds r/w state if security extn implemented */ 497 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 498 uint32_t csselr[M_REG_NUM_BANKS]; 499 uint32_t scr[M_REG_NUM_BANKS]; 500 uint32_t msplim[M_REG_NUM_BANKS]; 501 uint32_t psplim[M_REG_NUM_BANKS]; 502 } v7m; 503 504 /* Information associated with an exception about to be taken: 505 * code which raises an exception must set cs->exception_index and 506 * the relevant parts of this structure; the cpu_do_interrupt function 507 * will then set the guest-visible registers as part of the exception 508 * entry process. 509 */ 510 struct { 511 uint32_t syndrome; /* AArch64 format syndrome register */ 512 uint32_t fsr; /* AArch32 format fault status register info */ 513 uint64_t vaddress; /* virtual addr associated with exception, if any */ 514 uint32_t target_el; /* EL the exception should be targeted for */ 515 /* If we implement EL2 we will also need to store information 516 * about the intermediate physical address for stage 2 faults. 517 */ 518 } exception; 519 520 /* Thumb-2 EE state. */ 521 uint32_t teecr; 522 uint32_t teehbr; 523 524 /* VFP coprocessor state. */ 525 struct { 526 ARMVectorReg zregs[32]; 527 528 #ifdef TARGET_AARCH64 529 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 530 ARMPredicateReg pregs[17]; 531 #endif 532 533 uint32_t xregs[16]; 534 /* We store these fpcsr fields separately for convenience. */ 535 int vec_len; 536 int vec_stride; 537 538 /* scratch space when Tn are not sufficient. */ 539 uint32_t scratch[8]; 540 541 /* There are a number of distinct float control structures: 542 * 543 * fp_status: is the "normal" fp status. 544 * fp_status_fp16: used for half-precision calculations 545 * standard_fp_status : the ARM "Standard FPSCR Value" 546 * 547 * Half-precision operations are governed by a separate 548 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 549 * status structure to control this. 550 * 551 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 552 * round-to-nearest and is used by any operations (generally 553 * Neon) which the architecture defines as controlled by the 554 * standard FPSCR value rather than the FPSCR. 555 * 556 * To avoid having to transfer exception bits around, we simply 557 * say that the FPSCR cumulative exception flags are the logical 558 * OR of the flags in the three fp statuses. This relies on the 559 * only thing which needs to read the exception flags being 560 * an explicit FPSCR read. 561 */ 562 float_status fp_status; 563 float_status fp_status_f16; 564 float_status standard_fp_status; 565 566 /* ZCR_EL[1-3] */ 567 uint64_t zcr_el[4]; 568 } vfp; 569 uint64_t exclusive_addr; 570 uint64_t exclusive_val; 571 uint64_t exclusive_high; 572 573 /* iwMMXt coprocessor state. */ 574 struct { 575 uint64_t regs[16]; 576 uint64_t val; 577 578 uint32_t cregs[16]; 579 } iwmmxt; 580 581 #if defined(CONFIG_USER_ONLY) 582 /* For usermode syscall translation. */ 583 int eabi; 584 #endif 585 586 struct CPUBreakpoint *cpu_breakpoint[16]; 587 struct CPUWatchpoint *cpu_watchpoint[16]; 588 589 /* Fields up to this point are cleared by a CPU reset */ 590 struct {} end_reset_fields; 591 592 CPU_COMMON 593 594 /* Fields after CPU_COMMON are preserved across CPU reset. */ 595 596 /* Internal CPU feature flags. */ 597 uint64_t features; 598 599 /* PMSAv7 MPU */ 600 struct { 601 uint32_t *drbar; 602 uint32_t *drsr; 603 uint32_t *dracr; 604 uint32_t rnr[M_REG_NUM_BANKS]; 605 } pmsav7; 606 607 /* PMSAv8 MPU */ 608 struct { 609 /* The PMSAv8 implementation also shares some PMSAv7 config 610 * and state: 611 * pmsav7.rnr (region number register) 612 * pmsav7_dregion (number of configured regions) 613 */ 614 uint32_t *rbar[M_REG_NUM_BANKS]; 615 uint32_t *rlar[M_REG_NUM_BANKS]; 616 uint32_t mair0[M_REG_NUM_BANKS]; 617 uint32_t mair1[M_REG_NUM_BANKS]; 618 } pmsav8; 619 620 /* v8M SAU */ 621 struct { 622 uint32_t *rbar; 623 uint32_t *rlar; 624 uint32_t rnr; 625 uint32_t ctrl; 626 } sau; 627 628 void *nvic; 629 const struct arm_boot_info *boot_info; 630 /* Store GICv3CPUState to access from this struct */ 631 void *gicv3state; 632 } CPUARMState; 633 634 /** 635 * ARMELChangeHook: 636 * type of a function which can be registered via arm_register_el_change_hook() 637 * to get callbacks when the CPU changes its exception level or mode. 638 */ 639 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); 640 641 642 /* These values map onto the return values for 643 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 644 typedef enum ARMPSCIState { 645 PSCI_ON = 0, 646 PSCI_OFF = 1, 647 PSCI_ON_PENDING = 2 648 } ARMPSCIState; 649 650 /** 651 * ARMCPU: 652 * @env: #CPUARMState 653 * 654 * An ARM CPU core. 655 */ 656 struct ARMCPU { 657 /*< private >*/ 658 CPUState parent_obj; 659 /*< public >*/ 660 661 CPUARMState env; 662 663 /* Coprocessor information */ 664 GHashTable *cp_regs; 665 /* For marshalling (mostly coprocessor) register state between the 666 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 667 * we use these arrays. 668 */ 669 /* List of register indexes managed via these arrays; (full KVM style 670 * 64 bit indexes, not CPRegInfo 32 bit indexes) 671 */ 672 uint64_t *cpreg_indexes; 673 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 674 uint64_t *cpreg_values; 675 /* Length of the indexes, values, reset_values arrays */ 676 int32_t cpreg_array_len; 677 /* These are used only for migration: incoming data arrives in 678 * these fields and is sanity checked in post_load before copying 679 * to the working data structures above. 680 */ 681 uint64_t *cpreg_vmstate_indexes; 682 uint64_t *cpreg_vmstate_values; 683 int32_t cpreg_vmstate_array_len; 684 685 /* Timers used by the generic (architected) timer */ 686 QEMUTimer *gt_timer[NUM_GTIMERS]; 687 /* GPIO outputs for generic timer */ 688 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 689 /* GPIO output for GICv3 maintenance interrupt signal */ 690 qemu_irq gicv3_maintenance_interrupt; 691 /* GPIO output for the PMU interrupt */ 692 qemu_irq pmu_interrupt; 693 694 /* MemoryRegion to use for secure physical accesses */ 695 MemoryRegion *secure_memory; 696 697 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 698 Object *idau; 699 700 /* 'compatible' string for this CPU for Linux device trees */ 701 const char *dtb_compatible; 702 703 /* PSCI version for this CPU 704 * Bits[31:16] = Major Version 705 * Bits[15:0] = Minor Version 706 */ 707 uint32_t psci_version; 708 709 /* Should CPU start in PSCI powered-off state? */ 710 bool start_powered_off; 711 712 /* Current power state, access guarded by BQL */ 713 ARMPSCIState power_state; 714 715 /* CPU has virtualization extension */ 716 bool has_el2; 717 /* CPU has security extension */ 718 bool has_el3; 719 /* CPU has PMU (Performance Monitor Unit) */ 720 bool has_pmu; 721 722 /* CPU has memory protection unit */ 723 bool has_mpu; 724 /* PMSAv7 MPU number of supported regions */ 725 uint32_t pmsav7_dregion; 726 /* v8M SAU number of supported regions */ 727 uint32_t sau_sregion; 728 729 /* PSCI conduit used to invoke PSCI methods 730 * 0 - disabled, 1 - smc, 2 - hvc 731 */ 732 uint32_t psci_conduit; 733 734 /* For v8M, initial value of the Secure VTOR */ 735 uint32_t init_svtor; 736 737 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 738 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 739 */ 740 uint32_t kvm_target; 741 742 /* KVM init features for this CPU */ 743 uint32_t kvm_init_features[7]; 744 745 /* Uniprocessor system with MP extensions */ 746 bool mp_is_up; 747 748 /* The instance init functions for implementation-specific subclasses 749 * set these fields to specify the implementation-dependent values of 750 * various constant registers and reset values of non-constant 751 * registers. 752 * Some of these might become QOM properties eventually. 753 * Field names match the official register names as defined in the 754 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 755 * is used for reset values of non-constant registers; no reset_ 756 * prefix means a constant register. 757 */ 758 uint32_t midr; 759 uint32_t revidr; 760 uint32_t reset_fpsid; 761 uint32_t mvfr0; 762 uint32_t mvfr1; 763 uint32_t mvfr2; 764 uint32_t ctr; 765 uint32_t reset_sctlr; 766 uint32_t id_pfr0; 767 uint32_t id_pfr1; 768 uint32_t id_dfr0; 769 uint32_t pmceid0; 770 uint32_t pmceid1; 771 uint32_t id_afr0; 772 uint32_t id_mmfr0; 773 uint32_t id_mmfr1; 774 uint32_t id_mmfr2; 775 uint32_t id_mmfr3; 776 uint32_t id_mmfr4; 777 uint32_t id_isar0; 778 uint32_t id_isar1; 779 uint32_t id_isar2; 780 uint32_t id_isar3; 781 uint32_t id_isar4; 782 uint32_t id_isar5; 783 uint64_t id_aa64pfr0; 784 uint64_t id_aa64pfr1; 785 uint64_t id_aa64dfr0; 786 uint64_t id_aa64dfr1; 787 uint64_t id_aa64afr0; 788 uint64_t id_aa64afr1; 789 uint64_t id_aa64isar0; 790 uint64_t id_aa64isar1; 791 uint64_t id_aa64mmfr0; 792 uint64_t id_aa64mmfr1; 793 uint32_t dbgdidr; 794 uint32_t clidr; 795 uint64_t mp_affinity; /* MP ID without feature bits */ 796 /* The elements of this array are the CCSIDR values for each cache, 797 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 798 */ 799 uint32_t ccsidr[16]; 800 uint64_t reset_cbar; 801 uint32_t reset_auxcr; 802 bool reset_hivecs; 803 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 804 uint32_t dcz_blocksize; 805 uint64_t rvbar; 806 807 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 808 int gic_num_lrs; /* number of list registers */ 809 int gic_vpribits; /* number of virtual priority bits */ 810 int gic_vprebits; /* number of virtual preemption bits */ 811 812 /* Whether the cfgend input is high (i.e. this CPU should reset into 813 * big-endian mode). This setting isn't used directly: instead it modifies 814 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 815 * architecture version. 816 */ 817 bool cfgend; 818 819 ARMELChangeHook *el_change_hook; 820 void *el_change_hook_opaque; 821 822 int32_t node_id; /* NUMA node this CPU belongs to */ 823 824 /* Used to synchronize KVM and QEMU in-kernel device levels */ 825 uint8_t device_irq_level; 826 }; 827 828 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 829 { 830 return container_of(env, ARMCPU, env); 831 } 832 833 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 834 835 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 836 837 #define ENV_OFFSET offsetof(ARMCPU, env) 838 839 #ifndef CONFIG_USER_ONLY 840 extern const struct VMStateDescription vmstate_arm_cpu; 841 #endif 842 843 void arm_cpu_do_interrupt(CPUState *cpu); 844 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 845 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 846 847 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 848 int flags); 849 850 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 851 MemTxAttrs *attrs); 852 853 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 854 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 855 856 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 857 int cpuid, void *opaque); 858 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 859 int cpuid, void *opaque); 860 861 #ifdef TARGET_AARCH64 862 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 863 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 864 #endif 865 866 target_ulong do_arm_semihosting(CPUARMState *env); 867 void aarch64_sync_32_to_64(CPUARMState *env); 868 void aarch64_sync_64_to_32(CPUARMState *env); 869 870 static inline bool is_a64(CPUARMState *env) 871 { 872 return env->aarch64; 873 } 874 875 /* you can call this signal handler from your SIGBUS and SIGSEGV 876 signal handlers to inform the virtual CPU of exceptions. non zero 877 is returned if the signal was handled by the virtual CPU. */ 878 int cpu_arm_signal_handler(int host_signum, void *pinfo, 879 void *puc); 880 881 /** 882 * pmccntr_sync 883 * @env: CPUARMState 884 * 885 * Synchronises the counter in the PMCCNTR. This must always be called twice, 886 * once before any action that might affect the timer and again afterwards. 887 * The function is used to swap the state of the register if required. 888 * This only happens when not in user mode (!CONFIG_USER_ONLY) 889 */ 890 void pmccntr_sync(CPUARMState *env); 891 892 /* SCTLR bit meanings. Several bits have been reused in newer 893 * versions of the architecture; in that case we define constants 894 * for both old and new bit meanings. Code which tests against those 895 * bits should probably check or otherwise arrange that the CPU 896 * is the architectural version it expects. 897 */ 898 #define SCTLR_M (1U << 0) 899 #define SCTLR_A (1U << 1) 900 #define SCTLR_C (1U << 2) 901 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 902 #define SCTLR_SA (1U << 3) 903 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 904 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 905 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 906 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 907 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 908 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 909 #define SCTLR_ITD (1U << 7) /* v8 onward */ 910 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 911 #define SCTLR_SED (1U << 8) /* v8 onward */ 912 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 913 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 914 #define SCTLR_F (1U << 10) /* up to v6 */ 915 #define SCTLR_SW (1U << 10) /* v7 onward */ 916 #define SCTLR_Z (1U << 11) 917 #define SCTLR_I (1U << 12) 918 #define SCTLR_V (1U << 13) 919 #define SCTLR_RR (1U << 14) /* up to v7 */ 920 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 921 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 922 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 923 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 924 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 925 #define SCTLR_HA (1U << 17) 926 #define SCTLR_BR (1U << 17) /* PMSA only */ 927 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 928 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 929 #define SCTLR_WXN (1U << 19) 930 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 931 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 932 #define SCTLR_FI (1U << 21) 933 #define SCTLR_U (1U << 22) 934 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 935 #define SCTLR_VE (1U << 24) /* up to v7 */ 936 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 937 #define SCTLR_EE (1U << 25) 938 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 939 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 940 #define SCTLR_NMFI (1U << 27) 941 #define SCTLR_TRE (1U << 28) 942 #define SCTLR_AFE (1U << 29) 943 #define SCTLR_TE (1U << 30) 944 945 #define CPTR_TCPAC (1U << 31) 946 #define CPTR_TTA (1U << 20) 947 #define CPTR_TFP (1U << 10) 948 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 949 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 950 951 #define MDCR_EPMAD (1U << 21) 952 #define MDCR_EDAD (1U << 20) 953 #define MDCR_SPME (1U << 17) 954 #define MDCR_SDD (1U << 16) 955 #define MDCR_SPD (3U << 14) 956 #define MDCR_TDRA (1U << 11) 957 #define MDCR_TDOSA (1U << 10) 958 #define MDCR_TDA (1U << 9) 959 #define MDCR_TDE (1U << 8) 960 #define MDCR_HPME (1U << 7) 961 #define MDCR_TPM (1U << 6) 962 #define MDCR_TPMCR (1U << 5) 963 964 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 965 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 966 967 #define CPSR_M (0x1fU) 968 #define CPSR_T (1U << 5) 969 #define CPSR_F (1U << 6) 970 #define CPSR_I (1U << 7) 971 #define CPSR_A (1U << 8) 972 #define CPSR_E (1U << 9) 973 #define CPSR_IT_2_7 (0xfc00U) 974 #define CPSR_GE (0xfU << 16) 975 #define CPSR_IL (1U << 20) 976 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 977 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 978 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 979 * where it is live state but not accessible to the AArch32 code. 980 */ 981 #define CPSR_RESERVED (0x7U << 21) 982 #define CPSR_J (1U << 24) 983 #define CPSR_IT_0_1 (3U << 25) 984 #define CPSR_Q (1U << 27) 985 #define CPSR_V (1U << 28) 986 #define CPSR_C (1U << 29) 987 #define CPSR_Z (1U << 30) 988 #define CPSR_N (1U << 31) 989 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 990 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 991 992 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 993 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 994 | CPSR_NZCV) 995 /* Bits writable in user mode. */ 996 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 997 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 998 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 999 /* Mask of bits which may be set by exception return copying them from SPSR */ 1000 #define CPSR_ERET_MASK (~CPSR_RESERVED) 1001 1002 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1003 #define XPSR_EXCP 0x1ffU 1004 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1005 #define XPSR_IT_2_7 CPSR_IT_2_7 1006 #define XPSR_GE CPSR_GE 1007 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1008 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1009 #define XPSR_IT_0_1 CPSR_IT_0_1 1010 #define XPSR_Q CPSR_Q 1011 #define XPSR_V CPSR_V 1012 #define XPSR_C CPSR_C 1013 #define XPSR_Z CPSR_Z 1014 #define XPSR_N CPSR_N 1015 #define XPSR_NZCV CPSR_NZCV 1016 #define XPSR_IT CPSR_IT 1017 1018 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1019 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1020 #define TTBCR_PD0 (1U << 4) 1021 #define TTBCR_PD1 (1U << 5) 1022 #define TTBCR_EPD0 (1U << 7) 1023 #define TTBCR_IRGN0 (3U << 8) 1024 #define TTBCR_ORGN0 (3U << 10) 1025 #define TTBCR_SH0 (3U << 12) 1026 #define TTBCR_T1SZ (3U << 16) 1027 #define TTBCR_A1 (1U << 22) 1028 #define TTBCR_EPD1 (1U << 23) 1029 #define TTBCR_IRGN1 (3U << 24) 1030 #define TTBCR_ORGN1 (3U << 26) 1031 #define TTBCR_SH1 (1U << 28) 1032 #define TTBCR_EAE (1U << 31) 1033 1034 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1035 * Only these are valid when in AArch64 mode; in 1036 * AArch32 mode SPSRs are basically CPSR-format. 1037 */ 1038 #define PSTATE_SP (1U) 1039 #define PSTATE_M (0xFU) 1040 #define PSTATE_nRW (1U << 4) 1041 #define PSTATE_F (1U << 6) 1042 #define PSTATE_I (1U << 7) 1043 #define PSTATE_A (1U << 8) 1044 #define PSTATE_D (1U << 9) 1045 #define PSTATE_IL (1U << 20) 1046 #define PSTATE_SS (1U << 21) 1047 #define PSTATE_V (1U << 28) 1048 #define PSTATE_C (1U << 29) 1049 #define PSTATE_Z (1U << 30) 1050 #define PSTATE_N (1U << 31) 1051 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1052 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1053 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 1054 /* Mode values for AArch64 */ 1055 #define PSTATE_MODE_EL3h 13 1056 #define PSTATE_MODE_EL3t 12 1057 #define PSTATE_MODE_EL2h 9 1058 #define PSTATE_MODE_EL2t 8 1059 #define PSTATE_MODE_EL1h 5 1060 #define PSTATE_MODE_EL1t 4 1061 #define PSTATE_MODE_EL0t 0 1062 1063 /* Write a new value to v7m.exception, thus transitioning into or out 1064 * of Handler mode; this may result in a change of active stack pointer. 1065 */ 1066 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1067 1068 /* Map EL and handler into a PSTATE_MODE. */ 1069 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1070 { 1071 return (el << 2) | handler; 1072 } 1073 1074 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1075 * interprocessing, so we don't attempt to sync with the cpsr state used by 1076 * the 32 bit decoder. 1077 */ 1078 static inline uint32_t pstate_read(CPUARMState *env) 1079 { 1080 int ZF; 1081 1082 ZF = (env->ZF == 0); 1083 return (env->NF & 0x80000000) | (ZF << 30) 1084 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1085 | env->pstate | env->daif; 1086 } 1087 1088 static inline void pstate_write(CPUARMState *env, uint32_t val) 1089 { 1090 env->ZF = (~val) & PSTATE_Z; 1091 env->NF = val; 1092 env->CF = (val >> 29) & 1; 1093 env->VF = (val << 3) & 0x80000000; 1094 env->daif = val & PSTATE_DAIF; 1095 env->pstate = val & ~CACHED_PSTATE_BITS; 1096 } 1097 1098 /* Return the current CPSR value. */ 1099 uint32_t cpsr_read(CPUARMState *env); 1100 1101 typedef enum CPSRWriteType { 1102 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1103 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1104 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1105 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1106 } CPSRWriteType; 1107 1108 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1109 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1110 CPSRWriteType write_type); 1111 1112 /* Return the current xPSR value. */ 1113 static inline uint32_t xpsr_read(CPUARMState *env) 1114 { 1115 int ZF; 1116 ZF = (env->ZF == 0); 1117 return (env->NF & 0x80000000) | (ZF << 30) 1118 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1119 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1120 | ((env->condexec_bits & 0xfc) << 8) 1121 | env->v7m.exception; 1122 } 1123 1124 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1125 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1126 { 1127 if (mask & XPSR_NZCV) { 1128 env->ZF = (~val) & XPSR_Z; 1129 env->NF = val; 1130 env->CF = (val >> 29) & 1; 1131 env->VF = (val << 3) & 0x80000000; 1132 } 1133 if (mask & XPSR_Q) { 1134 env->QF = ((val & XPSR_Q) != 0); 1135 } 1136 if (mask & XPSR_T) { 1137 env->thumb = ((val & XPSR_T) != 0); 1138 } 1139 if (mask & XPSR_IT_0_1) { 1140 env->condexec_bits &= ~3; 1141 env->condexec_bits |= (val >> 25) & 3; 1142 } 1143 if (mask & XPSR_IT_2_7) { 1144 env->condexec_bits &= 3; 1145 env->condexec_bits |= (val >> 8) & 0xfc; 1146 } 1147 if (mask & XPSR_EXCP) { 1148 /* Note that this only happens on exception exit */ 1149 write_v7m_exception(env, val & XPSR_EXCP); 1150 } 1151 } 1152 1153 #define HCR_VM (1ULL << 0) 1154 #define HCR_SWIO (1ULL << 1) 1155 #define HCR_PTW (1ULL << 2) 1156 #define HCR_FMO (1ULL << 3) 1157 #define HCR_IMO (1ULL << 4) 1158 #define HCR_AMO (1ULL << 5) 1159 #define HCR_VF (1ULL << 6) 1160 #define HCR_VI (1ULL << 7) 1161 #define HCR_VSE (1ULL << 8) 1162 #define HCR_FB (1ULL << 9) 1163 #define HCR_BSU_MASK (3ULL << 10) 1164 #define HCR_DC (1ULL << 12) 1165 #define HCR_TWI (1ULL << 13) 1166 #define HCR_TWE (1ULL << 14) 1167 #define HCR_TID0 (1ULL << 15) 1168 #define HCR_TID1 (1ULL << 16) 1169 #define HCR_TID2 (1ULL << 17) 1170 #define HCR_TID3 (1ULL << 18) 1171 #define HCR_TSC (1ULL << 19) 1172 #define HCR_TIDCP (1ULL << 20) 1173 #define HCR_TACR (1ULL << 21) 1174 #define HCR_TSW (1ULL << 22) 1175 #define HCR_TPC (1ULL << 23) 1176 #define HCR_TPU (1ULL << 24) 1177 #define HCR_TTLB (1ULL << 25) 1178 #define HCR_TVM (1ULL << 26) 1179 #define HCR_TGE (1ULL << 27) 1180 #define HCR_TDZ (1ULL << 28) 1181 #define HCR_HCD (1ULL << 29) 1182 #define HCR_TRVM (1ULL << 30) 1183 #define HCR_RW (1ULL << 31) 1184 #define HCR_CD (1ULL << 32) 1185 #define HCR_ID (1ULL << 33) 1186 #define HCR_MASK ((1ULL << 34) - 1) 1187 1188 #define SCR_NS (1U << 0) 1189 #define SCR_IRQ (1U << 1) 1190 #define SCR_FIQ (1U << 2) 1191 #define SCR_EA (1U << 3) 1192 #define SCR_FW (1U << 4) 1193 #define SCR_AW (1U << 5) 1194 #define SCR_NET (1U << 6) 1195 #define SCR_SMD (1U << 7) 1196 #define SCR_HCE (1U << 8) 1197 #define SCR_SIF (1U << 9) 1198 #define SCR_RW (1U << 10) 1199 #define SCR_ST (1U << 11) 1200 #define SCR_TWI (1U << 12) 1201 #define SCR_TWE (1U << 13) 1202 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1203 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1204 1205 /* Return the current FPSCR value. */ 1206 uint32_t vfp_get_fpscr(CPUARMState *env); 1207 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1208 1209 /* FPCR, Floating Point Control Register 1210 * FPSR, Floating Poiht Status Register 1211 * 1212 * For A64 the FPSCR is split into two logically distinct registers, 1213 * FPCR and FPSR. However since they still use non-overlapping bits 1214 * we store the underlying state in fpscr and just mask on read/write. 1215 */ 1216 #define FPSR_MASK 0xf800009f 1217 #define FPCR_MASK 0x07f79f00 1218 1219 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1220 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1221 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1222 1223 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1224 { 1225 return vfp_get_fpscr(env) & FPSR_MASK; 1226 } 1227 1228 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1229 { 1230 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1231 vfp_set_fpscr(env, new_fpscr); 1232 } 1233 1234 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1235 { 1236 return vfp_get_fpscr(env) & FPCR_MASK; 1237 } 1238 1239 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1240 { 1241 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1242 vfp_set_fpscr(env, new_fpscr); 1243 } 1244 1245 enum arm_cpu_mode { 1246 ARM_CPU_MODE_USR = 0x10, 1247 ARM_CPU_MODE_FIQ = 0x11, 1248 ARM_CPU_MODE_IRQ = 0x12, 1249 ARM_CPU_MODE_SVC = 0x13, 1250 ARM_CPU_MODE_MON = 0x16, 1251 ARM_CPU_MODE_ABT = 0x17, 1252 ARM_CPU_MODE_HYP = 0x1a, 1253 ARM_CPU_MODE_UND = 0x1b, 1254 ARM_CPU_MODE_SYS = 0x1f 1255 }; 1256 1257 /* VFP system registers. */ 1258 #define ARM_VFP_FPSID 0 1259 #define ARM_VFP_FPSCR 1 1260 #define ARM_VFP_MVFR2 5 1261 #define ARM_VFP_MVFR1 6 1262 #define ARM_VFP_MVFR0 7 1263 #define ARM_VFP_FPEXC 8 1264 #define ARM_VFP_FPINST 9 1265 #define ARM_VFP_FPINST2 10 1266 1267 /* iwMMXt coprocessor control registers. */ 1268 #define ARM_IWMMXT_wCID 0 1269 #define ARM_IWMMXT_wCon 1 1270 #define ARM_IWMMXT_wCSSF 2 1271 #define ARM_IWMMXT_wCASF 3 1272 #define ARM_IWMMXT_wCGR0 8 1273 #define ARM_IWMMXT_wCGR1 9 1274 #define ARM_IWMMXT_wCGR2 10 1275 #define ARM_IWMMXT_wCGR3 11 1276 1277 /* V7M CCR bits */ 1278 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1279 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1280 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1281 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1282 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1283 FIELD(V7M_CCR, STKALIGN, 9, 1) 1284 FIELD(V7M_CCR, DC, 16, 1) 1285 FIELD(V7M_CCR, IC, 17, 1) 1286 1287 /* V7M SCR bits */ 1288 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1289 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1290 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1291 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1292 1293 /* V7M AIRCR bits */ 1294 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1295 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1296 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1297 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1298 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1299 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1300 FIELD(V7M_AIRCR, PRIS, 14, 1) 1301 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1302 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1303 1304 /* V7M CFSR bits for MMFSR */ 1305 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1306 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1307 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1308 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1309 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1310 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1311 1312 /* V7M CFSR bits for BFSR */ 1313 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1314 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1315 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1316 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1317 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1318 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1319 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1320 1321 /* V7M CFSR bits for UFSR */ 1322 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1323 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1324 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1325 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1326 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1327 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1328 1329 /* V7M CFSR bit masks covering all of the subregister bits */ 1330 FIELD(V7M_CFSR, MMFSR, 0, 8) 1331 FIELD(V7M_CFSR, BFSR, 8, 8) 1332 FIELD(V7M_CFSR, UFSR, 16, 16) 1333 1334 /* V7M HFSR bits */ 1335 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1336 FIELD(V7M_HFSR, FORCED, 30, 1) 1337 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1338 1339 /* V7M DFSR bits */ 1340 FIELD(V7M_DFSR, HALTED, 0, 1) 1341 FIELD(V7M_DFSR, BKPT, 1, 1) 1342 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1343 FIELD(V7M_DFSR, VCATCH, 3, 1) 1344 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1345 1346 /* V7M SFSR bits */ 1347 FIELD(V7M_SFSR, INVEP, 0, 1) 1348 FIELD(V7M_SFSR, INVIS, 1, 1) 1349 FIELD(V7M_SFSR, INVER, 2, 1) 1350 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1351 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1352 FIELD(V7M_SFSR, LSPERR, 5, 1) 1353 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1354 FIELD(V7M_SFSR, LSERR, 7, 1) 1355 1356 /* v7M MPU_CTRL bits */ 1357 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1358 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1359 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1360 1361 /* v7M CLIDR bits */ 1362 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1363 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1364 FIELD(V7M_CLIDR, LOC, 24, 3) 1365 FIELD(V7M_CLIDR, LOUU, 27, 3) 1366 FIELD(V7M_CLIDR, ICB, 30, 2) 1367 1368 FIELD(V7M_CSSELR, IND, 0, 1) 1369 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1370 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1371 * define a mask for this and check that it doesn't permit running off 1372 * the end of the array. 1373 */ 1374 FIELD(V7M_CSSELR, INDEX, 0, 4) 1375 1376 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1377 1378 /* If adding a feature bit which corresponds to a Linux ELF 1379 * HWCAP bit, remember to update the feature-bit-to-hwcap 1380 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1381 */ 1382 enum arm_features { 1383 ARM_FEATURE_VFP, 1384 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1385 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1386 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1387 ARM_FEATURE_V6, 1388 ARM_FEATURE_V6K, 1389 ARM_FEATURE_V7, 1390 ARM_FEATURE_THUMB2, 1391 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1392 ARM_FEATURE_VFP3, 1393 ARM_FEATURE_VFP_FP16, 1394 ARM_FEATURE_NEON, 1395 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1396 ARM_FEATURE_M, /* Microcontroller profile. */ 1397 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1398 ARM_FEATURE_THUMB2EE, 1399 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1400 ARM_FEATURE_V4T, 1401 ARM_FEATURE_V5, 1402 ARM_FEATURE_STRONGARM, 1403 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1404 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1405 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1406 ARM_FEATURE_GENERIC_TIMER, 1407 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1408 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1409 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1410 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1411 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1412 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1413 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1414 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1415 ARM_FEATURE_V8, 1416 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1417 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1418 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1419 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1420 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1421 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1422 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1423 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1424 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1425 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1426 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1427 ARM_FEATURE_PMU, /* has PMU support */ 1428 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1429 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1430 ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ 1431 ARM_FEATURE_SVE, /* has Scalable Vector Extension */ 1432 ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensions */ 1433 ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ 1434 ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ 1435 ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ 1436 ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ 1437 ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ 1438 ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ 1439 }; 1440 1441 static inline int arm_feature(CPUARMState *env, int feature) 1442 { 1443 return (env->features & (1ULL << feature)) != 0; 1444 } 1445 1446 #if !defined(CONFIG_USER_ONLY) 1447 /* Return true if exception levels below EL3 are in secure state, 1448 * or would be following an exception return to that level. 1449 * Unlike arm_is_secure() (which is always a question about the 1450 * _current_ state of the CPU) this doesn't care about the current 1451 * EL or mode. 1452 */ 1453 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1454 { 1455 if (arm_feature(env, ARM_FEATURE_EL3)) { 1456 return !(env->cp15.scr_el3 & SCR_NS); 1457 } else { 1458 /* If EL3 is not supported then the secure state is implementation 1459 * defined, in which case QEMU defaults to non-secure. 1460 */ 1461 return false; 1462 } 1463 } 1464 1465 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1466 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1467 { 1468 if (arm_feature(env, ARM_FEATURE_EL3)) { 1469 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1470 /* CPU currently in AArch64 state and EL3 */ 1471 return true; 1472 } else if (!is_a64(env) && 1473 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1474 /* CPU currently in AArch32 state and monitor mode */ 1475 return true; 1476 } 1477 } 1478 return false; 1479 } 1480 1481 /* Return true if the processor is in secure state */ 1482 static inline bool arm_is_secure(CPUARMState *env) 1483 { 1484 if (arm_is_el3_or_mon(env)) { 1485 return true; 1486 } 1487 return arm_is_secure_below_el3(env); 1488 } 1489 1490 #else 1491 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1492 { 1493 return false; 1494 } 1495 1496 static inline bool arm_is_secure(CPUARMState *env) 1497 { 1498 return false; 1499 } 1500 #endif 1501 1502 /* Return true if the specified exception level is running in AArch64 state. */ 1503 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1504 { 1505 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1506 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1507 */ 1508 assert(el >= 1 && el <= 3); 1509 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1510 1511 /* The highest exception level is always at the maximum supported 1512 * register width, and then lower levels have a register width controlled 1513 * by bits in the SCR or HCR registers. 1514 */ 1515 if (el == 3) { 1516 return aa64; 1517 } 1518 1519 if (arm_feature(env, ARM_FEATURE_EL3)) { 1520 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1521 } 1522 1523 if (el == 2) { 1524 return aa64; 1525 } 1526 1527 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1528 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1529 } 1530 1531 return aa64; 1532 } 1533 1534 /* Function for determing whether guest cp register reads and writes should 1535 * access the secure or non-secure bank of a cp register. When EL3 is 1536 * operating in AArch32 state, the NS-bit determines whether the secure 1537 * instance of a cp register should be used. When EL3 is AArch64 (or if 1538 * it doesn't exist at all) then there is no register banking, and all 1539 * accesses are to the non-secure version. 1540 */ 1541 static inline bool access_secure_reg(CPUARMState *env) 1542 { 1543 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1544 !arm_el_is_aa64(env, 3) && 1545 !(env->cp15.scr_el3 & SCR_NS)); 1546 1547 return ret; 1548 } 1549 1550 /* Macros for accessing a specified CP register bank */ 1551 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1552 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1553 1554 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1555 do { \ 1556 if (_secure) { \ 1557 (_env)->cp15._regname##_s = (_val); \ 1558 } else { \ 1559 (_env)->cp15._regname##_ns = (_val); \ 1560 } \ 1561 } while (0) 1562 1563 /* Macros for automatically accessing a specific CP register bank depending on 1564 * the current secure state of the system. These macros are not intended for 1565 * supporting instruction translation reads/writes as these are dependent 1566 * solely on the SCR.NS bit and not the mode. 1567 */ 1568 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1569 A32_BANKED_REG_GET((_env), _regname, \ 1570 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1571 1572 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1573 A32_BANKED_REG_SET((_env), _regname, \ 1574 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1575 (_val)) 1576 1577 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1578 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1579 uint32_t cur_el, bool secure); 1580 1581 /* Interface between CPU and Interrupt controller. */ 1582 #ifndef CONFIG_USER_ONLY 1583 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1584 #else 1585 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1586 { 1587 return true; 1588 } 1589 #endif 1590 /** 1591 * armv7m_nvic_set_pending: mark the specified exception as pending 1592 * @opaque: the NVIC 1593 * @irq: the exception number to mark pending 1594 * @secure: false for non-banked exceptions or for the nonsecure 1595 * version of a banked exception, true for the secure version of a banked 1596 * exception. 1597 * 1598 * Marks the specified exception as pending. Note that we will assert() 1599 * if @secure is true and @irq does not specify one of the fixed set 1600 * of architecturally banked exceptions. 1601 */ 1602 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1603 /** 1604 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 1605 * @opaque: the NVIC 1606 * @irq: the exception number to mark pending 1607 * @secure: false for non-banked exceptions or for the nonsecure 1608 * version of a banked exception, true for the secure version of a banked 1609 * exception. 1610 * 1611 * Similar to armv7m_nvic_set_pending(), but specifically for derived 1612 * exceptions (exceptions generated in the course of trying to take 1613 * a different exception). 1614 */ 1615 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 1616 /** 1617 * armv7m_nvic_get_pending_irq_info: return highest priority pending 1618 * exception, and whether it targets Secure state 1619 * @opaque: the NVIC 1620 * @pirq: set to pending exception number 1621 * @ptargets_secure: set to whether pending exception targets Secure 1622 * 1623 * This function writes the number of the highest priority pending 1624 * exception (the one which would be made active by 1625 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 1626 * to true if the current highest priority pending exception should 1627 * be taken to Secure state, false for NS. 1628 */ 1629 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 1630 bool *ptargets_secure); 1631 /** 1632 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 1633 * @opaque: the NVIC 1634 * 1635 * Move the current highest priority pending exception from the pending 1636 * state to the active state, and update v7m.exception to indicate that 1637 * it is the exception currently being handled. 1638 */ 1639 void armv7m_nvic_acknowledge_irq(void *opaque); 1640 /** 1641 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1642 * @opaque: the NVIC 1643 * @irq: the exception number to complete 1644 * @secure: true if this exception was secure 1645 * 1646 * Returns: -1 if the irq was not active 1647 * 1 if completing this irq brought us back to base (no active irqs) 1648 * 0 if there is still an irq active after this one was completed 1649 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1650 */ 1651 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 1652 /** 1653 * armv7m_nvic_raw_execution_priority: return the raw execution priority 1654 * @opaque: the NVIC 1655 * 1656 * Returns: the raw execution priority as defined by the v8M architecture. 1657 * This is the execution priority minus the effects of AIRCR.PRIS, 1658 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 1659 * (v8M ARM ARM I_PKLD.) 1660 */ 1661 int armv7m_nvic_raw_execution_priority(void *opaque); 1662 /** 1663 * armv7m_nvic_neg_prio_requested: return true if the requested execution 1664 * priority is negative for the specified security state. 1665 * @opaque: the NVIC 1666 * @secure: the security state to test 1667 * This corresponds to the pseudocode IsReqExecPriNeg(). 1668 */ 1669 #ifndef CONFIG_USER_ONLY 1670 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 1671 #else 1672 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 1673 { 1674 return false; 1675 } 1676 #endif 1677 1678 /* Interface for defining coprocessor registers. 1679 * Registers are defined in tables of arm_cp_reginfo structs 1680 * which are passed to define_arm_cp_regs(). 1681 */ 1682 1683 /* When looking up a coprocessor register we look for it 1684 * via an integer which encodes all of: 1685 * coprocessor number 1686 * Crn, Crm, opc1, opc2 fields 1687 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1688 * or via MRRC/MCRR?) 1689 * non-secure/secure bank (AArch32 only) 1690 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1691 * (In this case crn and opc2 should be zero.) 1692 * For AArch64, there is no 32/64 bit size distinction; 1693 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1694 * and 4 bit CRn and CRm. The encoding patterns are chosen 1695 * to be easy to convert to and from the KVM encodings, and also 1696 * so that the hashtable can contain both AArch32 and AArch64 1697 * registers (to allow for interprocessing where we might run 1698 * 32 bit code on a 64 bit core). 1699 */ 1700 /* This bit is private to our hashtable cpreg; in KVM register 1701 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1702 * in the upper bits of the 64 bit ID. 1703 */ 1704 #define CP_REG_AA64_SHIFT 28 1705 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1706 1707 /* To enable banking of coprocessor registers depending on ns-bit we 1708 * add a bit to distinguish between secure and non-secure cpregs in the 1709 * hashtable. 1710 */ 1711 #define CP_REG_NS_SHIFT 29 1712 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1713 1714 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1715 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1716 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1717 1718 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1719 (CP_REG_AA64_MASK | \ 1720 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1721 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1722 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1723 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1724 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1725 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1726 1727 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1728 * version used as a key for the coprocessor register hashtable 1729 */ 1730 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1731 { 1732 uint32_t cpregid = kvmid; 1733 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1734 cpregid |= CP_REG_AA64_MASK; 1735 } else { 1736 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1737 cpregid |= (1 << 15); 1738 } 1739 1740 /* KVM is always non-secure so add the NS flag on AArch32 register 1741 * entries. 1742 */ 1743 cpregid |= 1 << CP_REG_NS_SHIFT; 1744 } 1745 return cpregid; 1746 } 1747 1748 /* Convert a truncated 32 bit hashtable key into the full 1749 * 64 bit KVM register ID. 1750 */ 1751 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1752 { 1753 uint64_t kvmid; 1754 1755 if (cpregid & CP_REG_AA64_MASK) { 1756 kvmid = cpregid & ~CP_REG_AA64_MASK; 1757 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1758 } else { 1759 kvmid = cpregid & ~(1 << 15); 1760 if (cpregid & (1 << 15)) { 1761 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1762 } else { 1763 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1764 } 1765 } 1766 return kvmid; 1767 } 1768 1769 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1770 * special-behaviour cp reg and bits [11..8] indicate what behaviour 1771 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1772 * TCG can assume the value to be constant (ie load at translate time) 1773 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1774 * indicates that the TB should not be ended after a write to this register 1775 * (the default is that the TB ends after cp writes). OVERRIDE permits 1776 * a register definition to override a previous definition for the 1777 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1778 * old must have the OVERRIDE bit set. 1779 * ALIAS indicates that this register is an alias view of some underlying 1780 * state which is also visible via another register, and that the other 1781 * register is handling migration and reset; registers marked ALIAS will not be 1782 * migrated but may have their state set by syncing of register state from KVM. 1783 * NO_RAW indicates that this register has no underlying state and does not 1784 * support raw access for state saving/loading; it will not be used for either 1785 * migration or KVM state synchronization. (Typically this is for "registers" 1786 * which are actually used as instructions for cache maintenance and so on.) 1787 * IO indicates that this register does I/O and therefore its accesses 1788 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1789 * registers which implement clocks or timers require this. 1790 */ 1791 #define ARM_CP_SPECIAL 0x0001 1792 #define ARM_CP_CONST 0x0002 1793 #define ARM_CP_64BIT 0x0004 1794 #define ARM_CP_SUPPRESS_TB_END 0x0008 1795 #define ARM_CP_OVERRIDE 0x0010 1796 #define ARM_CP_ALIAS 0x0020 1797 #define ARM_CP_IO 0x0040 1798 #define ARM_CP_NO_RAW 0x0080 1799 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 1800 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 1801 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 1802 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 1803 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 1804 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1805 #define ARM_CP_FPU 0x1000 1806 #define ARM_CP_SVE 0x2000 1807 /* Used only as a terminator for ARMCPRegInfo lists */ 1808 #define ARM_CP_SENTINEL 0xffff 1809 /* Mask of only the flag bits in a type field */ 1810 #define ARM_CP_FLAG_MASK 0x30ff 1811 1812 /* Valid values for ARMCPRegInfo state field, indicating which of 1813 * the AArch32 and AArch64 execution states this register is visible in. 1814 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1815 * If the reginfo is declared to be visible in both states then a second 1816 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1817 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1818 * Note that we rely on the values of these enums as we iterate through 1819 * the various states in some places. 1820 */ 1821 enum { 1822 ARM_CP_STATE_AA32 = 0, 1823 ARM_CP_STATE_AA64 = 1, 1824 ARM_CP_STATE_BOTH = 2, 1825 }; 1826 1827 /* ARM CP register secure state flags. These flags identify security state 1828 * attributes for a given CP register entry. 1829 * The existence of both or neither secure and non-secure flags indicates that 1830 * the register has both a secure and non-secure hash entry. A single one of 1831 * these flags causes the register to only be hashed for the specified 1832 * security state. 1833 * Although definitions may have any combination of the S/NS bits, each 1834 * registered entry will only have one to identify whether the entry is secure 1835 * or non-secure. 1836 */ 1837 enum { 1838 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1839 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1840 }; 1841 1842 /* Return true if cptype is a valid type field. This is used to try to 1843 * catch errors where the sentinel has been accidentally left off the end 1844 * of a list of registers. 1845 */ 1846 static inline bool cptype_valid(int cptype) 1847 { 1848 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1849 || ((cptype & ARM_CP_SPECIAL) && 1850 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1851 } 1852 1853 /* Access rights: 1854 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1855 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1856 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1857 * (ie any of the privileged modes in Secure state, or Monitor mode). 1858 * If a register is accessible in one privilege level it's always accessible 1859 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1860 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1861 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1862 * terminology a little and call this PL3. 1863 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1864 * with the ELx exception levels. 1865 * 1866 * If access permissions for a register are more complex than can be 1867 * described with these bits, then use a laxer set of restrictions, and 1868 * do the more restrictive/complex check inside a helper function. 1869 */ 1870 #define PL3_R 0x80 1871 #define PL3_W 0x40 1872 #define PL2_R (0x20 | PL3_R) 1873 #define PL2_W (0x10 | PL3_W) 1874 #define PL1_R (0x08 | PL2_R) 1875 #define PL1_W (0x04 | PL2_W) 1876 #define PL0_R (0x02 | PL1_R) 1877 #define PL0_W (0x01 | PL1_W) 1878 1879 #define PL3_RW (PL3_R | PL3_W) 1880 #define PL2_RW (PL2_R | PL2_W) 1881 #define PL1_RW (PL1_R | PL1_W) 1882 #define PL0_RW (PL0_R | PL0_W) 1883 1884 /* Return the highest implemented Exception Level */ 1885 static inline int arm_highest_el(CPUARMState *env) 1886 { 1887 if (arm_feature(env, ARM_FEATURE_EL3)) { 1888 return 3; 1889 } 1890 if (arm_feature(env, ARM_FEATURE_EL2)) { 1891 return 2; 1892 } 1893 return 1; 1894 } 1895 1896 /* Return true if a v7M CPU is in Handler mode */ 1897 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 1898 { 1899 return env->v7m.exception != 0; 1900 } 1901 1902 /* Return the current Exception Level (as per ARMv8; note that this differs 1903 * from the ARMv7 Privilege Level). 1904 */ 1905 static inline int arm_current_el(CPUARMState *env) 1906 { 1907 if (arm_feature(env, ARM_FEATURE_M)) { 1908 return arm_v7m_is_handler_mode(env) || 1909 !(env->v7m.control[env->v7m.secure] & 1); 1910 } 1911 1912 if (is_a64(env)) { 1913 return extract32(env->pstate, 2, 2); 1914 } 1915 1916 switch (env->uncached_cpsr & 0x1f) { 1917 case ARM_CPU_MODE_USR: 1918 return 0; 1919 case ARM_CPU_MODE_HYP: 1920 return 2; 1921 case ARM_CPU_MODE_MON: 1922 return 3; 1923 default: 1924 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1925 /* If EL3 is 32-bit then all secure privileged modes run in 1926 * EL3 1927 */ 1928 return 3; 1929 } 1930 1931 return 1; 1932 } 1933 } 1934 1935 typedef struct ARMCPRegInfo ARMCPRegInfo; 1936 1937 typedef enum CPAccessResult { 1938 /* Access is permitted */ 1939 CP_ACCESS_OK = 0, 1940 /* Access fails due to a configurable trap or enable which would 1941 * result in a categorized exception syndrome giving information about 1942 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1943 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1944 * PL1 if in EL0, otherwise to the current EL). 1945 */ 1946 CP_ACCESS_TRAP = 1, 1947 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1948 * Note that this is not a catch-all case -- the set of cases which may 1949 * result in this failure is specifically defined by the architecture. 1950 */ 1951 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 1952 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 1953 CP_ACCESS_TRAP_EL2 = 3, 1954 CP_ACCESS_TRAP_EL3 = 4, 1955 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 1956 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 1957 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 1958 /* Access fails and results in an exception syndrome for an FP access, 1959 * trapped directly to EL2 or EL3 1960 */ 1961 CP_ACCESS_TRAP_FP_EL2 = 7, 1962 CP_ACCESS_TRAP_FP_EL3 = 8, 1963 } CPAccessResult; 1964 1965 /* Access functions for coprocessor registers. These cannot fail and 1966 * may not raise exceptions. 1967 */ 1968 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1969 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 1970 uint64_t value); 1971 /* Access permission check functions for coprocessor registers. */ 1972 typedef CPAccessResult CPAccessFn(CPUARMState *env, 1973 const ARMCPRegInfo *opaque, 1974 bool isread); 1975 /* Hook function for register reset */ 1976 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1977 1978 #define CP_ANY 0xff 1979 1980 /* Definition of an ARM coprocessor register */ 1981 struct ARMCPRegInfo { 1982 /* Name of register (useful mainly for debugging, need not be unique) */ 1983 const char *name; 1984 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 1985 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 1986 * 'wildcard' field -- any value of that field in the MRC/MCR insn 1987 * will be decoded to this register. The register read and write 1988 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 1989 * used by the program, so it is possible to register a wildcard and 1990 * then behave differently on read/write if necessary. 1991 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 1992 * must both be zero. 1993 * For AArch64-visible registers, opc0 is also used. 1994 * Since there are no "coprocessors" in AArch64, cp is purely used as a 1995 * way to distinguish (for KVM's benefit) guest-visible system registers 1996 * from demuxed ones provided to preserve the "no side effects on 1997 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 1998 * visible (to match KVM's encoding); cp==0 will be converted to 1999 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2000 */ 2001 uint8_t cp; 2002 uint8_t crn; 2003 uint8_t crm; 2004 uint8_t opc0; 2005 uint8_t opc1; 2006 uint8_t opc2; 2007 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2008 int state; 2009 /* Register type: ARM_CP_* bits/values */ 2010 int type; 2011 /* Access rights: PL*_[RW] */ 2012 int access; 2013 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2014 int secure; 2015 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2016 * this register was defined: can be used to hand data through to the 2017 * register read/write functions, since they are passed the ARMCPRegInfo*. 2018 */ 2019 void *opaque; 2020 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2021 * fieldoffset is non-zero, the reset value of the register. 2022 */ 2023 uint64_t resetvalue; 2024 /* Offset of the field in CPUARMState for this register. 2025 * 2026 * This is not needed if either: 2027 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2028 * 2. both readfn and writefn are specified 2029 */ 2030 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2031 2032 /* Offsets of the secure and non-secure fields in CPUARMState for the 2033 * register if it is banked. These fields are only used during the static 2034 * registration of a register. During hashing the bank associated 2035 * with a given security state is copied to fieldoffset which is used from 2036 * there on out. 2037 * 2038 * It is expected that register definitions use either fieldoffset or 2039 * bank_fieldoffsets in the definition but not both. It is also expected 2040 * that both bank offsets are set when defining a banked register. This 2041 * use indicates that a register is banked. 2042 */ 2043 ptrdiff_t bank_fieldoffsets[2]; 2044 2045 /* Function for making any access checks for this register in addition to 2046 * those specified by the 'access' permissions bits. If NULL, no extra 2047 * checks required. The access check is performed at runtime, not at 2048 * translate time. 2049 */ 2050 CPAccessFn *accessfn; 2051 /* Function for handling reads of this register. If NULL, then reads 2052 * will be done by loading from the offset into CPUARMState specified 2053 * by fieldoffset. 2054 */ 2055 CPReadFn *readfn; 2056 /* Function for handling writes of this register. If NULL, then writes 2057 * will be done by writing to the offset into CPUARMState specified 2058 * by fieldoffset. 2059 */ 2060 CPWriteFn *writefn; 2061 /* Function for doing a "raw" read; used when we need to copy 2062 * coprocessor state to the kernel for KVM or out for 2063 * migration. This only needs to be provided if there is also a 2064 * readfn and it has side effects (for instance clear-on-read bits). 2065 */ 2066 CPReadFn *raw_readfn; 2067 /* Function for doing a "raw" write; used when we need to copy KVM 2068 * kernel coprocessor state into userspace, or for inbound 2069 * migration. This only needs to be provided if there is also a 2070 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2071 * or similar behaviour. 2072 */ 2073 CPWriteFn *raw_writefn; 2074 /* Function for resetting the register. If NULL, then reset will be done 2075 * by writing resetvalue to the field specified in fieldoffset. If 2076 * fieldoffset is 0 then no reset will be done. 2077 */ 2078 CPResetFn *resetfn; 2079 }; 2080 2081 /* Macros which are lvalues for the field in CPUARMState for the 2082 * ARMCPRegInfo *ri. 2083 */ 2084 #define CPREG_FIELD32(env, ri) \ 2085 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2086 #define CPREG_FIELD64(env, ri) \ 2087 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2088 2089 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2090 2091 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2092 const ARMCPRegInfo *regs, void *opaque); 2093 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2094 const ARMCPRegInfo *regs, void *opaque); 2095 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2096 { 2097 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2098 } 2099 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2100 { 2101 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2102 } 2103 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2104 2105 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2106 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2107 uint64_t value); 2108 /* CPReadFn that can be used for read-as-zero behaviour */ 2109 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2110 2111 /* CPResetFn that does nothing, for use if no reset is required even 2112 * if fieldoffset is non zero. 2113 */ 2114 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2115 2116 /* Return true if this reginfo struct's field in the cpu state struct 2117 * is 64 bits wide. 2118 */ 2119 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2120 { 2121 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2122 } 2123 2124 static inline bool cp_access_ok(int current_el, 2125 const ARMCPRegInfo *ri, int isread) 2126 { 2127 return (ri->access >> ((current_el * 2) + isread)) & 1; 2128 } 2129 2130 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2131 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2132 2133 /** 2134 * write_list_to_cpustate 2135 * @cpu: ARMCPU 2136 * 2137 * For each register listed in the ARMCPU cpreg_indexes list, write 2138 * its value from the cpreg_values list into the ARMCPUState structure. 2139 * This updates TCG's working data structures from KVM data or 2140 * from incoming migration state. 2141 * 2142 * Returns: true if all register values were updated correctly, 2143 * false if some register was unknown or could not be written. 2144 * Note that we do not stop early on failure -- we will attempt 2145 * writing all registers in the list. 2146 */ 2147 bool write_list_to_cpustate(ARMCPU *cpu); 2148 2149 /** 2150 * write_cpustate_to_list: 2151 * @cpu: ARMCPU 2152 * 2153 * For each register listed in the ARMCPU cpreg_indexes list, write 2154 * its value from the ARMCPUState structure into the cpreg_values list. 2155 * This is used to copy info from TCG's working data structures into 2156 * KVM or for outbound migration. 2157 * 2158 * Returns: true if all register values were read correctly, 2159 * false if some register was unknown or could not be read. 2160 * Note that we do not stop early on failure -- we will attempt 2161 * reading all registers in the list. 2162 */ 2163 bool write_cpustate_to_list(ARMCPU *cpu); 2164 2165 #define ARM_CPUID_TI915T 0x54029152 2166 #define ARM_CPUID_TI925T 0x54029252 2167 2168 #if defined(CONFIG_USER_ONLY) 2169 #define TARGET_PAGE_BITS 12 2170 #else 2171 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2172 * have to support 1K tiny pages. 2173 */ 2174 #define TARGET_PAGE_BITS_VARY 2175 #define TARGET_PAGE_BITS_MIN 10 2176 #endif 2177 2178 #if defined(TARGET_AARCH64) 2179 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2180 # define TARGET_VIRT_ADDR_SPACE_BITS 64 2181 #else 2182 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2183 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2184 #endif 2185 2186 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2187 unsigned int target_el) 2188 { 2189 CPUARMState *env = cs->env_ptr; 2190 unsigned int cur_el = arm_current_el(env); 2191 bool secure = arm_is_secure(env); 2192 bool pstate_unmasked; 2193 int8_t unmasked = 0; 2194 2195 /* Don't take exceptions if they target a lower EL. 2196 * This check should catch any exceptions that would not be taken but left 2197 * pending. 2198 */ 2199 if (cur_el > target_el) { 2200 return false; 2201 } 2202 2203 switch (excp_idx) { 2204 case EXCP_FIQ: 2205 pstate_unmasked = !(env->daif & PSTATE_F); 2206 break; 2207 2208 case EXCP_IRQ: 2209 pstate_unmasked = !(env->daif & PSTATE_I); 2210 break; 2211 2212 case EXCP_VFIQ: 2213 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 2214 /* VFIQs are only taken when hypervized and non-secure. */ 2215 return false; 2216 } 2217 return !(env->daif & PSTATE_F); 2218 case EXCP_VIRQ: 2219 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 2220 /* VIRQs are only taken when hypervized and non-secure. */ 2221 return false; 2222 } 2223 return !(env->daif & PSTATE_I); 2224 default: 2225 g_assert_not_reached(); 2226 } 2227 2228 /* Use the target EL, current execution state and SCR/HCR settings to 2229 * determine whether the corresponding CPSR bit is used to mask the 2230 * interrupt. 2231 */ 2232 if ((target_el > cur_el) && (target_el != 1)) { 2233 /* Exceptions targeting a higher EL may not be maskable */ 2234 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2235 /* 64-bit masking rules are simple: exceptions to EL3 2236 * can't be masked, and exceptions to EL2 can only be 2237 * masked from Secure state. The HCR and SCR settings 2238 * don't affect the masking logic, only the interrupt routing. 2239 */ 2240 if (target_el == 3 || !secure) { 2241 unmasked = 1; 2242 } 2243 } else { 2244 /* The old 32-bit-only environment has a more complicated 2245 * masking setup. HCR and SCR bits not only affect interrupt 2246 * routing but also change the behaviour of masking. 2247 */ 2248 bool hcr, scr; 2249 2250 switch (excp_idx) { 2251 case EXCP_FIQ: 2252 /* If FIQs are routed to EL3 or EL2 then there are cases where 2253 * we override the CPSR.F in determining if the exception is 2254 * masked or not. If neither of these are set then we fall back 2255 * to the CPSR.F setting otherwise we further assess the state 2256 * below. 2257 */ 2258 hcr = (env->cp15.hcr_el2 & HCR_FMO); 2259 scr = (env->cp15.scr_el3 & SCR_FIQ); 2260 2261 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2262 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2263 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2264 * when non-secure but only when FIQs are only routed to EL3. 2265 */ 2266 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2267 break; 2268 case EXCP_IRQ: 2269 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2270 * we may override the CPSR.I masking when in non-secure state. 2271 * The SCR.IRQ setting has already been taken into consideration 2272 * when setting the target EL, so it does not have a further 2273 * affect here. 2274 */ 2275 hcr = (env->cp15.hcr_el2 & HCR_IMO); 2276 scr = false; 2277 break; 2278 default: 2279 g_assert_not_reached(); 2280 } 2281 2282 if ((scr || hcr) && !secure) { 2283 unmasked = 1; 2284 } 2285 } 2286 } 2287 2288 /* The PSTATE bits only mask the interrupt if we have not overriden the 2289 * ability above. 2290 */ 2291 return unmasked || pstate_unmasked; 2292 } 2293 2294 #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model) 2295 2296 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2297 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2298 2299 #define cpu_signal_handler cpu_arm_signal_handler 2300 #define cpu_list arm_cpu_list 2301 2302 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2303 * 2304 * If EL3 is 64-bit: 2305 * + NonSecure EL1 & 0 stage 1 2306 * + NonSecure EL1 & 0 stage 2 2307 * + NonSecure EL2 2308 * + Secure EL1 & EL0 2309 * + Secure EL3 2310 * If EL3 is 32-bit: 2311 * + NonSecure PL1 & 0 stage 1 2312 * + NonSecure PL1 & 0 stage 2 2313 * + NonSecure PL2 2314 * + Secure PL0 & PL1 2315 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2316 * 2317 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2318 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2319 * may differ in access permissions even if the VA->PA map is the same 2320 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2321 * translation, which means that we have one mmu_idx that deals with two 2322 * concatenated translation regimes [this sort of combined s1+2 TLB is 2323 * architecturally permitted] 2324 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2325 * handling via the TLB. The only way to do a stage 1 translation without 2326 * the immediate stage 2 translation is via the ATS or AT system insns, 2327 * which can be slow-pathed and always do a page table walk. 2328 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2329 * translation regimes, because they map reasonably well to each other 2330 * and they can't both be active at the same time. 2331 * This gives us the following list of mmu_idx values: 2332 * 2333 * NS EL0 (aka NS PL0) stage 1+2 2334 * NS EL1 (aka NS PL1) stage 1+2 2335 * NS EL2 (aka NS PL2) 2336 * S EL3 (aka S PL1) 2337 * S EL0 (aka S PL0) 2338 * S EL1 (not used if EL3 is 32 bit) 2339 * NS EL0+1 stage 2 2340 * 2341 * (The last of these is an mmu_idx because we want to be able to use the TLB 2342 * for the accesses done as part of a stage 1 page table walk, rather than 2343 * having to walk the stage 2 page table over and over.) 2344 * 2345 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2346 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2347 * NS EL2 if we ever model a Cortex-R52). 2348 * 2349 * M profile CPUs are rather different as they do not have a true MMU. 2350 * They have the following different MMU indexes: 2351 * User 2352 * Privileged 2353 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2354 * Privileged, execution priority negative (ditto) 2355 * If the CPU supports the v8M Security Extension then there are also: 2356 * Secure User 2357 * Secure Privileged 2358 * Secure User, execution priority negative 2359 * Secure Privileged, execution priority negative 2360 * 2361 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2362 * are not quite the same -- different CPU types (most notably M profile 2363 * vs A/R profile) would like to use MMU indexes with different semantics, 2364 * but since we don't ever need to use all of those in a single CPU we 2365 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2366 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2367 * the same for any particular CPU. 2368 * Variables of type ARMMUIdx are always full values, and the core 2369 * index values are in variables of type 'int'. 2370 * 2371 * Our enumeration includes at the end some entries which are not "true" 2372 * mmu_idx values in that they don't have corresponding TLBs and are only 2373 * valid for doing slow path page table walks. 2374 * 2375 * The constant names here are patterned after the general style of the names 2376 * of the AT/ATS operations. 2377 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2378 * For M profile we arrange them to have a bit for priv, a bit for negpri 2379 * and a bit for secure. 2380 */ 2381 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2382 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2383 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2384 2385 /* meanings of the bits for M profile mmu idx values */ 2386 #define ARM_MMU_IDX_M_PRIV 0x1 2387 #define ARM_MMU_IDX_M_NEGPRI 0x2 2388 #define ARM_MMU_IDX_M_S 0x4 2389 2390 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2391 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2392 2393 typedef enum ARMMMUIdx { 2394 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2395 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2396 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2397 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2398 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2399 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2400 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2401 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2402 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2403 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2404 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2405 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2406 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2407 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2408 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2409 /* Indexes below here don't have TLBs and are used only for AT system 2410 * instructions or for the first stage of an S12 page table walk. 2411 */ 2412 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2413 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2414 } ARMMMUIdx; 2415 2416 /* Bit macros for the core-mmu-index values for each index, 2417 * for use when calling tlb_flush_by_mmuidx() and friends. 2418 */ 2419 typedef enum ARMMMUIdxBit { 2420 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2421 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2422 ARMMMUIdxBit_S1E2 = 1 << 2, 2423 ARMMMUIdxBit_S1E3 = 1 << 3, 2424 ARMMMUIdxBit_S1SE0 = 1 << 4, 2425 ARMMMUIdxBit_S1SE1 = 1 << 5, 2426 ARMMMUIdxBit_S2NS = 1 << 6, 2427 ARMMMUIdxBit_MUser = 1 << 0, 2428 ARMMMUIdxBit_MPriv = 1 << 1, 2429 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2430 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2431 ARMMMUIdxBit_MSUser = 1 << 4, 2432 ARMMMUIdxBit_MSPriv = 1 << 5, 2433 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2434 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2435 } ARMMMUIdxBit; 2436 2437 #define MMU_USER_IDX 0 2438 2439 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2440 { 2441 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2442 } 2443 2444 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2445 { 2446 if (arm_feature(env, ARM_FEATURE_M)) { 2447 return mmu_idx | ARM_MMU_IDX_M; 2448 } else { 2449 return mmu_idx | ARM_MMU_IDX_A; 2450 } 2451 } 2452 2453 /* Return the exception level we're running at if this is our mmu_idx */ 2454 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2455 { 2456 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2457 case ARM_MMU_IDX_A: 2458 return mmu_idx & 3; 2459 case ARM_MMU_IDX_M: 2460 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2461 default: 2462 g_assert_not_reached(); 2463 } 2464 } 2465 2466 /* Return the MMU index for a v7M CPU in the specified security and 2467 * privilege state 2468 */ 2469 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2470 bool secstate, 2471 bool priv) 2472 { 2473 ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; 2474 2475 if (priv) { 2476 mmu_idx |= ARM_MMU_IDX_M_PRIV; 2477 } 2478 2479 if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { 2480 mmu_idx |= ARM_MMU_IDX_M_NEGPRI; 2481 } 2482 2483 if (secstate) { 2484 mmu_idx |= ARM_MMU_IDX_M_S; 2485 } 2486 2487 return mmu_idx; 2488 } 2489 2490 /* Return the MMU index for a v7M CPU in the specified security state */ 2491 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, 2492 bool secstate) 2493 { 2494 bool priv = arm_current_el(env) != 0; 2495 2496 return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); 2497 } 2498 2499 /* Determine the current mmu_idx to use for normal loads/stores */ 2500 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2501 { 2502 int el = arm_current_el(env); 2503 2504 if (arm_feature(env, ARM_FEATURE_M)) { 2505 ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); 2506 2507 return arm_to_core_mmu_idx(mmu_idx); 2508 } 2509 2510 if (el < 2 && arm_is_secure_below_el3(env)) { 2511 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); 2512 } 2513 return el; 2514 } 2515 2516 /* Indexes used when registering address spaces with cpu_address_space_init */ 2517 typedef enum ARMASIdx { 2518 ARMASIdx_NS = 0, 2519 ARMASIdx_S = 1, 2520 } ARMASIdx; 2521 2522 /* Return the Exception Level targeted by debug exceptions. */ 2523 static inline int arm_debug_target_el(CPUARMState *env) 2524 { 2525 bool secure = arm_is_secure(env); 2526 bool route_to_el2 = false; 2527 2528 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2529 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2530 env->cp15.mdcr_el2 & (1 << 8); 2531 } 2532 2533 if (route_to_el2) { 2534 return 2; 2535 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2536 !arm_el_is_aa64(env, 3) && secure) { 2537 return 3; 2538 } else { 2539 return 1; 2540 } 2541 } 2542 2543 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2544 { 2545 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2546 * CSSELR is RAZ/WI. 2547 */ 2548 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2549 } 2550 2551 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2552 { 2553 if (arm_is_secure(env)) { 2554 /* MDCR_EL3.SDD disables debug events from Secure state */ 2555 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2556 || arm_current_el(env) == 3) { 2557 return false; 2558 } 2559 } 2560 2561 if (arm_current_el(env) == arm_debug_target_el(env)) { 2562 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2563 || (env->daif & PSTATE_D)) { 2564 return false; 2565 } 2566 } 2567 return true; 2568 } 2569 2570 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2571 { 2572 int el = arm_current_el(env); 2573 2574 if (el == 0 && arm_el_is_aa64(env, 1)) { 2575 return aa64_generate_debug_exceptions(env); 2576 } 2577 2578 if (arm_is_secure(env)) { 2579 int spd; 2580 2581 if (el == 0 && (env->cp15.sder & 1)) { 2582 /* SDER.SUIDEN means debug exceptions from Secure EL0 2583 * are always enabled. Otherwise they are controlled by 2584 * SDCR.SPD like those from other Secure ELs. 2585 */ 2586 return true; 2587 } 2588 2589 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2590 switch (spd) { 2591 case 1: 2592 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2593 case 0: 2594 /* For 0b00 we return true if external secure invasive debug 2595 * is enabled. On real hardware this is controlled by external 2596 * signals to the core. QEMU always permits debug, and behaves 2597 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2598 */ 2599 return true; 2600 case 2: 2601 return false; 2602 case 3: 2603 return true; 2604 } 2605 } 2606 2607 return el != 2; 2608 } 2609 2610 /* Return true if debugging exceptions are currently enabled. 2611 * This corresponds to what in ARM ARM pseudocode would be 2612 * if UsingAArch32() then 2613 * return AArch32.GenerateDebugExceptions() 2614 * else 2615 * return AArch64.GenerateDebugExceptions() 2616 * We choose to push the if() down into this function for clarity, 2617 * since the pseudocode has it at all callsites except for the one in 2618 * CheckSoftwareStep(), where it is elided because both branches would 2619 * always return the same value. 2620 * 2621 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2622 * don't yet implement those exception levels or their associated trap bits. 2623 */ 2624 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2625 { 2626 if (env->aarch64) { 2627 return aa64_generate_debug_exceptions(env); 2628 } else { 2629 return aa32_generate_debug_exceptions(env); 2630 } 2631 } 2632 2633 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2634 * implicitly means this always returns false in pre-v8 CPUs.) 2635 */ 2636 static inline bool arm_singlestep_active(CPUARMState *env) 2637 { 2638 return extract32(env->cp15.mdscr_el1, 0, 1) 2639 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2640 && arm_generate_debug_exceptions(env); 2641 } 2642 2643 static inline bool arm_sctlr_b(CPUARMState *env) 2644 { 2645 return 2646 /* We need not implement SCTLR.ITD in user-mode emulation, so 2647 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2648 * This lets people run BE32 binaries with "-cpu any". 2649 */ 2650 #ifndef CONFIG_USER_ONLY 2651 !arm_feature(env, ARM_FEATURE_V7) && 2652 #endif 2653 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2654 } 2655 2656 /* Return true if the processor is in big-endian mode. */ 2657 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2658 { 2659 int cur_el; 2660 2661 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2662 if (!is_a64(env)) { 2663 return 2664 #ifdef CONFIG_USER_ONLY 2665 /* In system mode, BE32 is modelled in line with the 2666 * architecture (as word-invariant big-endianness), where loads 2667 * and stores are done little endian but from addresses which 2668 * are adjusted by XORing with the appropriate constant. So the 2669 * endianness to use for the raw data access is not affected by 2670 * SCTLR.B. 2671 * In user mode, however, we model BE32 as byte-invariant 2672 * big-endianness (because user-only code cannot tell the 2673 * difference), and so we need to use a data access endianness 2674 * that depends on SCTLR.B. 2675 */ 2676 arm_sctlr_b(env) || 2677 #endif 2678 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2679 } 2680 2681 cur_el = arm_current_el(env); 2682 2683 if (cur_el == 0) { 2684 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2685 } 2686 2687 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2688 } 2689 2690 #include "exec/cpu-all.h" 2691 2692 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2693 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2694 * We put flags which are shared between 32 and 64 bit mode at the top 2695 * of the word, and flags which apply to only one mode at the bottom. 2696 */ 2697 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2698 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2699 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2700 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2701 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2702 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2703 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2704 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2705 /* Target EL if we take a floating-point-disabled exception */ 2706 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2707 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2708 2709 /* Bit usage when in AArch32 state: */ 2710 #define ARM_TBFLAG_THUMB_SHIFT 0 2711 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2712 #define ARM_TBFLAG_VECLEN_SHIFT 1 2713 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2714 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2715 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2716 #define ARM_TBFLAG_VFPEN_SHIFT 7 2717 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2718 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2719 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2720 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2721 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2722 /* We store the bottom two bits of the CPAR as TB flags and handle 2723 * checks on the other bits at runtime 2724 */ 2725 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2726 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2727 /* Indicates whether cp register reads and writes by guest code should access 2728 * the secure or nonsecure bank of banked registers; note that this is not 2729 * the same thing as the current security state of the processor! 2730 */ 2731 #define ARM_TBFLAG_NS_SHIFT 19 2732 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2733 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2734 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2735 /* For M profile only, Handler (ie not Thread) mode */ 2736 #define ARM_TBFLAG_HANDLER_SHIFT 21 2737 #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) 2738 2739 /* Bit usage when in AArch64 state */ 2740 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2741 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2742 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2743 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2744 #define ARM_TBFLAG_SVEEXC_EL_SHIFT 2 2745 #define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT) 2746 #define ARM_TBFLAG_ZCR_LEN_SHIFT 4 2747 #define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT) 2748 2749 /* some convenience accessor macros */ 2750 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2751 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2752 #define ARM_TBFLAG_MMUIDX(F) \ 2753 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2754 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2755 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2756 #define ARM_TBFLAG_PSTATE_SS(F) \ 2757 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2758 #define ARM_TBFLAG_FPEXC_EL(F) \ 2759 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2760 #define ARM_TBFLAG_THUMB(F) \ 2761 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2762 #define ARM_TBFLAG_VECLEN(F) \ 2763 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2764 #define ARM_TBFLAG_VECSTRIDE(F) \ 2765 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2766 #define ARM_TBFLAG_VFPEN(F) \ 2767 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2768 #define ARM_TBFLAG_CONDEXEC(F) \ 2769 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2770 #define ARM_TBFLAG_SCTLR_B(F) \ 2771 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2772 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2773 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2774 #define ARM_TBFLAG_NS(F) \ 2775 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2776 #define ARM_TBFLAG_BE_DATA(F) \ 2777 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2778 #define ARM_TBFLAG_HANDLER(F) \ 2779 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) 2780 #define ARM_TBFLAG_TBI0(F) \ 2781 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2782 #define ARM_TBFLAG_TBI1(F) \ 2783 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2784 #define ARM_TBFLAG_SVEEXC_EL(F) \ 2785 (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT) 2786 #define ARM_TBFLAG_ZCR_LEN(F) \ 2787 (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT) 2788 2789 static inline bool bswap_code(bool sctlr_b) 2790 { 2791 #ifdef CONFIG_USER_ONLY 2792 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2793 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2794 * would also end up as a mixed-endian mode with BE code, LE data. 2795 */ 2796 return 2797 #ifdef TARGET_WORDS_BIGENDIAN 2798 1 ^ 2799 #endif 2800 sctlr_b; 2801 #else 2802 /* All code access in ARM is little endian, and there are no loaders 2803 * doing swaps that need to be reversed 2804 */ 2805 return 0; 2806 #endif 2807 } 2808 2809 #ifdef CONFIG_USER_ONLY 2810 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2811 { 2812 return 2813 #ifdef TARGET_WORDS_BIGENDIAN 2814 1 ^ 2815 #endif 2816 arm_cpu_data_is_big_endian(env); 2817 } 2818 #endif 2819 2820 #ifndef CONFIG_USER_ONLY 2821 /** 2822 * arm_regime_tbi0: 2823 * @env: CPUARMState 2824 * @mmu_idx: MMU index indicating required translation regime 2825 * 2826 * Extracts the TBI0 value from the appropriate TCR for the current EL 2827 * 2828 * Returns: the TBI0 value. 2829 */ 2830 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2831 2832 /** 2833 * arm_regime_tbi1: 2834 * @env: CPUARMState 2835 * @mmu_idx: MMU index indicating required translation regime 2836 * 2837 * Extracts the TBI1 value from the appropriate TCR for the current EL 2838 * 2839 * Returns: the TBI1 value. 2840 */ 2841 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2842 #else 2843 /* We can't handle tagged addresses properly in user-only mode */ 2844 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2845 { 2846 return 0; 2847 } 2848 2849 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2850 { 2851 return 0; 2852 } 2853 #endif 2854 2855 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2856 target_ulong *cs_base, uint32_t *flags); 2857 2858 enum { 2859 QEMU_PSCI_CONDUIT_DISABLED = 0, 2860 QEMU_PSCI_CONDUIT_SMC = 1, 2861 QEMU_PSCI_CONDUIT_HVC = 2, 2862 }; 2863 2864 #ifndef CONFIG_USER_ONLY 2865 /* Return the address space index to use for a memory access */ 2866 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2867 { 2868 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2869 } 2870 2871 /* Return the AddressSpace to use for a memory access 2872 * (which depends on whether the access is S or NS, and whether 2873 * the board gave us a separate AddressSpace for S accesses). 2874 */ 2875 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2876 { 2877 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2878 } 2879 #endif 2880 2881 /** 2882 * arm_register_el_change_hook: 2883 * Register a hook function which will be called back whenever this 2884 * CPU changes exception level or mode. The hook function will be 2885 * passed a pointer to the ARMCPU and the opaque data pointer passed 2886 * to this function when the hook was registered. 2887 * 2888 * Note that we currently only support registering a single hook function, 2889 * and will assert if this function is called twice. 2890 * This facility is intended for the use of the GICv3 emulation. 2891 */ 2892 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 2893 void *opaque); 2894 2895 /** 2896 * arm_get_el_change_hook_opaque: 2897 * Return the opaque data that will be used by the el_change_hook 2898 * for this CPU. 2899 */ 2900 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) 2901 { 2902 return cpu->el_change_hook_opaque; 2903 } 2904 2905 /** 2906 * aa32_vfp_dreg: 2907 * Return a pointer to the Dn register within env in 32-bit mode. 2908 */ 2909 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 2910 { 2911 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 2912 } 2913 2914 /** 2915 * aa32_vfp_qreg: 2916 * Return a pointer to the Qn register within env in 32-bit mode. 2917 */ 2918 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 2919 { 2920 return &env->vfp.zregs[regno].d[0]; 2921 } 2922 2923 /** 2924 * aa64_vfp_qreg: 2925 * Return a pointer to the Qn register within env in 64-bit mode. 2926 */ 2927 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 2928 { 2929 return &env->vfp.zregs[regno].d[0]; 2930 } 2931 2932 #endif 2933