1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 #include "target/arm/multiprocessing.h" 30 31 /* ARM processors have a weak memory model */ 32 #define TCG_GUEST_DEFAULT_MO (0) 33 34 #ifdef TARGET_AARCH64 35 #define KVM_HAVE_MCE_INJECTION 1 36 #endif 37 38 #define EXCP_UDEF 1 /* undefined instruction */ 39 #define EXCP_SWI 2 /* software interrupt */ 40 #define EXCP_PREFETCH_ABORT 3 41 #define EXCP_DATA_ABORT 4 42 #define EXCP_IRQ 5 43 #define EXCP_FIQ 6 44 #define EXCP_BKPT 7 45 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 46 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 47 #define EXCP_HVC 11 /* HyperVisor Call */ 48 #define EXCP_HYP_TRAP 12 49 #define EXCP_SMC 13 /* Secure Monitor Call */ 50 #define EXCP_VIRQ 14 51 #define EXCP_VFIQ 15 52 #define EXCP_SEMIHOST 16 /* semihosting call */ 53 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 54 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 55 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 56 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 57 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 58 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 59 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 60 #define EXCP_VSERR 24 61 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 62 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 63 64 #define ARMV7M_EXCP_RESET 1 65 #define ARMV7M_EXCP_NMI 2 66 #define ARMV7M_EXCP_HARD 3 67 #define ARMV7M_EXCP_MEM 4 68 #define ARMV7M_EXCP_BUS 5 69 #define ARMV7M_EXCP_USAGE 6 70 #define ARMV7M_EXCP_SECURE 7 71 #define ARMV7M_EXCP_SVC 11 72 #define ARMV7M_EXCP_DEBUG 12 73 #define ARMV7M_EXCP_PENDSV 14 74 #define ARMV7M_EXCP_SYSTICK 15 75 76 /* ARM-specific interrupt pending bits. */ 77 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 78 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 79 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 80 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 81 82 /* The usual mapping for an AArch64 system register to its AArch32 83 * counterpart is for the 32 bit world to have access to the lower 84 * half only (with writes leaving the upper half untouched). It's 85 * therefore useful to be able to pass TCG the offset of the least 86 * significant half of a uint64_t struct member. 87 */ 88 #if HOST_BIG_ENDIAN 89 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 90 #define offsetofhigh32(S, M) offsetof(S, M) 91 #else 92 #define offsetoflow32(S, M) offsetof(S, M) 93 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 94 #endif 95 96 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 97 #define ARM_CPU_IRQ 0 98 #define ARM_CPU_FIQ 1 99 #define ARM_CPU_VIRQ 2 100 #define ARM_CPU_VFIQ 3 101 102 /* ARM-specific extra insn start words: 103 * 1: Conditional execution bits 104 * 2: Partial exception syndrome for data aborts 105 */ 106 #define TARGET_INSN_START_EXTRA_WORDS 2 107 108 /* The 2nd extra word holding syndrome info for data aborts does not use 109 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 110 * help the sleb128 encoder do a better job. 111 * When restoring the CPU state, we shift it back up. 112 */ 113 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 114 #define ARM_INSN_START_WORD2_SHIFT 13 115 116 /* We currently assume float and double are IEEE single and double 117 precision respectively. 118 Doing runtime conversions is tricky because VFP registers may contain 119 integer values (eg. as the result of a FTOSI instruction). 120 s<2n> maps to the least significant half of d<n> 121 s<2n+1> maps to the most significant half of d<n> 122 */ 123 124 /** 125 * DynamicGDBXMLInfo: 126 * @desc: Contains the XML descriptions. 127 * @num: Number of the registers in this XML seen by GDB. 128 * @data: A union with data specific to the set of registers 129 * @cpregs_keys: Array that contains the corresponding Key of 130 * a given cpreg with the same order of the cpreg 131 * in the XML description. 132 */ 133 typedef struct DynamicGDBXMLInfo { 134 char *desc; 135 int num; 136 union { 137 struct { 138 uint32_t *keys; 139 } cpregs; 140 } data; 141 } DynamicGDBXMLInfo; 142 143 /* CPU state for each instance of a generic timer (in cp15 c14) */ 144 typedef struct ARMGenericTimer { 145 uint64_t cval; /* Timer CompareValue register */ 146 uint64_t ctl; /* Timer Control register */ 147 } ARMGenericTimer; 148 149 #define GTIMER_PHYS 0 150 #define GTIMER_VIRT 1 151 #define GTIMER_HYP 2 152 #define GTIMER_SEC 3 153 #define GTIMER_HYPVIRT 4 154 #define NUM_GTIMERS 5 155 156 #define VTCR_NSW (1u << 29) 157 #define VTCR_NSA (1u << 30) 158 #define VSTCR_SW VTCR_NSW 159 #define VSTCR_SA VTCR_NSA 160 161 /* Define a maximum sized vector register. 162 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 163 * For 64-bit, this is a 2048-bit SVE register. 164 * 165 * Note that the mapping between S, D, and Q views of the register bank 166 * differs between AArch64 and AArch32. 167 * In AArch32: 168 * Qn = regs[n].d[1]:regs[n].d[0] 169 * Dn = regs[n / 2].d[n & 1] 170 * Sn = regs[n / 4].d[n % 4 / 2], 171 * bits 31..0 for even n, and bits 63..32 for odd n 172 * (and regs[16] to regs[31] are inaccessible) 173 * In AArch64: 174 * Zn = regs[n].d[*] 175 * Qn = regs[n].d[1]:regs[n].d[0] 176 * Dn = regs[n].d[0] 177 * Sn = regs[n].d[0] bits 31..0 178 * Hn = regs[n].d[0] bits 15..0 179 * 180 * This corresponds to the architecturally defined mapping between 181 * the two execution states, and means we do not need to explicitly 182 * map these registers when changing states. 183 * 184 * Align the data for use with TCG host vector operations. 185 */ 186 187 #ifdef TARGET_AARCH64 188 # define ARM_MAX_VQ 16 189 #else 190 # define ARM_MAX_VQ 1 191 #endif 192 193 typedef struct ARMVectorReg { 194 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 195 } ARMVectorReg; 196 197 #ifdef TARGET_AARCH64 198 /* In AArch32 mode, predicate registers do not exist at all. */ 199 typedef struct ARMPredicateReg { 200 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 201 } ARMPredicateReg; 202 203 /* In AArch32 mode, PAC keys do not exist at all. */ 204 typedef struct ARMPACKey { 205 uint64_t lo, hi; 206 } ARMPACKey; 207 #endif 208 209 /* See the commentary above the TBFLAG field definitions. */ 210 typedef struct CPUARMTBFlags { 211 uint32_t flags; 212 target_ulong flags2; 213 } CPUARMTBFlags; 214 215 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 216 217 typedef struct NVICState NVICState; 218 219 typedef struct CPUArchState { 220 /* Regs for current mode. */ 221 uint32_t regs[16]; 222 223 /* 32/64 switch only happens when taking and returning from 224 * exceptions so the overlap semantics are taken care of then 225 * instead of having a complicated union. 226 */ 227 /* Regs for A64 mode. */ 228 uint64_t xregs[32]; 229 uint64_t pc; 230 /* PSTATE isn't an architectural register for ARMv8. However, it is 231 * convenient for us to assemble the underlying state into a 32 bit format 232 * identical to the architectural format used for the SPSR. (This is also 233 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 234 * 'pstate' register are.) Of the PSTATE bits: 235 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 236 * semantics as for AArch32, as described in the comments on each field) 237 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 238 * DAIF (exception masks) are kept in env->daif 239 * BTYPE is kept in env->btype 240 * SM and ZA are kept in env->svcr 241 * all other bits are stored in their correct places in env->pstate 242 */ 243 uint32_t pstate; 244 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 245 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 246 247 /* Cached TBFLAGS state. See below for which bits are included. */ 248 CPUARMTBFlags hflags; 249 250 /* Frequently accessed CPSR bits are stored separately for efficiency. 251 This contains all the other bits. Use cpsr_{read,write} to access 252 the whole CPSR. */ 253 uint32_t uncached_cpsr; 254 uint32_t spsr; 255 256 /* Banked registers. */ 257 uint64_t banked_spsr[8]; 258 uint32_t banked_r13[8]; 259 uint32_t banked_r14[8]; 260 261 /* These hold r8-r12. */ 262 uint32_t usr_regs[5]; 263 uint32_t fiq_regs[5]; 264 265 /* cpsr flag cache for faster execution */ 266 uint32_t CF; /* 0 or 1 */ 267 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 268 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 269 uint32_t ZF; /* Z set if zero. */ 270 uint32_t QF; /* 0 or 1 */ 271 uint32_t GE; /* cpsr[19:16] */ 272 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 273 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 274 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 275 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 276 277 uint64_t elr_el[4]; /* AArch64 exception link regs */ 278 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 279 280 /* System control coprocessor (cp15) */ 281 struct { 282 uint32_t c0_cpuid; 283 union { /* Cache size selection */ 284 struct { 285 uint64_t _unused_csselr0; 286 uint64_t csselr_ns; 287 uint64_t _unused_csselr1; 288 uint64_t csselr_s; 289 }; 290 uint64_t csselr_el[4]; 291 }; 292 union { /* System control register. */ 293 struct { 294 uint64_t _unused_sctlr; 295 uint64_t sctlr_ns; 296 uint64_t hsctlr; 297 uint64_t sctlr_s; 298 }; 299 uint64_t sctlr_el[4]; 300 }; 301 uint64_t vsctlr; /* Virtualization System control register. */ 302 uint64_t cpacr_el1; /* Architectural feature access control register */ 303 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 304 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 305 uint64_t sder; /* Secure debug enable register. */ 306 uint32_t nsacr; /* Non-secure access control register. */ 307 union { /* MMU translation table base 0. */ 308 struct { 309 uint64_t _unused_ttbr0_0; 310 uint64_t ttbr0_ns; 311 uint64_t _unused_ttbr0_1; 312 uint64_t ttbr0_s; 313 }; 314 uint64_t ttbr0_el[4]; 315 }; 316 union { /* MMU translation table base 1. */ 317 struct { 318 uint64_t _unused_ttbr1_0; 319 uint64_t ttbr1_ns; 320 uint64_t _unused_ttbr1_1; 321 uint64_t ttbr1_s; 322 }; 323 uint64_t ttbr1_el[4]; 324 }; 325 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 326 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 327 /* MMU translation table base control. */ 328 uint64_t tcr_el[4]; 329 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 330 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 331 uint32_t c2_data; /* MPU data cacheable bits. */ 332 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 333 union { /* MMU domain access control register 334 * MPU write buffer control. 335 */ 336 struct { 337 uint64_t dacr_ns; 338 uint64_t dacr_s; 339 }; 340 struct { 341 uint64_t dacr32_el2; 342 }; 343 }; 344 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 345 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 346 uint64_t hcr_el2; /* Hypervisor configuration register */ 347 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 348 uint64_t scr_el3; /* Secure configuration register. */ 349 union { /* Fault status registers. */ 350 struct { 351 uint64_t ifsr_ns; 352 uint64_t ifsr_s; 353 }; 354 struct { 355 uint64_t ifsr32_el2; 356 }; 357 }; 358 union { 359 struct { 360 uint64_t _unused_dfsr; 361 uint64_t dfsr_ns; 362 uint64_t hsr; 363 uint64_t dfsr_s; 364 }; 365 uint64_t esr_el[4]; 366 }; 367 uint32_t c6_region[8]; /* MPU base/size registers. */ 368 union { /* Fault address registers. */ 369 struct { 370 uint64_t _unused_far0; 371 #if HOST_BIG_ENDIAN 372 uint32_t ifar_ns; 373 uint32_t dfar_ns; 374 uint32_t ifar_s; 375 uint32_t dfar_s; 376 #else 377 uint32_t dfar_ns; 378 uint32_t ifar_ns; 379 uint32_t dfar_s; 380 uint32_t ifar_s; 381 #endif 382 uint64_t _unused_far3; 383 }; 384 uint64_t far_el[4]; 385 }; 386 uint64_t hpfar_el2; 387 uint64_t hstr_el2; 388 union { /* Translation result. */ 389 struct { 390 uint64_t _unused_par_0; 391 uint64_t par_ns; 392 uint64_t _unused_par_1; 393 uint64_t par_s; 394 }; 395 uint64_t par_el[4]; 396 }; 397 398 uint32_t c9_insn; /* Cache lockdown registers. */ 399 uint32_t c9_data; 400 uint64_t c9_pmcr; /* performance monitor control register */ 401 uint64_t c9_pmcnten; /* perf monitor counter enables */ 402 uint64_t c9_pmovsr; /* perf monitor overflow status */ 403 uint64_t c9_pmuserenr; /* perf monitor user enable */ 404 uint64_t c9_pmselr; /* perf monitor counter selection register */ 405 uint64_t c9_pminten; /* perf monitor interrupt enables */ 406 union { /* Memory attribute redirection */ 407 struct { 408 #if HOST_BIG_ENDIAN 409 uint64_t _unused_mair_0; 410 uint32_t mair1_ns; 411 uint32_t mair0_ns; 412 uint64_t _unused_mair_1; 413 uint32_t mair1_s; 414 uint32_t mair0_s; 415 #else 416 uint64_t _unused_mair_0; 417 uint32_t mair0_ns; 418 uint32_t mair1_ns; 419 uint64_t _unused_mair_1; 420 uint32_t mair0_s; 421 uint32_t mair1_s; 422 #endif 423 }; 424 uint64_t mair_el[4]; 425 }; 426 union { /* vector base address register */ 427 struct { 428 uint64_t _unused_vbar; 429 uint64_t vbar_ns; 430 uint64_t hvbar; 431 uint64_t vbar_s; 432 }; 433 uint64_t vbar_el[4]; 434 }; 435 uint32_t mvbar; /* (monitor) vector base address register */ 436 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 437 struct { /* FCSE PID. */ 438 uint32_t fcseidr_ns; 439 uint32_t fcseidr_s; 440 }; 441 union { /* Context ID. */ 442 struct { 443 uint64_t _unused_contextidr_0; 444 uint64_t contextidr_ns; 445 uint64_t _unused_contextidr_1; 446 uint64_t contextidr_s; 447 }; 448 uint64_t contextidr_el[4]; 449 }; 450 union { /* User RW Thread register. */ 451 struct { 452 uint64_t tpidrurw_ns; 453 uint64_t tpidrprw_ns; 454 uint64_t htpidr; 455 uint64_t _tpidr_el3; 456 }; 457 uint64_t tpidr_el[4]; 458 }; 459 uint64_t tpidr2_el0; 460 /* The secure banks of these registers don't map anywhere */ 461 uint64_t tpidrurw_s; 462 uint64_t tpidrprw_s; 463 uint64_t tpidruro_s; 464 465 union { /* User RO Thread register. */ 466 uint64_t tpidruro_ns; 467 uint64_t tpidrro_el[1]; 468 }; 469 uint64_t c14_cntfrq; /* Counter Frequency register */ 470 uint64_t c14_cntkctl; /* Timer Control register */ 471 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 472 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 473 ARMGenericTimer c14_timer[NUM_GTIMERS]; 474 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 475 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 476 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 477 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 478 uint32_t c15_threadid; /* TI debugger thread-ID. */ 479 uint32_t c15_config_base_address; /* SCU base address. */ 480 uint32_t c15_diagnostic; /* diagnostic register */ 481 uint32_t c15_power_diagnostic; 482 uint32_t c15_power_control; /* power control */ 483 uint64_t dbgbvr[16]; /* breakpoint value registers */ 484 uint64_t dbgbcr[16]; /* breakpoint control registers */ 485 uint64_t dbgwvr[16]; /* watchpoint value registers */ 486 uint64_t dbgwcr[16]; /* watchpoint control registers */ 487 uint64_t dbgclaim; /* DBGCLAIM bits */ 488 uint64_t mdscr_el1; 489 uint64_t oslsr_el1; /* OS Lock Status */ 490 uint64_t osdlr_el1; /* OS DoubleLock status */ 491 uint64_t mdcr_el2; 492 uint64_t mdcr_el3; 493 /* Stores the architectural value of the counter *the last time it was 494 * updated* by pmccntr_op_start. Accesses should always be surrounded 495 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 496 * architecturally-correct value is being read/set. 497 */ 498 uint64_t c15_ccnt; 499 /* Stores the delta between the architectural value and the underlying 500 * cycle count during normal operation. It is used to update c15_ccnt 501 * to be the correct architectural value before accesses. During 502 * accesses, c15_ccnt_delta contains the underlying count being used 503 * for the access, after which it reverts to the delta value in 504 * pmccntr_op_finish. 505 */ 506 uint64_t c15_ccnt_delta; 507 uint64_t c14_pmevcntr[31]; 508 uint64_t c14_pmevcntr_delta[31]; 509 uint64_t c14_pmevtyper[31]; 510 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 511 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 512 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 513 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 514 uint64_t gcr_el1; 515 uint64_t rgsr_el1; 516 517 /* Minimal RAS registers */ 518 uint64_t disr_el1; 519 uint64_t vdisr_el2; 520 uint64_t vsesr_el2; 521 522 /* 523 * Fine-Grained Trap registers. We store these as arrays so the 524 * access checking code doesn't have to manually select 525 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 526 * FEAT_FGT2 will add more elements to these arrays. 527 */ 528 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 529 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 530 uint64_t fgt_exec[1]; /* HFGITR */ 531 532 /* RME registers */ 533 uint64_t gpccr_el3; 534 uint64_t gptbr_el3; 535 uint64_t mfar_el3; 536 537 /* NV2 register */ 538 uint64_t vncr_el2; 539 } cp15; 540 541 struct { 542 /* M profile has up to 4 stack pointers: 543 * a Main Stack Pointer and a Process Stack Pointer for each 544 * of the Secure and Non-Secure states. (If the CPU doesn't support 545 * the security extension then it has only two SPs.) 546 * In QEMU we always store the currently active SP in regs[13], 547 * and the non-active SP for the current security state in 548 * v7m.other_sp. The stack pointers for the inactive security state 549 * are stored in other_ss_msp and other_ss_psp. 550 * switch_v7m_security_state() is responsible for rearranging them 551 * when we change security state. 552 */ 553 uint32_t other_sp; 554 uint32_t other_ss_msp; 555 uint32_t other_ss_psp; 556 uint32_t vecbase[M_REG_NUM_BANKS]; 557 uint32_t basepri[M_REG_NUM_BANKS]; 558 uint32_t control[M_REG_NUM_BANKS]; 559 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 560 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 561 uint32_t hfsr; /* HardFault Status */ 562 uint32_t dfsr; /* Debug Fault Status Register */ 563 uint32_t sfsr; /* Secure Fault Status Register */ 564 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 565 uint32_t bfar; /* BusFault Address */ 566 uint32_t sfar; /* Secure Fault Address Register */ 567 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 568 int exception; 569 uint32_t primask[M_REG_NUM_BANKS]; 570 uint32_t faultmask[M_REG_NUM_BANKS]; 571 uint32_t aircr; /* only holds r/w state if security extn implemented */ 572 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 573 uint32_t csselr[M_REG_NUM_BANKS]; 574 uint32_t scr[M_REG_NUM_BANKS]; 575 uint32_t msplim[M_REG_NUM_BANKS]; 576 uint32_t psplim[M_REG_NUM_BANKS]; 577 uint32_t fpcar[M_REG_NUM_BANKS]; 578 uint32_t fpccr[M_REG_NUM_BANKS]; 579 uint32_t fpdscr[M_REG_NUM_BANKS]; 580 uint32_t cpacr[M_REG_NUM_BANKS]; 581 uint32_t nsacr; 582 uint32_t ltpsize; 583 uint32_t vpr; 584 } v7m; 585 586 /* Information associated with an exception about to be taken: 587 * code which raises an exception must set cs->exception_index and 588 * the relevant parts of this structure; the cpu_do_interrupt function 589 * will then set the guest-visible registers as part of the exception 590 * entry process. 591 */ 592 struct { 593 uint32_t syndrome; /* AArch64 format syndrome register */ 594 uint32_t fsr; /* AArch32 format fault status register info */ 595 uint64_t vaddress; /* virtual addr associated with exception, if any */ 596 uint32_t target_el; /* EL the exception should be targeted for */ 597 /* If we implement EL2 we will also need to store information 598 * about the intermediate physical address for stage 2 faults. 599 */ 600 } exception; 601 602 /* Information associated with an SError */ 603 struct { 604 uint8_t pending; 605 uint8_t has_esr; 606 uint64_t esr; 607 } serror; 608 609 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 610 611 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 612 uint32_t irq_line_state; 613 614 /* Thumb-2 EE state. */ 615 uint32_t teecr; 616 uint32_t teehbr; 617 618 /* VFP coprocessor state. */ 619 struct { 620 ARMVectorReg zregs[32]; 621 622 #ifdef TARGET_AARCH64 623 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 624 #define FFR_PRED_NUM 16 625 ARMPredicateReg pregs[17]; 626 /* Scratch space for aa64 sve predicate temporary. */ 627 ARMPredicateReg preg_tmp; 628 #endif 629 630 /* We store these fpcsr fields separately for convenience. */ 631 uint32_t qc[4] QEMU_ALIGNED(16); 632 int vec_len; 633 int vec_stride; 634 635 uint32_t xregs[16]; 636 637 /* Scratch space for aa32 neon expansion. */ 638 uint32_t scratch[8]; 639 640 /* There are a number of distinct float control structures: 641 * 642 * fp_status: is the "normal" fp status. 643 * fp_status_fp16: used for half-precision calculations 644 * standard_fp_status : the ARM "Standard FPSCR Value" 645 * standard_fp_status_fp16 : used for half-precision 646 * calculations with the ARM "Standard FPSCR Value" 647 * 648 * Half-precision operations are governed by a separate 649 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 650 * status structure to control this. 651 * 652 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 653 * round-to-nearest and is used by any operations (generally 654 * Neon) which the architecture defines as controlled by the 655 * standard FPSCR value rather than the FPSCR. 656 * 657 * The "standard FPSCR but for fp16 ops" is needed because 658 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 659 * using a fixed value for it. 660 * 661 * To avoid having to transfer exception bits around, we simply 662 * say that the FPSCR cumulative exception flags are the logical 663 * OR of the flags in the four fp statuses. This relies on the 664 * only thing which needs to read the exception flags being 665 * an explicit FPSCR read. 666 */ 667 float_status fp_status; 668 float_status fp_status_f16; 669 float_status standard_fp_status; 670 float_status standard_fp_status_f16; 671 672 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 673 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 674 } vfp; 675 676 uint64_t exclusive_addr; 677 uint64_t exclusive_val; 678 /* 679 * Contains the 'val' for the second 64-bit register of LDXP, which comes 680 * from the higher address, not the high part of a complete 128-bit value. 681 * In some ways it might be more convenient to record the exclusive value 682 * as the low and high halves of a 128 bit data value, but the current 683 * semantics of these fields are baked into the migration format. 684 */ 685 uint64_t exclusive_high; 686 687 /* iwMMXt coprocessor state. */ 688 struct { 689 uint64_t regs[16]; 690 uint64_t val; 691 692 uint32_t cregs[16]; 693 } iwmmxt; 694 695 #ifdef TARGET_AARCH64 696 struct { 697 ARMPACKey apia; 698 ARMPACKey apib; 699 ARMPACKey apda; 700 ARMPACKey apdb; 701 ARMPACKey apga; 702 } keys; 703 704 uint64_t scxtnum_el[4]; 705 706 /* 707 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 708 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 709 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 710 * When SVL is less than the architectural maximum, the accessible 711 * storage is restricted, such that if the SVL is X bytes the guest can 712 * see only the bottom X elements of zarray[], and only the least 713 * significant X bytes of each element of the array. (In other words, 714 * the observable part is always square.) 715 * 716 * The ZA storage can also be considered as a set of square tiles of 717 * elements of different sizes. The mapping from tiles to the ZA array 718 * is architecturally defined, such that for tiles of elements of esz 719 * bytes, the Nth row (or "horizontal slice") of tile T is in 720 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 721 * in the ZA storage, because its rows are striped through the ZA array. 722 * 723 * Because this is so large, keep this toward the end of the reset area, 724 * to keep the offsets into the rest of the structure smaller. 725 */ 726 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 727 #endif 728 729 struct CPUBreakpoint *cpu_breakpoint[16]; 730 struct CPUWatchpoint *cpu_watchpoint[16]; 731 732 /* Optional fault info across tlb lookup. */ 733 ARMMMUFaultInfo *tlb_fi; 734 735 /* Fields up to this point are cleared by a CPU reset */ 736 struct {} end_reset_fields; 737 738 /* Fields after this point are preserved across CPU reset. */ 739 740 /* Internal CPU feature flags. */ 741 uint64_t features; 742 743 /* PMSAv7 MPU */ 744 struct { 745 uint32_t *drbar; 746 uint32_t *drsr; 747 uint32_t *dracr; 748 uint32_t rnr[M_REG_NUM_BANKS]; 749 } pmsav7; 750 751 /* PMSAv8 MPU */ 752 struct { 753 /* The PMSAv8 implementation also shares some PMSAv7 config 754 * and state: 755 * pmsav7.rnr (region number register) 756 * pmsav7_dregion (number of configured regions) 757 */ 758 uint32_t *rbar[M_REG_NUM_BANKS]; 759 uint32_t *rlar[M_REG_NUM_BANKS]; 760 uint32_t *hprbar; 761 uint32_t *hprlar; 762 uint32_t mair0[M_REG_NUM_BANKS]; 763 uint32_t mair1[M_REG_NUM_BANKS]; 764 uint32_t hprselr; 765 } pmsav8; 766 767 /* v8M SAU */ 768 struct { 769 uint32_t *rbar; 770 uint32_t *rlar; 771 uint32_t rnr; 772 uint32_t ctrl; 773 } sau; 774 775 #if !defined(CONFIG_USER_ONLY) 776 NVICState *nvic; 777 const struct arm_boot_info *boot_info; 778 /* Store GICv3CPUState to access from this struct */ 779 void *gicv3state; 780 #else /* CONFIG_USER_ONLY */ 781 /* For usermode syscall translation. */ 782 bool eabi; 783 #endif /* CONFIG_USER_ONLY */ 784 785 #ifdef TARGET_TAGGED_ADDRESSES 786 /* Linux syscall tagged address support */ 787 bool tagged_addr_enable; 788 #endif 789 } CPUARMState; 790 791 static inline void set_feature(CPUARMState *env, int feature) 792 { 793 env->features |= 1ULL << feature; 794 } 795 796 static inline void unset_feature(CPUARMState *env, int feature) 797 { 798 env->features &= ~(1ULL << feature); 799 } 800 801 /** 802 * ARMELChangeHookFn: 803 * type of a function which can be registered via arm_register_el_change_hook() 804 * to get callbacks when the CPU changes its exception level or mode. 805 */ 806 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 807 typedef struct ARMELChangeHook ARMELChangeHook; 808 struct ARMELChangeHook { 809 ARMELChangeHookFn *hook; 810 void *opaque; 811 QLIST_ENTRY(ARMELChangeHook) node; 812 }; 813 814 /* These values map onto the return values for 815 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 816 typedef enum ARMPSCIState { 817 PSCI_ON = 0, 818 PSCI_OFF = 1, 819 PSCI_ON_PENDING = 2 820 } ARMPSCIState; 821 822 typedef struct ARMISARegisters ARMISARegisters; 823 824 /* 825 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 826 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 827 * 828 * While processing properties during initialization, corresponding init bits 829 * are set for bits in sve_vq_map that have been set by properties. 830 * 831 * Bits set in supported represent valid vector lengths for the CPU type. 832 */ 833 typedef struct { 834 uint32_t map, init, supported; 835 } ARMVQMap; 836 837 /** 838 * ARMCPU: 839 * @env: #CPUARMState 840 * 841 * An ARM CPU core. 842 */ 843 struct ArchCPU { 844 CPUState parent_obj; 845 846 CPUARMState env; 847 848 /* Coprocessor information */ 849 GHashTable *cp_regs; 850 /* For marshalling (mostly coprocessor) register state between the 851 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 852 * we use these arrays. 853 */ 854 /* List of register indexes managed via these arrays; (full KVM style 855 * 64 bit indexes, not CPRegInfo 32 bit indexes) 856 */ 857 uint64_t *cpreg_indexes; 858 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 859 uint64_t *cpreg_values; 860 /* Length of the indexes, values, reset_values arrays */ 861 int32_t cpreg_array_len; 862 /* These are used only for migration: incoming data arrives in 863 * these fields and is sanity checked in post_load before copying 864 * to the working data structures above. 865 */ 866 uint64_t *cpreg_vmstate_indexes; 867 uint64_t *cpreg_vmstate_values; 868 int32_t cpreg_vmstate_array_len; 869 870 DynamicGDBXMLInfo dyn_sysreg_xml; 871 DynamicGDBXMLInfo dyn_svereg_xml; 872 DynamicGDBXMLInfo dyn_m_systemreg_xml; 873 DynamicGDBXMLInfo dyn_m_secextreg_xml; 874 875 /* Timers used by the generic (architected) timer */ 876 QEMUTimer *gt_timer[NUM_GTIMERS]; 877 /* 878 * Timer used by the PMU. Its state is restored after migration by 879 * pmu_op_finish() - it does not need other handling during migration 880 */ 881 QEMUTimer *pmu_timer; 882 /* GPIO outputs for generic timer */ 883 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 884 /* GPIO output for GICv3 maintenance interrupt signal */ 885 qemu_irq gicv3_maintenance_interrupt; 886 /* GPIO output for the PMU interrupt */ 887 qemu_irq pmu_interrupt; 888 889 /* MemoryRegion to use for secure physical accesses */ 890 MemoryRegion *secure_memory; 891 892 /* MemoryRegion to use for allocation tag accesses */ 893 MemoryRegion *tag_memory; 894 MemoryRegion *secure_tag_memory; 895 896 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 897 Object *idau; 898 899 /* 'compatible' string for this CPU for Linux device trees */ 900 const char *dtb_compatible; 901 902 /* PSCI version for this CPU 903 * Bits[31:16] = Major Version 904 * Bits[15:0] = Minor Version 905 */ 906 uint32_t psci_version; 907 908 /* Current power state, access guarded by BQL */ 909 ARMPSCIState power_state; 910 911 /* CPU has virtualization extension */ 912 bool has_el2; 913 /* CPU has security extension */ 914 bool has_el3; 915 /* CPU has PMU (Performance Monitor Unit) */ 916 bool has_pmu; 917 /* CPU has VFP */ 918 bool has_vfp; 919 /* CPU has 32 VFP registers */ 920 bool has_vfp_d32; 921 /* CPU has Neon */ 922 bool has_neon; 923 /* CPU has M-profile DSP extension */ 924 bool has_dsp; 925 926 /* CPU has memory protection unit */ 927 bool has_mpu; 928 /* PMSAv7 MPU number of supported regions */ 929 uint32_t pmsav7_dregion; 930 /* PMSAv8 MPU number of supported hyp regions */ 931 uint32_t pmsav8r_hdregion; 932 /* v8M SAU number of supported regions */ 933 uint32_t sau_sregion; 934 935 /* PSCI conduit used to invoke PSCI methods 936 * 0 - disabled, 1 - smc, 2 - hvc 937 */ 938 uint32_t psci_conduit; 939 940 /* For v8M, initial value of the Secure VTOR */ 941 uint32_t init_svtor; 942 /* For v8M, initial value of the Non-secure VTOR */ 943 uint32_t init_nsvtor; 944 945 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 946 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 947 */ 948 uint32_t kvm_target; 949 950 #ifdef CONFIG_KVM 951 /* KVM init features for this CPU */ 952 uint32_t kvm_init_features[7]; 953 954 /* KVM CPU state */ 955 956 /* KVM virtual time adjustment */ 957 bool kvm_adjvtime; 958 bool kvm_vtime_dirty; 959 uint64_t kvm_vtime; 960 961 /* KVM steal time */ 962 OnOffAuto kvm_steal_time; 963 #endif /* CONFIG_KVM */ 964 965 /* Uniprocessor system with MP extensions */ 966 bool mp_is_up; 967 968 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 969 * and the probe failed (so we need to report the error in realize) 970 */ 971 bool host_cpu_probe_failed; 972 973 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 974 * register. 975 */ 976 int32_t core_count; 977 978 /* The instance init functions for implementation-specific subclasses 979 * set these fields to specify the implementation-dependent values of 980 * various constant registers and reset values of non-constant 981 * registers. 982 * Some of these might become QOM properties eventually. 983 * Field names match the official register names as defined in the 984 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 985 * is used for reset values of non-constant registers; no reset_ 986 * prefix means a constant register. 987 * Some of these registers are split out into a substructure that 988 * is shared with the translators to control the ISA. 989 * 990 * Note that if you add an ID register to the ARMISARegisters struct 991 * you need to also update the 32-bit and 64-bit versions of the 992 * kvm_arm_get_host_cpu_features() function to correctly populate the 993 * field by reading the value from the KVM vCPU. 994 */ 995 struct ARMISARegisters { 996 uint32_t id_isar0; 997 uint32_t id_isar1; 998 uint32_t id_isar2; 999 uint32_t id_isar3; 1000 uint32_t id_isar4; 1001 uint32_t id_isar5; 1002 uint32_t id_isar6; 1003 uint32_t id_mmfr0; 1004 uint32_t id_mmfr1; 1005 uint32_t id_mmfr2; 1006 uint32_t id_mmfr3; 1007 uint32_t id_mmfr4; 1008 uint32_t id_mmfr5; 1009 uint32_t id_pfr0; 1010 uint32_t id_pfr1; 1011 uint32_t id_pfr2; 1012 uint32_t mvfr0; 1013 uint32_t mvfr1; 1014 uint32_t mvfr2; 1015 uint32_t id_dfr0; 1016 uint32_t id_dfr1; 1017 uint32_t dbgdidr; 1018 uint32_t dbgdevid; 1019 uint32_t dbgdevid1; 1020 uint64_t id_aa64isar0; 1021 uint64_t id_aa64isar1; 1022 uint64_t id_aa64isar2; 1023 uint64_t id_aa64pfr0; 1024 uint64_t id_aa64pfr1; 1025 uint64_t id_aa64mmfr0; 1026 uint64_t id_aa64mmfr1; 1027 uint64_t id_aa64mmfr2; 1028 uint64_t id_aa64dfr0; 1029 uint64_t id_aa64dfr1; 1030 uint64_t id_aa64zfr0; 1031 uint64_t id_aa64smfr0; 1032 uint64_t reset_pmcr_el0; 1033 } isar; 1034 uint64_t midr; 1035 uint32_t revidr; 1036 uint32_t reset_fpsid; 1037 uint64_t ctr; 1038 uint32_t reset_sctlr; 1039 uint64_t pmceid0; 1040 uint64_t pmceid1; 1041 uint32_t id_afr0; 1042 uint64_t id_aa64afr0; 1043 uint64_t id_aa64afr1; 1044 uint64_t clidr; 1045 uint64_t mp_affinity; /* MP ID without feature bits */ 1046 /* The elements of this array are the CCSIDR values for each cache, 1047 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1048 */ 1049 uint64_t ccsidr[16]; 1050 uint64_t reset_cbar; 1051 uint32_t reset_auxcr; 1052 bool reset_hivecs; 1053 uint8_t reset_l0gptsz; 1054 1055 /* 1056 * Intermediate values used during property parsing. 1057 * Once finalized, the values should be read from ID_AA64*. 1058 */ 1059 bool prop_pauth; 1060 bool prop_pauth_impdef; 1061 bool prop_pauth_qarma3; 1062 bool prop_lpa2; 1063 1064 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1065 uint8_t dcz_blocksize; 1066 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1067 uint8_t gm_blocksize; 1068 1069 uint64_t rvbar_prop; /* Property/input signals. */ 1070 1071 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1072 int gic_num_lrs; /* number of list registers */ 1073 int gic_vpribits; /* number of virtual priority bits */ 1074 int gic_vprebits; /* number of virtual preemption bits */ 1075 int gic_pribits; /* number of physical priority bits */ 1076 1077 /* Whether the cfgend input is high (i.e. this CPU should reset into 1078 * big-endian mode). This setting isn't used directly: instead it modifies 1079 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1080 * architecture version. 1081 */ 1082 bool cfgend; 1083 1084 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1085 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1086 1087 int32_t node_id; /* NUMA node this CPU belongs to */ 1088 1089 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1090 uint8_t device_irq_level; 1091 1092 /* Used to set the maximum vector length the cpu will support. */ 1093 uint32_t sve_max_vq; 1094 1095 #ifdef CONFIG_USER_ONLY 1096 /* Used to set the default vector length at process start. */ 1097 uint32_t sve_default_vq; 1098 uint32_t sme_default_vq; 1099 #endif 1100 1101 ARMVQMap sve_vq; 1102 ARMVQMap sme_vq; 1103 1104 /* Generic timer counter frequency, in Hz */ 1105 uint64_t gt_cntfrq_hz; 1106 }; 1107 1108 typedef struct ARMCPUInfo { 1109 const char *name; 1110 void (*initfn)(Object *obj); 1111 void (*class_init)(ObjectClass *oc, void *data); 1112 } ARMCPUInfo; 1113 1114 /** 1115 * ARMCPUClass: 1116 * @parent_realize: The parent class' realize handler. 1117 * @parent_phases: The parent class' reset phase handlers. 1118 * 1119 * An ARM CPU model. 1120 */ 1121 struct ARMCPUClass { 1122 CPUClass parent_class; 1123 1124 const ARMCPUInfo *info; 1125 DeviceRealize parent_realize; 1126 ResettablePhases parent_phases; 1127 }; 1128 1129 struct AArch64CPUClass { 1130 ARMCPUClass parent_class; 1131 }; 1132 1133 /* Callback functions for the generic timer's timers. */ 1134 void arm_gt_ptimer_cb(void *opaque); 1135 void arm_gt_vtimer_cb(void *opaque); 1136 void arm_gt_htimer_cb(void *opaque); 1137 void arm_gt_stimer_cb(void *opaque); 1138 void arm_gt_hvtimer_cb(void *opaque); 1139 1140 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1141 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1142 1143 void arm_cpu_post_init(Object *obj); 1144 1145 #define ARM_AFF0_SHIFT 0 1146 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1147 #define ARM_AFF1_SHIFT 8 1148 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1149 #define ARM_AFF2_SHIFT 16 1150 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1151 #define ARM_AFF3_SHIFT 32 1152 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1153 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1154 1155 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1156 #define ARM64_AFFINITY_MASK \ 1157 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1158 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1159 1160 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1161 1162 #ifndef CONFIG_USER_ONLY 1163 extern const VMStateDescription vmstate_arm_cpu; 1164 1165 void arm_cpu_do_interrupt(CPUState *cpu); 1166 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1167 1168 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1169 MemTxAttrs *attrs); 1170 #endif /* !CONFIG_USER_ONLY */ 1171 1172 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1173 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1174 1175 /* Returns the dynamically generated XML for the gdb stub. 1176 * Returns a pointer to the XML contents for the specified XML file or NULL 1177 * if the XML name doesn't match the predefined one. 1178 */ 1179 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1180 1181 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1182 int cpuid, DumpState *s); 1183 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1184 int cpuid, DumpState *s); 1185 1186 /** 1187 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1188 * @cpu: CPU (which must have been freshly reset) 1189 * @target_el: exception level to put the CPU into 1190 * @secure: whether to put the CPU in secure state 1191 * 1192 * When QEMU is directly running a guest kernel at a lower level than 1193 * EL3 it implicitly emulates some aspects of the guest firmware. 1194 * This includes that on reset we need to configure the parts of the 1195 * CPU corresponding to EL3 so that the real guest code can run at its 1196 * lower exception level. This function does that post-reset CPU setup, 1197 * for when we do direct boot of a guest kernel, and for when we 1198 * emulate PSCI and similar firmware interfaces starting a CPU at a 1199 * lower exception level. 1200 * 1201 * @target_el must be an EL implemented by the CPU between 1 and 3. 1202 * We do not support dropping into a Secure EL other than 3. 1203 * 1204 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1205 */ 1206 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1207 1208 #ifdef TARGET_AARCH64 1209 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1210 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1211 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1212 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1213 int new_el, bool el0_a64); 1214 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1215 1216 /* 1217 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1218 * The byte at offset i from the start of the in-memory representation contains 1219 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1220 * lowest offsets are stored in the lowest memory addresses, then that nearly 1221 * matches QEMU's representation, which is to use an array of host-endian 1222 * uint64_t's, where the lower offsets are at the lower indices. To complete 1223 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1224 */ 1225 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1226 { 1227 #if HOST_BIG_ENDIAN 1228 int i; 1229 1230 for (i = 0; i < nr; ++i) { 1231 dst[i] = bswap64(src[i]); 1232 } 1233 1234 return dst; 1235 #else 1236 return src; 1237 #endif 1238 } 1239 1240 #else 1241 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1242 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1243 int n, bool a) 1244 { } 1245 #endif 1246 1247 void aarch64_sync_32_to_64(CPUARMState *env); 1248 void aarch64_sync_64_to_32(CPUARMState *env); 1249 1250 int fp_exception_el(CPUARMState *env, int cur_el); 1251 int sve_exception_el(CPUARMState *env, int cur_el); 1252 int sme_exception_el(CPUARMState *env, int cur_el); 1253 1254 /** 1255 * sve_vqm1_for_el_sm: 1256 * @env: CPUARMState 1257 * @el: exception level 1258 * @sm: streaming mode 1259 * 1260 * Compute the current vector length for @el & @sm, in units of 1261 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1262 * If @sm, compute for SVL, otherwise NVL. 1263 */ 1264 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1265 1266 /* Likewise, but using @sm = PSTATE.SM. */ 1267 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1268 1269 static inline bool is_a64(CPUARMState *env) 1270 { 1271 return env->aarch64; 1272 } 1273 1274 /** 1275 * pmu_op_start/finish 1276 * @env: CPUARMState 1277 * 1278 * Convert all PMU counters between their delta form (the typical mode when 1279 * they are enabled) and the guest-visible values. These two calls must 1280 * surround any action which might affect the counters. 1281 */ 1282 void pmu_op_start(CPUARMState *env); 1283 void pmu_op_finish(CPUARMState *env); 1284 1285 /* 1286 * Called when a PMU counter is due to overflow 1287 */ 1288 void arm_pmu_timer_cb(void *opaque); 1289 1290 /** 1291 * Functions to register as EL change hooks for PMU mode filtering 1292 */ 1293 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1294 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1295 1296 /* 1297 * pmu_init 1298 * @cpu: ARMCPU 1299 * 1300 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1301 * for the current configuration 1302 */ 1303 void pmu_init(ARMCPU *cpu); 1304 1305 /* SCTLR bit meanings. Several bits have been reused in newer 1306 * versions of the architecture; in that case we define constants 1307 * for both old and new bit meanings. Code which tests against those 1308 * bits should probably check or otherwise arrange that the CPU 1309 * is the architectural version it expects. 1310 */ 1311 #define SCTLR_M (1U << 0) 1312 #define SCTLR_A (1U << 1) 1313 #define SCTLR_C (1U << 2) 1314 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1315 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1316 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1317 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1318 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1319 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1320 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1321 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1322 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1323 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1324 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1325 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1326 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1327 #define SCTLR_SED (1U << 8) /* v8 onward */ 1328 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1329 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1330 #define SCTLR_F (1U << 10) /* up to v6 */ 1331 #define SCTLR_SW (1U << 10) /* v7 */ 1332 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1333 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1334 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1335 #define SCTLR_I (1U << 12) 1336 #define SCTLR_V (1U << 13) /* AArch32 only */ 1337 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1338 #define SCTLR_RR (1U << 14) /* up to v7 */ 1339 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1340 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1341 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1342 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1343 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1344 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1345 #define SCTLR_BR (1U << 17) /* PMSA only */ 1346 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1347 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1348 #define SCTLR_WXN (1U << 19) 1349 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1350 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1351 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1352 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1353 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1354 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1355 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1356 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1357 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1358 #define SCTLR_VE (1U << 24) /* up to v7 */ 1359 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1360 #define SCTLR_EE (1U << 25) 1361 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1362 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1363 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1364 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1365 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1366 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1367 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1368 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1369 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1370 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1371 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1372 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1373 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1374 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1375 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1376 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1377 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1378 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1379 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1380 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1381 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1382 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1383 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1384 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1385 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1386 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1387 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1388 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1389 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1390 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1391 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1392 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1393 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1394 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1395 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1396 1397 /* Bit definitions for CPACR (AArch32 only) */ 1398 FIELD(CPACR, CP10, 20, 2) 1399 FIELD(CPACR, CP11, 22, 2) 1400 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1401 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1402 FIELD(CPACR, ASEDIS, 31, 1) 1403 1404 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1405 FIELD(CPACR_EL1, ZEN, 16, 2) 1406 FIELD(CPACR_EL1, FPEN, 20, 2) 1407 FIELD(CPACR_EL1, SMEN, 24, 2) 1408 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1409 1410 /* Bit definitions for HCPTR (AArch32 only) */ 1411 FIELD(HCPTR, TCP10, 10, 1) 1412 FIELD(HCPTR, TCP11, 11, 1) 1413 FIELD(HCPTR, TASE, 15, 1) 1414 FIELD(HCPTR, TTA, 20, 1) 1415 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1416 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1417 1418 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1419 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1420 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1421 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1422 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1423 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1424 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1425 FIELD(CPTR_EL2, TTA, 28, 1) 1426 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1427 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1428 1429 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1430 FIELD(CPTR_EL3, EZ, 8, 1) 1431 FIELD(CPTR_EL3, TFP, 10, 1) 1432 FIELD(CPTR_EL3, ESM, 12, 1) 1433 FIELD(CPTR_EL3, TTA, 20, 1) 1434 FIELD(CPTR_EL3, TAM, 30, 1) 1435 FIELD(CPTR_EL3, TCPAC, 31, 1) 1436 1437 #define MDCR_MTPME (1U << 28) 1438 #define MDCR_TDCC (1U << 27) 1439 #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ 1440 #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ 1441 #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ 1442 #define MDCR_EPMAD (1U << 21) 1443 #define MDCR_EDAD (1U << 20) 1444 #define MDCR_TTRF (1U << 19) 1445 #define MDCR_STE (1U << 18) /* MDCR_EL3 */ 1446 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1447 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1448 #define MDCR_SDD (1U << 16) 1449 #define MDCR_SPD (3U << 14) 1450 #define MDCR_TDRA (1U << 11) 1451 #define MDCR_TDOSA (1U << 10) 1452 #define MDCR_TDA (1U << 9) 1453 #define MDCR_TDE (1U << 8) 1454 #define MDCR_HPME (1U << 7) 1455 #define MDCR_TPM (1U << 6) 1456 #define MDCR_TPMCR (1U << 5) 1457 #define MDCR_HPMN (0x1fU) 1458 1459 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1460 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ 1461 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ 1462 MDCR_STE | MDCR_SPME | MDCR_SPD) 1463 1464 #define CPSR_M (0x1fU) 1465 #define CPSR_T (1U << 5) 1466 #define CPSR_F (1U << 6) 1467 #define CPSR_I (1U << 7) 1468 #define CPSR_A (1U << 8) 1469 #define CPSR_E (1U << 9) 1470 #define CPSR_IT_2_7 (0xfc00U) 1471 #define CPSR_GE (0xfU << 16) 1472 #define CPSR_IL (1U << 20) 1473 #define CPSR_DIT (1U << 21) 1474 #define CPSR_PAN (1U << 22) 1475 #define CPSR_SSBS (1U << 23) 1476 #define CPSR_J (1U << 24) 1477 #define CPSR_IT_0_1 (3U << 25) 1478 #define CPSR_Q (1U << 27) 1479 #define CPSR_V (1U << 28) 1480 #define CPSR_C (1U << 29) 1481 #define CPSR_Z (1U << 30) 1482 #define CPSR_N (1U << 31) 1483 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1484 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1485 1486 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1487 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1488 | CPSR_NZCV) 1489 /* Bits writable in user mode. */ 1490 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1491 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1492 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1493 1494 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1495 #define XPSR_EXCP 0x1ffU 1496 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1497 #define XPSR_IT_2_7 CPSR_IT_2_7 1498 #define XPSR_GE CPSR_GE 1499 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1500 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1501 #define XPSR_IT_0_1 CPSR_IT_0_1 1502 #define XPSR_Q CPSR_Q 1503 #define XPSR_V CPSR_V 1504 #define XPSR_C CPSR_C 1505 #define XPSR_Z CPSR_Z 1506 #define XPSR_N CPSR_N 1507 #define XPSR_NZCV CPSR_NZCV 1508 #define XPSR_IT CPSR_IT 1509 1510 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1511 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1512 #define TTBCR_PD0 (1U << 4) 1513 #define TTBCR_PD1 (1U << 5) 1514 #define TTBCR_EPD0 (1U << 7) 1515 #define TTBCR_IRGN0 (3U << 8) 1516 #define TTBCR_ORGN0 (3U << 10) 1517 #define TTBCR_SH0 (3U << 12) 1518 #define TTBCR_T1SZ (3U << 16) 1519 #define TTBCR_A1 (1U << 22) 1520 #define TTBCR_EPD1 (1U << 23) 1521 #define TTBCR_IRGN1 (3U << 24) 1522 #define TTBCR_ORGN1 (3U << 26) 1523 #define TTBCR_SH1 (1U << 28) 1524 #define TTBCR_EAE (1U << 31) 1525 1526 FIELD(VTCR, T0SZ, 0, 6) 1527 FIELD(VTCR, SL0, 6, 2) 1528 FIELD(VTCR, IRGN0, 8, 2) 1529 FIELD(VTCR, ORGN0, 10, 2) 1530 FIELD(VTCR, SH0, 12, 2) 1531 FIELD(VTCR, TG0, 14, 2) 1532 FIELD(VTCR, PS, 16, 3) 1533 FIELD(VTCR, VS, 19, 1) 1534 FIELD(VTCR, HA, 21, 1) 1535 FIELD(VTCR, HD, 22, 1) 1536 FIELD(VTCR, HWU59, 25, 1) 1537 FIELD(VTCR, HWU60, 26, 1) 1538 FIELD(VTCR, HWU61, 27, 1) 1539 FIELD(VTCR, HWU62, 28, 1) 1540 FIELD(VTCR, NSW, 29, 1) 1541 FIELD(VTCR, NSA, 30, 1) 1542 FIELD(VTCR, DS, 32, 1) 1543 FIELD(VTCR, SL2, 33, 1) 1544 1545 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1546 * Only these are valid when in AArch64 mode; in 1547 * AArch32 mode SPSRs are basically CPSR-format. 1548 */ 1549 #define PSTATE_SP (1U) 1550 #define PSTATE_M (0xFU) 1551 #define PSTATE_nRW (1U << 4) 1552 #define PSTATE_F (1U << 6) 1553 #define PSTATE_I (1U << 7) 1554 #define PSTATE_A (1U << 8) 1555 #define PSTATE_D (1U << 9) 1556 #define PSTATE_BTYPE (3U << 10) 1557 #define PSTATE_SSBS (1U << 12) 1558 #define PSTATE_IL (1U << 20) 1559 #define PSTATE_SS (1U << 21) 1560 #define PSTATE_PAN (1U << 22) 1561 #define PSTATE_UAO (1U << 23) 1562 #define PSTATE_DIT (1U << 24) 1563 #define PSTATE_TCO (1U << 25) 1564 #define PSTATE_V (1U << 28) 1565 #define PSTATE_C (1U << 29) 1566 #define PSTATE_Z (1U << 30) 1567 #define PSTATE_N (1U << 31) 1568 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1569 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1570 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1571 /* Mode values for AArch64 */ 1572 #define PSTATE_MODE_EL3h 13 1573 #define PSTATE_MODE_EL3t 12 1574 #define PSTATE_MODE_EL2h 9 1575 #define PSTATE_MODE_EL2t 8 1576 #define PSTATE_MODE_EL1h 5 1577 #define PSTATE_MODE_EL1t 4 1578 #define PSTATE_MODE_EL0t 0 1579 1580 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1581 FIELD(SVCR, SM, 0, 1) 1582 FIELD(SVCR, ZA, 1, 1) 1583 1584 /* Fields for SMCR_ELx. */ 1585 FIELD(SMCR, LEN, 0, 4) 1586 FIELD(SMCR, FA64, 31, 1) 1587 1588 /* Write a new value to v7m.exception, thus transitioning into or out 1589 * of Handler mode; this may result in a change of active stack pointer. 1590 */ 1591 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1592 1593 /* Map EL and handler into a PSTATE_MODE. */ 1594 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1595 { 1596 return (el << 2) | handler; 1597 } 1598 1599 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1600 * interprocessing, so we don't attempt to sync with the cpsr state used by 1601 * the 32 bit decoder. 1602 */ 1603 static inline uint32_t pstate_read(CPUARMState *env) 1604 { 1605 int ZF; 1606 1607 ZF = (env->ZF == 0); 1608 return (env->NF & 0x80000000) | (ZF << 30) 1609 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1610 | env->pstate | env->daif | (env->btype << 10); 1611 } 1612 1613 static inline void pstate_write(CPUARMState *env, uint32_t val) 1614 { 1615 env->ZF = (~val) & PSTATE_Z; 1616 env->NF = val; 1617 env->CF = (val >> 29) & 1; 1618 env->VF = (val << 3) & 0x80000000; 1619 env->daif = val & PSTATE_DAIF; 1620 env->btype = (val >> 10) & 3; 1621 env->pstate = val & ~CACHED_PSTATE_BITS; 1622 } 1623 1624 /* Return the current CPSR value. */ 1625 uint32_t cpsr_read(CPUARMState *env); 1626 1627 typedef enum CPSRWriteType { 1628 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1629 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1630 CPSRWriteRaw = 2, 1631 /* trust values, no reg bank switch, no hflags rebuild */ 1632 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1633 } CPSRWriteType; 1634 1635 /* 1636 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1637 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1638 * correspond to TB flags bits cached in the hflags, unless @write_type 1639 * is CPSRWriteRaw. 1640 */ 1641 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1642 CPSRWriteType write_type); 1643 1644 /* Return the current xPSR value. */ 1645 static inline uint32_t xpsr_read(CPUARMState *env) 1646 { 1647 int ZF; 1648 ZF = (env->ZF == 0); 1649 return (env->NF & 0x80000000) | (ZF << 30) 1650 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1651 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1652 | ((env->condexec_bits & 0xfc) << 8) 1653 | (env->GE << 16) 1654 | env->v7m.exception; 1655 } 1656 1657 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1658 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1659 { 1660 if (mask & XPSR_NZCV) { 1661 env->ZF = (~val) & XPSR_Z; 1662 env->NF = val; 1663 env->CF = (val >> 29) & 1; 1664 env->VF = (val << 3) & 0x80000000; 1665 } 1666 if (mask & XPSR_Q) { 1667 env->QF = ((val & XPSR_Q) != 0); 1668 } 1669 if (mask & XPSR_GE) { 1670 env->GE = (val & XPSR_GE) >> 16; 1671 } 1672 #ifndef CONFIG_USER_ONLY 1673 if (mask & XPSR_T) { 1674 env->thumb = ((val & XPSR_T) != 0); 1675 } 1676 if (mask & XPSR_IT_0_1) { 1677 env->condexec_bits &= ~3; 1678 env->condexec_bits |= (val >> 25) & 3; 1679 } 1680 if (mask & XPSR_IT_2_7) { 1681 env->condexec_bits &= 3; 1682 env->condexec_bits |= (val >> 8) & 0xfc; 1683 } 1684 if (mask & XPSR_EXCP) { 1685 /* Note that this only happens on exception exit */ 1686 write_v7m_exception(env, val & XPSR_EXCP); 1687 } 1688 #endif 1689 } 1690 1691 #define HCR_VM (1ULL << 0) 1692 #define HCR_SWIO (1ULL << 1) 1693 #define HCR_PTW (1ULL << 2) 1694 #define HCR_FMO (1ULL << 3) 1695 #define HCR_IMO (1ULL << 4) 1696 #define HCR_AMO (1ULL << 5) 1697 #define HCR_VF (1ULL << 6) 1698 #define HCR_VI (1ULL << 7) 1699 #define HCR_VSE (1ULL << 8) 1700 #define HCR_FB (1ULL << 9) 1701 #define HCR_BSU_MASK (3ULL << 10) 1702 #define HCR_DC (1ULL << 12) 1703 #define HCR_TWI (1ULL << 13) 1704 #define HCR_TWE (1ULL << 14) 1705 #define HCR_TID0 (1ULL << 15) 1706 #define HCR_TID1 (1ULL << 16) 1707 #define HCR_TID2 (1ULL << 17) 1708 #define HCR_TID3 (1ULL << 18) 1709 #define HCR_TSC (1ULL << 19) 1710 #define HCR_TIDCP (1ULL << 20) 1711 #define HCR_TACR (1ULL << 21) 1712 #define HCR_TSW (1ULL << 22) 1713 #define HCR_TPCP (1ULL << 23) 1714 #define HCR_TPU (1ULL << 24) 1715 #define HCR_TTLB (1ULL << 25) 1716 #define HCR_TVM (1ULL << 26) 1717 #define HCR_TGE (1ULL << 27) 1718 #define HCR_TDZ (1ULL << 28) 1719 #define HCR_HCD (1ULL << 29) 1720 #define HCR_TRVM (1ULL << 30) 1721 #define HCR_RW (1ULL << 31) 1722 #define HCR_CD (1ULL << 32) 1723 #define HCR_ID (1ULL << 33) 1724 #define HCR_E2H (1ULL << 34) 1725 #define HCR_TLOR (1ULL << 35) 1726 #define HCR_TERR (1ULL << 36) 1727 #define HCR_TEA (1ULL << 37) 1728 #define HCR_MIOCNCE (1ULL << 38) 1729 #define HCR_TME (1ULL << 39) 1730 #define HCR_APK (1ULL << 40) 1731 #define HCR_API (1ULL << 41) 1732 #define HCR_NV (1ULL << 42) 1733 #define HCR_NV1 (1ULL << 43) 1734 #define HCR_AT (1ULL << 44) 1735 #define HCR_NV2 (1ULL << 45) 1736 #define HCR_FWB (1ULL << 46) 1737 #define HCR_FIEN (1ULL << 47) 1738 #define HCR_GPF (1ULL << 48) 1739 #define HCR_TID4 (1ULL << 49) 1740 #define HCR_TICAB (1ULL << 50) 1741 #define HCR_AMVOFFEN (1ULL << 51) 1742 #define HCR_TOCU (1ULL << 52) 1743 #define HCR_ENSCXT (1ULL << 53) 1744 #define HCR_TTLBIS (1ULL << 54) 1745 #define HCR_TTLBOS (1ULL << 55) 1746 #define HCR_ATA (1ULL << 56) 1747 #define HCR_DCT (1ULL << 57) 1748 #define HCR_TID5 (1ULL << 58) 1749 #define HCR_TWEDEN (1ULL << 59) 1750 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1751 1752 #define HCRX_ENAS0 (1ULL << 0) 1753 #define HCRX_ENALS (1ULL << 1) 1754 #define HCRX_ENASR (1ULL << 2) 1755 #define HCRX_FNXS (1ULL << 3) 1756 #define HCRX_FGTNXS (1ULL << 4) 1757 #define HCRX_SMPME (1ULL << 5) 1758 #define HCRX_TALLINT (1ULL << 6) 1759 #define HCRX_VINMI (1ULL << 7) 1760 #define HCRX_VFNMI (1ULL << 8) 1761 #define HCRX_CMOW (1ULL << 9) 1762 #define HCRX_MCE2 (1ULL << 10) 1763 #define HCRX_MSCEN (1ULL << 11) 1764 1765 #define HPFAR_NS (1ULL << 63) 1766 1767 #define SCR_NS (1ULL << 0) 1768 #define SCR_IRQ (1ULL << 1) 1769 #define SCR_FIQ (1ULL << 2) 1770 #define SCR_EA (1ULL << 3) 1771 #define SCR_FW (1ULL << 4) 1772 #define SCR_AW (1ULL << 5) 1773 #define SCR_NET (1ULL << 6) 1774 #define SCR_SMD (1ULL << 7) 1775 #define SCR_HCE (1ULL << 8) 1776 #define SCR_SIF (1ULL << 9) 1777 #define SCR_RW (1ULL << 10) 1778 #define SCR_ST (1ULL << 11) 1779 #define SCR_TWI (1ULL << 12) 1780 #define SCR_TWE (1ULL << 13) 1781 #define SCR_TLOR (1ULL << 14) 1782 #define SCR_TERR (1ULL << 15) 1783 #define SCR_APK (1ULL << 16) 1784 #define SCR_API (1ULL << 17) 1785 #define SCR_EEL2 (1ULL << 18) 1786 #define SCR_EASE (1ULL << 19) 1787 #define SCR_NMEA (1ULL << 20) 1788 #define SCR_FIEN (1ULL << 21) 1789 #define SCR_ENSCXT (1ULL << 25) 1790 #define SCR_ATA (1ULL << 26) 1791 #define SCR_FGTEN (1ULL << 27) 1792 #define SCR_ECVEN (1ULL << 28) 1793 #define SCR_TWEDEN (1ULL << 29) 1794 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1795 #define SCR_TME (1ULL << 34) 1796 #define SCR_AMVOFFEN (1ULL << 35) 1797 #define SCR_ENAS0 (1ULL << 36) 1798 #define SCR_ADEN (1ULL << 37) 1799 #define SCR_HXEN (1ULL << 38) 1800 #define SCR_TRNDR (1ULL << 40) 1801 #define SCR_ENTP2 (1ULL << 41) 1802 #define SCR_GPF (1ULL << 48) 1803 #define SCR_NSE (1ULL << 62) 1804 1805 #define HSTR_TTEE (1 << 16) 1806 #define HSTR_TJDBX (1 << 17) 1807 1808 #define CNTHCTL_CNTVMASK (1 << 18) 1809 #define CNTHCTL_CNTPMASK (1 << 19) 1810 1811 /* Return the current FPSCR value. */ 1812 uint32_t vfp_get_fpscr(CPUARMState *env); 1813 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1814 1815 /* FPCR, Floating Point Control Register 1816 * FPSR, Floating Poiht Status Register 1817 * 1818 * For A64 the FPSCR is split into two logically distinct registers, 1819 * FPCR and FPSR. However since they still use non-overlapping bits 1820 * we store the underlying state in fpscr and just mask on read/write. 1821 */ 1822 #define FPSR_MASK 0xf800009f 1823 #define FPCR_MASK 0x07ff9f00 1824 1825 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1826 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1827 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1828 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1829 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1830 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1831 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1832 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1833 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1834 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1835 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1836 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1837 #define FPCR_V (1 << 28) /* FP overflow flag */ 1838 #define FPCR_C (1 << 29) /* FP carry flag */ 1839 #define FPCR_Z (1 << 30) /* FP zero flag */ 1840 #define FPCR_N (1 << 31) /* FP negative flag */ 1841 1842 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1843 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1844 #define FPCR_LTPSIZE_LENGTH 3 1845 1846 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1847 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1848 1849 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1850 { 1851 return vfp_get_fpscr(env) & FPSR_MASK; 1852 } 1853 1854 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1855 { 1856 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1857 vfp_set_fpscr(env, new_fpscr); 1858 } 1859 1860 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1861 { 1862 return vfp_get_fpscr(env) & FPCR_MASK; 1863 } 1864 1865 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1866 { 1867 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1868 vfp_set_fpscr(env, new_fpscr); 1869 } 1870 1871 enum arm_cpu_mode { 1872 ARM_CPU_MODE_USR = 0x10, 1873 ARM_CPU_MODE_FIQ = 0x11, 1874 ARM_CPU_MODE_IRQ = 0x12, 1875 ARM_CPU_MODE_SVC = 0x13, 1876 ARM_CPU_MODE_MON = 0x16, 1877 ARM_CPU_MODE_ABT = 0x17, 1878 ARM_CPU_MODE_HYP = 0x1a, 1879 ARM_CPU_MODE_UND = 0x1b, 1880 ARM_CPU_MODE_SYS = 0x1f 1881 }; 1882 1883 /* VFP system registers. */ 1884 #define ARM_VFP_FPSID 0 1885 #define ARM_VFP_FPSCR 1 1886 #define ARM_VFP_MVFR2 5 1887 #define ARM_VFP_MVFR1 6 1888 #define ARM_VFP_MVFR0 7 1889 #define ARM_VFP_FPEXC 8 1890 #define ARM_VFP_FPINST 9 1891 #define ARM_VFP_FPINST2 10 1892 /* These ones are M-profile only */ 1893 #define ARM_VFP_FPSCR_NZCVQC 2 1894 #define ARM_VFP_VPR 12 1895 #define ARM_VFP_P0 13 1896 #define ARM_VFP_FPCXT_NS 14 1897 #define ARM_VFP_FPCXT_S 15 1898 1899 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1900 #define QEMU_VFP_FPSCR_NZCV 0xffff 1901 1902 /* iwMMXt coprocessor control registers. */ 1903 #define ARM_IWMMXT_wCID 0 1904 #define ARM_IWMMXT_wCon 1 1905 #define ARM_IWMMXT_wCSSF 2 1906 #define ARM_IWMMXT_wCASF 3 1907 #define ARM_IWMMXT_wCGR0 8 1908 #define ARM_IWMMXT_wCGR1 9 1909 #define ARM_IWMMXT_wCGR2 10 1910 #define ARM_IWMMXT_wCGR3 11 1911 1912 /* V7M CCR bits */ 1913 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1914 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1915 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1916 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1917 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1918 FIELD(V7M_CCR, STKALIGN, 9, 1) 1919 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1920 FIELD(V7M_CCR, DC, 16, 1) 1921 FIELD(V7M_CCR, IC, 17, 1) 1922 FIELD(V7M_CCR, BP, 18, 1) 1923 FIELD(V7M_CCR, LOB, 19, 1) 1924 FIELD(V7M_CCR, TRD, 20, 1) 1925 1926 /* V7M SCR bits */ 1927 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1928 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1929 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1930 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1931 1932 /* V7M AIRCR bits */ 1933 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1934 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1935 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1936 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1937 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1938 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1939 FIELD(V7M_AIRCR, PRIS, 14, 1) 1940 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1941 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1942 1943 /* V7M CFSR bits for MMFSR */ 1944 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1945 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1946 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1947 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1948 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1949 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1950 1951 /* V7M CFSR bits for BFSR */ 1952 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1953 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1954 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1955 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1956 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1957 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1958 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1959 1960 /* V7M CFSR bits for UFSR */ 1961 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1962 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1963 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1964 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1965 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1966 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1967 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1968 1969 /* V7M CFSR bit masks covering all of the subregister bits */ 1970 FIELD(V7M_CFSR, MMFSR, 0, 8) 1971 FIELD(V7M_CFSR, BFSR, 8, 8) 1972 FIELD(V7M_CFSR, UFSR, 16, 16) 1973 1974 /* V7M HFSR bits */ 1975 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1976 FIELD(V7M_HFSR, FORCED, 30, 1) 1977 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1978 1979 /* V7M DFSR bits */ 1980 FIELD(V7M_DFSR, HALTED, 0, 1) 1981 FIELD(V7M_DFSR, BKPT, 1, 1) 1982 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1983 FIELD(V7M_DFSR, VCATCH, 3, 1) 1984 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1985 1986 /* V7M SFSR bits */ 1987 FIELD(V7M_SFSR, INVEP, 0, 1) 1988 FIELD(V7M_SFSR, INVIS, 1, 1) 1989 FIELD(V7M_SFSR, INVER, 2, 1) 1990 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1991 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1992 FIELD(V7M_SFSR, LSPERR, 5, 1) 1993 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1994 FIELD(V7M_SFSR, LSERR, 7, 1) 1995 1996 /* v7M MPU_CTRL bits */ 1997 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1998 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1999 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 2000 2001 /* v7M CLIDR bits */ 2002 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 2003 FIELD(V7M_CLIDR, LOUIS, 21, 3) 2004 FIELD(V7M_CLIDR, LOC, 24, 3) 2005 FIELD(V7M_CLIDR, LOUU, 27, 3) 2006 FIELD(V7M_CLIDR, ICB, 30, 2) 2007 2008 FIELD(V7M_CSSELR, IND, 0, 1) 2009 FIELD(V7M_CSSELR, LEVEL, 1, 3) 2010 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 2011 * define a mask for this and check that it doesn't permit running off 2012 * the end of the array. 2013 */ 2014 FIELD(V7M_CSSELR, INDEX, 0, 4) 2015 2016 /* v7M FPCCR bits */ 2017 FIELD(V7M_FPCCR, LSPACT, 0, 1) 2018 FIELD(V7M_FPCCR, USER, 1, 1) 2019 FIELD(V7M_FPCCR, S, 2, 1) 2020 FIELD(V7M_FPCCR, THREAD, 3, 1) 2021 FIELD(V7M_FPCCR, HFRDY, 4, 1) 2022 FIELD(V7M_FPCCR, MMRDY, 5, 1) 2023 FIELD(V7M_FPCCR, BFRDY, 6, 1) 2024 FIELD(V7M_FPCCR, SFRDY, 7, 1) 2025 FIELD(V7M_FPCCR, MONRDY, 8, 1) 2026 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 2027 FIELD(V7M_FPCCR, UFRDY, 10, 1) 2028 FIELD(V7M_FPCCR, RES0, 11, 15) 2029 FIELD(V7M_FPCCR, TS, 26, 1) 2030 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 2031 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 2032 FIELD(V7M_FPCCR, LSPENS, 29, 1) 2033 FIELD(V7M_FPCCR, LSPEN, 30, 1) 2034 FIELD(V7M_FPCCR, ASPEN, 31, 1) 2035 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 2036 #define R_V7M_FPCCR_BANKED_MASK \ 2037 (R_V7M_FPCCR_LSPACT_MASK | \ 2038 R_V7M_FPCCR_USER_MASK | \ 2039 R_V7M_FPCCR_THREAD_MASK | \ 2040 R_V7M_FPCCR_MMRDY_MASK | \ 2041 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 2042 R_V7M_FPCCR_UFRDY_MASK | \ 2043 R_V7M_FPCCR_ASPEN_MASK) 2044 2045 /* v7M VPR bits */ 2046 FIELD(V7M_VPR, P0, 0, 16) 2047 FIELD(V7M_VPR, MASK01, 16, 4) 2048 FIELD(V7M_VPR, MASK23, 20, 4) 2049 2050 /* 2051 * System register ID fields. 2052 */ 2053 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 2054 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 2055 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 2056 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 2057 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 2058 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 2059 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 2060 FIELD(CLIDR_EL1, LOUIS, 21, 3) 2061 FIELD(CLIDR_EL1, LOC, 24, 3) 2062 FIELD(CLIDR_EL1, LOUU, 27, 3) 2063 FIELD(CLIDR_EL1, ICB, 30, 3) 2064 2065 /* When FEAT_CCIDX is implemented */ 2066 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 2067 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 2068 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 2069 2070 /* When FEAT_CCIDX is not implemented */ 2071 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 2072 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 2073 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 2074 2075 FIELD(CTR_EL0, IMINLINE, 0, 4) 2076 FIELD(CTR_EL0, L1IP, 14, 2) 2077 FIELD(CTR_EL0, DMINLINE, 16, 4) 2078 FIELD(CTR_EL0, ERG, 20, 4) 2079 FIELD(CTR_EL0, CWG, 24, 4) 2080 FIELD(CTR_EL0, IDC, 28, 1) 2081 FIELD(CTR_EL0, DIC, 29, 1) 2082 FIELD(CTR_EL0, TMINLINE, 32, 6) 2083 2084 FIELD(MIDR_EL1, REVISION, 0, 4) 2085 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2086 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2087 FIELD(MIDR_EL1, VARIANT, 20, 4) 2088 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2089 2090 FIELD(ID_ISAR0, SWAP, 0, 4) 2091 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2092 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2093 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2094 FIELD(ID_ISAR0, COPROC, 16, 4) 2095 FIELD(ID_ISAR0, DEBUG, 20, 4) 2096 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2097 2098 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2099 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2100 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2101 FIELD(ID_ISAR1, EXTEND, 12, 4) 2102 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2103 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2104 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2105 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2106 2107 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2108 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2109 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2110 FIELD(ID_ISAR2, MULT, 12, 4) 2111 FIELD(ID_ISAR2, MULTS, 16, 4) 2112 FIELD(ID_ISAR2, MULTU, 20, 4) 2113 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2114 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2115 2116 FIELD(ID_ISAR3, SATURATE, 0, 4) 2117 FIELD(ID_ISAR3, SIMD, 4, 4) 2118 FIELD(ID_ISAR3, SVC, 8, 4) 2119 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2120 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2121 FIELD(ID_ISAR3, T32COPY, 20, 4) 2122 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2123 FIELD(ID_ISAR3, T32EE, 28, 4) 2124 2125 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2126 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2127 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2128 FIELD(ID_ISAR4, SMC, 12, 4) 2129 FIELD(ID_ISAR4, BARRIER, 16, 4) 2130 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2131 FIELD(ID_ISAR4, PSR_M, 24, 4) 2132 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2133 2134 FIELD(ID_ISAR5, SEVL, 0, 4) 2135 FIELD(ID_ISAR5, AES, 4, 4) 2136 FIELD(ID_ISAR5, SHA1, 8, 4) 2137 FIELD(ID_ISAR5, SHA2, 12, 4) 2138 FIELD(ID_ISAR5, CRC32, 16, 4) 2139 FIELD(ID_ISAR5, RDM, 24, 4) 2140 FIELD(ID_ISAR5, VCMA, 28, 4) 2141 2142 FIELD(ID_ISAR6, JSCVT, 0, 4) 2143 FIELD(ID_ISAR6, DP, 4, 4) 2144 FIELD(ID_ISAR6, FHM, 8, 4) 2145 FIELD(ID_ISAR6, SB, 12, 4) 2146 FIELD(ID_ISAR6, SPECRES, 16, 4) 2147 FIELD(ID_ISAR6, BF16, 20, 4) 2148 FIELD(ID_ISAR6, I8MM, 24, 4) 2149 2150 FIELD(ID_MMFR0, VMSA, 0, 4) 2151 FIELD(ID_MMFR0, PMSA, 4, 4) 2152 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2153 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2154 FIELD(ID_MMFR0, TCM, 16, 4) 2155 FIELD(ID_MMFR0, AUXREG, 20, 4) 2156 FIELD(ID_MMFR0, FCSE, 24, 4) 2157 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2158 2159 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2160 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2161 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2162 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2163 FIELD(ID_MMFR1, L1HVD, 16, 4) 2164 FIELD(ID_MMFR1, L1UNI, 20, 4) 2165 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2166 FIELD(ID_MMFR1, BPRED, 28, 4) 2167 2168 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2169 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2170 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2171 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2172 FIELD(ID_MMFR2, UNITLB, 16, 4) 2173 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2174 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2175 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2176 2177 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2178 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2179 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2180 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2181 FIELD(ID_MMFR3, PAN, 16, 4) 2182 FIELD(ID_MMFR3, COHWALK, 20, 4) 2183 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2184 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2185 2186 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2187 FIELD(ID_MMFR4, AC2, 4, 4) 2188 FIELD(ID_MMFR4, XNX, 8, 4) 2189 FIELD(ID_MMFR4, CNP, 12, 4) 2190 FIELD(ID_MMFR4, HPDS, 16, 4) 2191 FIELD(ID_MMFR4, LSM, 20, 4) 2192 FIELD(ID_MMFR4, CCIDX, 24, 4) 2193 FIELD(ID_MMFR4, EVT, 28, 4) 2194 2195 FIELD(ID_MMFR5, ETS, 0, 4) 2196 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2197 2198 FIELD(ID_PFR0, STATE0, 0, 4) 2199 FIELD(ID_PFR0, STATE1, 4, 4) 2200 FIELD(ID_PFR0, STATE2, 8, 4) 2201 FIELD(ID_PFR0, STATE3, 12, 4) 2202 FIELD(ID_PFR0, CSV2, 16, 4) 2203 FIELD(ID_PFR0, AMU, 20, 4) 2204 FIELD(ID_PFR0, DIT, 24, 4) 2205 FIELD(ID_PFR0, RAS, 28, 4) 2206 2207 FIELD(ID_PFR1, PROGMOD, 0, 4) 2208 FIELD(ID_PFR1, SECURITY, 4, 4) 2209 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2210 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2211 FIELD(ID_PFR1, GENTIMER, 16, 4) 2212 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2213 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2214 FIELD(ID_PFR1, GIC, 28, 4) 2215 2216 FIELD(ID_PFR2, CSV3, 0, 4) 2217 FIELD(ID_PFR2, SSBS, 4, 4) 2218 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2219 2220 FIELD(ID_AA64ISAR0, AES, 4, 4) 2221 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2222 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2223 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2224 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2225 FIELD(ID_AA64ISAR0, TME, 24, 4) 2226 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2227 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2228 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2229 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2230 FIELD(ID_AA64ISAR0, DP, 44, 4) 2231 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2232 FIELD(ID_AA64ISAR0, TS, 52, 4) 2233 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2234 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2235 2236 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2237 FIELD(ID_AA64ISAR1, APA, 4, 4) 2238 FIELD(ID_AA64ISAR1, API, 8, 4) 2239 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2240 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2241 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2242 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2243 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2244 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2245 FIELD(ID_AA64ISAR1, SB, 36, 4) 2246 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2247 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2248 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2249 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2250 FIELD(ID_AA64ISAR1, XS, 56, 4) 2251 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2252 2253 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2254 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2255 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2256 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2257 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2258 FIELD(ID_AA64ISAR2, BC, 20, 4) 2259 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2260 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2261 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2262 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2263 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2264 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2265 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2266 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2267 2268 FIELD(ID_AA64PFR0, EL0, 0, 4) 2269 FIELD(ID_AA64PFR0, EL1, 4, 4) 2270 FIELD(ID_AA64PFR0, EL2, 8, 4) 2271 FIELD(ID_AA64PFR0, EL3, 12, 4) 2272 FIELD(ID_AA64PFR0, FP, 16, 4) 2273 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2274 FIELD(ID_AA64PFR0, GIC, 24, 4) 2275 FIELD(ID_AA64PFR0, RAS, 28, 4) 2276 FIELD(ID_AA64PFR0, SVE, 32, 4) 2277 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2278 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2279 FIELD(ID_AA64PFR0, AMU, 44, 4) 2280 FIELD(ID_AA64PFR0, DIT, 48, 4) 2281 FIELD(ID_AA64PFR0, RME, 52, 4) 2282 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2283 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2284 2285 FIELD(ID_AA64PFR1, BT, 0, 4) 2286 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2287 FIELD(ID_AA64PFR1, MTE, 8, 4) 2288 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2289 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2290 FIELD(ID_AA64PFR1, SME, 24, 4) 2291 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2292 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2293 FIELD(ID_AA64PFR1, NMI, 36, 4) 2294 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2295 FIELD(ID_AA64PFR1, GCS, 44, 4) 2296 FIELD(ID_AA64PFR1, THE, 48, 4) 2297 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2298 FIELD(ID_AA64PFR1, DF2, 56, 4) 2299 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2300 2301 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2302 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2303 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2304 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2305 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2306 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2307 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2308 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2309 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2310 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2311 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2312 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2313 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2314 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2315 2316 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2317 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2318 FIELD(ID_AA64MMFR1, VH, 8, 4) 2319 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2320 FIELD(ID_AA64MMFR1, LO, 16, 4) 2321 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2322 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2323 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2324 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2325 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2326 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2327 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2328 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2329 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2330 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2331 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2332 2333 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2334 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2335 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2336 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2337 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2338 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2339 FIELD(ID_AA64MMFR2, NV, 24, 4) 2340 FIELD(ID_AA64MMFR2, ST, 28, 4) 2341 FIELD(ID_AA64MMFR2, AT, 32, 4) 2342 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2343 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2344 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2345 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2346 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2347 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2348 2349 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2350 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2351 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2352 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2353 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2354 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2355 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2356 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2357 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2358 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2359 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2360 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2361 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2362 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2363 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2364 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2365 2366 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2367 FIELD(ID_AA64ZFR0, AES, 4, 4) 2368 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2369 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2370 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2371 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2372 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2373 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2374 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2375 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2376 2377 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2378 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2379 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2380 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2381 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2382 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2383 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2384 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2385 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2386 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2387 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2388 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2389 2390 FIELD(ID_DFR0, COPDBG, 0, 4) 2391 FIELD(ID_DFR0, COPSDBG, 4, 4) 2392 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2393 FIELD(ID_DFR0, COPTRC, 12, 4) 2394 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2395 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2396 FIELD(ID_DFR0, PERFMON, 24, 4) 2397 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2398 2399 FIELD(ID_DFR1, MTPMU, 0, 4) 2400 FIELD(ID_DFR1, HPMN0, 4, 4) 2401 2402 FIELD(DBGDIDR, SE_IMP, 12, 1) 2403 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2404 FIELD(DBGDIDR, VERSION, 16, 4) 2405 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2406 FIELD(DBGDIDR, BRPS, 24, 4) 2407 FIELD(DBGDIDR, WRPS, 28, 4) 2408 2409 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2410 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2411 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2412 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2413 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2414 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2415 FIELD(DBGDEVID, AUXREGS, 24, 4) 2416 FIELD(DBGDEVID, CIDMASK, 28, 4) 2417 2418 FIELD(MVFR0, SIMDREG, 0, 4) 2419 FIELD(MVFR0, FPSP, 4, 4) 2420 FIELD(MVFR0, FPDP, 8, 4) 2421 FIELD(MVFR0, FPTRAP, 12, 4) 2422 FIELD(MVFR0, FPDIVIDE, 16, 4) 2423 FIELD(MVFR0, FPSQRT, 20, 4) 2424 FIELD(MVFR0, FPSHVEC, 24, 4) 2425 FIELD(MVFR0, FPROUND, 28, 4) 2426 2427 FIELD(MVFR1, FPFTZ, 0, 4) 2428 FIELD(MVFR1, FPDNAN, 4, 4) 2429 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2430 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2431 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2432 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2433 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2434 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2435 FIELD(MVFR1, FPHP, 24, 4) 2436 FIELD(MVFR1, SIMDFMAC, 28, 4) 2437 2438 FIELD(MVFR2, SIMDMISC, 0, 4) 2439 FIELD(MVFR2, FPMISC, 4, 4) 2440 2441 FIELD(GPCCR, PPS, 0, 3) 2442 FIELD(GPCCR, IRGN, 8, 2) 2443 FIELD(GPCCR, ORGN, 10, 2) 2444 FIELD(GPCCR, SH, 12, 2) 2445 FIELD(GPCCR, PGS, 14, 2) 2446 FIELD(GPCCR, GPC, 16, 1) 2447 FIELD(GPCCR, GPCP, 17, 1) 2448 FIELD(GPCCR, L0GPTSZ, 20, 4) 2449 2450 FIELD(MFAR, FPA, 12, 40) 2451 FIELD(MFAR, NSE, 62, 1) 2452 FIELD(MFAR, NS, 63, 1) 2453 2454 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2455 2456 /* If adding a feature bit which corresponds to a Linux ELF 2457 * HWCAP bit, remember to update the feature-bit-to-hwcap 2458 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2459 */ 2460 enum arm_features { 2461 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2462 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2463 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2464 ARM_FEATURE_V6, 2465 ARM_FEATURE_V6K, 2466 ARM_FEATURE_V7, 2467 ARM_FEATURE_THUMB2, 2468 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2469 ARM_FEATURE_NEON, 2470 ARM_FEATURE_M, /* Microcontroller profile. */ 2471 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2472 ARM_FEATURE_THUMB2EE, 2473 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2474 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2475 ARM_FEATURE_V4T, 2476 ARM_FEATURE_V5, 2477 ARM_FEATURE_STRONGARM, 2478 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2479 ARM_FEATURE_GENERIC_TIMER, 2480 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2481 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2482 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2483 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2484 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2485 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2486 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2487 ARM_FEATURE_V8, 2488 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2489 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2490 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2491 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2492 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2493 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2494 ARM_FEATURE_PMU, /* has PMU support */ 2495 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2496 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2497 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2498 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2499 }; 2500 2501 static inline int arm_feature(CPUARMState *env, int feature) 2502 { 2503 return (env->features & (1ULL << feature)) != 0; 2504 } 2505 2506 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2507 2508 /* 2509 * ARM v9 security states. 2510 * The ordering of the enumeration corresponds to the low 2 bits 2511 * of the GPI value, and (except for Root) the concat of NSE:NS. 2512 */ 2513 2514 typedef enum ARMSecuritySpace { 2515 ARMSS_Secure = 0, 2516 ARMSS_NonSecure = 1, 2517 ARMSS_Root = 2, 2518 ARMSS_Realm = 3, 2519 } ARMSecuritySpace; 2520 2521 /* Return true if @space is secure, in the pre-v9 sense. */ 2522 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2523 { 2524 return space == ARMSS_Secure || space == ARMSS_Root; 2525 } 2526 2527 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2528 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2529 { 2530 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2531 } 2532 2533 #if !defined(CONFIG_USER_ONLY) 2534 /** 2535 * arm_security_space_below_el3: 2536 * @env: cpu context 2537 * 2538 * Return the security space of exception levels below EL3, following 2539 * an exception return to those levels. Unlike arm_security_space, 2540 * this doesn't care about the current EL. 2541 */ 2542 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2543 2544 /** 2545 * arm_is_secure_below_el3: 2546 * @env: cpu context 2547 * 2548 * Return true if exception levels below EL3 are in secure state, 2549 * or would be following an exception return to those levels. 2550 */ 2551 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2552 { 2553 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2554 return ss == ARMSS_Secure; 2555 } 2556 2557 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2558 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2559 { 2560 assert(!arm_feature(env, ARM_FEATURE_M)); 2561 if (arm_feature(env, ARM_FEATURE_EL3)) { 2562 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2563 /* CPU currently in AArch64 state and EL3 */ 2564 return true; 2565 } else if (!is_a64(env) && 2566 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2567 /* CPU currently in AArch32 state and monitor mode */ 2568 return true; 2569 } 2570 } 2571 return false; 2572 } 2573 2574 /** 2575 * arm_security_space: 2576 * @env: cpu context 2577 * 2578 * Return the current security space of the cpu. 2579 */ 2580 ARMSecuritySpace arm_security_space(CPUARMState *env); 2581 2582 /** 2583 * arm_is_secure: 2584 * @env: cpu context 2585 * 2586 * Return true if the processor is in secure state. 2587 */ 2588 static inline bool arm_is_secure(CPUARMState *env) 2589 { 2590 return arm_space_is_secure(arm_security_space(env)); 2591 } 2592 2593 /* 2594 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2595 * This corresponds to the pseudocode EL2Enabled(). 2596 */ 2597 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2598 ARMSecuritySpace space) 2599 { 2600 assert(space != ARMSS_Root); 2601 return arm_feature(env, ARM_FEATURE_EL2) 2602 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2603 } 2604 2605 static inline bool arm_is_el2_enabled(CPUARMState *env) 2606 { 2607 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2608 } 2609 2610 #else 2611 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2612 { 2613 return ARMSS_NonSecure; 2614 } 2615 2616 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2617 { 2618 return false; 2619 } 2620 2621 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2622 { 2623 return ARMSS_NonSecure; 2624 } 2625 2626 static inline bool arm_is_secure(CPUARMState *env) 2627 { 2628 return false; 2629 } 2630 2631 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2632 ARMSecuritySpace space) 2633 { 2634 return false; 2635 } 2636 2637 static inline bool arm_is_el2_enabled(CPUARMState *env) 2638 { 2639 return false; 2640 } 2641 #endif 2642 2643 /** 2644 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2645 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2646 * "for all purposes other than a direct read or write access of HCR_EL2." 2647 * Not included here is HCR_RW. 2648 */ 2649 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2650 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2651 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2652 2653 /* Return true if the specified exception level is running in AArch64 state. */ 2654 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2655 { 2656 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2657 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2658 */ 2659 assert(el >= 1 && el <= 3); 2660 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2661 2662 /* The highest exception level is always at the maximum supported 2663 * register width, and then lower levels have a register width controlled 2664 * by bits in the SCR or HCR registers. 2665 */ 2666 if (el == 3) { 2667 return aa64; 2668 } 2669 2670 if (arm_feature(env, ARM_FEATURE_EL3) && 2671 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2672 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2673 } 2674 2675 if (el == 2) { 2676 return aa64; 2677 } 2678 2679 if (arm_is_el2_enabled(env)) { 2680 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2681 } 2682 2683 return aa64; 2684 } 2685 2686 /* Function for determining whether guest cp register reads and writes should 2687 * access the secure or non-secure bank of a cp register. When EL3 is 2688 * operating in AArch32 state, the NS-bit determines whether the secure 2689 * instance of a cp register should be used. When EL3 is AArch64 (or if 2690 * it doesn't exist at all) then there is no register banking, and all 2691 * accesses are to the non-secure version. 2692 */ 2693 static inline bool access_secure_reg(CPUARMState *env) 2694 { 2695 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2696 !arm_el_is_aa64(env, 3) && 2697 !(env->cp15.scr_el3 & SCR_NS)); 2698 2699 return ret; 2700 } 2701 2702 /* Macros for accessing a specified CP register bank */ 2703 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2704 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2705 2706 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2707 do { \ 2708 if (_secure) { \ 2709 (_env)->cp15._regname##_s = (_val); \ 2710 } else { \ 2711 (_env)->cp15._regname##_ns = (_val); \ 2712 } \ 2713 } while (0) 2714 2715 /* Macros for automatically accessing a specific CP register bank depending on 2716 * the current secure state of the system. These macros are not intended for 2717 * supporting instruction translation reads/writes as these are dependent 2718 * solely on the SCR.NS bit and not the mode. 2719 */ 2720 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2721 A32_BANKED_REG_GET((_env), _regname, \ 2722 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2723 2724 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2725 A32_BANKED_REG_SET((_env), _regname, \ 2726 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2727 (_val)) 2728 2729 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2730 uint32_t cur_el, bool secure); 2731 2732 /* Return the highest implemented Exception Level */ 2733 static inline int arm_highest_el(CPUARMState *env) 2734 { 2735 if (arm_feature(env, ARM_FEATURE_EL3)) { 2736 return 3; 2737 } 2738 if (arm_feature(env, ARM_FEATURE_EL2)) { 2739 return 2; 2740 } 2741 return 1; 2742 } 2743 2744 /* Return true if a v7M CPU is in Handler mode */ 2745 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2746 { 2747 return env->v7m.exception != 0; 2748 } 2749 2750 /* Return the current Exception Level (as per ARMv8; note that this differs 2751 * from the ARMv7 Privilege Level). 2752 */ 2753 static inline int arm_current_el(CPUARMState *env) 2754 { 2755 if (arm_feature(env, ARM_FEATURE_M)) { 2756 return arm_v7m_is_handler_mode(env) || 2757 !(env->v7m.control[env->v7m.secure] & 1); 2758 } 2759 2760 if (is_a64(env)) { 2761 return extract32(env->pstate, 2, 2); 2762 } 2763 2764 switch (env->uncached_cpsr & 0x1f) { 2765 case ARM_CPU_MODE_USR: 2766 return 0; 2767 case ARM_CPU_MODE_HYP: 2768 return 2; 2769 case ARM_CPU_MODE_MON: 2770 return 3; 2771 default: 2772 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2773 /* If EL3 is 32-bit then all secure privileged modes run in 2774 * EL3 2775 */ 2776 return 3; 2777 } 2778 2779 return 1; 2780 } 2781 } 2782 2783 /** 2784 * write_list_to_cpustate 2785 * @cpu: ARMCPU 2786 * 2787 * For each register listed in the ARMCPU cpreg_indexes list, write 2788 * its value from the cpreg_values list into the ARMCPUState structure. 2789 * This updates TCG's working data structures from KVM data or 2790 * from incoming migration state. 2791 * 2792 * Returns: true if all register values were updated correctly, 2793 * false if some register was unknown or could not be written. 2794 * Note that we do not stop early on failure -- we will attempt 2795 * writing all registers in the list. 2796 */ 2797 bool write_list_to_cpustate(ARMCPU *cpu); 2798 2799 /** 2800 * write_cpustate_to_list: 2801 * @cpu: ARMCPU 2802 * @kvm_sync: true if this is for syncing back to KVM 2803 * 2804 * For each register listed in the ARMCPU cpreg_indexes list, write 2805 * its value from the ARMCPUState structure into the cpreg_values list. 2806 * This is used to copy info from TCG's working data structures into 2807 * KVM or for outbound migration. 2808 * 2809 * @kvm_sync is true if we are doing this in order to sync the 2810 * register state back to KVM. In this case we will only update 2811 * values in the list if the previous list->cpustate sync actually 2812 * successfully wrote the CPU state. Otherwise we will keep the value 2813 * that is in the list. 2814 * 2815 * Returns: true if all register values were read correctly, 2816 * false if some register was unknown or could not be read. 2817 * Note that we do not stop early on failure -- we will attempt 2818 * reading all registers in the list. 2819 */ 2820 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2821 2822 #define ARM_CPUID_TI915T 0x54029152 2823 #define ARM_CPUID_TI925T 0x54029252 2824 2825 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2826 2827 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2828 2829 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2830 * 2831 * If EL3 is 64-bit: 2832 * + NonSecure EL1 & 0 stage 1 2833 * + NonSecure EL1 & 0 stage 2 2834 * + NonSecure EL2 2835 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2836 * + Secure EL1 & 0 2837 * + Secure EL3 2838 * If EL3 is 32-bit: 2839 * + NonSecure PL1 & 0 stage 1 2840 * + NonSecure PL1 & 0 stage 2 2841 * + NonSecure PL2 2842 * + Secure PL0 2843 * + Secure PL1 2844 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2845 * 2846 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2847 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2848 * because they may differ in access permissions even if the VA->PA map is 2849 * the same 2850 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2851 * translation, which means that we have one mmu_idx that deals with two 2852 * concatenated translation regimes [this sort of combined s1+2 TLB is 2853 * architecturally permitted] 2854 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2855 * handling via the TLB. The only way to do a stage 1 translation without 2856 * the immediate stage 2 translation is via the ATS or AT system insns, 2857 * which can be slow-pathed and always do a page table walk. 2858 * The only use of stage 2 translations is either as part of an s1+2 2859 * lookup or when loading the descriptors during a stage 1 page table walk, 2860 * and in both those cases we don't use the TLB. 2861 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2862 * translation regimes, because they map reasonably well to each other 2863 * and they can't both be active at the same time. 2864 * 5. we want to be able to use the TLB for accesses done as part of a 2865 * stage1 page table walk, rather than having to walk the stage2 page 2866 * table over and over. 2867 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2868 * Never (PAN) bit within PSTATE. 2869 * 7. we fold together the secure and non-secure regimes for A-profile, 2870 * because there are no banked system registers for aarch64, so the 2871 * process of switching between secure and non-secure is 2872 * already heavyweight. 2873 * 2874 * This gives us the following list of cases: 2875 * 2876 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2877 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2878 * EL1 EL1&0 stage 1+2 +PAN 2879 * EL0 EL2&0 2880 * EL2 EL2&0 2881 * EL2 EL2&0 +PAN 2882 * EL2 (aka NS PL2) 2883 * EL3 (aka S PL1) 2884 * Physical (NS & S) 2885 * Stage2 (NS & S) 2886 * 2887 * for a total of 12 different mmu_idx. 2888 * 2889 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2890 * as A profile. They only need to distinguish EL0 and EL1 (and 2891 * EL2 if we ever model a Cortex-R52). 2892 * 2893 * M profile CPUs are rather different as they do not have a true MMU. 2894 * They have the following different MMU indexes: 2895 * User 2896 * Privileged 2897 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2898 * Privileged, execution priority negative (ditto) 2899 * If the CPU supports the v8M Security Extension then there are also: 2900 * Secure User 2901 * Secure Privileged 2902 * Secure User, execution priority negative 2903 * Secure Privileged, execution priority negative 2904 * 2905 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2906 * are not quite the same -- different CPU types (most notably M profile 2907 * vs A/R profile) would like to use MMU indexes with different semantics, 2908 * but since we don't ever need to use all of those in a single CPU we 2909 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2910 * modes + total number of M profile MMU modes". The lower bits of 2911 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2912 * the same for any particular CPU. 2913 * Variables of type ARMMUIdx are always full values, and the core 2914 * index values are in variables of type 'int'. 2915 * 2916 * Our enumeration includes at the end some entries which are not "true" 2917 * mmu_idx values in that they don't have corresponding TLBs and are only 2918 * valid for doing slow path page table walks. 2919 * 2920 * The constant names here are patterned after the general style of the names 2921 * of the AT/ATS operations. 2922 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2923 * For M profile we arrange them to have a bit for priv, a bit for negpri 2924 * and a bit for secure. 2925 */ 2926 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2927 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2928 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2929 2930 /* Meanings of the bits for M profile mmu idx values */ 2931 #define ARM_MMU_IDX_M_PRIV 0x1 2932 #define ARM_MMU_IDX_M_NEGPRI 0x2 2933 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2934 2935 #define ARM_MMU_IDX_TYPE_MASK \ 2936 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2937 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2938 2939 typedef enum ARMMMUIdx { 2940 /* 2941 * A-profile. 2942 */ 2943 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2944 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2945 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2946 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2947 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2948 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2949 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2950 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2951 2952 /* 2953 * Used for second stage of an S12 page table walk, or for descriptor 2954 * loads during first stage of an S1 page table walk. Note that both 2955 * are in use simultaneously for SecureEL2: the security state for 2956 * the S2 ptw is selected by the NS bit from the S1 ptw. 2957 */ 2958 ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A, 2959 ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, 2960 2961 /* TLBs with 1-1 mapping to the physical address spaces. */ 2962 ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, 2963 ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, 2964 ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, 2965 ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, 2966 2967 /* 2968 * These are not allocated TLBs and are used only for AT system 2969 * instructions or for the first stage of an S12 page table walk. 2970 */ 2971 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2972 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2973 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2974 2975 /* 2976 * M-profile. 2977 */ 2978 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2979 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2980 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2981 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2982 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2983 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2984 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2985 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2986 } ARMMMUIdx; 2987 2988 /* 2989 * Bit macros for the core-mmu-index values for each index, 2990 * for use when calling tlb_flush_by_mmuidx() and friends. 2991 */ 2992 #define TO_CORE_BIT(NAME) \ 2993 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2994 2995 typedef enum ARMMMUIdxBit { 2996 TO_CORE_BIT(E10_0), 2997 TO_CORE_BIT(E20_0), 2998 TO_CORE_BIT(E10_1), 2999 TO_CORE_BIT(E10_1_PAN), 3000 TO_CORE_BIT(E2), 3001 TO_CORE_BIT(E20_2), 3002 TO_CORE_BIT(E20_2_PAN), 3003 TO_CORE_BIT(E3), 3004 TO_CORE_BIT(Stage2), 3005 TO_CORE_BIT(Stage2_S), 3006 3007 TO_CORE_BIT(MUser), 3008 TO_CORE_BIT(MPriv), 3009 TO_CORE_BIT(MUserNegPri), 3010 TO_CORE_BIT(MPrivNegPri), 3011 TO_CORE_BIT(MSUser), 3012 TO_CORE_BIT(MSPriv), 3013 TO_CORE_BIT(MSUserNegPri), 3014 TO_CORE_BIT(MSPrivNegPri), 3015 } ARMMMUIdxBit; 3016 3017 #undef TO_CORE_BIT 3018 3019 #define MMU_USER_IDX 0 3020 3021 /* Indexes used when registering address spaces with cpu_address_space_init */ 3022 typedef enum ARMASIdx { 3023 ARMASIdx_NS = 0, 3024 ARMASIdx_S = 1, 3025 ARMASIdx_TagNS = 2, 3026 ARMASIdx_TagS = 3, 3027 } ARMASIdx; 3028 3029 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 3030 { 3031 /* Assert the relative order of the physical mmu indexes. */ 3032 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 3033 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 3034 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 3035 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 3036 3037 return ARMMMUIdx_Phys_S + space; 3038 } 3039 3040 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 3041 { 3042 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 3043 return idx - ARMMMUIdx_Phys_S; 3044 } 3045 3046 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3047 { 3048 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3049 * CSSELR is RAZ/WI. 3050 */ 3051 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3052 } 3053 3054 static inline bool arm_sctlr_b(CPUARMState *env) 3055 { 3056 return 3057 /* We need not implement SCTLR.ITD in user-mode emulation, so 3058 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3059 * This lets people run BE32 binaries with "-cpu any". 3060 */ 3061 #ifndef CONFIG_USER_ONLY 3062 !arm_feature(env, ARM_FEATURE_V7) && 3063 #endif 3064 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3065 } 3066 3067 uint64_t arm_sctlr(CPUARMState *env, int el); 3068 3069 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3070 bool sctlr_b) 3071 { 3072 #ifdef CONFIG_USER_ONLY 3073 /* 3074 * In system mode, BE32 is modelled in line with the 3075 * architecture (as word-invariant big-endianness), where loads 3076 * and stores are done little endian but from addresses which 3077 * are adjusted by XORing with the appropriate constant. So the 3078 * endianness to use for the raw data access is not affected by 3079 * SCTLR.B. 3080 * In user mode, however, we model BE32 as byte-invariant 3081 * big-endianness (because user-only code cannot tell the 3082 * difference), and so we need to use a data access endianness 3083 * that depends on SCTLR.B. 3084 */ 3085 if (sctlr_b) { 3086 return true; 3087 } 3088 #endif 3089 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3090 return env->uncached_cpsr & CPSR_E; 3091 } 3092 3093 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3094 { 3095 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3096 } 3097 3098 /* Return true if the processor is in big-endian mode. */ 3099 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3100 { 3101 if (!is_a64(env)) { 3102 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3103 } else { 3104 int cur_el = arm_current_el(env); 3105 uint64_t sctlr = arm_sctlr(env, cur_el); 3106 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3107 } 3108 } 3109 3110 #include "exec/cpu-all.h" 3111 3112 /* 3113 * We have more than 32-bits worth of state per TB, so we split the data 3114 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3115 * We collect these two parts in CPUARMTBFlags where they are named 3116 * flags and flags2 respectively. 3117 * 3118 * The flags that are shared between all execution modes, TBFLAG_ANY, 3119 * are stored in flags. The flags that are specific to a given mode 3120 * are stores in flags2. Since cs_base is sized on the configured 3121 * address size, flags2 always has 64-bits for A64, and a minimum of 3122 * 32-bits for A32 and M32. 3123 * 3124 * The bits for 32-bit A-profile and M-profile partially overlap: 3125 * 3126 * 31 23 11 10 0 3127 * +-------------+----------+----------------+ 3128 * | | | TBFLAG_A32 | 3129 * | TBFLAG_AM32 | +-----+----------+ 3130 * | | |TBFLAG_M32| 3131 * +-------------+----------------+----------+ 3132 * 31 23 6 5 0 3133 * 3134 * Unless otherwise noted, these bits are cached in env->hflags. 3135 */ 3136 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3137 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3138 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3139 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3140 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3141 /* Target EL if we take a floating-point-disabled exception */ 3142 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3143 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3144 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3145 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3146 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3147 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3148 3149 /* 3150 * Bit usage when in AArch32 state, both A- and M-profile. 3151 */ 3152 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3153 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3154 3155 /* 3156 * Bit usage when in AArch32 state, for A-profile only. 3157 */ 3158 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3159 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3160 /* 3161 * We store the bottom two bits of the CPAR as TB flags and handle 3162 * checks on the other bits at runtime. This shares the same bits as 3163 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3164 * Not cached, because VECLEN+VECSTRIDE are not cached. 3165 */ 3166 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3167 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3168 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3169 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3170 /* 3171 * Indicates whether cp register reads and writes by guest code should access 3172 * the secure or nonsecure bank of banked registers; note that this is not 3173 * the same thing as the current security state of the processor! 3174 */ 3175 FIELD(TBFLAG_A32, NS, 10, 1) 3176 /* 3177 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3178 * This requires an SME trap from AArch32 mode when using NEON. 3179 */ 3180 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3181 3182 /* 3183 * Bit usage when in AArch32 state, for M-profile only. 3184 */ 3185 /* Handler (ie not Thread) mode */ 3186 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3187 /* Whether we should generate stack-limit checks */ 3188 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3189 /* Set if FPCCR.LSPACT is set */ 3190 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3191 /* Set if we must create a new FP context */ 3192 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3193 /* Set if FPCCR.S does not match current security state */ 3194 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3195 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3196 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3197 /* Set if in secure mode */ 3198 FIELD(TBFLAG_M32, SECURE, 6, 1) 3199 3200 /* 3201 * Bit usage when in AArch64 state 3202 */ 3203 FIELD(TBFLAG_A64, TBII, 0, 2) 3204 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3205 /* The current vector length, either NVL or SVL. */ 3206 FIELD(TBFLAG_A64, VL, 4, 4) 3207 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3208 FIELD(TBFLAG_A64, BT, 9, 1) 3209 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3210 FIELD(TBFLAG_A64, TBID, 12, 2) 3211 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3212 FIELD(TBFLAG_A64, ATA, 15, 1) 3213 FIELD(TBFLAG_A64, TCMA, 16, 2) 3214 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3215 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3216 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3217 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3218 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3219 FIELD(TBFLAG_A64, SVL, 24, 4) 3220 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3221 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3222 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 3223 FIELD(TBFLAG_A64, NAA, 30, 1) 3224 FIELD(TBFLAG_A64, ATA0, 31, 1) 3225 FIELD(TBFLAG_A64, NV, 32, 1) 3226 FIELD(TBFLAG_A64, NV1, 33, 1) 3227 FIELD(TBFLAG_A64, NV2, 34, 1) 3228 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ 3229 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) 3230 /* Set if FEAT_NV2 RAM accesses are big-endian */ 3231 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 3232 3233 /* 3234 * Helpers for using the above. Note that only the A64 accessors use 3235 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 3236 * word either is or might be 32 bits only. 3237 */ 3238 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3239 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3240 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3241 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3242 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3243 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3244 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3245 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3246 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3247 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3248 3249 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3250 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 3251 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3252 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3253 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3254 3255 /** 3256 * cpu_mmu_index: 3257 * @env: The cpu environment 3258 * @ifetch: True for code access, false for data access. 3259 * 3260 * Return the core mmu index for the current translation regime. 3261 * This function is used by generic TCG code paths. 3262 */ 3263 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3264 { 3265 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3266 } 3267 3268 /** 3269 * sve_vq 3270 * @env: the cpu context 3271 * 3272 * Return the VL cached within env->hflags, in units of quadwords. 3273 */ 3274 static inline int sve_vq(CPUARMState *env) 3275 { 3276 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3277 } 3278 3279 /** 3280 * sme_vq 3281 * @env: the cpu context 3282 * 3283 * Return the SVL cached within env->hflags, in units of quadwords. 3284 */ 3285 static inline int sme_vq(CPUARMState *env) 3286 { 3287 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3288 } 3289 3290 static inline bool bswap_code(bool sctlr_b) 3291 { 3292 #ifdef CONFIG_USER_ONLY 3293 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3294 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3295 * would also end up as a mixed-endian mode with BE code, LE data. 3296 */ 3297 return TARGET_BIG_ENDIAN ^ sctlr_b; 3298 #else 3299 /* All code access in ARM is little endian, and there are no loaders 3300 * doing swaps that need to be reversed 3301 */ 3302 return 0; 3303 #endif 3304 } 3305 3306 #ifdef CONFIG_USER_ONLY 3307 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3308 { 3309 return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); 3310 } 3311 #endif 3312 3313 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, 3314 uint64_t *cs_base, uint32_t *flags); 3315 3316 enum { 3317 QEMU_PSCI_CONDUIT_DISABLED = 0, 3318 QEMU_PSCI_CONDUIT_SMC = 1, 3319 QEMU_PSCI_CONDUIT_HVC = 2, 3320 }; 3321 3322 #ifndef CONFIG_USER_ONLY 3323 /* Return the address space index to use for a memory access */ 3324 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3325 { 3326 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3327 } 3328 3329 /* Return the AddressSpace to use for a memory access 3330 * (which depends on whether the access is S or NS, and whether 3331 * the board gave us a separate AddressSpace for S accesses). 3332 */ 3333 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3334 { 3335 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3336 } 3337 #endif 3338 3339 /** 3340 * arm_register_pre_el_change_hook: 3341 * Register a hook function which will be called immediately before this 3342 * CPU changes exception level or mode. The hook function will be 3343 * passed a pointer to the ARMCPU and the opaque data pointer passed 3344 * to this function when the hook was registered. 3345 * 3346 * Note that if a pre-change hook is called, any registered post-change hooks 3347 * are guaranteed to subsequently be called. 3348 */ 3349 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3350 void *opaque); 3351 /** 3352 * arm_register_el_change_hook: 3353 * Register a hook function which will be called immediately after this 3354 * CPU changes exception level or mode. The hook function will be 3355 * passed a pointer to the ARMCPU and the opaque data pointer passed 3356 * to this function when the hook was registered. 3357 * 3358 * Note that any registered hooks registered here are guaranteed to be called 3359 * if pre-change hooks have been. 3360 */ 3361 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3362 *opaque); 3363 3364 /** 3365 * arm_rebuild_hflags: 3366 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3367 */ 3368 void arm_rebuild_hflags(CPUARMState *env); 3369 3370 /** 3371 * aa32_vfp_dreg: 3372 * Return a pointer to the Dn register within env in 32-bit mode. 3373 */ 3374 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3375 { 3376 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3377 } 3378 3379 /** 3380 * aa32_vfp_qreg: 3381 * Return a pointer to the Qn register within env in 32-bit mode. 3382 */ 3383 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3384 { 3385 return &env->vfp.zregs[regno].d[0]; 3386 } 3387 3388 /** 3389 * aa64_vfp_qreg: 3390 * Return a pointer to the Qn register within env in 64-bit mode. 3391 */ 3392 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3393 { 3394 return &env->vfp.zregs[regno].d[0]; 3395 } 3396 3397 /* Shared between translate-sve.c and sve_helper.c. */ 3398 extern const uint64_t pred_esz_masks[5]; 3399 3400 /* 3401 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3402 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3403 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3404 */ 3405 #define PAGE_BTI PAGE_TARGET_1 3406 #define PAGE_MTE PAGE_TARGET_2 3407 #define PAGE_TARGET_STICKY PAGE_MTE 3408 3409 /* We associate one allocation tag per 16 bytes, the minimum. */ 3410 #define LOG2_TAG_GRANULE 4 3411 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3412 3413 #ifdef CONFIG_USER_ONLY 3414 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3415 #endif 3416 3417 #ifdef TARGET_TAGGED_ADDRESSES 3418 /** 3419 * cpu_untagged_addr: 3420 * @cs: CPU context 3421 * @x: tagged address 3422 * 3423 * Remove any address tag from @x. This is explicitly related to the 3424 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3425 * 3426 * There should be a better place to put this, but we need this in 3427 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3428 */ 3429 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3430 { 3431 ARMCPU *cpu = ARM_CPU(cs); 3432 if (cpu->env.tagged_addr_enable) { 3433 /* 3434 * TBI is enabled for userspace but not kernelspace addresses. 3435 * Only clear the tag if bit 55 is clear. 3436 */ 3437 x &= sextract64(x, 0, 56); 3438 } 3439 return x; 3440 } 3441 #endif 3442 3443 #endif 3444