1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "exec/gdbstub.h" 29 #include "qapi/qapi-types-common.h" 30 #include "target/arm/multiprocessing.h" 31 #include "target/arm/gtimer.h" 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #ifdef TARGET_AARCH64 37 #define KVM_HAVE_MCE_INJECTION 1 38 #endif 39 40 #define EXCP_UDEF 1 /* undefined instruction */ 41 #define EXCP_SWI 2 /* software interrupt */ 42 #define EXCP_PREFETCH_ABORT 3 43 #define EXCP_DATA_ABORT 4 44 #define EXCP_IRQ 5 45 #define EXCP_FIQ 6 46 #define EXCP_BKPT 7 47 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 48 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 49 #define EXCP_HVC 11 /* HyperVisor Call */ 50 #define EXCP_HYP_TRAP 12 51 #define EXCP_SMC 13 /* Secure Monitor Call */ 52 #define EXCP_VIRQ 14 53 #define EXCP_VFIQ 15 54 #define EXCP_SEMIHOST 16 /* semihosting call */ 55 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 56 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 57 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 58 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 59 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 60 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 61 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 62 #define EXCP_VSERR 24 63 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 64 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 65 66 #define ARMV7M_EXCP_RESET 1 67 #define ARMV7M_EXCP_NMI 2 68 #define ARMV7M_EXCP_HARD 3 69 #define ARMV7M_EXCP_MEM 4 70 #define ARMV7M_EXCP_BUS 5 71 #define ARMV7M_EXCP_USAGE 6 72 #define ARMV7M_EXCP_SECURE 7 73 #define ARMV7M_EXCP_SVC 11 74 #define ARMV7M_EXCP_DEBUG 12 75 #define ARMV7M_EXCP_PENDSV 14 76 #define ARMV7M_EXCP_SYSTICK 15 77 78 /* ARM-specific interrupt pending bits. */ 79 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 80 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 81 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 82 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 83 84 /* The usual mapping for an AArch64 system register to its AArch32 85 * counterpart is for the 32 bit world to have access to the lower 86 * half only (with writes leaving the upper half untouched). It's 87 * therefore useful to be able to pass TCG the offset of the least 88 * significant half of a uint64_t struct member. 89 */ 90 #if HOST_BIG_ENDIAN 91 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 92 #define offsetofhigh32(S, M) offsetof(S, M) 93 #else 94 #define offsetoflow32(S, M) offsetof(S, M) 95 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 96 #endif 97 98 /* ARM-specific extra insn start words: 99 * 1: Conditional execution bits 100 * 2: Partial exception syndrome for data aborts 101 */ 102 #define TARGET_INSN_START_EXTRA_WORDS 2 103 104 /* The 2nd extra word holding syndrome info for data aborts does not use 105 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 106 * help the sleb128 encoder do a better job. 107 * When restoring the CPU state, we shift it back up. 108 */ 109 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 110 #define ARM_INSN_START_WORD2_SHIFT 13 111 112 /* We currently assume float and double are IEEE single and double 113 precision respectively. 114 Doing runtime conversions is tricky because VFP registers may contain 115 integer values (eg. as the result of a FTOSI instruction). 116 s<2n> maps to the least significant half of d<n> 117 s<2n+1> maps to the most significant half of d<n> 118 */ 119 120 /** 121 * DynamicGDBFeatureInfo: 122 * @desc: Contains the feature descriptions. 123 * @data: A union with data specific to the set of registers 124 * @cpregs_keys: Array that contains the corresponding Key of 125 * a given cpreg with the same order of the cpreg 126 * in the XML description. 127 */ 128 typedef struct DynamicGDBFeatureInfo { 129 GDBFeature desc; 130 union { 131 struct { 132 uint32_t *keys; 133 } cpregs; 134 } data; 135 } DynamicGDBFeatureInfo; 136 137 /* CPU state for each instance of a generic timer (in cp15 c14) */ 138 typedef struct ARMGenericTimer { 139 uint64_t cval; /* Timer CompareValue register */ 140 uint64_t ctl; /* Timer Control register */ 141 } ARMGenericTimer; 142 143 /* Define a maximum sized vector register. 144 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 145 * For 64-bit, this is a 2048-bit SVE register. 146 * 147 * Note that the mapping between S, D, and Q views of the register bank 148 * differs between AArch64 and AArch32. 149 * In AArch32: 150 * Qn = regs[n].d[1]:regs[n].d[0] 151 * Dn = regs[n / 2].d[n & 1] 152 * Sn = regs[n / 4].d[n % 4 / 2], 153 * bits 31..0 for even n, and bits 63..32 for odd n 154 * (and regs[16] to regs[31] are inaccessible) 155 * In AArch64: 156 * Zn = regs[n].d[*] 157 * Qn = regs[n].d[1]:regs[n].d[0] 158 * Dn = regs[n].d[0] 159 * Sn = regs[n].d[0] bits 31..0 160 * Hn = regs[n].d[0] bits 15..0 161 * 162 * This corresponds to the architecturally defined mapping between 163 * the two execution states, and means we do not need to explicitly 164 * map these registers when changing states. 165 * 166 * Align the data for use with TCG host vector operations. 167 */ 168 169 #ifdef TARGET_AARCH64 170 # define ARM_MAX_VQ 16 171 #else 172 # define ARM_MAX_VQ 1 173 #endif 174 175 typedef struct ARMVectorReg { 176 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 177 } ARMVectorReg; 178 179 #ifdef TARGET_AARCH64 180 /* In AArch32 mode, predicate registers do not exist at all. */ 181 typedef struct ARMPredicateReg { 182 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 183 } ARMPredicateReg; 184 185 /* In AArch32 mode, PAC keys do not exist at all. */ 186 typedef struct ARMPACKey { 187 uint64_t lo, hi; 188 } ARMPACKey; 189 #endif 190 191 /* See the commentary above the TBFLAG field definitions. */ 192 typedef struct CPUARMTBFlags { 193 uint32_t flags; 194 target_ulong flags2; 195 } CPUARMTBFlags; 196 197 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 198 199 typedef struct NVICState NVICState; 200 201 typedef struct CPUArchState { 202 /* Regs for current mode. */ 203 uint32_t regs[16]; 204 205 /* 32/64 switch only happens when taking and returning from 206 * exceptions so the overlap semantics are taken care of then 207 * instead of having a complicated union. 208 */ 209 /* Regs for A64 mode. */ 210 uint64_t xregs[32]; 211 uint64_t pc; 212 /* PSTATE isn't an architectural register for ARMv8. However, it is 213 * convenient for us to assemble the underlying state into a 32 bit format 214 * identical to the architectural format used for the SPSR. (This is also 215 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 216 * 'pstate' register are.) Of the PSTATE bits: 217 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 218 * semantics as for AArch32, as described in the comments on each field) 219 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 220 * DAIF (exception masks) are kept in env->daif 221 * BTYPE is kept in env->btype 222 * SM and ZA are kept in env->svcr 223 * all other bits are stored in their correct places in env->pstate 224 */ 225 uint32_t pstate; 226 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 227 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 228 229 /* Cached TBFLAGS state. See below for which bits are included. */ 230 CPUARMTBFlags hflags; 231 232 /* Frequently accessed CPSR bits are stored separately for efficiency. 233 This contains all the other bits. Use cpsr_{read,write} to access 234 the whole CPSR. */ 235 uint32_t uncached_cpsr; 236 uint32_t spsr; 237 238 /* Banked registers. */ 239 uint64_t banked_spsr[8]; 240 uint32_t banked_r13[8]; 241 uint32_t banked_r14[8]; 242 243 /* These hold r8-r12. */ 244 uint32_t usr_regs[5]; 245 uint32_t fiq_regs[5]; 246 247 /* cpsr flag cache for faster execution */ 248 uint32_t CF; /* 0 or 1 */ 249 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 250 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 251 uint32_t ZF; /* Z set if zero. */ 252 uint32_t QF; /* 0 or 1 */ 253 uint32_t GE; /* cpsr[19:16] */ 254 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 255 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 256 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 257 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 258 259 uint64_t elr_el[4]; /* AArch64 exception link regs */ 260 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 261 262 /* System control coprocessor (cp15) */ 263 struct { 264 uint32_t c0_cpuid; 265 union { /* Cache size selection */ 266 struct { 267 uint64_t _unused_csselr0; 268 uint64_t csselr_ns; 269 uint64_t _unused_csselr1; 270 uint64_t csselr_s; 271 }; 272 uint64_t csselr_el[4]; 273 }; 274 union { /* System control register. */ 275 struct { 276 uint64_t _unused_sctlr; 277 uint64_t sctlr_ns; 278 uint64_t hsctlr; 279 uint64_t sctlr_s; 280 }; 281 uint64_t sctlr_el[4]; 282 }; 283 uint64_t vsctlr; /* Virtualization System control register. */ 284 uint64_t cpacr_el1; /* Architectural feature access control register */ 285 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 286 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 287 uint64_t sder; /* Secure debug enable register. */ 288 uint32_t nsacr; /* Non-secure access control register. */ 289 union { /* MMU translation table base 0. */ 290 struct { 291 uint64_t _unused_ttbr0_0; 292 uint64_t ttbr0_ns; 293 uint64_t _unused_ttbr0_1; 294 uint64_t ttbr0_s; 295 }; 296 uint64_t ttbr0_el[4]; 297 }; 298 union { /* MMU translation table base 1. */ 299 struct { 300 uint64_t _unused_ttbr1_0; 301 uint64_t ttbr1_ns; 302 uint64_t _unused_ttbr1_1; 303 uint64_t ttbr1_s; 304 }; 305 uint64_t ttbr1_el[4]; 306 }; 307 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 308 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 309 /* MMU translation table base control. */ 310 uint64_t tcr_el[4]; 311 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 312 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 313 uint32_t c2_data; /* MPU data cacheable bits. */ 314 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 315 union { /* MMU domain access control register 316 * MPU write buffer control. 317 */ 318 struct { 319 uint64_t dacr_ns; 320 uint64_t dacr_s; 321 }; 322 struct { 323 uint64_t dacr32_el2; 324 }; 325 }; 326 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 327 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 328 uint64_t hcr_el2; /* Hypervisor configuration register */ 329 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 330 uint64_t scr_el3; /* Secure configuration register. */ 331 union { /* Fault status registers. */ 332 struct { 333 uint64_t ifsr_ns; 334 uint64_t ifsr_s; 335 }; 336 struct { 337 uint64_t ifsr32_el2; 338 }; 339 }; 340 union { 341 struct { 342 uint64_t _unused_dfsr; 343 uint64_t dfsr_ns; 344 uint64_t hsr; 345 uint64_t dfsr_s; 346 }; 347 uint64_t esr_el[4]; 348 }; 349 uint32_t c6_region[8]; /* MPU base/size registers. */ 350 union { /* Fault address registers. */ 351 struct { 352 uint64_t _unused_far0; 353 #if HOST_BIG_ENDIAN 354 uint32_t ifar_ns; 355 uint32_t dfar_ns; 356 uint32_t ifar_s; 357 uint32_t dfar_s; 358 #else 359 uint32_t dfar_ns; 360 uint32_t ifar_ns; 361 uint32_t dfar_s; 362 uint32_t ifar_s; 363 #endif 364 uint64_t _unused_far3; 365 }; 366 uint64_t far_el[4]; 367 }; 368 uint64_t hpfar_el2; 369 uint64_t hstr_el2; 370 union { /* Translation result. */ 371 struct { 372 uint64_t _unused_par_0; 373 uint64_t par_ns; 374 uint64_t _unused_par_1; 375 uint64_t par_s; 376 }; 377 uint64_t par_el[4]; 378 }; 379 380 uint32_t c9_insn; /* Cache lockdown registers. */ 381 uint32_t c9_data; 382 uint64_t c9_pmcr; /* performance monitor control register */ 383 uint64_t c9_pmcnten; /* perf monitor counter enables */ 384 uint64_t c9_pmovsr; /* perf monitor overflow status */ 385 uint64_t c9_pmuserenr; /* perf monitor user enable */ 386 uint64_t c9_pmselr; /* perf monitor counter selection register */ 387 uint64_t c9_pminten; /* perf monitor interrupt enables */ 388 union { /* Memory attribute redirection */ 389 struct { 390 #if HOST_BIG_ENDIAN 391 uint64_t _unused_mair_0; 392 uint32_t mair1_ns; 393 uint32_t mair0_ns; 394 uint64_t _unused_mair_1; 395 uint32_t mair1_s; 396 uint32_t mair0_s; 397 #else 398 uint64_t _unused_mair_0; 399 uint32_t mair0_ns; 400 uint32_t mair1_ns; 401 uint64_t _unused_mair_1; 402 uint32_t mair0_s; 403 uint32_t mair1_s; 404 #endif 405 }; 406 uint64_t mair_el[4]; 407 }; 408 union { /* vector base address register */ 409 struct { 410 uint64_t _unused_vbar; 411 uint64_t vbar_ns; 412 uint64_t hvbar; 413 uint64_t vbar_s; 414 }; 415 uint64_t vbar_el[4]; 416 }; 417 uint32_t mvbar; /* (monitor) vector base address register */ 418 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 419 struct { /* FCSE PID. */ 420 uint32_t fcseidr_ns; 421 uint32_t fcseidr_s; 422 }; 423 union { /* Context ID. */ 424 struct { 425 uint64_t _unused_contextidr_0; 426 uint64_t contextidr_ns; 427 uint64_t _unused_contextidr_1; 428 uint64_t contextidr_s; 429 }; 430 uint64_t contextidr_el[4]; 431 }; 432 union { /* User RW Thread register. */ 433 struct { 434 uint64_t tpidrurw_ns; 435 uint64_t tpidrprw_ns; 436 uint64_t htpidr; 437 uint64_t _tpidr_el3; 438 }; 439 uint64_t tpidr_el[4]; 440 }; 441 uint64_t tpidr2_el0; 442 /* The secure banks of these registers don't map anywhere */ 443 uint64_t tpidrurw_s; 444 uint64_t tpidrprw_s; 445 uint64_t tpidruro_s; 446 447 union { /* User RO Thread register. */ 448 uint64_t tpidruro_ns; 449 uint64_t tpidrro_el[1]; 450 }; 451 uint64_t c14_cntfrq; /* Counter Frequency register */ 452 uint64_t c14_cntkctl; /* Timer Control register */ 453 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 454 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 455 uint64_t cntpoff_el2; /* Counter Physical Offset register */ 456 ARMGenericTimer c14_timer[NUM_GTIMERS]; 457 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 458 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 459 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 460 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 461 uint32_t c15_threadid; /* TI debugger thread-ID. */ 462 uint32_t c15_config_base_address; /* SCU base address. */ 463 uint32_t c15_diagnostic; /* diagnostic register */ 464 uint32_t c15_power_diagnostic; 465 uint32_t c15_power_control; /* power control */ 466 uint64_t dbgbvr[16]; /* breakpoint value registers */ 467 uint64_t dbgbcr[16]; /* breakpoint control registers */ 468 uint64_t dbgwvr[16]; /* watchpoint value registers */ 469 uint64_t dbgwcr[16]; /* watchpoint control registers */ 470 uint64_t dbgclaim; /* DBGCLAIM bits */ 471 uint64_t mdscr_el1; 472 uint64_t oslsr_el1; /* OS Lock Status */ 473 uint64_t osdlr_el1; /* OS DoubleLock status */ 474 uint64_t mdcr_el2; 475 uint64_t mdcr_el3; 476 /* Stores the architectural value of the counter *the last time it was 477 * updated* by pmccntr_op_start. Accesses should always be surrounded 478 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 479 * architecturally-correct value is being read/set. 480 */ 481 uint64_t c15_ccnt; 482 /* Stores the delta between the architectural value and the underlying 483 * cycle count during normal operation. It is used to update c15_ccnt 484 * to be the correct architectural value before accesses. During 485 * accesses, c15_ccnt_delta contains the underlying count being used 486 * for the access, after which it reverts to the delta value in 487 * pmccntr_op_finish. 488 */ 489 uint64_t c15_ccnt_delta; 490 uint64_t c14_pmevcntr[31]; 491 uint64_t c14_pmevcntr_delta[31]; 492 uint64_t c14_pmevtyper[31]; 493 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 494 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 495 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 496 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 497 uint64_t gcr_el1; 498 uint64_t rgsr_el1; 499 500 /* Minimal RAS registers */ 501 uint64_t disr_el1; 502 uint64_t vdisr_el2; 503 uint64_t vsesr_el2; 504 505 /* 506 * Fine-Grained Trap registers. We store these as arrays so the 507 * access checking code doesn't have to manually select 508 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 509 * FEAT_FGT2 will add more elements to these arrays. 510 */ 511 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 512 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 513 uint64_t fgt_exec[1]; /* HFGITR */ 514 515 /* RME registers */ 516 uint64_t gpccr_el3; 517 uint64_t gptbr_el3; 518 uint64_t mfar_el3; 519 520 /* NV2 register */ 521 uint64_t vncr_el2; 522 } cp15; 523 524 struct { 525 /* M profile has up to 4 stack pointers: 526 * a Main Stack Pointer and a Process Stack Pointer for each 527 * of the Secure and Non-Secure states. (If the CPU doesn't support 528 * the security extension then it has only two SPs.) 529 * In QEMU we always store the currently active SP in regs[13], 530 * and the non-active SP for the current security state in 531 * v7m.other_sp. The stack pointers for the inactive security state 532 * are stored in other_ss_msp and other_ss_psp. 533 * switch_v7m_security_state() is responsible for rearranging them 534 * when we change security state. 535 */ 536 uint32_t other_sp; 537 uint32_t other_ss_msp; 538 uint32_t other_ss_psp; 539 uint32_t vecbase[M_REG_NUM_BANKS]; 540 uint32_t basepri[M_REG_NUM_BANKS]; 541 uint32_t control[M_REG_NUM_BANKS]; 542 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 543 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 544 uint32_t hfsr; /* HardFault Status */ 545 uint32_t dfsr; /* Debug Fault Status Register */ 546 uint32_t sfsr; /* Secure Fault Status Register */ 547 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 548 uint32_t bfar; /* BusFault Address */ 549 uint32_t sfar; /* Secure Fault Address Register */ 550 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 551 int exception; 552 uint32_t primask[M_REG_NUM_BANKS]; 553 uint32_t faultmask[M_REG_NUM_BANKS]; 554 uint32_t aircr; /* only holds r/w state if security extn implemented */ 555 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 556 uint32_t csselr[M_REG_NUM_BANKS]; 557 uint32_t scr[M_REG_NUM_BANKS]; 558 uint32_t msplim[M_REG_NUM_BANKS]; 559 uint32_t psplim[M_REG_NUM_BANKS]; 560 uint32_t fpcar[M_REG_NUM_BANKS]; 561 uint32_t fpccr[M_REG_NUM_BANKS]; 562 uint32_t fpdscr[M_REG_NUM_BANKS]; 563 uint32_t cpacr[M_REG_NUM_BANKS]; 564 uint32_t nsacr; 565 uint32_t ltpsize; 566 uint32_t vpr; 567 } v7m; 568 569 /* Information associated with an exception about to be taken: 570 * code which raises an exception must set cs->exception_index and 571 * the relevant parts of this structure; the cpu_do_interrupt function 572 * will then set the guest-visible registers as part of the exception 573 * entry process. 574 */ 575 struct { 576 uint32_t syndrome; /* AArch64 format syndrome register */ 577 uint32_t fsr; /* AArch32 format fault status register info */ 578 uint64_t vaddress; /* virtual addr associated with exception, if any */ 579 uint32_t target_el; /* EL the exception should be targeted for */ 580 /* If we implement EL2 we will also need to store information 581 * about the intermediate physical address for stage 2 faults. 582 */ 583 } exception; 584 585 /* Information associated with an SError */ 586 struct { 587 uint8_t pending; 588 uint8_t has_esr; 589 uint64_t esr; 590 } serror; 591 592 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 593 594 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 595 uint32_t irq_line_state; 596 597 /* Thumb-2 EE state. */ 598 uint32_t teecr; 599 uint32_t teehbr; 600 601 /* VFP coprocessor state. */ 602 struct { 603 ARMVectorReg zregs[32]; 604 605 #ifdef TARGET_AARCH64 606 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 607 #define FFR_PRED_NUM 16 608 ARMPredicateReg pregs[17]; 609 /* Scratch space for aa64 sve predicate temporary. */ 610 ARMPredicateReg preg_tmp; 611 #endif 612 613 /* We store these fpcsr fields separately for convenience. */ 614 uint32_t qc[4] QEMU_ALIGNED(16); 615 int vec_len; 616 int vec_stride; 617 618 uint32_t xregs[16]; 619 620 /* Scratch space for aa32 neon expansion. */ 621 uint32_t scratch[8]; 622 623 /* There are a number of distinct float control structures: 624 * 625 * fp_status: is the "normal" fp status. 626 * fp_status_fp16: used for half-precision calculations 627 * standard_fp_status : the ARM "Standard FPSCR Value" 628 * standard_fp_status_fp16 : used for half-precision 629 * calculations with the ARM "Standard FPSCR Value" 630 * 631 * Half-precision operations are governed by a separate 632 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 633 * status structure to control this. 634 * 635 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 636 * round-to-nearest and is used by any operations (generally 637 * Neon) which the architecture defines as controlled by the 638 * standard FPSCR value rather than the FPSCR. 639 * 640 * The "standard FPSCR but for fp16 ops" is needed because 641 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 642 * using a fixed value for it. 643 * 644 * To avoid having to transfer exception bits around, we simply 645 * say that the FPSCR cumulative exception flags are the logical 646 * OR of the flags in the four fp statuses. This relies on the 647 * only thing which needs to read the exception flags being 648 * an explicit FPSCR read. 649 */ 650 float_status fp_status; 651 float_status fp_status_f16; 652 float_status standard_fp_status; 653 float_status standard_fp_status_f16; 654 655 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 656 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 657 } vfp; 658 659 uint64_t exclusive_addr; 660 uint64_t exclusive_val; 661 /* 662 * Contains the 'val' for the second 64-bit register of LDXP, which comes 663 * from the higher address, not the high part of a complete 128-bit value. 664 * In some ways it might be more convenient to record the exclusive value 665 * as the low and high halves of a 128 bit data value, but the current 666 * semantics of these fields are baked into the migration format. 667 */ 668 uint64_t exclusive_high; 669 670 /* iwMMXt coprocessor state. */ 671 struct { 672 uint64_t regs[16]; 673 uint64_t val; 674 675 uint32_t cregs[16]; 676 } iwmmxt; 677 678 #ifdef TARGET_AARCH64 679 struct { 680 ARMPACKey apia; 681 ARMPACKey apib; 682 ARMPACKey apda; 683 ARMPACKey apdb; 684 ARMPACKey apga; 685 } keys; 686 687 uint64_t scxtnum_el[4]; 688 689 /* 690 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 691 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 692 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 693 * When SVL is less than the architectural maximum, the accessible 694 * storage is restricted, such that if the SVL is X bytes the guest can 695 * see only the bottom X elements of zarray[], and only the least 696 * significant X bytes of each element of the array. (In other words, 697 * the observable part is always square.) 698 * 699 * The ZA storage can also be considered as a set of square tiles of 700 * elements of different sizes. The mapping from tiles to the ZA array 701 * is architecturally defined, such that for tiles of elements of esz 702 * bytes, the Nth row (or "horizontal slice") of tile T is in 703 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 704 * in the ZA storage, because its rows are striped through the ZA array. 705 * 706 * Because this is so large, keep this toward the end of the reset area, 707 * to keep the offsets into the rest of the structure smaller. 708 */ 709 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 710 #endif 711 712 struct CPUBreakpoint *cpu_breakpoint[16]; 713 struct CPUWatchpoint *cpu_watchpoint[16]; 714 715 /* Optional fault info across tlb lookup. */ 716 ARMMMUFaultInfo *tlb_fi; 717 718 /* Fields up to this point are cleared by a CPU reset */ 719 struct {} end_reset_fields; 720 721 /* Fields after this point are preserved across CPU reset. */ 722 723 /* Internal CPU feature flags. */ 724 uint64_t features; 725 726 /* PMSAv7 MPU */ 727 struct { 728 uint32_t *drbar; 729 uint32_t *drsr; 730 uint32_t *dracr; 731 uint32_t rnr[M_REG_NUM_BANKS]; 732 } pmsav7; 733 734 /* PMSAv8 MPU */ 735 struct { 736 /* The PMSAv8 implementation also shares some PMSAv7 config 737 * and state: 738 * pmsav7.rnr (region number register) 739 * pmsav7_dregion (number of configured regions) 740 */ 741 uint32_t *rbar[M_REG_NUM_BANKS]; 742 uint32_t *rlar[M_REG_NUM_BANKS]; 743 uint32_t *hprbar; 744 uint32_t *hprlar; 745 uint32_t mair0[M_REG_NUM_BANKS]; 746 uint32_t mair1[M_REG_NUM_BANKS]; 747 uint32_t hprselr; 748 } pmsav8; 749 750 /* v8M SAU */ 751 struct { 752 uint32_t *rbar; 753 uint32_t *rlar; 754 uint32_t rnr; 755 uint32_t ctrl; 756 } sau; 757 758 #if !defined(CONFIG_USER_ONLY) 759 NVICState *nvic; 760 const struct arm_boot_info *boot_info; 761 /* Store GICv3CPUState to access from this struct */ 762 void *gicv3state; 763 #else /* CONFIG_USER_ONLY */ 764 /* For usermode syscall translation. */ 765 bool eabi; 766 #endif /* CONFIG_USER_ONLY */ 767 768 #ifdef TARGET_TAGGED_ADDRESSES 769 /* Linux syscall tagged address support */ 770 bool tagged_addr_enable; 771 #endif 772 } CPUARMState; 773 774 static inline void set_feature(CPUARMState *env, int feature) 775 { 776 env->features |= 1ULL << feature; 777 } 778 779 static inline void unset_feature(CPUARMState *env, int feature) 780 { 781 env->features &= ~(1ULL << feature); 782 } 783 784 /** 785 * ARMELChangeHookFn: 786 * type of a function which can be registered via arm_register_el_change_hook() 787 * to get callbacks when the CPU changes its exception level or mode. 788 */ 789 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 790 typedef struct ARMELChangeHook ARMELChangeHook; 791 struct ARMELChangeHook { 792 ARMELChangeHookFn *hook; 793 void *opaque; 794 QLIST_ENTRY(ARMELChangeHook) node; 795 }; 796 797 /* These values map onto the return values for 798 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 799 typedef enum ARMPSCIState { 800 PSCI_ON = 0, 801 PSCI_OFF = 1, 802 PSCI_ON_PENDING = 2 803 } ARMPSCIState; 804 805 typedef struct ARMISARegisters ARMISARegisters; 806 807 /* 808 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 809 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 810 * 811 * While processing properties during initialization, corresponding init bits 812 * are set for bits in sve_vq_map that have been set by properties. 813 * 814 * Bits set in supported represent valid vector lengths for the CPU type. 815 */ 816 typedef struct { 817 uint32_t map, init, supported; 818 } ARMVQMap; 819 820 /** 821 * ARMCPU: 822 * @env: #CPUARMState 823 * 824 * An ARM CPU core. 825 */ 826 struct ArchCPU { 827 CPUState parent_obj; 828 829 CPUARMState env; 830 831 /* Coprocessor information */ 832 GHashTable *cp_regs; 833 /* For marshalling (mostly coprocessor) register state between the 834 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 835 * we use these arrays. 836 */ 837 /* List of register indexes managed via these arrays; (full KVM style 838 * 64 bit indexes, not CPRegInfo 32 bit indexes) 839 */ 840 uint64_t *cpreg_indexes; 841 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 842 uint64_t *cpreg_values; 843 /* Length of the indexes, values, reset_values arrays */ 844 int32_t cpreg_array_len; 845 /* These are used only for migration: incoming data arrives in 846 * these fields and is sanity checked in post_load before copying 847 * to the working data structures above. 848 */ 849 uint64_t *cpreg_vmstate_indexes; 850 uint64_t *cpreg_vmstate_values; 851 int32_t cpreg_vmstate_array_len; 852 853 DynamicGDBFeatureInfo dyn_sysreg_feature; 854 DynamicGDBFeatureInfo dyn_svereg_feature; 855 DynamicGDBFeatureInfo dyn_m_systemreg_feature; 856 DynamicGDBFeatureInfo dyn_m_secextreg_feature; 857 858 /* Timers used by the generic (architected) timer */ 859 QEMUTimer *gt_timer[NUM_GTIMERS]; 860 /* 861 * Timer used by the PMU. Its state is restored after migration by 862 * pmu_op_finish() - it does not need other handling during migration 863 */ 864 QEMUTimer *pmu_timer; 865 /* GPIO outputs for generic timer */ 866 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 867 /* GPIO output for GICv3 maintenance interrupt signal */ 868 qemu_irq gicv3_maintenance_interrupt; 869 /* GPIO output for the PMU interrupt */ 870 qemu_irq pmu_interrupt; 871 872 /* MemoryRegion to use for secure physical accesses */ 873 MemoryRegion *secure_memory; 874 875 /* MemoryRegion to use for allocation tag accesses */ 876 MemoryRegion *tag_memory; 877 MemoryRegion *secure_tag_memory; 878 879 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 880 Object *idau; 881 882 /* 'compatible' string for this CPU for Linux device trees */ 883 const char *dtb_compatible; 884 885 /* PSCI version for this CPU 886 * Bits[31:16] = Major Version 887 * Bits[15:0] = Minor Version 888 */ 889 uint32_t psci_version; 890 891 /* Current power state, access guarded by BQL */ 892 ARMPSCIState power_state; 893 894 /* CPU has virtualization extension */ 895 bool has_el2; 896 /* CPU has security extension */ 897 bool has_el3; 898 /* CPU has PMU (Performance Monitor Unit) */ 899 bool has_pmu; 900 /* CPU has VFP */ 901 bool has_vfp; 902 /* CPU has 32 VFP registers */ 903 bool has_vfp_d32; 904 /* CPU has Neon */ 905 bool has_neon; 906 /* CPU has M-profile DSP extension */ 907 bool has_dsp; 908 909 /* CPU has memory protection unit */ 910 bool has_mpu; 911 /* PMSAv7 MPU number of supported regions */ 912 uint32_t pmsav7_dregion; 913 /* PMSAv8 MPU number of supported hyp regions */ 914 uint32_t pmsav8r_hdregion; 915 /* v8M SAU number of supported regions */ 916 uint32_t sau_sregion; 917 918 /* PSCI conduit used to invoke PSCI methods 919 * 0 - disabled, 1 - smc, 2 - hvc 920 */ 921 uint32_t psci_conduit; 922 923 /* For v8M, initial value of the Secure VTOR */ 924 uint32_t init_svtor; 925 /* For v8M, initial value of the Non-secure VTOR */ 926 uint32_t init_nsvtor; 927 928 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 929 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 930 */ 931 uint32_t kvm_target; 932 933 #ifdef CONFIG_KVM 934 /* KVM init features for this CPU */ 935 uint32_t kvm_init_features[7]; 936 937 /* KVM CPU state */ 938 939 /* KVM virtual time adjustment */ 940 bool kvm_adjvtime; 941 bool kvm_vtime_dirty; 942 uint64_t kvm_vtime; 943 944 /* KVM steal time */ 945 OnOffAuto kvm_steal_time; 946 #endif /* CONFIG_KVM */ 947 948 /* Uniprocessor system with MP extensions */ 949 bool mp_is_up; 950 951 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 952 * and the probe failed (so we need to report the error in realize) 953 */ 954 bool host_cpu_probe_failed; 955 956 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 957 * register. 958 */ 959 int32_t core_count; 960 961 /* The instance init functions for implementation-specific subclasses 962 * set these fields to specify the implementation-dependent values of 963 * various constant registers and reset values of non-constant 964 * registers. 965 * Some of these might become QOM properties eventually. 966 * Field names match the official register names as defined in the 967 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 968 * is used for reset values of non-constant registers; no reset_ 969 * prefix means a constant register. 970 * Some of these registers are split out into a substructure that 971 * is shared with the translators to control the ISA. 972 * 973 * Note that if you add an ID register to the ARMISARegisters struct 974 * you need to also update the 32-bit and 64-bit versions of the 975 * kvm_arm_get_host_cpu_features() function to correctly populate the 976 * field by reading the value from the KVM vCPU. 977 */ 978 struct ARMISARegisters { 979 uint32_t id_isar0; 980 uint32_t id_isar1; 981 uint32_t id_isar2; 982 uint32_t id_isar3; 983 uint32_t id_isar4; 984 uint32_t id_isar5; 985 uint32_t id_isar6; 986 uint32_t id_mmfr0; 987 uint32_t id_mmfr1; 988 uint32_t id_mmfr2; 989 uint32_t id_mmfr3; 990 uint32_t id_mmfr4; 991 uint32_t id_mmfr5; 992 uint32_t id_pfr0; 993 uint32_t id_pfr1; 994 uint32_t id_pfr2; 995 uint32_t mvfr0; 996 uint32_t mvfr1; 997 uint32_t mvfr2; 998 uint32_t id_dfr0; 999 uint32_t id_dfr1; 1000 uint32_t dbgdidr; 1001 uint32_t dbgdevid; 1002 uint32_t dbgdevid1; 1003 uint64_t id_aa64isar0; 1004 uint64_t id_aa64isar1; 1005 uint64_t id_aa64isar2; 1006 uint64_t id_aa64pfr0; 1007 uint64_t id_aa64pfr1; 1008 uint64_t id_aa64mmfr0; 1009 uint64_t id_aa64mmfr1; 1010 uint64_t id_aa64mmfr2; 1011 uint64_t id_aa64dfr0; 1012 uint64_t id_aa64dfr1; 1013 uint64_t id_aa64zfr0; 1014 uint64_t id_aa64smfr0; 1015 uint64_t reset_pmcr_el0; 1016 } isar; 1017 uint64_t midr; 1018 uint32_t revidr; 1019 uint32_t reset_fpsid; 1020 uint64_t ctr; 1021 uint32_t reset_sctlr; 1022 uint64_t pmceid0; 1023 uint64_t pmceid1; 1024 uint32_t id_afr0; 1025 uint64_t id_aa64afr0; 1026 uint64_t id_aa64afr1; 1027 uint64_t clidr; 1028 uint64_t mp_affinity; /* MP ID without feature bits */ 1029 /* The elements of this array are the CCSIDR values for each cache, 1030 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1031 */ 1032 uint64_t ccsidr[16]; 1033 uint64_t reset_cbar; 1034 uint32_t reset_auxcr; 1035 bool reset_hivecs; 1036 uint8_t reset_l0gptsz; 1037 1038 /* 1039 * Intermediate values used during property parsing. 1040 * Once finalized, the values should be read from ID_AA64*. 1041 */ 1042 bool prop_pauth; 1043 bool prop_pauth_impdef; 1044 bool prop_pauth_qarma3; 1045 bool prop_lpa2; 1046 1047 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1048 uint8_t dcz_blocksize; 1049 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1050 uint8_t gm_blocksize; 1051 1052 uint64_t rvbar_prop; /* Property/input signals. */ 1053 1054 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1055 int gic_num_lrs; /* number of list registers */ 1056 int gic_vpribits; /* number of virtual priority bits */ 1057 int gic_vprebits; /* number of virtual preemption bits */ 1058 int gic_pribits; /* number of physical priority bits */ 1059 1060 /* Whether the cfgend input is high (i.e. this CPU should reset into 1061 * big-endian mode). This setting isn't used directly: instead it modifies 1062 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1063 * architecture version. 1064 */ 1065 bool cfgend; 1066 1067 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1068 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1069 1070 int32_t node_id; /* NUMA node this CPU belongs to */ 1071 1072 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1073 uint8_t device_irq_level; 1074 1075 /* Used to set the maximum vector length the cpu will support. */ 1076 uint32_t sve_max_vq; 1077 1078 #ifdef CONFIG_USER_ONLY 1079 /* Used to set the default vector length at process start. */ 1080 uint32_t sve_default_vq; 1081 uint32_t sme_default_vq; 1082 #endif 1083 1084 ARMVQMap sve_vq; 1085 ARMVQMap sme_vq; 1086 1087 /* Generic timer counter frequency, in Hz */ 1088 uint64_t gt_cntfrq_hz; 1089 }; 1090 1091 typedef struct ARMCPUInfo { 1092 const char *name; 1093 void (*initfn)(Object *obj); 1094 void (*class_init)(ObjectClass *oc, void *data); 1095 } ARMCPUInfo; 1096 1097 /** 1098 * ARMCPUClass: 1099 * @parent_realize: The parent class' realize handler. 1100 * @parent_phases: The parent class' reset phase handlers. 1101 * 1102 * An ARM CPU model. 1103 */ 1104 struct ARMCPUClass { 1105 CPUClass parent_class; 1106 1107 const ARMCPUInfo *info; 1108 DeviceRealize parent_realize; 1109 ResettablePhases parent_phases; 1110 }; 1111 1112 struct AArch64CPUClass { 1113 ARMCPUClass parent_class; 1114 }; 1115 1116 /* Callback functions for the generic timer's timers. */ 1117 void arm_gt_ptimer_cb(void *opaque); 1118 void arm_gt_vtimer_cb(void *opaque); 1119 void arm_gt_htimer_cb(void *opaque); 1120 void arm_gt_stimer_cb(void *opaque); 1121 void arm_gt_hvtimer_cb(void *opaque); 1122 1123 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1124 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1125 1126 void arm_cpu_post_init(Object *obj); 1127 1128 #define ARM_AFF0_SHIFT 0 1129 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1130 #define ARM_AFF1_SHIFT 8 1131 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1132 #define ARM_AFF2_SHIFT 16 1133 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1134 #define ARM_AFF3_SHIFT 32 1135 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1136 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1137 1138 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1139 #define ARM64_AFFINITY_MASK \ 1140 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1141 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1142 1143 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1144 1145 #ifndef CONFIG_USER_ONLY 1146 extern const VMStateDescription vmstate_arm_cpu; 1147 1148 void arm_cpu_do_interrupt(CPUState *cpu); 1149 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1150 1151 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1152 MemTxAttrs *attrs); 1153 #endif /* !CONFIG_USER_ONLY */ 1154 1155 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1156 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1157 1158 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1159 int cpuid, DumpState *s); 1160 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1161 int cpuid, DumpState *s); 1162 1163 /** 1164 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1165 * @cpu: CPU (which must have been freshly reset) 1166 * @target_el: exception level to put the CPU into 1167 * @secure: whether to put the CPU in secure state 1168 * 1169 * When QEMU is directly running a guest kernel at a lower level than 1170 * EL3 it implicitly emulates some aspects of the guest firmware. 1171 * This includes that on reset we need to configure the parts of the 1172 * CPU corresponding to EL3 so that the real guest code can run at its 1173 * lower exception level. This function does that post-reset CPU setup, 1174 * for when we do direct boot of a guest kernel, and for when we 1175 * emulate PSCI and similar firmware interfaces starting a CPU at a 1176 * lower exception level. 1177 * 1178 * @target_el must be an EL implemented by the CPU between 1 and 3. 1179 * We do not support dropping into a Secure EL other than 3. 1180 * 1181 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1182 */ 1183 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1184 1185 #ifdef TARGET_AARCH64 1186 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1187 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1188 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1189 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1190 int new_el, bool el0_a64); 1191 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1192 1193 /* 1194 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1195 * The byte at offset i from the start of the in-memory representation contains 1196 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1197 * lowest offsets are stored in the lowest memory addresses, then that nearly 1198 * matches QEMU's representation, which is to use an array of host-endian 1199 * uint64_t's, where the lower offsets are at the lower indices. To complete 1200 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1201 */ 1202 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1203 { 1204 #if HOST_BIG_ENDIAN 1205 int i; 1206 1207 for (i = 0; i < nr; ++i) { 1208 dst[i] = bswap64(src[i]); 1209 } 1210 1211 return dst; 1212 #else 1213 return src; 1214 #endif 1215 } 1216 1217 #else 1218 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1219 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1220 int n, bool a) 1221 { } 1222 #endif 1223 1224 void aarch64_sync_32_to_64(CPUARMState *env); 1225 void aarch64_sync_64_to_32(CPUARMState *env); 1226 1227 int fp_exception_el(CPUARMState *env, int cur_el); 1228 int sve_exception_el(CPUARMState *env, int cur_el); 1229 int sme_exception_el(CPUARMState *env, int cur_el); 1230 1231 /** 1232 * sve_vqm1_for_el_sm: 1233 * @env: CPUARMState 1234 * @el: exception level 1235 * @sm: streaming mode 1236 * 1237 * Compute the current vector length for @el & @sm, in units of 1238 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1239 * If @sm, compute for SVL, otherwise NVL. 1240 */ 1241 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1242 1243 /* Likewise, but using @sm = PSTATE.SM. */ 1244 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1245 1246 static inline bool is_a64(CPUARMState *env) 1247 { 1248 return env->aarch64; 1249 } 1250 1251 /** 1252 * pmu_op_start/finish 1253 * @env: CPUARMState 1254 * 1255 * Convert all PMU counters between their delta form (the typical mode when 1256 * they are enabled) and the guest-visible values. These two calls must 1257 * surround any action which might affect the counters. 1258 */ 1259 void pmu_op_start(CPUARMState *env); 1260 void pmu_op_finish(CPUARMState *env); 1261 1262 /* 1263 * Called when a PMU counter is due to overflow 1264 */ 1265 void arm_pmu_timer_cb(void *opaque); 1266 1267 /** 1268 * Functions to register as EL change hooks for PMU mode filtering 1269 */ 1270 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1271 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1272 1273 /* 1274 * pmu_init 1275 * @cpu: ARMCPU 1276 * 1277 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1278 * for the current configuration 1279 */ 1280 void pmu_init(ARMCPU *cpu); 1281 1282 /* SCTLR bit meanings. Several bits have been reused in newer 1283 * versions of the architecture; in that case we define constants 1284 * for both old and new bit meanings. Code which tests against those 1285 * bits should probably check or otherwise arrange that the CPU 1286 * is the architectural version it expects. 1287 */ 1288 #define SCTLR_M (1U << 0) 1289 #define SCTLR_A (1U << 1) 1290 #define SCTLR_C (1U << 2) 1291 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1292 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1293 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1294 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1295 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1296 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1297 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1298 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1299 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1300 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1301 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1302 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1303 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1304 #define SCTLR_SED (1U << 8) /* v8 onward */ 1305 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1306 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1307 #define SCTLR_F (1U << 10) /* up to v6 */ 1308 #define SCTLR_SW (1U << 10) /* v7 */ 1309 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1310 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1311 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1312 #define SCTLR_I (1U << 12) 1313 #define SCTLR_V (1U << 13) /* AArch32 only */ 1314 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1315 #define SCTLR_RR (1U << 14) /* up to v7 */ 1316 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1317 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1318 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1319 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1320 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1321 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1322 #define SCTLR_BR (1U << 17) /* PMSA only */ 1323 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1324 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1325 #define SCTLR_WXN (1U << 19) 1326 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1327 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1328 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1329 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1330 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1331 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1332 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1333 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1334 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1335 #define SCTLR_VE (1U << 24) /* up to v7 */ 1336 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1337 #define SCTLR_EE (1U << 25) 1338 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1339 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1340 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1341 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1342 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1343 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1344 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1345 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1346 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1347 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1348 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1349 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1350 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1351 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1352 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1353 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1354 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1355 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1356 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1357 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1358 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1359 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1360 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1361 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1362 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1363 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1364 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1365 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1366 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1367 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1368 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1369 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1370 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1371 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1372 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1373 1374 #define CPSR_M (0x1fU) 1375 #define CPSR_T (1U << 5) 1376 #define CPSR_F (1U << 6) 1377 #define CPSR_I (1U << 7) 1378 #define CPSR_A (1U << 8) 1379 #define CPSR_E (1U << 9) 1380 #define CPSR_IT_2_7 (0xfc00U) 1381 #define CPSR_GE (0xfU << 16) 1382 #define CPSR_IL (1U << 20) 1383 #define CPSR_DIT (1U << 21) 1384 #define CPSR_PAN (1U << 22) 1385 #define CPSR_SSBS (1U << 23) 1386 #define CPSR_J (1U << 24) 1387 #define CPSR_IT_0_1 (3U << 25) 1388 #define CPSR_Q (1U << 27) 1389 #define CPSR_V (1U << 28) 1390 #define CPSR_C (1U << 29) 1391 #define CPSR_Z (1U << 30) 1392 #define CPSR_N (1U << 31) 1393 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1394 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1395 1396 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1397 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1398 | CPSR_NZCV) 1399 /* Bits writable in user mode. */ 1400 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1401 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1402 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1403 1404 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1405 #define XPSR_EXCP 0x1ffU 1406 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1407 #define XPSR_IT_2_7 CPSR_IT_2_7 1408 #define XPSR_GE CPSR_GE 1409 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1410 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1411 #define XPSR_IT_0_1 CPSR_IT_0_1 1412 #define XPSR_Q CPSR_Q 1413 #define XPSR_V CPSR_V 1414 #define XPSR_C CPSR_C 1415 #define XPSR_Z CPSR_Z 1416 #define XPSR_N CPSR_N 1417 #define XPSR_NZCV CPSR_NZCV 1418 #define XPSR_IT CPSR_IT 1419 1420 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1421 * Only these are valid when in AArch64 mode; in 1422 * AArch32 mode SPSRs are basically CPSR-format. 1423 */ 1424 #define PSTATE_SP (1U) 1425 #define PSTATE_M (0xFU) 1426 #define PSTATE_nRW (1U << 4) 1427 #define PSTATE_F (1U << 6) 1428 #define PSTATE_I (1U << 7) 1429 #define PSTATE_A (1U << 8) 1430 #define PSTATE_D (1U << 9) 1431 #define PSTATE_BTYPE (3U << 10) 1432 #define PSTATE_SSBS (1U << 12) 1433 #define PSTATE_IL (1U << 20) 1434 #define PSTATE_SS (1U << 21) 1435 #define PSTATE_PAN (1U << 22) 1436 #define PSTATE_UAO (1U << 23) 1437 #define PSTATE_DIT (1U << 24) 1438 #define PSTATE_TCO (1U << 25) 1439 #define PSTATE_V (1U << 28) 1440 #define PSTATE_C (1U << 29) 1441 #define PSTATE_Z (1U << 30) 1442 #define PSTATE_N (1U << 31) 1443 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1444 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1445 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1446 /* Mode values for AArch64 */ 1447 #define PSTATE_MODE_EL3h 13 1448 #define PSTATE_MODE_EL3t 12 1449 #define PSTATE_MODE_EL2h 9 1450 #define PSTATE_MODE_EL2t 8 1451 #define PSTATE_MODE_EL1h 5 1452 #define PSTATE_MODE_EL1t 4 1453 #define PSTATE_MODE_EL0t 0 1454 1455 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1456 FIELD(SVCR, SM, 0, 1) 1457 FIELD(SVCR, ZA, 1, 1) 1458 1459 /* Fields for SMCR_ELx. */ 1460 FIELD(SMCR, LEN, 0, 4) 1461 FIELD(SMCR, FA64, 31, 1) 1462 1463 /* Write a new value to v7m.exception, thus transitioning into or out 1464 * of Handler mode; this may result in a change of active stack pointer. 1465 */ 1466 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1467 1468 /* Map EL and handler into a PSTATE_MODE. */ 1469 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1470 { 1471 return (el << 2) | handler; 1472 } 1473 1474 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1475 * interprocessing, so we don't attempt to sync with the cpsr state used by 1476 * the 32 bit decoder. 1477 */ 1478 static inline uint32_t pstate_read(CPUARMState *env) 1479 { 1480 int ZF; 1481 1482 ZF = (env->ZF == 0); 1483 return (env->NF & 0x80000000) | (ZF << 30) 1484 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1485 | env->pstate | env->daif | (env->btype << 10); 1486 } 1487 1488 static inline void pstate_write(CPUARMState *env, uint32_t val) 1489 { 1490 env->ZF = (~val) & PSTATE_Z; 1491 env->NF = val; 1492 env->CF = (val >> 29) & 1; 1493 env->VF = (val << 3) & 0x80000000; 1494 env->daif = val & PSTATE_DAIF; 1495 env->btype = (val >> 10) & 3; 1496 env->pstate = val & ~CACHED_PSTATE_BITS; 1497 } 1498 1499 /* Return the current CPSR value. */ 1500 uint32_t cpsr_read(CPUARMState *env); 1501 1502 typedef enum CPSRWriteType { 1503 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1504 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1505 CPSRWriteRaw = 2, 1506 /* trust values, no reg bank switch, no hflags rebuild */ 1507 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1508 } CPSRWriteType; 1509 1510 /* 1511 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1512 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1513 * correspond to TB flags bits cached in the hflags, unless @write_type 1514 * is CPSRWriteRaw. 1515 */ 1516 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1517 CPSRWriteType write_type); 1518 1519 /* Return the current xPSR value. */ 1520 static inline uint32_t xpsr_read(CPUARMState *env) 1521 { 1522 int ZF; 1523 ZF = (env->ZF == 0); 1524 return (env->NF & 0x80000000) | (ZF << 30) 1525 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1526 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1527 | ((env->condexec_bits & 0xfc) << 8) 1528 | (env->GE << 16) 1529 | env->v7m.exception; 1530 } 1531 1532 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1533 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1534 { 1535 if (mask & XPSR_NZCV) { 1536 env->ZF = (~val) & XPSR_Z; 1537 env->NF = val; 1538 env->CF = (val >> 29) & 1; 1539 env->VF = (val << 3) & 0x80000000; 1540 } 1541 if (mask & XPSR_Q) { 1542 env->QF = ((val & XPSR_Q) != 0); 1543 } 1544 if (mask & XPSR_GE) { 1545 env->GE = (val & XPSR_GE) >> 16; 1546 } 1547 #ifndef CONFIG_USER_ONLY 1548 if (mask & XPSR_T) { 1549 env->thumb = ((val & XPSR_T) != 0); 1550 } 1551 if (mask & XPSR_IT_0_1) { 1552 env->condexec_bits &= ~3; 1553 env->condexec_bits |= (val >> 25) & 3; 1554 } 1555 if (mask & XPSR_IT_2_7) { 1556 env->condexec_bits &= 3; 1557 env->condexec_bits |= (val >> 8) & 0xfc; 1558 } 1559 if (mask & XPSR_EXCP) { 1560 /* Note that this only happens on exception exit */ 1561 write_v7m_exception(env, val & XPSR_EXCP); 1562 } 1563 #endif 1564 } 1565 1566 #define HCR_VM (1ULL << 0) 1567 #define HCR_SWIO (1ULL << 1) 1568 #define HCR_PTW (1ULL << 2) 1569 #define HCR_FMO (1ULL << 3) 1570 #define HCR_IMO (1ULL << 4) 1571 #define HCR_AMO (1ULL << 5) 1572 #define HCR_VF (1ULL << 6) 1573 #define HCR_VI (1ULL << 7) 1574 #define HCR_VSE (1ULL << 8) 1575 #define HCR_FB (1ULL << 9) 1576 #define HCR_BSU_MASK (3ULL << 10) 1577 #define HCR_DC (1ULL << 12) 1578 #define HCR_TWI (1ULL << 13) 1579 #define HCR_TWE (1ULL << 14) 1580 #define HCR_TID0 (1ULL << 15) 1581 #define HCR_TID1 (1ULL << 16) 1582 #define HCR_TID2 (1ULL << 17) 1583 #define HCR_TID3 (1ULL << 18) 1584 #define HCR_TSC (1ULL << 19) 1585 #define HCR_TIDCP (1ULL << 20) 1586 #define HCR_TACR (1ULL << 21) 1587 #define HCR_TSW (1ULL << 22) 1588 #define HCR_TPCP (1ULL << 23) 1589 #define HCR_TPU (1ULL << 24) 1590 #define HCR_TTLB (1ULL << 25) 1591 #define HCR_TVM (1ULL << 26) 1592 #define HCR_TGE (1ULL << 27) 1593 #define HCR_TDZ (1ULL << 28) 1594 #define HCR_HCD (1ULL << 29) 1595 #define HCR_TRVM (1ULL << 30) 1596 #define HCR_RW (1ULL << 31) 1597 #define HCR_CD (1ULL << 32) 1598 #define HCR_ID (1ULL << 33) 1599 #define HCR_E2H (1ULL << 34) 1600 #define HCR_TLOR (1ULL << 35) 1601 #define HCR_TERR (1ULL << 36) 1602 #define HCR_TEA (1ULL << 37) 1603 #define HCR_MIOCNCE (1ULL << 38) 1604 #define HCR_TME (1ULL << 39) 1605 #define HCR_APK (1ULL << 40) 1606 #define HCR_API (1ULL << 41) 1607 #define HCR_NV (1ULL << 42) 1608 #define HCR_NV1 (1ULL << 43) 1609 #define HCR_AT (1ULL << 44) 1610 #define HCR_NV2 (1ULL << 45) 1611 #define HCR_FWB (1ULL << 46) 1612 #define HCR_FIEN (1ULL << 47) 1613 #define HCR_GPF (1ULL << 48) 1614 #define HCR_TID4 (1ULL << 49) 1615 #define HCR_TICAB (1ULL << 50) 1616 #define HCR_AMVOFFEN (1ULL << 51) 1617 #define HCR_TOCU (1ULL << 52) 1618 #define HCR_ENSCXT (1ULL << 53) 1619 #define HCR_TTLBIS (1ULL << 54) 1620 #define HCR_TTLBOS (1ULL << 55) 1621 #define HCR_ATA (1ULL << 56) 1622 #define HCR_DCT (1ULL << 57) 1623 #define HCR_TID5 (1ULL << 58) 1624 #define HCR_TWEDEN (1ULL << 59) 1625 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1626 1627 #define SCR_NS (1ULL << 0) 1628 #define SCR_IRQ (1ULL << 1) 1629 #define SCR_FIQ (1ULL << 2) 1630 #define SCR_EA (1ULL << 3) 1631 #define SCR_FW (1ULL << 4) 1632 #define SCR_AW (1ULL << 5) 1633 #define SCR_NET (1ULL << 6) 1634 #define SCR_SMD (1ULL << 7) 1635 #define SCR_HCE (1ULL << 8) 1636 #define SCR_SIF (1ULL << 9) 1637 #define SCR_RW (1ULL << 10) 1638 #define SCR_ST (1ULL << 11) 1639 #define SCR_TWI (1ULL << 12) 1640 #define SCR_TWE (1ULL << 13) 1641 #define SCR_TLOR (1ULL << 14) 1642 #define SCR_TERR (1ULL << 15) 1643 #define SCR_APK (1ULL << 16) 1644 #define SCR_API (1ULL << 17) 1645 #define SCR_EEL2 (1ULL << 18) 1646 #define SCR_EASE (1ULL << 19) 1647 #define SCR_NMEA (1ULL << 20) 1648 #define SCR_FIEN (1ULL << 21) 1649 #define SCR_ENSCXT (1ULL << 25) 1650 #define SCR_ATA (1ULL << 26) 1651 #define SCR_FGTEN (1ULL << 27) 1652 #define SCR_ECVEN (1ULL << 28) 1653 #define SCR_TWEDEN (1ULL << 29) 1654 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1655 #define SCR_TME (1ULL << 34) 1656 #define SCR_AMVOFFEN (1ULL << 35) 1657 #define SCR_ENAS0 (1ULL << 36) 1658 #define SCR_ADEN (1ULL << 37) 1659 #define SCR_HXEN (1ULL << 38) 1660 #define SCR_TRNDR (1ULL << 40) 1661 #define SCR_ENTP2 (1ULL << 41) 1662 #define SCR_GPF (1ULL << 48) 1663 #define SCR_NSE (1ULL << 62) 1664 1665 /* Return the current FPSCR value. */ 1666 uint32_t vfp_get_fpscr(CPUARMState *env); 1667 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1668 1669 /* FPCR, Floating Point Control Register 1670 * FPSR, Floating Poiht Status Register 1671 * 1672 * For A64 the FPSCR is split into two logically distinct registers, 1673 * FPCR and FPSR. However since they still use non-overlapping bits 1674 * we store the underlying state in fpscr and just mask on read/write. 1675 */ 1676 #define FPSR_MASK 0xf800009f 1677 #define FPCR_MASK 0x07ff9f00 1678 1679 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1680 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1681 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1682 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1683 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1684 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1685 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1686 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1687 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1688 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1689 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1690 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1691 #define FPCR_V (1 << 28) /* FP overflow flag */ 1692 #define FPCR_C (1 << 29) /* FP carry flag */ 1693 #define FPCR_Z (1 << 30) /* FP zero flag */ 1694 #define FPCR_N (1 << 31) /* FP negative flag */ 1695 1696 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1697 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1698 #define FPCR_LTPSIZE_LENGTH 3 1699 1700 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1701 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1702 1703 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1704 { 1705 return vfp_get_fpscr(env) & FPSR_MASK; 1706 } 1707 1708 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1709 { 1710 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1711 vfp_set_fpscr(env, new_fpscr); 1712 } 1713 1714 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1715 { 1716 return vfp_get_fpscr(env) & FPCR_MASK; 1717 } 1718 1719 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1720 { 1721 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1722 vfp_set_fpscr(env, new_fpscr); 1723 } 1724 1725 enum arm_cpu_mode { 1726 ARM_CPU_MODE_USR = 0x10, 1727 ARM_CPU_MODE_FIQ = 0x11, 1728 ARM_CPU_MODE_IRQ = 0x12, 1729 ARM_CPU_MODE_SVC = 0x13, 1730 ARM_CPU_MODE_MON = 0x16, 1731 ARM_CPU_MODE_ABT = 0x17, 1732 ARM_CPU_MODE_HYP = 0x1a, 1733 ARM_CPU_MODE_UND = 0x1b, 1734 ARM_CPU_MODE_SYS = 0x1f 1735 }; 1736 1737 /* VFP system registers. */ 1738 #define ARM_VFP_FPSID 0 1739 #define ARM_VFP_FPSCR 1 1740 #define ARM_VFP_MVFR2 5 1741 #define ARM_VFP_MVFR1 6 1742 #define ARM_VFP_MVFR0 7 1743 #define ARM_VFP_FPEXC 8 1744 #define ARM_VFP_FPINST 9 1745 #define ARM_VFP_FPINST2 10 1746 /* These ones are M-profile only */ 1747 #define ARM_VFP_FPSCR_NZCVQC 2 1748 #define ARM_VFP_VPR 12 1749 #define ARM_VFP_P0 13 1750 #define ARM_VFP_FPCXT_NS 14 1751 #define ARM_VFP_FPCXT_S 15 1752 1753 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1754 #define QEMU_VFP_FPSCR_NZCV 0xffff 1755 1756 /* iwMMXt coprocessor control registers. */ 1757 #define ARM_IWMMXT_wCID 0 1758 #define ARM_IWMMXT_wCon 1 1759 #define ARM_IWMMXT_wCSSF 2 1760 #define ARM_IWMMXT_wCASF 3 1761 #define ARM_IWMMXT_wCGR0 8 1762 #define ARM_IWMMXT_wCGR1 9 1763 #define ARM_IWMMXT_wCGR2 10 1764 #define ARM_IWMMXT_wCGR3 11 1765 1766 /* V7M CCR bits */ 1767 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1768 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1769 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1770 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1771 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1772 FIELD(V7M_CCR, STKALIGN, 9, 1) 1773 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1774 FIELD(V7M_CCR, DC, 16, 1) 1775 FIELD(V7M_CCR, IC, 17, 1) 1776 FIELD(V7M_CCR, BP, 18, 1) 1777 FIELD(V7M_CCR, LOB, 19, 1) 1778 FIELD(V7M_CCR, TRD, 20, 1) 1779 1780 /* V7M SCR bits */ 1781 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1782 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1783 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1784 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1785 1786 /* V7M AIRCR bits */ 1787 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1788 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1789 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1790 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1791 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1792 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1793 FIELD(V7M_AIRCR, PRIS, 14, 1) 1794 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1795 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1796 1797 /* V7M CFSR bits for MMFSR */ 1798 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1799 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1800 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1801 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1802 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1803 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1804 1805 /* V7M CFSR bits for BFSR */ 1806 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1807 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1808 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1809 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1810 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1811 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1812 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1813 1814 /* V7M CFSR bits for UFSR */ 1815 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1816 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1817 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1818 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1819 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1820 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1821 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1822 1823 /* V7M CFSR bit masks covering all of the subregister bits */ 1824 FIELD(V7M_CFSR, MMFSR, 0, 8) 1825 FIELD(V7M_CFSR, BFSR, 8, 8) 1826 FIELD(V7M_CFSR, UFSR, 16, 16) 1827 1828 /* V7M HFSR bits */ 1829 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1830 FIELD(V7M_HFSR, FORCED, 30, 1) 1831 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1832 1833 /* V7M DFSR bits */ 1834 FIELD(V7M_DFSR, HALTED, 0, 1) 1835 FIELD(V7M_DFSR, BKPT, 1, 1) 1836 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1837 FIELD(V7M_DFSR, VCATCH, 3, 1) 1838 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1839 1840 /* V7M SFSR bits */ 1841 FIELD(V7M_SFSR, INVEP, 0, 1) 1842 FIELD(V7M_SFSR, INVIS, 1, 1) 1843 FIELD(V7M_SFSR, INVER, 2, 1) 1844 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1845 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1846 FIELD(V7M_SFSR, LSPERR, 5, 1) 1847 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1848 FIELD(V7M_SFSR, LSERR, 7, 1) 1849 1850 /* v7M MPU_CTRL bits */ 1851 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1852 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1853 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1854 1855 /* v7M CLIDR bits */ 1856 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1857 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1858 FIELD(V7M_CLIDR, LOC, 24, 3) 1859 FIELD(V7M_CLIDR, LOUU, 27, 3) 1860 FIELD(V7M_CLIDR, ICB, 30, 2) 1861 1862 FIELD(V7M_CSSELR, IND, 0, 1) 1863 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1864 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1865 * define a mask for this and check that it doesn't permit running off 1866 * the end of the array. 1867 */ 1868 FIELD(V7M_CSSELR, INDEX, 0, 4) 1869 1870 /* v7M FPCCR bits */ 1871 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1872 FIELD(V7M_FPCCR, USER, 1, 1) 1873 FIELD(V7M_FPCCR, S, 2, 1) 1874 FIELD(V7M_FPCCR, THREAD, 3, 1) 1875 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1876 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1877 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1878 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1879 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1880 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1881 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1882 FIELD(V7M_FPCCR, RES0, 11, 15) 1883 FIELD(V7M_FPCCR, TS, 26, 1) 1884 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1885 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1886 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1887 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1888 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1889 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1890 #define R_V7M_FPCCR_BANKED_MASK \ 1891 (R_V7M_FPCCR_LSPACT_MASK | \ 1892 R_V7M_FPCCR_USER_MASK | \ 1893 R_V7M_FPCCR_THREAD_MASK | \ 1894 R_V7M_FPCCR_MMRDY_MASK | \ 1895 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1896 R_V7M_FPCCR_UFRDY_MASK | \ 1897 R_V7M_FPCCR_ASPEN_MASK) 1898 1899 /* v7M VPR bits */ 1900 FIELD(V7M_VPR, P0, 0, 16) 1901 FIELD(V7M_VPR, MASK01, 16, 4) 1902 FIELD(V7M_VPR, MASK23, 20, 4) 1903 1904 /* 1905 * System register ID fields. 1906 */ 1907 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1908 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1909 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1910 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1911 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1912 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1913 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1914 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1915 FIELD(CLIDR_EL1, LOC, 24, 3) 1916 FIELD(CLIDR_EL1, LOUU, 27, 3) 1917 FIELD(CLIDR_EL1, ICB, 30, 3) 1918 1919 /* When FEAT_CCIDX is implemented */ 1920 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1921 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1922 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1923 1924 /* When FEAT_CCIDX is not implemented */ 1925 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1926 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1927 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1928 1929 FIELD(CTR_EL0, IMINLINE, 0, 4) 1930 FIELD(CTR_EL0, L1IP, 14, 2) 1931 FIELD(CTR_EL0, DMINLINE, 16, 4) 1932 FIELD(CTR_EL0, ERG, 20, 4) 1933 FIELD(CTR_EL0, CWG, 24, 4) 1934 FIELD(CTR_EL0, IDC, 28, 1) 1935 FIELD(CTR_EL0, DIC, 29, 1) 1936 FIELD(CTR_EL0, TMINLINE, 32, 6) 1937 1938 FIELD(MIDR_EL1, REVISION, 0, 4) 1939 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1940 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1941 FIELD(MIDR_EL1, VARIANT, 20, 4) 1942 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1943 1944 FIELD(ID_ISAR0, SWAP, 0, 4) 1945 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1946 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1947 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1948 FIELD(ID_ISAR0, COPROC, 16, 4) 1949 FIELD(ID_ISAR0, DEBUG, 20, 4) 1950 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1951 1952 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1953 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1954 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1955 FIELD(ID_ISAR1, EXTEND, 12, 4) 1956 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1957 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1958 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1959 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1960 1961 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1962 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1963 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1964 FIELD(ID_ISAR2, MULT, 12, 4) 1965 FIELD(ID_ISAR2, MULTS, 16, 4) 1966 FIELD(ID_ISAR2, MULTU, 20, 4) 1967 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1968 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1969 1970 FIELD(ID_ISAR3, SATURATE, 0, 4) 1971 FIELD(ID_ISAR3, SIMD, 4, 4) 1972 FIELD(ID_ISAR3, SVC, 8, 4) 1973 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1974 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1975 FIELD(ID_ISAR3, T32COPY, 20, 4) 1976 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1977 FIELD(ID_ISAR3, T32EE, 28, 4) 1978 1979 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1980 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1981 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1982 FIELD(ID_ISAR4, SMC, 12, 4) 1983 FIELD(ID_ISAR4, BARRIER, 16, 4) 1984 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1985 FIELD(ID_ISAR4, PSR_M, 24, 4) 1986 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1987 1988 FIELD(ID_ISAR5, SEVL, 0, 4) 1989 FIELD(ID_ISAR5, AES, 4, 4) 1990 FIELD(ID_ISAR5, SHA1, 8, 4) 1991 FIELD(ID_ISAR5, SHA2, 12, 4) 1992 FIELD(ID_ISAR5, CRC32, 16, 4) 1993 FIELD(ID_ISAR5, RDM, 24, 4) 1994 FIELD(ID_ISAR5, VCMA, 28, 4) 1995 1996 FIELD(ID_ISAR6, JSCVT, 0, 4) 1997 FIELD(ID_ISAR6, DP, 4, 4) 1998 FIELD(ID_ISAR6, FHM, 8, 4) 1999 FIELD(ID_ISAR6, SB, 12, 4) 2000 FIELD(ID_ISAR6, SPECRES, 16, 4) 2001 FIELD(ID_ISAR6, BF16, 20, 4) 2002 FIELD(ID_ISAR6, I8MM, 24, 4) 2003 2004 FIELD(ID_MMFR0, VMSA, 0, 4) 2005 FIELD(ID_MMFR0, PMSA, 4, 4) 2006 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2007 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2008 FIELD(ID_MMFR0, TCM, 16, 4) 2009 FIELD(ID_MMFR0, AUXREG, 20, 4) 2010 FIELD(ID_MMFR0, FCSE, 24, 4) 2011 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2012 2013 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2014 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2015 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2016 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2017 FIELD(ID_MMFR1, L1HVD, 16, 4) 2018 FIELD(ID_MMFR1, L1UNI, 20, 4) 2019 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2020 FIELD(ID_MMFR1, BPRED, 28, 4) 2021 2022 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2023 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2024 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2025 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2026 FIELD(ID_MMFR2, UNITLB, 16, 4) 2027 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2028 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2029 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2030 2031 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2032 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2033 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2034 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2035 FIELD(ID_MMFR3, PAN, 16, 4) 2036 FIELD(ID_MMFR3, COHWALK, 20, 4) 2037 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2038 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2039 2040 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2041 FIELD(ID_MMFR4, AC2, 4, 4) 2042 FIELD(ID_MMFR4, XNX, 8, 4) 2043 FIELD(ID_MMFR4, CNP, 12, 4) 2044 FIELD(ID_MMFR4, HPDS, 16, 4) 2045 FIELD(ID_MMFR4, LSM, 20, 4) 2046 FIELD(ID_MMFR4, CCIDX, 24, 4) 2047 FIELD(ID_MMFR4, EVT, 28, 4) 2048 2049 FIELD(ID_MMFR5, ETS, 0, 4) 2050 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2051 2052 FIELD(ID_PFR0, STATE0, 0, 4) 2053 FIELD(ID_PFR0, STATE1, 4, 4) 2054 FIELD(ID_PFR0, STATE2, 8, 4) 2055 FIELD(ID_PFR0, STATE3, 12, 4) 2056 FIELD(ID_PFR0, CSV2, 16, 4) 2057 FIELD(ID_PFR0, AMU, 20, 4) 2058 FIELD(ID_PFR0, DIT, 24, 4) 2059 FIELD(ID_PFR0, RAS, 28, 4) 2060 2061 FIELD(ID_PFR1, PROGMOD, 0, 4) 2062 FIELD(ID_PFR1, SECURITY, 4, 4) 2063 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2064 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2065 FIELD(ID_PFR1, GENTIMER, 16, 4) 2066 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2067 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2068 FIELD(ID_PFR1, GIC, 28, 4) 2069 2070 FIELD(ID_PFR2, CSV3, 0, 4) 2071 FIELD(ID_PFR2, SSBS, 4, 4) 2072 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2073 2074 FIELD(ID_AA64ISAR0, AES, 4, 4) 2075 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2076 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2077 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2078 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2079 FIELD(ID_AA64ISAR0, TME, 24, 4) 2080 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2081 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2082 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2083 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2084 FIELD(ID_AA64ISAR0, DP, 44, 4) 2085 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2086 FIELD(ID_AA64ISAR0, TS, 52, 4) 2087 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2088 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2089 2090 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2091 FIELD(ID_AA64ISAR1, APA, 4, 4) 2092 FIELD(ID_AA64ISAR1, API, 8, 4) 2093 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2094 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2095 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2096 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2097 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2098 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2099 FIELD(ID_AA64ISAR1, SB, 36, 4) 2100 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2101 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2102 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2103 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2104 FIELD(ID_AA64ISAR1, XS, 56, 4) 2105 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2106 2107 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2108 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2109 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2110 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2111 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2112 FIELD(ID_AA64ISAR2, BC, 20, 4) 2113 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2114 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2115 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2116 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2117 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2118 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2119 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2120 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2121 2122 FIELD(ID_AA64PFR0, EL0, 0, 4) 2123 FIELD(ID_AA64PFR0, EL1, 4, 4) 2124 FIELD(ID_AA64PFR0, EL2, 8, 4) 2125 FIELD(ID_AA64PFR0, EL3, 12, 4) 2126 FIELD(ID_AA64PFR0, FP, 16, 4) 2127 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2128 FIELD(ID_AA64PFR0, GIC, 24, 4) 2129 FIELD(ID_AA64PFR0, RAS, 28, 4) 2130 FIELD(ID_AA64PFR0, SVE, 32, 4) 2131 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2132 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2133 FIELD(ID_AA64PFR0, AMU, 44, 4) 2134 FIELD(ID_AA64PFR0, DIT, 48, 4) 2135 FIELD(ID_AA64PFR0, RME, 52, 4) 2136 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2137 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2138 2139 FIELD(ID_AA64PFR1, BT, 0, 4) 2140 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2141 FIELD(ID_AA64PFR1, MTE, 8, 4) 2142 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2143 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2144 FIELD(ID_AA64PFR1, SME, 24, 4) 2145 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2146 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2147 FIELD(ID_AA64PFR1, NMI, 36, 4) 2148 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2149 FIELD(ID_AA64PFR1, GCS, 44, 4) 2150 FIELD(ID_AA64PFR1, THE, 48, 4) 2151 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2152 FIELD(ID_AA64PFR1, DF2, 56, 4) 2153 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2154 2155 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2156 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2157 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2158 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2159 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2160 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2161 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2162 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2163 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2164 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2165 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2166 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2167 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2168 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2169 2170 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2171 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2172 FIELD(ID_AA64MMFR1, VH, 8, 4) 2173 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2174 FIELD(ID_AA64MMFR1, LO, 16, 4) 2175 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2176 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2177 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2178 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2179 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2180 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2181 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2182 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2183 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2184 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2185 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2186 2187 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2188 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2189 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2190 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2191 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2192 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2193 FIELD(ID_AA64MMFR2, NV, 24, 4) 2194 FIELD(ID_AA64MMFR2, ST, 28, 4) 2195 FIELD(ID_AA64MMFR2, AT, 32, 4) 2196 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2197 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2198 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2199 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2200 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2201 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2202 2203 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2204 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2205 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2206 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2207 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2208 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2209 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2210 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2211 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2212 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2213 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2214 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2215 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2216 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2217 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2218 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2219 2220 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2221 FIELD(ID_AA64ZFR0, AES, 4, 4) 2222 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2223 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2224 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2225 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2226 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2227 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2228 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2229 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2230 2231 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2232 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2233 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2234 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2235 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2236 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2237 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2238 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2239 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2240 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2241 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2242 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2243 2244 FIELD(ID_DFR0, COPDBG, 0, 4) 2245 FIELD(ID_DFR0, COPSDBG, 4, 4) 2246 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2247 FIELD(ID_DFR0, COPTRC, 12, 4) 2248 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2249 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2250 FIELD(ID_DFR0, PERFMON, 24, 4) 2251 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2252 2253 FIELD(ID_DFR1, MTPMU, 0, 4) 2254 FIELD(ID_DFR1, HPMN0, 4, 4) 2255 2256 FIELD(DBGDIDR, SE_IMP, 12, 1) 2257 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2258 FIELD(DBGDIDR, VERSION, 16, 4) 2259 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2260 FIELD(DBGDIDR, BRPS, 24, 4) 2261 FIELD(DBGDIDR, WRPS, 28, 4) 2262 2263 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2264 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2265 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2266 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2267 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2268 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2269 FIELD(DBGDEVID, AUXREGS, 24, 4) 2270 FIELD(DBGDEVID, CIDMASK, 28, 4) 2271 2272 FIELD(MVFR0, SIMDREG, 0, 4) 2273 FIELD(MVFR0, FPSP, 4, 4) 2274 FIELD(MVFR0, FPDP, 8, 4) 2275 FIELD(MVFR0, FPTRAP, 12, 4) 2276 FIELD(MVFR0, FPDIVIDE, 16, 4) 2277 FIELD(MVFR0, FPSQRT, 20, 4) 2278 FIELD(MVFR0, FPSHVEC, 24, 4) 2279 FIELD(MVFR0, FPROUND, 28, 4) 2280 2281 FIELD(MVFR1, FPFTZ, 0, 4) 2282 FIELD(MVFR1, FPDNAN, 4, 4) 2283 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2284 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2285 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2286 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2287 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2288 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2289 FIELD(MVFR1, FPHP, 24, 4) 2290 FIELD(MVFR1, SIMDFMAC, 28, 4) 2291 2292 FIELD(MVFR2, SIMDMISC, 0, 4) 2293 FIELD(MVFR2, FPMISC, 4, 4) 2294 2295 FIELD(GPCCR, PPS, 0, 3) 2296 FIELD(GPCCR, IRGN, 8, 2) 2297 FIELD(GPCCR, ORGN, 10, 2) 2298 FIELD(GPCCR, SH, 12, 2) 2299 FIELD(GPCCR, PGS, 14, 2) 2300 FIELD(GPCCR, GPC, 16, 1) 2301 FIELD(GPCCR, GPCP, 17, 1) 2302 FIELD(GPCCR, L0GPTSZ, 20, 4) 2303 2304 FIELD(MFAR, FPA, 12, 40) 2305 FIELD(MFAR, NSE, 62, 1) 2306 FIELD(MFAR, NS, 63, 1) 2307 2308 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2309 2310 /* If adding a feature bit which corresponds to a Linux ELF 2311 * HWCAP bit, remember to update the feature-bit-to-hwcap 2312 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2313 */ 2314 enum arm_features { 2315 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2316 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2317 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2318 ARM_FEATURE_V6, 2319 ARM_FEATURE_V6K, 2320 ARM_FEATURE_V7, 2321 ARM_FEATURE_THUMB2, 2322 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2323 ARM_FEATURE_NEON, 2324 ARM_FEATURE_M, /* Microcontroller profile. */ 2325 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2326 ARM_FEATURE_THUMB2EE, 2327 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2328 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2329 ARM_FEATURE_V4T, 2330 ARM_FEATURE_V5, 2331 ARM_FEATURE_STRONGARM, 2332 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2333 ARM_FEATURE_GENERIC_TIMER, 2334 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2335 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2336 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2337 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2338 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2339 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2340 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2341 ARM_FEATURE_V8, 2342 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2343 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2344 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2345 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2346 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2347 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2348 ARM_FEATURE_PMU, /* has PMU support */ 2349 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2350 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2351 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2352 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2353 }; 2354 2355 static inline int arm_feature(CPUARMState *env, int feature) 2356 { 2357 return (env->features & (1ULL << feature)) != 0; 2358 } 2359 2360 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2361 2362 /* 2363 * ARM v9 security states. 2364 * The ordering of the enumeration corresponds to the low 2 bits 2365 * of the GPI value, and (except for Root) the concat of NSE:NS. 2366 */ 2367 2368 typedef enum ARMSecuritySpace { 2369 ARMSS_Secure = 0, 2370 ARMSS_NonSecure = 1, 2371 ARMSS_Root = 2, 2372 ARMSS_Realm = 3, 2373 } ARMSecuritySpace; 2374 2375 /* Return true if @space is secure, in the pre-v9 sense. */ 2376 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2377 { 2378 return space == ARMSS_Secure || space == ARMSS_Root; 2379 } 2380 2381 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2382 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2383 { 2384 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2385 } 2386 2387 #if !defined(CONFIG_USER_ONLY) 2388 /** 2389 * arm_security_space_below_el3: 2390 * @env: cpu context 2391 * 2392 * Return the security space of exception levels below EL3, following 2393 * an exception return to those levels. Unlike arm_security_space, 2394 * this doesn't care about the current EL. 2395 */ 2396 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2397 2398 /** 2399 * arm_is_secure_below_el3: 2400 * @env: cpu context 2401 * 2402 * Return true if exception levels below EL3 are in secure state, 2403 * or would be following an exception return to those levels. 2404 */ 2405 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2406 { 2407 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2408 return ss == ARMSS_Secure; 2409 } 2410 2411 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2412 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2413 { 2414 assert(!arm_feature(env, ARM_FEATURE_M)); 2415 if (arm_feature(env, ARM_FEATURE_EL3)) { 2416 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2417 /* CPU currently in AArch64 state and EL3 */ 2418 return true; 2419 } else if (!is_a64(env) && 2420 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2421 /* CPU currently in AArch32 state and monitor mode */ 2422 return true; 2423 } 2424 } 2425 return false; 2426 } 2427 2428 /** 2429 * arm_security_space: 2430 * @env: cpu context 2431 * 2432 * Return the current security space of the cpu. 2433 */ 2434 ARMSecuritySpace arm_security_space(CPUARMState *env); 2435 2436 /** 2437 * arm_is_secure: 2438 * @env: cpu context 2439 * 2440 * Return true if the processor is in secure state. 2441 */ 2442 static inline bool arm_is_secure(CPUARMState *env) 2443 { 2444 return arm_space_is_secure(arm_security_space(env)); 2445 } 2446 2447 /* 2448 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2449 * This corresponds to the pseudocode EL2Enabled(). 2450 */ 2451 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2452 ARMSecuritySpace space) 2453 { 2454 assert(space != ARMSS_Root); 2455 return arm_feature(env, ARM_FEATURE_EL2) 2456 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2457 } 2458 2459 static inline bool arm_is_el2_enabled(CPUARMState *env) 2460 { 2461 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2462 } 2463 2464 #else 2465 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2466 { 2467 return ARMSS_NonSecure; 2468 } 2469 2470 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2471 { 2472 return false; 2473 } 2474 2475 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2476 { 2477 return ARMSS_NonSecure; 2478 } 2479 2480 static inline bool arm_is_secure(CPUARMState *env) 2481 { 2482 return false; 2483 } 2484 2485 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2486 ARMSecuritySpace space) 2487 { 2488 return false; 2489 } 2490 2491 static inline bool arm_is_el2_enabled(CPUARMState *env) 2492 { 2493 return false; 2494 } 2495 #endif 2496 2497 /** 2498 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2499 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2500 * "for all purposes other than a direct read or write access of HCR_EL2." 2501 * Not included here is HCR_RW. 2502 */ 2503 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2504 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2505 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2506 2507 /* Return true if the specified exception level is running in AArch64 state. */ 2508 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2509 { 2510 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2511 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2512 */ 2513 assert(el >= 1 && el <= 3); 2514 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2515 2516 /* The highest exception level is always at the maximum supported 2517 * register width, and then lower levels have a register width controlled 2518 * by bits in the SCR or HCR registers. 2519 */ 2520 if (el == 3) { 2521 return aa64; 2522 } 2523 2524 if (arm_feature(env, ARM_FEATURE_EL3) && 2525 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2526 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2527 } 2528 2529 if (el == 2) { 2530 return aa64; 2531 } 2532 2533 if (arm_is_el2_enabled(env)) { 2534 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2535 } 2536 2537 return aa64; 2538 } 2539 2540 /* Function for determining whether guest cp register reads and writes should 2541 * access the secure or non-secure bank of a cp register. When EL3 is 2542 * operating in AArch32 state, the NS-bit determines whether the secure 2543 * instance of a cp register should be used. When EL3 is AArch64 (or if 2544 * it doesn't exist at all) then there is no register banking, and all 2545 * accesses are to the non-secure version. 2546 */ 2547 static inline bool access_secure_reg(CPUARMState *env) 2548 { 2549 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2550 !arm_el_is_aa64(env, 3) && 2551 !(env->cp15.scr_el3 & SCR_NS)); 2552 2553 return ret; 2554 } 2555 2556 /* Macros for accessing a specified CP register bank */ 2557 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2558 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2559 2560 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2561 do { \ 2562 if (_secure) { \ 2563 (_env)->cp15._regname##_s = (_val); \ 2564 } else { \ 2565 (_env)->cp15._regname##_ns = (_val); \ 2566 } \ 2567 } while (0) 2568 2569 /* Macros for automatically accessing a specific CP register bank depending on 2570 * the current secure state of the system. These macros are not intended for 2571 * supporting instruction translation reads/writes as these are dependent 2572 * solely on the SCR.NS bit and not the mode. 2573 */ 2574 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2575 A32_BANKED_REG_GET((_env), _regname, \ 2576 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2577 2578 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2579 A32_BANKED_REG_SET((_env), _regname, \ 2580 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2581 (_val)) 2582 2583 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2584 uint32_t cur_el, bool secure); 2585 2586 /* Return the highest implemented Exception Level */ 2587 static inline int arm_highest_el(CPUARMState *env) 2588 { 2589 if (arm_feature(env, ARM_FEATURE_EL3)) { 2590 return 3; 2591 } 2592 if (arm_feature(env, ARM_FEATURE_EL2)) { 2593 return 2; 2594 } 2595 return 1; 2596 } 2597 2598 /* Return true if a v7M CPU is in Handler mode */ 2599 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2600 { 2601 return env->v7m.exception != 0; 2602 } 2603 2604 /* Return the current Exception Level (as per ARMv8; note that this differs 2605 * from the ARMv7 Privilege Level). 2606 */ 2607 static inline int arm_current_el(CPUARMState *env) 2608 { 2609 if (arm_feature(env, ARM_FEATURE_M)) { 2610 return arm_v7m_is_handler_mode(env) || 2611 !(env->v7m.control[env->v7m.secure] & 1); 2612 } 2613 2614 if (is_a64(env)) { 2615 return extract32(env->pstate, 2, 2); 2616 } 2617 2618 switch (env->uncached_cpsr & 0x1f) { 2619 case ARM_CPU_MODE_USR: 2620 return 0; 2621 case ARM_CPU_MODE_HYP: 2622 return 2; 2623 case ARM_CPU_MODE_MON: 2624 return 3; 2625 default: 2626 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2627 /* If EL3 is 32-bit then all secure privileged modes run in 2628 * EL3 2629 */ 2630 return 3; 2631 } 2632 2633 return 1; 2634 } 2635 } 2636 2637 /** 2638 * write_list_to_cpustate 2639 * @cpu: ARMCPU 2640 * 2641 * For each register listed in the ARMCPU cpreg_indexes list, write 2642 * its value from the cpreg_values list into the ARMCPUState structure. 2643 * This updates TCG's working data structures from KVM data or 2644 * from incoming migration state. 2645 * 2646 * Returns: true if all register values were updated correctly, 2647 * false if some register was unknown or could not be written. 2648 * Note that we do not stop early on failure -- we will attempt 2649 * writing all registers in the list. 2650 */ 2651 bool write_list_to_cpustate(ARMCPU *cpu); 2652 2653 /** 2654 * write_cpustate_to_list: 2655 * @cpu: ARMCPU 2656 * @kvm_sync: true if this is for syncing back to KVM 2657 * 2658 * For each register listed in the ARMCPU cpreg_indexes list, write 2659 * its value from the ARMCPUState structure into the cpreg_values list. 2660 * This is used to copy info from TCG's working data structures into 2661 * KVM or for outbound migration. 2662 * 2663 * @kvm_sync is true if we are doing this in order to sync the 2664 * register state back to KVM. In this case we will only update 2665 * values in the list if the previous list->cpustate sync actually 2666 * successfully wrote the CPU state. Otherwise we will keep the value 2667 * that is in the list. 2668 * 2669 * Returns: true if all register values were read correctly, 2670 * false if some register was unknown or could not be read. 2671 * Note that we do not stop early on failure -- we will attempt 2672 * reading all registers in the list. 2673 */ 2674 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2675 2676 #define ARM_CPUID_TI915T 0x54029152 2677 #define ARM_CPUID_TI925T 0x54029252 2678 2679 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2680 2681 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2682 2683 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2684 * 2685 * If EL3 is 64-bit: 2686 * + NonSecure EL1 & 0 stage 1 2687 * + NonSecure EL1 & 0 stage 2 2688 * + NonSecure EL2 2689 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2690 * + Secure EL1 & 0 2691 * + Secure EL3 2692 * If EL3 is 32-bit: 2693 * + NonSecure PL1 & 0 stage 1 2694 * + NonSecure PL1 & 0 stage 2 2695 * + NonSecure PL2 2696 * + Secure PL0 2697 * + Secure PL1 2698 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2699 * 2700 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2701 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2702 * because they may differ in access permissions even if the VA->PA map is 2703 * the same 2704 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2705 * translation, which means that we have one mmu_idx that deals with two 2706 * concatenated translation regimes [this sort of combined s1+2 TLB is 2707 * architecturally permitted] 2708 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2709 * handling via the TLB. The only way to do a stage 1 translation without 2710 * the immediate stage 2 translation is via the ATS or AT system insns, 2711 * which can be slow-pathed and always do a page table walk. 2712 * The only use of stage 2 translations is either as part of an s1+2 2713 * lookup or when loading the descriptors during a stage 1 page table walk, 2714 * and in both those cases we don't use the TLB. 2715 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2716 * translation regimes, because they map reasonably well to each other 2717 * and they can't both be active at the same time. 2718 * 5. we want to be able to use the TLB for accesses done as part of a 2719 * stage1 page table walk, rather than having to walk the stage2 page 2720 * table over and over. 2721 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2722 * Never (PAN) bit within PSTATE. 2723 * 7. we fold together the secure and non-secure regimes for A-profile, 2724 * because there are no banked system registers for aarch64, so the 2725 * process of switching between secure and non-secure is 2726 * already heavyweight. 2727 * 2728 * This gives us the following list of cases: 2729 * 2730 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2731 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2732 * EL1 EL1&0 stage 1+2 +PAN 2733 * EL0 EL2&0 2734 * EL2 EL2&0 2735 * EL2 EL2&0 +PAN 2736 * EL2 (aka NS PL2) 2737 * EL3 (aka S PL1) 2738 * Physical (NS & S) 2739 * Stage2 (NS & S) 2740 * 2741 * for a total of 12 different mmu_idx. 2742 * 2743 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2744 * as A profile. They only need to distinguish EL0 and EL1 (and 2745 * EL2 if we ever model a Cortex-R52). 2746 * 2747 * M profile CPUs are rather different as they do not have a true MMU. 2748 * They have the following different MMU indexes: 2749 * User 2750 * Privileged 2751 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2752 * Privileged, execution priority negative (ditto) 2753 * If the CPU supports the v8M Security Extension then there are also: 2754 * Secure User 2755 * Secure Privileged 2756 * Secure User, execution priority negative 2757 * Secure Privileged, execution priority negative 2758 * 2759 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2760 * are not quite the same -- different CPU types (most notably M profile 2761 * vs A/R profile) would like to use MMU indexes with different semantics, 2762 * but since we don't ever need to use all of those in a single CPU we 2763 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2764 * modes + total number of M profile MMU modes". The lower bits of 2765 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2766 * the same for any particular CPU. 2767 * Variables of type ARMMUIdx are always full values, and the core 2768 * index values are in variables of type 'int'. 2769 * 2770 * Our enumeration includes at the end some entries which are not "true" 2771 * mmu_idx values in that they don't have corresponding TLBs and are only 2772 * valid for doing slow path page table walks. 2773 * 2774 * The constant names here are patterned after the general style of the names 2775 * of the AT/ATS operations. 2776 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2777 * For M profile we arrange them to have a bit for priv, a bit for negpri 2778 * and a bit for secure. 2779 */ 2780 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2781 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2782 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2783 2784 /* Meanings of the bits for M profile mmu idx values */ 2785 #define ARM_MMU_IDX_M_PRIV 0x1 2786 #define ARM_MMU_IDX_M_NEGPRI 0x2 2787 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2788 2789 #define ARM_MMU_IDX_TYPE_MASK \ 2790 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2791 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2792 2793 typedef enum ARMMMUIdx { 2794 /* 2795 * A-profile. 2796 */ 2797 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2798 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2799 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2800 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2801 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2802 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2803 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2804 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2805 2806 /* 2807 * Used for second stage of an S12 page table walk, or for descriptor 2808 * loads during first stage of an S1 page table walk. Note that both 2809 * are in use simultaneously for SecureEL2: the security state for 2810 * the S2 ptw is selected by the NS bit from the S1 ptw. 2811 */ 2812 ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A, 2813 ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, 2814 2815 /* TLBs with 1-1 mapping to the physical address spaces. */ 2816 ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, 2817 ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, 2818 ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, 2819 ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, 2820 2821 /* 2822 * These are not allocated TLBs and are used only for AT system 2823 * instructions or for the first stage of an S12 page table walk. 2824 */ 2825 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2826 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2827 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2828 2829 /* 2830 * M-profile. 2831 */ 2832 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2833 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2834 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2835 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2836 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2837 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2838 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2839 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2840 } ARMMMUIdx; 2841 2842 /* 2843 * Bit macros for the core-mmu-index values for each index, 2844 * for use when calling tlb_flush_by_mmuidx() and friends. 2845 */ 2846 #define TO_CORE_BIT(NAME) \ 2847 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2848 2849 typedef enum ARMMMUIdxBit { 2850 TO_CORE_BIT(E10_0), 2851 TO_CORE_BIT(E20_0), 2852 TO_CORE_BIT(E10_1), 2853 TO_CORE_BIT(E10_1_PAN), 2854 TO_CORE_BIT(E2), 2855 TO_CORE_BIT(E20_2), 2856 TO_CORE_BIT(E20_2_PAN), 2857 TO_CORE_BIT(E3), 2858 TO_CORE_BIT(Stage2), 2859 TO_CORE_BIT(Stage2_S), 2860 2861 TO_CORE_BIT(MUser), 2862 TO_CORE_BIT(MPriv), 2863 TO_CORE_BIT(MUserNegPri), 2864 TO_CORE_BIT(MPrivNegPri), 2865 TO_CORE_BIT(MSUser), 2866 TO_CORE_BIT(MSPriv), 2867 TO_CORE_BIT(MSUserNegPri), 2868 TO_CORE_BIT(MSPrivNegPri), 2869 } ARMMMUIdxBit; 2870 2871 #undef TO_CORE_BIT 2872 2873 #define MMU_USER_IDX 0 2874 2875 /* Indexes used when registering address spaces with cpu_address_space_init */ 2876 typedef enum ARMASIdx { 2877 ARMASIdx_NS = 0, 2878 ARMASIdx_S = 1, 2879 ARMASIdx_TagNS = 2, 2880 ARMASIdx_TagS = 3, 2881 } ARMASIdx; 2882 2883 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 2884 { 2885 /* Assert the relative order of the physical mmu indexes. */ 2886 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 2887 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 2888 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 2889 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 2890 2891 return ARMMMUIdx_Phys_S + space; 2892 } 2893 2894 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 2895 { 2896 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 2897 return idx - ARMMMUIdx_Phys_S; 2898 } 2899 2900 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2901 { 2902 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2903 * CSSELR is RAZ/WI. 2904 */ 2905 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2906 } 2907 2908 static inline bool arm_sctlr_b(CPUARMState *env) 2909 { 2910 return 2911 /* We need not implement SCTLR.ITD in user-mode emulation, so 2912 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2913 * This lets people run BE32 binaries with "-cpu any". 2914 */ 2915 #ifndef CONFIG_USER_ONLY 2916 !arm_feature(env, ARM_FEATURE_V7) && 2917 #endif 2918 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2919 } 2920 2921 uint64_t arm_sctlr(CPUARMState *env, int el); 2922 2923 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 2924 bool sctlr_b) 2925 { 2926 #ifdef CONFIG_USER_ONLY 2927 /* 2928 * In system mode, BE32 is modelled in line with the 2929 * architecture (as word-invariant big-endianness), where loads 2930 * and stores are done little endian but from addresses which 2931 * are adjusted by XORing with the appropriate constant. So the 2932 * endianness to use for the raw data access is not affected by 2933 * SCTLR.B. 2934 * In user mode, however, we model BE32 as byte-invariant 2935 * big-endianness (because user-only code cannot tell the 2936 * difference), and so we need to use a data access endianness 2937 * that depends on SCTLR.B. 2938 */ 2939 if (sctlr_b) { 2940 return true; 2941 } 2942 #endif 2943 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2944 return env->uncached_cpsr & CPSR_E; 2945 } 2946 2947 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 2948 { 2949 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 2950 } 2951 2952 /* Return true if the processor is in big-endian mode. */ 2953 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2954 { 2955 if (!is_a64(env)) { 2956 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 2957 } else { 2958 int cur_el = arm_current_el(env); 2959 uint64_t sctlr = arm_sctlr(env, cur_el); 2960 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 2961 } 2962 } 2963 2964 #include "exec/cpu-all.h" 2965 2966 /* 2967 * We have more than 32-bits worth of state per TB, so we split the data 2968 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 2969 * We collect these two parts in CPUARMTBFlags where they are named 2970 * flags and flags2 respectively. 2971 * 2972 * The flags that are shared between all execution modes, TBFLAG_ANY, 2973 * are stored in flags. The flags that are specific to a given mode 2974 * are stores in flags2. Since cs_base is sized on the configured 2975 * address size, flags2 always has 64-bits for A64, and a minimum of 2976 * 32-bits for A32 and M32. 2977 * 2978 * The bits for 32-bit A-profile and M-profile partially overlap: 2979 * 2980 * 31 23 11 10 0 2981 * +-------------+----------+----------------+ 2982 * | | | TBFLAG_A32 | 2983 * | TBFLAG_AM32 | +-----+----------+ 2984 * | | |TBFLAG_M32| 2985 * +-------------+----------------+----------+ 2986 * 31 23 6 5 0 2987 * 2988 * Unless otherwise noted, these bits are cached in env->hflags. 2989 */ 2990 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 2991 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 2992 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 2993 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 2994 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 2995 /* Target EL if we take a floating-point-disabled exception */ 2996 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 2997 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 2998 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 2999 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3000 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3001 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3002 3003 /* 3004 * Bit usage when in AArch32 state, both A- and M-profile. 3005 */ 3006 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3007 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3008 3009 /* 3010 * Bit usage when in AArch32 state, for A-profile only. 3011 */ 3012 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3013 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3014 /* 3015 * We store the bottom two bits of the CPAR as TB flags and handle 3016 * checks on the other bits at runtime. This shares the same bits as 3017 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3018 * Not cached, because VECLEN+VECSTRIDE are not cached. 3019 */ 3020 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3021 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3022 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3023 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3024 /* 3025 * Indicates whether cp register reads and writes by guest code should access 3026 * the secure or nonsecure bank of banked registers; note that this is not 3027 * the same thing as the current security state of the processor! 3028 */ 3029 FIELD(TBFLAG_A32, NS, 10, 1) 3030 /* 3031 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3032 * This requires an SME trap from AArch32 mode when using NEON. 3033 */ 3034 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3035 3036 /* 3037 * Bit usage when in AArch32 state, for M-profile only. 3038 */ 3039 /* Handler (ie not Thread) mode */ 3040 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3041 /* Whether we should generate stack-limit checks */ 3042 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3043 /* Set if FPCCR.LSPACT is set */ 3044 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3045 /* Set if we must create a new FP context */ 3046 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3047 /* Set if FPCCR.S does not match current security state */ 3048 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3049 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3050 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3051 /* Set if in secure mode */ 3052 FIELD(TBFLAG_M32, SECURE, 6, 1) 3053 3054 /* 3055 * Bit usage when in AArch64 state 3056 */ 3057 FIELD(TBFLAG_A64, TBII, 0, 2) 3058 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3059 /* The current vector length, either NVL or SVL. */ 3060 FIELD(TBFLAG_A64, VL, 4, 4) 3061 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3062 FIELD(TBFLAG_A64, BT, 9, 1) 3063 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3064 FIELD(TBFLAG_A64, TBID, 12, 2) 3065 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3066 FIELD(TBFLAG_A64, ATA, 15, 1) 3067 FIELD(TBFLAG_A64, TCMA, 16, 2) 3068 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3069 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3070 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3071 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3072 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3073 FIELD(TBFLAG_A64, SVL, 24, 4) 3074 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3075 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3076 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 3077 FIELD(TBFLAG_A64, NAA, 30, 1) 3078 FIELD(TBFLAG_A64, ATA0, 31, 1) 3079 FIELD(TBFLAG_A64, NV, 32, 1) 3080 FIELD(TBFLAG_A64, NV1, 33, 1) 3081 FIELD(TBFLAG_A64, NV2, 34, 1) 3082 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ 3083 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) 3084 /* Set if FEAT_NV2 RAM accesses are big-endian */ 3085 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 3086 3087 /* 3088 * Helpers for using the above. Note that only the A64 accessors use 3089 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 3090 * word either is or might be 32 bits only. 3091 */ 3092 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3093 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3094 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3095 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3096 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3097 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3098 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3099 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3100 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3101 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3102 3103 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3104 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 3105 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3106 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3107 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3108 3109 /** 3110 * sve_vq 3111 * @env: the cpu context 3112 * 3113 * Return the VL cached within env->hflags, in units of quadwords. 3114 */ 3115 static inline int sve_vq(CPUARMState *env) 3116 { 3117 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3118 } 3119 3120 /** 3121 * sme_vq 3122 * @env: the cpu context 3123 * 3124 * Return the SVL cached within env->hflags, in units of quadwords. 3125 */ 3126 static inline int sme_vq(CPUARMState *env) 3127 { 3128 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3129 } 3130 3131 static inline bool bswap_code(bool sctlr_b) 3132 { 3133 #ifdef CONFIG_USER_ONLY 3134 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3135 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3136 * would also end up as a mixed-endian mode with BE code, LE data. 3137 */ 3138 return TARGET_BIG_ENDIAN ^ sctlr_b; 3139 #else 3140 /* All code access in ARM is little endian, and there are no loaders 3141 * doing swaps that need to be reversed 3142 */ 3143 return 0; 3144 #endif 3145 } 3146 3147 #ifdef CONFIG_USER_ONLY 3148 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3149 { 3150 return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); 3151 } 3152 #endif 3153 3154 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, 3155 uint64_t *cs_base, uint32_t *flags); 3156 3157 enum { 3158 QEMU_PSCI_CONDUIT_DISABLED = 0, 3159 QEMU_PSCI_CONDUIT_SMC = 1, 3160 QEMU_PSCI_CONDUIT_HVC = 2, 3161 }; 3162 3163 #ifndef CONFIG_USER_ONLY 3164 /* Return the address space index to use for a memory access */ 3165 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3166 { 3167 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3168 } 3169 3170 /* Return the AddressSpace to use for a memory access 3171 * (which depends on whether the access is S or NS, and whether 3172 * the board gave us a separate AddressSpace for S accesses). 3173 */ 3174 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3175 { 3176 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3177 } 3178 #endif 3179 3180 /** 3181 * arm_register_pre_el_change_hook: 3182 * Register a hook function which will be called immediately before this 3183 * CPU changes exception level or mode. The hook function will be 3184 * passed a pointer to the ARMCPU and the opaque data pointer passed 3185 * to this function when the hook was registered. 3186 * 3187 * Note that if a pre-change hook is called, any registered post-change hooks 3188 * are guaranteed to subsequently be called. 3189 */ 3190 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3191 void *opaque); 3192 /** 3193 * arm_register_el_change_hook: 3194 * Register a hook function which will be called immediately after this 3195 * CPU changes exception level or mode. The hook function will be 3196 * passed a pointer to the ARMCPU and the opaque data pointer passed 3197 * to this function when the hook was registered. 3198 * 3199 * Note that any registered hooks registered here are guaranteed to be called 3200 * if pre-change hooks have been. 3201 */ 3202 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3203 *opaque); 3204 3205 /** 3206 * arm_rebuild_hflags: 3207 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3208 */ 3209 void arm_rebuild_hflags(CPUARMState *env); 3210 3211 /** 3212 * aa32_vfp_dreg: 3213 * Return a pointer to the Dn register within env in 32-bit mode. 3214 */ 3215 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3216 { 3217 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3218 } 3219 3220 /** 3221 * aa32_vfp_qreg: 3222 * Return a pointer to the Qn register within env in 32-bit mode. 3223 */ 3224 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3225 { 3226 return &env->vfp.zregs[regno].d[0]; 3227 } 3228 3229 /** 3230 * aa64_vfp_qreg: 3231 * Return a pointer to the Qn register within env in 64-bit mode. 3232 */ 3233 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3234 { 3235 return &env->vfp.zregs[regno].d[0]; 3236 } 3237 3238 /* Shared between translate-sve.c and sve_helper.c. */ 3239 extern const uint64_t pred_esz_masks[5]; 3240 3241 /* 3242 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3243 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3244 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3245 */ 3246 #define PAGE_BTI PAGE_TARGET_1 3247 #define PAGE_MTE PAGE_TARGET_2 3248 #define PAGE_TARGET_STICKY PAGE_MTE 3249 3250 /* We associate one allocation tag per 16 bytes, the minimum. */ 3251 #define LOG2_TAG_GRANULE 4 3252 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3253 3254 #ifdef CONFIG_USER_ONLY 3255 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3256 #endif 3257 3258 #ifdef TARGET_TAGGED_ADDRESSES 3259 /** 3260 * cpu_untagged_addr: 3261 * @cs: CPU context 3262 * @x: tagged address 3263 * 3264 * Remove any address tag from @x. This is explicitly related to the 3265 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3266 * 3267 * There should be a better place to put this, but we need this in 3268 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3269 */ 3270 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3271 { 3272 ARMCPU *cpu = ARM_CPU(cs); 3273 if (cpu->env.tagged_addr_enable) { 3274 /* 3275 * TBI is enabled for userspace but not kernelspace addresses. 3276 * Only clear the tag if bit 55 is clear. 3277 */ 3278 x &= sextract64(x, 0, 56); 3279 } 3280 return x; 3281 } 3282 #endif 3283 3284 #endif 3285