1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 #define VTCR_NSW (1u << 29) 170 #define VTCR_NSA (1u << 30) 171 #define VSTCR_SW VTCR_NSW 172 #define VSTCR_SA VTCR_NSA 173 174 /* Define a maximum sized vector register. 175 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 176 * For 64-bit, this is a 2048-bit SVE register. 177 * 178 * Note that the mapping between S, D, and Q views of the register bank 179 * differs between AArch64 and AArch32. 180 * In AArch32: 181 * Qn = regs[n].d[1]:regs[n].d[0] 182 * Dn = regs[n / 2].d[n & 1] 183 * Sn = regs[n / 4].d[n % 4 / 2], 184 * bits 31..0 for even n, and bits 63..32 for odd n 185 * (and regs[16] to regs[31] are inaccessible) 186 * In AArch64: 187 * Zn = regs[n].d[*] 188 * Qn = regs[n].d[1]:regs[n].d[0] 189 * Dn = regs[n].d[0] 190 * Sn = regs[n].d[0] bits 31..0 191 * Hn = regs[n].d[0] bits 15..0 192 * 193 * This corresponds to the architecturally defined mapping between 194 * the two execution states, and means we do not need to explicitly 195 * map these registers when changing states. 196 * 197 * Align the data for use with TCG host vector operations. 198 */ 199 200 #ifdef TARGET_AARCH64 201 # define ARM_MAX_VQ 16 202 #else 203 # define ARM_MAX_VQ 1 204 #endif 205 206 typedef struct ARMVectorReg { 207 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 208 } ARMVectorReg; 209 210 #ifdef TARGET_AARCH64 211 /* In AArch32 mode, predicate registers do not exist at all. */ 212 typedef struct ARMPredicateReg { 213 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 214 } ARMPredicateReg; 215 216 /* In AArch32 mode, PAC keys do not exist at all. */ 217 typedef struct ARMPACKey { 218 uint64_t lo, hi; 219 } ARMPACKey; 220 #endif 221 222 /* See the commentary above the TBFLAG field definitions. */ 223 typedef struct CPUARMTBFlags { 224 uint32_t flags; 225 target_ulong flags2; 226 } CPUARMTBFlags; 227 228 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 229 230 typedef struct CPUArchState { 231 /* Regs for current mode. */ 232 uint32_t regs[16]; 233 234 /* 32/64 switch only happens when taking and returning from 235 * exceptions so the overlap semantics are taken care of then 236 * instead of having a complicated union. 237 */ 238 /* Regs for A64 mode. */ 239 uint64_t xregs[32]; 240 uint64_t pc; 241 /* PSTATE isn't an architectural register for ARMv8. However, it is 242 * convenient for us to assemble the underlying state into a 32 bit format 243 * identical to the architectural format used for the SPSR. (This is also 244 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 245 * 'pstate' register are.) Of the PSTATE bits: 246 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 247 * semantics as for AArch32, as described in the comments on each field) 248 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 249 * DAIF (exception masks) are kept in env->daif 250 * BTYPE is kept in env->btype 251 * SM and ZA are kept in env->svcr 252 * all other bits are stored in their correct places in env->pstate 253 */ 254 uint32_t pstate; 255 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 256 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 257 258 /* Cached TBFLAGS state. See below for which bits are included. */ 259 CPUARMTBFlags hflags; 260 261 /* Frequently accessed CPSR bits are stored separately for efficiency. 262 This contains all the other bits. Use cpsr_{read,write} to access 263 the whole CPSR. */ 264 uint32_t uncached_cpsr; 265 uint32_t spsr; 266 267 /* Banked registers. */ 268 uint64_t banked_spsr[8]; 269 uint32_t banked_r13[8]; 270 uint32_t banked_r14[8]; 271 272 /* These hold r8-r12. */ 273 uint32_t usr_regs[5]; 274 uint32_t fiq_regs[5]; 275 276 /* cpsr flag cache for faster execution */ 277 uint32_t CF; /* 0 or 1 */ 278 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 279 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 280 uint32_t ZF; /* Z set if zero. */ 281 uint32_t QF; /* 0 or 1 */ 282 uint32_t GE; /* cpsr[19:16] */ 283 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 284 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 285 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 286 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 287 288 uint64_t elr_el[4]; /* AArch64 exception link regs */ 289 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 290 291 /* System control coprocessor (cp15) */ 292 struct { 293 uint32_t c0_cpuid; 294 union { /* Cache size selection */ 295 struct { 296 uint64_t _unused_csselr0; 297 uint64_t csselr_ns; 298 uint64_t _unused_csselr1; 299 uint64_t csselr_s; 300 }; 301 uint64_t csselr_el[4]; 302 }; 303 union { /* System control register. */ 304 struct { 305 uint64_t _unused_sctlr; 306 uint64_t sctlr_ns; 307 uint64_t hsctlr; 308 uint64_t sctlr_s; 309 }; 310 uint64_t sctlr_el[4]; 311 }; 312 uint64_t vsctlr; /* Virtualization System control register. */ 313 uint64_t cpacr_el1; /* Architectural feature access control register */ 314 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 315 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 316 uint64_t sder; /* Secure debug enable register. */ 317 uint32_t nsacr; /* Non-secure access control register. */ 318 union { /* MMU translation table base 0. */ 319 struct { 320 uint64_t _unused_ttbr0_0; 321 uint64_t ttbr0_ns; 322 uint64_t _unused_ttbr0_1; 323 uint64_t ttbr0_s; 324 }; 325 uint64_t ttbr0_el[4]; 326 }; 327 union { /* MMU translation table base 1. */ 328 struct { 329 uint64_t _unused_ttbr1_0; 330 uint64_t ttbr1_ns; 331 uint64_t _unused_ttbr1_1; 332 uint64_t ttbr1_s; 333 }; 334 uint64_t ttbr1_el[4]; 335 }; 336 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 337 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 338 /* MMU translation table base control. */ 339 uint64_t tcr_el[4]; 340 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 341 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 342 uint32_t c2_data; /* MPU data cacheable bits. */ 343 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 344 union { /* MMU domain access control register 345 * MPU write buffer control. 346 */ 347 struct { 348 uint64_t dacr_ns; 349 uint64_t dacr_s; 350 }; 351 struct { 352 uint64_t dacr32_el2; 353 }; 354 }; 355 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 356 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 357 uint64_t hcr_el2; /* Hypervisor configuration register */ 358 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 359 uint64_t scr_el3; /* Secure configuration register. */ 360 union { /* Fault status registers. */ 361 struct { 362 uint64_t ifsr_ns; 363 uint64_t ifsr_s; 364 }; 365 struct { 366 uint64_t ifsr32_el2; 367 }; 368 }; 369 union { 370 struct { 371 uint64_t _unused_dfsr; 372 uint64_t dfsr_ns; 373 uint64_t hsr; 374 uint64_t dfsr_s; 375 }; 376 uint64_t esr_el[4]; 377 }; 378 uint32_t c6_region[8]; /* MPU base/size registers. */ 379 union { /* Fault address registers. */ 380 struct { 381 uint64_t _unused_far0; 382 #if HOST_BIG_ENDIAN 383 uint32_t ifar_ns; 384 uint32_t dfar_ns; 385 uint32_t ifar_s; 386 uint32_t dfar_s; 387 #else 388 uint32_t dfar_ns; 389 uint32_t ifar_ns; 390 uint32_t dfar_s; 391 uint32_t ifar_s; 392 #endif 393 uint64_t _unused_far3; 394 }; 395 uint64_t far_el[4]; 396 }; 397 uint64_t hpfar_el2; 398 uint64_t hstr_el2; 399 union { /* Translation result. */ 400 struct { 401 uint64_t _unused_par_0; 402 uint64_t par_ns; 403 uint64_t _unused_par_1; 404 uint64_t par_s; 405 }; 406 uint64_t par_el[4]; 407 }; 408 409 uint32_t c9_insn; /* Cache lockdown registers. */ 410 uint32_t c9_data; 411 uint64_t c9_pmcr; /* performance monitor control register */ 412 uint64_t c9_pmcnten; /* perf monitor counter enables */ 413 uint64_t c9_pmovsr; /* perf monitor overflow status */ 414 uint64_t c9_pmuserenr; /* perf monitor user enable */ 415 uint64_t c9_pmselr; /* perf monitor counter selection register */ 416 uint64_t c9_pminten; /* perf monitor interrupt enables */ 417 union { /* Memory attribute redirection */ 418 struct { 419 #if HOST_BIG_ENDIAN 420 uint64_t _unused_mair_0; 421 uint32_t mair1_ns; 422 uint32_t mair0_ns; 423 uint64_t _unused_mair_1; 424 uint32_t mair1_s; 425 uint32_t mair0_s; 426 #else 427 uint64_t _unused_mair_0; 428 uint32_t mair0_ns; 429 uint32_t mair1_ns; 430 uint64_t _unused_mair_1; 431 uint32_t mair0_s; 432 uint32_t mair1_s; 433 #endif 434 }; 435 uint64_t mair_el[4]; 436 }; 437 union { /* vector base address register */ 438 struct { 439 uint64_t _unused_vbar; 440 uint64_t vbar_ns; 441 uint64_t hvbar; 442 uint64_t vbar_s; 443 }; 444 uint64_t vbar_el[4]; 445 }; 446 uint32_t mvbar; /* (monitor) vector base address register */ 447 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 448 struct { /* FCSE PID. */ 449 uint32_t fcseidr_ns; 450 uint32_t fcseidr_s; 451 }; 452 union { /* Context ID. */ 453 struct { 454 uint64_t _unused_contextidr_0; 455 uint64_t contextidr_ns; 456 uint64_t _unused_contextidr_1; 457 uint64_t contextidr_s; 458 }; 459 uint64_t contextidr_el[4]; 460 }; 461 union { /* User RW Thread register. */ 462 struct { 463 uint64_t tpidrurw_ns; 464 uint64_t tpidrprw_ns; 465 uint64_t htpidr; 466 uint64_t _tpidr_el3; 467 }; 468 uint64_t tpidr_el[4]; 469 }; 470 uint64_t tpidr2_el0; 471 /* The secure banks of these registers don't map anywhere */ 472 uint64_t tpidrurw_s; 473 uint64_t tpidrprw_s; 474 uint64_t tpidruro_s; 475 476 union { /* User RO Thread register. */ 477 uint64_t tpidruro_ns; 478 uint64_t tpidrro_el[1]; 479 }; 480 uint64_t c14_cntfrq; /* Counter Frequency register */ 481 uint64_t c14_cntkctl; /* Timer Control register */ 482 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 483 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 484 ARMGenericTimer c14_timer[NUM_GTIMERS]; 485 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 486 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 487 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 488 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 489 uint32_t c15_threadid; /* TI debugger thread-ID. */ 490 uint32_t c15_config_base_address; /* SCU base address. */ 491 uint32_t c15_diagnostic; /* diagnostic register */ 492 uint32_t c15_power_diagnostic; 493 uint32_t c15_power_control; /* power control */ 494 uint64_t dbgbvr[16]; /* breakpoint value registers */ 495 uint64_t dbgbcr[16]; /* breakpoint control registers */ 496 uint64_t dbgwvr[16]; /* watchpoint value registers */ 497 uint64_t dbgwcr[16]; /* watchpoint control registers */ 498 uint64_t dbgclaim; /* DBGCLAIM bits */ 499 uint64_t mdscr_el1; 500 uint64_t oslsr_el1; /* OS Lock Status */ 501 uint64_t osdlr_el1; /* OS DoubleLock status */ 502 uint64_t mdcr_el2; 503 uint64_t mdcr_el3; 504 /* Stores the architectural value of the counter *the last time it was 505 * updated* by pmccntr_op_start. Accesses should always be surrounded 506 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 507 * architecturally-correct value is being read/set. 508 */ 509 uint64_t c15_ccnt; 510 /* Stores the delta between the architectural value and the underlying 511 * cycle count during normal operation. It is used to update c15_ccnt 512 * to be the correct architectural value before accesses. During 513 * accesses, c15_ccnt_delta contains the underlying count being used 514 * for the access, after which it reverts to the delta value in 515 * pmccntr_op_finish. 516 */ 517 uint64_t c15_ccnt_delta; 518 uint64_t c14_pmevcntr[31]; 519 uint64_t c14_pmevcntr_delta[31]; 520 uint64_t c14_pmevtyper[31]; 521 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 522 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 523 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 524 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 525 uint64_t gcr_el1; 526 uint64_t rgsr_el1; 527 528 /* Minimal RAS registers */ 529 uint64_t disr_el1; 530 uint64_t vdisr_el2; 531 uint64_t vsesr_el2; 532 533 /* 534 * Fine-Grained Trap registers. We store these as arrays so the 535 * access checking code doesn't have to manually select 536 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 537 * FEAT_FGT2 will add more elements to these arrays. 538 */ 539 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 540 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 541 uint64_t fgt_exec[1]; /* HFGITR */ 542 } cp15; 543 544 struct { 545 /* M profile has up to 4 stack pointers: 546 * a Main Stack Pointer and a Process Stack Pointer for each 547 * of the Secure and Non-Secure states. (If the CPU doesn't support 548 * the security extension then it has only two SPs.) 549 * In QEMU we always store the currently active SP in regs[13], 550 * and the non-active SP for the current security state in 551 * v7m.other_sp. The stack pointers for the inactive security state 552 * are stored in other_ss_msp and other_ss_psp. 553 * switch_v7m_security_state() is responsible for rearranging them 554 * when we change security state. 555 */ 556 uint32_t other_sp; 557 uint32_t other_ss_msp; 558 uint32_t other_ss_psp; 559 uint32_t vecbase[M_REG_NUM_BANKS]; 560 uint32_t basepri[M_REG_NUM_BANKS]; 561 uint32_t control[M_REG_NUM_BANKS]; 562 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 563 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 564 uint32_t hfsr; /* HardFault Status */ 565 uint32_t dfsr; /* Debug Fault Status Register */ 566 uint32_t sfsr; /* Secure Fault Status Register */ 567 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 568 uint32_t bfar; /* BusFault Address */ 569 uint32_t sfar; /* Secure Fault Address Register */ 570 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 571 int exception; 572 uint32_t primask[M_REG_NUM_BANKS]; 573 uint32_t faultmask[M_REG_NUM_BANKS]; 574 uint32_t aircr; /* only holds r/w state if security extn implemented */ 575 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 576 uint32_t csselr[M_REG_NUM_BANKS]; 577 uint32_t scr[M_REG_NUM_BANKS]; 578 uint32_t msplim[M_REG_NUM_BANKS]; 579 uint32_t psplim[M_REG_NUM_BANKS]; 580 uint32_t fpcar[M_REG_NUM_BANKS]; 581 uint32_t fpccr[M_REG_NUM_BANKS]; 582 uint32_t fpdscr[M_REG_NUM_BANKS]; 583 uint32_t cpacr[M_REG_NUM_BANKS]; 584 uint32_t nsacr; 585 uint32_t ltpsize; 586 uint32_t vpr; 587 } v7m; 588 589 /* Information associated with an exception about to be taken: 590 * code which raises an exception must set cs->exception_index and 591 * the relevant parts of this structure; the cpu_do_interrupt function 592 * will then set the guest-visible registers as part of the exception 593 * entry process. 594 */ 595 struct { 596 uint32_t syndrome; /* AArch64 format syndrome register */ 597 uint32_t fsr; /* AArch32 format fault status register info */ 598 uint64_t vaddress; /* virtual addr associated with exception, if any */ 599 uint32_t target_el; /* EL the exception should be targeted for */ 600 /* If we implement EL2 we will also need to store information 601 * about the intermediate physical address for stage 2 faults. 602 */ 603 } exception; 604 605 /* Information associated with an SError */ 606 struct { 607 uint8_t pending; 608 uint8_t has_esr; 609 uint64_t esr; 610 } serror; 611 612 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 613 614 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 615 uint32_t irq_line_state; 616 617 /* Thumb-2 EE state. */ 618 uint32_t teecr; 619 uint32_t teehbr; 620 621 /* VFP coprocessor state. */ 622 struct { 623 ARMVectorReg zregs[32]; 624 625 #ifdef TARGET_AARCH64 626 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 627 #define FFR_PRED_NUM 16 628 ARMPredicateReg pregs[17]; 629 /* Scratch space for aa64 sve predicate temporary. */ 630 ARMPredicateReg preg_tmp; 631 #endif 632 633 /* We store these fpcsr fields separately for convenience. */ 634 uint32_t qc[4] QEMU_ALIGNED(16); 635 int vec_len; 636 int vec_stride; 637 638 uint32_t xregs[16]; 639 640 /* Scratch space for aa32 neon expansion. */ 641 uint32_t scratch[8]; 642 643 /* There are a number of distinct float control structures: 644 * 645 * fp_status: is the "normal" fp status. 646 * fp_status_fp16: used for half-precision calculations 647 * standard_fp_status : the ARM "Standard FPSCR Value" 648 * standard_fp_status_fp16 : used for half-precision 649 * calculations with the ARM "Standard FPSCR Value" 650 * 651 * Half-precision operations are governed by a separate 652 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 653 * status structure to control this. 654 * 655 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 656 * round-to-nearest and is used by any operations (generally 657 * Neon) which the architecture defines as controlled by the 658 * standard FPSCR value rather than the FPSCR. 659 * 660 * The "standard FPSCR but for fp16 ops" is needed because 661 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 662 * using a fixed value for it. 663 * 664 * To avoid having to transfer exception bits around, we simply 665 * say that the FPSCR cumulative exception flags are the logical 666 * OR of the flags in the four fp statuses. This relies on the 667 * only thing which needs to read the exception flags being 668 * an explicit FPSCR read. 669 */ 670 float_status fp_status; 671 float_status fp_status_f16; 672 float_status standard_fp_status; 673 float_status standard_fp_status_f16; 674 675 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 676 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 677 } vfp; 678 uint64_t exclusive_addr; 679 uint64_t exclusive_val; 680 uint64_t exclusive_high; 681 682 /* iwMMXt coprocessor state. */ 683 struct { 684 uint64_t regs[16]; 685 uint64_t val; 686 687 uint32_t cregs[16]; 688 } iwmmxt; 689 690 #ifdef TARGET_AARCH64 691 struct { 692 ARMPACKey apia; 693 ARMPACKey apib; 694 ARMPACKey apda; 695 ARMPACKey apdb; 696 ARMPACKey apga; 697 } keys; 698 699 uint64_t scxtnum_el[4]; 700 701 /* 702 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 703 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 704 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 705 * When SVL is less than the architectural maximum, the accessible 706 * storage is restricted, such that if the SVL is X bytes the guest can 707 * see only the bottom X elements of zarray[], and only the least 708 * significant X bytes of each element of the array. (In other words, 709 * the observable part is always square.) 710 * 711 * The ZA storage can also be considered as a set of square tiles of 712 * elements of different sizes. The mapping from tiles to the ZA array 713 * is architecturally defined, such that for tiles of elements of esz 714 * bytes, the Nth row (or "horizontal slice") of tile T is in 715 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 716 * in the ZA storage, because its rows are striped through the ZA array. 717 * 718 * Because this is so large, keep this toward the end of the reset area, 719 * to keep the offsets into the rest of the structure smaller. 720 */ 721 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 722 #endif 723 724 #if defined(CONFIG_USER_ONLY) 725 /* For usermode syscall translation. */ 726 int eabi; 727 #endif 728 729 struct CPUBreakpoint *cpu_breakpoint[16]; 730 struct CPUWatchpoint *cpu_watchpoint[16]; 731 732 /* Optional fault info across tlb lookup. */ 733 ARMMMUFaultInfo *tlb_fi; 734 735 /* Fields up to this point are cleared by a CPU reset */ 736 struct {} end_reset_fields; 737 738 /* Fields after this point are preserved across CPU reset. */ 739 740 /* Internal CPU feature flags. */ 741 uint64_t features; 742 743 /* PMSAv7 MPU */ 744 struct { 745 uint32_t *drbar; 746 uint32_t *drsr; 747 uint32_t *dracr; 748 uint32_t rnr[M_REG_NUM_BANKS]; 749 } pmsav7; 750 751 /* PMSAv8 MPU */ 752 struct { 753 /* The PMSAv8 implementation also shares some PMSAv7 config 754 * and state: 755 * pmsav7.rnr (region number register) 756 * pmsav7_dregion (number of configured regions) 757 */ 758 uint32_t *rbar[M_REG_NUM_BANKS]; 759 uint32_t *rlar[M_REG_NUM_BANKS]; 760 uint32_t *hprbar; 761 uint32_t *hprlar; 762 uint32_t mair0[M_REG_NUM_BANKS]; 763 uint32_t mair1[M_REG_NUM_BANKS]; 764 uint32_t hprselr; 765 } pmsav8; 766 767 /* v8M SAU */ 768 struct { 769 uint32_t *rbar; 770 uint32_t *rlar; 771 uint32_t rnr; 772 uint32_t ctrl; 773 } sau; 774 775 void *nvic; 776 const struct arm_boot_info *boot_info; 777 /* Store GICv3CPUState to access from this struct */ 778 void *gicv3state; 779 780 #ifdef TARGET_TAGGED_ADDRESSES 781 /* Linux syscall tagged address support */ 782 bool tagged_addr_enable; 783 #endif 784 } CPUARMState; 785 786 static inline void set_feature(CPUARMState *env, int feature) 787 { 788 env->features |= 1ULL << feature; 789 } 790 791 static inline void unset_feature(CPUARMState *env, int feature) 792 { 793 env->features &= ~(1ULL << feature); 794 } 795 796 /** 797 * ARMELChangeHookFn: 798 * type of a function which can be registered via arm_register_el_change_hook() 799 * to get callbacks when the CPU changes its exception level or mode. 800 */ 801 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 802 typedef struct ARMELChangeHook ARMELChangeHook; 803 struct ARMELChangeHook { 804 ARMELChangeHookFn *hook; 805 void *opaque; 806 QLIST_ENTRY(ARMELChangeHook) node; 807 }; 808 809 /* These values map onto the return values for 810 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 811 typedef enum ARMPSCIState { 812 PSCI_ON = 0, 813 PSCI_OFF = 1, 814 PSCI_ON_PENDING = 2 815 } ARMPSCIState; 816 817 typedef struct ARMISARegisters ARMISARegisters; 818 819 /* 820 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 821 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 822 * 823 * While processing properties during initialization, corresponding init bits 824 * are set for bits in sve_vq_map that have been set by properties. 825 * 826 * Bits set in supported represent valid vector lengths for the CPU type. 827 */ 828 typedef struct { 829 uint32_t map, init, supported; 830 } ARMVQMap; 831 832 /** 833 * ARMCPU: 834 * @env: #CPUARMState 835 * 836 * An ARM CPU core. 837 */ 838 struct ArchCPU { 839 /*< private >*/ 840 CPUState parent_obj; 841 /*< public >*/ 842 843 CPUNegativeOffsetState neg; 844 CPUARMState env; 845 846 /* Coprocessor information */ 847 GHashTable *cp_regs; 848 /* For marshalling (mostly coprocessor) register state between the 849 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 850 * we use these arrays. 851 */ 852 /* List of register indexes managed via these arrays; (full KVM style 853 * 64 bit indexes, not CPRegInfo 32 bit indexes) 854 */ 855 uint64_t *cpreg_indexes; 856 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 857 uint64_t *cpreg_values; 858 /* Length of the indexes, values, reset_values arrays */ 859 int32_t cpreg_array_len; 860 /* These are used only for migration: incoming data arrives in 861 * these fields and is sanity checked in post_load before copying 862 * to the working data structures above. 863 */ 864 uint64_t *cpreg_vmstate_indexes; 865 uint64_t *cpreg_vmstate_values; 866 int32_t cpreg_vmstate_array_len; 867 868 DynamicGDBXMLInfo dyn_sysreg_xml; 869 DynamicGDBXMLInfo dyn_svereg_xml; 870 871 /* Timers used by the generic (architected) timer */ 872 QEMUTimer *gt_timer[NUM_GTIMERS]; 873 /* 874 * Timer used by the PMU. Its state is restored after migration by 875 * pmu_op_finish() - it does not need other handling during migration 876 */ 877 QEMUTimer *pmu_timer; 878 /* GPIO outputs for generic timer */ 879 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 880 /* GPIO output for GICv3 maintenance interrupt signal */ 881 qemu_irq gicv3_maintenance_interrupt; 882 /* GPIO output for the PMU interrupt */ 883 qemu_irq pmu_interrupt; 884 885 /* MemoryRegion to use for secure physical accesses */ 886 MemoryRegion *secure_memory; 887 888 /* MemoryRegion to use for allocation tag accesses */ 889 MemoryRegion *tag_memory; 890 MemoryRegion *secure_tag_memory; 891 892 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 893 Object *idau; 894 895 /* 'compatible' string for this CPU for Linux device trees */ 896 const char *dtb_compatible; 897 898 /* PSCI version for this CPU 899 * Bits[31:16] = Major Version 900 * Bits[15:0] = Minor Version 901 */ 902 uint32_t psci_version; 903 904 /* Current power state, access guarded by BQL */ 905 ARMPSCIState power_state; 906 907 /* CPU has virtualization extension */ 908 bool has_el2; 909 /* CPU has security extension */ 910 bool has_el3; 911 /* CPU has PMU (Performance Monitor Unit) */ 912 bool has_pmu; 913 /* CPU has VFP */ 914 bool has_vfp; 915 /* CPU has Neon */ 916 bool has_neon; 917 /* CPU has M-profile DSP extension */ 918 bool has_dsp; 919 920 /* CPU has memory protection unit */ 921 bool has_mpu; 922 /* PMSAv7 MPU number of supported regions */ 923 uint32_t pmsav7_dregion; 924 /* PMSAv8 MPU number of supported hyp regions */ 925 uint32_t pmsav8r_hdregion; 926 /* v8M SAU number of supported regions */ 927 uint32_t sau_sregion; 928 929 /* PSCI conduit used to invoke PSCI methods 930 * 0 - disabled, 1 - smc, 2 - hvc 931 */ 932 uint32_t psci_conduit; 933 934 /* For v8M, initial value of the Secure VTOR */ 935 uint32_t init_svtor; 936 /* For v8M, initial value of the Non-secure VTOR */ 937 uint32_t init_nsvtor; 938 939 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 940 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 941 */ 942 uint32_t kvm_target; 943 944 /* KVM init features for this CPU */ 945 uint32_t kvm_init_features[7]; 946 947 /* KVM CPU state */ 948 949 /* KVM virtual time adjustment */ 950 bool kvm_adjvtime; 951 bool kvm_vtime_dirty; 952 uint64_t kvm_vtime; 953 954 /* KVM steal time */ 955 OnOffAuto kvm_steal_time; 956 957 /* Uniprocessor system with MP extensions */ 958 bool mp_is_up; 959 960 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 961 * and the probe failed (so we need to report the error in realize) 962 */ 963 bool host_cpu_probe_failed; 964 965 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 966 * register. 967 */ 968 int32_t core_count; 969 970 /* The instance init functions for implementation-specific subclasses 971 * set these fields to specify the implementation-dependent values of 972 * various constant registers and reset values of non-constant 973 * registers. 974 * Some of these might become QOM properties eventually. 975 * Field names match the official register names as defined in the 976 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 977 * is used for reset values of non-constant registers; no reset_ 978 * prefix means a constant register. 979 * Some of these registers are split out into a substructure that 980 * is shared with the translators to control the ISA. 981 * 982 * Note that if you add an ID register to the ARMISARegisters struct 983 * you need to also update the 32-bit and 64-bit versions of the 984 * kvm_arm_get_host_cpu_features() function to correctly populate the 985 * field by reading the value from the KVM vCPU. 986 */ 987 struct ARMISARegisters { 988 uint32_t id_isar0; 989 uint32_t id_isar1; 990 uint32_t id_isar2; 991 uint32_t id_isar3; 992 uint32_t id_isar4; 993 uint32_t id_isar5; 994 uint32_t id_isar6; 995 uint32_t id_mmfr0; 996 uint32_t id_mmfr1; 997 uint32_t id_mmfr2; 998 uint32_t id_mmfr3; 999 uint32_t id_mmfr4; 1000 uint32_t id_mmfr5; 1001 uint32_t id_pfr0; 1002 uint32_t id_pfr1; 1003 uint32_t id_pfr2; 1004 uint32_t mvfr0; 1005 uint32_t mvfr1; 1006 uint32_t mvfr2; 1007 uint32_t id_dfr0; 1008 uint32_t id_dfr1; 1009 uint32_t dbgdidr; 1010 uint32_t dbgdevid; 1011 uint32_t dbgdevid1; 1012 uint64_t id_aa64isar0; 1013 uint64_t id_aa64isar1; 1014 uint64_t id_aa64pfr0; 1015 uint64_t id_aa64pfr1; 1016 uint64_t id_aa64mmfr0; 1017 uint64_t id_aa64mmfr1; 1018 uint64_t id_aa64mmfr2; 1019 uint64_t id_aa64dfr0; 1020 uint64_t id_aa64dfr1; 1021 uint64_t id_aa64zfr0; 1022 uint64_t id_aa64smfr0; 1023 uint64_t reset_pmcr_el0; 1024 } isar; 1025 uint64_t midr; 1026 uint32_t revidr; 1027 uint32_t reset_fpsid; 1028 uint64_t ctr; 1029 uint32_t reset_sctlr; 1030 uint64_t pmceid0; 1031 uint64_t pmceid1; 1032 uint32_t id_afr0; 1033 uint64_t id_aa64afr0; 1034 uint64_t id_aa64afr1; 1035 uint64_t clidr; 1036 uint64_t mp_affinity; /* MP ID without feature bits */ 1037 /* The elements of this array are the CCSIDR values for each cache, 1038 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1039 */ 1040 uint64_t ccsidr[16]; 1041 uint64_t reset_cbar; 1042 uint32_t reset_auxcr; 1043 bool reset_hivecs; 1044 1045 /* 1046 * Intermediate values used during property parsing. 1047 * Once finalized, the values should be read from ID_AA64*. 1048 */ 1049 bool prop_pauth; 1050 bool prop_pauth_impdef; 1051 bool prop_lpa2; 1052 1053 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1054 uint32_t dcz_blocksize; 1055 uint64_t rvbar_prop; /* Property/input signals. */ 1056 1057 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1058 int gic_num_lrs; /* number of list registers */ 1059 int gic_vpribits; /* number of virtual priority bits */ 1060 int gic_vprebits; /* number of virtual preemption bits */ 1061 int gic_pribits; /* number of physical priority bits */ 1062 1063 /* Whether the cfgend input is high (i.e. this CPU should reset into 1064 * big-endian mode). This setting isn't used directly: instead it modifies 1065 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1066 * architecture version. 1067 */ 1068 bool cfgend; 1069 1070 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1071 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1072 1073 int32_t node_id; /* NUMA node this CPU belongs to */ 1074 1075 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1076 uint8_t device_irq_level; 1077 1078 /* Used to set the maximum vector length the cpu will support. */ 1079 uint32_t sve_max_vq; 1080 1081 #ifdef CONFIG_USER_ONLY 1082 /* Used to set the default vector length at process start. */ 1083 uint32_t sve_default_vq; 1084 uint32_t sme_default_vq; 1085 #endif 1086 1087 ARMVQMap sve_vq; 1088 ARMVQMap sme_vq; 1089 1090 /* Generic timer counter frequency, in Hz */ 1091 uint64_t gt_cntfrq_hz; 1092 }; 1093 1094 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1095 1096 void arm_cpu_post_init(Object *obj); 1097 1098 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1099 1100 #ifndef CONFIG_USER_ONLY 1101 extern const VMStateDescription vmstate_arm_cpu; 1102 1103 void arm_cpu_do_interrupt(CPUState *cpu); 1104 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1105 #endif /* !CONFIG_USER_ONLY */ 1106 1107 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1108 MemTxAttrs *attrs); 1109 1110 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1111 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1112 1113 /* 1114 * Helpers to dynamically generates XML descriptions of the sysregs 1115 * and SVE registers. Returns the number of registers in each set. 1116 */ 1117 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1118 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1119 1120 /* Returns the dynamically generated XML for the gdb stub. 1121 * Returns a pointer to the XML contents for the specified XML file or NULL 1122 * if the XML name doesn't match the predefined one. 1123 */ 1124 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1125 1126 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1127 int cpuid, DumpState *s); 1128 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1129 int cpuid, DumpState *s); 1130 1131 #ifdef TARGET_AARCH64 1132 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1133 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1134 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1135 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1136 int new_el, bool el0_a64); 1137 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1138 1139 /* 1140 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1141 * The byte at offset i from the start of the in-memory representation contains 1142 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1143 * lowest offsets are stored in the lowest memory addresses, then that nearly 1144 * matches QEMU's representation, which is to use an array of host-endian 1145 * uint64_t's, where the lower offsets are at the lower indices. To complete 1146 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1147 */ 1148 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1149 { 1150 #if HOST_BIG_ENDIAN 1151 int i; 1152 1153 for (i = 0; i < nr; ++i) { 1154 dst[i] = bswap64(src[i]); 1155 } 1156 1157 return dst; 1158 #else 1159 return src; 1160 #endif 1161 } 1162 1163 #else 1164 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1165 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1166 int n, bool a) 1167 { } 1168 #endif 1169 1170 void aarch64_sync_32_to_64(CPUARMState *env); 1171 void aarch64_sync_64_to_32(CPUARMState *env); 1172 1173 int fp_exception_el(CPUARMState *env, int cur_el); 1174 int sve_exception_el(CPUARMState *env, int cur_el); 1175 int sme_exception_el(CPUARMState *env, int cur_el); 1176 1177 /** 1178 * sve_vqm1_for_el_sm: 1179 * @env: CPUARMState 1180 * @el: exception level 1181 * @sm: streaming mode 1182 * 1183 * Compute the current vector length for @el & @sm, in units of 1184 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1185 * If @sm, compute for SVL, otherwise NVL. 1186 */ 1187 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1188 1189 /* Likewise, but using @sm = PSTATE.SM. */ 1190 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1191 1192 static inline bool is_a64(CPUARMState *env) 1193 { 1194 return env->aarch64; 1195 } 1196 1197 /** 1198 * pmu_op_start/finish 1199 * @env: CPUARMState 1200 * 1201 * Convert all PMU counters between their delta form (the typical mode when 1202 * they are enabled) and the guest-visible values. These two calls must 1203 * surround any action which might affect the counters. 1204 */ 1205 void pmu_op_start(CPUARMState *env); 1206 void pmu_op_finish(CPUARMState *env); 1207 1208 /* 1209 * Called when a PMU counter is due to overflow 1210 */ 1211 void arm_pmu_timer_cb(void *opaque); 1212 1213 /** 1214 * Functions to register as EL change hooks for PMU mode filtering 1215 */ 1216 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1217 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1218 1219 /* 1220 * pmu_init 1221 * @cpu: ARMCPU 1222 * 1223 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1224 * for the current configuration 1225 */ 1226 void pmu_init(ARMCPU *cpu); 1227 1228 /* SCTLR bit meanings. Several bits have been reused in newer 1229 * versions of the architecture; in that case we define constants 1230 * for both old and new bit meanings. Code which tests against those 1231 * bits should probably check or otherwise arrange that the CPU 1232 * is the architectural version it expects. 1233 */ 1234 #define SCTLR_M (1U << 0) 1235 #define SCTLR_A (1U << 1) 1236 #define SCTLR_C (1U << 2) 1237 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1238 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1239 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1240 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1241 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1242 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1243 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1244 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1245 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1246 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1247 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1248 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1249 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1250 #define SCTLR_SED (1U << 8) /* v8 onward */ 1251 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1252 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1253 #define SCTLR_F (1U << 10) /* up to v6 */ 1254 #define SCTLR_SW (1U << 10) /* v7 */ 1255 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1256 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1257 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1258 #define SCTLR_I (1U << 12) 1259 #define SCTLR_V (1U << 13) /* AArch32 only */ 1260 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1261 #define SCTLR_RR (1U << 14) /* up to v7 */ 1262 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1263 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1264 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1265 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1266 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1267 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1268 #define SCTLR_BR (1U << 17) /* PMSA only */ 1269 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1270 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1271 #define SCTLR_WXN (1U << 19) 1272 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1273 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1274 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1275 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1276 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1277 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1278 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1279 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1280 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1281 #define SCTLR_VE (1U << 24) /* up to v7 */ 1282 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1283 #define SCTLR_EE (1U << 25) 1284 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1285 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1286 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1287 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1288 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1289 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1290 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1291 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1292 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1293 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1294 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1295 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1296 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1297 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1298 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1299 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1300 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1301 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1302 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1303 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1304 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1305 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1306 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1307 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1308 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1309 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1310 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1311 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1312 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1313 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1314 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1315 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1316 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1317 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1318 1319 /* Bit definitions for CPACR (AArch32 only) */ 1320 FIELD(CPACR, CP10, 20, 2) 1321 FIELD(CPACR, CP11, 22, 2) 1322 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1323 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1324 FIELD(CPACR, ASEDIS, 31, 1) 1325 1326 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1327 FIELD(CPACR_EL1, ZEN, 16, 2) 1328 FIELD(CPACR_EL1, FPEN, 20, 2) 1329 FIELD(CPACR_EL1, SMEN, 24, 2) 1330 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1331 1332 /* Bit definitions for HCPTR (AArch32 only) */ 1333 FIELD(HCPTR, TCP10, 10, 1) 1334 FIELD(HCPTR, TCP11, 11, 1) 1335 FIELD(HCPTR, TASE, 15, 1) 1336 FIELD(HCPTR, TTA, 20, 1) 1337 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1338 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1339 1340 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1341 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1342 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1343 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1344 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1345 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1346 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1347 FIELD(CPTR_EL2, TTA, 28, 1) 1348 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1349 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1350 1351 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1352 FIELD(CPTR_EL3, EZ, 8, 1) 1353 FIELD(CPTR_EL3, TFP, 10, 1) 1354 FIELD(CPTR_EL3, ESM, 12, 1) 1355 FIELD(CPTR_EL3, TTA, 20, 1) 1356 FIELD(CPTR_EL3, TAM, 30, 1) 1357 FIELD(CPTR_EL3, TCPAC, 31, 1) 1358 1359 #define MDCR_MTPME (1U << 28) 1360 #define MDCR_TDCC (1U << 27) 1361 #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ 1362 #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ 1363 #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ 1364 #define MDCR_EPMAD (1U << 21) 1365 #define MDCR_EDAD (1U << 20) 1366 #define MDCR_TTRF (1U << 19) 1367 #define MDCR_STE (1U << 18) /* MDCR_EL3 */ 1368 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1369 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1370 #define MDCR_SDD (1U << 16) 1371 #define MDCR_SPD (3U << 14) 1372 #define MDCR_TDRA (1U << 11) 1373 #define MDCR_TDOSA (1U << 10) 1374 #define MDCR_TDA (1U << 9) 1375 #define MDCR_TDE (1U << 8) 1376 #define MDCR_HPME (1U << 7) 1377 #define MDCR_TPM (1U << 6) 1378 #define MDCR_TPMCR (1U << 5) 1379 #define MDCR_HPMN (0x1fU) 1380 1381 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1382 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ 1383 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ 1384 MDCR_STE | MDCR_SPME | MDCR_SPD) 1385 1386 #define CPSR_M (0x1fU) 1387 #define CPSR_T (1U << 5) 1388 #define CPSR_F (1U << 6) 1389 #define CPSR_I (1U << 7) 1390 #define CPSR_A (1U << 8) 1391 #define CPSR_E (1U << 9) 1392 #define CPSR_IT_2_7 (0xfc00U) 1393 #define CPSR_GE (0xfU << 16) 1394 #define CPSR_IL (1U << 20) 1395 #define CPSR_DIT (1U << 21) 1396 #define CPSR_PAN (1U << 22) 1397 #define CPSR_SSBS (1U << 23) 1398 #define CPSR_J (1U << 24) 1399 #define CPSR_IT_0_1 (3U << 25) 1400 #define CPSR_Q (1U << 27) 1401 #define CPSR_V (1U << 28) 1402 #define CPSR_C (1U << 29) 1403 #define CPSR_Z (1U << 30) 1404 #define CPSR_N (1U << 31) 1405 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1406 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1407 1408 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1409 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1410 | CPSR_NZCV) 1411 /* Bits writable in user mode. */ 1412 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1413 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1414 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1415 1416 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1417 #define XPSR_EXCP 0x1ffU 1418 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1419 #define XPSR_IT_2_7 CPSR_IT_2_7 1420 #define XPSR_GE CPSR_GE 1421 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1422 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1423 #define XPSR_IT_0_1 CPSR_IT_0_1 1424 #define XPSR_Q CPSR_Q 1425 #define XPSR_V CPSR_V 1426 #define XPSR_C CPSR_C 1427 #define XPSR_Z CPSR_Z 1428 #define XPSR_N CPSR_N 1429 #define XPSR_NZCV CPSR_NZCV 1430 #define XPSR_IT CPSR_IT 1431 1432 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1433 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1434 #define TTBCR_PD0 (1U << 4) 1435 #define TTBCR_PD1 (1U << 5) 1436 #define TTBCR_EPD0 (1U << 7) 1437 #define TTBCR_IRGN0 (3U << 8) 1438 #define TTBCR_ORGN0 (3U << 10) 1439 #define TTBCR_SH0 (3U << 12) 1440 #define TTBCR_T1SZ (3U << 16) 1441 #define TTBCR_A1 (1U << 22) 1442 #define TTBCR_EPD1 (1U << 23) 1443 #define TTBCR_IRGN1 (3U << 24) 1444 #define TTBCR_ORGN1 (3U << 26) 1445 #define TTBCR_SH1 (1U << 28) 1446 #define TTBCR_EAE (1U << 31) 1447 1448 FIELD(VTCR, T0SZ, 0, 6) 1449 FIELD(VTCR, SL0, 6, 2) 1450 FIELD(VTCR, IRGN0, 8, 2) 1451 FIELD(VTCR, ORGN0, 10, 2) 1452 FIELD(VTCR, SH0, 12, 2) 1453 FIELD(VTCR, TG0, 14, 2) 1454 FIELD(VTCR, PS, 16, 3) 1455 FIELD(VTCR, VS, 19, 1) 1456 FIELD(VTCR, HA, 21, 1) 1457 FIELD(VTCR, HD, 22, 1) 1458 FIELD(VTCR, HWU59, 25, 1) 1459 FIELD(VTCR, HWU60, 26, 1) 1460 FIELD(VTCR, HWU61, 27, 1) 1461 FIELD(VTCR, HWU62, 28, 1) 1462 FIELD(VTCR, NSW, 29, 1) 1463 FIELD(VTCR, NSA, 30, 1) 1464 FIELD(VTCR, DS, 32, 1) 1465 FIELD(VTCR, SL2, 33, 1) 1466 1467 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1468 * Only these are valid when in AArch64 mode; in 1469 * AArch32 mode SPSRs are basically CPSR-format. 1470 */ 1471 #define PSTATE_SP (1U) 1472 #define PSTATE_M (0xFU) 1473 #define PSTATE_nRW (1U << 4) 1474 #define PSTATE_F (1U << 6) 1475 #define PSTATE_I (1U << 7) 1476 #define PSTATE_A (1U << 8) 1477 #define PSTATE_D (1U << 9) 1478 #define PSTATE_BTYPE (3U << 10) 1479 #define PSTATE_SSBS (1U << 12) 1480 #define PSTATE_IL (1U << 20) 1481 #define PSTATE_SS (1U << 21) 1482 #define PSTATE_PAN (1U << 22) 1483 #define PSTATE_UAO (1U << 23) 1484 #define PSTATE_DIT (1U << 24) 1485 #define PSTATE_TCO (1U << 25) 1486 #define PSTATE_V (1U << 28) 1487 #define PSTATE_C (1U << 29) 1488 #define PSTATE_Z (1U << 30) 1489 #define PSTATE_N (1U << 31) 1490 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1491 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1492 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1493 /* Mode values for AArch64 */ 1494 #define PSTATE_MODE_EL3h 13 1495 #define PSTATE_MODE_EL3t 12 1496 #define PSTATE_MODE_EL2h 9 1497 #define PSTATE_MODE_EL2t 8 1498 #define PSTATE_MODE_EL1h 5 1499 #define PSTATE_MODE_EL1t 4 1500 #define PSTATE_MODE_EL0t 0 1501 1502 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1503 FIELD(SVCR, SM, 0, 1) 1504 FIELD(SVCR, ZA, 1, 1) 1505 1506 /* Fields for SMCR_ELx. */ 1507 FIELD(SMCR, LEN, 0, 4) 1508 FIELD(SMCR, FA64, 31, 1) 1509 1510 /* Write a new value to v7m.exception, thus transitioning into or out 1511 * of Handler mode; this may result in a change of active stack pointer. 1512 */ 1513 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1514 1515 /* Map EL and handler into a PSTATE_MODE. */ 1516 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1517 { 1518 return (el << 2) | handler; 1519 } 1520 1521 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1522 * interprocessing, so we don't attempt to sync with the cpsr state used by 1523 * the 32 bit decoder. 1524 */ 1525 static inline uint32_t pstate_read(CPUARMState *env) 1526 { 1527 int ZF; 1528 1529 ZF = (env->ZF == 0); 1530 return (env->NF & 0x80000000) | (ZF << 30) 1531 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1532 | env->pstate | env->daif | (env->btype << 10); 1533 } 1534 1535 static inline void pstate_write(CPUARMState *env, uint32_t val) 1536 { 1537 env->ZF = (~val) & PSTATE_Z; 1538 env->NF = val; 1539 env->CF = (val >> 29) & 1; 1540 env->VF = (val << 3) & 0x80000000; 1541 env->daif = val & PSTATE_DAIF; 1542 env->btype = (val >> 10) & 3; 1543 env->pstate = val & ~CACHED_PSTATE_BITS; 1544 } 1545 1546 /* Return the current CPSR value. */ 1547 uint32_t cpsr_read(CPUARMState *env); 1548 1549 typedef enum CPSRWriteType { 1550 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1551 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1552 CPSRWriteRaw = 2, 1553 /* trust values, no reg bank switch, no hflags rebuild */ 1554 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1555 } CPSRWriteType; 1556 1557 /* 1558 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1559 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1560 * correspond to TB flags bits cached in the hflags, unless @write_type 1561 * is CPSRWriteRaw. 1562 */ 1563 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1564 CPSRWriteType write_type); 1565 1566 /* Return the current xPSR value. */ 1567 static inline uint32_t xpsr_read(CPUARMState *env) 1568 { 1569 int ZF; 1570 ZF = (env->ZF == 0); 1571 return (env->NF & 0x80000000) | (ZF << 30) 1572 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1573 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1574 | ((env->condexec_bits & 0xfc) << 8) 1575 | (env->GE << 16) 1576 | env->v7m.exception; 1577 } 1578 1579 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1580 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1581 { 1582 if (mask & XPSR_NZCV) { 1583 env->ZF = (~val) & XPSR_Z; 1584 env->NF = val; 1585 env->CF = (val >> 29) & 1; 1586 env->VF = (val << 3) & 0x80000000; 1587 } 1588 if (mask & XPSR_Q) { 1589 env->QF = ((val & XPSR_Q) != 0); 1590 } 1591 if (mask & XPSR_GE) { 1592 env->GE = (val & XPSR_GE) >> 16; 1593 } 1594 #ifndef CONFIG_USER_ONLY 1595 if (mask & XPSR_T) { 1596 env->thumb = ((val & XPSR_T) != 0); 1597 } 1598 if (mask & XPSR_IT_0_1) { 1599 env->condexec_bits &= ~3; 1600 env->condexec_bits |= (val >> 25) & 3; 1601 } 1602 if (mask & XPSR_IT_2_7) { 1603 env->condexec_bits &= 3; 1604 env->condexec_bits |= (val >> 8) & 0xfc; 1605 } 1606 if (mask & XPSR_EXCP) { 1607 /* Note that this only happens on exception exit */ 1608 write_v7m_exception(env, val & XPSR_EXCP); 1609 } 1610 #endif 1611 } 1612 1613 #define HCR_VM (1ULL << 0) 1614 #define HCR_SWIO (1ULL << 1) 1615 #define HCR_PTW (1ULL << 2) 1616 #define HCR_FMO (1ULL << 3) 1617 #define HCR_IMO (1ULL << 4) 1618 #define HCR_AMO (1ULL << 5) 1619 #define HCR_VF (1ULL << 6) 1620 #define HCR_VI (1ULL << 7) 1621 #define HCR_VSE (1ULL << 8) 1622 #define HCR_FB (1ULL << 9) 1623 #define HCR_BSU_MASK (3ULL << 10) 1624 #define HCR_DC (1ULL << 12) 1625 #define HCR_TWI (1ULL << 13) 1626 #define HCR_TWE (1ULL << 14) 1627 #define HCR_TID0 (1ULL << 15) 1628 #define HCR_TID1 (1ULL << 16) 1629 #define HCR_TID2 (1ULL << 17) 1630 #define HCR_TID3 (1ULL << 18) 1631 #define HCR_TSC (1ULL << 19) 1632 #define HCR_TIDCP (1ULL << 20) 1633 #define HCR_TACR (1ULL << 21) 1634 #define HCR_TSW (1ULL << 22) 1635 #define HCR_TPCP (1ULL << 23) 1636 #define HCR_TPU (1ULL << 24) 1637 #define HCR_TTLB (1ULL << 25) 1638 #define HCR_TVM (1ULL << 26) 1639 #define HCR_TGE (1ULL << 27) 1640 #define HCR_TDZ (1ULL << 28) 1641 #define HCR_HCD (1ULL << 29) 1642 #define HCR_TRVM (1ULL << 30) 1643 #define HCR_RW (1ULL << 31) 1644 #define HCR_CD (1ULL << 32) 1645 #define HCR_ID (1ULL << 33) 1646 #define HCR_E2H (1ULL << 34) 1647 #define HCR_TLOR (1ULL << 35) 1648 #define HCR_TERR (1ULL << 36) 1649 #define HCR_TEA (1ULL << 37) 1650 #define HCR_MIOCNCE (1ULL << 38) 1651 /* RES0 bit 39 */ 1652 #define HCR_APK (1ULL << 40) 1653 #define HCR_API (1ULL << 41) 1654 #define HCR_NV (1ULL << 42) 1655 #define HCR_NV1 (1ULL << 43) 1656 #define HCR_AT (1ULL << 44) 1657 #define HCR_NV2 (1ULL << 45) 1658 #define HCR_FWB (1ULL << 46) 1659 #define HCR_FIEN (1ULL << 47) 1660 /* RES0 bit 48 */ 1661 #define HCR_TID4 (1ULL << 49) 1662 #define HCR_TICAB (1ULL << 50) 1663 #define HCR_AMVOFFEN (1ULL << 51) 1664 #define HCR_TOCU (1ULL << 52) 1665 #define HCR_ENSCXT (1ULL << 53) 1666 #define HCR_TTLBIS (1ULL << 54) 1667 #define HCR_TTLBOS (1ULL << 55) 1668 #define HCR_ATA (1ULL << 56) 1669 #define HCR_DCT (1ULL << 57) 1670 #define HCR_TID5 (1ULL << 58) 1671 #define HCR_TWEDEN (1ULL << 59) 1672 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1673 1674 #define HCRX_ENAS0 (1ULL << 0) 1675 #define HCRX_ENALS (1ULL << 1) 1676 #define HCRX_ENASR (1ULL << 2) 1677 #define HCRX_FNXS (1ULL << 3) 1678 #define HCRX_FGTNXS (1ULL << 4) 1679 #define HCRX_SMPME (1ULL << 5) 1680 #define HCRX_TALLINT (1ULL << 6) 1681 #define HCRX_VINMI (1ULL << 7) 1682 #define HCRX_VFNMI (1ULL << 8) 1683 #define HCRX_CMOW (1ULL << 9) 1684 #define HCRX_MCE2 (1ULL << 10) 1685 #define HCRX_MSCEN (1ULL << 11) 1686 1687 #define HPFAR_NS (1ULL << 63) 1688 1689 #define SCR_NS (1ULL << 0) 1690 #define SCR_IRQ (1ULL << 1) 1691 #define SCR_FIQ (1ULL << 2) 1692 #define SCR_EA (1ULL << 3) 1693 #define SCR_FW (1ULL << 4) 1694 #define SCR_AW (1ULL << 5) 1695 #define SCR_NET (1ULL << 6) 1696 #define SCR_SMD (1ULL << 7) 1697 #define SCR_HCE (1ULL << 8) 1698 #define SCR_SIF (1ULL << 9) 1699 #define SCR_RW (1ULL << 10) 1700 #define SCR_ST (1ULL << 11) 1701 #define SCR_TWI (1ULL << 12) 1702 #define SCR_TWE (1ULL << 13) 1703 #define SCR_TLOR (1ULL << 14) 1704 #define SCR_TERR (1ULL << 15) 1705 #define SCR_APK (1ULL << 16) 1706 #define SCR_API (1ULL << 17) 1707 #define SCR_EEL2 (1ULL << 18) 1708 #define SCR_EASE (1ULL << 19) 1709 #define SCR_NMEA (1ULL << 20) 1710 #define SCR_FIEN (1ULL << 21) 1711 #define SCR_ENSCXT (1ULL << 25) 1712 #define SCR_ATA (1ULL << 26) 1713 #define SCR_FGTEN (1ULL << 27) 1714 #define SCR_ECVEN (1ULL << 28) 1715 #define SCR_TWEDEN (1ULL << 29) 1716 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1717 #define SCR_TME (1ULL << 34) 1718 #define SCR_AMVOFFEN (1ULL << 35) 1719 #define SCR_ENAS0 (1ULL << 36) 1720 #define SCR_ADEN (1ULL << 37) 1721 #define SCR_HXEN (1ULL << 38) 1722 #define SCR_TRNDR (1ULL << 40) 1723 #define SCR_ENTP2 (1ULL << 41) 1724 #define SCR_GPF (1ULL << 48) 1725 1726 #define HSTR_TTEE (1 << 16) 1727 #define HSTR_TJDBX (1 << 17) 1728 1729 /* Return the current FPSCR value. */ 1730 uint32_t vfp_get_fpscr(CPUARMState *env); 1731 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1732 1733 /* FPCR, Floating Point Control Register 1734 * FPSR, Floating Poiht Status Register 1735 * 1736 * For A64 the FPSCR is split into two logically distinct registers, 1737 * FPCR and FPSR. However since they still use non-overlapping bits 1738 * we store the underlying state in fpscr and just mask on read/write. 1739 */ 1740 #define FPSR_MASK 0xf800009f 1741 #define FPCR_MASK 0x07ff9f00 1742 1743 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1744 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1745 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1746 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1747 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1748 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1749 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1750 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1751 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1752 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1753 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1754 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1755 #define FPCR_V (1 << 28) /* FP overflow flag */ 1756 #define FPCR_C (1 << 29) /* FP carry flag */ 1757 #define FPCR_Z (1 << 30) /* FP zero flag */ 1758 #define FPCR_N (1 << 31) /* FP negative flag */ 1759 1760 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1761 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1762 #define FPCR_LTPSIZE_LENGTH 3 1763 1764 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1765 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1766 1767 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1768 { 1769 return vfp_get_fpscr(env) & FPSR_MASK; 1770 } 1771 1772 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1773 { 1774 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1775 vfp_set_fpscr(env, new_fpscr); 1776 } 1777 1778 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1779 { 1780 return vfp_get_fpscr(env) & FPCR_MASK; 1781 } 1782 1783 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1784 { 1785 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1786 vfp_set_fpscr(env, new_fpscr); 1787 } 1788 1789 enum arm_cpu_mode { 1790 ARM_CPU_MODE_USR = 0x10, 1791 ARM_CPU_MODE_FIQ = 0x11, 1792 ARM_CPU_MODE_IRQ = 0x12, 1793 ARM_CPU_MODE_SVC = 0x13, 1794 ARM_CPU_MODE_MON = 0x16, 1795 ARM_CPU_MODE_ABT = 0x17, 1796 ARM_CPU_MODE_HYP = 0x1a, 1797 ARM_CPU_MODE_UND = 0x1b, 1798 ARM_CPU_MODE_SYS = 0x1f 1799 }; 1800 1801 /* VFP system registers. */ 1802 #define ARM_VFP_FPSID 0 1803 #define ARM_VFP_FPSCR 1 1804 #define ARM_VFP_MVFR2 5 1805 #define ARM_VFP_MVFR1 6 1806 #define ARM_VFP_MVFR0 7 1807 #define ARM_VFP_FPEXC 8 1808 #define ARM_VFP_FPINST 9 1809 #define ARM_VFP_FPINST2 10 1810 /* These ones are M-profile only */ 1811 #define ARM_VFP_FPSCR_NZCVQC 2 1812 #define ARM_VFP_VPR 12 1813 #define ARM_VFP_P0 13 1814 #define ARM_VFP_FPCXT_NS 14 1815 #define ARM_VFP_FPCXT_S 15 1816 1817 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1818 #define QEMU_VFP_FPSCR_NZCV 0xffff 1819 1820 /* iwMMXt coprocessor control registers. */ 1821 #define ARM_IWMMXT_wCID 0 1822 #define ARM_IWMMXT_wCon 1 1823 #define ARM_IWMMXT_wCSSF 2 1824 #define ARM_IWMMXT_wCASF 3 1825 #define ARM_IWMMXT_wCGR0 8 1826 #define ARM_IWMMXT_wCGR1 9 1827 #define ARM_IWMMXT_wCGR2 10 1828 #define ARM_IWMMXT_wCGR3 11 1829 1830 /* V7M CCR bits */ 1831 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1832 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1833 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1834 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1835 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1836 FIELD(V7M_CCR, STKALIGN, 9, 1) 1837 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1838 FIELD(V7M_CCR, DC, 16, 1) 1839 FIELD(V7M_CCR, IC, 17, 1) 1840 FIELD(V7M_CCR, BP, 18, 1) 1841 FIELD(V7M_CCR, LOB, 19, 1) 1842 FIELD(V7M_CCR, TRD, 20, 1) 1843 1844 /* V7M SCR bits */ 1845 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1846 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1847 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1848 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1849 1850 /* V7M AIRCR bits */ 1851 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1852 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1853 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1854 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1855 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1856 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1857 FIELD(V7M_AIRCR, PRIS, 14, 1) 1858 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1859 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1860 1861 /* V7M CFSR bits for MMFSR */ 1862 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1863 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1864 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1865 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1866 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1867 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1868 1869 /* V7M CFSR bits for BFSR */ 1870 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1871 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1872 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1873 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1874 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1875 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1876 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1877 1878 /* V7M CFSR bits for UFSR */ 1879 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1880 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1881 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1882 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1883 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1884 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1885 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1886 1887 /* V7M CFSR bit masks covering all of the subregister bits */ 1888 FIELD(V7M_CFSR, MMFSR, 0, 8) 1889 FIELD(V7M_CFSR, BFSR, 8, 8) 1890 FIELD(V7M_CFSR, UFSR, 16, 16) 1891 1892 /* V7M HFSR bits */ 1893 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1894 FIELD(V7M_HFSR, FORCED, 30, 1) 1895 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1896 1897 /* V7M DFSR bits */ 1898 FIELD(V7M_DFSR, HALTED, 0, 1) 1899 FIELD(V7M_DFSR, BKPT, 1, 1) 1900 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1901 FIELD(V7M_DFSR, VCATCH, 3, 1) 1902 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1903 1904 /* V7M SFSR bits */ 1905 FIELD(V7M_SFSR, INVEP, 0, 1) 1906 FIELD(V7M_SFSR, INVIS, 1, 1) 1907 FIELD(V7M_SFSR, INVER, 2, 1) 1908 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1909 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1910 FIELD(V7M_SFSR, LSPERR, 5, 1) 1911 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1912 FIELD(V7M_SFSR, LSERR, 7, 1) 1913 1914 /* v7M MPU_CTRL bits */ 1915 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1916 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1917 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1918 1919 /* v7M CLIDR bits */ 1920 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1921 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1922 FIELD(V7M_CLIDR, LOC, 24, 3) 1923 FIELD(V7M_CLIDR, LOUU, 27, 3) 1924 FIELD(V7M_CLIDR, ICB, 30, 2) 1925 1926 FIELD(V7M_CSSELR, IND, 0, 1) 1927 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1928 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1929 * define a mask for this and check that it doesn't permit running off 1930 * the end of the array. 1931 */ 1932 FIELD(V7M_CSSELR, INDEX, 0, 4) 1933 1934 /* v7M FPCCR bits */ 1935 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1936 FIELD(V7M_FPCCR, USER, 1, 1) 1937 FIELD(V7M_FPCCR, S, 2, 1) 1938 FIELD(V7M_FPCCR, THREAD, 3, 1) 1939 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1940 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1941 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1942 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1943 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1944 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1945 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1946 FIELD(V7M_FPCCR, RES0, 11, 15) 1947 FIELD(V7M_FPCCR, TS, 26, 1) 1948 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1949 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1950 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1951 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1952 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1953 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1954 #define R_V7M_FPCCR_BANKED_MASK \ 1955 (R_V7M_FPCCR_LSPACT_MASK | \ 1956 R_V7M_FPCCR_USER_MASK | \ 1957 R_V7M_FPCCR_THREAD_MASK | \ 1958 R_V7M_FPCCR_MMRDY_MASK | \ 1959 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1960 R_V7M_FPCCR_UFRDY_MASK | \ 1961 R_V7M_FPCCR_ASPEN_MASK) 1962 1963 /* v7M VPR bits */ 1964 FIELD(V7M_VPR, P0, 0, 16) 1965 FIELD(V7M_VPR, MASK01, 16, 4) 1966 FIELD(V7M_VPR, MASK23, 20, 4) 1967 1968 /* 1969 * System register ID fields. 1970 */ 1971 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1972 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1973 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1974 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1975 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1976 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1977 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1978 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1979 FIELD(CLIDR_EL1, LOC, 24, 3) 1980 FIELD(CLIDR_EL1, LOUU, 27, 3) 1981 FIELD(CLIDR_EL1, ICB, 30, 3) 1982 1983 /* When FEAT_CCIDX is implemented */ 1984 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1985 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1986 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1987 1988 /* When FEAT_CCIDX is not implemented */ 1989 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1990 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1991 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1992 1993 FIELD(CTR_EL0, IMINLINE, 0, 4) 1994 FIELD(CTR_EL0, L1IP, 14, 2) 1995 FIELD(CTR_EL0, DMINLINE, 16, 4) 1996 FIELD(CTR_EL0, ERG, 20, 4) 1997 FIELD(CTR_EL0, CWG, 24, 4) 1998 FIELD(CTR_EL0, IDC, 28, 1) 1999 FIELD(CTR_EL0, DIC, 29, 1) 2000 FIELD(CTR_EL0, TMINLINE, 32, 6) 2001 2002 FIELD(MIDR_EL1, REVISION, 0, 4) 2003 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2004 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2005 FIELD(MIDR_EL1, VARIANT, 20, 4) 2006 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2007 2008 FIELD(ID_ISAR0, SWAP, 0, 4) 2009 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2010 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2011 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2012 FIELD(ID_ISAR0, COPROC, 16, 4) 2013 FIELD(ID_ISAR0, DEBUG, 20, 4) 2014 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2015 2016 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2017 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2018 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2019 FIELD(ID_ISAR1, EXTEND, 12, 4) 2020 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2021 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2022 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2023 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2024 2025 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2026 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2027 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2028 FIELD(ID_ISAR2, MULT, 12, 4) 2029 FIELD(ID_ISAR2, MULTS, 16, 4) 2030 FIELD(ID_ISAR2, MULTU, 20, 4) 2031 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2032 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2033 2034 FIELD(ID_ISAR3, SATURATE, 0, 4) 2035 FIELD(ID_ISAR3, SIMD, 4, 4) 2036 FIELD(ID_ISAR3, SVC, 8, 4) 2037 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2038 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2039 FIELD(ID_ISAR3, T32COPY, 20, 4) 2040 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2041 FIELD(ID_ISAR3, T32EE, 28, 4) 2042 2043 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2044 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2045 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2046 FIELD(ID_ISAR4, SMC, 12, 4) 2047 FIELD(ID_ISAR4, BARRIER, 16, 4) 2048 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2049 FIELD(ID_ISAR4, PSR_M, 24, 4) 2050 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2051 2052 FIELD(ID_ISAR5, SEVL, 0, 4) 2053 FIELD(ID_ISAR5, AES, 4, 4) 2054 FIELD(ID_ISAR5, SHA1, 8, 4) 2055 FIELD(ID_ISAR5, SHA2, 12, 4) 2056 FIELD(ID_ISAR5, CRC32, 16, 4) 2057 FIELD(ID_ISAR5, RDM, 24, 4) 2058 FIELD(ID_ISAR5, VCMA, 28, 4) 2059 2060 FIELD(ID_ISAR6, JSCVT, 0, 4) 2061 FIELD(ID_ISAR6, DP, 4, 4) 2062 FIELD(ID_ISAR6, FHM, 8, 4) 2063 FIELD(ID_ISAR6, SB, 12, 4) 2064 FIELD(ID_ISAR6, SPECRES, 16, 4) 2065 FIELD(ID_ISAR6, BF16, 20, 4) 2066 FIELD(ID_ISAR6, I8MM, 24, 4) 2067 2068 FIELD(ID_MMFR0, VMSA, 0, 4) 2069 FIELD(ID_MMFR0, PMSA, 4, 4) 2070 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2071 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2072 FIELD(ID_MMFR0, TCM, 16, 4) 2073 FIELD(ID_MMFR0, AUXREG, 20, 4) 2074 FIELD(ID_MMFR0, FCSE, 24, 4) 2075 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2076 2077 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2078 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2079 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2080 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2081 FIELD(ID_MMFR1, L1HVD, 16, 4) 2082 FIELD(ID_MMFR1, L1UNI, 20, 4) 2083 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2084 FIELD(ID_MMFR1, BPRED, 28, 4) 2085 2086 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2087 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2088 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2089 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2090 FIELD(ID_MMFR2, UNITLB, 16, 4) 2091 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2092 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2093 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2094 2095 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2096 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2097 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2098 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2099 FIELD(ID_MMFR3, PAN, 16, 4) 2100 FIELD(ID_MMFR3, COHWALK, 20, 4) 2101 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2102 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2103 2104 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2105 FIELD(ID_MMFR4, AC2, 4, 4) 2106 FIELD(ID_MMFR4, XNX, 8, 4) 2107 FIELD(ID_MMFR4, CNP, 12, 4) 2108 FIELD(ID_MMFR4, HPDS, 16, 4) 2109 FIELD(ID_MMFR4, LSM, 20, 4) 2110 FIELD(ID_MMFR4, CCIDX, 24, 4) 2111 FIELD(ID_MMFR4, EVT, 28, 4) 2112 2113 FIELD(ID_MMFR5, ETS, 0, 4) 2114 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2115 2116 FIELD(ID_PFR0, STATE0, 0, 4) 2117 FIELD(ID_PFR0, STATE1, 4, 4) 2118 FIELD(ID_PFR0, STATE2, 8, 4) 2119 FIELD(ID_PFR0, STATE3, 12, 4) 2120 FIELD(ID_PFR0, CSV2, 16, 4) 2121 FIELD(ID_PFR0, AMU, 20, 4) 2122 FIELD(ID_PFR0, DIT, 24, 4) 2123 FIELD(ID_PFR0, RAS, 28, 4) 2124 2125 FIELD(ID_PFR1, PROGMOD, 0, 4) 2126 FIELD(ID_PFR1, SECURITY, 4, 4) 2127 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2128 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2129 FIELD(ID_PFR1, GENTIMER, 16, 4) 2130 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2131 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2132 FIELD(ID_PFR1, GIC, 28, 4) 2133 2134 FIELD(ID_PFR2, CSV3, 0, 4) 2135 FIELD(ID_PFR2, SSBS, 4, 4) 2136 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2137 2138 FIELD(ID_AA64ISAR0, AES, 4, 4) 2139 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2140 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2141 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2142 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2143 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2144 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2145 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2146 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2147 FIELD(ID_AA64ISAR0, DP, 44, 4) 2148 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2149 FIELD(ID_AA64ISAR0, TS, 52, 4) 2150 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2151 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2152 2153 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2154 FIELD(ID_AA64ISAR1, APA, 4, 4) 2155 FIELD(ID_AA64ISAR1, API, 8, 4) 2156 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2157 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2158 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2159 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2160 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2161 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2162 FIELD(ID_AA64ISAR1, SB, 36, 4) 2163 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2164 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2165 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2166 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2167 FIELD(ID_AA64ISAR1, XS, 56, 4) 2168 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2169 2170 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2171 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2172 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2173 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2174 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2175 FIELD(ID_AA64ISAR2, BC, 20, 4) 2176 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2177 2178 FIELD(ID_AA64PFR0, EL0, 0, 4) 2179 FIELD(ID_AA64PFR0, EL1, 4, 4) 2180 FIELD(ID_AA64PFR0, EL2, 8, 4) 2181 FIELD(ID_AA64PFR0, EL3, 12, 4) 2182 FIELD(ID_AA64PFR0, FP, 16, 4) 2183 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2184 FIELD(ID_AA64PFR0, GIC, 24, 4) 2185 FIELD(ID_AA64PFR0, RAS, 28, 4) 2186 FIELD(ID_AA64PFR0, SVE, 32, 4) 2187 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2188 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2189 FIELD(ID_AA64PFR0, AMU, 44, 4) 2190 FIELD(ID_AA64PFR0, DIT, 48, 4) 2191 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2192 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2193 2194 FIELD(ID_AA64PFR1, BT, 0, 4) 2195 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2196 FIELD(ID_AA64PFR1, MTE, 8, 4) 2197 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2198 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2199 FIELD(ID_AA64PFR1, SME, 24, 4) 2200 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2201 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2202 FIELD(ID_AA64PFR1, NMI, 36, 4) 2203 2204 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2205 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2206 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2207 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2208 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2209 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2210 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2211 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2212 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2213 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2214 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2215 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2216 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2217 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2218 2219 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2220 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2221 FIELD(ID_AA64MMFR1, VH, 8, 4) 2222 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2223 FIELD(ID_AA64MMFR1, LO, 16, 4) 2224 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2225 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2226 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2227 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2228 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2229 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2230 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2231 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2232 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2233 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2234 2235 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2236 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2237 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2238 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2239 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2240 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2241 FIELD(ID_AA64MMFR2, NV, 24, 4) 2242 FIELD(ID_AA64MMFR2, ST, 28, 4) 2243 FIELD(ID_AA64MMFR2, AT, 32, 4) 2244 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2245 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2246 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2247 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2248 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2249 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2250 2251 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2252 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2253 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2254 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2255 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2256 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2257 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2258 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2259 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2260 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2261 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2262 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2263 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2264 2265 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2266 FIELD(ID_AA64ZFR0, AES, 4, 4) 2267 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2268 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2269 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2270 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2271 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2272 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2273 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2274 2275 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2276 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2277 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2278 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2279 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2280 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2281 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2282 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2283 2284 FIELD(ID_DFR0, COPDBG, 0, 4) 2285 FIELD(ID_DFR0, COPSDBG, 4, 4) 2286 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2287 FIELD(ID_DFR0, COPTRC, 12, 4) 2288 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2289 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2290 FIELD(ID_DFR0, PERFMON, 24, 4) 2291 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2292 2293 FIELD(ID_DFR1, MTPMU, 0, 4) 2294 FIELD(ID_DFR1, HPMN0, 4, 4) 2295 2296 FIELD(DBGDIDR, SE_IMP, 12, 1) 2297 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2298 FIELD(DBGDIDR, VERSION, 16, 4) 2299 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2300 FIELD(DBGDIDR, BRPS, 24, 4) 2301 FIELD(DBGDIDR, WRPS, 28, 4) 2302 2303 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2304 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2305 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2306 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2307 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2308 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2309 FIELD(DBGDEVID, AUXREGS, 24, 4) 2310 FIELD(DBGDEVID, CIDMASK, 28, 4) 2311 2312 FIELD(MVFR0, SIMDREG, 0, 4) 2313 FIELD(MVFR0, FPSP, 4, 4) 2314 FIELD(MVFR0, FPDP, 8, 4) 2315 FIELD(MVFR0, FPTRAP, 12, 4) 2316 FIELD(MVFR0, FPDIVIDE, 16, 4) 2317 FIELD(MVFR0, FPSQRT, 20, 4) 2318 FIELD(MVFR0, FPSHVEC, 24, 4) 2319 FIELD(MVFR0, FPROUND, 28, 4) 2320 2321 FIELD(MVFR1, FPFTZ, 0, 4) 2322 FIELD(MVFR1, FPDNAN, 4, 4) 2323 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2324 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2325 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2326 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2327 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2328 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2329 FIELD(MVFR1, FPHP, 24, 4) 2330 FIELD(MVFR1, SIMDFMAC, 28, 4) 2331 2332 FIELD(MVFR2, SIMDMISC, 0, 4) 2333 FIELD(MVFR2, FPMISC, 4, 4) 2334 2335 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2336 2337 /* If adding a feature bit which corresponds to a Linux ELF 2338 * HWCAP bit, remember to update the feature-bit-to-hwcap 2339 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2340 */ 2341 enum arm_features { 2342 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2343 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2344 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2345 ARM_FEATURE_V6, 2346 ARM_FEATURE_V6K, 2347 ARM_FEATURE_V7, 2348 ARM_FEATURE_THUMB2, 2349 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2350 ARM_FEATURE_NEON, 2351 ARM_FEATURE_M, /* Microcontroller profile. */ 2352 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2353 ARM_FEATURE_THUMB2EE, 2354 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2355 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2356 ARM_FEATURE_V4T, 2357 ARM_FEATURE_V5, 2358 ARM_FEATURE_STRONGARM, 2359 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2360 ARM_FEATURE_GENERIC_TIMER, 2361 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2362 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2363 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2364 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2365 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2366 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2367 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2368 ARM_FEATURE_V8, 2369 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2370 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2371 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2372 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2373 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2374 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2375 ARM_FEATURE_PMU, /* has PMU support */ 2376 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2377 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2378 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2379 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2380 }; 2381 2382 static inline int arm_feature(CPUARMState *env, int feature) 2383 { 2384 return (env->features & (1ULL << feature)) != 0; 2385 } 2386 2387 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2388 2389 #if !defined(CONFIG_USER_ONLY) 2390 /* Return true if exception levels below EL3 are in secure state, 2391 * or would be following an exception return to that level. 2392 * Unlike arm_is_secure() (which is always a question about the 2393 * _current_ state of the CPU) this doesn't care about the current 2394 * EL or mode. 2395 */ 2396 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2397 { 2398 if (arm_feature(env, ARM_FEATURE_EL3)) { 2399 return !(env->cp15.scr_el3 & SCR_NS); 2400 } else { 2401 /* If EL3 is not supported then the secure state is implementation 2402 * defined, in which case QEMU defaults to non-secure. 2403 */ 2404 return false; 2405 } 2406 } 2407 2408 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2409 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2410 { 2411 if (arm_feature(env, ARM_FEATURE_EL3)) { 2412 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2413 /* CPU currently in AArch64 state and EL3 */ 2414 return true; 2415 } else if (!is_a64(env) && 2416 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2417 /* CPU currently in AArch32 state and monitor mode */ 2418 return true; 2419 } 2420 } 2421 return false; 2422 } 2423 2424 /* Return true if the processor is in secure state */ 2425 static inline bool arm_is_secure(CPUARMState *env) 2426 { 2427 if (arm_is_el3_or_mon(env)) { 2428 return true; 2429 } 2430 return arm_is_secure_below_el3(env); 2431 } 2432 2433 /* 2434 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2435 * This corresponds to the pseudocode EL2Enabled() 2436 */ 2437 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2438 { 2439 return arm_feature(env, ARM_FEATURE_EL2) 2440 && (!secure || (env->cp15.scr_el3 & SCR_EEL2)); 2441 } 2442 2443 static inline bool arm_is_el2_enabled(CPUARMState *env) 2444 { 2445 return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env)); 2446 } 2447 2448 #else 2449 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2450 { 2451 return false; 2452 } 2453 2454 static inline bool arm_is_secure(CPUARMState *env) 2455 { 2456 return false; 2457 } 2458 2459 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2460 { 2461 return false; 2462 } 2463 2464 static inline bool arm_is_el2_enabled(CPUARMState *env) 2465 { 2466 return false; 2467 } 2468 #endif 2469 2470 /** 2471 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2472 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2473 * "for all purposes other than a direct read or write access of HCR_EL2." 2474 * Not included here is HCR_RW. 2475 */ 2476 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); 2477 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2478 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2479 2480 /* Return true if the specified exception level is running in AArch64 state. */ 2481 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2482 { 2483 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2484 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2485 */ 2486 assert(el >= 1 && el <= 3); 2487 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2488 2489 /* The highest exception level is always at the maximum supported 2490 * register width, and then lower levels have a register width controlled 2491 * by bits in the SCR or HCR registers. 2492 */ 2493 if (el == 3) { 2494 return aa64; 2495 } 2496 2497 if (arm_feature(env, ARM_FEATURE_EL3) && 2498 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2499 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2500 } 2501 2502 if (el == 2) { 2503 return aa64; 2504 } 2505 2506 if (arm_is_el2_enabled(env)) { 2507 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2508 } 2509 2510 return aa64; 2511 } 2512 2513 /* Function for determing whether guest cp register reads and writes should 2514 * access the secure or non-secure bank of a cp register. When EL3 is 2515 * operating in AArch32 state, the NS-bit determines whether the secure 2516 * instance of a cp register should be used. When EL3 is AArch64 (or if 2517 * it doesn't exist at all) then there is no register banking, and all 2518 * accesses are to the non-secure version. 2519 */ 2520 static inline bool access_secure_reg(CPUARMState *env) 2521 { 2522 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2523 !arm_el_is_aa64(env, 3) && 2524 !(env->cp15.scr_el3 & SCR_NS)); 2525 2526 return ret; 2527 } 2528 2529 /* Macros for accessing a specified CP register bank */ 2530 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2531 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2532 2533 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2534 do { \ 2535 if (_secure) { \ 2536 (_env)->cp15._regname##_s = (_val); \ 2537 } else { \ 2538 (_env)->cp15._regname##_ns = (_val); \ 2539 } \ 2540 } while (0) 2541 2542 /* Macros for automatically accessing a specific CP register bank depending on 2543 * the current secure state of the system. These macros are not intended for 2544 * supporting instruction translation reads/writes as these are dependent 2545 * solely on the SCR.NS bit and not the mode. 2546 */ 2547 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2548 A32_BANKED_REG_GET((_env), _regname, \ 2549 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2550 2551 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2552 A32_BANKED_REG_SET((_env), _regname, \ 2553 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2554 (_val)) 2555 2556 void arm_cpu_list(void); 2557 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2558 uint32_t cur_el, bool secure); 2559 2560 /* Interface between CPU and Interrupt controller. */ 2561 #ifndef CONFIG_USER_ONLY 2562 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2563 #else 2564 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2565 { 2566 return true; 2567 } 2568 #endif 2569 /** 2570 * armv7m_nvic_set_pending: mark the specified exception as pending 2571 * @opaque: the NVIC 2572 * @irq: the exception number to mark pending 2573 * @secure: false for non-banked exceptions or for the nonsecure 2574 * version of a banked exception, true for the secure version of a banked 2575 * exception. 2576 * 2577 * Marks the specified exception as pending. Note that we will assert() 2578 * if @secure is true and @irq does not specify one of the fixed set 2579 * of architecturally banked exceptions. 2580 */ 2581 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2582 /** 2583 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2584 * @opaque: the NVIC 2585 * @irq: the exception number to mark pending 2586 * @secure: false for non-banked exceptions or for the nonsecure 2587 * version of a banked exception, true for the secure version of a banked 2588 * exception. 2589 * 2590 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2591 * exceptions (exceptions generated in the course of trying to take 2592 * a different exception). 2593 */ 2594 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2595 /** 2596 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2597 * @opaque: the NVIC 2598 * @irq: the exception number to mark pending 2599 * @secure: false for non-banked exceptions or for the nonsecure 2600 * version of a banked exception, true for the secure version of a banked 2601 * exception. 2602 * 2603 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2604 * generated in the course of lazy stacking of FP registers. 2605 */ 2606 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2607 /** 2608 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2609 * exception, and whether it targets Secure state 2610 * @opaque: the NVIC 2611 * @pirq: set to pending exception number 2612 * @ptargets_secure: set to whether pending exception targets Secure 2613 * 2614 * This function writes the number of the highest priority pending 2615 * exception (the one which would be made active by 2616 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2617 * to true if the current highest priority pending exception should 2618 * be taken to Secure state, false for NS. 2619 */ 2620 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2621 bool *ptargets_secure); 2622 /** 2623 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2624 * @opaque: the NVIC 2625 * 2626 * Move the current highest priority pending exception from the pending 2627 * state to the active state, and update v7m.exception to indicate that 2628 * it is the exception currently being handled. 2629 */ 2630 void armv7m_nvic_acknowledge_irq(void *opaque); 2631 /** 2632 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2633 * @opaque: the NVIC 2634 * @irq: the exception number to complete 2635 * @secure: true if this exception was secure 2636 * 2637 * Returns: -1 if the irq was not active 2638 * 1 if completing this irq brought us back to base (no active irqs) 2639 * 0 if there is still an irq active after this one was completed 2640 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2641 */ 2642 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2643 /** 2644 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2645 * @opaque: the NVIC 2646 * @irq: the exception number to mark pending 2647 * @secure: false for non-banked exceptions or for the nonsecure 2648 * version of a banked exception, true for the secure version of a banked 2649 * exception. 2650 * 2651 * Return whether an exception is "ready", i.e. whether the exception is 2652 * enabled and is configured at a priority which would allow it to 2653 * interrupt the current execution priority. This controls whether the 2654 * RDY bit for it in the FPCCR is set. 2655 */ 2656 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2657 /** 2658 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2659 * @opaque: the NVIC 2660 * 2661 * Returns: the raw execution priority as defined by the v8M architecture. 2662 * This is the execution priority minus the effects of AIRCR.PRIS, 2663 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2664 * (v8M ARM ARM I_PKLD.) 2665 */ 2666 int armv7m_nvic_raw_execution_priority(void *opaque); 2667 /** 2668 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2669 * priority is negative for the specified security state. 2670 * @opaque: the NVIC 2671 * @secure: the security state to test 2672 * This corresponds to the pseudocode IsReqExecPriNeg(). 2673 */ 2674 #ifndef CONFIG_USER_ONLY 2675 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2676 #else 2677 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2678 { 2679 return false; 2680 } 2681 #endif 2682 2683 /* Interface for defining coprocessor registers. 2684 * Registers are defined in tables of arm_cp_reginfo structs 2685 * which are passed to define_arm_cp_regs(). 2686 */ 2687 2688 /* When looking up a coprocessor register we look for it 2689 * via an integer which encodes all of: 2690 * coprocessor number 2691 * Crn, Crm, opc1, opc2 fields 2692 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2693 * or via MRRC/MCRR?) 2694 * non-secure/secure bank (AArch32 only) 2695 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2696 * (In this case crn and opc2 should be zero.) 2697 * For AArch64, there is no 32/64 bit size distinction; 2698 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2699 * and 4 bit CRn and CRm. The encoding patterns are chosen 2700 * to be easy to convert to and from the KVM encodings, and also 2701 * so that the hashtable can contain both AArch32 and AArch64 2702 * registers (to allow for interprocessing where we might run 2703 * 32 bit code on a 64 bit core). 2704 */ 2705 /* This bit is private to our hashtable cpreg; in KVM register 2706 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2707 * in the upper bits of the 64 bit ID. 2708 */ 2709 #define CP_REG_AA64_SHIFT 28 2710 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2711 2712 /* To enable banking of coprocessor registers depending on ns-bit we 2713 * add a bit to distinguish between secure and non-secure cpregs in the 2714 * hashtable. 2715 */ 2716 #define CP_REG_NS_SHIFT 29 2717 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2718 2719 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2720 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2721 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2722 2723 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2724 (CP_REG_AA64_MASK | \ 2725 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2726 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2727 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2728 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2729 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2730 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2731 2732 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2733 * version used as a key for the coprocessor register hashtable 2734 */ 2735 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2736 { 2737 uint32_t cpregid = kvmid; 2738 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2739 cpregid |= CP_REG_AA64_MASK; 2740 } else { 2741 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2742 cpregid |= (1 << 15); 2743 } 2744 2745 /* KVM is always non-secure so add the NS flag on AArch32 register 2746 * entries. 2747 */ 2748 cpregid |= 1 << CP_REG_NS_SHIFT; 2749 } 2750 return cpregid; 2751 } 2752 2753 /* Convert a truncated 32 bit hashtable key into the full 2754 * 64 bit KVM register ID. 2755 */ 2756 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2757 { 2758 uint64_t kvmid; 2759 2760 if (cpregid & CP_REG_AA64_MASK) { 2761 kvmid = cpregid & ~CP_REG_AA64_MASK; 2762 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2763 } else { 2764 kvmid = cpregid & ~(1 << 15); 2765 if (cpregid & (1 << 15)) { 2766 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2767 } else { 2768 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2769 } 2770 } 2771 return kvmid; 2772 } 2773 2774 /* Return the highest implemented Exception Level */ 2775 static inline int arm_highest_el(CPUARMState *env) 2776 { 2777 if (arm_feature(env, ARM_FEATURE_EL3)) { 2778 return 3; 2779 } 2780 if (arm_feature(env, ARM_FEATURE_EL2)) { 2781 return 2; 2782 } 2783 return 1; 2784 } 2785 2786 /* Return true if a v7M CPU is in Handler mode */ 2787 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2788 { 2789 return env->v7m.exception != 0; 2790 } 2791 2792 /* Return the current Exception Level (as per ARMv8; note that this differs 2793 * from the ARMv7 Privilege Level). 2794 */ 2795 static inline int arm_current_el(CPUARMState *env) 2796 { 2797 if (arm_feature(env, ARM_FEATURE_M)) { 2798 return arm_v7m_is_handler_mode(env) || 2799 !(env->v7m.control[env->v7m.secure] & 1); 2800 } 2801 2802 if (is_a64(env)) { 2803 return extract32(env->pstate, 2, 2); 2804 } 2805 2806 switch (env->uncached_cpsr & 0x1f) { 2807 case ARM_CPU_MODE_USR: 2808 return 0; 2809 case ARM_CPU_MODE_HYP: 2810 return 2; 2811 case ARM_CPU_MODE_MON: 2812 return 3; 2813 default: 2814 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2815 /* If EL3 is 32-bit then all secure privileged modes run in 2816 * EL3 2817 */ 2818 return 3; 2819 } 2820 2821 return 1; 2822 } 2823 } 2824 2825 /** 2826 * write_list_to_cpustate 2827 * @cpu: ARMCPU 2828 * 2829 * For each register listed in the ARMCPU cpreg_indexes list, write 2830 * its value from the cpreg_values list into the ARMCPUState structure. 2831 * This updates TCG's working data structures from KVM data or 2832 * from incoming migration state. 2833 * 2834 * Returns: true if all register values were updated correctly, 2835 * false if some register was unknown or could not be written. 2836 * Note that we do not stop early on failure -- we will attempt 2837 * writing all registers in the list. 2838 */ 2839 bool write_list_to_cpustate(ARMCPU *cpu); 2840 2841 /** 2842 * write_cpustate_to_list: 2843 * @cpu: ARMCPU 2844 * @kvm_sync: true if this is for syncing back to KVM 2845 * 2846 * For each register listed in the ARMCPU cpreg_indexes list, write 2847 * its value from the ARMCPUState structure into the cpreg_values list. 2848 * This is used to copy info from TCG's working data structures into 2849 * KVM or for outbound migration. 2850 * 2851 * @kvm_sync is true if we are doing this in order to sync the 2852 * register state back to KVM. In this case we will only update 2853 * values in the list if the previous list->cpustate sync actually 2854 * successfully wrote the CPU state. Otherwise we will keep the value 2855 * that is in the list. 2856 * 2857 * Returns: true if all register values were read correctly, 2858 * false if some register was unknown or could not be read. 2859 * Note that we do not stop early on failure -- we will attempt 2860 * reading all registers in the list. 2861 */ 2862 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2863 2864 #define ARM_CPUID_TI915T 0x54029152 2865 #define ARM_CPUID_TI925T 0x54029252 2866 2867 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2868 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2869 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2870 2871 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2872 2873 #define cpu_list arm_cpu_list 2874 2875 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2876 * 2877 * If EL3 is 64-bit: 2878 * + NonSecure EL1 & 0 stage 1 2879 * + NonSecure EL1 & 0 stage 2 2880 * + NonSecure EL2 2881 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2882 * + Secure EL1 & 0 2883 * + Secure EL3 2884 * If EL3 is 32-bit: 2885 * + NonSecure PL1 & 0 stage 1 2886 * + NonSecure PL1 & 0 stage 2 2887 * + NonSecure PL2 2888 * + Secure PL0 2889 * + Secure PL1 2890 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2891 * 2892 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2893 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2894 * because they may differ in access permissions even if the VA->PA map is 2895 * the same 2896 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2897 * translation, which means that we have one mmu_idx that deals with two 2898 * concatenated translation regimes [this sort of combined s1+2 TLB is 2899 * architecturally permitted] 2900 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2901 * handling via the TLB. The only way to do a stage 1 translation without 2902 * the immediate stage 2 translation is via the ATS or AT system insns, 2903 * which can be slow-pathed and always do a page table walk. 2904 * The only use of stage 2 translations is either as part of an s1+2 2905 * lookup or when loading the descriptors during a stage 1 page table walk, 2906 * and in both those cases we don't use the TLB. 2907 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2908 * translation regimes, because they map reasonably well to each other 2909 * and they can't both be active at the same time. 2910 * 5. we want to be able to use the TLB for accesses done as part of a 2911 * stage1 page table walk, rather than having to walk the stage2 page 2912 * table over and over. 2913 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2914 * Never (PAN) bit within PSTATE. 2915 * 7. we fold together the secure and non-secure regimes for A-profile, 2916 * because there are no banked system registers for aarch64, so the 2917 * process of switching between secure and non-secure is 2918 * already heavyweight. 2919 * 2920 * This gives us the following list of cases: 2921 * 2922 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2923 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2924 * EL1 EL1&0 stage 1+2 +PAN 2925 * EL0 EL2&0 2926 * EL2 EL2&0 2927 * EL2 EL2&0 +PAN 2928 * EL2 (aka NS PL2) 2929 * EL3 (aka S PL1) 2930 * Physical (NS & S) 2931 * Stage2 (NS & S) 2932 * 2933 * for a total of 12 different mmu_idx. 2934 * 2935 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2936 * as A profile. They only need to distinguish EL0 and EL1 (and 2937 * EL2 if we ever model a Cortex-R52). 2938 * 2939 * M profile CPUs are rather different as they do not have a true MMU. 2940 * They have the following different MMU indexes: 2941 * User 2942 * Privileged 2943 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2944 * Privileged, execution priority negative (ditto) 2945 * If the CPU supports the v8M Security Extension then there are also: 2946 * Secure User 2947 * Secure Privileged 2948 * Secure User, execution priority negative 2949 * Secure Privileged, execution priority negative 2950 * 2951 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2952 * are not quite the same -- different CPU types (most notably M profile 2953 * vs A/R profile) would like to use MMU indexes with different semantics, 2954 * but since we don't ever need to use all of those in a single CPU we 2955 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2956 * modes + total number of M profile MMU modes". The lower bits of 2957 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2958 * the same for any particular CPU. 2959 * Variables of type ARMMUIdx are always full values, and the core 2960 * index values are in variables of type 'int'. 2961 * 2962 * Our enumeration includes at the end some entries which are not "true" 2963 * mmu_idx values in that they don't have corresponding TLBs and are only 2964 * valid for doing slow path page table walks. 2965 * 2966 * The constant names here are patterned after the general style of the names 2967 * of the AT/ATS operations. 2968 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2969 * For M profile we arrange them to have a bit for priv, a bit for negpri 2970 * and a bit for secure. 2971 */ 2972 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2973 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2974 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2975 2976 /* Meanings of the bits for M profile mmu idx values */ 2977 #define ARM_MMU_IDX_M_PRIV 0x1 2978 #define ARM_MMU_IDX_M_NEGPRI 0x2 2979 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2980 2981 #define ARM_MMU_IDX_TYPE_MASK \ 2982 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2983 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2984 2985 typedef enum ARMMMUIdx { 2986 /* 2987 * A-profile. 2988 */ 2989 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2990 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2991 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2992 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2993 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2994 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2995 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2996 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2997 2998 /* TLBs with 1-1 mapping to the physical address spaces. */ 2999 ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A, 3000 ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A, 3001 3002 /* 3003 * Used for second stage of an S12 page table walk, or for descriptor 3004 * loads during first stage of an S1 page table walk. Note that both 3005 * are in use simultaneously for SecureEL2: the security state for 3006 * the S2 ptw is selected by the NS bit from the S1 ptw. 3007 */ 3008 ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A, 3009 ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A, 3010 3011 /* 3012 * These are not allocated TLBs and are used only for AT system 3013 * instructions or for the first stage of an S12 page table walk. 3014 */ 3015 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 3016 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 3017 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 3018 3019 /* 3020 * M-profile. 3021 */ 3022 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 3023 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 3024 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 3025 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 3026 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 3027 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 3028 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 3029 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 3030 } ARMMMUIdx; 3031 3032 /* 3033 * Bit macros for the core-mmu-index values for each index, 3034 * for use when calling tlb_flush_by_mmuidx() and friends. 3035 */ 3036 #define TO_CORE_BIT(NAME) \ 3037 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 3038 3039 typedef enum ARMMMUIdxBit { 3040 TO_CORE_BIT(E10_0), 3041 TO_CORE_BIT(E20_0), 3042 TO_CORE_BIT(E10_1), 3043 TO_CORE_BIT(E10_1_PAN), 3044 TO_CORE_BIT(E2), 3045 TO_CORE_BIT(E20_2), 3046 TO_CORE_BIT(E20_2_PAN), 3047 TO_CORE_BIT(E3), 3048 TO_CORE_BIT(Stage2), 3049 TO_CORE_BIT(Stage2_S), 3050 3051 TO_CORE_BIT(MUser), 3052 TO_CORE_BIT(MPriv), 3053 TO_CORE_BIT(MUserNegPri), 3054 TO_CORE_BIT(MPrivNegPri), 3055 TO_CORE_BIT(MSUser), 3056 TO_CORE_BIT(MSPriv), 3057 TO_CORE_BIT(MSUserNegPri), 3058 TO_CORE_BIT(MSPrivNegPri), 3059 } ARMMMUIdxBit; 3060 3061 #undef TO_CORE_BIT 3062 3063 #define MMU_USER_IDX 0 3064 3065 /* Indexes used when registering address spaces with cpu_address_space_init */ 3066 typedef enum ARMASIdx { 3067 ARMASIdx_NS = 0, 3068 ARMASIdx_S = 1, 3069 ARMASIdx_TagNS = 2, 3070 ARMASIdx_TagS = 3, 3071 } ARMASIdx; 3072 3073 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3074 { 3075 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3076 * CSSELR is RAZ/WI. 3077 */ 3078 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3079 } 3080 3081 static inline bool arm_sctlr_b(CPUARMState *env) 3082 { 3083 return 3084 /* We need not implement SCTLR.ITD in user-mode emulation, so 3085 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3086 * This lets people run BE32 binaries with "-cpu any". 3087 */ 3088 #ifndef CONFIG_USER_ONLY 3089 !arm_feature(env, ARM_FEATURE_V7) && 3090 #endif 3091 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3092 } 3093 3094 uint64_t arm_sctlr(CPUARMState *env, int el); 3095 3096 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3097 bool sctlr_b) 3098 { 3099 #ifdef CONFIG_USER_ONLY 3100 /* 3101 * In system mode, BE32 is modelled in line with the 3102 * architecture (as word-invariant big-endianness), where loads 3103 * and stores are done little endian but from addresses which 3104 * are adjusted by XORing with the appropriate constant. So the 3105 * endianness to use for the raw data access is not affected by 3106 * SCTLR.B. 3107 * In user mode, however, we model BE32 as byte-invariant 3108 * big-endianness (because user-only code cannot tell the 3109 * difference), and so we need to use a data access endianness 3110 * that depends on SCTLR.B. 3111 */ 3112 if (sctlr_b) { 3113 return true; 3114 } 3115 #endif 3116 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3117 return env->uncached_cpsr & CPSR_E; 3118 } 3119 3120 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3121 { 3122 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3123 } 3124 3125 /* Return true if the processor is in big-endian mode. */ 3126 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3127 { 3128 if (!is_a64(env)) { 3129 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3130 } else { 3131 int cur_el = arm_current_el(env); 3132 uint64_t sctlr = arm_sctlr(env, cur_el); 3133 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3134 } 3135 } 3136 3137 #include "exec/cpu-all.h" 3138 3139 /* 3140 * We have more than 32-bits worth of state per TB, so we split the data 3141 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3142 * We collect these two parts in CPUARMTBFlags where they are named 3143 * flags and flags2 respectively. 3144 * 3145 * The flags that are shared between all execution modes, TBFLAG_ANY, 3146 * are stored in flags. The flags that are specific to a given mode 3147 * are stores in flags2. Since cs_base is sized on the configured 3148 * address size, flags2 always has 64-bits for A64, and a minimum of 3149 * 32-bits for A32 and M32. 3150 * 3151 * The bits for 32-bit A-profile and M-profile partially overlap: 3152 * 3153 * 31 23 11 10 0 3154 * +-------------+----------+----------------+ 3155 * | | | TBFLAG_A32 | 3156 * | TBFLAG_AM32 | +-----+----------+ 3157 * | | |TBFLAG_M32| 3158 * +-------------+----------------+----------+ 3159 * 31 23 6 5 0 3160 * 3161 * Unless otherwise noted, these bits are cached in env->hflags. 3162 */ 3163 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3164 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3165 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3166 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3167 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3168 /* Target EL if we take a floating-point-disabled exception */ 3169 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3170 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3171 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3172 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3173 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3174 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3175 3176 /* 3177 * Bit usage when in AArch32 state, both A- and M-profile. 3178 */ 3179 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3180 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3181 3182 /* 3183 * Bit usage when in AArch32 state, for A-profile only. 3184 */ 3185 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3186 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3187 /* 3188 * We store the bottom two bits of the CPAR as TB flags and handle 3189 * checks on the other bits at runtime. This shares the same bits as 3190 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3191 * Not cached, because VECLEN+VECSTRIDE are not cached. 3192 */ 3193 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3194 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3195 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3196 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3197 /* 3198 * Indicates whether cp register reads and writes by guest code should access 3199 * the secure or nonsecure bank of banked registers; note that this is not 3200 * the same thing as the current security state of the processor! 3201 */ 3202 FIELD(TBFLAG_A32, NS, 10, 1) 3203 /* 3204 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3205 * This requires an SME trap from AArch32 mode when using NEON. 3206 */ 3207 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3208 3209 /* 3210 * Bit usage when in AArch32 state, for M-profile only. 3211 */ 3212 /* Handler (ie not Thread) mode */ 3213 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3214 /* Whether we should generate stack-limit checks */ 3215 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3216 /* Set if FPCCR.LSPACT is set */ 3217 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3218 /* Set if we must create a new FP context */ 3219 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3220 /* Set if FPCCR.S does not match current security state */ 3221 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3222 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3223 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3224 /* Set if in secure mode */ 3225 FIELD(TBFLAG_M32, SECURE, 6, 1) 3226 3227 /* 3228 * Bit usage when in AArch64 state 3229 */ 3230 FIELD(TBFLAG_A64, TBII, 0, 2) 3231 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3232 /* The current vector length, either NVL or SVL. */ 3233 FIELD(TBFLAG_A64, VL, 4, 4) 3234 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3235 FIELD(TBFLAG_A64, BT, 9, 1) 3236 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3237 FIELD(TBFLAG_A64, TBID, 12, 2) 3238 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3239 FIELD(TBFLAG_A64, ATA, 15, 1) 3240 FIELD(TBFLAG_A64, TCMA, 16, 2) 3241 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3242 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3243 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3244 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3245 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3246 FIELD(TBFLAG_A64, SVL, 24, 4) 3247 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3248 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3249 FIELD(TBFLAG_A64, FGT_ERET, 29, 1) 3250 3251 /* 3252 * Helpers for using the above. 3253 */ 3254 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3255 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3256 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3257 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3258 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3259 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3260 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3261 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3262 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3263 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3264 3265 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3266 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3267 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3268 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3269 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3270 3271 /** 3272 * cpu_mmu_index: 3273 * @env: The cpu environment 3274 * @ifetch: True for code access, false for data access. 3275 * 3276 * Return the core mmu index for the current translation regime. 3277 * This function is used by generic TCG code paths. 3278 */ 3279 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3280 { 3281 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3282 } 3283 3284 /** 3285 * sve_vq 3286 * @env: the cpu context 3287 * 3288 * Return the VL cached within env->hflags, in units of quadwords. 3289 */ 3290 static inline int sve_vq(CPUARMState *env) 3291 { 3292 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3293 } 3294 3295 /** 3296 * sme_vq 3297 * @env: the cpu context 3298 * 3299 * Return the SVL cached within env->hflags, in units of quadwords. 3300 */ 3301 static inline int sme_vq(CPUARMState *env) 3302 { 3303 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3304 } 3305 3306 static inline bool bswap_code(bool sctlr_b) 3307 { 3308 #ifdef CONFIG_USER_ONLY 3309 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3310 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3311 * would also end up as a mixed-endian mode with BE code, LE data. 3312 */ 3313 return 3314 #if TARGET_BIG_ENDIAN 3315 1 ^ 3316 #endif 3317 sctlr_b; 3318 #else 3319 /* All code access in ARM is little endian, and there are no loaders 3320 * doing swaps that need to be reversed 3321 */ 3322 return 0; 3323 #endif 3324 } 3325 3326 #ifdef CONFIG_USER_ONLY 3327 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3328 { 3329 return 3330 #if TARGET_BIG_ENDIAN 3331 1 ^ 3332 #endif 3333 arm_cpu_data_is_big_endian(env); 3334 } 3335 #endif 3336 3337 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3338 target_ulong *cs_base, uint32_t *flags); 3339 3340 enum { 3341 QEMU_PSCI_CONDUIT_DISABLED = 0, 3342 QEMU_PSCI_CONDUIT_SMC = 1, 3343 QEMU_PSCI_CONDUIT_HVC = 2, 3344 }; 3345 3346 #ifndef CONFIG_USER_ONLY 3347 /* Return the address space index to use for a memory access */ 3348 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3349 { 3350 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3351 } 3352 3353 /* Return the AddressSpace to use for a memory access 3354 * (which depends on whether the access is S or NS, and whether 3355 * the board gave us a separate AddressSpace for S accesses). 3356 */ 3357 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3358 { 3359 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3360 } 3361 #endif 3362 3363 /** 3364 * arm_register_pre_el_change_hook: 3365 * Register a hook function which will be called immediately before this 3366 * CPU changes exception level or mode. The hook function will be 3367 * passed a pointer to the ARMCPU and the opaque data pointer passed 3368 * to this function when the hook was registered. 3369 * 3370 * Note that if a pre-change hook is called, any registered post-change hooks 3371 * are guaranteed to subsequently be called. 3372 */ 3373 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3374 void *opaque); 3375 /** 3376 * arm_register_el_change_hook: 3377 * Register a hook function which will be called immediately after this 3378 * CPU changes exception level or mode. The hook function will be 3379 * passed a pointer to the ARMCPU and the opaque data pointer passed 3380 * to this function when the hook was registered. 3381 * 3382 * Note that any registered hooks registered here are guaranteed to be called 3383 * if pre-change hooks have been. 3384 */ 3385 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3386 *opaque); 3387 3388 /** 3389 * arm_rebuild_hflags: 3390 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3391 */ 3392 void arm_rebuild_hflags(CPUARMState *env); 3393 3394 /** 3395 * aa32_vfp_dreg: 3396 * Return a pointer to the Dn register within env in 32-bit mode. 3397 */ 3398 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3399 { 3400 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3401 } 3402 3403 /** 3404 * aa32_vfp_qreg: 3405 * Return a pointer to the Qn register within env in 32-bit mode. 3406 */ 3407 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3408 { 3409 return &env->vfp.zregs[regno].d[0]; 3410 } 3411 3412 /** 3413 * aa64_vfp_qreg: 3414 * Return a pointer to the Qn register within env in 64-bit mode. 3415 */ 3416 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3417 { 3418 return &env->vfp.zregs[regno].d[0]; 3419 } 3420 3421 /* Shared between translate-sve.c and sve_helper.c. */ 3422 extern const uint64_t pred_esz_masks[5]; 3423 3424 /* 3425 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3426 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3427 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3428 */ 3429 #define PAGE_BTI PAGE_TARGET_1 3430 #define PAGE_MTE PAGE_TARGET_2 3431 #define PAGE_TARGET_STICKY PAGE_MTE 3432 3433 /* We associate one allocation tag per 16 bytes, the minimum. */ 3434 #define LOG2_TAG_GRANULE 4 3435 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3436 3437 #ifdef CONFIG_USER_ONLY 3438 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3439 #endif 3440 3441 #ifdef TARGET_TAGGED_ADDRESSES 3442 /** 3443 * cpu_untagged_addr: 3444 * @cs: CPU context 3445 * @x: tagged address 3446 * 3447 * Remove any address tag from @x. This is explicitly related to the 3448 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3449 * 3450 * There should be a better place to put this, but we need this in 3451 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3452 */ 3453 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3454 { 3455 ARMCPU *cpu = ARM_CPU(cs); 3456 if (cpu->env.tagged_addr_enable) { 3457 /* 3458 * TBI is enabled for userspace but not kernelspace addresses. 3459 * Only clear the tag if bit 55 is clear. 3460 */ 3461 x &= sextract64(x, 0, 56); 3462 } 3463 return x; 3464 } 3465 #endif 3466 3467 /* 3468 * Naming convention for isar_feature functions: 3469 * Functions which test 32-bit ID registers should have _aa32_ in 3470 * their name. Functions which test 64-bit ID registers should have 3471 * _aa64_ in their name. These must only be used in code where we 3472 * know for certain that the CPU has AArch32 or AArch64 respectively 3473 * or where the correct answer for a CPU which doesn't implement that 3474 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3475 * system registers that are specific to that CPU state, for "should 3476 * we let this system register bit be set" tests where the 32-bit 3477 * flavour of the register doesn't have the bit, and so on). 3478 * Functions which simply ask "does this feature exist at all" have 3479 * _any_ in their name, and always return the logical OR of the _aa64_ 3480 * and the _aa32_ function. 3481 */ 3482 3483 /* 3484 * 32-bit feature tests via id registers. 3485 */ 3486 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3487 { 3488 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3489 } 3490 3491 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3492 { 3493 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3494 } 3495 3496 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3497 { 3498 /* (M-profile) low-overhead loops and branch future */ 3499 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3500 } 3501 3502 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3503 { 3504 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3505 } 3506 3507 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3508 { 3509 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3510 } 3511 3512 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3513 { 3514 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3515 } 3516 3517 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3518 { 3519 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3520 } 3521 3522 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3523 { 3524 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3525 } 3526 3527 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3528 { 3529 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3530 } 3531 3532 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3533 { 3534 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3535 } 3536 3537 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3538 { 3539 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3540 } 3541 3542 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3543 { 3544 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3545 } 3546 3547 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3548 { 3549 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3550 } 3551 3552 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3553 { 3554 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3555 } 3556 3557 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3558 { 3559 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3560 } 3561 3562 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3563 { 3564 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3565 } 3566 3567 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3568 { 3569 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3570 } 3571 3572 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3573 { 3574 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3575 } 3576 3577 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3578 { 3579 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3580 } 3581 3582 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3583 { 3584 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3585 } 3586 3587 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3588 { 3589 /* 3590 * Return true if M-profile state handling insns 3591 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3592 */ 3593 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3594 } 3595 3596 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3597 { 3598 /* Sadly this is encoded differently for A-profile and M-profile */ 3599 if (isar_feature_aa32_mprofile(id)) { 3600 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3601 } else { 3602 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3603 } 3604 } 3605 3606 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3607 { 3608 /* 3609 * Return true if MVE is supported (either integer or floating point). 3610 * We must check for M-profile as the MVFR1 field means something 3611 * else for A-profile. 3612 */ 3613 return isar_feature_aa32_mprofile(id) && 3614 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3615 } 3616 3617 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3618 { 3619 /* 3620 * Return true if MVE is supported (either integer or floating point). 3621 * We must check for M-profile as the MVFR1 field means something 3622 * else for A-profile. 3623 */ 3624 return isar_feature_aa32_mprofile(id) && 3625 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3626 } 3627 3628 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3629 { 3630 /* 3631 * Return true if either VFP or SIMD is implemented. 3632 * In this case, a minimum of VFP w/ D0-D15. 3633 */ 3634 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3635 } 3636 3637 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3638 { 3639 /* Return true if D16-D31 are implemented */ 3640 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3641 } 3642 3643 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3644 { 3645 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3646 } 3647 3648 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3649 { 3650 /* Return true if CPU supports single precision floating point, VFPv2 */ 3651 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3652 } 3653 3654 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3655 { 3656 /* Return true if CPU supports single precision floating point, VFPv3 */ 3657 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3658 } 3659 3660 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3661 { 3662 /* Return true if CPU supports double precision floating point, VFPv2 */ 3663 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3664 } 3665 3666 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3667 { 3668 /* Return true if CPU supports double precision floating point, VFPv3 */ 3669 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3670 } 3671 3672 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3673 { 3674 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3675 } 3676 3677 /* 3678 * We always set the FP and SIMD FP16 fields to indicate identical 3679 * levels of support (assuming SIMD is implemented at all), so 3680 * we only need one set of accessors. 3681 */ 3682 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3683 { 3684 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3685 } 3686 3687 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3688 { 3689 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3690 } 3691 3692 /* 3693 * Note that this ID register field covers both VFP and Neon FMAC, 3694 * so should usually be tested in combination with some other 3695 * check that confirms the presence of whichever of VFP or Neon is 3696 * relevant, to avoid accidentally enabling a Neon feature on 3697 * a VFP-no-Neon core or vice-versa. 3698 */ 3699 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3700 { 3701 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3702 } 3703 3704 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3705 { 3706 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3707 } 3708 3709 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3710 { 3711 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3712 } 3713 3714 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3715 { 3716 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3717 } 3718 3719 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3720 { 3721 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3722 } 3723 3724 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3725 { 3726 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3727 } 3728 3729 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3730 { 3731 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3732 } 3733 3734 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3735 { 3736 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3737 } 3738 3739 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) 3740 { 3741 /* 0xf means "non-standard IMPDEF PMU" */ 3742 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3743 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3744 } 3745 3746 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) 3747 { 3748 /* 0xf means "non-standard IMPDEF PMU" */ 3749 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3750 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3751 } 3752 3753 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) 3754 { 3755 /* 0xf means "non-standard IMPDEF PMU" */ 3756 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 && 3757 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3758 } 3759 3760 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3761 { 3762 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3763 } 3764 3765 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3766 { 3767 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3768 } 3769 3770 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3771 { 3772 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3773 } 3774 3775 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3776 { 3777 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3778 } 3779 3780 static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) 3781 { 3782 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1; 3783 } 3784 3785 static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) 3786 { 3787 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2; 3788 } 3789 3790 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3791 { 3792 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3793 } 3794 3795 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3796 { 3797 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3798 } 3799 3800 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) 3801 { 3802 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5; 3803 } 3804 3805 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3806 { 3807 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3808 } 3809 3810 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) 3811 { 3812 return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0; 3813 } 3814 3815 /* 3816 * 64-bit feature tests via id registers. 3817 */ 3818 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3819 { 3820 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3821 } 3822 3823 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3824 { 3825 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3826 } 3827 3828 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3829 { 3830 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3831 } 3832 3833 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3834 { 3835 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3836 } 3837 3838 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3839 { 3840 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3841 } 3842 3843 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3844 { 3845 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3846 } 3847 3848 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3849 { 3850 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3851 } 3852 3853 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3854 { 3855 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3856 } 3857 3858 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3859 { 3860 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3861 } 3862 3863 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3864 { 3865 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3866 } 3867 3868 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3869 { 3870 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3871 } 3872 3873 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3874 { 3875 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3876 } 3877 3878 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3879 { 3880 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3881 } 3882 3883 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3884 { 3885 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3886 } 3887 3888 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3889 { 3890 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3891 } 3892 3893 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3894 { 3895 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3896 } 3897 3898 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3899 { 3900 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3901 } 3902 3903 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3904 { 3905 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3906 } 3907 3908 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3909 { 3910 /* 3911 * Return true if any form of pauth is enabled, as this 3912 * predicate controls migration of the 128-bit keys. 3913 */ 3914 return (id->id_aa64isar1 & 3915 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3916 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3917 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3918 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3919 } 3920 3921 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3922 { 3923 /* 3924 * Return true if pauth is enabled with the architected QARMA algorithm. 3925 * QEMU will always set APA+GPA to the same value. 3926 */ 3927 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3928 } 3929 3930 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3931 { 3932 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3933 } 3934 3935 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3936 { 3937 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3938 } 3939 3940 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3941 { 3942 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3943 } 3944 3945 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3946 { 3947 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3948 } 3949 3950 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3951 { 3952 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3953 } 3954 3955 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3956 { 3957 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3958 } 3959 3960 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3961 { 3962 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3963 } 3964 3965 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3966 { 3967 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3968 } 3969 3970 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3971 { 3972 /* We always set the AdvSIMD and FP fields identically. */ 3973 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3974 } 3975 3976 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3977 { 3978 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3979 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3980 } 3981 3982 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3983 { 3984 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3985 } 3986 3987 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3988 { 3989 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3990 } 3991 3992 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) 3993 { 3994 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; 3995 } 3996 3997 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3998 { 3999 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 4000 } 4001 4002 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) 4003 { 4004 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2; 4005 } 4006 4007 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 4008 { 4009 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 4010 } 4011 4012 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 4013 { 4014 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 4015 } 4016 4017 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 4018 { 4019 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 4020 } 4021 4022 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 4023 { 4024 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 4025 } 4026 4027 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 4028 { 4029 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 4030 } 4031 4032 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 4033 { 4034 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 4035 } 4036 4037 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) 4038 { 4039 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; 4040 } 4041 4042 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 4043 { 4044 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 4045 } 4046 4047 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 4048 { 4049 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 4050 } 4051 4052 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) 4053 { 4054 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; 4055 } 4056 4057 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) 4058 { 4059 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; 4060 } 4061 4062 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) 4063 { 4064 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1; 4065 } 4066 4067 static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) 4068 { 4069 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2; 4070 } 4071 4072 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 4073 { 4074 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 4075 } 4076 4077 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 4078 { 4079 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 4080 } 4081 4082 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 4083 { 4084 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 4085 } 4086 4087 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) 4088 { 4089 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; 4090 } 4091 4092 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) 4093 { 4094 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 4095 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4096 } 4097 4098 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) 4099 { 4100 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 4101 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4102 } 4103 4104 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) 4105 { 4106 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 && 4107 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4108 } 4109 4110 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 4111 { 4112 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 4113 } 4114 4115 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 4116 { 4117 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 4118 } 4119 4120 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 4121 { 4122 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 4123 } 4124 4125 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 4126 { 4127 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 4128 } 4129 4130 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 4131 { 4132 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4133 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 4134 } 4135 4136 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 4137 { 4138 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 4139 } 4140 4141 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 4142 { 4143 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4144 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 4145 } 4146 4147 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) 4148 { 4149 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0; 4150 } 4151 4152 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) 4153 { 4154 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1; 4155 } 4156 4157 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) 4158 { 4159 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0; 4160 } 4161 4162 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) 4163 { 4164 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4165 return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id)); 4166 } 4167 4168 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) 4169 { 4170 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4171 return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id)); 4172 } 4173 4174 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) 4175 { 4176 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); 4177 return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); 4178 } 4179 4180 static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) 4181 { 4182 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0; 4183 } 4184 4185 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4186 { 4187 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4188 } 4189 4190 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4191 { 4192 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4193 } 4194 4195 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) 4196 { 4197 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; 4198 } 4199 4200 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) 4201 { 4202 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0; 4203 } 4204 4205 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) 4206 { 4207 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2; 4208 } 4209 4210 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4211 { 4212 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4213 } 4214 4215 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4216 { 4217 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4218 } 4219 4220 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 4221 { 4222 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); 4223 if (key >= 2) { 4224 return true; /* FEAT_CSV2_2 */ 4225 } 4226 if (key == 1) { 4227 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); 4228 return key >= 2; /* FEAT_CSV2_1p2 */ 4229 } 4230 return false; 4231 } 4232 4233 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4234 { 4235 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4236 } 4237 4238 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4239 { 4240 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4241 } 4242 4243 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4244 { 4245 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4246 } 4247 4248 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4249 { 4250 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4251 } 4252 4253 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4254 { 4255 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4256 } 4257 4258 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4259 { 4260 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4261 } 4262 4263 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4264 { 4265 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4266 } 4267 4268 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4269 { 4270 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4271 } 4272 4273 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4274 { 4275 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4276 } 4277 4278 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4279 { 4280 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4281 } 4282 4283 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4284 { 4285 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4286 } 4287 4288 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4289 { 4290 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4291 } 4292 4293 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) 4294 { 4295 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); 4296 } 4297 4298 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) 4299 { 4300 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; 4301 } 4302 4303 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) 4304 { 4305 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); 4306 } 4307 4308 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) 4309 { 4310 return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; 4311 } 4312 4313 /* 4314 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4315 */ 4316 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4317 { 4318 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4319 } 4320 4321 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4322 { 4323 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4324 } 4325 4326 static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id) 4327 { 4328 return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id); 4329 } 4330 4331 static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) 4332 { 4333 return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); 4334 } 4335 4336 static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) 4337 { 4338 return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); 4339 } 4340 4341 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4342 { 4343 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4344 } 4345 4346 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4347 { 4348 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4349 } 4350 4351 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4352 { 4353 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4354 } 4355 4356 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4357 { 4358 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4359 } 4360 4361 static inline bool isar_feature_any_half_evt(const ARMISARegisters *id) 4362 { 4363 return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id); 4364 } 4365 4366 static inline bool isar_feature_any_evt(const ARMISARegisters *id) 4367 { 4368 return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); 4369 } 4370 4371 /* 4372 * Forward to the above feature tests given an ARMCPU pointer. 4373 */ 4374 #define cpu_isar_feature(name, cpu) \ 4375 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4376 4377 #endif 4378