1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 #define VTCR_NSW (1u << 29) 170 #define VTCR_NSA (1u << 30) 171 #define VSTCR_SW VTCR_NSW 172 #define VSTCR_SA VTCR_NSA 173 174 /* Define a maximum sized vector register. 175 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 176 * For 64-bit, this is a 2048-bit SVE register. 177 * 178 * Note that the mapping between S, D, and Q views of the register bank 179 * differs between AArch64 and AArch32. 180 * In AArch32: 181 * Qn = regs[n].d[1]:regs[n].d[0] 182 * Dn = regs[n / 2].d[n & 1] 183 * Sn = regs[n / 4].d[n % 4 / 2], 184 * bits 31..0 for even n, and bits 63..32 for odd n 185 * (and regs[16] to regs[31] are inaccessible) 186 * In AArch64: 187 * Zn = regs[n].d[*] 188 * Qn = regs[n].d[1]:regs[n].d[0] 189 * Dn = regs[n].d[0] 190 * Sn = regs[n].d[0] bits 31..0 191 * Hn = regs[n].d[0] bits 15..0 192 * 193 * This corresponds to the architecturally defined mapping between 194 * the two execution states, and means we do not need to explicitly 195 * map these registers when changing states. 196 * 197 * Align the data for use with TCG host vector operations. 198 */ 199 200 #ifdef TARGET_AARCH64 201 # define ARM_MAX_VQ 16 202 #else 203 # define ARM_MAX_VQ 1 204 #endif 205 206 typedef struct ARMVectorReg { 207 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 208 } ARMVectorReg; 209 210 #ifdef TARGET_AARCH64 211 /* In AArch32 mode, predicate registers do not exist at all. */ 212 typedef struct ARMPredicateReg { 213 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 214 } ARMPredicateReg; 215 216 /* In AArch32 mode, PAC keys do not exist at all. */ 217 typedef struct ARMPACKey { 218 uint64_t lo, hi; 219 } ARMPACKey; 220 #endif 221 222 /* See the commentary above the TBFLAG field definitions. */ 223 typedef struct CPUARMTBFlags { 224 uint32_t flags; 225 target_ulong flags2; 226 } CPUARMTBFlags; 227 228 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 229 230 typedef struct NVICState NVICState; 231 232 typedef struct CPUArchState { 233 /* Regs for current mode. */ 234 uint32_t regs[16]; 235 236 /* 32/64 switch only happens when taking and returning from 237 * exceptions so the overlap semantics are taken care of then 238 * instead of having a complicated union. 239 */ 240 /* Regs for A64 mode. */ 241 uint64_t xregs[32]; 242 uint64_t pc; 243 /* PSTATE isn't an architectural register for ARMv8. However, it is 244 * convenient for us to assemble the underlying state into a 32 bit format 245 * identical to the architectural format used for the SPSR. (This is also 246 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 247 * 'pstate' register are.) Of the PSTATE bits: 248 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 249 * semantics as for AArch32, as described in the comments on each field) 250 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 251 * DAIF (exception masks) are kept in env->daif 252 * BTYPE is kept in env->btype 253 * SM and ZA are kept in env->svcr 254 * all other bits are stored in their correct places in env->pstate 255 */ 256 uint32_t pstate; 257 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 258 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 259 260 /* Cached TBFLAGS state. See below for which bits are included. */ 261 CPUARMTBFlags hflags; 262 263 /* Frequently accessed CPSR bits are stored separately for efficiency. 264 This contains all the other bits. Use cpsr_{read,write} to access 265 the whole CPSR. */ 266 uint32_t uncached_cpsr; 267 uint32_t spsr; 268 269 /* Banked registers. */ 270 uint64_t banked_spsr[8]; 271 uint32_t banked_r13[8]; 272 uint32_t banked_r14[8]; 273 274 /* These hold r8-r12. */ 275 uint32_t usr_regs[5]; 276 uint32_t fiq_regs[5]; 277 278 /* cpsr flag cache for faster execution */ 279 uint32_t CF; /* 0 or 1 */ 280 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 281 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 282 uint32_t ZF; /* Z set if zero. */ 283 uint32_t QF; /* 0 or 1 */ 284 uint32_t GE; /* cpsr[19:16] */ 285 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 286 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 287 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 288 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 289 290 uint64_t elr_el[4]; /* AArch64 exception link regs */ 291 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 292 293 /* System control coprocessor (cp15) */ 294 struct { 295 uint32_t c0_cpuid; 296 union { /* Cache size selection */ 297 struct { 298 uint64_t _unused_csselr0; 299 uint64_t csselr_ns; 300 uint64_t _unused_csselr1; 301 uint64_t csselr_s; 302 }; 303 uint64_t csselr_el[4]; 304 }; 305 union { /* System control register. */ 306 struct { 307 uint64_t _unused_sctlr; 308 uint64_t sctlr_ns; 309 uint64_t hsctlr; 310 uint64_t sctlr_s; 311 }; 312 uint64_t sctlr_el[4]; 313 }; 314 uint64_t vsctlr; /* Virtualization System control register. */ 315 uint64_t cpacr_el1; /* Architectural feature access control register */ 316 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 317 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 318 uint64_t sder; /* Secure debug enable register. */ 319 uint32_t nsacr; /* Non-secure access control register. */ 320 union { /* MMU translation table base 0. */ 321 struct { 322 uint64_t _unused_ttbr0_0; 323 uint64_t ttbr0_ns; 324 uint64_t _unused_ttbr0_1; 325 uint64_t ttbr0_s; 326 }; 327 uint64_t ttbr0_el[4]; 328 }; 329 union { /* MMU translation table base 1. */ 330 struct { 331 uint64_t _unused_ttbr1_0; 332 uint64_t ttbr1_ns; 333 uint64_t _unused_ttbr1_1; 334 uint64_t ttbr1_s; 335 }; 336 uint64_t ttbr1_el[4]; 337 }; 338 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 339 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 340 /* MMU translation table base control. */ 341 uint64_t tcr_el[4]; 342 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 343 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 344 uint32_t c2_data; /* MPU data cacheable bits. */ 345 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 346 union { /* MMU domain access control register 347 * MPU write buffer control. 348 */ 349 struct { 350 uint64_t dacr_ns; 351 uint64_t dacr_s; 352 }; 353 struct { 354 uint64_t dacr32_el2; 355 }; 356 }; 357 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 358 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 359 uint64_t hcr_el2; /* Hypervisor configuration register */ 360 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 361 uint64_t scr_el3; /* Secure configuration register. */ 362 union { /* Fault status registers. */ 363 struct { 364 uint64_t ifsr_ns; 365 uint64_t ifsr_s; 366 }; 367 struct { 368 uint64_t ifsr32_el2; 369 }; 370 }; 371 union { 372 struct { 373 uint64_t _unused_dfsr; 374 uint64_t dfsr_ns; 375 uint64_t hsr; 376 uint64_t dfsr_s; 377 }; 378 uint64_t esr_el[4]; 379 }; 380 uint32_t c6_region[8]; /* MPU base/size registers. */ 381 union { /* Fault address registers. */ 382 struct { 383 uint64_t _unused_far0; 384 #if HOST_BIG_ENDIAN 385 uint32_t ifar_ns; 386 uint32_t dfar_ns; 387 uint32_t ifar_s; 388 uint32_t dfar_s; 389 #else 390 uint32_t dfar_ns; 391 uint32_t ifar_ns; 392 uint32_t dfar_s; 393 uint32_t ifar_s; 394 #endif 395 uint64_t _unused_far3; 396 }; 397 uint64_t far_el[4]; 398 }; 399 uint64_t hpfar_el2; 400 uint64_t hstr_el2; 401 union { /* Translation result. */ 402 struct { 403 uint64_t _unused_par_0; 404 uint64_t par_ns; 405 uint64_t _unused_par_1; 406 uint64_t par_s; 407 }; 408 uint64_t par_el[4]; 409 }; 410 411 uint32_t c9_insn; /* Cache lockdown registers. */ 412 uint32_t c9_data; 413 uint64_t c9_pmcr; /* performance monitor control register */ 414 uint64_t c9_pmcnten; /* perf monitor counter enables */ 415 uint64_t c9_pmovsr; /* perf monitor overflow status */ 416 uint64_t c9_pmuserenr; /* perf monitor user enable */ 417 uint64_t c9_pmselr; /* perf monitor counter selection register */ 418 uint64_t c9_pminten; /* perf monitor interrupt enables */ 419 union { /* Memory attribute redirection */ 420 struct { 421 #if HOST_BIG_ENDIAN 422 uint64_t _unused_mair_0; 423 uint32_t mair1_ns; 424 uint32_t mair0_ns; 425 uint64_t _unused_mair_1; 426 uint32_t mair1_s; 427 uint32_t mair0_s; 428 #else 429 uint64_t _unused_mair_0; 430 uint32_t mair0_ns; 431 uint32_t mair1_ns; 432 uint64_t _unused_mair_1; 433 uint32_t mair0_s; 434 uint32_t mair1_s; 435 #endif 436 }; 437 uint64_t mair_el[4]; 438 }; 439 union { /* vector base address register */ 440 struct { 441 uint64_t _unused_vbar; 442 uint64_t vbar_ns; 443 uint64_t hvbar; 444 uint64_t vbar_s; 445 }; 446 uint64_t vbar_el[4]; 447 }; 448 uint32_t mvbar; /* (monitor) vector base address register */ 449 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 450 struct { /* FCSE PID. */ 451 uint32_t fcseidr_ns; 452 uint32_t fcseidr_s; 453 }; 454 union { /* Context ID. */ 455 struct { 456 uint64_t _unused_contextidr_0; 457 uint64_t contextidr_ns; 458 uint64_t _unused_contextidr_1; 459 uint64_t contextidr_s; 460 }; 461 uint64_t contextidr_el[4]; 462 }; 463 union { /* User RW Thread register. */ 464 struct { 465 uint64_t tpidrurw_ns; 466 uint64_t tpidrprw_ns; 467 uint64_t htpidr; 468 uint64_t _tpidr_el3; 469 }; 470 uint64_t tpidr_el[4]; 471 }; 472 uint64_t tpidr2_el0; 473 /* The secure banks of these registers don't map anywhere */ 474 uint64_t tpidrurw_s; 475 uint64_t tpidrprw_s; 476 uint64_t tpidruro_s; 477 478 union { /* User RO Thread register. */ 479 uint64_t tpidruro_ns; 480 uint64_t tpidrro_el[1]; 481 }; 482 uint64_t c14_cntfrq; /* Counter Frequency register */ 483 uint64_t c14_cntkctl; /* Timer Control register */ 484 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 485 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 486 ARMGenericTimer c14_timer[NUM_GTIMERS]; 487 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 488 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 489 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 490 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 491 uint32_t c15_threadid; /* TI debugger thread-ID. */ 492 uint32_t c15_config_base_address; /* SCU base address. */ 493 uint32_t c15_diagnostic; /* diagnostic register */ 494 uint32_t c15_power_diagnostic; 495 uint32_t c15_power_control; /* power control */ 496 uint64_t dbgbvr[16]; /* breakpoint value registers */ 497 uint64_t dbgbcr[16]; /* breakpoint control registers */ 498 uint64_t dbgwvr[16]; /* watchpoint value registers */ 499 uint64_t dbgwcr[16]; /* watchpoint control registers */ 500 uint64_t dbgclaim; /* DBGCLAIM bits */ 501 uint64_t mdscr_el1; 502 uint64_t oslsr_el1; /* OS Lock Status */ 503 uint64_t osdlr_el1; /* OS DoubleLock status */ 504 uint64_t mdcr_el2; 505 uint64_t mdcr_el3; 506 /* Stores the architectural value of the counter *the last time it was 507 * updated* by pmccntr_op_start. Accesses should always be surrounded 508 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 509 * architecturally-correct value is being read/set. 510 */ 511 uint64_t c15_ccnt; 512 /* Stores the delta between the architectural value and the underlying 513 * cycle count during normal operation. It is used to update c15_ccnt 514 * to be the correct architectural value before accesses. During 515 * accesses, c15_ccnt_delta contains the underlying count being used 516 * for the access, after which it reverts to the delta value in 517 * pmccntr_op_finish. 518 */ 519 uint64_t c15_ccnt_delta; 520 uint64_t c14_pmevcntr[31]; 521 uint64_t c14_pmevcntr_delta[31]; 522 uint64_t c14_pmevtyper[31]; 523 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 524 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 525 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 526 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 527 uint64_t gcr_el1; 528 uint64_t rgsr_el1; 529 530 /* Minimal RAS registers */ 531 uint64_t disr_el1; 532 uint64_t vdisr_el2; 533 uint64_t vsesr_el2; 534 535 /* 536 * Fine-Grained Trap registers. We store these as arrays so the 537 * access checking code doesn't have to manually select 538 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 539 * FEAT_FGT2 will add more elements to these arrays. 540 */ 541 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 542 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 543 uint64_t fgt_exec[1]; /* HFGITR */ 544 } cp15; 545 546 struct { 547 /* M profile has up to 4 stack pointers: 548 * a Main Stack Pointer and a Process Stack Pointer for each 549 * of the Secure and Non-Secure states. (If the CPU doesn't support 550 * the security extension then it has only two SPs.) 551 * In QEMU we always store the currently active SP in regs[13], 552 * and the non-active SP for the current security state in 553 * v7m.other_sp. The stack pointers for the inactive security state 554 * are stored in other_ss_msp and other_ss_psp. 555 * switch_v7m_security_state() is responsible for rearranging them 556 * when we change security state. 557 */ 558 uint32_t other_sp; 559 uint32_t other_ss_msp; 560 uint32_t other_ss_psp; 561 uint32_t vecbase[M_REG_NUM_BANKS]; 562 uint32_t basepri[M_REG_NUM_BANKS]; 563 uint32_t control[M_REG_NUM_BANKS]; 564 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 565 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 566 uint32_t hfsr; /* HardFault Status */ 567 uint32_t dfsr; /* Debug Fault Status Register */ 568 uint32_t sfsr; /* Secure Fault Status Register */ 569 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 570 uint32_t bfar; /* BusFault Address */ 571 uint32_t sfar; /* Secure Fault Address Register */ 572 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 573 int exception; 574 uint32_t primask[M_REG_NUM_BANKS]; 575 uint32_t faultmask[M_REG_NUM_BANKS]; 576 uint32_t aircr; /* only holds r/w state if security extn implemented */ 577 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 578 uint32_t csselr[M_REG_NUM_BANKS]; 579 uint32_t scr[M_REG_NUM_BANKS]; 580 uint32_t msplim[M_REG_NUM_BANKS]; 581 uint32_t psplim[M_REG_NUM_BANKS]; 582 uint32_t fpcar[M_REG_NUM_BANKS]; 583 uint32_t fpccr[M_REG_NUM_BANKS]; 584 uint32_t fpdscr[M_REG_NUM_BANKS]; 585 uint32_t cpacr[M_REG_NUM_BANKS]; 586 uint32_t nsacr; 587 uint32_t ltpsize; 588 uint32_t vpr; 589 } v7m; 590 591 /* Information associated with an exception about to be taken: 592 * code which raises an exception must set cs->exception_index and 593 * the relevant parts of this structure; the cpu_do_interrupt function 594 * will then set the guest-visible registers as part of the exception 595 * entry process. 596 */ 597 struct { 598 uint32_t syndrome; /* AArch64 format syndrome register */ 599 uint32_t fsr; /* AArch32 format fault status register info */ 600 uint64_t vaddress; /* virtual addr associated with exception, if any */ 601 uint32_t target_el; /* EL the exception should be targeted for */ 602 /* If we implement EL2 we will also need to store information 603 * about the intermediate physical address for stage 2 faults. 604 */ 605 } exception; 606 607 /* Information associated with an SError */ 608 struct { 609 uint8_t pending; 610 uint8_t has_esr; 611 uint64_t esr; 612 } serror; 613 614 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 615 616 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 617 uint32_t irq_line_state; 618 619 /* Thumb-2 EE state. */ 620 uint32_t teecr; 621 uint32_t teehbr; 622 623 /* VFP coprocessor state. */ 624 struct { 625 ARMVectorReg zregs[32]; 626 627 #ifdef TARGET_AARCH64 628 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 629 #define FFR_PRED_NUM 16 630 ARMPredicateReg pregs[17]; 631 /* Scratch space for aa64 sve predicate temporary. */ 632 ARMPredicateReg preg_tmp; 633 #endif 634 635 /* We store these fpcsr fields separately for convenience. */ 636 uint32_t qc[4] QEMU_ALIGNED(16); 637 int vec_len; 638 int vec_stride; 639 640 uint32_t xregs[16]; 641 642 /* Scratch space for aa32 neon expansion. */ 643 uint32_t scratch[8]; 644 645 /* There are a number of distinct float control structures: 646 * 647 * fp_status: is the "normal" fp status. 648 * fp_status_fp16: used for half-precision calculations 649 * standard_fp_status : the ARM "Standard FPSCR Value" 650 * standard_fp_status_fp16 : used for half-precision 651 * calculations with the ARM "Standard FPSCR Value" 652 * 653 * Half-precision operations are governed by a separate 654 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 655 * status structure to control this. 656 * 657 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 658 * round-to-nearest and is used by any operations (generally 659 * Neon) which the architecture defines as controlled by the 660 * standard FPSCR value rather than the FPSCR. 661 * 662 * The "standard FPSCR but for fp16 ops" is needed because 663 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 664 * using a fixed value for it. 665 * 666 * To avoid having to transfer exception bits around, we simply 667 * say that the FPSCR cumulative exception flags are the logical 668 * OR of the flags in the four fp statuses. This relies on the 669 * only thing which needs to read the exception flags being 670 * an explicit FPSCR read. 671 */ 672 float_status fp_status; 673 float_status fp_status_f16; 674 float_status standard_fp_status; 675 float_status standard_fp_status_f16; 676 677 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 678 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 679 } vfp; 680 uint64_t exclusive_addr; 681 uint64_t exclusive_val; 682 uint64_t exclusive_high; 683 684 /* iwMMXt coprocessor state. */ 685 struct { 686 uint64_t regs[16]; 687 uint64_t val; 688 689 uint32_t cregs[16]; 690 } iwmmxt; 691 692 #ifdef TARGET_AARCH64 693 struct { 694 ARMPACKey apia; 695 ARMPACKey apib; 696 ARMPACKey apda; 697 ARMPACKey apdb; 698 ARMPACKey apga; 699 } keys; 700 701 uint64_t scxtnum_el[4]; 702 703 /* 704 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 705 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 706 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 707 * When SVL is less than the architectural maximum, the accessible 708 * storage is restricted, such that if the SVL is X bytes the guest can 709 * see only the bottom X elements of zarray[], and only the least 710 * significant X bytes of each element of the array. (In other words, 711 * the observable part is always square.) 712 * 713 * The ZA storage can also be considered as a set of square tiles of 714 * elements of different sizes. The mapping from tiles to the ZA array 715 * is architecturally defined, such that for tiles of elements of esz 716 * bytes, the Nth row (or "horizontal slice") of tile T is in 717 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 718 * in the ZA storage, because its rows are striped through the ZA array. 719 * 720 * Because this is so large, keep this toward the end of the reset area, 721 * to keep the offsets into the rest of the structure smaller. 722 */ 723 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 724 #endif 725 726 struct CPUBreakpoint *cpu_breakpoint[16]; 727 struct CPUWatchpoint *cpu_watchpoint[16]; 728 729 /* Optional fault info across tlb lookup. */ 730 ARMMMUFaultInfo *tlb_fi; 731 732 /* Fields up to this point are cleared by a CPU reset */ 733 struct {} end_reset_fields; 734 735 /* Fields after this point are preserved across CPU reset. */ 736 737 /* Internal CPU feature flags. */ 738 uint64_t features; 739 740 /* PMSAv7 MPU */ 741 struct { 742 uint32_t *drbar; 743 uint32_t *drsr; 744 uint32_t *dracr; 745 uint32_t rnr[M_REG_NUM_BANKS]; 746 } pmsav7; 747 748 /* PMSAv8 MPU */ 749 struct { 750 /* The PMSAv8 implementation also shares some PMSAv7 config 751 * and state: 752 * pmsav7.rnr (region number register) 753 * pmsav7_dregion (number of configured regions) 754 */ 755 uint32_t *rbar[M_REG_NUM_BANKS]; 756 uint32_t *rlar[M_REG_NUM_BANKS]; 757 uint32_t *hprbar; 758 uint32_t *hprlar; 759 uint32_t mair0[M_REG_NUM_BANKS]; 760 uint32_t mair1[M_REG_NUM_BANKS]; 761 uint32_t hprselr; 762 } pmsav8; 763 764 /* v8M SAU */ 765 struct { 766 uint32_t *rbar; 767 uint32_t *rlar; 768 uint32_t rnr; 769 uint32_t ctrl; 770 } sau; 771 772 #if !defined(CONFIG_USER_ONLY) 773 NVICState *nvic; 774 const struct arm_boot_info *boot_info; 775 /* Store GICv3CPUState to access from this struct */ 776 void *gicv3state; 777 #else /* CONFIG_USER_ONLY */ 778 /* For usermode syscall translation. */ 779 bool eabi; 780 #endif /* CONFIG_USER_ONLY */ 781 782 #ifdef TARGET_TAGGED_ADDRESSES 783 /* Linux syscall tagged address support */ 784 bool tagged_addr_enable; 785 #endif 786 } CPUARMState; 787 788 static inline void set_feature(CPUARMState *env, int feature) 789 { 790 env->features |= 1ULL << feature; 791 } 792 793 static inline void unset_feature(CPUARMState *env, int feature) 794 { 795 env->features &= ~(1ULL << feature); 796 } 797 798 /** 799 * ARMELChangeHookFn: 800 * type of a function which can be registered via arm_register_el_change_hook() 801 * to get callbacks when the CPU changes its exception level or mode. 802 */ 803 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 804 typedef struct ARMELChangeHook ARMELChangeHook; 805 struct ARMELChangeHook { 806 ARMELChangeHookFn *hook; 807 void *opaque; 808 QLIST_ENTRY(ARMELChangeHook) node; 809 }; 810 811 /* These values map onto the return values for 812 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 813 typedef enum ARMPSCIState { 814 PSCI_ON = 0, 815 PSCI_OFF = 1, 816 PSCI_ON_PENDING = 2 817 } ARMPSCIState; 818 819 typedef struct ARMISARegisters ARMISARegisters; 820 821 /* 822 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 823 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 824 * 825 * While processing properties during initialization, corresponding init bits 826 * are set for bits in sve_vq_map that have been set by properties. 827 * 828 * Bits set in supported represent valid vector lengths for the CPU type. 829 */ 830 typedef struct { 831 uint32_t map, init, supported; 832 } ARMVQMap; 833 834 /** 835 * ARMCPU: 836 * @env: #CPUARMState 837 * 838 * An ARM CPU core. 839 */ 840 struct ArchCPU { 841 /*< private >*/ 842 CPUState parent_obj; 843 /*< public >*/ 844 845 CPUNegativeOffsetState neg; 846 CPUARMState env; 847 848 /* Coprocessor information */ 849 GHashTable *cp_regs; 850 /* For marshalling (mostly coprocessor) register state between the 851 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 852 * we use these arrays. 853 */ 854 /* List of register indexes managed via these arrays; (full KVM style 855 * 64 bit indexes, not CPRegInfo 32 bit indexes) 856 */ 857 uint64_t *cpreg_indexes; 858 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 859 uint64_t *cpreg_values; 860 /* Length of the indexes, values, reset_values arrays */ 861 int32_t cpreg_array_len; 862 /* These are used only for migration: incoming data arrives in 863 * these fields and is sanity checked in post_load before copying 864 * to the working data structures above. 865 */ 866 uint64_t *cpreg_vmstate_indexes; 867 uint64_t *cpreg_vmstate_values; 868 int32_t cpreg_vmstate_array_len; 869 870 DynamicGDBXMLInfo dyn_sysreg_xml; 871 DynamicGDBXMLInfo dyn_svereg_xml; 872 873 /* Timers used by the generic (architected) timer */ 874 QEMUTimer *gt_timer[NUM_GTIMERS]; 875 /* 876 * Timer used by the PMU. Its state is restored after migration by 877 * pmu_op_finish() - it does not need other handling during migration 878 */ 879 QEMUTimer *pmu_timer; 880 /* GPIO outputs for generic timer */ 881 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 882 /* GPIO output for GICv3 maintenance interrupt signal */ 883 qemu_irq gicv3_maintenance_interrupt; 884 /* GPIO output for the PMU interrupt */ 885 qemu_irq pmu_interrupt; 886 887 /* MemoryRegion to use for secure physical accesses */ 888 MemoryRegion *secure_memory; 889 890 /* MemoryRegion to use for allocation tag accesses */ 891 MemoryRegion *tag_memory; 892 MemoryRegion *secure_tag_memory; 893 894 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 895 Object *idau; 896 897 /* 'compatible' string for this CPU for Linux device trees */ 898 const char *dtb_compatible; 899 900 /* PSCI version for this CPU 901 * Bits[31:16] = Major Version 902 * Bits[15:0] = Minor Version 903 */ 904 uint32_t psci_version; 905 906 /* Current power state, access guarded by BQL */ 907 ARMPSCIState power_state; 908 909 /* CPU has virtualization extension */ 910 bool has_el2; 911 /* CPU has security extension */ 912 bool has_el3; 913 /* CPU has PMU (Performance Monitor Unit) */ 914 bool has_pmu; 915 /* CPU has VFP */ 916 bool has_vfp; 917 /* CPU has Neon */ 918 bool has_neon; 919 /* CPU has M-profile DSP extension */ 920 bool has_dsp; 921 922 /* CPU has memory protection unit */ 923 bool has_mpu; 924 /* PMSAv7 MPU number of supported regions */ 925 uint32_t pmsav7_dregion; 926 /* PMSAv8 MPU number of supported hyp regions */ 927 uint32_t pmsav8r_hdregion; 928 /* v8M SAU number of supported regions */ 929 uint32_t sau_sregion; 930 931 /* PSCI conduit used to invoke PSCI methods 932 * 0 - disabled, 1 - smc, 2 - hvc 933 */ 934 uint32_t psci_conduit; 935 936 /* For v8M, initial value of the Secure VTOR */ 937 uint32_t init_svtor; 938 /* For v8M, initial value of the Non-secure VTOR */ 939 uint32_t init_nsvtor; 940 941 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 942 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 943 */ 944 uint32_t kvm_target; 945 946 /* KVM init features for this CPU */ 947 uint32_t kvm_init_features[7]; 948 949 /* KVM CPU state */ 950 951 /* KVM virtual time adjustment */ 952 bool kvm_adjvtime; 953 bool kvm_vtime_dirty; 954 uint64_t kvm_vtime; 955 956 /* KVM steal time */ 957 OnOffAuto kvm_steal_time; 958 959 /* Uniprocessor system with MP extensions */ 960 bool mp_is_up; 961 962 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 963 * and the probe failed (so we need to report the error in realize) 964 */ 965 bool host_cpu_probe_failed; 966 967 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 968 * register. 969 */ 970 int32_t core_count; 971 972 /* The instance init functions for implementation-specific subclasses 973 * set these fields to specify the implementation-dependent values of 974 * various constant registers and reset values of non-constant 975 * registers. 976 * Some of these might become QOM properties eventually. 977 * Field names match the official register names as defined in the 978 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 979 * is used for reset values of non-constant registers; no reset_ 980 * prefix means a constant register. 981 * Some of these registers are split out into a substructure that 982 * is shared with the translators to control the ISA. 983 * 984 * Note that if you add an ID register to the ARMISARegisters struct 985 * you need to also update the 32-bit and 64-bit versions of the 986 * kvm_arm_get_host_cpu_features() function to correctly populate the 987 * field by reading the value from the KVM vCPU. 988 */ 989 struct ARMISARegisters { 990 uint32_t id_isar0; 991 uint32_t id_isar1; 992 uint32_t id_isar2; 993 uint32_t id_isar3; 994 uint32_t id_isar4; 995 uint32_t id_isar5; 996 uint32_t id_isar6; 997 uint32_t id_mmfr0; 998 uint32_t id_mmfr1; 999 uint32_t id_mmfr2; 1000 uint32_t id_mmfr3; 1001 uint32_t id_mmfr4; 1002 uint32_t id_mmfr5; 1003 uint32_t id_pfr0; 1004 uint32_t id_pfr1; 1005 uint32_t id_pfr2; 1006 uint32_t mvfr0; 1007 uint32_t mvfr1; 1008 uint32_t mvfr2; 1009 uint32_t id_dfr0; 1010 uint32_t id_dfr1; 1011 uint32_t dbgdidr; 1012 uint32_t dbgdevid; 1013 uint32_t dbgdevid1; 1014 uint64_t id_aa64isar0; 1015 uint64_t id_aa64isar1; 1016 uint64_t id_aa64pfr0; 1017 uint64_t id_aa64pfr1; 1018 uint64_t id_aa64mmfr0; 1019 uint64_t id_aa64mmfr1; 1020 uint64_t id_aa64mmfr2; 1021 uint64_t id_aa64dfr0; 1022 uint64_t id_aa64dfr1; 1023 uint64_t id_aa64zfr0; 1024 uint64_t id_aa64smfr0; 1025 uint64_t reset_pmcr_el0; 1026 } isar; 1027 uint64_t midr; 1028 uint32_t revidr; 1029 uint32_t reset_fpsid; 1030 uint64_t ctr; 1031 uint32_t reset_sctlr; 1032 uint64_t pmceid0; 1033 uint64_t pmceid1; 1034 uint32_t id_afr0; 1035 uint64_t id_aa64afr0; 1036 uint64_t id_aa64afr1; 1037 uint64_t clidr; 1038 uint64_t mp_affinity; /* MP ID without feature bits */ 1039 /* The elements of this array are the CCSIDR values for each cache, 1040 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1041 */ 1042 uint64_t ccsidr[16]; 1043 uint64_t reset_cbar; 1044 uint32_t reset_auxcr; 1045 bool reset_hivecs; 1046 1047 /* 1048 * Intermediate values used during property parsing. 1049 * Once finalized, the values should be read from ID_AA64*. 1050 */ 1051 bool prop_pauth; 1052 bool prop_pauth_impdef; 1053 bool prop_lpa2; 1054 1055 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1056 uint32_t dcz_blocksize; 1057 uint64_t rvbar_prop; /* Property/input signals. */ 1058 1059 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1060 int gic_num_lrs; /* number of list registers */ 1061 int gic_vpribits; /* number of virtual priority bits */ 1062 int gic_vprebits; /* number of virtual preemption bits */ 1063 int gic_pribits; /* number of physical priority bits */ 1064 1065 /* Whether the cfgend input is high (i.e. this CPU should reset into 1066 * big-endian mode). This setting isn't used directly: instead it modifies 1067 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1068 * architecture version. 1069 */ 1070 bool cfgend; 1071 1072 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1073 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1074 1075 int32_t node_id; /* NUMA node this CPU belongs to */ 1076 1077 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1078 uint8_t device_irq_level; 1079 1080 /* Used to set the maximum vector length the cpu will support. */ 1081 uint32_t sve_max_vq; 1082 1083 #ifdef CONFIG_USER_ONLY 1084 /* Used to set the default vector length at process start. */ 1085 uint32_t sve_default_vq; 1086 uint32_t sme_default_vq; 1087 #endif 1088 1089 ARMVQMap sve_vq; 1090 ARMVQMap sme_vq; 1091 1092 /* Generic timer counter frequency, in Hz */ 1093 uint64_t gt_cntfrq_hz; 1094 }; 1095 1096 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1097 1098 void arm_cpu_post_init(Object *obj); 1099 1100 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1101 1102 #ifndef CONFIG_USER_ONLY 1103 extern const VMStateDescription vmstate_arm_cpu; 1104 1105 void arm_cpu_do_interrupt(CPUState *cpu); 1106 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1107 #endif /* !CONFIG_USER_ONLY */ 1108 1109 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1110 MemTxAttrs *attrs); 1111 1112 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1113 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1114 1115 /* 1116 * Helpers to dynamically generates XML descriptions of the sysregs 1117 * and SVE registers. Returns the number of registers in each set. 1118 */ 1119 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1120 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1121 1122 /* Returns the dynamically generated XML for the gdb stub. 1123 * Returns a pointer to the XML contents for the specified XML file or NULL 1124 * if the XML name doesn't match the predefined one. 1125 */ 1126 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1127 1128 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1129 int cpuid, DumpState *s); 1130 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1131 int cpuid, DumpState *s); 1132 1133 #ifdef TARGET_AARCH64 1134 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1135 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1136 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1137 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1138 int new_el, bool el0_a64); 1139 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1140 1141 /* 1142 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1143 * The byte at offset i from the start of the in-memory representation contains 1144 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1145 * lowest offsets are stored in the lowest memory addresses, then that nearly 1146 * matches QEMU's representation, which is to use an array of host-endian 1147 * uint64_t's, where the lower offsets are at the lower indices. To complete 1148 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1149 */ 1150 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1151 { 1152 #if HOST_BIG_ENDIAN 1153 int i; 1154 1155 for (i = 0; i < nr; ++i) { 1156 dst[i] = bswap64(src[i]); 1157 } 1158 1159 return dst; 1160 #else 1161 return src; 1162 #endif 1163 } 1164 1165 #else 1166 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1167 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1168 int n, bool a) 1169 { } 1170 #endif 1171 1172 void aarch64_sync_32_to_64(CPUARMState *env); 1173 void aarch64_sync_64_to_32(CPUARMState *env); 1174 1175 int fp_exception_el(CPUARMState *env, int cur_el); 1176 int sve_exception_el(CPUARMState *env, int cur_el); 1177 int sme_exception_el(CPUARMState *env, int cur_el); 1178 1179 /** 1180 * sve_vqm1_for_el_sm: 1181 * @env: CPUARMState 1182 * @el: exception level 1183 * @sm: streaming mode 1184 * 1185 * Compute the current vector length for @el & @sm, in units of 1186 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1187 * If @sm, compute for SVL, otherwise NVL. 1188 */ 1189 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1190 1191 /* Likewise, but using @sm = PSTATE.SM. */ 1192 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1193 1194 static inline bool is_a64(CPUARMState *env) 1195 { 1196 return env->aarch64; 1197 } 1198 1199 /** 1200 * pmu_op_start/finish 1201 * @env: CPUARMState 1202 * 1203 * Convert all PMU counters between their delta form (the typical mode when 1204 * they are enabled) and the guest-visible values. These two calls must 1205 * surround any action which might affect the counters. 1206 */ 1207 void pmu_op_start(CPUARMState *env); 1208 void pmu_op_finish(CPUARMState *env); 1209 1210 /* 1211 * Called when a PMU counter is due to overflow 1212 */ 1213 void arm_pmu_timer_cb(void *opaque); 1214 1215 /** 1216 * Functions to register as EL change hooks for PMU mode filtering 1217 */ 1218 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1219 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1220 1221 /* 1222 * pmu_init 1223 * @cpu: ARMCPU 1224 * 1225 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1226 * for the current configuration 1227 */ 1228 void pmu_init(ARMCPU *cpu); 1229 1230 /* SCTLR bit meanings. Several bits have been reused in newer 1231 * versions of the architecture; in that case we define constants 1232 * for both old and new bit meanings. Code which tests against those 1233 * bits should probably check or otherwise arrange that the CPU 1234 * is the architectural version it expects. 1235 */ 1236 #define SCTLR_M (1U << 0) 1237 #define SCTLR_A (1U << 1) 1238 #define SCTLR_C (1U << 2) 1239 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1240 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1241 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1242 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1243 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1244 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1245 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1246 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1247 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1248 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1249 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1250 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1251 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1252 #define SCTLR_SED (1U << 8) /* v8 onward */ 1253 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1254 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1255 #define SCTLR_F (1U << 10) /* up to v6 */ 1256 #define SCTLR_SW (1U << 10) /* v7 */ 1257 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1258 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1259 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1260 #define SCTLR_I (1U << 12) 1261 #define SCTLR_V (1U << 13) /* AArch32 only */ 1262 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1263 #define SCTLR_RR (1U << 14) /* up to v7 */ 1264 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1265 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1266 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1267 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1268 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1269 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1270 #define SCTLR_BR (1U << 17) /* PMSA only */ 1271 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1272 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1273 #define SCTLR_WXN (1U << 19) 1274 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1275 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1276 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1277 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1278 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1279 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1280 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1281 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1282 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1283 #define SCTLR_VE (1U << 24) /* up to v7 */ 1284 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1285 #define SCTLR_EE (1U << 25) 1286 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1287 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1288 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1289 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1290 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1291 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1292 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1293 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1294 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1295 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1296 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1297 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1298 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1299 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1300 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1301 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1302 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1303 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1304 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1305 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1306 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1307 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1308 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1309 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1310 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1311 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1312 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1313 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1314 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1315 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1316 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1317 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1318 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1319 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1320 1321 /* Bit definitions for CPACR (AArch32 only) */ 1322 FIELD(CPACR, CP10, 20, 2) 1323 FIELD(CPACR, CP11, 22, 2) 1324 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1325 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1326 FIELD(CPACR, ASEDIS, 31, 1) 1327 1328 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1329 FIELD(CPACR_EL1, ZEN, 16, 2) 1330 FIELD(CPACR_EL1, FPEN, 20, 2) 1331 FIELD(CPACR_EL1, SMEN, 24, 2) 1332 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1333 1334 /* Bit definitions for HCPTR (AArch32 only) */ 1335 FIELD(HCPTR, TCP10, 10, 1) 1336 FIELD(HCPTR, TCP11, 11, 1) 1337 FIELD(HCPTR, TASE, 15, 1) 1338 FIELD(HCPTR, TTA, 20, 1) 1339 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1340 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1341 1342 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1343 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1344 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1345 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1346 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1347 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1348 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1349 FIELD(CPTR_EL2, TTA, 28, 1) 1350 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1351 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1352 1353 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1354 FIELD(CPTR_EL3, EZ, 8, 1) 1355 FIELD(CPTR_EL3, TFP, 10, 1) 1356 FIELD(CPTR_EL3, ESM, 12, 1) 1357 FIELD(CPTR_EL3, TTA, 20, 1) 1358 FIELD(CPTR_EL3, TAM, 30, 1) 1359 FIELD(CPTR_EL3, TCPAC, 31, 1) 1360 1361 #define MDCR_MTPME (1U << 28) 1362 #define MDCR_TDCC (1U << 27) 1363 #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ 1364 #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ 1365 #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ 1366 #define MDCR_EPMAD (1U << 21) 1367 #define MDCR_EDAD (1U << 20) 1368 #define MDCR_TTRF (1U << 19) 1369 #define MDCR_STE (1U << 18) /* MDCR_EL3 */ 1370 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1371 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1372 #define MDCR_SDD (1U << 16) 1373 #define MDCR_SPD (3U << 14) 1374 #define MDCR_TDRA (1U << 11) 1375 #define MDCR_TDOSA (1U << 10) 1376 #define MDCR_TDA (1U << 9) 1377 #define MDCR_TDE (1U << 8) 1378 #define MDCR_HPME (1U << 7) 1379 #define MDCR_TPM (1U << 6) 1380 #define MDCR_TPMCR (1U << 5) 1381 #define MDCR_HPMN (0x1fU) 1382 1383 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1384 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ 1385 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ 1386 MDCR_STE | MDCR_SPME | MDCR_SPD) 1387 1388 #define CPSR_M (0x1fU) 1389 #define CPSR_T (1U << 5) 1390 #define CPSR_F (1U << 6) 1391 #define CPSR_I (1U << 7) 1392 #define CPSR_A (1U << 8) 1393 #define CPSR_E (1U << 9) 1394 #define CPSR_IT_2_7 (0xfc00U) 1395 #define CPSR_GE (0xfU << 16) 1396 #define CPSR_IL (1U << 20) 1397 #define CPSR_DIT (1U << 21) 1398 #define CPSR_PAN (1U << 22) 1399 #define CPSR_SSBS (1U << 23) 1400 #define CPSR_J (1U << 24) 1401 #define CPSR_IT_0_1 (3U << 25) 1402 #define CPSR_Q (1U << 27) 1403 #define CPSR_V (1U << 28) 1404 #define CPSR_C (1U << 29) 1405 #define CPSR_Z (1U << 30) 1406 #define CPSR_N (1U << 31) 1407 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1408 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1409 1410 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1411 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1412 | CPSR_NZCV) 1413 /* Bits writable in user mode. */ 1414 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1415 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1416 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1417 1418 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1419 #define XPSR_EXCP 0x1ffU 1420 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1421 #define XPSR_IT_2_7 CPSR_IT_2_7 1422 #define XPSR_GE CPSR_GE 1423 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1424 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1425 #define XPSR_IT_0_1 CPSR_IT_0_1 1426 #define XPSR_Q CPSR_Q 1427 #define XPSR_V CPSR_V 1428 #define XPSR_C CPSR_C 1429 #define XPSR_Z CPSR_Z 1430 #define XPSR_N CPSR_N 1431 #define XPSR_NZCV CPSR_NZCV 1432 #define XPSR_IT CPSR_IT 1433 1434 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1435 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1436 #define TTBCR_PD0 (1U << 4) 1437 #define TTBCR_PD1 (1U << 5) 1438 #define TTBCR_EPD0 (1U << 7) 1439 #define TTBCR_IRGN0 (3U << 8) 1440 #define TTBCR_ORGN0 (3U << 10) 1441 #define TTBCR_SH0 (3U << 12) 1442 #define TTBCR_T1SZ (3U << 16) 1443 #define TTBCR_A1 (1U << 22) 1444 #define TTBCR_EPD1 (1U << 23) 1445 #define TTBCR_IRGN1 (3U << 24) 1446 #define TTBCR_ORGN1 (3U << 26) 1447 #define TTBCR_SH1 (1U << 28) 1448 #define TTBCR_EAE (1U << 31) 1449 1450 FIELD(VTCR, T0SZ, 0, 6) 1451 FIELD(VTCR, SL0, 6, 2) 1452 FIELD(VTCR, IRGN0, 8, 2) 1453 FIELD(VTCR, ORGN0, 10, 2) 1454 FIELD(VTCR, SH0, 12, 2) 1455 FIELD(VTCR, TG0, 14, 2) 1456 FIELD(VTCR, PS, 16, 3) 1457 FIELD(VTCR, VS, 19, 1) 1458 FIELD(VTCR, HA, 21, 1) 1459 FIELD(VTCR, HD, 22, 1) 1460 FIELD(VTCR, HWU59, 25, 1) 1461 FIELD(VTCR, HWU60, 26, 1) 1462 FIELD(VTCR, HWU61, 27, 1) 1463 FIELD(VTCR, HWU62, 28, 1) 1464 FIELD(VTCR, NSW, 29, 1) 1465 FIELD(VTCR, NSA, 30, 1) 1466 FIELD(VTCR, DS, 32, 1) 1467 FIELD(VTCR, SL2, 33, 1) 1468 1469 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1470 * Only these are valid when in AArch64 mode; in 1471 * AArch32 mode SPSRs are basically CPSR-format. 1472 */ 1473 #define PSTATE_SP (1U) 1474 #define PSTATE_M (0xFU) 1475 #define PSTATE_nRW (1U << 4) 1476 #define PSTATE_F (1U << 6) 1477 #define PSTATE_I (1U << 7) 1478 #define PSTATE_A (1U << 8) 1479 #define PSTATE_D (1U << 9) 1480 #define PSTATE_BTYPE (3U << 10) 1481 #define PSTATE_SSBS (1U << 12) 1482 #define PSTATE_IL (1U << 20) 1483 #define PSTATE_SS (1U << 21) 1484 #define PSTATE_PAN (1U << 22) 1485 #define PSTATE_UAO (1U << 23) 1486 #define PSTATE_DIT (1U << 24) 1487 #define PSTATE_TCO (1U << 25) 1488 #define PSTATE_V (1U << 28) 1489 #define PSTATE_C (1U << 29) 1490 #define PSTATE_Z (1U << 30) 1491 #define PSTATE_N (1U << 31) 1492 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1493 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1494 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1495 /* Mode values for AArch64 */ 1496 #define PSTATE_MODE_EL3h 13 1497 #define PSTATE_MODE_EL3t 12 1498 #define PSTATE_MODE_EL2h 9 1499 #define PSTATE_MODE_EL2t 8 1500 #define PSTATE_MODE_EL1h 5 1501 #define PSTATE_MODE_EL1t 4 1502 #define PSTATE_MODE_EL0t 0 1503 1504 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1505 FIELD(SVCR, SM, 0, 1) 1506 FIELD(SVCR, ZA, 1, 1) 1507 1508 /* Fields for SMCR_ELx. */ 1509 FIELD(SMCR, LEN, 0, 4) 1510 FIELD(SMCR, FA64, 31, 1) 1511 1512 /* Write a new value to v7m.exception, thus transitioning into or out 1513 * of Handler mode; this may result in a change of active stack pointer. 1514 */ 1515 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1516 1517 /* Map EL and handler into a PSTATE_MODE. */ 1518 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1519 { 1520 return (el << 2) | handler; 1521 } 1522 1523 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1524 * interprocessing, so we don't attempt to sync with the cpsr state used by 1525 * the 32 bit decoder. 1526 */ 1527 static inline uint32_t pstate_read(CPUARMState *env) 1528 { 1529 int ZF; 1530 1531 ZF = (env->ZF == 0); 1532 return (env->NF & 0x80000000) | (ZF << 30) 1533 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1534 | env->pstate | env->daif | (env->btype << 10); 1535 } 1536 1537 static inline void pstate_write(CPUARMState *env, uint32_t val) 1538 { 1539 env->ZF = (~val) & PSTATE_Z; 1540 env->NF = val; 1541 env->CF = (val >> 29) & 1; 1542 env->VF = (val << 3) & 0x80000000; 1543 env->daif = val & PSTATE_DAIF; 1544 env->btype = (val >> 10) & 3; 1545 env->pstate = val & ~CACHED_PSTATE_BITS; 1546 } 1547 1548 /* Return the current CPSR value. */ 1549 uint32_t cpsr_read(CPUARMState *env); 1550 1551 typedef enum CPSRWriteType { 1552 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1553 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1554 CPSRWriteRaw = 2, 1555 /* trust values, no reg bank switch, no hflags rebuild */ 1556 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1557 } CPSRWriteType; 1558 1559 /* 1560 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1561 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1562 * correspond to TB flags bits cached in the hflags, unless @write_type 1563 * is CPSRWriteRaw. 1564 */ 1565 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1566 CPSRWriteType write_type); 1567 1568 /* Return the current xPSR value. */ 1569 static inline uint32_t xpsr_read(CPUARMState *env) 1570 { 1571 int ZF; 1572 ZF = (env->ZF == 0); 1573 return (env->NF & 0x80000000) | (ZF << 30) 1574 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1575 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1576 | ((env->condexec_bits & 0xfc) << 8) 1577 | (env->GE << 16) 1578 | env->v7m.exception; 1579 } 1580 1581 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1582 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1583 { 1584 if (mask & XPSR_NZCV) { 1585 env->ZF = (~val) & XPSR_Z; 1586 env->NF = val; 1587 env->CF = (val >> 29) & 1; 1588 env->VF = (val << 3) & 0x80000000; 1589 } 1590 if (mask & XPSR_Q) { 1591 env->QF = ((val & XPSR_Q) != 0); 1592 } 1593 if (mask & XPSR_GE) { 1594 env->GE = (val & XPSR_GE) >> 16; 1595 } 1596 #ifndef CONFIG_USER_ONLY 1597 if (mask & XPSR_T) { 1598 env->thumb = ((val & XPSR_T) != 0); 1599 } 1600 if (mask & XPSR_IT_0_1) { 1601 env->condexec_bits &= ~3; 1602 env->condexec_bits |= (val >> 25) & 3; 1603 } 1604 if (mask & XPSR_IT_2_7) { 1605 env->condexec_bits &= 3; 1606 env->condexec_bits |= (val >> 8) & 0xfc; 1607 } 1608 if (mask & XPSR_EXCP) { 1609 /* Note that this only happens on exception exit */ 1610 write_v7m_exception(env, val & XPSR_EXCP); 1611 } 1612 #endif 1613 } 1614 1615 #define HCR_VM (1ULL << 0) 1616 #define HCR_SWIO (1ULL << 1) 1617 #define HCR_PTW (1ULL << 2) 1618 #define HCR_FMO (1ULL << 3) 1619 #define HCR_IMO (1ULL << 4) 1620 #define HCR_AMO (1ULL << 5) 1621 #define HCR_VF (1ULL << 6) 1622 #define HCR_VI (1ULL << 7) 1623 #define HCR_VSE (1ULL << 8) 1624 #define HCR_FB (1ULL << 9) 1625 #define HCR_BSU_MASK (3ULL << 10) 1626 #define HCR_DC (1ULL << 12) 1627 #define HCR_TWI (1ULL << 13) 1628 #define HCR_TWE (1ULL << 14) 1629 #define HCR_TID0 (1ULL << 15) 1630 #define HCR_TID1 (1ULL << 16) 1631 #define HCR_TID2 (1ULL << 17) 1632 #define HCR_TID3 (1ULL << 18) 1633 #define HCR_TSC (1ULL << 19) 1634 #define HCR_TIDCP (1ULL << 20) 1635 #define HCR_TACR (1ULL << 21) 1636 #define HCR_TSW (1ULL << 22) 1637 #define HCR_TPCP (1ULL << 23) 1638 #define HCR_TPU (1ULL << 24) 1639 #define HCR_TTLB (1ULL << 25) 1640 #define HCR_TVM (1ULL << 26) 1641 #define HCR_TGE (1ULL << 27) 1642 #define HCR_TDZ (1ULL << 28) 1643 #define HCR_HCD (1ULL << 29) 1644 #define HCR_TRVM (1ULL << 30) 1645 #define HCR_RW (1ULL << 31) 1646 #define HCR_CD (1ULL << 32) 1647 #define HCR_ID (1ULL << 33) 1648 #define HCR_E2H (1ULL << 34) 1649 #define HCR_TLOR (1ULL << 35) 1650 #define HCR_TERR (1ULL << 36) 1651 #define HCR_TEA (1ULL << 37) 1652 #define HCR_MIOCNCE (1ULL << 38) 1653 /* RES0 bit 39 */ 1654 #define HCR_APK (1ULL << 40) 1655 #define HCR_API (1ULL << 41) 1656 #define HCR_NV (1ULL << 42) 1657 #define HCR_NV1 (1ULL << 43) 1658 #define HCR_AT (1ULL << 44) 1659 #define HCR_NV2 (1ULL << 45) 1660 #define HCR_FWB (1ULL << 46) 1661 #define HCR_FIEN (1ULL << 47) 1662 /* RES0 bit 48 */ 1663 #define HCR_TID4 (1ULL << 49) 1664 #define HCR_TICAB (1ULL << 50) 1665 #define HCR_AMVOFFEN (1ULL << 51) 1666 #define HCR_TOCU (1ULL << 52) 1667 #define HCR_ENSCXT (1ULL << 53) 1668 #define HCR_TTLBIS (1ULL << 54) 1669 #define HCR_TTLBOS (1ULL << 55) 1670 #define HCR_ATA (1ULL << 56) 1671 #define HCR_DCT (1ULL << 57) 1672 #define HCR_TID5 (1ULL << 58) 1673 #define HCR_TWEDEN (1ULL << 59) 1674 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1675 1676 #define HCRX_ENAS0 (1ULL << 0) 1677 #define HCRX_ENALS (1ULL << 1) 1678 #define HCRX_ENASR (1ULL << 2) 1679 #define HCRX_FNXS (1ULL << 3) 1680 #define HCRX_FGTNXS (1ULL << 4) 1681 #define HCRX_SMPME (1ULL << 5) 1682 #define HCRX_TALLINT (1ULL << 6) 1683 #define HCRX_VINMI (1ULL << 7) 1684 #define HCRX_VFNMI (1ULL << 8) 1685 #define HCRX_CMOW (1ULL << 9) 1686 #define HCRX_MCE2 (1ULL << 10) 1687 #define HCRX_MSCEN (1ULL << 11) 1688 1689 #define HPFAR_NS (1ULL << 63) 1690 1691 #define SCR_NS (1ULL << 0) 1692 #define SCR_IRQ (1ULL << 1) 1693 #define SCR_FIQ (1ULL << 2) 1694 #define SCR_EA (1ULL << 3) 1695 #define SCR_FW (1ULL << 4) 1696 #define SCR_AW (1ULL << 5) 1697 #define SCR_NET (1ULL << 6) 1698 #define SCR_SMD (1ULL << 7) 1699 #define SCR_HCE (1ULL << 8) 1700 #define SCR_SIF (1ULL << 9) 1701 #define SCR_RW (1ULL << 10) 1702 #define SCR_ST (1ULL << 11) 1703 #define SCR_TWI (1ULL << 12) 1704 #define SCR_TWE (1ULL << 13) 1705 #define SCR_TLOR (1ULL << 14) 1706 #define SCR_TERR (1ULL << 15) 1707 #define SCR_APK (1ULL << 16) 1708 #define SCR_API (1ULL << 17) 1709 #define SCR_EEL2 (1ULL << 18) 1710 #define SCR_EASE (1ULL << 19) 1711 #define SCR_NMEA (1ULL << 20) 1712 #define SCR_FIEN (1ULL << 21) 1713 #define SCR_ENSCXT (1ULL << 25) 1714 #define SCR_ATA (1ULL << 26) 1715 #define SCR_FGTEN (1ULL << 27) 1716 #define SCR_ECVEN (1ULL << 28) 1717 #define SCR_TWEDEN (1ULL << 29) 1718 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1719 #define SCR_TME (1ULL << 34) 1720 #define SCR_AMVOFFEN (1ULL << 35) 1721 #define SCR_ENAS0 (1ULL << 36) 1722 #define SCR_ADEN (1ULL << 37) 1723 #define SCR_HXEN (1ULL << 38) 1724 #define SCR_TRNDR (1ULL << 40) 1725 #define SCR_ENTP2 (1ULL << 41) 1726 #define SCR_GPF (1ULL << 48) 1727 1728 #define HSTR_TTEE (1 << 16) 1729 #define HSTR_TJDBX (1 << 17) 1730 1731 /* Return the current FPSCR value. */ 1732 uint32_t vfp_get_fpscr(CPUARMState *env); 1733 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1734 1735 /* FPCR, Floating Point Control Register 1736 * FPSR, Floating Poiht Status Register 1737 * 1738 * For A64 the FPSCR is split into two logically distinct registers, 1739 * FPCR and FPSR. However since they still use non-overlapping bits 1740 * we store the underlying state in fpscr and just mask on read/write. 1741 */ 1742 #define FPSR_MASK 0xf800009f 1743 #define FPCR_MASK 0x07ff9f00 1744 1745 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1746 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1747 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1748 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1749 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1750 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1751 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1752 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1753 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1754 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1755 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1756 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1757 #define FPCR_V (1 << 28) /* FP overflow flag */ 1758 #define FPCR_C (1 << 29) /* FP carry flag */ 1759 #define FPCR_Z (1 << 30) /* FP zero flag */ 1760 #define FPCR_N (1 << 31) /* FP negative flag */ 1761 1762 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1763 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1764 #define FPCR_LTPSIZE_LENGTH 3 1765 1766 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1767 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1768 1769 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1770 { 1771 return vfp_get_fpscr(env) & FPSR_MASK; 1772 } 1773 1774 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1775 { 1776 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1777 vfp_set_fpscr(env, new_fpscr); 1778 } 1779 1780 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1781 { 1782 return vfp_get_fpscr(env) & FPCR_MASK; 1783 } 1784 1785 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1786 { 1787 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1788 vfp_set_fpscr(env, new_fpscr); 1789 } 1790 1791 enum arm_cpu_mode { 1792 ARM_CPU_MODE_USR = 0x10, 1793 ARM_CPU_MODE_FIQ = 0x11, 1794 ARM_CPU_MODE_IRQ = 0x12, 1795 ARM_CPU_MODE_SVC = 0x13, 1796 ARM_CPU_MODE_MON = 0x16, 1797 ARM_CPU_MODE_ABT = 0x17, 1798 ARM_CPU_MODE_HYP = 0x1a, 1799 ARM_CPU_MODE_UND = 0x1b, 1800 ARM_CPU_MODE_SYS = 0x1f 1801 }; 1802 1803 /* VFP system registers. */ 1804 #define ARM_VFP_FPSID 0 1805 #define ARM_VFP_FPSCR 1 1806 #define ARM_VFP_MVFR2 5 1807 #define ARM_VFP_MVFR1 6 1808 #define ARM_VFP_MVFR0 7 1809 #define ARM_VFP_FPEXC 8 1810 #define ARM_VFP_FPINST 9 1811 #define ARM_VFP_FPINST2 10 1812 /* These ones are M-profile only */ 1813 #define ARM_VFP_FPSCR_NZCVQC 2 1814 #define ARM_VFP_VPR 12 1815 #define ARM_VFP_P0 13 1816 #define ARM_VFP_FPCXT_NS 14 1817 #define ARM_VFP_FPCXT_S 15 1818 1819 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1820 #define QEMU_VFP_FPSCR_NZCV 0xffff 1821 1822 /* iwMMXt coprocessor control registers. */ 1823 #define ARM_IWMMXT_wCID 0 1824 #define ARM_IWMMXT_wCon 1 1825 #define ARM_IWMMXT_wCSSF 2 1826 #define ARM_IWMMXT_wCASF 3 1827 #define ARM_IWMMXT_wCGR0 8 1828 #define ARM_IWMMXT_wCGR1 9 1829 #define ARM_IWMMXT_wCGR2 10 1830 #define ARM_IWMMXT_wCGR3 11 1831 1832 /* V7M CCR bits */ 1833 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1834 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1835 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1836 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1837 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1838 FIELD(V7M_CCR, STKALIGN, 9, 1) 1839 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1840 FIELD(V7M_CCR, DC, 16, 1) 1841 FIELD(V7M_CCR, IC, 17, 1) 1842 FIELD(V7M_CCR, BP, 18, 1) 1843 FIELD(V7M_CCR, LOB, 19, 1) 1844 FIELD(V7M_CCR, TRD, 20, 1) 1845 1846 /* V7M SCR bits */ 1847 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1848 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1849 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1850 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1851 1852 /* V7M AIRCR bits */ 1853 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1854 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1855 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1856 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1857 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1858 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1859 FIELD(V7M_AIRCR, PRIS, 14, 1) 1860 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1861 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1862 1863 /* V7M CFSR bits for MMFSR */ 1864 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1865 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1866 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1867 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1868 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1869 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1870 1871 /* V7M CFSR bits for BFSR */ 1872 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1873 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1874 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1875 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1876 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1877 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1878 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1879 1880 /* V7M CFSR bits for UFSR */ 1881 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1882 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1883 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1884 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1885 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1886 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1887 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1888 1889 /* V7M CFSR bit masks covering all of the subregister bits */ 1890 FIELD(V7M_CFSR, MMFSR, 0, 8) 1891 FIELD(V7M_CFSR, BFSR, 8, 8) 1892 FIELD(V7M_CFSR, UFSR, 16, 16) 1893 1894 /* V7M HFSR bits */ 1895 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1896 FIELD(V7M_HFSR, FORCED, 30, 1) 1897 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1898 1899 /* V7M DFSR bits */ 1900 FIELD(V7M_DFSR, HALTED, 0, 1) 1901 FIELD(V7M_DFSR, BKPT, 1, 1) 1902 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1903 FIELD(V7M_DFSR, VCATCH, 3, 1) 1904 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1905 1906 /* V7M SFSR bits */ 1907 FIELD(V7M_SFSR, INVEP, 0, 1) 1908 FIELD(V7M_SFSR, INVIS, 1, 1) 1909 FIELD(V7M_SFSR, INVER, 2, 1) 1910 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1911 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1912 FIELD(V7M_SFSR, LSPERR, 5, 1) 1913 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1914 FIELD(V7M_SFSR, LSERR, 7, 1) 1915 1916 /* v7M MPU_CTRL bits */ 1917 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1918 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1919 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1920 1921 /* v7M CLIDR bits */ 1922 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1923 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1924 FIELD(V7M_CLIDR, LOC, 24, 3) 1925 FIELD(V7M_CLIDR, LOUU, 27, 3) 1926 FIELD(V7M_CLIDR, ICB, 30, 2) 1927 1928 FIELD(V7M_CSSELR, IND, 0, 1) 1929 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1930 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1931 * define a mask for this and check that it doesn't permit running off 1932 * the end of the array. 1933 */ 1934 FIELD(V7M_CSSELR, INDEX, 0, 4) 1935 1936 /* v7M FPCCR bits */ 1937 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1938 FIELD(V7M_FPCCR, USER, 1, 1) 1939 FIELD(V7M_FPCCR, S, 2, 1) 1940 FIELD(V7M_FPCCR, THREAD, 3, 1) 1941 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1942 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1943 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1944 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1945 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1946 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1947 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1948 FIELD(V7M_FPCCR, RES0, 11, 15) 1949 FIELD(V7M_FPCCR, TS, 26, 1) 1950 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1951 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1952 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1953 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1954 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1955 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1956 #define R_V7M_FPCCR_BANKED_MASK \ 1957 (R_V7M_FPCCR_LSPACT_MASK | \ 1958 R_V7M_FPCCR_USER_MASK | \ 1959 R_V7M_FPCCR_THREAD_MASK | \ 1960 R_V7M_FPCCR_MMRDY_MASK | \ 1961 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1962 R_V7M_FPCCR_UFRDY_MASK | \ 1963 R_V7M_FPCCR_ASPEN_MASK) 1964 1965 /* v7M VPR bits */ 1966 FIELD(V7M_VPR, P0, 0, 16) 1967 FIELD(V7M_VPR, MASK01, 16, 4) 1968 FIELD(V7M_VPR, MASK23, 20, 4) 1969 1970 /* 1971 * System register ID fields. 1972 */ 1973 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1974 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1975 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1976 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1977 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1978 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1979 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1980 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1981 FIELD(CLIDR_EL1, LOC, 24, 3) 1982 FIELD(CLIDR_EL1, LOUU, 27, 3) 1983 FIELD(CLIDR_EL1, ICB, 30, 3) 1984 1985 /* When FEAT_CCIDX is implemented */ 1986 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1987 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1988 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1989 1990 /* When FEAT_CCIDX is not implemented */ 1991 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1992 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1993 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1994 1995 FIELD(CTR_EL0, IMINLINE, 0, 4) 1996 FIELD(CTR_EL0, L1IP, 14, 2) 1997 FIELD(CTR_EL0, DMINLINE, 16, 4) 1998 FIELD(CTR_EL0, ERG, 20, 4) 1999 FIELD(CTR_EL0, CWG, 24, 4) 2000 FIELD(CTR_EL0, IDC, 28, 1) 2001 FIELD(CTR_EL0, DIC, 29, 1) 2002 FIELD(CTR_EL0, TMINLINE, 32, 6) 2003 2004 FIELD(MIDR_EL1, REVISION, 0, 4) 2005 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2006 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2007 FIELD(MIDR_EL1, VARIANT, 20, 4) 2008 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2009 2010 FIELD(ID_ISAR0, SWAP, 0, 4) 2011 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2012 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2013 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2014 FIELD(ID_ISAR0, COPROC, 16, 4) 2015 FIELD(ID_ISAR0, DEBUG, 20, 4) 2016 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2017 2018 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2019 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2020 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2021 FIELD(ID_ISAR1, EXTEND, 12, 4) 2022 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2023 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2024 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2025 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2026 2027 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2028 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2029 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2030 FIELD(ID_ISAR2, MULT, 12, 4) 2031 FIELD(ID_ISAR2, MULTS, 16, 4) 2032 FIELD(ID_ISAR2, MULTU, 20, 4) 2033 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2034 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2035 2036 FIELD(ID_ISAR3, SATURATE, 0, 4) 2037 FIELD(ID_ISAR3, SIMD, 4, 4) 2038 FIELD(ID_ISAR3, SVC, 8, 4) 2039 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2040 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2041 FIELD(ID_ISAR3, T32COPY, 20, 4) 2042 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2043 FIELD(ID_ISAR3, T32EE, 28, 4) 2044 2045 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2046 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2047 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2048 FIELD(ID_ISAR4, SMC, 12, 4) 2049 FIELD(ID_ISAR4, BARRIER, 16, 4) 2050 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2051 FIELD(ID_ISAR4, PSR_M, 24, 4) 2052 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2053 2054 FIELD(ID_ISAR5, SEVL, 0, 4) 2055 FIELD(ID_ISAR5, AES, 4, 4) 2056 FIELD(ID_ISAR5, SHA1, 8, 4) 2057 FIELD(ID_ISAR5, SHA2, 12, 4) 2058 FIELD(ID_ISAR5, CRC32, 16, 4) 2059 FIELD(ID_ISAR5, RDM, 24, 4) 2060 FIELD(ID_ISAR5, VCMA, 28, 4) 2061 2062 FIELD(ID_ISAR6, JSCVT, 0, 4) 2063 FIELD(ID_ISAR6, DP, 4, 4) 2064 FIELD(ID_ISAR6, FHM, 8, 4) 2065 FIELD(ID_ISAR6, SB, 12, 4) 2066 FIELD(ID_ISAR6, SPECRES, 16, 4) 2067 FIELD(ID_ISAR6, BF16, 20, 4) 2068 FIELD(ID_ISAR6, I8MM, 24, 4) 2069 2070 FIELD(ID_MMFR0, VMSA, 0, 4) 2071 FIELD(ID_MMFR0, PMSA, 4, 4) 2072 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2073 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2074 FIELD(ID_MMFR0, TCM, 16, 4) 2075 FIELD(ID_MMFR0, AUXREG, 20, 4) 2076 FIELD(ID_MMFR0, FCSE, 24, 4) 2077 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2078 2079 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2080 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2081 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2082 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2083 FIELD(ID_MMFR1, L1HVD, 16, 4) 2084 FIELD(ID_MMFR1, L1UNI, 20, 4) 2085 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2086 FIELD(ID_MMFR1, BPRED, 28, 4) 2087 2088 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2089 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2090 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2091 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2092 FIELD(ID_MMFR2, UNITLB, 16, 4) 2093 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2094 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2095 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2096 2097 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2098 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2099 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2100 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2101 FIELD(ID_MMFR3, PAN, 16, 4) 2102 FIELD(ID_MMFR3, COHWALK, 20, 4) 2103 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2104 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2105 2106 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2107 FIELD(ID_MMFR4, AC2, 4, 4) 2108 FIELD(ID_MMFR4, XNX, 8, 4) 2109 FIELD(ID_MMFR4, CNP, 12, 4) 2110 FIELD(ID_MMFR4, HPDS, 16, 4) 2111 FIELD(ID_MMFR4, LSM, 20, 4) 2112 FIELD(ID_MMFR4, CCIDX, 24, 4) 2113 FIELD(ID_MMFR4, EVT, 28, 4) 2114 2115 FIELD(ID_MMFR5, ETS, 0, 4) 2116 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2117 2118 FIELD(ID_PFR0, STATE0, 0, 4) 2119 FIELD(ID_PFR0, STATE1, 4, 4) 2120 FIELD(ID_PFR0, STATE2, 8, 4) 2121 FIELD(ID_PFR0, STATE3, 12, 4) 2122 FIELD(ID_PFR0, CSV2, 16, 4) 2123 FIELD(ID_PFR0, AMU, 20, 4) 2124 FIELD(ID_PFR0, DIT, 24, 4) 2125 FIELD(ID_PFR0, RAS, 28, 4) 2126 2127 FIELD(ID_PFR1, PROGMOD, 0, 4) 2128 FIELD(ID_PFR1, SECURITY, 4, 4) 2129 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2130 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2131 FIELD(ID_PFR1, GENTIMER, 16, 4) 2132 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2133 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2134 FIELD(ID_PFR1, GIC, 28, 4) 2135 2136 FIELD(ID_PFR2, CSV3, 0, 4) 2137 FIELD(ID_PFR2, SSBS, 4, 4) 2138 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2139 2140 FIELD(ID_AA64ISAR0, AES, 4, 4) 2141 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2142 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2143 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2144 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2145 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2146 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2147 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2148 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2149 FIELD(ID_AA64ISAR0, DP, 44, 4) 2150 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2151 FIELD(ID_AA64ISAR0, TS, 52, 4) 2152 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2153 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2154 2155 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2156 FIELD(ID_AA64ISAR1, APA, 4, 4) 2157 FIELD(ID_AA64ISAR1, API, 8, 4) 2158 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2159 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2160 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2161 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2162 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2163 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2164 FIELD(ID_AA64ISAR1, SB, 36, 4) 2165 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2166 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2167 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2168 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2169 FIELD(ID_AA64ISAR1, XS, 56, 4) 2170 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2171 2172 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2173 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2174 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2175 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2176 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2177 FIELD(ID_AA64ISAR2, BC, 20, 4) 2178 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2179 2180 FIELD(ID_AA64PFR0, EL0, 0, 4) 2181 FIELD(ID_AA64PFR0, EL1, 4, 4) 2182 FIELD(ID_AA64PFR0, EL2, 8, 4) 2183 FIELD(ID_AA64PFR0, EL3, 12, 4) 2184 FIELD(ID_AA64PFR0, FP, 16, 4) 2185 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2186 FIELD(ID_AA64PFR0, GIC, 24, 4) 2187 FIELD(ID_AA64PFR0, RAS, 28, 4) 2188 FIELD(ID_AA64PFR0, SVE, 32, 4) 2189 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2190 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2191 FIELD(ID_AA64PFR0, AMU, 44, 4) 2192 FIELD(ID_AA64PFR0, DIT, 48, 4) 2193 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2194 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2195 2196 FIELD(ID_AA64PFR1, BT, 0, 4) 2197 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2198 FIELD(ID_AA64PFR1, MTE, 8, 4) 2199 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2200 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2201 FIELD(ID_AA64PFR1, SME, 24, 4) 2202 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2203 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2204 FIELD(ID_AA64PFR1, NMI, 36, 4) 2205 2206 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2207 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2208 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2209 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2210 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2211 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2212 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2213 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2214 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2215 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2216 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2217 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2218 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2219 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2220 2221 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2222 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2223 FIELD(ID_AA64MMFR1, VH, 8, 4) 2224 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2225 FIELD(ID_AA64MMFR1, LO, 16, 4) 2226 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2227 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2228 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2229 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2230 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2231 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2232 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2233 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2234 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2235 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2236 2237 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2238 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2239 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2240 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2241 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2242 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2243 FIELD(ID_AA64MMFR2, NV, 24, 4) 2244 FIELD(ID_AA64MMFR2, ST, 28, 4) 2245 FIELD(ID_AA64MMFR2, AT, 32, 4) 2246 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2247 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2248 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2249 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2250 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2251 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2252 2253 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2254 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2255 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2256 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2257 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2258 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2259 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2260 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2261 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2262 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2263 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2264 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2265 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2266 2267 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2268 FIELD(ID_AA64ZFR0, AES, 4, 4) 2269 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2270 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2271 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2272 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2273 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2274 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2275 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2276 2277 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2278 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2279 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2280 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2281 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2282 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2283 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2284 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2285 2286 FIELD(ID_DFR0, COPDBG, 0, 4) 2287 FIELD(ID_DFR0, COPSDBG, 4, 4) 2288 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2289 FIELD(ID_DFR0, COPTRC, 12, 4) 2290 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2291 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2292 FIELD(ID_DFR0, PERFMON, 24, 4) 2293 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2294 2295 FIELD(ID_DFR1, MTPMU, 0, 4) 2296 FIELD(ID_DFR1, HPMN0, 4, 4) 2297 2298 FIELD(DBGDIDR, SE_IMP, 12, 1) 2299 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2300 FIELD(DBGDIDR, VERSION, 16, 4) 2301 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2302 FIELD(DBGDIDR, BRPS, 24, 4) 2303 FIELD(DBGDIDR, WRPS, 28, 4) 2304 2305 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2306 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2307 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2308 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2309 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2310 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2311 FIELD(DBGDEVID, AUXREGS, 24, 4) 2312 FIELD(DBGDEVID, CIDMASK, 28, 4) 2313 2314 FIELD(MVFR0, SIMDREG, 0, 4) 2315 FIELD(MVFR0, FPSP, 4, 4) 2316 FIELD(MVFR0, FPDP, 8, 4) 2317 FIELD(MVFR0, FPTRAP, 12, 4) 2318 FIELD(MVFR0, FPDIVIDE, 16, 4) 2319 FIELD(MVFR0, FPSQRT, 20, 4) 2320 FIELD(MVFR0, FPSHVEC, 24, 4) 2321 FIELD(MVFR0, FPROUND, 28, 4) 2322 2323 FIELD(MVFR1, FPFTZ, 0, 4) 2324 FIELD(MVFR1, FPDNAN, 4, 4) 2325 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2326 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2327 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2328 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2329 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2330 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2331 FIELD(MVFR1, FPHP, 24, 4) 2332 FIELD(MVFR1, SIMDFMAC, 28, 4) 2333 2334 FIELD(MVFR2, SIMDMISC, 0, 4) 2335 FIELD(MVFR2, FPMISC, 4, 4) 2336 2337 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2338 2339 /* If adding a feature bit which corresponds to a Linux ELF 2340 * HWCAP bit, remember to update the feature-bit-to-hwcap 2341 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2342 */ 2343 enum arm_features { 2344 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2345 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2346 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2347 ARM_FEATURE_V6, 2348 ARM_FEATURE_V6K, 2349 ARM_FEATURE_V7, 2350 ARM_FEATURE_THUMB2, 2351 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2352 ARM_FEATURE_NEON, 2353 ARM_FEATURE_M, /* Microcontroller profile. */ 2354 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2355 ARM_FEATURE_THUMB2EE, 2356 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2357 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2358 ARM_FEATURE_V4T, 2359 ARM_FEATURE_V5, 2360 ARM_FEATURE_STRONGARM, 2361 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2362 ARM_FEATURE_GENERIC_TIMER, 2363 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2364 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2365 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2366 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2367 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2368 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2369 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2370 ARM_FEATURE_V8, 2371 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2372 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2373 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2374 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2375 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2376 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2377 ARM_FEATURE_PMU, /* has PMU support */ 2378 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2379 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2380 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2381 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2382 }; 2383 2384 static inline int arm_feature(CPUARMState *env, int feature) 2385 { 2386 return (env->features & (1ULL << feature)) != 0; 2387 } 2388 2389 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2390 2391 #if !defined(CONFIG_USER_ONLY) 2392 /* Return true if exception levels below EL3 are in secure state, 2393 * or would be following an exception return to that level. 2394 * Unlike arm_is_secure() (which is always a question about the 2395 * _current_ state of the CPU) this doesn't care about the current 2396 * EL or mode. 2397 */ 2398 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2399 { 2400 if (arm_feature(env, ARM_FEATURE_EL3)) { 2401 return !(env->cp15.scr_el3 & SCR_NS); 2402 } else { 2403 /* If EL3 is not supported then the secure state is implementation 2404 * defined, in which case QEMU defaults to non-secure. 2405 */ 2406 return false; 2407 } 2408 } 2409 2410 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2411 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2412 { 2413 if (arm_feature(env, ARM_FEATURE_EL3)) { 2414 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2415 /* CPU currently in AArch64 state and EL3 */ 2416 return true; 2417 } else if (!is_a64(env) && 2418 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2419 /* CPU currently in AArch32 state and monitor mode */ 2420 return true; 2421 } 2422 } 2423 return false; 2424 } 2425 2426 /* Return true if the processor is in secure state */ 2427 static inline bool arm_is_secure(CPUARMState *env) 2428 { 2429 if (arm_is_el3_or_mon(env)) { 2430 return true; 2431 } 2432 return arm_is_secure_below_el3(env); 2433 } 2434 2435 /* 2436 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2437 * This corresponds to the pseudocode EL2Enabled() 2438 */ 2439 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2440 { 2441 return arm_feature(env, ARM_FEATURE_EL2) 2442 && (!secure || (env->cp15.scr_el3 & SCR_EEL2)); 2443 } 2444 2445 static inline bool arm_is_el2_enabled(CPUARMState *env) 2446 { 2447 return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env)); 2448 } 2449 2450 #else 2451 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2452 { 2453 return false; 2454 } 2455 2456 static inline bool arm_is_secure(CPUARMState *env) 2457 { 2458 return false; 2459 } 2460 2461 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2462 { 2463 return false; 2464 } 2465 2466 static inline bool arm_is_el2_enabled(CPUARMState *env) 2467 { 2468 return false; 2469 } 2470 #endif 2471 2472 /** 2473 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2474 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2475 * "for all purposes other than a direct read or write access of HCR_EL2." 2476 * Not included here is HCR_RW. 2477 */ 2478 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); 2479 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2480 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2481 2482 /* Return true if the specified exception level is running in AArch64 state. */ 2483 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2484 { 2485 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2486 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2487 */ 2488 assert(el >= 1 && el <= 3); 2489 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2490 2491 /* The highest exception level is always at the maximum supported 2492 * register width, and then lower levels have a register width controlled 2493 * by bits in the SCR or HCR registers. 2494 */ 2495 if (el == 3) { 2496 return aa64; 2497 } 2498 2499 if (arm_feature(env, ARM_FEATURE_EL3) && 2500 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2501 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2502 } 2503 2504 if (el == 2) { 2505 return aa64; 2506 } 2507 2508 if (arm_is_el2_enabled(env)) { 2509 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2510 } 2511 2512 return aa64; 2513 } 2514 2515 /* Function for determing whether guest cp register reads and writes should 2516 * access the secure or non-secure bank of a cp register. When EL3 is 2517 * operating in AArch32 state, the NS-bit determines whether the secure 2518 * instance of a cp register should be used. When EL3 is AArch64 (or if 2519 * it doesn't exist at all) then there is no register banking, and all 2520 * accesses are to the non-secure version. 2521 */ 2522 static inline bool access_secure_reg(CPUARMState *env) 2523 { 2524 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2525 !arm_el_is_aa64(env, 3) && 2526 !(env->cp15.scr_el3 & SCR_NS)); 2527 2528 return ret; 2529 } 2530 2531 /* Macros for accessing a specified CP register bank */ 2532 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2533 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2534 2535 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2536 do { \ 2537 if (_secure) { \ 2538 (_env)->cp15._regname##_s = (_val); \ 2539 } else { \ 2540 (_env)->cp15._regname##_ns = (_val); \ 2541 } \ 2542 } while (0) 2543 2544 /* Macros for automatically accessing a specific CP register bank depending on 2545 * the current secure state of the system. These macros are not intended for 2546 * supporting instruction translation reads/writes as these are dependent 2547 * solely on the SCR.NS bit and not the mode. 2548 */ 2549 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2550 A32_BANKED_REG_GET((_env), _regname, \ 2551 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2552 2553 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2554 A32_BANKED_REG_SET((_env), _regname, \ 2555 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2556 (_val)) 2557 2558 void arm_cpu_list(void); 2559 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2560 uint32_t cur_el, bool secure); 2561 2562 /* Interface between CPU and Interrupt controller. */ 2563 #ifndef CONFIG_USER_ONLY 2564 bool armv7m_nvic_can_take_pending_exception(NVICState *s); 2565 #else 2566 static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) 2567 { 2568 return true; 2569 } 2570 #endif 2571 /** 2572 * armv7m_nvic_set_pending: mark the specified exception as pending 2573 * @s: the NVIC 2574 * @irq: the exception number to mark pending 2575 * @secure: false for non-banked exceptions or for the nonsecure 2576 * version of a banked exception, true for the secure version of a banked 2577 * exception. 2578 * 2579 * Marks the specified exception as pending. Note that we will assert() 2580 * if @secure is true and @irq does not specify one of the fixed set 2581 * of architecturally banked exceptions. 2582 */ 2583 void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); 2584 /** 2585 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2586 * @s: the NVIC 2587 * @irq: the exception number to mark pending 2588 * @secure: false for non-banked exceptions or for the nonsecure 2589 * version of a banked exception, true for the secure version of a banked 2590 * exception. 2591 * 2592 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2593 * exceptions (exceptions generated in the course of trying to take 2594 * a different exception). 2595 */ 2596 void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); 2597 /** 2598 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2599 * @s: the NVIC 2600 * @irq: the exception number to mark pending 2601 * @secure: false for non-banked exceptions or for the nonsecure 2602 * version of a banked exception, true for the secure version of a banked 2603 * exception. 2604 * 2605 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2606 * generated in the course of lazy stacking of FP registers. 2607 */ 2608 void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); 2609 /** 2610 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2611 * exception, and whether it targets Secure state 2612 * @s: the NVIC 2613 * @pirq: set to pending exception number 2614 * @ptargets_secure: set to whether pending exception targets Secure 2615 * 2616 * This function writes the number of the highest priority pending 2617 * exception (the one which would be made active by 2618 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2619 * to true if the current highest priority pending exception should 2620 * be taken to Secure state, false for NS. 2621 */ 2622 void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, 2623 bool *ptargets_secure); 2624 /** 2625 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2626 * @s: the NVIC 2627 * 2628 * Move the current highest priority pending exception from the pending 2629 * state to the active state, and update v7m.exception to indicate that 2630 * it is the exception currently being handled. 2631 */ 2632 void armv7m_nvic_acknowledge_irq(NVICState *s); 2633 /** 2634 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2635 * @s: the NVIC 2636 * @irq: the exception number to complete 2637 * @secure: true if this exception was secure 2638 * 2639 * Returns: -1 if the irq was not active 2640 * 1 if completing this irq brought us back to base (no active irqs) 2641 * 0 if there is still an irq active after this one was completed 2642 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2643 */ 2644 int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); 2645 /** 2646 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2647 * @s: the NVIC 2648 * @irq: the exception number to mark pending 2649 * @secure: false for non-banked exceptions or for the nonsecure 2650 * version of a banked exception, true for the secure version of a banked 2651 * exception. 2652 * 2653 * Return whether an exception is "ready", i.e. whether the exception is 2654 * enabled and is configured at a priority which would allow it to 2655 * interrupt the current execution priority. This controls whether the 2656 * RDY bit for it in the FPCCR is set. 2657 */ 2658 bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); 2659 /** 2660 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2661 * @s: the NVIC 2662 * 2663 * Returns: the raw execution priority as defined by the v8M architecture. 2664 * This is the execution priority minus the effects of AIRCR.PRIS, 2665 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2666 * (v8M ARM ARM I_PKLD.) 2667 */ 2668 int armv7m_nvic_raw_execution_priority(NVICState *s); 2669 /** 2670 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2671 * priority is negative for the specified security state. 2672 * @s: the NVIC 2673 * @secure: the security state to test 2674 * This corresponds to the pseudocode IsReqExecPriNeg(). 2675 */ 2676 #ifndef CONFIG_USER_ONLY 2677 bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); 2678 #else 2679 static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) 2680 { 2681 return false; 2682 } 2683 #endif 2684 2685 /* Interface for defining coprocessor registers. 2686 * Registers are defined in tables of arm_cp_reginfo structs 2687 * which are passed to define_arm_cp_regs(). 2688 */ 2689 2690 /* When looking up a coprocessor register we look for it 2691 * via an integer which encodes all of: 2692 * coprocessor number 2693 * Crn, Crm, opc1, opc2 fields 2694 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2695 * or via MRRC/MCRR?) 2696 * non-secure/secure bank (AArch32 only) 2697 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2698 * (In this case crn and opc2 should be zero.) 2699 * For AArch64, there is no 32/64 bit size distinction; 2700 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2701 * and 4 bit CRn and CRm. The encoding patterns are chosen 2702 * to be easy to convert to and from the KVM encodings, and also 2703 * so that the hashtable can contain both AArch32 and AArch64 2704 * registers (to allow for interprocessing where we might run 2705 * 32 bit code on a 64 bit core). 2706 */ 2707 /* This bit is private to our hashtable cpreg; in KVM register 2708 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2709 * in the upper bits of the 64 bit ID. 2710 */ 2711 #define CP_REG_AA64_SHIFT 28 2712 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2713 2714 /* To enable banking of coprocessor registers depending on ns-bit we 2715 * add a bit to distinguish between secure and non-secure cpregs in the 2716 * hashtable. 2717 */ 2718 #define CP_REG_NS_SHIFT 29 2719 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2720 2721 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2722 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2723 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2724 2725 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2726 (CP_REG_AA64_MASK | \ 2727 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2728 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2729 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2730 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2731 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2732 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2733 2734 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2735 * version used as a key for the coprocessor register hashtable 2736 */ 2737 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2738 { 2739 uint32_t cpregid = kvmid; 2740 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2741 cpregid |= CP_REG_AA64_MASK; 2742 } else { 2743 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2744 cpregid |= (1 << 15); 2745 } 2746 2747 /* KVM is always non-secure so add the NS flag on AArch32 register 2748 * entries. 2749 */ 2750 cpregid |= 1 << CP_REG_NS_SHIFT; 2751 } 2752 return cpregid; 2753 } 2754 2755 /* Convert a truncated 32 bit hashtable key into the full 2756 * 64 bit KVM register ID. 2757 */ 2758 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2759 { 2760 uint64_t kvmid; 2761 2762 if (cpregid & CP_REG_AA64_MASK) { 2763 kvmid = cpregid & ~CP_REG_AA64_MASK; 2764 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2765 } else { 2766 kvmid = cpregid & ~(1 << 15); 2767 if (cpregid & (1 << 15)) { 2768 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2769 } else { 2770 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2771 } 2772 } 2773 return kvmid; 2774 } 2775 2776 /* Return the highest implemented Exception Level */ 2777 static inline int arm_highest_el(CPUARMState *env) 2778 { 2779 if (arm_feature(env, ARM_FEATURE_EL3)) { 2780 return 3; 2781 } 2782 if (arm_feature(env, ARM_FEATURE_EL2)) { 2783 return 2; 2784 } 2785 return 1; 2786 } 2787 2788 /* Return true if a v7M CPU is in Handler mode */ 2789 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2790 { 2791 return env->v7m.exception != 0; 2792 } 2793 2794 /* Return the current Exception Level (as per ARMv8; note that this differs 2795 * from the ARMv7 Privilege Level). 2796 */ 2797 static inline int arm_current_el(CPUARMState *env) 2798 { 2799 if (arm_feature(env, ARM_FEATURE_M)) { 2800 return arm_v7m_is_handler_mode(env) || 2801 !(env->v7m.control[env->v7m.secure] & 1); 2802 } 2803 2804 if (is_a64(env)) { 2805 return extract32(env->pstate, 2, 2); 2806 } 2807 2808 switch (env->uncached_cpsr & 0x1f) { 2809 case ARM_CPU_MODE_USR: 2810 return 0; 2811 case ARM_CPU_MODE_HYP: 2812 return 2; 2813 case ARM_CPU_MODE_MON: 2814 return 3; 2815 default: 2816 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2817 /* If EL3 is 32-bit then all secure privileged modes run in 2818 * EL3 2819 */ 2820 return 3; 2821 } 2822 2823 return 1; 2824 } 2825 } 2826 2827 /** 2828 * write_list_to_cpustate 2829 * @cpu: ARMCPU 2830 * 2831 * For each register listed in the ARMCPU cpreg_indexes list, write 2832 * its value from the cpreg_values list into the ARMCPUState structure. 2833 * This updates TCG's working data structures from KVM data or 2834 * from incoming migration state. 2835 * 2836 * Returns: true if all register values were updated correctly, 2837 * false if some register was unknown or could not be written. 2838 * Note that we do not stop early on failure -- we will attempt 2839 * writing all registers in the list. 2840 */ 2841 bool write_list_to_cpustate(ARMCPU *cpu); 2842 2843 /** 2844 * write_cpustate_to_list: 2845 * @cpu: ARMCPU 2846 * @kvm_sync: true if this is for syncing back to KVM 2847 * 2848 * For each register listed in the ARMCPU cpreg_indexes list, write 2849 * its value from the ARMCPUState structure into the cpreg_values list. 2850 * This is used to copy info from TCG's working data structures into 2851 * KVM or for outbound migration. 2852 * 2853 * @kvm_sync is true if we are doing this in order to sync the 2854 * register state back to KVM. In this case we will only update 2855 * values in the list if the previous list->cpustate sync actually 2856 * successfully wrote the CPU state. Otherwise we will keep the value 2857 * that is in the list. 2858 * 2859 * Returns: true if all register values were read correctly, 2860 * false if some register was unknown or could not be read. 2861 * Note that we do not stop early on failure -- we will attempt 2862 * reading all registers in the list. 2863 */ 2864 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2865 2866 #define ARM_CPUID_TI915T 0x54029152 2867 #define ARM_CPUID_TI925T 0x54029252 2868 2869 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2870 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2871 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2872 2873 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2874 2875 #define cpu_list arm_cpu_list 2876 2877 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2878 * 2879 * If EL3 is 64-bit: 2880 * + NonSecure EL1 & 0 stage 1 2881 * + NonSecure EL1 & 0 stage 2 2882 * + NonSecure EL2 2883 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2884 * + Secure EL1 & 0 2885 * + Secure EL3 2886 * If EL3 is 32-bit: 2887 * + NonSecure PL1 & 0 stage 1 2888 * + NonSecure PL1 & 0 stage 2 2889 * + NonSecure PL2 2890 * + Secure PL0 2891 * + Secure PL1 2892 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2893 * 2894 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2895 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2896 * because they may differ in access permissions even if the VA->PA map is 2897 * the same 2898 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2899 * translation, which means that we have one mmu_idx that deals with two 2900 * concatenated translation regimes [this sort of combined s1+2 TLB is 2901 * architecturally permitted] 2902 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2903 * handling via the TLB. The only way to do a stage 1 translation without 2904 * the immediate stage 2 translation is via the ATS or AT system insns, 2905 * which can be slow-pathed and always do a page table walk. 2906 * The only use of stage 2 translations is either as part of an s1+2 2907 * lookup or when loading the descriptors during a stage 1 page table walk, 2908 * and in both those cases we don't use the TLB. 2909 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2910 * translation regimes, because they map reasonably well to each other 2911 * and they can't both be active at the same time. 2912 * 5. we want to be able to use the TLB for accesses done as part of a 2913 * stage1 page table walk, rather than having to walk the stage2 page 2914 * table over and over. 2915 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2916 * Never (PAN) bit within PSTATE. 2917 * 7. we fold together the secure and non-secure regimes for A-profile, 2918 * because there are no banked system registers for aarch64, so the 2919 * process of switching between secure and non-secure is 2920 * already heavyweight. 2921 * 2922 * This gives us the following list of cases: 2923 * 2924 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2925 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2926 * EL1 EL1&0 stage 1+2 +PAN 2927 * EL0 EL2&0 2928 * EL2 EL2&0 2929 * EL2 EL2&0 +PAN 2930 * EL2 (aka NS PL2) 2931 * EL3 (aka S PL1) 2932 * Physical (NS & S) 2933 * Stage2 (NS & S) 2934 * 2935 * for a total of 12 different mmu_idx. 2936 * 2937 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2938 * as A profile. They only need to distinguish EL0 and EL1 (and 2939 * EL2 if we ever model a Cortex-R52). 2940 * 2941 * M profile CPUs are rather different as they do not have a true MMU. 2942 * They have the following different MMU indexes: 2943 * User 2944 * Privileged 2945 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2946 * Privileged, execution priority negative (ditto) 2947 * If the CPU supports the v8M Security Extension then there are also: 2948 * Secure User 2949 * Secure Privileged 2950 * Secure User, execution priority negative 2951 * Secure Privileged, execution priority negative 2952 * 2953 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2954 * are not quite the same -- different CPU types (most notably M profile 2955 * vs A/R profile) would like to use MMU indexes with different semantics, 2956 * but since we don't ever need to use all of those in a single CPU we 2957 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2958 * modes + total number of M profile MMU modes". The lower bits of 2959 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2960 * the same for any particular CPU. 2961 * Variables of type ARMMUIdx are always full values, and the core 2962 * index values are in variables of type 'int'. 2963 * 2964 * Our enumeration includes at the end some entries which are not "true" 2965 * mmu_idx values in that they don't have corresponding TLBs and are only 2966 * valid for doing slow path page table walks. 2967 * 2968 * The constant names here are patterned after the general style of the names 2969 * of the AT/ATS operations. 2970 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2971 * For M profile we arrange them to have a bit for priv, a bit for negpri 2972 * and a bit for secure. 2973 */ 2974 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2975 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2976 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2977 2978 /* Meanings of the bits for M profile mmu idx values */ 2979 #define ARM_MMU_IDX_M_PRIV 0x1 2980 #define ARM_MMU_IDX_M_NEGPRI 0x2 2981 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2982 2983 #define ARM_MMU_IDX_TYPE_MASK \ 2984 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2985 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2986 2987 typedef enum ARMMMUIdx { 2988 /* 2989 * A-profile. 2990 */ 2991 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2992 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2993 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2994 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2995 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2996 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2997 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2998 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2999 3000 /* TLBs with 1-1 mapping to the physical address spaces. */ 3001 ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A, 3002 ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A, 3003 3004 /* 3005 * Used for second stage of an S12 page table walk, or for descriptor 3006 * loads during first stage of an S1 page table walk. Note that both 3007 * are in use simultaneously for SecureEL2: the security state for 3008 * the S2 ptw is selected by the NS bit from the S1 ptw. 3009 */ 3010 ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A, 3011 ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A, 3012 3013 /* 3014 * These are not allocated TLBs and are used only for AT system 3015 * instructions or for the first stage of an S12 page table walk. 3016 */ 3017 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 3018 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 3019 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 3020 3021 /* 3022 * M-profile. 3023 */ 3024 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 3025 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 3026 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 3027 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 3028 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 3029 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 3030 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 3031 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 3032 } ARMMMUIdx; 3033 3034 /* 3035 * Bit macros for the core-mmu-index values for each index, 3036 * for use when calling tlb_flush_by_mmuidx() and friends. 3037 */ 3038 #define TO_CORE_BIT(NAME) \ 3039 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 3040 3041 typedef enum ARMMMUIdxBit { 3042 TO_CORE_BIT(E10_0), 3043 TO_CORE_BIT(E20_0), 3044 TO_CORE_BIT(E10_1), 3045 TO_CORE_BIT(E10_1_PAN), 3046 TO_CORE_BIT(E2), 3047 TO_CORE_BIT(E20_2), 3048 TO_CORE_BIT(E20_2_PAN), 3049 TO_CORE_BIT(E3), 3050 TO_CORE_BIT(Stage2), 3051 TO_CORE_BIT(Stage2_S), 3052 3053 TO_CORE_BIT(MUser), 3054 TO_CORE_BIT(MPriv), 3055 TO_CORE_BIT(MUserNegPri), 3056 TO_CORE_BIT(MPrivNegPri), 3057 TO_CORE_BIT(MSUser), 3058 TO_CORE_BIT(MSPriv), 3059 TO_CORE_BIT(MSUserNegPri), 3060 TO_CORE_BIT(MSPrivNegPri), 3061 } ARMMMUIdxBit; 3062 3063 #undef TO_CORE_BIT 3064 3065 #define MMU_USER_IDX 0 3066 3067 /* Indexes used when registering address spaces with cpu_address_space_init */ 3068 typedef enum ARMASIdx { 3069 ARMASIdx_NS = 0, 3070 ARMASIdx_S = 1, 3071 ARMASIdx_TagNS = 2, 3072 ARMASIdx_TagS = 3, 3073 } ARMASIdx; 3074 3075 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3076 { 3077 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3078 * CSSELR is RAZ/WI. 3079 */ 3080 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3081 } 3082 3083 static inline bool arm_sctlr_b(CPUARMState *env) 3084 { 3085 return 3086 /* We need not implement SCTLR.ITD in user-mode emulation, so 3087 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3088 * This lets people run BE32 binaries with "-cpu any". 3089 */ 3090 #ifndef CONFIG_USER_ONLY 3091 !arm_feature(env, ARM_FEATURE_V7) && 3092 #endif 3093 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3094 } 3095 3096 uint64_t arm_sctlr(CPUARMState *env, int el); 3097 3098 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3099 bool sctlr_b) 3100 { 3101 #ifdef CONFIG_USER_ONLY 3102 /* 3103 * In system mode, BE32 is modelled in line with the 3104 * architecture (as word-invariant big-endianness), where loads 3105 * and stores are done little endian but from addresses which 3106 * are adjusted by XORing with the appropriate constant. So the 3107 * endianness to use for the raw data access is not affected by 3108 * SCTLR.B. 3109 * In user mode, however, we model BE32 as byte-invariant 3110 * big-endianness (because user-only code cannot tell the 3111 * difference), and so we need to use a data access endianness 3112 * that depends on SCTLR.B. 3113 */ 3114 if (sctlr_b) { 3115 return true; 3116 } 3117 #endif 3118 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3119 return env->uncached_cpsr & CPSR_E; 3120 } 3121 3122 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3123 { 3124 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3125 } 3126 3127 /* Return true if the processor is in big-endian mode. */ 3128 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3129 { 3130 if (!is_a64(env)) { 3131 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3132 } else { 3133 int cur_el = arm_current_el(env); 3134 uint64_t sctlr = arm_sctlr(env, cur_el); 3135 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3136 } 3137 } 3138 3139 #include "exec/cpu-all.h" 3140 3141 /* 3142 * We have more than 32-bits worth of state per TB, so we split the data 3143 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3144 * We collect these two parts in CPUARMTBFlags where they are named 3145 * flags and flags2 respectively. 3146 * 3147 * The flags that are shared between all execution modes, TBFLAG_ANY, 3148 * are stored in flags. The flags that are specific to a given mode 3149 * are stores in flags2. Since cs_base is sized on the configured 3150 * address size, flags2 always has 64-bits for A64, and a minimum of 3151 * 32-bits for A32 and M32. 3152 * 3153 * The bits for 32-bit A-profile and M-profile partially overlap: 3154 * 3155 * 31 23 11 10 0 3156 * +-------------+----------+----------------+ 3157 * | | | TBFLAG_A32 | 3158 * | TBFLAG_AM32 | +-----+----------+ 3159 * | | |TBFLAG_M32| 3160 * +-------------+----------------+----------+ 3161 * 31 23 6 5 0 3162 * 3163 * Unless otherwise noted, these bits are cached in env->hflags. 3164 */ 3165 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3166 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3167 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3168 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3169 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3170 /* Target EL if we take a floating-point-disabled exception */ 3171 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3172 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3173 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3174 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3175 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3176 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3177 3178 /* 3179 * Bit usage when in AArch32 state, both A- and M-profile. 3180 */ 3181 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3182 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3183 3184 /* 3185 * Bit usage when in AArch32 state, for A-profile only. 3186 */ 3187 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3188 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3189 /* 3190 * We store the bottom two bits of the CPAR as TB flags and handle 3191 * checks on the other bits at runtime. This shares the same bits as 3192 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3193 * Not cached, because VECLEN+VECSTRIDE are not cached. 3194 */ 3195 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3196 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3197 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3198 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3199 /* 3200 * Indicates whether cp register reads and writes by guest code should access 3201 * the secure or nonsecure bank of banked registers; note that this is not 3202 * the same thing as the current security state of the processor! 3203 */ 3204 FIELD(TBFLAG_A32, NS, 10, 1) 3205 /* 3206 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3207 * This requires an SME trap from AArch32 mode when using NEON. 3208 */ 3209 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3210 3211 /* 3212 * Bit usage when in AArch32 state, for M-profile only. 3213 */ 3214 /* Handler (ie not Thread) mode */ 3215 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3216 /* Whether we should generate stack-limit checks */ 3217 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3218 /* Set if FPCCR.LSPACT is set */ 3219 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3220 /* Set if we must create a new FP context */ 3221 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3222 /* Set if FPCCR.S does not match current security state */ 3223 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3224 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3225 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3226 /* Set if in secure mode */ 3227 FIELD(TBFLAG_M32, SECURE, 6, 1) 3228 3229 /* 3230 * Bit usage when in AArch64 state 3231 */ 3232 FIELD(TBFLAG_A64, TBII, 0, 2) 3233 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3234 /* The current vector length, either NVL or SVL. */ 3235 FIELD(TBFLAG_A64, VL, 4, 4) 3236 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3237 FIELD(TBFLAG_A64, BT, 9, 1) 3238 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3239 FIELD(TBFLAG_A64, TBID, 12, 2) 3240 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3241 FIELD(TBFLAG_A64, ATA, 15, 1) 3242 FIELD(TBFLAG_A64, TCMA, 16, 2) 3243 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3244 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3245 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3246 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3247 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3248 FIELD(TBFLAG_A64, SVL, 24, 4) 3249 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3250 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3251 FIELD(TBFLAG_A64, FGT_ERET, 29, 1) 3252 3253 /* 3254 * Helpers for using the above. 3255 */ 3256 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3257 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3258 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3259 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3260 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3261 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3262 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3263 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3264 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3265 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3266 3267 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3268 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3269 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3270 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3271 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3272 3273 /** 3274 * cpu_mmu_index: 3275 * @env: The cpu environment 3276 * @ifetch: True for code access, false for data access. 3277 * 3278 * Return the core mmu index for the current translation regime. 3279 * This function is used by generic TCG code paths. 3280 */ 3281 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3282 { 3283 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3284 } 3285 3286 /** 3287 * sve_vq 3288 * @env: the cpu context 3289 * 3290 * Return the VL cached within env->hflags, in units of quadwords. 3291 */ 3292 static inline int sve_vq(CPUARMState *env) 3293 { 3294 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3295 } 3296 3297 /** 3298 * sme_vq 3299 * @env: the cpu context 3300 * 3301 * Return the SVL cached within env->hflags, in units of quadwords. 3302 */ 3303 static inline int sme_vq(CPUARMState *env) 3304 { 3305 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3306 } 3307 3308 static inline bool bswap_code(bool sctlr_b) 3309 { 3310 #ifdef CONFIG_USER_ONLY 3311 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3312 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3313 * would also end up as a mixed-endian mode with BE code, LE data. 3314 */ 3315 return 3316 #if TARGET_BIG_ENDIAN 3317 1 ^ 3318 #endif 3319 sctlr_b; 3320 #else 3321 /* All code access in ARM is little endian, and there are no loaders 3322 * doing swaps that need to be reversed 3323 */ 3324 return 0; 3325 #endif 3326 } 3327 3328 #ifdef CONFIG_USER_ONLY 3329 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3330 { 3331 return 3332 #if TARGET_BIG_ENDIAN 3333 1 ^ 3334 #endif 3335 arm_cpu_data_is_big_endian(env); 3336 } 3337 #endif 3338 3339 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3340 target_ulong *cs_base, uint32_t *flags); 3341 3342 enum { 3343 QEMU_PSCI_CONDUIT_DISABLED = 0, 3344 QEMU_PSCI_CONDUIT_SMC = 1, 3345 QEMU_PSCI_CONDUIT_HVC = 2, 3346 }; 3347 3348 #ifndef CONFIG_USER_ONLY 3349 /* Return the address space index to use for a memory access */ 3350 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3351 { 3352 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3353 } 3354 3355 /* Return the AddressSpace to use for a memory access 3356 * (which depends on whether the access is S or NS, and whether 3357 * the board gave us a separate AddressSpace for S accesses). 3358 */ 3359 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3360 { 3361 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3362 } 3363 #endif 3364 3365 /** 3366 * arm_register_pre_el_change_hook: 3367 * Register a hook function which will be called immediately before this 3368 * CPU changes exception level or mode. The hook function will be 3369 * passed a pointer to the ARMCPU and the opaque data pointer passed 3370 * to this function when the hook was registered. 3371 * 3372 * Note that if a pre-change hook is called, any registered post-change hooks 3373 * are guaranteed to subsequently be called. 3374 */ 3375 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3376 void *opaque); 3377 /** 3378 * arm_register_el_change_hook: 3379 * Register a hook function which will be called immediately after this 3380 * CPU changes exception level or mode. The hook function will be 3381 * passed a pointer to the ARMCPU and the opaque data pointer passed 3382 * to this function when the hook was registered. 3383 * 3384 * Note that any registered hooks registered here are guaranteed to be called 3385 * if pre-change hooks have been. 3386 */ 3387 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3388 *opaque); 3389 3390 /** 3391 * arm_rebuild_hflags: 3392 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3393 */ 3394 void arm_rebuild_hflags(CPUARMState *env); 3395 3396 /** 3397 * aa32_vfp_dreg: 3398 * Return a pointer to the Dn register within env in 32-bit mode. 3399 */ 3400 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3401 { 3402 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3403 } 3404 3405 /** 3406 * aa32_vfp_qreg: 3407 * Return a pointer to the Qn register within env in 32-bit mode. 3408 */ 3409 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3410 { 3411 return &env->vfp.zregs[regno].d[0]; 3412 } 3413 3414 /** 3415 * aa64_vfp_qreg: 3416 * Return a pointer to the Qn register within env in 64-bit mode. 3417 */ 3418 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3419 { 3420 return &env->vfp.zregs[regno].d[0]; 3421 } 3422 3423 /* Shared between translate-sve.c and sve_helper.c. */ 3424 extern const uint64_t pred_esz_masks[5]; 3425 3426 /* 3427 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3428 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3429 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3430 */ 3431 #define PAGE_BTI PAGE_TARGET_1 3432 #define PAGE_MTE PAGE_TARGET_2 3433 #define PAGE_TARGET_STICKY PAGE_MTE 3434 3435 /* We associate one allocation tag per 16 bytes, the minimum. */ 3436 #define LOG2_TAG_GRANULE 4 3437 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3438 3439 #ifdef CONFIG_USER_ONLY 3440 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3441 #endif 3442 3443 #ifdef TARGET_TAGGED_ADDRESSES 3444 /** 3445 * cpu_untagged_addr: 3446 * @cs: CPU context 3447 * @x: tagged address 3448 * 3449 * Remove any address tag from @x. This is explicitly related to the 3450 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3451 * 3452 * There should be a better place to put this, but we need this in 3453 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3454 */ 3455 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3456 { 3457 ARMCPU *cpu = ARM_CPU(cs); 3458 if (cpu->env.tagged_addr_enable) { 3459 /* 3460 * TBI is enabled for userspace but not kernelspace addresses. 3461 * Only clear the tag if bit 55 is clear. 3462 */ 3463 x &= sextract64(x, 0, 56); 3464 } 3465 return x; 3466 } 3467 #endif 3468 3469 /* 3470 * Naming convention for isar_feature functions: 3471 * Functions which test 32-bit ID registers should have _aa32_ in 3472 * their name. Functions which test 64-bit ID registers should have 3473 * _aa64_ in their name. These must only be used in code where we 3474 * know for certain that the CPU has AArch32 or AArch64 respectively 3475 * or where the correct answer for a CPU which doesn't implement that 3476 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3477 * system registers that are specific to that CPU state, for "should 3478 * we let this system register bit be set" tests where the 32-bit 3479 * flavour of the register doesn't have the bit, and so on). 3480 * Functions which simply ask "does this feature exist at all" have 3481 * _any_ in their name, and always return the logical OR of the _aa64_ 3482 * and the _aa32_ function. 3483 */ 3484 3485 /* 3486 * 32-bit feature tests via id registers. 3487 */ 3488 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3489 { 3490 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3491 } 3492 3493 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3494 { 3495 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3496 } 3497 3498 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3499 { 3500 /* (M-profile) low-overhead loops and branch future */ 3501 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3502 } 3503 3504 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3505 { 3506 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3507 } 3508 3509 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3510 { 3511 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3512 } 3513 3514 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3515 { 3516 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3517 } 3518 3519 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3520 { 3521 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3522 } 3523 3524 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3525 { 3526 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3527 } 3528 3529 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3530 { 3531 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3532 } 3533 3534 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3535 { 3536 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3537 } 3538 3539 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3540 { 3541 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3542 } 3543 3544 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3545 { 3546 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3547 } 3548 3549 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3550 { 3551 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3552 } 3553 3554 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3555 { 3556 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3557 } 3558 3559 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3560 { 3561 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3562 } 3563 3564 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3565 { 3566 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3567 } 3568 3569 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3570 { 3571 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3572 } 3573 3574 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3575 { 3576 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3577 } 3578 3579 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3580 { 3581 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3582 } 3583 3584 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3585 { 3586 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3587 } 3588 3589 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3590 { 3591 /* 3592 * Return true if M-profile state handling insns 3593 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3594 */ 3595 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3596 } 3597 3598 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3599 { 3600 /* Sadly this is encoded differently for A-profile and M-profile */ 3601 if (isar_feature_aa32_mprofile(id)) { 3602 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3603 } else { 3604 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3605 } 3606 } 3607 3608 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3609 { 3610 /* 3611 * Return true if MVE is supported (either integer or floating point). 3612 * We must check for M-profile as the MVFR1 field means something 3613 * else for A-profile. 3614 */ 3615 return isar_feature_aa32_mprofile(id) && 3616 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3617 } 3618 3619 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3620 { 3621 /* 3622 * Return true if MVE is supported (either integer or floating point). 3623 * We must check for M-profile as the MVFR1 field means something 3624 * else for A-profile. 3625 */ 3626 return isar_feature_aa32_mprofile(id) && 3627 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3628 } 3629 3630 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3631 { 3632 /* 3633 * Return true if either VFP or SIMD is implemented. 3634 * In this case, a minimum of VFP w/ D0-D15. 3635 */ 3636 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3637 } 3638 3639 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3640 { 3641 /* Return true if D16-D31 are implemented */ 3642 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3643 } 3644 3645 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3646 { 3647 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3648 } 3649 3650 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3651 { 3652 /* Return true if CPU supports single precision floating point, VFPv2 */ 3653 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3654 } 3655 3656 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3657 { 3658 /* Return true if CPU supports single precision floating point, VFPv3 */ 3659 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3660 } 3661 3662 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3663 { 3664 /* Return true if CPU supports double precision floating point, VFPv2 */ 3665 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3666 } 3667 3668 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3669 { 3670 /* Return true if CPU supports double precision floating point, VFPv3 */ 3671 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3672 } 3673 3674 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3675 { 3676 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3677 } 3678 3679 /* 3680 * We always set the FP and SIMD FP16 fields to indicate identical 3681 * levels of support (assuming SIMD is implemented at all), so 3682 * we only need one set of accessors. 3683 */ 3684 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3685 { 3686 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3687 } 3688 3689 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3690 { 3691 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3692 } 3693 3694 /* 3695 * Note that this ID register field covers both VFP and Neon FMAC, 3696 * so should usually be tested in combination with some other 3697 * check that confirms the presence of whichever of VFP or Neon is 3698 * relevant, to avoid accidentally enabling a Neon feature on 3699 * a VFP-no-Neon core or vice-versa. 3700 */ 3701 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3702 { 3703 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3704 } 3705 3706 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3707 { 3708 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3709 } 3710 3711 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3712 { 3713 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3714 } 3715 3716 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3717 { 3718 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3719 } 3720 3721 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3722 { 3723 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3724 } 3725 3726 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3727 { 3728 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3729 } 3730 3731 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3732 { 3733 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3734 } 3735 3736 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3737 { 3738 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3739 } 3740 3741 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) 3742 { 3743 /* 0xf means "non-standard IMPDEF PMU" */ 3744 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3745 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3746 } 3747 3748 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) 3749 { 3750 /* 0xf means "non-standard IMPDEF PMU" */ 3751 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3752 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3753 } 3754 3755 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) 3756 { 3757 /* 0xf means "non-standard IMPDEF PMU" */ 3758 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 && 3759 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3760 } 3761 3762 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3763 { 3764 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3765 } 3766 3767 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3768 { 3769 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3770 } 3771 3772 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3773 { 3774 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3775 } 3776 3777 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3778 { 3779 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3780 } 3781 3782 static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) 3783 { 3784 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1; 3785 } 3786 3787 static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) 3788 { 3789 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2; 3790 } 3791 3792 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3793 { 3794 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3795 } 3796 3797 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3798 { 3799 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3800 } 3801 3802 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) 3803 { 3804 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5; 3805 } 3806 3807 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3808 { 3809 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3810 } 3811 3812 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) 3813 { 3814 return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0; 3815 } 3816 3817 /* 3818 * 64-bit feature tests via id registers. 3819 */ 3820 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3821 { 3822 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3823 } 3824 3825 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3826 { 3827 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3828 } 3829 3830 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3831 { 3832 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3833 } 3834 3835 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3836 { 3837 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3838 } 3839 3840 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3841 { 3842 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3843 } 3844 3845 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3846 { 3847 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3848 } 3849 3850 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3851 { 3852 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3853 } 3854 3855 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3856 { 3857 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3858 } 3859 3860 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3861 { 3862 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3863 } 3864 3865 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3866 { 3867 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3868 } 3869 3870 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3871 { 3872 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3873 } 3874 3875 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3876 { 3877 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3878 } 3879 3880 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3881 { 3882 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3883 } 3884 3885 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3886 { 3887 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3888 } 3889 3890 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3891 { 3892 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3893 } 3894 3895 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3896 { 3897 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3898 } 3899 3900 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3901 { 3902 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3903 } 3904 3905 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3906 { 3907 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3908 } 3909 3910 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3911 { 3912 /* 3913 * Return true if any form of pauth is enabled, as this 3914 * predicate controls migration of the 128-bit keys. 3915 */ 3916 return (id->id_aa64isar1 & 3917 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3918 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3919 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3920 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3921 } 3922 3923 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3924 { 3925 /* 3926 * Return true if pauth is enabled with the architected QARMA algorithm. 3927 * QEMU will always set APA+GPA to the same value. 3928 */ 3929 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3930 } 3931 3932 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3933 { 3934 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3935 } 3936 3937 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3938 { 3939 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3940 } 3941 3942 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3943 { 3944 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3945 } 3946 3947 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3948 { 3949 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3950 } 3951 3952 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3953 { 3954 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3955 } 3956 3957 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3958 { 3959 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3960 } 3961 3962 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3963 { 3964 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3965 } 3966 3967 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3968 { 3969 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3970 } 3971 3972 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3973 { 3974 /* We always set the AdvSIMD and FP fields identically. */ 3975 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3976 } 3977 3978 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3979 { 3980 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3981 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3982 } 3983 3984 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3985 { 3986 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3987 } 3988 3989 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3990 { 3991 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3992 } 3993 3994 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) 3995 { 3996 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; 3997 } 3998 3999 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 4000 { 4001 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 4002 } 4003 4004 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) 4005 { 4006 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2; 4007 } 4008 4009 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 4010 { 4011 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 4012 } 4013 4014 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 4015 { 4016 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 4017 } 4018 4019 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 4020 { 4021 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 4022 } 4023 4024 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 4025 { 4026 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 4027 } 4028 4029 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 4030 { 4031 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 4032 } 4033 4034 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 4035 { 4036 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 4037 } 4038 4039 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) 4040 { 4041 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; 4042 } 4043 4044 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 4045 { 4046 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 4047 } 4048 4049 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 4050 { 4051 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 4052 } 4053 4054 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) 4055 { 4056 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; 4057 } 4058 4059 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) 4060 { 4061 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; 4062 } 4063 4064 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) 4065 { 4066 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1; 4067 } 4068 4069 static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) 4070 { 4071 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2; 4072 } 4073 4074 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 4075 { 4076 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 4077 } 4078 4079 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 4080 { 4081 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 4082 } 4083 4084 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 4085 { 4086 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 4087 } 4088 4089 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) 4090 { 4091 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; 4092 } 4093 4094 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) 4095 { 4096 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 4097 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4098 } 4099 4100 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) 4101 { 4102 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 4103 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4104 } 4105 4106 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) 4107 { 4108 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 && 4109 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4110 } 4111 4112 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 4113 { 4114 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 4115 } 4116 4117 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 4118 { 4119 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 4120 } 4121 4122 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 4123 { 4124 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 4125 } 4126 4127 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 4128 { 4129 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 4130 } 4131 4132 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 4133 { 4134 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4135 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 4136 } 4137 4138 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 4139 { 4140 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 4141 } 4142 4143 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 4144 { 4145 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4146 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 4147 } 4148 4149 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) 4150 { 4151 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0; 4152 } 4153 4154 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) 4155 { 4156 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1; 4157 } 4158 4159 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) 4160 { 4161 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0; 4162 } 4163 4164 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) 4165 { 4166 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4167 return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id)); 4168 } 4169 4170 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) 4171 { 4172 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4173 return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id)); 4174 } 4175 4176 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) 4177 { 4178 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); 4179 return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); 4180 } 4181 4182 static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) 4183 { 4184 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0; 4185 } 4186 4187 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4188 { 4189 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4190 } 4191 4192 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4193 { 4194 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4195 } 4196 4197 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) 4198 { 4199 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; 4200 } 4201 4202 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) 4203 { 4204 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0; 4205 } 4206 4207 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) 4208 { 4209 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2; 4210 } 4211 4212 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4213 { 4214 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4215 } 4216 4217 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4218 { 4219 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4220 } 4221 4222 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 4223 { 4224 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); 4225 if (key >= 2) { 4226 return true; /* FEAT_CSV2_2 */ 4227 } 4228 if (key == 1) { 4229 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); 4230 return key >= 2; /* FEAT_CSV2_1p2 */ 4231 } 4232 return false; 4233 } 4234 4235 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4236 { 4237 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4238 } 4239 4240 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4241 { 4242 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4243 } 4244 4245 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4246 { 4247 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4248 } 4249 4250 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4251 { 4252 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4253 } 4254 4255 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4256 { 4257 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4258 } 4259 4260 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4261 { 4262 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4263 } 4264 4265 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4266 { 4267 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4268 } 4269 4270 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4271 { 4272 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4273 } 4274 4275 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4276 { 4277 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4278 } 4279 4280 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4281 { 4282 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4283 } 4284 4285 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4286 { 4287 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4288 } 4289 4290 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4291 { 4292 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4293 } 4294 4295 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) 4296 { 4297 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); 4298 } 4299 4300 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) 4301 { 4302 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; 4303 } 4304 4305 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) 4306 { 4307 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); 4308 } 4309 4310 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) 4311 { 4312 return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; 4313 } 4314 4315 /* 4316 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4317 */ 4318 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4319 { 4320 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4321 } 4322 4323 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4324 { 4325 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4326 } 4327 4328 static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id) 4329 { 4330 return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id); 4331 } 4332 4333 static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) 4334 { 4335 return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); 4336 } 4337 4338 static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) 4339 { 4340 return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); 4341 } 4342 4343 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4344 { 4345 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4346 } 4347 4348 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4349 { 4350 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4351 } 4352 4353 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4354 { 4355 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4356 } 4357 4358 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4359 { 4360 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4361 } 4362 4363 static inline bool isar_feature_any_half_evt(const ARMISARegisters *id) 4364 { 4365 return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id); 4366 } 4367 4368 static inline bool isar_feature_any_evt(const ARMISARegisters *id) 4369 { 4370 return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); 4371 } 4372 4373 /* 4374 * Forward to the above feature tests given an ARMCPU pointer. 4375 */ 4376 #define cpu_isar_feature(name, cpu) \ 4377 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4378 4379 #endif 4380