xref: /openbmc/qemu/target/arm/cpu.h (revision 8d99713b)
1 /*
2  * ARM virtual CPU header
3  *
4  *  Copyright (c) 2003 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef ARM_CPU_H
21 #define ARM_CPU_H
22 
23 #include "kvm-consts.h"
24 #include "hw/registerfields.h"
25 #include "cpu-qom.h"
26 #include "exec/cpu-defs.h"
27 #include "qapi/qapi-types-common.h"
28 
29 /* ARM processors have a weak memory model */
30 #define TCG_GUEST_DEFAULT_MO      (0)
31 
32 #ifdef TARGET_AARCH64
33 #define KVM_HAVE_MCE_INJECTION 1
34 #endif
35 
36 #define EXCP_UDEF            1   /* undefined instruction */
37 #define EXCP_SWI             2   /* software interrupt */
38 #define EXCP_PREFETCH_ABORT  3
39 #define EXCP_DATA_ABORT      4
40 #define EXCP_IRQ             5
41 #define EXCP_FIQ             6
42 #define EXCP_BKPT            7
43 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
44 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
45 #define EXCP_HVC            11   /* HyperVisor Call */
46 #define EXCP_HYP_TRAP       12
47 #define EXCP_SMC            13   /* Secure Monitor Call */
48 #define EXCP_VIRQ           14
49 #define EXCP_VFIQ           15
50 #define EXCP_SEMIHOST       16   /* semihosting call */
51 #define EXCP_NOCP           17   /* v7M NOCP UsageFault */
52 #define EXCP_INVSTATE       18   /* v7M INVSTATE UsageFault */
53 #define EXCP_STKOF          19   /* v8M STKOF UsageFault */
54 #define EXCP_LAZYFP         20   /* v7M fault during lazy FP stacking */
55 #define EXCP_LSERR          21   /* v8M LSERR SecureFault */
56 #define EXCP_UNALIGNED      22   /* v7M UNALIGNED UsageFault */
57 #define EXCP_DIVBYZERO      23   /* v7M DIVBYZERO UsageFault */
58 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
59 
60 #define ARMV7M_EXCP_RESET   1
61 #define ARMV7M_EXCP_NMI     2
62 #define ARMV7M_EXCP_HARD    3
63 #define ARMV7M_EXCP_MEM     4
64 #define ARMV7M_EXCP_BUS     5
65 #define ARMV7M_EXCP_USAGE   6
66 #define ARMV7M_EXCP_SECURE  7
67 #define ARMV7M_EXCP_SVC     11
68 #define ARMV7M_EXCP_DEBUG   12
69 #define ARMV7M_EXCP_PENDSV  14
70 #define ARMV7M_EXCP_SYSTICK 15
71 
72 /* For M profile, some registers are banked secure vs non-secure;
73  * these are represented as a 2-element array where the first element
74  * is the non-secure copy and the second is the secure copy.
75  * When the CPU does not have implement the security extension then
76  * only the first element is used.
77  * This means that the copy for the current security state can be
78  * accessed via env->registerfield[env->v7m.secure] (whether the security
79  * extension is implemented or not).
80  */
81 enum {
82     M_REG_NS = 0,
83     M_REG_S = 1,
84     M_REG_NUM_BANKS = 2,
85 };
86 
87 /* ARM-specific interrupt pending bits.  */
88 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
89 #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
90 #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
91 
92 /* The usual mapping for an AArch64 system register to its AArch32
93  * counterpart is for the 32 bit world to have access to the lower
94  * half only (with writes leaving the upper half untouched). It's
95  * therefore useful to be able to pass TCG the offset of the least
96  * significant half of a uint64_t struct member.
97  */
98 #ifdef HOST_WORDS_BIGENDIAN
99 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
100 #define offsetofhigh32(S, M) offsetof(S, M)
101 #else
102 #define offsetoflow32(S, M) offsetof(S, M)
103 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
104 #endif
105 
106 /* Meanings of the ARMCPU object's four inbound GPIO lines */
107 #define ARM_CPU_IRQ 0
108 #define ARM_CPU_FIQ 1
109 #define ARM_CPU_VIRQ 2
110 #define ARM_CPU_VFIQ 3
111 
112 /* ARM-specific extra insn start words:
113  * 1: Conditional execution bits
114  * 2: Partial exception syndrome for data aborts
115  */
116 #define TARGET_INSN_START_EXTRA_WORDS 2
117 
118 /* The 2nd extra word holding syndrome info for data aborts does not use
119  * the upper 6 bits nor the lower 14 bits. We mask and shift it down to
120  * help the sleb128 encoder do a better job.
121  * When restoring the CPU state, we shift it back up.
122  */
123 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
124 #define ARM_INSN_START_WORD2_SHIFT 14
125 
126 /* We currently assume float and double are IEEE single and double
127    precision respectively.
128    Doing runtime conversions is tricky because VFP registers may contain
129    integer values (eg. as the result of a FTOSI instruction).
130    s<2n> maps to the least significant half of d<n>
131    s<2n+1> maps to the most significant half of d<n>
132  */
133 
134 /**
135  * DynamicGDBXMLInfo:
136  * @desc: Contains the XML descriptions.
137  * @num: Number of the registers in this XML seen by GDB.
138  * @data: A union with data specific to the set of registers
139  *    @cpregs_keys: Array that contains the corresponding Key of
140  *                  a given cpreg with the same order of the cpreg
141  *                  in the XML description.
142  */
143 typedef struct DynamicGDBXMLInfo {
144     char *desc;
145     int num;
146     union {
147         struct {
148             uint32_t *keys;
149         } cpregs;
150     } data;
151 } DynamicGDBXMLInfo;
152 
153 /* CPU state for each instance of a generic timer (in cp15 c14) */
154 typedef struct ARMGenericTimer {
155     uint64_t cval; /* Timer CompareValue register */
156     uint64_t ctl; /* Timer Control register */
157 } ARMGenericTimer;
158 
159 #define GTIMER_PHYS     0
160 #define GTIMER_VIRT     1
161 #define GTIMER_HYP      2
162 #define GTIMER_SEC      3
163 #define GTIMER_HYPVIRT  4
164 #define NUM_GTIMERS     5
165 
166 typedef struct {
167     uint64_t raw_tcr;
168     uint32_t mask;
169     uint32_t base_mask;
170 } TCR;
171 
172 #define VTCR_NSW (1u << 29)
173 #define VTCR_NSA (1u << 30)
174 #define VSTCR_SW VTCR_NSW
175 #define VSTCR_SA VTCR_NSA
176 
177 /* Define a maximum sized vector register.
178  * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
179  * For 64-bit, this is a 2048-bit SVE register.
180  *
181  * Note that the mapping between S, D, and Q views of the register bank
182  * differs between AArch64 and AArch32.
183  * In AArch32:
184  *  Qn = regs[n].d[1]:regs[n].d[0]
185  *  Dn = regs[n / 2].d[n & 1]
186  *  Sn = regs[n / 4].d[n % 4 / 2],
187  *       bits 31..0 for even n, and bits 63..32 for odd n
188  *       (and regs[16] to regs[31] are inaccessible)
189  * In AArch64:
190  *  Zn = regs[n].d[*]
191  *  Qn = regs[n].d[1]:regs[n].d[0]
192  *  Dn = regs[n].d[0]
193  *  Sn = regs[n].d[0] bits 31..0
194  *  Hn = regs[n].d[0] bits 15..0
195  *
196  * This corresponds to the architecturally defined mapping between
197  * the two execution states, and means we do not need to explicitly
198  * map these registers when changing states.
199  *
200  * Align the data for use with TCG host vector operations.
201  */
202 
203 #ifdef TARGET_AARCH64
204 # define ARM_MAX_VQ    16
205 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
206 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
207 #else
208 # define ARM_MAX_VQ    1
209 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
210 static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { }
211 #endif
212 
213 typedef struct ARMVectorReg {
214     uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
215 } ARMVectorReg;
216 
217 #ifdef TARGET_AARCH64
218 /* In AArch32 mode, predicate registers do not exist at all.  */
219 typedef struct ARMPredicateReg {
220     uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
221 } ARMPredicateReg;
222 
223 /* In AArch32 mode, PAC keys do not exist at all.  */
224 typedef struct ARMPACKey {
225     uint64_t lo, hi;
226 } ARMPACKey;
227 #endif
228 
229 /* See the commentary above the TBFLAG field definitions.  */
230 typedef struct CPUARMTBFlags {
231     uint32_t flags;
232     target_ulong flags2;
233 } CPUARMTBFlags;
234 
235 typedef struct CPUARMState {
236     /* Regs for current mode.  */
237     uint32_t regs[16];
238 
239     /* 32/64 switch only happens when taking and returning from
240      * exceptions so the overlap semantics are taken care of then
241      * instead of having a complicated union.
242      */
243     /* Regs for A64 mode.  */
244     uint64_t xregs[32];
245     uint64_t pc;
246     /* PSTATE isn't an architectural register for ARMv8. However, it is
247      * convenient for us to assemble the underlying state into a 32 bit format
248      * identical to the architectural format used for the SPSR. (This is also
249      * what the Linux kernel's 'pstate' field in signal handlers and KVM's
250      * 'pstate' register are.) Of the PSTATE bits:
251      *  NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
252      *    semantics as for AArch32, as described in the comments on each field)
253      *  nRW (also known as M[4]) is kept, inverted, in env->aarch64
254      *  DAIF (exception masks) are kept in env->daif
255      *  BTYPE is kept in env->btype
256      *  all other bits are stored in their correct places in env->pstate
257      */
258     uint32_t pstate;
259     uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
260 
261     /* Cached TBFLAGS state.  See below for which bits are included.  */
262     CPUARMTBFlags hflags;
263 
264     /* Frequently accessed CPSR bits are stored separately for efficiency.
265        This contains all the other bits.  Use cpsr_{read,write} to access
266        the whole CPSR.  */
267     uint32_t uncached_cpsr;
268     uint32_t spsr;
269 
270     /* Banked registers.  */
271     uint64_t banked_spsr[8];
272     uint32_t banked_r13[8];
273     uint32_t banked_r14[8];
274 
275     /* These hold r8-r12.  */
276     uint32_t usr_regs[5];
277     uint32_t fiq_regs[5];
278 
279     /* cpsr flag cache for faster execution */
280     uint32_t CF; /* 0 or 1 */
281     uint32_t VF; /* V is the bit 31. All other bits are undefined */
282     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
283     uint32_t ZF; /* Z set if zero.  */
284     uint32_t QF; /* 0 or 1 */
285     uint32_t GE; /* cpsr[19:16] */
286     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
287     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
288     uint32_t btype;  /* BTI branch type.  spsr[11:10].  */
289     uint64_t daif; /* exception masks, in the bits they are in PSTATE */
290 
291     uint64_t elr_el[4]; /* AArch64 exception link regs  */
292     uint64_t sp_el[4]; /* AArch64 banked stack pointers */
293 
294     /* System control coprocessor (cp15) */
295     struct {
296         uint32_t c0_cpuid;
297         union { /* Cache size selection */
298             struct {
299                 uint64_t _unused_csselr0;
300                 uint64_t csselr_ns;
301                 uint64_t _unused_csselr1;
302                 uint64_t csselr_s;
303             };
304             uint64_t csselr_el[4];
305         };
306         union { /* System control register. */
307             struct {
308                 uint64_t _unused_sctlr;
309                 uint64_t sctlr_ns;
310                 uint64_t hsctlr;
311                 uint64_t sctlr_s;
312             };
313             uint64_t sctlr_el[4];
314         };
315         uint64_t cpacr_el1; /* Architectural feature access control register */
316         uint64_t cptr_el[4];  /* ARMv8 feature trap registers */
317         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
318         uint64_t sder; /* Secure debug enable register. */
319         uint32_t nsacr; /* Non-secure access control register. */
320         union { /* MMU translation table base 0. */
321             struct {
322                 uint64_t _unused_ttbr0_0;
323                 uint64_t ttbr0_ns;
324                 uint64_t _unused_ttbr0_1;
325                 uint64_t ttbr0_s;
326             };
327             uint64_t ttbr0_el[4];
328         };
329         union { /* MMU translation table base 1. */
330             struct {
331                 uint64_t _unused_ttbr1_0;
332                 uint64_t ttbr1_ns;
333                 uint64_t _unused_ttbr1_1;
334                 uint64_t ttbr1_s;
335             };
336             uint64_t ttbr1_el[4];
337         };
338         uint64_t vttbr_el2; /* Virtualization Translation Table Base.  */
339         uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */
340         /* MMU translation table base control. */
341         TCR tcr_el[4];
342         TCR vtcr_el2; /* Virtualization Translation Control.  */
343         TCR vstcr_el2; /* Secure Virtualization Translation Control. */
344         uint32_t c2_data; /* MPU data cacheable bits.  */
345         uint32_t c2_insn; /* MPU instruction cacheable bits.  */
346         union { /* MMU domain access control register
347                  * MPU write buffer control.
348                  */
349             struct {
350                 uint64_t dacr_ns;
351                 uint64_t dacr_s;
352             };
353             struct {
354                 uint64_t dacr32_el2;
355             };
356         };
357         uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
358         uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
359         uint64_t hcr_el2; /* Hypervisor configuration register */
360         uint64_t scr_el3; /* Secure configuration register.  */
361         union { /* Fault status registers.  */
362             struct {
363                 uint64_t ifsr_ns;
364                 uint64_t ifsr_s;
365             };
366             struct {
367                 uint64_t ifsr32_el2;
368             };
369         };
370         union {
371             struct {
372                 uint64_t _unused_dfsr;
373                 uint64_t dfsr_ns;
374                 uint64_t hsr;
375                 uint64_t dfsr_s;
376             };
377             uint64_t esr_el[4];
378         };
379         uint32_t c6_region[8]; /* MPU base/size registers.  */
380         union { /* Fault address registers. */
381             struct {
382                 uint64_t _unused_far0;
383 #ifdef HOST_WORDS_BIGENDIAN
384                 uint32_t ifar_ns;
385                 uint32_t dfar_ns;
386                 uint32_t ifar_s;
387                 uint32_t dfar_s;
388 #else
389                 uint32_t dfar_ns;
390                 uint32_t ifar_ns;
391                 uint32_t dfar_s;
392                 uint32_t ifar_s;
393 #endif
394                 uint64_t _unused_far3;
395             };
396             uint64_t far_el[4];
397         };
398         uint64_t hpfar_el2;
399         uint64_t hstr_el2;
400         union { /* Translation result. */
401             struct {
402                 uint64_t _unused_par_0;
403                 uint64_t par_ns;
404                 uint64_t _unused_par_1;
405                 uint64_t par_s;
406             };
407             uint64_t par_el[4];
408         };
409 
410         uint32_t c9_insn; /* Cache lockdown registers.  */
411         uint32_t c9_data;
412         uint64_t c9_pmcr; /* performance monitor control register */
413         uint64_t c9_pmcnten; /* perf monitor counter enables */
414         uint64_t c9_pmovsr; /* perf monitor overflow status */
415         uint64_t c9_pmuserenr; /* perf monitor user enable */
416         uint64_t c9_pmselr; /* perf monitor counter selection register */
417         uint64_t c9_pminten; /* perf monitor interrupt enables */
418         union { /* Memory attribute redirection */
419             struct {
420 #ifdef HOST_WORDS_BIGENDIAN
421                 uint64_t _unused_mair_0;
422                 uint32_t mair1_ns;
423                 uint32_t mair0_ns;
424                 uint64_t _unused_mair_1;
425                 uint32_t mair1_s;
426                 uint32_t mair0_s;
427 #else
428                 uint64_t _unused_mair_0;
429                 uint32_t mair0_ns;
430                 uint32_t mair1_ns;
431                 uint64_t _unused_mair_1;
432                 uint32_t mair0_s;
433                 uint32_t mair1_s;
434 #endif
435             };
436             uint64_t mair_el[4];
437         };
438         union { /* vector base address register */
439             struct {
440                 uint64_t _unused_vbar;
441                 uint64_t vbar_ns;
442                 uint64_t hvbar;
443                 uint64_t vbar_s;
444             };
445             uint64_t vbar_el[4];
446         };
447         uint32_t mvbar; /* (monitor) vector base address register */
448         struct { /* FCSE PID. */
449             uint32_t fcseidr_ns;
450             uint32_t fcseidr_s;
451         };
452         union { /* Context ID. */
453             struct {
454                 uint64_t _unused_contextidr_0;
455                 uint64_t contextidr_ns;
456                 uint64_t _unused_contextidr_1;
457                 uint64_t contextidr_s;
458             };
459             uint64_t contextidr_el[4];
460         };
461         union { /* User RW Thread register. */
462             struct {
463                 uint64_t tpidrurw_ns;
464                 uint64_t tpidrprw_ns;
465                 uint64_t htpidr;
466                 uint64_t _tpidr_el3;
467             };
468             uint64_t tpidr_el[4];
469         };
470         /* The secure banks of these registers don't map anywhere */
471         uint64_t tpidrurw_s;
472         uint64_t tpidrprw_s;
473         uint64_t tpidruro_s;
474 
475         union { /* User RO Thread register. */
476             uint64_t tpidruro_ns;
477             uint64_t tpidrro_el[1];
478         };
479         uint64_t c14_cntfrq; /* Counter Frequency register */
480         uint64_t c14_cntkctl; /* Timer Control register */
481         uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
482         uint64_t cntvoff_el2; /* Counter Virtual Offset register */
483         ARMGenericTimer c14_timer[NUM_GTIMERS];
484         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
485         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
486         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
487         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
488         uint32_t c15_threadid; /* TI debugger thread-ID.  */
489         uint32_t c15_config_base_address; /* SCU base address.  */
490         uint32_t c15_diagnostic; /* diagnostic register */
491         uint32_t c15_power_diagnostic;
492         uint32_t c15_power_control; /* power control */
493         uint64_t dbgbvr[16]; /* breakpoint value registers */
494         uint64_t dbgbcr[16]; /* breakpoint control registers */
495         uint64_t dbgwvr[16]; /* watchpoint value registers */
496         uint64_t dbgwcr[16]; /* watchpoint control registers */
497         uint64_t mdscr_el1;
498         uint64_t oslsr_el1; /* OS Lock Status */
499         uint64_t mdcr_el2;
500         uint64_t mdcr_el3;
501         /* Stores the architectural value of the counter *the last time it was
502          * updated* by pmccntr_op_start. Accesses should always be surrounded
503          * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
504          * architecturally-correct value is being read/set.
505          */
506         uint64_t c15_ccnt;
507         /* Stores the delta between the architectural value and the underlying
508          * cycle count during normal operation. It is used to update c15_ccnt
509          * to be the correct architectural value before accesses. During
510          * accesses, c15_ccnt_delta contains the underlying count being used
511          * for the access, after which it reverts to the delta value in
512          * pmccntr_op_finish.
513          */
514         uint64_t c15_ccnt_delta;
515         uint64_t c14_pmevcntr[31];
516         uint64_t c14_pmevcntr_delta[31];
517         uint64_t c14_pmevtyper[31];
518         uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
519         uint64_t vpidr_el2; /* Virtualization Processor ID Register */
520         uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
521         uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0.  */
522         uint64_t gcr_el1;
523         uint64_t rgsr_el1;
524     } cp15;
525 
526     struct {
527         /* M profile has up to 4 stack pointers:
528          * a Main Stack Pointer and a Process Stack Pointer for each
529          * of the Secure and Non-Secure states. (If the CPU doesn't support
530          * the security extension then it has only two SPs.)
531          * In QEMU we always store the currently active SP in regs[13],
532          * and the non-active SP for the current security state in
533          * v7m.other_sp. The stack pointers for the inactive security state
534          * are stored in other_ss_msp and other_ss_psp.
535          * switch_v7m_security_state() is responsible for rearranging them
536          * when we change security state.
537          */
538         uint32_t other_sp;
539         uint32_t other_ss_msp;
540         uint32_t other_ss_psp;
541         uint32_t vecbase[M_REG_NUM_BANKS];
542         uint32_t basepri[M_REG_NUM_BANKS];
543         uint32_t control[M_REG_NUM_BANKS];
544         uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
545         uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
546         uint32_t hfsr; /* HardFault Status */
547         uint32_t dfsr; /* Debug Fault Status Register */
548         uint32_t sfsr; /* Secure Fault Status Register */
549         uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
550         uint32_t bfar; /* BusFault Address */
551         uint32_t sfar; /* Secure Fault Address Register */
552         unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
553         int exception;
554         uint32_t primask[M_REG_NUM_BANKS];
555         uint32_t faultmask[M_REG_NUM_BANKS];
556         uint32_t aircr; /* only holds r/w state if security extn implemented */
557         uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
558         uint32_t csselr[M_REG_NUM_BANKS];
559         uint32_t scr[M_REG_NUM_BANKS];
560         uint32_t msplim[M_REG_NUM_BANKS];
561         uint32_t psplim[M_REG_NUM_BANKS];
562         uint32_t fpcar[M_REG_NUM_BANKS];
563         uint32_t fpccr[M_REG_NUM_BANKS];
564         uint32_t fpdscr[M_REG_NUM_BANKS];
565         uint32_t cpacr[M_REG_NUM_BANKS];
566         uint32_t nsacr;
567         uint32_t ltpsize;
568         uint32_t vpr;
569     } v7m;
570 
571     /* Information associated with an exception about to be taken:
572      * code which raises an exception must set cs->exception_index and
573      * the relevant parts of this structure; the cpu_do_interrupt function
574      * will then set the guest-visible registers as part of the exception
575      * entry process.
576      */
577     struct {
578         uint32_t syndrome; /* AArch64 format syndrome register */
579         uint32_t fsr; /* AArch32 format fault status register info */
580         uint64_t vaddress; /* virtual addr associated with exception, if any */
581         uint32_t target_el; /* EL the exception should be targeted for */
582         /* If we implement EL2 we will also need to store information
583          * about the intermediate physical address for stage 2 faults.
584          */
585     } exception;
586 
587     /* Information associated with an SError */
588     struct {
589         uint8_t pending;
590         uint8_t has_esr;
591         uint64_t esr;
592     } serror;
593 
594     uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
595 
596     /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
597     uint32_t irq_line_state;
598 
599     /* Thumb-2 EE state.  */
600     uint32_t teecr;
601     uint32_t teehbr;
602 
603     /* VFP coprocessor state.  */
604     struct {
605         ARMVectorReg zregs[32];
606 
607 #ifdef TARGET_AARCH64
608         /* Store FFR as pregs[16] to make it easier to treat as any other.  */
609 #define FFR_PRED_NUM 16
610         ARMPredicateReg pregs[17];
611         /* Scratch space for aa64 sve predicate temporary.  */
612         ARMPredicateReg preg_tmp;
613 #endif
614 
615         /* We store these fpcsr fields separately for convenience.  */
616         uint32_t qc[4] QEMU_ALIGNED(16);
617         int vec_len;
618         int vec_stride;
619 
620         uint32_t xregs[16];
621 
622         /* Scratch space for aa32 neon expansion.  */
623         uint32_t scratch[8];
624 
625         /* There are a number of distinct float control structures:
626          *
627          *  fp_status: is the "normal" fp status.
628          *  fp_status_fp16: used for half-precision calculations
629          *  standard_fp_status : the ARM "Standard FPSCR Value"
630          *  standard_fp_status_fp16 : used for half-precision
631          *       calculations with the ARM "Standard FPSCR Value"
632          *
633          * Half-precision operations are governed by a separate
634          * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
635          * status structure to control this.
636          *
637          * The "Standard FPSCR", ie default-NaN, flush-to-zero,
638          * round-to-nearest and is used by any operations (generally
639          * Neon) which the architecture defines as controlled by the
640          * standard FPSCR value rather than the FPSCR.
641          *
642          * The "standard FPSCR but for fp16 ops" is needed because
643          * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than
644          * using a fixed value for it.
645          *
646          * To avoid having to transfer exception bits around, we simply
647          * say that the FPSCR cumulative exception flags are the logical
648          * OR of the flags in the four fp statuses. This relies on the
649          * only thing which needs to read the exception flags being
650          * an explicit FPSCR read.
651          */
652         float_status fp_status;
653         float_status fp_status_f16;
654         float_status standard_fp_status;
655         float_status standard_fp_status_f16;
656 
657         /* ZCR_EL[1-3] */
658         uint64_t zcr_el[4];
659     } vfp;
660     uint64_t exclusive_addr;
661     uint64_t exclusive_val;
662     uint64_t exclusive_high;
663 
664     /* iwMMXt coprocessor state.  */
665     struct {
666         uint64_t regs[16];
667         uint64_t val;
668 
669         uint32_t cregs[16];
670     } iwmmxt;
671 
672 #ifdef TARGET_AARCH64
673     struct {
674         ARMPACKey apia;
675         ARMPACKey apib;
676         ARMPACKey apda;
677         ARMPACKey apdb;
678         ARMPACKey apga;
679     } keys;
680 #endif
681 
682 #if defined(CONFIG_USER_ONLY)
683     /* For usermode syscall translation.  */
684     int eabi;
685 #endif
686 
687     struct CPUBreakpoint *cpu_breakpoint[16];
688     struct CPUWatchpoint *cpu_watchpoint[16];
689 
690     /* Fields up to this point are cleared by a CPU reset */
691     struct {} end_reset_fields;
692 
693     /* Fields after this point are preserved across CPU reset. */
694 
695     /* Internal CPU feature flags.  */
696     uint64_t features;
697 
698     /* PMSAv7 MPU */
699     struct {
700         uint32_t *drbar;
701         uint32_t *drsr;
702         uint32_t *dracr;
703         uint32_t rnr[M_REG_NUM_BANKS];
704     } pmsav7;
705 
706     /* PMSAv8 MPU */
707     struct {
708         /* The PMSAv8 implementation also shares some PMSAv7 config
709          * and state:
710          *  pmsav7.rnr (region number register)
711          *  pmsav7_dregion (number of configured regions)
712          */
713         uint32_t *rbar[M_REG_NUM_BANKS];
714         uint32_t *rlar[M_REG_NUM_BANKS];
715         uint32_t mair0[M_REG_NUM_BANKS];
716         uint32_t mair1[M_REG_NUM_BANKS];
717     } pmsav8;
718 
719     /* v8M SAU */
720     struct {
721         uint32_t *rbar;
722         uint32_t *rlar;
723         uint32_t rnr;
724         uint32_t ctrl;
725     } sau;
726 
727     void *nvic;
728     const struct arm_boot_info *boot_info;
729     /* Store GICv3CPUState to access from this struct */
730     void *gicv3state;
731 
732 #ifdef TARGET_TAGGED_ADDRESSES
733     /* Linux syscall tagged address support */
734     bool tagged_addr_enable;
735 #endif
736 } CPUARMState;
737 
738 static inline void set_feature(CPUARMState *env, int feature)
739 {
740     env->features |= 1ULL << feature;
741 }
742 
743 static inline void unset_feature(CPUARMState *env, int feature)
744 {
745     env->features &= ~(1ULL << feature);
746 }
747 
748 /**
749  * ARMELChangeHookFn:
750  * type of a function which can be registered via arm_register_el_change_hook()
751  * to get callbacks when the CPU changes its exception level or mode.
752  */
753 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
754 typedef struct ARMELChangeHook ARMELChangeHook;
755 struct ARMELChangeHook {
756     ARMELChangeHookFn *hook;
757     void *opaque;
758     QLIST_ENTRY(ARMELChangeHook) node;
759 };
760 
761 /* These values map onto the return values for
762  * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
763 typedef enum ARMPSCIState {
764     PSCI_ON = 0,
765     PSCI_OFF = 1,
766     PSCI_ON_PENDING = 2
767 } ARMPSCIState;
768 
769 typedef struct ARMISARegisters ARMISARegisters;
770 
771 /**
772  * ARMCPU:
773  * @env: #CPUARMState
774  *
775  * An ARM CPU core.
776  */
777 struct ARMCPU {
778     /*< private >*/
779     CPUState parent_obj;
780     /*< public >*/
781 
782     CPUNegativeOffsetState neg;
783     CPUARMState env;
784 
785     /* Coprocessor information */
786     GHashTable *cp_regs;
787     /* For marshalling (mostly coprocessor) register state between the
788      * kernel and QEMU (for KVM) and between two QEMUs (for migration),
789      * we use these arrays.
790      */
791     /* List of register indexes managed via these arrays; (full KVM style
792      * 64 bit indexes, not CPRegInfo 32 bit indexes)
793      */
794     uint64_t *cpreg_indexes;
795     /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
796     uint64_t *cpreg_values;
797     /* Length of the indexes, values, reset_values arrays */
798     int32_t cpreg_array_len;
799     /* These are used only for migration: incoming data arrives in
800      * these fields and is sanity checked in post_load before copying
801      * to the working data structures above.
802      */
803     uint64_t *cpreg_vmstate_indexes;
804     uint64_t *cpreg_vmstate_values;
805     int32_t cpreg_vmstate_array_len;
806 
807     DynamicGDBXMLInfo dyn_sysreg_xml;
808     DynamicGDBXMLInfo dyn_svereg_xml;
809 
810     /* Timers used by the generic (architected) timer */
811     QEMUTimer *gt_timer[NUM_GTIMERS];
812     /*
813      * Timer used by the PMU. Its state is restored after migration by
814      * pmu_op_finish() - it does not need other handling during migration
815      */
816     QEMUTimer *pmu_timer;
817     /* GPIO outputs for generic timer */
818     qemu_irq gt_timer_outputs[NUM_GTIMERS];
819     /* GPIO output for GICv3 maintenance interrupt signal */
820     qemu_irq gicv3_maintenance_interrupt;
821     /* GPIO output for the PMU interrupt */
822     qemu_irq pmu_interrupt;
823 
824     /* MemoryRegion to use for secure physical accesses */
825     MemoryRegion *secure_memory;
826 
827     /* MemoryRegion to use for allocation tag accesses */
828     MemoryRegion *tag_memory;
829     MemoryRegion *secure_tag_memory;
830 
831     /* For v8M, pointer to the IDAU interface provided by board/SoC */
832     Object *idau;
833 
834     /* 'compatible' string for this CPU for Linux device trees */
835     const char *dtb_compatible;
836 
837     /* PSCI version for this CPU
838      * Bits[31:16] = Major Version
839      * Bits[15:0] = Minor Version
840      */
841     uint32_t psci_version;
842 
843     /* Current power state, access guarded by BQL */
844     ARMPSCIState power_state;
845 
846     /* CPU has virtualization extension */
847     bool has_el2;
848     /* CPU has security extension */
849     bool has_el3;
850     /* CPU has PMU (Performance Monitor Unit) */
851     bool has_pmu;
852     /* CPU has VFP */
853     bool has_vfp;
854     /* CPU has Neon */
855     bool has_neon;
856     /* CPU has M-profile DSP extension */
857     bool has_dsp;
858 
859     /* CPU has memory protection unit */
860     bool has_mpu;
861     /* PMSAv7 MPU number of supported regions */
862     uint32_t pmsav7_dregion;
863     /* v8M SAU number of supported regions */
864     uint32_t sau_sregion;
865 
866     /* PSCI conduit used to invoke PSCI methods
867      * 0 - disabled, 1 - smc, 2 - hvc
868      */
869     uint32_t psci_conduit;
870 
871     /* For v8M, initial value of the Secure VTOR */
872     uint32_t init_svtor;
873     /* For v8M, initial value of the Non-secure VTOR */
874     uint32_t init_nsvtor;
875 
876     /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
877      * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
878      */
879     uint32_t kvm_target;
880 
881     /* KVM init features for this CPU */
882     uint32_t kvm_init_features[7];
883 
884     /* KVM CPU state */
885 
886     /* KVM virtual time adjustment */
887     bool kvm_adjvtime;
888     bool kvm_vtime_dirty;
889     uint64_t kvm_vtime;
890 
891     /* KVM steal time */
892     OnOffAuto kvm_steal_time;
893 
894     /* Uniprocessor system with MP extensions */
895     bool mp_is_up;
896 
897     /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init
898      * and the probe failed (so we need to report the error in realize)
899      */
900     bool host_cpu_probe_failed;
901 
902     /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
903      * register.
904      */
905     int32_t core_count;
906 
907     /* The instance init functions for implementation-specific subclasses
908      * set these fields to specify the implementation-dependent values of
909      * various constant registers and reset values of non-constant
910      * registers.
911      * Some of these might become QOM properties eventually.
912      * Field names match the official register names as defined in the
913      * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
914      * is used for reset values of non-constant registers; no reset_
915      * prefix means a constant register.
916      * Some of these registers are split out into a substructure that
917      * is shared with the translators to control the ISA.
918      *
919      * Note that if you add an ID register to the ARMISARegisters struct
920      * you need to also update the 32-bit and 64-bit versions of the
921      * kvm_arm_get_host_cpu_features() function to correctly populate the
922      * field by reading the value from the KVM vCPU.
923      */
924     struct ARMISARegisters {
925         uint32_t id_isar0;
926         uint32_t id_isar1;
927         uint32_t id_isar2;
928         uint32_t id_isar3;
929         uint32_t id_isar4;
930         uint32_t id_isar5;
931         uint32_t id_isar6;
932         uint32_t id_mmfr0;
933         uint32_t id_mmfr1;
934         uint32_t id_mmfr2;
935         uint32_t id_mmfr3;
936         uint32_t id_mmfr4;
937         uint32_t id_pfr0;
938         uint32_t id_pfr1;
939         uint32_t id_pfr2;
940         uint32_t mvfr0;
941         uint32_t mvfr1;
942         uint32_t mvfr2;
943         uint32_t id_dfr0;
944         uint32_t dbgdidr;
945         uint64_t id_aa64isar0;
946         uint64_t id_aa64isar1;
947         uint64_t id_aa64pfr0;
948         uint64_t id_aa64pfr1;
949         uint64_t id_aa64mmfr0;
950         uint64_t id_aa64mmfr1;
951         uint64_t id_aa64mmfr2;
952         uint64_t id_aa64dfr0;
953         uint64_t id_aa64dfr1;
954         uint64_t id_aa64zfr0;
955     } isar;
956     uint64_t midr;
957     uint32_t revidr;
958     uint32_t reset_fpsid;
959     uint64_t ctr;
960     uint32_t reset_sctlr;
961     uint64_t pmceid0;
962     uint64_t pmceid1;
963     uint32_t id_afr0;
964     uint64_t id_aa64afr0;
965     uint64_t id_aa64afr1;
966     uint64_t clidr;
967     uint64_t mp_affinity; /* MP ID without feature bits */
968     /* The elements of this array are the CCSIDR values for each cache,
969      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
970      */
971     uint64_t ccsidr[16];
972     uint64_t reset_cbar;
973     uint32_t reset_auxcr;
974     bool reset_hivecs;
975 
976     /*
977      * Intermediate values used during property parsing.
978      * Once finalized, the values should be read from ID_AA64ISAR1.
979      */
980     bool prop_pauth;
981     bool prop_pauth_impdef;
982 
983     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
984     uint32_t dcz_blocksize;
985     uint64_t rvbar;
986 
987     /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
988     int gic_num_lrs; /* number of list registers */
989     int gic_vpribits; /* number of virtual priority bits */
990     int gic_vprebits; /* number of virtual preemption bits */
991 
992     /* Whether the cfgend input is high (i.e. this CPU should reset into
993      * big-endian mode).  This setting isn't used directly: instead it modifies
994      * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
995      * architecture version.
996      */
997     bool cfgend;
998 
999     QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
1000     QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
1001 
1002     int32_t node_id; /* NUMA node this CPU belongs to */
1003 
1004     /* Used to synchronize KVM and QEMU in-kernel device levels */
1005     uint8_t device_irq_level;
1006 
1007     /* Used to set the maximum vector length the cpu will support.  */
1008     uint32_t sve_max_vq;
1009 
1010 #ifdef CONFIG_USER_ONLY
1011     /* Used to set the default vector length at process start. */
1012     uint32_t sve_default_vq;
1013 #endif
1014 
1015     /*
1016      * In sve_vq_map each set bit is a supported vector length of
1017      * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
1018      * length in quadwords.
1019      *
1020      * While processing properties during initialization, corresponding
1021      * sve_vq_init bits are set for bits in sve_vq_map that have been
1022      * set by properties.
1023      *
1024      * Bits set in sve_vq_supported represent valid vector lengths for
1025      * the CPU type.
1026      */
1027     DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
1028     DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
1029     DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ);
1030 
1031     /* Generic timer counter frequency, in Hz */
1032     uint64_t gt_cntfrq_hz;
1033 };
1034 
1035 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
1036 
1037 void arm_cpu_post_init(Object *obj);
1038 
1039 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
1040 
1041 #ifndef CONFIG_USER_ONLY
1042 extern const VMStateDescription vmstate_arm_cpu;
1043 
1044 void arm_cpu_do_interrupt(CPUState *cpu);
1045 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1046 #endif /* !CONFIG_USER_ONLY */
1047 
1048 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1049                                          MemTxAttrs *attrs);
1050 
1051 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1052 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1053 
1054 /*
1055  * Helpers to dynamically generates XML descriptions of the sysregs
1056  * and SVE registers. Returns the number of registers in each set.
1057  */
1058 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
1059 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
1060 
1061 /* Returns the dynamically generated XML for the gdb stub.
1062  * Returns a pointer to the XML contents for the specified XML file or NULL
1063  * if the XML name doesn't match the predefined one.
1064  */
1065 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1066 
1067 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1068                              int cpuid, void *opaque);
1069 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1070                              int cpuid, void *opaque);
1071 
1072 #ifdef TARGET_AARCH64
1073 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1074 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1075 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1076 void aarch64_sve_change_el(CPUARMState *env, int old_el,
1077                            int new_el, bool el0_a64);
1078 void aarch64_add_sve_properties(Object *obj);
1079 void aarch64_add_pauth_properties(Object *obj);
1080 
1081 /*
1082  * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1083  * The byte at offset i from the start of the in-memory representation contains
1084  * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
1085  * lowest offsets are stored in the lowest memory addresses, then that nearly
1086  * matches QEMU's representation, which is to use an array of host-endian
1087  * uint64_t's, where the lower offsets are at the lower indices. To complete
1088  * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1089  */
1090 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1091 {
1092 #ifdef HOST_WORDS_BIGENDIAN
1093     int i;
1094 
1095     for (i = 0; i < nr; ++i) {
1096         dst[i] = bswap64(src[i]);
1097     }
1098 
1099     return dst;
1100 #else
1101     return src;
1102 #endif
1103 }
1104 
1105 #else
1106 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1107 static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1108                                          int n, bool a)
1109 { }
1110 static inline void aarch64_add_sve_properties(Object *obj) { }
1111 #endif
1112 
1113 void aarch64_sync_32_to_64(CPUARMState *env);
1114 void aarch64_sync_64_to_32(CPUARMState *env);
1115 
1116 int fp_exception_el(CPUARMState *env, int cur_el);
1117 int sve_exception_el(CPUARMState *env, int cur_el);
1118 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
1119 
1120 static inline bool is_a64(CPUARMState *env)
1121 {
1122     return env->aarch64;
1123 }
1124 
1125 /**
1126  * pmu_op_start/finish
1127  * @env: CPUARMState
1128  *
1129  * Convert all PMU counters between their delta form (the typical mode when
1130  * they are enabled) and the guest-visible values. These two calls must
1131  * surround any action which might affect the counters.
1132  */
1133 void pmu_op_start(CPUARMState *env);
1134 void pmu_op_finish(CPUARMState *env);
1135 
1136 /*
1137  * Called when a PMU counter is due to overflow
1138  */
1139 void arm_pmu_timer_cb(void *opaque);
1140 
1141 /**
1142  * Functions to register as EL change hooks for PMU mode filtering
1143  */
1144 void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1145 void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1146 
1147 /*
1148  * pmu_init
1149  * @cpu: ARMCPU
1150  *
1151  * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state
1152  * for the current configuration
1153  */
1154 void pmu_init(ARMCPU *cpu);
1155 
1156 /* SCTLR bit meanings. Several bits have been reused in newer
1157  * versions of the architecture; in that case we define constants
1158  * for both old and new bit meanings. Code which tests against those
1159  * bits should probably check or otherwise arrange that the CPU
1160  * is the architectural version it expects.
1161  */
1162 #define SCTLR_M       (1U << 0)
1163 #define SCTLR_A       (1U << 1)
1164 #define SCTLR_C       (1U << 2)
1165 #define SCTLR_W       (1U << 3) /* up to v6; RAO in v7 */
1166 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1167 #define SCTLR_SA      (1U << 3) /* AArch64 only */
1168 #define SCTLR_P       (1U << 4) /* up to v5; RAO in v6 and v7 */
1169 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1170 #define SCTLR_SA0     (1U << 4) /* v8 onward, AArch64 only */
1171 #define SCTLR_D       (1U << 5) /* up to v5; RAO in v6 */
1172 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1173 #define SCTLR_L       (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1174 #define SCTLR_nAA     (1U << 6) /* when v8.4-LSE is implemented */
1175 #define SCTLR_B       (1U << 7) /* up to v6; RAZ in v7 */
1176 #define SCTLR_ITD     (1U << 7) /* v8 onward */
1177 #define SCTLR_S       (1U << 8) /* up to v6; RAZ in v7 */
1178 #define SCTLR_SED     (1U << 8) /* v8 onward */
1179 #define SCTLR_R       (1U << 9) /* up to v6; RAZ in v7 */
1180 #define SCTLR_UMA     (1U << 9) /* v8 onward, AArch64 only */
1181 #define SCTLR_F       (1U << 10) /* up to v6 */
1182 #define SCTLR_SW      (1U << 10) /* v7 */
1183 #define SCTLR_EnRCTX  (1U << 10) /* in v8.0-PredInv */
1184 #define SCTLR_Z       (1U << 11) /* in v7, RES1 in v8 */
1185 #define SCTLR_EOS     (1U << 11) /* v8.5-ExS */
1186 #define SCTLR_I       (1U << 12)
1187 #define SCTLR_V       (1U << 13) /* AArch32 only */
1188 #define SCTLR_EnDB    (1U << 13) /* v8.3, AArch64 only */
1189 #define SCTLR_RR      (1U << 14) /* up to v7 */
1190 #define SCTLR_DZE     (1U << 14) /* v8 onward, AArch64 only */
1191 #define SCTLR_L4      (1U << 15) /* up to v6; RAZ in v7 */
1192 #define SCTLR_UCT     (1U << 15) /* v8 onward, AArch64 only */
1193 #define SCTLR_DT      (1U << 16) /* up to ??, RAO in v6 and v7 */
1194 #define SCTLR_nTWI    (1U << 16) /* v8 onward */
1195 #define SCTLR_HA      (1U << 17) /* up to v7, RES0 in v8 */
1196 #define SCTLR_BR      (1U << 17) /* PMSA only */
1197 #define SCTLR_IT      (1U << 18) /* up to ??, RAO in v6 and v7 */
1198 #define SCTLR_nTWE    (1U << 18) /* v8 onward */
1199 #define SCTLR_WXN     (1U << 19)
1200 #define SCTLR_ST      (1U << 20) /* up to ??, RAZ in v6 */
1201 #define SCTLR_UWXN    (1U << 20) /* v7 onward, AArch32 only */
1202 #define SCTLR_FI      (1U << 21) /* up to v7, v8 RES0 */
1203 #define SCTLR_IESB    (1U << 21) /* v8.2-IESB, AArch64 only */
1204 #define SCTLR_U       (1U << 22) /* up to v6, RAO in v7 */
1205 #define SCTLR_EIS     (1U << 22) /* v8.5-ExS */
1206 #define SCTLR_XP      (1U << 23) /* up to v6; v7 onward RAO */
1207 #define SCTLR_SPAN    (1U << 23) /* v8.1-PAN */
1208 #define SCTLR_VE      (1U << 24) /* up to v7 */
1209 #define SCTLR_E0E     (1U << 24) /* v8 onward, AArch64 only */
1210 #define SCTLR_EE      (1U << 25)
1211 #define SCTLR_L2      (1U << 26) /* up to v6, RAZ in v7 */
1212 #define SCTLR_UCI     (1U << 26) /* v8 onward, AArch64 only */
1213 #define SCTLR_NMFI    (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1214 #define SCTLR_EnDA    (1U << 27) /* v8.3, AArch64 only */
1215 #define SCTLR_TRE     (1U << 28) /* AArch32 only */
1216 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1217 #define SCTLR_AFE     (1U << 29) /* AArch32 only */
1218 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1219 #define SCTLR_TE      (1U << 30) /* AArch32 only */
1220 #define SCTLR_EnIB    (1U << 30) /* v8.3, AArch64 only */
1221 #define SCTLR_EnIA    (1U << 31) /* v8.3, AArch64 only */
1222 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
1223 #define SCTLR_BT0     (1ULL << 35) /* v8.5-BTI */
1224 #define SCTLR_BT1     (1ULL << 36) /* v8.5-BTI */
1225 #define SCTLR_ITFSB   (1ULL << 37) /* v8.5-MemTag */
1226 #define SCTLR_TCF0    (3ULL << 38) /* v8.5-MemTag */
1227 #define SCTLR_TCF     (3ULL << 40) /* v8.5-MemTag */
1228 #define SCTLR_ATA0    (1ULL << 42) /* v8.5-MemTag */
1229 #define SCTLR_ATA     (1ULL << 43) /* v8.5-MemTag */
1230 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
1231 
1232 #define CPTR_TCPAC    (1U << 31)
1233 #define CPTR_TTA      (1U << 20)
1234 #define CPTR_TFP      (1U << 10)
1235 #define CPTR_TZ       (1U << 8)   /* CPTR_EL2 */
1236 #define CPTR_EZ       (1U << 8)   /* CPTR_EL3 */
1237 
1238 #define MDCR_EPMAD    (1U << 21)
1239 #define MDCR_EDAD     (1U << 20)
1240 #define MDCR_SPME     (1U << 17)  /* MDCR_EL3 */
1241 #define MDCR_HPMD     (1U << 17)  /* MDCR_EL2 */
1242 #define MDCR_SDD      (1U << 16)
1243 #define MDCR_SPD      (3U << 14)
1244 #define MDCR_TDRA     (1U << 11)
1245 #define MDCR_TDOSA    (1U << 10)
1246 #define MDCR_TDA      (1U << 9)
1247 #define MDCR_TDE      (1U << 8)
1248 #define MDCR_HPME     (1U << 7)
1249 #define MDCR_TPM      (1U << 6)
1250 #define MDCR_TPMCR    (1U << 5)
1251 #define MDCR_HPMN     (0x1fU)
1252 
1253 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
1254 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1255 
1256 #define CPSR_M (0x1fU)
1257 #define CPSR_T (1U << 5)
1258 #define CPSR_F (1U << 6)
1259 #define CPSR_I (1U << 7)
1260 #define CPSR_A (1U << 8)
1261 #define CPSR_E (1U << 9)
1262 #define CPSR_IT_2_7 (0xfc00U)
1263 #define CPSR_GE (0xfU << 16)
1264 #define CPSR_IL (1U << 20)
1265 #define CPSR_DIT (1U << 21)
1266 #define CPSR_PAN (1U << 22)
1267 #define CPSR_SSBS (1U << 23)
1268 #define CPSR_J (1U << 24)
1269 #define CPSR_IT_0_1 (3U << 25)
1270 #define CPSR_Q (1U << 27)
1271 #define CPSR_V (1U << 28)
1272 #define CPSR_C (1U << 29)
1273 #define CPSR_Z (1U << 30)
1274 #define CPSR_N (1U << 31)
1275 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1276 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1277 
1278 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1279 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1280     | CPSR_NZCV)
1281 /* Bits writable in user mode.  */
1282 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1283 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
1284 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1285 
1286 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1287 #define XPSR_EXCP 0x1ffU
1288 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1289 #define XPSR_IT_2_7 CPSR_IT_2_7
1290 #define XPSR_GE CPSR_GE
1291 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1292 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1293 #define XPSR_IT_0_1 CPSR_IT_0_1
1294 #define XPSR_Q CPSR_Q
1295 #define XPSR_V CPSR_V
1296 #define XPSR_C CPSR_C
1297 #define XPSR_Z CPSR_Z
1298 #define XPSR_N CPSR_N
1299 #define XPSR_NZCV CPSR_NZCV
1300 #define XPSR_IT CPSR_IT
1301 
1302 #define TTBCR_N      (7U << 0) /* TTBCR.EAE==0 */
1303 #define TTBCR_T0SZ   (7U << 0) /* TTBCR.EAE==1 */
1304 #define TTBCR_PD0    (1U << 4)
1305 #define TTBCR_PD1    (1U << 5)
1306 #define TTBCR_EPD0   (1U << 7)
1307 #define TTBCR_IRGN0  (3U << 8)
1308 #define TTBCR_ORGN0  (3U << 10)
1309 #define TTBCR_SH0    (3U << 12)
1310 #define TTBCR_T1SZ   (3U << 16)
1311 #define TTBCR_A1     (1U << 22)
1312 #define TTBCR_EPD1   (1U << 23)
1313 #define TTBCR_IRGN1  (3U << 24)
1314 #define TTBCR_ORGN1  (3U << 26)
1315 #define TTBCR_SH1    (1U << 28)
1316 #define TTBCR_EAE    (1U << 31)
1317 
1318 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1319  * Only these are valid when in AArch64 mode; in
1320  * AArch32 mode SPSRs are basically CPSR-format.
1321  */
1322 #define PSTATE_SP (1U)
1323 #define PSTATE_M (0xFU)
1324 #define PSTATE_nRW (1U << 4)
1325 #define PSTATE_F (1U << 6)
1326 #define PSTATE_I (1U << 7)
1327 #define PSTATE_A (1U << 8)
1328 #define PSTATE_D (1U << 9)
1329 #define PSTATE_BTYPE (3U << 10)
1330 #define PSTATE_SSBS (1U << 12)
1331 #define PSTATE_IL (1U << 20)
1332 #define PSTATE_SS (1U << 21)
1333 #define PSTATE_PAN (1U << 22)
1334 #define PSTATE_UAO (1U << 23)
1335 #define PSTATE_DIT (1U << 24)
1336 #define PSTATE_TCO (1U << 25)
1337 #define PSTATE_V (1U << 28)
1338 #define PSTATE_C (1U << 29)
1339 #define PSTATE_Z (1U << 30)
1340 #define PSTATE_N (1U << 31)
1341 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1342 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1343 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1344 /* Mode values for AArch64 */
1345 #define PSTATE_MODE_EL3h 13
1346 #define PSTATE_MODE_EL3t 12
1347 #define PSTATE_MODE_EL2h 9
1348 #define PSTATE_MODE_EL2t 8
1349 #define PSTATE_MODE_EL1h 5
1350 #define PSTATE_MODE_EL1t 4
1351 #define PSTATE_MODE_EL0t 0
1352 
1353 /* Write a new value to v7m.exception, thus transitioning into or out
1354  * of Handler mode; this may result in a change of active stack pointer.
1355  */
1356 void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1357 
1358 /* Map EL and handler into a PSTATE_MODE.  */
1359 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1360 {
1361     return (el << 2) | handler;
1362 }
1363 
1364 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1365  * interprocessing, so we don't attempt to sync with the cpsr state used by
1366  * the 32 bit decoder.
1367  */
1368 static inline uint32_t pstate_read(CPUARMState *env)
1369 {
1370     int ZF;
1371 
1372     ZF = (env->ZF == 0);
1373     return (env->NF & 0x80000000) | (ZF << 30)
1374         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1375         | env->pstate | env->daif | (env->btype << 10);
1376 }
1377 
1378 static inline void pstate_write(CPUARMState *env, uint32_t val)
1379 {
1380     env->ZF = (~val) & PSTATE_Z;
1381     env->NF = val;
1382     env->CF = (val >> 29) & 1;
1383     env->VF = (val << 3) & 0x80000000;
1384     env->daif = val & PSTATE_DAIF;
1385     env->btype = (val >> 10) & 3;
1386     env->pstate = val & ~CACHED_PSTATE_BITS;
1387 }
1388 
1389 /* Return the current CPSR value.  */
1390 uint32_t cpsr_read(CPUARMState *env);
1391 
1392 typedef enum CPSRWriteType {
1393     CPSRWriteByInstr = 0,         /* from guest MSR or CPS */
1394     CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1395     CPSRWriteRaw = 2,
1396         /* trust values, no reg bank switch, no hflags rebuild */
1397     CPSRWriteByGDBStub = 3,       /* from the GDB stub */
1398 } CPSRWriteType;
1399 
1400 /*
1401  * Set the CPSR.  Note that some bits of mask must be all-set or all-clear.
1402  * This will do an arm_rebuild_hflags() if any of the bits in @mask
1403  * correspond to TB flags bits cached in the hflags, unless @write_type
1404  * is CPSRWriteRaw.
1405  */
1406 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1407                 CPSRWriteType write_type);
1408 
1409 /* Return the current xPSR value.  */
1410 static inline uint32_t xpsr_read(CPUARMState *env)
1411 {
1412     int ZF;
1413     ZF = (env->ZF == 0);
1414     return (env->NF & 0x80000000) | (ZF << 30)
1415         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1416         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1417         | ((env->condexec_bits & 0xfc) << 8)
1418         | (env->GE << 16)
1419         | env->v7m.exception;
1420 }
1421 
1422 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
1423 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1424 {
1425     if (mask & XPSR_NZCV) {
1426         env->ZF = (~val) & XPSR_Z;
1427         env->NF = val;
1428         env->CF = (val >> 29) & 1;
1429         env->VF = (val << 3) & 0x80000000;
1430     }
1431     if (mask & XPSR_Q) {
1432         env->QF = ((val & XPSR_Q) != 0);
1433     }
1434     if (mask & XPSR_GE) {
1435         env->GE = (val & XPSR_GE) >> 16;
1436     }
1437 #ifndef CONFIG_USER_ONLY
1438     if (mask & XPSR_T) {
1439         env->thumb = ((val & XPSR_T) != 0);
1440     }
1441     if (mask & XPSR_IT_0_1) {
1442         env->condexec_bits &= ~3;
1443         env->condexec_bits |= (val >> 25) & 3;
1444     }
1445     if (mask & XPSR_IT_2_7) {
1446         env->condexec_bits &= 3;
1447         env->condexec_bits |= (val >> 8) & 0xfc;
1448     }
1449     if (mask & XPSR_EXCP) {
1450         /* Note that this only happens on exception exit */
1451         write_v7m_exception(env, val & XPSR_EXCP);
1452     }
1453 #endif
1454 }
1455 
1456 #define HCR_VM        (1ULL << 0)
1457 #define HCR_SWIO      (1ULL << 1)
1458 #define HCR_PTW       (1ULL << 2)
1459 #define HCR_FMO       (1ULL << 3)
1460 #define HCR_IMO       (1ULL << 4)
1461 #define HCR_AMO       (1ULL << 5)
1462 #define HCR_VF        (1ULL << 6)
1463 #define HCR_VI        (1ULL << 7)
1464 #define HCR_VSE       (1ULL << 8)
1465 #define HCR_FB        (1ULL << 9)
1466 #define HCR_BSU_MASK  (3ULL << 10)
1467 #define HCR_DC        (1ULL << 12)
1468 #define HCR_TWI       (1ULL << 13)
1469 #define HCR_TWE       (1ULL << 14)
1470 #define HCR_TID0      (1ULL << 15)
1471 #define HCR_TID1      (1ULL << 16)
1472 #define HCR_TID2      (1ULL << 17)
1473 #define HCR_TID3      (1ULL << 18)
1474 #define HCR_TSC       (1ULL << 19)
1475 #define HCR_TIDCP     (1ULL << 20)
1476 #define HCR_TACR      (1ULL << 21)
1477 #define HCR_TSW       (1ULL << 22)
1478 #define HCR_TPCP      (1ULL << 23)
1479 #define HCR_TPU       (1ULL << 24)
1480 #define HCR_TTLB      (1ULL << 25)
1481 #define HCR_TVM       (1ULL << 26)
1482 #define HCR_TGE       (1ULL << 27)
1483 #define HCR_TDZ       (1ULL << 28)
1484 #define HCR_HCD       (1ULL << 29)
1485 #define HCR_TRVM      (1ULL << 30)
1486 #define HCR_RW        (1ULL << 31)
1487 #define HCR_CD        (1ULL << 32)
1488 #define HCR_ID        (1ULL << 33)
1489 #define HCR_E2H       (1ULL << 34)
1490 #define HCR_TLOR      (1ULL << 35)
1491 #define HCR_TERR      (1ULL << 36)
1492 #define HCR_TEA       (1ULL << 37)
1493 #define HCR_MIOCNCE   (1ULL << 38)
1494 /* RES0 bit 39 */
1495 #define HCR_APK       (1ULL << 40)
1496 #define HCR_API       (1ULL << 41)
1497 #define HCR_NV        (1ULL << 42)
1498 #define HCR_NV1       (1ULL << 43)
1499 #define HCR_AT        (1ULL << 44)
1500 #define HCR_NV2       (1ULL << 45)
1501 #define HCR_FWB       (1ULL << 46)
1502 #define HCR_FIEN      (1ULL << 47)
1503 /* RES0 bit 48 */
1504 #define HCR_TID4      (1ULL << 49)
1505 #define HCR_TICAB     (1ULL << 50)
1506 #define HCR_AMVOFFEN  (1ULL << 51)
1507 #define HCR_TOCU      (1ULL << 52)
1508 #define HCR_ENSCXT    (1ULL << 53)
1509 #define HCR_TTLBIS    (1ULL << 54)
1510 #define HCR_TTLBOS    (1ULL << 55)
1511 #define HCR_ATA       (1ULL << 56)
1512 #define HCR_DCT       (1ULL << 57)
1513 #define HCR_TID5      (1ULL << 58)
1514 #define HCR_TWEDEN    (1ULL << 59)
1515 #define HCR_TWEDEL    MAKE_64BIT_MASK(60, 4)
1516 
1517 #define HPFAR_NS      (1ULL << 63)
1518 
1519 #define SCR_NS                (1U << 0)
1520 #define SCR_IRQ               (1U << 1)
1521 #define SCR_FIQ               (1U << 2)
1522 #define SCR_EA                (1U << 3)
1523 #define SCR_FW                (1U << 4)
1524 #define SCR_AW                (1U << 5)
1525 #define SCR_NET               (1U << 6)
1526 #define SCR_SMD               (1U << 7)
1527 #define SCR_HCE               (1U << 8)
1528 #define SCR_SIF               (1U << 9)
1529 #define SCR_RW                (1U << 10)
1530 #define SCR_ST                (1U << 11)
1531 #define SCR_TWI               (1U << 12)
1532 #define SCR_TWE               (1U << 13)
1533 #define SCR_TLOR              (1U << 14)
1534 #define SCR_TERR              (1U << 15)
1535 #define SCR_APK               (1U << 16)
1536 #define SCR_API               (1U << 17)
1537 #define SCR_EEL2              (1U << 18)
1538 #define SCR_EASE              (1U << 19)
1539 #define SCR_NMEA              (1U << 20)
1540 #define SCR_FIEN              (1U << 21)
1541 #define SCR_ENSCXT            (1U << 25)
1542 #define SCR_ATA               (1U << 26)
1543 
1544 #define HSTR_TTEE (1 << 16)
1545 #define HSTR_TJDBX (1 << 17)
1546 
1547 /* Return the current FPSCR value.  */
1548 uint32_t vfp_get_fpscr(CPUARMState *env);
1549 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1550 
1551 /* FPCR, Floating Point Control Register
1552  * FPSR, Floating Poiht Status Register
1553  *
1554  * For A64 the FPSCR is split into two logically distinct registers,
1555  * FPCR and FPSR. However since they still use non-overlapping bits
1556  * we store the underlying state in fpscr and just mask on read/write.
1557  */
1558 #define FPSR_MASK 0xf800009f
1559 #define FPCR_MASK 0x07ff9f00
1560 
1561 #define FPCR_IOE    (1 << 8)    /* Invalid Operation exception trap enable */
1562 #define FPCR_DZE    (1 << 9)    /* Divide by Zero exception trap enable */
1563 #define FPCR_OFE    (1 << 10)   /* Overflow exception trap enable */
1564 #define FPCR_UFE    (1 << 11)   /* Underflow exception trap enable */
1565 #define FPCR_IXE    (1 << 12)   /* Inexact exception trap enable */
1566 #define FPCR_IDE    (1 << 15)   /* Input Denormal exception trap enable */
1567 #define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
1568 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
1569 #define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
1570 #define FPCR_DN     (1 << 25)   /* Default NaN enable bit */
1571 #define FPCR_AHP    (1 << 26)   /* Alternative half-precision */
1572 #define FPCR_QC     (1 << 27)   /* Cumulative saturation bit */
1573 #define FPCR_V      (1 << 28)   /* FP overflow flag */
1574 #define FPCR_C      (1 << 29)   /* FP carry flag */
1575 #define FPCR_Z      (1 << 30)   /* FP zero flag */
1576 #define FPCR_N      (1 << 31)   /* FP negative flag */
1577 
1578 #define FPCR_LTPSIZE_SHIFT 16   /* LTPSIZE, M-profile only */
1579 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
1580 #define FPCR_LTPSIZE_LENGTH 3
1581 
1582 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
1583 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
1584 
1585 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1586 {
1587     return vfp_get_fpscr(env) & FPSR_MASK;
1588 }
1589 
1590 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1591 {
1592     uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1593     vfp_set_fpscr(env, new_fpscr);
1594 }
1595 
1596 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1597 {
1598     return vfp_get_fpscr(env) & FPCR_MASK;
1599 }
1600 
1601 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1602 {
1603     uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1604     vfp_set_fpscr(env, new_fpscr);
1605 }
1606 
1607 enum arm_cpu_mode {
1608   ARM_CPU_MODE_USR = 0x10,
1609   ARM_CPU_MODE_FIQ = 0x11,
1610   ARM_CPU_MODE_IRQ = 0x12,
1611   ARM_CPU_MODE_SVC = 0x13,
1612   ARM_CPU_MODE_MON = 0x16,
1613   ARM_CPU_MODE_ABT = 0x17,
1614   ARM_CPU_MODE_HYP = 0x1a,
1615   ARM_CPU_MODE_UND = 0x1b,
1616   ARM_CPU_MODE_SYS = 0x1f
1617 };
1618 
1619 /* VFP system registers.  */
1620 #define ARM_VFP_FPSID   0
1621 #define ARM_VFP_FPSCR   1
1622 #define ARM_VFP_MVFR2   5
1623 #define ARM_VFP_MVFR1   6
1624 #define ARM_VFP_MVFR0   7
1625 #define ARM_VFP_FPEXC   8
1626 #define ARM_VFP_FPINST  9
1627 #define ARM_VFP_FPINST2 10
1628 /* These ones are M-profile only */
1629 #define ARM_VFP_FPSCR_NZCVQC 2
1630 #define ARM_VFP_VPR 12
1631 #define ARM_VFP_P0 13
1632 #define ARM_VFP_FPCXT_NS 14
1633 #define ARM_VFP_FPCXT_S 15
1634 
1635 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
1636 #define QEMU_VFP_FPSCR_NZCV 0xffff
1637 
1638 /* iwMMXt coprocessor control registers.  */
1639 #define ARM_IWMMXT_wCID  0
1640 #define ARM_IWMMXT_wCon  1
1641 #define ARM_IWMMXT_wCSSF 2
1642 #define ARM_IWMMXT_wCASF 3
1643 #define ARM_IWMMXT_wCGR0 8
1644 #define ARM_IWMMXT_wCGR1 9
1645 #define ARM_IWMMXT_wCGR2 10
1646 #define ARM_IWMMXT_wCGR3 11
1647 
1648 /* V7M CCR bits */
1649 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1650 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1651 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1652 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1653 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1654 FIELD(V7M_CCR, STKALIGN, 9, 1)
1655 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1656 FIELD(V7M_CCR, DC, 16, 1)
1657 FIELD(V7M_CCR, IC, 17, 1)
1658 FIELD(V7M_CCR, BP, 18, 1)
1659 FIELD(V7M_CCR, LOB, 19, 1)
1660 FIELD(V7M_CCR, TRD, 20, 1)
1661 
1662 /* V7M SCR bits */
1663 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1664 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1665 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1666 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1667 
1668 /* V7M AIRCR bits */
1669 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1670 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1671 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1672 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1673 FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1674 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1675 FIELD(V7M_AIRCR, PRIS, 14, 1)
1676 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1677 FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1678 
1679 /* V7M CFSR bits for MMFSR */
1680 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1681 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1682 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1683 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1684 FIELD(V7M_CFSR, MLSPERR, 5, 1)
1685 FIELD(V7M_CFSR, MMARVALID, 7, 1)
1686 
1687 /* V7M CFSR bits for BFSR */
1688 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1689 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1690 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1691 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1692 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1693 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1694 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1695 
1696 /* V7M CFSR bits for UFSR */
1697 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1698 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1699 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1700 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1701 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1702 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1703 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1704 
1705 /* V7M CFSR bit masks covering all of the subregister bits */
1706 FIELD(V7M_CFSR, MMFSR, 0, 8)
1707 FIELD(V7M_CFSR, BFSR, 8, 8)
1708 FIELD(V7M_CFSR, UFSR, 16, 16)
1709 
1710 /* V7M HFSR bits */
1711 FIELD(V7M_HFSR, VECTTBL, 1, 1)
1712 FIELD(V7M_HFSR, FORCED, 30, 1)
1713 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1714 
1715 /* V7M DFSR bits */
1716 FIELD(V7M_DFSR, HALTED, 0, 1)
1717 FIELD(V7M_DFSR, BKPT, 1, 1)
1718 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1719 FIELD(V7M_DFSR, VCATCH, 3, 1)
1720 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1721 
1722 /* V7M SFSR bits */
1723 FIELD(V7M_SFSR, INVEP, 0, 1)
1724 FIELD(V7M_SFSR, INVIS, 1, 1)
1725 FIELD(V7M_SFSR, INVER, 2, 1)
1726 FIELD(V7M_SFSR, AUVIOL, 3, 1)
1727 FIELD(V7M_SFSR, INVTRAN, 4, 1)
1728 FIELD(V7M_SFSR, LSPERR, 5, 1)
1729 FIELD(V7M_SFSR, SFARVALID, 6, 1)
1730 FIELD(V7M_SFSR, LSERR, 7, 1)
1731 
1732 /* v7M MPU_CTRL bits */
1733 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1734 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1735 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1736 
1737 /* v7M CLIDR bits */
1738 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1739 FIELD(V7M_CLIDR, LOUIS, 21, 3)
1740 FIELD(V7M_CLIDR, LOC, 24, 3)
1741 FIELD(V7M_CLIDR, LOUU, 27, 3)
1742 FIELD(V7M_CLIDR, ICB, 30, 2)
1743 
1744 FIELD(V7M_CSSELR, IND, 0, 1)
1745 FIELD(V7M_CSSELR, LEVEL, 1, 3)
1746 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1747  * define a mask for this and check that it doesn't permit running off
1748  * the end of the array.
1749  */
1750 FIELD(V7M_CSSELR, INDEX, 0, 4)
1751 
1752 /* v7M FPCCR bits */
1753 FIELD(V7M_FPCCR, LSPACT, 0, 1)
1754 FIELD(V7M_FPCCR, USER, 1, 1)
1755 FIELD(V7M_FPCCR, S, 2, 1)
1756 FIELD(V7M_FPCCR, THREAD, 3, 1)
1757 FIELD(V7M_FPCCR, HFRDY, 4, 1)
1758 FIELD(V7M_FPCCR, MMRDY, 5, 1)
1759 FIELD(V7M_FPCCR, BFRDY, 6, 1)
1760 FIELD(V7M_FPCCR, SFRDY, 7, 1)
1761 FIELD(V7M_FPCCR, MONRDY, 8, 1)
1762 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1763 FIELD(V7M_FPCCR, UFRDY, 10, 1)
1764 FIELD(V7M_FPCCR, RES0, 11, 15)
1765 FIELD(V7M_FPCCR, TS, 26, 1)
1766 FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1767 FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1768 FIELD(V7M_FPCCR, LSPENS, 29, 1)
1769 FIELD(V7M_FPCCR, LSPEN, 30, 1)
1770 FIELD(V7M_FPCCR, ASPEN, 31, 1)
1771 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
1772 #define R_V7M_FPCCR_BANKED_MASK                 \
1773     (R_V7M_FPCCR_LSPACT_MASK |                  \
1774      R_V7M_FPCCR_USER_MASK |                    \
1775      R_V7M_FPCCR_THREAD_MASK |                  \
1776      R_V7M_FPCCR_MMRDY_MASK |                   \
1777      R_V7M_FPCCR_SPLIMVIOL_MASK |               \
1778      R_V7M_FPCCR_UFRDY_MASK |                   \
1779      R_V7M_FPCCR_ASPEN_MASK)
1780 
1781 /* v7M VPR bits */
1782 FIELD(V7M_VPR, P0, 0, 16)
1783 FIELD(V7M_VPR, MASK01, 16, 4)
1784 FIELD(V7M_VPR, MASK23, 20, 4)
1785 
1786 /*
1787  * System register ID fields.
1788  */
1789 FIELD(CLIDR_EL1, CTYPE1, 0, 3)
1790 FIELD(CLIDR_EL1, CTYPE2, 3, 3)
1791 FIELD(CLIDR_EL1, CTYPE3, 6, 3)
1792 FIELD(CLIDR_EL1, CTYPE4, 9, 3)
1793 FIELD(CLIDR_EL1, CTYPE5, 12, 3)
1794 FIELD(CLIDR_EL1, CTYPE6, 15, 3)
1795 FIELD(CLIDR_EL1, CTYPE7, 18, 3)
1796 FIELD(CLIDR_EL1, LOUIS, 21, 3)
1797 FIELD(CLIDR_EL1, LOC, 24, 3)
1798 FIELD(CLIDR_EL1, LOUU, 27, 3)
1799 FIELD(CLIDR_EL1, ICB, 30, 3)
1800 
1801 /* When FEAT_CCIDX is implemented */
1802 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
1803 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
1804 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
1805 
1806 /* When FEAT_CCIDX is not implemented */
1807 FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
1808 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
1809 FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
1810 
1811 FIELD(CTR_EL0,  IMINLINE, 0, 4)
1812 FIELD(CTR_EL0,  L1IP, 14, 2)
1813 FIELD(CTR_EL0,  DMINLINE, 16, 4)
1814 FIELD(CTR_EL0,  ERG, 20, 4)
1815 FIELD(CTR_EL0,  CWG, 24, 4)
1816 FIELD(CTR_EL0,  IDC, 28, 1)
1817 FIELD(CTR_EL0,  DIC, 29, 1)
1818 FIELD(CTR_EL0,  TMINLINE, 32, 6)
1819 
1820 FIELD(MIDR_EL1, REVISION, 0, 4)
1821 FIELD(MIDR_EL1, PARTNUM, 4, 12)
1822 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
1823 FIELD(MIDR_EL1, VARIANT, 20, 4)
1824 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
1825 
1826 FIELD(ID_ISAR0, SWAP, 0, 4)
1827 FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1828 FIELD(ID_ISAR0, BITFIELD, 8, 4)
1829 FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1830 FIELD(ID_ISAR0, COPROC, 16, 4)
1831 FIELD(ID_ISAR0, DEBUG, 20, 4)
1832 FIELD(ID_ISAR0, DIVIDE, 24, 4)
1833 
1834 FIELD(ID_ISAR1, ENDIAN, 0, 4)
1835 FIELD(ID_ISAR1, EXCEPT, 4, 4)
1836 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1837 FIELD(ID_ISAR1, EXTEND, 12, 4)
1838 FIELD(ID_ISAR1, IFTHEN, 16, 4)
1839 FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1840 FIELD(ID_ISAR1, INTERWORK, 24, 4)
1841 FIELD(ID_ISAR1, JAZELLE, 28, 4)
1842 
1843 FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1844 FIELD(ID_ISAR2, MEMHINT, 4, 4)
1845 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1846 FIELD(ID_ISAR2, MULT, 12, 4)
1847 FIELD(ID_ISAR2, MULTS, 16, 4)
1848 FIELD(ID_ISAR2, MULTU, 20, 4)
1849 FIELD(ID_ISAR2, PSR_AR, 24, 4)
1850 FIELD(ID_ISAR2, REVERSAL, 28, 4)
1851 
1852 FIELD(ID_ISAR3, SATURATE, 0, 4)
1853 FIELD(ID_ISAR3, SIMD, 4, 4)
1854 FIELD(ID_ISAR3, SVC, 8, 4)
1855 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
1856 FIELD(ID_ISAR3, TABBRANCH, 16, 4)
1857 FIELD(ID_ISAR3, T32COPY, 20, 4)
1858 FIELD(ID_ISAR3, TRUENOP, 24, 4)
1859 FIELD(ID_ISAR3, T32EE, 28, 4)
1860 
1861 FIELD(ID_ISAR4, UNPRIV, 0, 4)
1862 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
1863 FIELD(ID_ISAR4, WRITEBACK, 8, 4)
1864 FIELD(ID_ISAR4, SMC, 12, 4)
1865 FIELD(ID_ISAR4, BARRIER, 16, 4)
1866 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
1867 FIELD(ID_ISAR4, PSR_M, 24, 4)
1868 FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
1869 
1870 FIELD(ID_ISAR5, SEVL, 0, 4)
1871 FIELD(ID_ISAR5, AES, 4, 4)
1872 FIELD(ID_ISAR5, SHA1, 8, 4)
1873 FIELD(ID_ISAR5, SHA2, 12, 4)
1874 FIELD(ID_ISAR5, CRC32, 16, 4)
1875 FIELD(ID_ISAR5, RDM, 24, 4)
1876 FIELD(ID_ISAR5, VCMA, 28, 4)
1877 
1878 FIELD(ID_ISAR6, JSCVT, 0, 4)
1879 FIELD(ID_ISAR6, DP, 4, 4)
1880 FIELD(ID_ISAR6, FHM, 8, 4)
1881 FIELD(ID_ISAR6, SB, 12, 4)
1882 FIELD(ID_ISAR6, SPECRES, 16, 4)
1883 FIELD(ID_ISAR6, BF16, 20, 4)
1884 FIELD(ID_ISAR6, I8MM, 24, 4)
1885 
1886 FIELD(ID_MMFR0, VMSA, 0, 4)
1887 FIELD(ID_MMFR0, PMSA, 4, 4)
1888 FIELD(ID_MMFR0, OUTERSHR, 8, 4)
1889 FIELD(ID_MMFR0, SHARELVL, 12, 4)
1890 FIELD(ID_MMFR0, TCM, 16, 4)
1891 FIELD(ID_MMFR0, AUXREG, 20, 4)
1892 FIELD(ID_MMFR0, FCSE, 24, 4)
1893 FIELD(ID_MMFR0, INNERSHR, 28, 4)
1894 
1895 FIELD(ID_MMFR1, L1HVDVA, 0, 4)
1896 FIELD(ID_MMFR1, L1UNIVA, 4, 4)
1897 FIELD(ID_MMFR1, L1HVDSW, 8, 4)
1898 FIELD(ID_MMFR1, L1UNISW, 12, 4)
1899 FIELD(ID_MMFR1, L1HVD, 16, 4)
1900 FIELD(ID_MMFR1, L1UNI, 20, 4)
1901 FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
1902 FIELD(ID_MMFR1, BPRED, 28, 4)
1903 
1904 FIELD(ID_MMFR2, L1HVDFG, 0, 4)
1905 FIELD(ID_MMFR2, L1HVDBG, 4, 4)
1906 FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
1907 FIELD(ID_MMFR2, HVDTLB, 12, 4)
1908 FIELD(ID_MMFR2, UNITLB, 16, 4)
1909 FIELD(ID_MMFR2, MEMBARR, 20, 4)
1910 FIELD(ID_MMFR2, WFISTALL, 24, 4)
1911 FIELD(ID_MMFR2, HWACCFLG, 28, 4)
1912 
1913 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
1914 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
1915 FIELD(ID_MMFR3, BPMAINT, 8, 4)
1916 FIELD(ID_MMFR3, MAINTBCST, 12, 4)
1917 FIELD(ID_MMFR3, PAN, 16, 4)
1918 FIELD(ID_MMFR3, COHWALK, 20, 4)
1919 FIELD(ID_MMFR3, CMEMSZ, 24, 4)
1920 FIELD(ID_MMFR3, SUPERSEC, 28, 4)
1921 
1922 FIELD(ID_MMFR4, SPECSEI, 0, 4)
1923 FIELD(ID_MMFR4, AC2, 4, 4)
1924 FIELD(ID_MMFR4, XNX, 8, 4)
1925 FIELD(ID_MMFR4, CNP, 12, 4)
1926 FIELD(ID_MMFR4, HPDS, 16, 4)
1927 FIELD(ID_MMFR4, LSM, 20, 4)
1928 FIELD(ID_MMFR4, CCIDX, 24, 4)
1929 FIELD(ID_MMFR4, EVT, 28, 4)
1930 
1931 FIELD(ID_MMFR5, ETS, 0, 4)
1932 
1933 FIELD(ID_PFR0, STATE0, 0, 4)
1934 FIELD(ID_PFR0, STATE1, 4, 4)
1935 FIELD(ID_PFR0, STATE2, 8, 4)
1936 FIELD(ID_PFR0, STATE3, 12, 4)
1937 FIELD(ID_PFR0, CSV2, 16, 4)
1938 FIELD(ID_PFR0, AMU, 20, 4)
1939 FIELD(ID_PFR0, DIT, 24, 4)
1940 FIELD(ID_PFR0, RAS, 28, 4)
1941 
1942 FIELD(ID_PFR1, PROGMOD, 0, 4)
1943 FIELD(ID_PFR1, SECURITY, 4, 4)
1944 FIELD(ID_PFR1, MPROGMOD, 8, 4)
1945 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
1946 FIELD(ID_PFR1, GENTIMER, 16, 4)
1947 FIELD(ID_PFR1, SEC_FRAC, 20, 4)
1948 FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
1949 FIELD(ID_PFR1, GIC, 28, 4)
1950 
1951 FIELD(ID_PFR2, CSV3, 0, 4)
1952 FIELD(ID_PFR2, SSBS, 4, 4)
1953 FIELD(ID_PFR2, RAS_FRAC, 8, 4)
1954 
1955 FIELD(ID_AA64ISAR0, AES, 4, 4)
1956 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
1957 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
1958 FIELD(ID_AA64ISAR0, CRC32, 16, 4)
1959 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
1960 FIELD(ID_AA64ISAR0, RDM, 28, 4)
1961 FIELD(ID_AA64ISAR0, SHA3, 32, 4)
1962 FIELD(ID_AA64ISAR0, SM3, 36, 4)
1963 FIELD(ID_AA64ISAR0, SM4, 40, 4)
1964 FIELD(ID_AA64ISAR0, DP, 44, 4)
1965 FIELD(ID_AA64ISAR0, FHM, 48, 4)
1966 FIELD(ID_AA64ISAR0, TS, 52, 4)
1967 FIELD(ID_AA64ISAR0, TLB, 56, 4)
1968 FIELD(ID_AA64ISAR0, RNDR, 60, 4)
1969 
1970 FIELD(ID_AA64ISAR1, DPB, 0, 4)
1971 FIELD(ID_AA64ISAR1, APA, 4, 4)
1972 FIELD(ID_AA64ISAR1, API, 8, 4)
1973 FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
1974 FIELD(ID_AA64ISAR1, FCMA, 16, 4)
1975 FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
1976 FIELD(ID_AA64ISAR1, GPA, 24, 4)
1977 FIELD(ID_AA64ISAR1, GPI, 28, 4)
1978 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
1979 FIELD(ID_AA64ISAR1, SB, 36, 4)
1980 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
1981 FIELD(ID_AA64ISAR1, BF16, 44, 4)
1982 FIELD(ID_AA64ISAR1, DGH, 48, 4)
1983 FIELD(ID_AA64ISAR1, I8MM, 52, 4)
1984 
1985 FIELD(ID_AA64PFR0, EL0, 0, 4)
1986 FIELD(ID_AA64PFR0, EL1, 4, 4)
1987 FIELD(ID_AA64PFR0, EL2, 8, 4)
1988 FIELD(ID_AA64PFR0, EL3, 12, 4)
1989 FIELD(ID_AA64PFR0, FP, 16, 4)
1990 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
1991 FIELD(ID_AA64PFR0, GIC, 24, 4)
1992 FIELD(ID_AA64PFR0, RAS, 28, 4)
1993 FIELD(ID_AA64PFR0, SVE, 32, 4)
1994 FIELD(ID_AA64PFR0, SEL2, 36, 4)
1995 FIELD(ID_AA64PFR0, MPAM, 40, 4)
1996 FIELD(ID_AA64PFR0, AMU, 44, 4)
1997 FIELD(ID_AA64PFR0, DIT, 48, 4)
1998 FIELD(ID_AA64PFR0, CSV2, 56, 4)
1999 FIELD(ID_AA64PFR0, CSV3, 60, 4)
2000 
2001 FIELD(ID_AA64PFR1, BT, 0, 4)
2002 FIELD(ID_AA64PFR1, SSBS, 4, 4)
2003 FIELD(ID_AA64PFR1, MTE, 8, 4)
2004 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
2005 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
2006 
2007 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
2008 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
2009 FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
2010 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
2011 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
2012 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
2013 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
2014 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
2015 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
2016 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
2017 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
2018 FIELD(ID_AA64MMFR0, EXS, 44, 4)
2019 FIELD(ID_AA64MMFR0, FGT, 56, 4)
2020 FIELD(ID_AA64MMFR0, ECV, 60, 4)
2021 
2022 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
2023 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
2024 FIELD(ID_AA64MMFR1, VH, 8, 4)
2025 FIELD(ID_AA64MMFR1, HPDS, 12, 4)
2026 FIELD(ID_AA64MMFR1, LO, 16, 4)
2027 FIELD(ID_AA64MMFR1, PAN, 20, 4)
2028 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
2029 FIELD(ID_AA64MMFR1, XNX, 28, 4)
2030 FIELD(ID_AA64MMFR1, TWED, 32, 4)
2031 FIELD(ID_AA64MMFR1, ETS, 36, 4)
2032 
2033 FIELD(ID_AA64MMFR2, CNP, 0, 4)
2034 FIELD(ID_AA64MMFR2, UAO, 4, 4)
2035 FIELD(ID_AA64MMFR2, LSM, 8, 4)
2036 FIELD(ID_AA64MMFR2, IESB, 12, 4)
2037 FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
2038 FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
2039 FIELD(ID_AA64MMFR2, NV, 24, 4)
2040 FIELD(ID_AA64MMFR2, ST, 28, 4)
2041 FIELD(ID_AA64MMFR2, AT, 32, 4)
2042 FIELD(ID_AA64MMFR2, IDS, 36, 4)
2043 FIELD(ID_AA64MMFR2, FWB, 40, 4)
2044 FIELD(ID_AA64MMFR2, TTL, 48, 4)
2045 FIELD(ID_AA64MMFR2, BBM, 52, 4)
2046 FIELD(ID_AA64MMFR2, EVT, 56, 4)
2047 FIELD(ID_AA64MMFR2, E0PD, 60, 4)
2048 
2049 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
2050 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
2051 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
2052 FIELD(ID_AA64DFR0, BRPS, 12, 4)
2053 FIELD(ID_AA64DFR0, WRPS, 20, 4)
2054 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
2055 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
2056 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
2057 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
2058 FIELD(ID_AA64DFR0, MTPMU, 48, 4)
2059 
2060 FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
2061 FIELD(ID_AA64ZFR0, AES, 4, 4)
2062 FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
2063 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
2064 FIELD(ID_AA64ZFR0, SHA3, 32, 4)
2065 FIELD(ID_AA64ZFR0, SM4, 40, 4)
2066 FIELD(ID_AA64ZFR0, I8MM, 44, 4)
2067 FIELD(ID_AA64ZFR0, F32MM, 52, 4)
2068 FIELD(ID_AA64ZFR0, F64MM, 56, 4)
2069 
2070 FIELD(ID_DFR0, COPDBG, 0, 4)
2071 FIELD(ID_DFR0, COPSDBG, 4, 4)
2072 FIELD(ID_DFR0, MMAPDBG, 8, 4)
2073 FIELD(ID_DFR0, COPTRC, 12, 4)
2074 FIELD(ID_DFR0, MMAPTRC, 16, 4)
2075 FIELD(ID_DFR0, MPROFDBG, 20, 4)
2076 FIELD(ID_DFR0, PERFMON, 24, 4)
2077 FIELD(ID_DFR0, TRACEFILT, 28, 4)
2078 
2079 FIELD(ID_DFR1, MTPMU, 0, 4)
2080 
2081 FIELD(DBGDIDR, SE_IMP, 12, 1)
2082 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
2083 FIELD(DBGDIDR, VERSION, 16, 4)
2084 FIELD(DBGDIDR, CTX_CMPS, 20, 4)
2085 FIELD(DBGDIDR, BRPS, 24, 4)
2086 FIELD(DBGDIDR, WRPS, 28, 4)
2087 
2088 FIELD(MVFR0, SIMDREG, 0, 4)
2089 FIELD(MVFR0, FPSP, 4, 4)
2090 FIELD(MVFR0, FPDP, 8, 4)
2091 FIELD(MVFR0, FPTRAP, 12, 4)
2092 FIELD(MVFR0, FPDIVIDE, 16, 4)
2093 FIELD(MVFR0, FPSQRT, 20, 4)
2094 FIELD(MVFR0, FPSHVEC, 24, 4)
2095 FIELD(MVFR0, FPROUND, 28, 4)
2096 
2097 FIELD(MVFR1, FPFTZ, 0, 4)
2098 FIELD(MVFR1, FPDNAN, 4, 4)
2099 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
2100 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
2101 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
2102 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
2103 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
2104 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
2105 FIELD(MVFR1, FPHP, 24, 4)
2106 FIELD(MVFR1, SIMDFMAC, 28, 4)
2107 
2108 FIELD(MVFR2, SIMDMISC, 0, 4)
2109 FIELD(MVFR2, FPMISC, 4, 4)
2110 
2111 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2112 
2113 /* If adding a feature bit which corresponds to a Linux ELF
2114  * HWCAP bit, remember to update the feature-bit-to-hwcap
2115  * mapping in linux-user/elfload.c:get_elf_hwcap().
2116  */
2117 enum arm_features {
2118     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
2119     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
2120     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
2121     ARM_FEATURE_V6,
2122     ARM_FEATURE_V6K,
2123     ARM_FEATURE_V7,
2124     ARM_FEATURE_THUMB2,
2125     ARM_FEATURE_PMSA,   /* no MMU; may have Memory Protection Unit */
2126     ARM_FEATURE_NEON,
2127     ARM_FEATURE_M, /* Microcontroller profile.  */
2128     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
2129     ARM_FEATURE_THUMB2EE,
2130     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
2131     ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
2132     ARM_FEATURE_V4T,
2133     ARM_FEATURE_V5,
2134     ARM_FEATURE_STRONGARM,
2135     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
2136     ARM_FEATURE_GENERIC_TIMER,
2137     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
2138     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
2139     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
2140     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
2141     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
2142     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
2143     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
2144     ARM_FEATURE_V8,
2145     ARM_FEATURE_AARCH64, /* supports 64 bit mode */
2146     ARM_FEATURE_CBAR, /* has cp15 CBAR */
2147     ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
2148     ARM_FEATURE_EL2, /* has EL2 Virtualization support */
2149     ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
2150     ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
2151     ARM_FEATURE_PMU, /* has PMU support */
2152     ARM_FEATURE_VBAR, /* has cp15 VBAR */
2153     ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
2154     ARM_FEATURE_M_MAIN, /* M profile Main Extension */
2155     ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
2156 };
2157 
2158 static inline int arm_feature(CPUARMState *env, int feature)
2159 {
2160     return (env->features & (1ULL << feature)) != 0;
2161 }
2162 
2163 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
2164 
2165 #if !defined(CONFIG_USER_ONLY)
2166 /* Return true if exception levels below EL3 are in secure state,
2167  * or would be following an exception return to that level.
2168  * Unlike arm_is_secure() (which is always a question about the
2169  * _current_ state of the CPU) this doesn't care about the current
2170  * EL or mode.
2171  */
2172 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2173 {
2174     if (arm_feature(env, ARM_FEATURE_EL3)) {
2175         return !(env->cp15.scr_el3 & SCR_NS);
2176     } else {
2177         /* If EL3 is not supported then the secure state is implementation
2178          * defined, in which case QEMU defaults to non-secure.
2179          */
2180         return false;
2181     }
2182 }
2183 
2184 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
2185 static inline bool arm_is_el3_or_mon(CPUARMState *env)
2186 {
2187     if (arm_feature(env, ARM_FEATURE_EL3)) {
2188         if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2189             /* CPU currently in AArch64 state and EL3 */
2190             return true;
2191         } else if (!is_a64(env) &&
2192                 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2193             /* CPU currently in AArch32 state and monitor mode */
2194             return true;
2195         }
2196     }
2197     return false;
2198 }
2199 
2200 /* Return true if the processor is in secure state */
2201 static inline bool arm_is_secure(CPUARMState *env)
2202 {
2203     if (arm_is_el3_or_mon(env)) {
2204         return true;
2205     }
2206     return arm_is_secure_below_el3(env);
2207 }
2208 
2209 /*
2210  * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
2211  * This corresponds to the pseudocode EL2Enabled()
2212  */
2213 static inline bool arm_is_el2_enabled(CPUARMState *env)
2214 {
2215     if (arm_feature(env, ARM_FEATURE_EL2)) {
2216         if (arm_is_secure_below_el3(env)) {
2217             return (env->cp15.scr_el3 & SCR_EEL2) != 0;
2218         }
2219         return true;
2220     }
2221     return false;
2222 }
2223 
2224 #else
2225 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2226 {
2227     return false;
2228 }
2229 
2230 static inline bool arm_is_secure(CPUARMState *env)
2231 {
2232     return false;
2233 }
2234 
2235 static inline bool arm_is_el2_enabled(CPUARMState *env)
2236 {
2237     return false;
2238 }
2239 #endif
2240 
2241 /**
2242  * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
2243  * E.g. when in secure state, fields in HCR_EL2 are suppressed,
2244  * "for all purposes other than a direct read or write access of HCR_EL2."
2245  * Not included here is HCR_RW.
2246  */
2247 uint64_t arm_hcr_el2_eff(CPUARMState *env);
2248 
2249 /* Return true if the specified exception level is running in AArch64 state. */
2250 static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2251 {
2252     /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
2253      * and if we're not in EL0 then the state of EL0 isn't well defined.)
2254      */
2255     assert(el >= 1 && el <= 3);
2256     bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2257 
2258     /* The highest exception level is always at the maximum supported
2259      * register width, and then lower levels have a register width controlled
2260      * by bits in the SCR or HCR registers.
2261      */
2262     if (el == 3) {
2263         return aa64;
2264     }
2265 
2266     if (arm_feature(env, ARM_FEATURE_EL3) &&
2267         ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
2268         aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2269     }
2270 
2271     if (el == 2) {
2272         return aa64;
2273     }
2274 
2275     if (arm_is_el2_enabled(env)) {
2276         aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2277     }
2278 
2279     return aa64;
2280 }
2281 
2282 /* Function for determing whether guest cp register reads and writes should
2283  * access the secure or non-secure bank of a cp register.  When EL3 is
2284  * operating in AArch32 state, the NS-bit determines whether the secure
2285  * instance of a cp register should be used. When EL3 is AArch64 (or if
2286  * it doesn't exist at all) then there is no register banking, and all
2287  * accesses are to the non-secure version.
2288  */
2289 static inline bool access_secure_reg(CPUARMState *env)
2290 {
2291     bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2292                 !arm_el_is_aa64(env, 3) &&
2293                 !(env->cp15.scr_el3 & SCR_NS));
2294 
2295     return ret;
2296 }
2297 
2298 /* Macros for accessing a specified CP register bank */
2299 #define A32_BANKED_REG_GET(_env, _regname, _secure)    \
2300     ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2301 
2302 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val)   \
2303     do {                                                \
2304         if (_secure) {                                   \
2305             (_env)->cp15._regname##_s = (_val);            \
2306         } else {                                        \
2307             (_env)->cp15._regname##_ns = (_val);           \
2308         }                                               \
2309     } while (0)
2310 
2311 /* Macros for automatically accessing a specific CP register bank depending on
2312  * the current secure state of the system.  These macros are not intended for
2313  * supporting instruction translation reads/writes as these are dependent
2314  * solely on the SCR.NS bit and not the mode.
2315  */
2316 #define A32_BANKED_CURRENT_REG_GET(_env, _regname)        \
2317     A32_BANKED_REG_GET((_env), _regname,                \
2318                        (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2319 
2320 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val)                       \
2321     A32_BANKED_REG_SET((_env), _regname,                                    \
2322                        (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2323                        (_val))
2324 
2325 void arm_cpu_list(void);
2326 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2327                                  uint32_t cur_el, bool secure);
2328 
2329 /* Interface between CPU and Interrupt controller.  */
2330 #ifndef CONFIG_USER_ONLY
2331 bool armv7m_nvic_can_take_pending_exception(void *opaque);
2332 #else
2333 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
2334 {
2335     return true;
2336 }
2337 #endif
2338 /**
2339  * armv7m_nvic_set_pending: mark the specified exception as pending
2340  * @opaque: the NVIC
2341  * @irq: the exception number to mark pending
2342  * @secure: false for non-banked exceptions or for the nonsecure
2343  * version of a banked exception, true for the secure version of a banked
2344  * exception.
2345  *
2346  * Marks the specified exception as pending. Note that we will assert()
2347  * if @secure is true and @irq does not specify one of the fixed set
2348  * of architecturally banked exceptions.
2349  */
2350 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
2351 /**
2352  * armv7m_nvic_set_pending_derived: mark this derived exception as pending
2353  * @opaque: the NVIC
2354  * @irq: the exception number to mark pending
2355  * @secure: false for non-banked exceptions or for the nonsecure
2356  * version of a banked exception, true for the secure version of a banked
2357  * exception.
2358  *
2359  * Similar to armv7m_nvic_set_pending(), but specifically for derived
2360  * exceptions (exceptions generated in the course of trying to take
2361  * a different exception).
2362  */
2363 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
2364 /**
2365  * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
2366  * @opaque: the NVIC
2367  * @irq: the exception number to mark pending
2368  * @secure: false for non-banked exceptions or for the nonsecure
2369  * version of a banked exception, true for the secure version of a banked
2370  * exception.
2371  *
2372  * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
2373  * generated in the course of lazy stacking of FP registers.
2374  */
2375 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
2376 /**
2377  * armv7m_nvic_get_pending_irq_info: return highest priority pending
2378  *    exception, and whether it targets Secure state
2379  * @opaque: the NVIC
2380  * @pirq: set to pending exception number
2381  * @ptargets_secure: set to whether pending exception targets Secure
2382  *
2383  * This function writes the number of the highest priority pending
2384  * exception (the one which would be made active by
2385  * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
2386  * to true if the current highest priority pending exception should
2387  * be taken to Secure state, false for NS.
2388  */
2389 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
2390                                       bool *ptargets_secure);
2391 /**
2392  * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
2393  * @opaque: the NVIC
2394  *
2395  * Move the current highest priority pending exception from the pending
2396  * state to the active state, and update v7m.exception to indicate that
2397  * it is the exception currently being handled.
2398  */
2399 void armv7m_nvic_acknowledge_irq(void *opaque);
2400 /**
2401  * armv7m_nvic_complete_irq: complete specified interrupt or exception
2402  * @opaque: the NVIC
2403  * @irq: the exception number to complete
2404  * @secure: true if this exception was secure
2405  *
2406  * Returns: -1 if the irq was not active
2407  *           1 if completing this irq brought us back to base (no active irqs)
2408  *           0 if there is still an irq active after this one was completed
2409  * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
2410  */
2411 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2412 /**
2413  * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
2414  * @opaque: the NVIC
2415  * @irq: the exception number to mark pending
2416  * @secure: false for non-banked exceptions or for the nonsecure
2417  * version of a banked exception, true for the secure version of a banked
2418  * exception.
2419  *
2420  * Return whether an exception is "ready", i.e. whether the exception is
2421  * enabled and is configured at a priority which would allow it to
2422  * interrupt the current execution priority. This controls whether the
2423  * RDY bit for it in the FPCCR is set.
2424  */
2425 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
2426 /**
2427  * armv7m_nvic_raw_execution_priority: return the raw execution priority
2428  * @opaque: the NVIC
2429  *
2430  * Returns: the raw execution priority as defined by the v8M architecture.
2431  * This is the execution priority minus the effects of AIRCR.PRIS,
2432  * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
2433  * (v8M ARM ARM I_PKLD.)
2434  */
2435 int armv7m_nvic_raw_execution_priority(void *opaque);
2436 /**
2437  * armv7m_nvic_neg_prio_requested: return true if the requested execution
2438  * priority is negative for the specified security state.
2439  * @opaque: the NVIC
2440  * @secure: the security state to test
2441  * This corresponds to the pseudocode IsReqExecPriNeg().
2442  */
2443 #ifndef CONFIG_USER_ONLY
2444 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2445 #else
2446 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2447 {
2448     return false;
2449 }
2450 #endif
2451 
2452 /* Interface for defining coprocessor registers.
2453  * Registers are defined in tables of arm_cp_reginfo structs
2454  * which are passed to define_arm_cp_regs().
2455  */
2456 
2457 /* When looking up a coprocessor register we look for it
2458  * via an integer which encodes all of:
2459  *  coprocessor number
2460  *  Crn, Crm, opc1, opc2 fields
2461  *  32 or 64 bit register (ie is it accessed via MRC/MCR
2462  *    or via MRRC/MCRR?)
2463  *  non-secure/secure bank (AArch32 only)
2464  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
2465  * (In this case crn and opc2 should be zero.)
2466  * For AArch64, there is no 32/64 bit size distinction;
2467  * instead all registers have a 2 bit op0, 3 bit op1 and op2,
2468  * and 4 bit CRn and CRm. The encoding patterns are chosen
2469  * to be easy to convert to and from the KVM encodings, and also
2470  * so that the hashtable can contain both AArch32 and AArch64
2471  * registers (to allow for interprocessing where we might run
2472  * 32 bit code on a 64 bit core).
2473  */
2474 /* This bit is private to our hashtable cpreg; in KVM register
2475  * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
2476  * in the upper bits of the 64 bit ID.
2477  */
2478 #define CP_REG_AA64_SHIFT 28
2479 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2480 
2481 /* To enable banking of coprocessor registers depending on ns-bit we
2482  * add a bit to distinguish between secure and non-secure cpregs in the
2483  * hashtable.
2484  */
2485 #define CP_REG_NS_SHIFT 29
2486 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2487 
2488 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
2489     ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
2490      ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2491 
2492 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2493     (CP_REG_AA64_MASK |                                 \
2494      ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
2495      ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
2496      ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
2497      ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
2498      ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
2499      ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2500 
2501 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
2502  * version used as a key for the coprocessor register hashtable
2503  */
2504 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2505 {
2506     uint32_t cpregid = kvmid;
2507     if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2508         cpregid |= CP_REG_AA64_MASK;
2509     } else {
2510         if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2511             cpregid |= (1 << 15);
2512         }
2513 
2514         /* KVM is always non-secure so add the NS flag on AArch32 register
2515          * entries.
2516          */
2517          cpregid |= 1 << CP_REG_NS_SHIFT;
2518     }
2519     return cpregid;
2520 }
2521 
2522 /* Convert a truncated 32 bit hashtable key into the full
2523  * 64 bit KVM register ID.
2524  */
2525 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2526 {
2527     uint64_t kvmid;
2528 
2529     if (cpregid & CP_REG_AA64_MASK) {
2530         kvmid = cpregid & ~CP_REG_AA64_MASK;
2531         kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2532     } else {
2533         kvmid = cpregid & ~(1 << 15);
2534         if (cpregid & (1 << 15)) {
2535             kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2536         } else {
2537             kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2538         }
2539     }
2540     return kvmid;
2541 }
2542 
2543 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
2544  * special-behaviour cp reg and bits [11..8] indicate what behaviour
2545  * it has. Otherwise it is a simple cp reg, where CONST indicates that
2546  * TCG can assume the value to be constant (ie load at translate time)
2547  * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
2548  * indicates that the TB should not be ended after a write to this register
2549  * (the default is that the TB ends after cp writes). OVERRIDE permits
2550  * a register definition to override a previous definition for the
2551  * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
2552  * old must have the OVERRIDE bit set.
2553  * ALIAS indicates that this register is an alias view of some underlying
2554  * state which is also visible via another register, and that the other
2555  * register is handling migration and reset; registers marked ALIAS will not be
2556  * migrated but may have their state set by syncing of register state from KVM.
2557  * NO_RAW indicates that this register has no underlying state and does not
2558  * support raw access for state saving/loading; it will not be used for either
2559  * migration or KVM state synchronization. (Typically this is for "registers"
2560  * which are actually used as instructions for cache maintenance and so on.)
2561  * IO indicates that this register does I/O and therefore its accesses
2562  * need to be marked with gen_io_start() and also end the TB. In particular,
2563  * registers which implement clocks or timers require this.
2564  * RAISES_EXC is for when the read or write hook might raise an exception;
2565  * the generated code will synchronize the CPU state before calling the hook
2566  * so that it is safe for the hook to call raise_exception().
2567  * NEWEL is for writes to registers that might change the exception
2568  * level - typically on older ARM chips. For those cases we need to
2569  * re-read the new el when recomputing the translation flags.
2570  */
2571 #define ARM_CP_SPECIAL           0x0001
2572 #define ARM_CP_CONST             0x0002
2573 #define ARM_CP_64BIT             0x0004
2574 #define ARM_CP_SUPPRESS_TB_END   0x0008
2575 #define ARM_CP_OVERRIDE          0x0010
2576 #define ARM_CP_ALIAS             0x0020
2577 #define ARM_CP_IO                0x0040
2578 #define ARM_CP_NO_RAW            0x0080
2579 #define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
2580 #define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
2581 #define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
2582 #define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
2583 #define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
2584 #define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
2585 #define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
2586 #define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
2587 #define ARM_CP_FPU               0x1000
2588 #define ARM_CP_SVE               0x2000
2589 #define ARM_CP_NO_GDB            0x4000
2590 #define ARM_CP_RAISES_EXC        0x8000
2591 #define ARM_CP_NEWEL             0x10000
2592 /* Used only as a terminator for ARMCPRegInfo lists */
2593 #define ARM_CP_SENTINEL          0xfffff
2594 /* Mask of only the flag bits in a type field */
2595 #define ARM_CP_FLAG_MASK         0x1f0ff
2596 
2597 /* Valid values for ARMCPRegInfo state field, indicating which of
2598  * the AArch32 and AArch64 execution states this register is visible in.
2599  * If the reginfo doesn't explicitly specify then it is AArch32 only.
2600  * If the reginfo is declared to be visible in both states then a second
2601  * reginfo is synthesised for the AArch32 view of the AArch64 register,
2602  * such that the AArch32 view is the lower 32 bits of the AArch64 one.
2603  * Note that we rely on the values of these enums as we iterate through
2604  * the various states in some places.
2605  */
2606 enum {
2607     ARM_CP_STATE_AA32 = 0,
2608     ARM_CP_STATE_AA64 = 1,
2609     ARM_CP_STATE_BOTH = 2,
2610 };
2611 
2612 /* ARM CP register secure state flags.  These flags identify security state
2613  * attributes for a given CP register entry.
2614  * The existence of both or neither secure and non-secure flags indicates that
2615  * the register has both a secure and non-secure hash entry.  A single one of
2616  * these flags causes the register to only be hashed for the specified
2617  * security state.
2618  * Although definitions may have any combination of the S/NS bits, each
2619  * registered entry will only have one to identify whether the entry is secure
2620  * or non-secure.
2621  */
2622 enum {
2623     ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
2624     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
2625 };
2626 
2627 /* Return true if cptype is a valid type field. This is used to try to
2628  * catch errors where the sentinel has been accidentally left off the end
2629  * of a list of registers.
2630  */
2631 static inline bool cptype_valid(int cptype)
2632 {
2633     return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
2634         || ((cptype & ARM_CP_SPECIAL) &&
2635             ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
2636 }
2637 
2638 /* Access rights:
2639  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
2640  * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
2641  * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
2642  * (ie any of the privileged modes in Secure state, or Monitor mode).
2643  * If a register is accessible in one privilege level it's always accessible
2644  * in higher privilege levels too. Since "Secure PL1" also follows this rule
2645  * (ie anything visible in PL2 is visible in S-PL1, some things are only
2646  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
2647  * terminology a little and call this PL3.
2648  * In AArch64 things are somewhat simpler as the PLx bits line up exactly
2649  * with the ELx exception levels.
2650  *
2651  * If access permissions for a register are more complex than can be
2652  * described with these bits, then use a laxer set of restrictions, and
2653  * do the more restrictive/complex check inside a helper function.
2654  */
2655 #define PL3_R 0x80
2656 #define PL3_W 0x40
2657 #define PL2_R (0x20 | PL3_R)
2658 #define PL2_W (0x10 | PL3_W)
2659 #define PL1_R (0x08 | PL2_R)
2660 #define PL1_W (0x04 | PL2_W)
2661 #define PL0_R (0x02 | PL1_R)
2662 #define PL0_W (0x01 | PL1_W)
2663 
2664 /*
2665  * For user-mode some registers are accessible to EL0 via a kernel
2666  * trap-and-emulate ABI. In this case we define the read permissions
2667  * as actually being PL0_R. However some bits of any given register
2668  * may still be masked.
2669  */
2670 #ifdef CONFIG_USER_ONLY
2671 #define PL0U_R PL0_R
2672 #else
2673 #define PL0U_R PL1_R
2674 #endif
2675 
2676 #define PL3_RW (PL3_R | PL3_W)
2677 #define PL2_RW (PL2_R | PL2_W)
2678 #define PL1_RW (PL1_R | PL1_W)
2679 #define PL0_RW (PL0_R | PL0_W)
2680 
2681 /* Return the highest implemented Exception Level */
2682 static inline int arm_highest_el(CPUARMState *env)
2683 {
2684     if (arm_feature(env, ARM_FEATURE_EL3)) {
2685         return 3;
2686     }
2687     if (arm_feature(env, ARM_FEATURE_EL2)) {
2688         return 2;
2689     }
2690     return 1;
2691 }
2692 
2693 /* Return true if a v7M CPU is in Handler mode */
2694 static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2695 {
2696     return env->v7m.exception != 0;
2697 }
2698 
2699 /* Return the current Exception Level (as per ARMv8; note that this differs
2700  * from the ARMv7 Privilege Level).
2701  */
2702 static inline int arm_current_el(CPUARMState *env)
2703 {
2704     if (arm_feature(env, ARM_FEATURE_M)) {
2705         return arm_v7m_is_handler_mode(env) ||
2706             !(env->v7m.control[env->v7m.secure] & 1);
2707     }
2708 
2709     if (is_a64(env)) {
2710         return extract32(env->pstate, 2, 2);
2711     }
2712 
2713     switch (env->uncached_cpsr & 0x1f) {
2714     case ARM_CPU_MODE_USR:
2715         return 0;
2716     case ARM_CPU_MODE_HYP:
2717         return 2;
2718     case ARM_CPU_MODE_MON:
2719         return 3;
2720     default:
2721         if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2722             /* If EL3 is 32-bit then all secure privileged modes run in
2723              * EL3
2724              */
2725             return 3;
2726         }
2727 
2728         return 1;
2729     }
2730 }
2731 
2732 typedef struct ARMCPRegInfo ARMCPRegInfo;
2733 
2734 typedef enum CPAccessResult {
2735     /* Access is permitted */
2736     CP_ACCESS_OK = 0,
2737     /* Access fails due to a configurable trap or enable which would
2738      * result in a categorized exception syndrome giving information about
2739      * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
2740      * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
2741      * PL1 if in EL0, otherwise to the current EL).
2742      */
2743     CP_ACCESS_TRAP = 1,
2744     /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
2745      * Note that this is not a catch-all case -- the set of cases which may
2746      * result in this failure is specifically defined by the architecture.
2747      */
2748     CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2749     /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
2750     CP_ACCESS_TRAP_EL2 = 3,
2751     CP_ACCESS_TRAP_EL3 = 4,
2752     /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
2753     CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2754     CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2755     /* Access fails and results in an exception syndrome for an FP access,
2756      * trapped directly to EL2 or EL3
2757      */
2758     CP_ACCESS_TRAP_FP_EL2 = 7,
2759     CP_ACCESS_TRAP_FP_EL3 = 8,
2760 } CPAccessResult;
2761 
2762 /* Access functions for coprocessor registers. These cannot fail and
2763  * may not raise exceptions.
2764  */
2765 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2766 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2767                        uint64_t value);
2768 /* Access permission check functions for coprocessor registers. */
2769 typedef CPAccessResult CPAccessFn(CPUARMState *env,
2770                                   const ARMCPRegInfo *opaque,
2771                                   bool isread);
2772 /* Hook function for register reset */
2773 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2774 
2775 #define CP_ANY 0xff
2776 
2777 /* Definition of an ARM coprocessor register */
2778 struct ARMCPRegInfo {
2779     /* Name of register (useful mainly for debugging, need not be unique) */
2780     const char *name;
2781     /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
2782      * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
2783      * 'wildcard' field -- any value of that field in the MRC/MCR insn
2784      * will be decoded to this register. The register read and write
2785      * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
2786      * used by the program, so it is possible to register a wildcard and
2787      * then behave differently on read/write if necessary.
2788      * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
2789      * must both be zero.
2790      * For AArch64-visible registers, opc0 is also used.
2791      * Since there are no "coprocessors" in AArch64, cp is purely used as a
2792      * way to distinguish (for KVM's benefit) guest-visible system registers
2793      * from demuxed ones provided to preserve the "no side effects on
2794      * KVM register read/write from QEMU" semantics. cp==0x13 is guest
2795      * visible (to match KVM's encoding); cp==0 will be converted to
2796      * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
2797      */
2798     uint8_t cp;
2799     uint8_t crn;
2800     uint8_t crm;
2801     uint8_t opc0;
2802     uint8_t opc1;
2803     uint8_t opc2;
2804     /* Execution state in which this register is visible: ARM_CP_STATE_* */
2805     int state;
2806     /* Register type: ARM_CP_* bits/values */
2807     int type;
2808     /* Access rights: PL*_[RW] */
2809     int access;
2810     /* Security state: ARM_CP_SECSTATE_* bits/values */
2811     int secure;
2812     /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
2813      * this register was defined: can be used to hand data through to the
2814      * register read/write functions, since they are passed the ARMCPRegInfo*.
2815      */
2816     void *opaque;
2817     /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
2818      * fieldoffset is non-zero, the reset value of the register.
2819      */
2820     uint64_t resetvalue;
2821     /* Offset of the field in CPUARMState for this register.
2822      *
2823      * This is not needed if either:
2824      *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
2825      *  2. both readfn and writefn are specified
2826      */
2827     ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
2828 
2829     /* Offsets of the secure and non-secure fields in CPUARMState for the
2830      * register if it is banked.  These fields are only used during the static
2831      * registration of a register.  During hashing the bank associated
2832      * with a given security state is copied to fieldoffset which is used from
2833      * there on out.
2834      *
2835      * It is expected that register definitions use either fieldoffset or
2836      * bank_fieldoffsets in the definition but not both.  It is also expected
2837      * that both bank offsets are set when defining a banked register.  This
2838      * use indicates that a register is banked.
2839      */
2840     ptrdiff_t bank_fieldoffsets[2];
2841 
2842     /* Function for making any access checks for this register in addition to
2843      * those specified by the 'access' permissions bits. If NULL, no extra
2844      * checks required. The access check is performed at runtime, not at
2845      * translate time.
2846      */
2847     CPAccessFn *accessfn;
2848     /* Function for handling reads of this register. If NULL, then reads
2849      * will be done by loading from the offset into CPUARMState specified
2850      * by fieldoffset.
2851      */
2852     CPReadFn *readfn;
2853     /* Function for handling writes of this register. If NULL, then writes
2854      * will be done by writing to the offset into CPUARMState specified
2855      * by fieldoffset.
2856      */
2857     CPWriteFn *writefn;
2858     /* Function for doing a "raw" read; used when we need to copy
2859      * coprocessor state to the kernel for KVM or out for
2860      * migration. This only needs to be provided if there is also a
2861      * readfn and it has side effects (for instance clear-on-read bits).
2862      */
2863     CPReadFn *raw_readfn;
2864     /* Function for doing a "raw" write; used when we need to copy KVM
2865      * kernel coprocessor state into userspace, or for inbound
2866      * migration. This only needs to be provided if there is also a
2867      * writefn and it masks out "unwritable" bits or has write-one-to-clear
2868      * or similar behaviour.
2869      */
2870     CPWriteFn *raw_writefn;
2871     /* Function for resetting the register. If NULL, then reset will be done
2872      * by writing resetvalue to the field specified in fieldoffset. If
2873      * fieldoffset is 0 then no reset will be done.
2874      */
2875     CPResetFn *resetfn;
2876 
2877     /*
2878      * "Original" writefn and readfn.
2879      * For ARMv8.1-VHE register aliases, we overwrite the read/write
2880      * accessor functions of various EL1/EL0 to perform the runtime
2881      * check for which sysreg should actually be modified, and then
2882      * forwards the operation.  Before overwriting the accessors,
2883      * the original function is copied here, so that accesses that
2884      * really do go to the EL1/EL0 version proceed normally.
2885      * (The corresponding EL2 register is linked via opaque.)
2886      */
2887     CPReadFn *orig_readfn;
2888     CPWriteFn *orig_writefn;
2889 };
2890 
2891 /* Macros which are lvalues for the field in CPUARMState for the
2892  * ARMCPRegInfo *ri.
2893  */
2894 #define CPREG_FIELD32(env, ri) \
2895     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2896 #define CPREG_FIELD64(env, ri) \
2897     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2898 
2899 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2900 
2901 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2902                                     const ARMCPRegInfo *regs, void *opaque);
2903 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2904                                        const ARMCPRegInfo *regs, void *opaque);
2905 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2906 {
2907     define_arm_cp_regs_with_opaque(cpu, regs, 0);
2908 }
2909 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2910 {
2911     define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2912 }
2913 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2914 
2915 /*
2916  * Definition of an ARM co-processor register as viewed from
2917  * userspace. This is used for presenting sanitised versions of
2918  * registers to userspace when emulating the Linux AArch64 CPU
2919  * ID/feature ABI (advertised as HWCAP_CPUID).
2920  */
2921 typedef struct ARMCPRegUserSpaceInfo {
2922     /* Name of register */
2923     const char *name;
2924 
2925     /* Is the name actually a glob pattern */
2926     bool is_glob;
2927 
2928     /* Only some bits are exported to user space */
2929     uint64_t exported_bits;
2930 
2931     /* Fixed bits are applied after the mask */
2932     uint64_t fixed_bits;
2933 } ARMCPRegUserSpaceInfo;
2934 
2935 #define REGUSERINFO_SENTINEL { .name = NULL }
2936 
2937 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
2938 
2939 /* CPWriteFn that can be used to implement writes-ignored behaviour */
2940 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2941                          uint64_t value);
2942 /* CPReadFn that can be used for read-as-zero behaviour */
2943 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2944 
2945 /* CPResetFn that does nothing, for use if no reset is required even
2946  * if fieldoffset is non zero.
2947  */
2948 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2949 
2950 /* Return true if this reginfo struct's field in the cpu state struct
2951  * is 64 bits wide.
2952  */
2953 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2954 {
2955     return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2956 }
2957 
2958 static inline bool cp_access_ok(int current_el,
2959                                 const ARMCPRegInfo *ri, int isread)
2960 {
2961     return (ri->access >> ((current_el * 2) + isread)) & 1;
2962 }
2963 
2964 /* Raw read of a coprocessor register (as needed for migration, etc) */
2965 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2966 
2967 /**
2968  * write_list_to_cpustate
2969  * @cpu: ARMCPU
2970  *
2971  * For each register listed in the ARMCPU cpreg_indexes list, write
2972  * its value from the cpreg_values list into the ARMCPUState structure.
2973  * This updates TCG's working data structures from KVM data or
2974  * from incoming migration state.
2975  *
2976  * Returns: true if all register values were updated correctly,
2977  * false if some register was unknown or could not be written.
2978  * Note that we do not stop early on failure -- we will attempt
2979  * writing all registers in the list.
2980  */
2981 bool write_list_to_cpustate(ARMCPU *cpu);
2982 
2983 /**
2984  * write_cpustate_to_list:
2985  * @cpu: ARMCPU
2986  * @kvm_sync: true if this is for syncing back to KVM
2987  *
2988  * For each register listed in the ARMCPU cpreg_indexes list, write
2989  * its value from the ARMCPUState structure into the cpreg_values list.
2990  * This is used to copy info from TCG's working data structures into
2991  * KVM or for outbound migration.
2992  *
2993  * @kvm_sync is true if we are doing this in order to sync the
2994  * register state back to KVM. In this case we will only update
2995  * values in the list if the previous list->cpustate sync actually
2996  * successfully wrote the CPU state. Otherwise we will keep the value
2997  * that is in the list.
2998  *
2999  * Returns: true if all register values were read correctly,
3000  * false if some register was unknown or could not be read.
3001  * Note that we do not stop early on failure -- we will attempt
3002  * reading all registers in the list.
3003  */
3004 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
3005 
3006 #define ARM_CPUID_TI915T      0x54029152
3007 #define ARM_CPUID_TI925T      0x54029252
3008 
3009 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
3010 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
3011 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
3012 
3013 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
3014 
3015 #define cpu_list arm_cpu_list
3016 
3017 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
3018  *
3019  * If EL3 is 64-bit:
3020  *  + NonSecure EL1 & 0 stage 1
3021  *  + NonSecure EL1 & 0 stage 2
3022  *  + NonSecure EL2
3023  *  + NonSecure EL2 & 0   (ARMv8.1-VHE)
3024  *  + Secure EL1 & 0
3025  *  + Secure EL3
3026  * If EL3 is 32-bit:
3027  *  + NonSecure PL1 & 0 stage 1
3028  *  + NonSecure PL1 & 0 stage 2
3029  *  + NonSecure PL2
3030  *  + Secure PL0
3031  *  + Secure PL1
3032  * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
3033  *
3034  * For QEMU, an mmu_idx is not quite the same as a translation regime because:
3035  *  1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
3036  *     because they may differ in access permissions even if the VA->PA map is
3037  *     the same
3038  *  2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
3039  *     translation, which means that we have one mmu_idx that deals with two
3040  *     concatenated translation regimes [this sort of combined s1+2 TLB is
3041  *     architecturally permitted]
3042  *  3. we don't need to allocate an mmu_idx to translations that we won't be
3043  *     handling via the TLB. The only way to do a stage 1 translation without
3044  *     the immediate stage 2 translation is via the ATS or AT system insns,
3045  *     which can be slow-pathed and always do a page table walk.
3046  *     The only use of stage 2 translations is either as part of an s1+2
3047  *     lookup or when loading the descriptors during a stage 1 page table walk,
3048  *     and in both those cases we don't use the TLB.
3049  *  4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
3050  *     translation regimes, because they map reasonably well to each other
3051  *     and they can't both be active at the same time.
3052  *  5. we want to be able to use the TLB for accesses done as part of a
3053  *     stage1 page table walk, rather than having to walk the stage2 page
3054  *     table over and over.
3055  *  6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
3056  *     Never (PAN) bit within PSTATE.
3057  *
3058  * This gives us the following list of cases:
3059  *
3060  * NS EL0 EL1&0 stage 1+2 (aka NS PL0)
3061  * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
3062  * NS EL1 EL1&0 stage 1+2 +PAN
3063  * NS EL0 EL2&0
3064  * NS EL2 EL2&0
3065  * NS EL2 EL2&0 +PAN
3066  * NS EL2 (aka NS PL2)
3067  * S EL0 EL1&0 (aka S PL0)
3068  * S EL1 EL1&0 (not used if EL3 is 32 bit)
3069  * S EL1 EL1&0 +PAN
3070  * S EL3 (aka S PL1)
3071  *
3072  * for a total of 11 different mmu_idx.
3073  *
3074  * R profile CPUs have an MPU, but can use the same set of MMU indexes
3075  * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
3076  * NS EL2 if we ever model a Cortex-R52).
3077  *
3078  * M profile CPUs are rather different as they do not have a true MMU.
3079  * They have the following different MMU indexes:
3080  *  User
3081  *  Privileged
3082  *  User, execution priority negative (ie the MPU HFNMIENA bit may apply)
3083  *  Privileged, execution priority negative (ditto)
3084  * If the CPU supports the v8M Security Extension then there are also:
3085  *  Secure User
3086  *  Secure Privileged
3087  *  Secure User, execution priority negative
3088  *  Secure Privileged, execution priority negative
3089  *
3090  * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
3091  * are not quite the same -- different CPU types (most notably M profile
3092  * vs A/R profile) would like to use MMU indexes with different semantics,
3093  * but since we don't ever need to use all of those in a single CPU we
3094  * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
3095  * modes + total number of M profile MMU modes". The lower bits of
3096  * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
3097  * the same for any particular CPU.
3098  * Variables of type ARMMUIdx are always full values, and the core
3099  * index values are in variables of type 'int'.
3100  *
3101  * Our enumeration includes at the end some entries which are not "true"
3102  * mmu_idx values in that they don't have corresponding TLBs and are only
3103  * valid for doing slow path page table walks.
3104  *
3105  * The constant names here are patterned after the general style of the names
3106  * of the AT/ATS operations.
3107  * The values used are carefully arranged to make mmu_idx => EL lookup easy.
3108  * For M profile we arrange them to have a bit for priv, a bit for negpri
3109  * and a bit for secure.
3110  */
3111 #define ARM_MMU_IDX_A     0x10  /* A profile */
3112 #define ARM_MMU_IDX_NOTLB 0x20  /* does not have a TLB */
3113 #define ARM_MMU_IDX_M     0x40  /* M profile */
3114 
3115 /* Meanings of the bits for A profile mmu idx values */
3116 #define ARM_MMU_IDX_A_NS     0x8
3117 
3118 /* Meanings of the bits for M profile mmu idx values */
3119 #define ARM_MMU_IDX_M_PRIV   0x1
3120 #define ARM_MMU_IDX_M_NEGPRI 0x2
3121 #define ARM_MMU_IDX_M_S      0x4  /* Secure */
3122 
3123 #define ARM_MMU_IDX_TYPE_MASK \
3124     (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
3125 #define ARM_MMU_IDX_COREIDX_MASK 0xf
3126 
3127 typedef enum ARMMMUIdx {
3128     /*
3129      * A-profile.
3130      */
3131     ARMMMUIdx_SE10_0     =  0 | ARM_MMU_IDX_A,
3132     ARMMMUIdx_SE20_0     =  1 | ARM_MMU_IDX_A,
3133     ARMMMUIdx_SE10_1     =  2 | ARM_MMU_IDX_A,
3134     ARMMMUIdx_SE20_2     =  3 | ARM_MMU_IDX_A,
3135     ARMMMUIdx_SE10_1_PAN =  4 | ARM_MMU_IDX_A,
3136     ARMMMUIdx_SE20_2_PAN =  5 | ARM_MMU_IDX_A,
3137     ARMMMUIdx_SE2        =  6 | ARM_MMU_IDX_A,
3138     ARMMMUIdx_SE3        =  7 | ARM_MMU_IDX_A,
3139 
3140     ARMMMUIdx_E10_0     = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS,
3141     ARMMMUIdx_E20_0     = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS,
3142     ARMMMUIdx_E10_1     = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS,
3143     ARMMMUIdx_E20_2     = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS,
3144     ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS,
3145     ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS,
3146     ARMMMUIdx_E2        = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS,
3147 
3148     /*
3149      * These are not allocated TLBs and are used only for AT system
3150      * instructions or for the first stage of an S12 page table walk.
3151      */
3152     ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
3153     ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
3154     ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
3155     ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB,
3156     ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB,
3157     ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB,
3158     /*
3159      * Not allocated a TLB: used only for second stage of an S12 page
3160      * table walk, or for descriptor loads during first stage of an S1
3161      * page table walk. Note that if we ever want to have a TLB for this
3162      * then various TLB flush insns which currently are no-ops or flush
3163      * only stage 1 MMU indexes will need to change to flush stage 2.
3164      */
3165     ARMMMUIdx_Stage2     = 6 | ARM_MMU_IDX_NOTLB,
3166     ARMMMUIdx_Stage2_S   = 7 | ARM_MMU_IDX_NOTLB,
3167 
3168     /*
3169      * M-profile.
3170      */
3171     ARMMMUIdx_MUser = ARM_MMU_IDX_M,
3172     ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
3173     ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
3174     ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
3175     ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
3176     ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
3177     ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
3178     ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
3179 } ARMMMUIdx;
3180 
3181 /*
3182  * Bit macros for the core-mmu-index values for each index,
3183  * for use when calling tlb_flush_by_mmuidx() and friends.
3184  */
3185 #define TO_CORE_BIT(NAME) \
3186     ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
3187 
3188 typedef enum ARMMMUIdxBit {
3189     TO_CORE_BIT(E10_0),
3190     TO_CORE_BIT(E20_0),
3191     TO_CORE_BIT(E10_1),
3192     TO_CORE_BIT(E10_1_PAN),
3193     TO_CORE_BIT(E2),
3194     TO_CORE_BIT(E20_2),
3195     TO_CORE_BIT(E20_2_PAN),
3196     TO_CORE_BIT(SE10_0),
3197     TO_CORE_BIT(SE20_0),
3198     TO_CORE_BIT(SE10_1),
3199     TO_CORE_BIT(SE20_2),
3200     TO_CORE_BIT(SE10_1_PAN),
3201     TO_CORE_BIT(SE20_2_PAN),
3202     TO_CORE_BIT(SE2),
3203     TO_CORE_BIT(SE3),
3204 
3205     TO_CORE_BIT(MUser),
3206     TO_CORE_BIT(MPriv),
3207     TO_CORE_BIT(MUserNegPri),
3208     TO_CORE_BIT(MPrivNegPri),
3209     TO_CORE_BIT(MSUser),
3210     TO_CORE_BIT(MSPriv),
3211     TO_CORE_BIT(MSUserNegPri),
3212     TO_CORE_BIT(MSPrivNegPri),
3213 } ARMMMUIdxBit;
3214 
3215 #undef TO_CORE_BIT
3216 
3217 #define MMU_USER_IDX 0
3218 
3219 /* Indexes used when registering address spaces with cpu_address_space_init */
3220 typedef enum ARMASIdx {
3221     ARMASIdx_NS = 0,
3222     ARMASIdx_S = 1,
3223     ARMASIdx_TagNS = 2,
3224     ARMASIdx_TagS = 3,
3225 } ARMASIdx;
3226 
3227 /* Return the Exception Level targeted by debug exceptions. */
3228 static inline int arm_debug_target_el(CPUARMState *env)
3229 {
3230     bool secure = arm_is_secure(env);
3231     bool route_to_el2 = false;
3232 
3233     if (arm_is_el2_enabled(env)) {
3234         route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
3235                        env->cp15.mdcr_el2 & MDCR_TDE;
3236     }
3237 
3238     if (route_to_el2) {
3239         return 2;
3240     } else if (arm_feature(env, ARM_FEATURE_EL3) &&
3241                !arm_el_is_aa64(env, 3) && secure) {
3242         return 3;
3243     } else {
3244         return 1;
3245     }
3246 }
3247 
3248 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
3249 {
3250     /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
3251      * CSSELR is RAZ/WI.
3252      */
3253     return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
3254 }
3255 
3256 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
3257 static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
3258 {
3259     int cur_el = arm_current_el(env);
3260     int debug_el;
3261 
3262     if (cur_el == 3) {
3263         return false;
3264     }
3265 
3266     /* MDCR_EL3.SDD disables debug events from Secure state */
3267     if (arm_is_secure_below_el3(env)
3268         && extract32(env->cp15.mdcr_el3, 16, 1)) {
3269         return false;
3270     }
3271 
3272     /*
3273      * Same EL to same EL debug exceptions need MDSCR_KDE enabled
3274      * while not masking the (D)ebug bit in DAIF.
3275      */
3276     debug_el = arm_debug_target_el(env);
3277 
3278     if (cur_el == debug_el) {
3279         return extract32(env->cp15.mdscr_el1, 13, 1)
3280             && !(env->daif & PSTATE_D);
3281     }
3282 
3283     /* Otherwise the debug target needs to be a higher EL */
3284     return debug_el > cur_el;
3285 }
3286 
3287 static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
3288 {
3289     int el = arm_current_el(env);
3290 
3291     if (el == 0 && arm_el_is_aa64(env, 1)) {
3292         return aa64_generate_debug_exceptions(env);
3293     }
3294 
3295     if (arm_is_secure(env)) {
3296         int spd;
3297 
3298         if (el == 0 && (env->cp15.sder & 1)) {
3299             /* SDER.SUIDEN means debug exceptions from Secure EL0
3300              * are always enabled. Otherwise they are controlled by
3301              * SDCR.SPD like those from other Secure ELs.
3302              */
3303             return true;
3304         }
3305 
3306         spd = extract32(env->cp15.mdcr_el3, 14, 2);
3307         switch (spd) {
3308         case 1:
3309             /* SPD == 0b01 is reserved, but behaves as 0b00. */
3310         case 0:
3311             /* For 0b00 we return true if external secure invasive debug
3312              * is enabled. On real hardware this is controlled by external
3313              * signals to the core. QEMU always permits debug, and behaves
3314              * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
3315              */
3316             return true;
3317         case 2:
3318             return false;
3319         case 3:
3320             return true;
3321         }
3322     }
3323 
3324     return el != 2;
3325 }
3326 
3327 /* Return true if debugging exceptions are currently enabled.
3328  * This corresponds to what in ARM ARM pseudocode would be
3329  *    if UsingAArch32() then
3330  *        return AArch32.GenerateDebugExceptions()
3331  *    else
3332  *        return AArch64.GenerateDebugExceptions()
3333  * We choose to push the if() down into this function for clarity,
3334  * since the pseudocode has it at all callsites except for the one in
3335  * CheckSoftwareStep(), where it is elided because both branches would
3336  * always return the same value.
3337  */
3338 static inline bool arm_generate_debug_exceptions(CPUARMState *env)
3339 {
3340     if (env->aarch64) {
3341         return aa64_generate_debug_exceptions(env);
3342     } else {
3343         return aa32_generate_debug_exceptions(env);
3344     }
3345 }
3346 
3347 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
3348  * implicitly means this always returns false in pre-v8 CPUs.)
3349  */
3350 static inline bool arm_singlestep_active(CPUARMState *env)
3351 {
3352     return extract32(env->cp15.mdscr_el1, 0, 1)
3353         && arm_el_is_aa64(env, arm_debug_target_el(env))
3354         && arm_generate_debug_exceptions(env);
3355 }
3356 
3357 static inline bool arm_sctlr_b(CPUARMState *env)
3358 {
3359     return
3360         /* We need not implement SCTLR.ITD in user-mode emulation, so
3361          * let linux-user ignore the fact that it conflicts with SCTLR_B.
3362          * This lets people run BE32 binaries with "-cpu any".
3363          */
3364 #ifndef CONFIG_USER_ONLY
3365         !arm_feature(env, ARM_FEATURE_V7) &&
3366 #endif
3367         (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3368 }
3369 
3370 uint64_t arm_sctlr(CPUARMState *env, int el);
3371 
3372 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
3373                                                   bool sctlr_b)
3374 {
3375 #ifdef CONFIG_USER_ONLY
3376     /*
3377      * In system mode, BE32 is modelled in line with the
3378      * architecture (as word-invariant big-endianness), where loads
3379      * and stores are done little endian but from addresses which
3380      * are adjusted by XORing with the appropriate constant. So the
3381      * endianness to use for the raw data access is not affected by
3382      * SCTLR.B.
3383      * In user mode, however, we model BE32 as byte-invariant
3384      * big-endianness (because user-only code cannot tell the
3385      * difference), and so we need to use a data access endianness
3386      * that depends on SCTLR.B.
3387      */
3388     if (sctlr_b) {
3389         return true;
3390     }
3391 #endif
3392     /* In 32bit endianness is determined by looking at CPSR's E bit */
3393     return env->uncached_cpsr & CPSR_E;
3394 }
3395 
3396 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3397 {
3398     return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3399 }
3400 
3401 /* Return true if the processor is in big-endian mode. */
3402 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3403 {
3404     if (!is_a64(env)) {
3405         return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3406     } else {
3407         int cur_el = arm_current_el(env);
3408         uint64_t sctlr = arm_sctlr(env, cur_el);
3409         return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3410     }
3411 }
3412 
3413 typedef CPUARMState CPUArchState;
3414 typedef ARMCPU ArchCPU;
3415 
3416 #include "exec/cpu-all.h"
3417 
3418 /*
3419  * We have more than 32-bits worth of state per TB, so we split the data
3420  * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
3421  * We collect these two parts in CPUARMTBFlags where they are named
3422  * flags and flags2 respectively.
3423  *
3424  * The flags that are shared between all execution modes, TBFLAG_ANY,
3425  * are stored in flags.  The flags that are specific to a given mode
3426  * are stores in flags2.  Since cs_base is sized on the configured
3427  * address size, flags2 always has 64-bits for A64, and a minimum of
3428  * 32-bits for A32 and M32.
3429  *
3430  * The bits for 32-bit A-profile and M-profile partially overlap:
3431  *
3432  *  31         23         11 10             0
3433  * +-------------+----------+----------------+
3434  * |             |          |   TBFLAG_A32   |
3435  * | TBFLAG_AM32 |          +-----+----------+
3436  * |             |                |TBFLAG_M32|
3437  * +-------------+----------------+----------+
3438  *  31         23                6 5        0
3439  *
3440  * Unless otherwise noted, these bits are cached in env->hflags.
3441  */
3442 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
3443 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
3444 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1)      /* Not cached. */
3445 FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
3446 FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
3447 /* Target EL if we take a floating-point-disabled exception */
3448 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
3449 /* For A-profile only, target EL for debug exceptions.  */
3450 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2)
3451 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
3452 FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1)
3453 FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1)
3454 
3455 /*
3456  * Bit usage when in AArch32 state, both A- and M-profile.
3457  */
3458 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8)      /* Not cached. */
3459 FIELD(TBFLAG_AM32, THUMB, 23, 1)         /* Not cached. */
3460 
3461 /*
3462  * Bit usage when in AArch32 state, for A-profile only.
3463  */
3464 FIELD(TBFLAG_A32, VECLEN, 0, 3)         /* Not cached. */
3465 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2)     /* Not cached. */
3466 /*
3467  * We store the bottom two bits of the CPAR as TB flags and handle
3468  * checks on the other bits at runtime. This shares the same bits as
3469  * VECSTRIDE, which is OK as no XScale CPU has VFP.
3470  * Not cached, because VECLEN+VECSTRIDE are not cached.
3471  */
3472 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2)
3473 FIELD(TBFLAG_A32, VFPEN, 7, 1)         /* Partially cached, minus FPEXC. */
3474 FIELD(TBFLAG_A32, SCTLR__B, 8, 1)      /* Cannot overlap with SCTLR_B */
3475 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
3476 /*
3477  * Indicates whether cp register reads and writes by guest code should access
3478  * the secure or nonsecure bank of banked registers; note that this is not
3479  * the same thing as the current security state of the processor!
3480  */
3481 FIELD(TBFLAG_A32, NS, 10, 1)
3482 
3483 /*
3484  * Bit usage when in AArch32 state, for M-profile only.
3485  */
3486 /* Handler (ie not Thread) mode */
3487 FIELD(TBFLAG_M32, HANDLER, 0, 1)
3488 /* Whether we should generate stack-limit checks */
3489 FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
3490 /* Set if FPCCR.LSPACT is set */
3491 FIELD(TBFLAG_M32, LSPACT, 2, 1)                 /* Not cached. */
3492 /* Set if we must create a new FP context */
3493 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1)     /* Not cached. */
3494 /* Set if FPCCR.S does not match current security state */
3495 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1)          /* Not cached. */
3496 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */
3497 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1)            /* Not cached. */
3498 
3499 /*
3500  * Bit usage when in AArch64 state
3501  */
3502 FIELD(TBFLAG_A64, TBII, 0, 2)
3503 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3504 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
3505 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3506 FIELD(TBFLAG_A64, BT, 9, 1)
3507 FIELD(TBFLAG_A64, BTYPE, 10, 2)         /* Not cached. */
3508 FIELD(TBFLAG_A64, TBID, 12, 2)
3509 FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3510 FIELD(TBFLAG_A64, ATA, 15, 1)
3511 FIELD(TBFLAG_A64, TCMA, 16, 2)
3512 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3513 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3514 
3515 /*
3516  * Helpers for using the above.
3517  */
3518 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \
3519     (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
3520 #define DP_TBFLAG_A64(DST, WHICH, VAL) \
3521     (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL))
3522 #define DP_TBFLAG_A32(DST, WHICH, VAL) \
3523     (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
3524 #define DP_TBFLAG_M32(DST, WHICH, VAL) \
3525     (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
3526 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \
3527     (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
3528 
3529 #define EX_TBFLAG_ANY(IN, WHICH)   FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
3530 #define EX_TBFLAG_A64(IN, WHICH)   FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH)
3531 #define EX_TBFLAG_A32(IN, WHICH)   FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
3532 #define EX_TBFLAG_M32(IN, WHICH)   FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
3533 #define EX_TBFLAG_AM32(IN, WHICH)  FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
3534 
3535 /**
3536  * cpu_mmu_index:
3537  * @env: The cpu environment
3538  * @ifetch: True for code access, false for data access.
3539  *
3540  * Return the core mmu index for the current translation regime.
3541  * This function is used by generic TCG code paths.
3542  */
3543 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3544 {
3545     return EX_TBFLAG_ANY(env->hflags, MMUIDX);
3546 }
3547 
3548 static inline bool bswap_code(bool sctlr_b)
3549 {
3550 #ifdef CONFIG_USER_ONLY
3551     /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
3552      * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
3553      * would also end up as a mixed-endian mode with BE code, LE data.
3554      */
3555     return
3556 #ifdef TARGET_WORDS_BIGENDIAN
3557         1 ^
3558 #endif
3559         sctlr_b;
3560 #else
3561     /* All code access in ARM is little endian, and there are no loaders
3562      * doing swaps that need to be reversed
3563      */
3564     return 0;
3565 #endif
3566 }
3567 
3568 #ifdef CONFIG_USER_ONLY
3569 static inline bool arm_cpu_bswap_data(CPUARMState *env)
3570 {
3571     return
3572 #ifdef TARGET_WORDS_BIGENDIAN
3573        1 ^
3574 #endif
3575        arm_cpu_data_is_big_endian(env);
3576 }
3577 #endif
3578 
3579 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3580                           target_ulong *cs_base, uint32_t *flags);
3581 
3582 enum {
3583     QEMU_PSCI_CONDUIT_DISABLED = 0,
3584     QEMU_PSCI_CONDUIT_SMC = 1,
3585     QEMU_PSCI_CONDUIT_HVC = 2,
3586 };
3587 
3588 #ifndef CONFIG_USER_ONLY
3589 /* Return the address space index to use for a memory access */
3590 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3591 {
3592     return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3593 }
3594 
3595 /* Return the AddressSpace to use for a memory access
3596  * (which depends on whether the access is S or NS, and whether
3597  * the board gave us a separate AddressSpace for S accesses).
3598  */
3599 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3600 {
3601     return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3602 }
3603 #endif
3604 
3605 /**
3606  * arm_register_pre_el_change_hook:
3607  * Register a hook function which will be called immediately before this
3608  * CPU changes exception level or mode. The hook function will be
3609  * passed a pointer to the ARMCPU and the opaque data pointer passed
3610  * to this function when the hook was registered.
3611  *
3612  * Note that if a pre-change hook is called, any registered post-change hooks
3613  * are guaranteed to subsequently be called.
3614  */
3615 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3616                                  void *opaque);
3617 /**
3618  * arm_register_el_change_hook:
3619  * Register a hook function which will be called immediately after this
3620  * CPU changes exception level or mode. The hook function will be
3621  * passed a pointer to the ARMCPU and the opaque data pointer passed
3622  * to this function when the hook was registered.
3623  *
3624  * Note that any registered hooks registered here are guaranteed to be called
3625  * if pre-change hooks have been.
3626  */
3627 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3628         *opaque);
3629 
3630 /**
3631  * arm_rebuild_hflags:
3632  * Rebuild the cached TBFLAGS for arbitrary changed processor state.
3633  */
3634 void arm_rebuild_hflags(CPUARMState *env);
3635 
3636 /**
3637  * aa32_vfp_dreg:
3638  * Return a pointer to the Dn register within env in 32-bit mode.
3639  */
3640 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3641 {
3642     return &env->vfp.zregs[regno >> 1].d[regno & 1];
3643 }
3644 
3645 /**
3646  * aa32_vfp_qreg:
3647  * Return a pointer to the Qn register within env in 32-bit mode.
3648  */
3649 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3650 {
3651     return &env->vfp.zregs[regno].d[0];
3652 }
3653 
3654 /**
3655  * aa64_vfp_qreg:
3656  * Return a pointer to the Qn register within env in 64-bit mode.
3657  */
3658 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3659 {
3660     return &env->vfp.zregs[regno].d[0];
3661 }
3662 
3663 /* Shared between translate-sve.c and sve_helper.c.  */
3664 extern const uint64_t pred_esz_masks[4];
3665 
3666 /* Helper for the macros below, validating the argument type. */
3667 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
3668 {
3669     return x;
3670 }
3671 
3672 /*
3673  * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB.
3674  * Using these should be a bit more self-documenting than using the
3675  * generic target bits directly.
3676  */
3677 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
3678 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
3679 
3680 /*
3681  * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
3682  */
3683 #define PAGE_BTI  PAGE_TARGET_1
3684 #define PAGE_MTE  PAGE_TARGET_2
3685 
3686 #ifdef TARGET_TAGGED_ADDRESSES
3687 /**
3688  * cpu_untagged_addr:
3689  * @cs: CPU context
3690  * @x: tagged address
3691  *
3692  * Remove any address tag from @x.  This is explicitly related to the
3693  * linux syscall TIF_TAGGED_ADDR setting, not TBI in general.
3694  *
3695  * There should be a better place to put this, but we need this in
3696  * include/exec/cpu_ldst.h, and not some place linux-user specific.
3697  */
3698 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x)
3699 {
3700     ARMCPU *cpu = ARM_CPU(cs);
3701     if (cpu->env.tagged_addr_enable) {
3702         /*
3703          * TBI is enabled for userspace but not kernelspace addresses.
3704          * Only clear the tag if bit 55 is clear.
3705          */
3706         x &= sextract64(x, 0, 56);
3707     }
3708     return x;
3709 }
3710 #endif
3711 
3712 /*
3713  * Naming convention for isar_feature functions:
3714  * Functions which test 32-bit ID registers should have _aa32_ in
3715  * their name. Functions which test 64-bit ID registers should have
3716  * _aa64_ in their name. These must only be used in code where we
3717  * know for certain that the CPU has AArch32 or AArch64 respectively
3718  * or where the correct answer for a CPU which doesn't implement that
3719  * CPU state is "false" (eg when generating A32 or A64 code, if adding
3720  * system registers that are specific to that CPU state, for "should
3721  * we let this system register bit be set" tests where the 32-bit
3722  * flavour of the register doesn't have the bit, and so on).
3723  * Functions which simply ask "does this feature exist at all" have
3724  * _any_ in their name, and always return the logical OR of the _aa64_
3725  * and the _aa32_ function.
3726  */
3727 
3728 /*
3729  * 32-bit feature tests via id registers.
3730  */
3731 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
3732 {
3733     return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3734 }
3735 
3736 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
3737 {
3738     return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3739 }
3740 
3741 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
3742 {
3743     /* (M-profile) low-overhead loops and branch future */
3744     return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
3745 }
3746 
3747 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
3748 {
3749     return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3750 }
3751 
3752 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3753 {
3754     return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3755 }
3756 
3757 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3758 {
3759     return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3760 }
3761 
3762 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3763 {
3764     return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3765 }
3766 
3767 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3768 {
3769     return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3770 }
3771 
3772 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3773 {
3774     return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3775 }
3776 
3777 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3778 {
3779     return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3780 }
3781 
3782 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3783 {
3784     return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3785 }
3786 
3787 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
3788 {
3789     return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
3790 }
3791 
3792 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3793 {
3794     return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3795 }
3796 
3797 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
3798 {
3799     return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
3800 }
3801 
3802 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
3803 {
3804     return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
3805 }
3806 
3807 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
3808 {
3809     return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
3810 }
3811 
3812 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id)
3813 {
3814     return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0;
3815 }
3816 
3817 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
3818 {
3819     return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
3820 }
3821 
3822 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
3823 {
3824     return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
3825 }
3826 
3827 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
3828 {
3829     return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
3830 }
3831 
3832 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
3833 {
3834     /*
3835      * Return true if M-profile state handling insns
3836      * (VSCCLRM, CLRM, FPCTX access insns) are implemented
3837      */
3838     return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
3839 }
3840 
3841 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
3842 {
3843     /* Sadly this is encoded differently for A-profile and M-profile */
3844     if (isar_feature_aa32_mprofile(id)) {
3845         return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
3846     } else {
3847         return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
3848     }
3849 }
3850 
3851 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id)
3852 {
3853     /*
3854      * Return true if MVE is supported (either integer or floating point).
3855      * We must check for M-profile as the MVFR1 field means something
3856      * else for A-profile.
3857      */
3858     return isar_feature_aa32_mprofile(id) &&
3859         FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0;
3860 }
3861 
3862 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id)
3863 {
3864     /*
3865      * Return true if MVE is supported (either integer or floating point).
3866      * We must check for M-profile as the MVFR1 field means something
3867      * else for A-profile.
3868      */
3869     return isar_feature_aa32_mprofile(id) &&
3870         FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2;
3871 }
3872 
3873 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
3874 {
3875     /*
3876      * Return true if either VFP or SIMD is implemented.
3877      * In this case, a minimum of VFP w/ D0-D15.
3878      */
3879     return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
3880 }
3881 
3882 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
3883 {
3884     /* Return true if D16-D31 are implemented */
3885     return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
3886 }
3887 
3888 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3889 {
3890     return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
3891 }
3892 
3893 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
3894 {
3895     /* Return true if CPU supports single precision floating point, VFPv2 */
3896     return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
3897 }
3898 
3899 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
3900 {
3901     /* Return true if CPU supports single precision floating point, VFPv3 */
3902     return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
3903 }
3904 
3905 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
3906 {
3907     /* Return true if CPU supports double precision floating point, VFPv2 */
3908     return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
3909 }
3910 
3911 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
3912 {
3913     /* Return true if CPU supports double precision floating point, VFPv3 */
3914     return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
3915 }
3916 
3917 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
3918 {
3919     return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
3920 }
3921 
3922 /*
3923  * We always set the FP and SIMD FP16 fields to indicate identical
3924  * levels of support (assuming SIMD is implemented at all), so
3925  * we only need one set of accessors.
3926  */
3927 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
3928 {
3929     return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
3930 }
3931 
3932 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
3933 {
3934     return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
3935 }
3936 
3937 /*
3938  * Note that this ID register field covers both VFP and Neon FMAC,
3939  * so should usually be tested in combination with some other
3940  * check that confirms the presence of whichever of VFP or Neon is
3941  * relevant, to avoid accidentally enabling a Neon feature on
3942  * a VFP-no-Neon core or vice-versa.
3943  */
3944 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
3945 {
3946     return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
3947 }
3948 
3949 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
3950 {
3951     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
3952 }
3953 
3954 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
3955 {
3956     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
3957 }
3958 
3959 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
3960 {
3961     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
3962 }
3963 
3964 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
3965 {
3966     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
3967 }
3968 
3969 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
3970 {
3971     return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
3972 }
3973 
3974 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
3975 {
3976     return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
3977 }
3978 
3979 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
3980 {
3981     return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
3982 }
3983 
3984 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
3985 {
3986     /* 0xf means "non-standard IMPDEF PMU" */
3987     return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
3988         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3989 }
3990 
3991 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id)
3992 {
3993     /* 0xf means "non-standard IMPDEF PMU" */
3994     return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
3995         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3996 }
3997 
3998 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
3999 {
4000     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
4001 }
4002 
4003 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
4004 {
4005     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
4006 }
4007 
4008 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
4009 {
4010     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
4011 }
4012 
4013 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
4014 {
4015     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
4016 }
4017 
4018 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
4019 {
4020     return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
4021 }
4022 
4023 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
4024 {
4025     return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
4026 }
4027 
4028 /*
4029  * 64-bit feature tests via id registers.
4030  */
4031 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
4032 {
4033     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
4034 }
4035 
4036 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
4037 {
4038     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
4039 }
4040 
4041 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
4042 {
4043     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
4044 }
4045 
4046 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
4047 {
4048     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
4049 }
4050 
4051 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
4052 {
4053     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
4054 }
4055 
4056 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
4057 {
4058     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
4059 }
4060 
4061 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
4062 {
4063     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
4064 }
4065 
4066 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
4067 {
4068     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
4069 }
4070 
4071 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
4072 {
4073     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
4074 }
4075 
4076 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
4077 {
4078     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
4079 }
4080 
4081 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
4082 {
4083     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
4084 }
4085 
4086 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
4087 {
4088     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
4089 }
4090 
4091 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
4092 {
4093     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
4094 }
4095 
4096 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
4097 {
4098     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
4099 }
4100 
4101 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
4102 {
4103     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
4104 }
4105 
4106 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
4107 {
4108     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
4109 }
4110 
4111 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
4112 {
4113     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
4114 }
4115 
4116 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
4117 {
4118     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
4119 }
4120 
4121 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
4122 {
4123     /*
4124      * Return true if any form of pauth is enabled, as this
4125      * predicate controls migration of the 128-bit keys.
4126      */
4127     return (id->id_aa64isar1 &
4128             (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
4129              FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
4130              FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
4131              FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
4132 }
4133 
4134 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
4135 {
4136     /*
4137      * Return true if pauth is enabled with the architected QARMA algorithm.
4138      * QEMU will always set APA+GPA to the same value.
4139      */
4140     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
4141 }
4142 
4143 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
4144 {
4145     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
4146 }
4147 
4148 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
4149 {
4150     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
4151 }
4152 
4153 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
4154 {
4155     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
4156 }
4157 
4158 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
4159 {
4160     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
4161 }
4162 
4163 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
4164 {
4165     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
4166 }
4167 
4168 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
4169 {
4170     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
4171 }
4172 
4173 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
4174 {
4175     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
4176 }
4177 
4178 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
4179 {
4180     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
4181 }
4182 
4183 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
4184 {
4185     /* We always set the AdvSIMD and FP fields identically.  */
4186     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
4187 }
4188 
4189 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
4190 {
4191     /* We always set the AdvSIMD and FP fields identically wrt FP16.  */
4192     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
4193 }
4194 
4195 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
4196 {
4197     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
4198 }
4199 
4200 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
4201 {
4202     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
4203 }
4204 
4205 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
4206 {
4207     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
4208 }
4209 
4210 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
4211 {
4212     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
4213 }
4214 
4215 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
4216 {
4217     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
4218 }
4219 
4220 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
4221 {
4222     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
4223 }
4224 
4225 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
4226 {
4227     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
4228 }
4229 
4230 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
4231 {
4232     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
4233 }
4234 
4235 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
4236 {
4237     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
4238 }
4239 
4240 static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
4241 {
4242     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
4243 }
4244 
4245 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
4246 {
4247     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
4248 }
4249 
4250 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
4251 {
4252     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
4253 }
4254 
4255 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
4256 {
4257     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
4258 }
4259 
4260 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
4261 {
4262     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
4263         FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4264 }
4265 
4266 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
4267 {
4268     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
4269         FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4270 }
4271 
4272 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
4273 {
4274     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
4275 }
4276 
4277 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
4278 {
4279     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
4280 }
4281 
4282 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
4283 {
4284     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
4285 }
4286 
4287 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
4288 {
4289     return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
4290 }
4291 
4292 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
4293 {
4294     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
4295     return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
4296 }
4297 
4298 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
4299 {
4300     return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
4301 }
4302 
4303 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
4304 {
4305     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
4306     return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
4307 }
4308 
4309 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
4310 {
4311     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
4312 }
4313 
4314 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
4315 {
4316     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
4317 }
4318 
4319 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
4320 {
4321     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
4322 }
4323 
4324 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
4325 {
4326     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
4327 }
4328 
4329 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
4330 {
4331     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
4332 }
4333 
4334 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
4335 {
4336     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
4337 }
4338 
4339 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
4340 {
4341     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
4342 }
4343 
4344 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
4345 {
4346     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
4347 }
4348 
4349 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
4350 {
4351     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
4352 }
4353 
4354 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
4355 {
4356     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0;
4357 }
4358 
4359 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
4360 {
4361     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
4362 }
4363 
4364 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
4365 {
4366     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
4367 }
4368 
4369 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
4370 {
4371     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
4372 }
4373 
4374 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
4375 {
4376     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
4377 }
4378 
4379 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
4380 {
4381     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
4382 }
4383 
4384 /*
4385  * Feature tests for "does this exist in either 32-bit or 64-bit?"
4386  */
4387 static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
4388 {
4389     return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
4390 }
4391 
4392 static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
4393 {
4394     return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
4395 }
4396 
4397 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id)
4398 {
4399     return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id);
4400 }
4401 
4402 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id)
4403 {
4404     return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id);
4405 }
4406 
4407 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
4408 {
4409     return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
4410 }
4411 
4412 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
4413 {
4414     return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
4415 }
4416 
4417 /*
4418  * Forward to the above feature tests given an ARMCPU pointer.
4419  */
4420 #define cpu_isar_feature(name, cpu) \
4421     ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
4422 
4423 #endif
4424