1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #define EXCP_UDEF 1 /* undefined instruction */ 43 #define EXCP_SWI 2 /* software interrupt */ 44 #define EXCP_PREFETCH_ABORT 3 45 #define EXCP_DATA_ABORT 4 46 #define EXCP_IRQ 5 47 #define EXCP_FIQ 6 48 #define EXCP_BKPT 7 49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 51 #define EXCP_HVC 11 /* HyperVisor Call */ 52 #define EXCP_HYP_TRAP 12 53 #define EXCP_SMC 13 /* Secure Monitor Call */ 54 #define EXCP_VIRQ 14 55 #define EXCP_VFIQ 15 56 #define EXCP_SEMIHOST 16 /* semihosting call */ 57 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 58 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 59 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 94 /* The usual mapping for an AArch64 system register to its AArch32 95 * counterpart is for the 32 bit world to have access to the lower 96 * half only (with writes leaving the upper half untouched). It's 97 * therefore useful to be able to pass TCG the offset of the least 98 * significant half of a uint64_t struct member. 99 */ 100 #ifdef HOST_WORDS_BIGENDIAN 101 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 102 #define offsetofhigh32(S, M) offsetof(S, M) 103 #else 104 #define offsetoflow32(S, M) offsetof(S, M) 105 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 106 #endif 107 108 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 109 #define ARM_CPU_IRQ 0 110 #define ARM_CPU_FIQ 1 111 #define ARM_CPU_VIRQ 2 112 #define ARM_CPU_VFIQ 3 113 114 #define NB_MMU_MODES 8 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num_cpregs: Number of the Coprocessor registers seen by GDB. 141 * @cpregs_keys: Array that contains the corresponding Key of 142 * a given cpreg with the same order of the cpreg in the XML description. 143 */ 144 typedef struct DynamicGDBXMLInfo { 145 char *desc; 146 int num_cpregs; 147 uint32_t *cpregs_keys; 148 } DynamicGDBXMLInfo; 149 150 /* CPU state for each instance of a generic timer (in cp15 c14) */ 151 typedef struct ARMGenericTimer { 152 uint64_t cval; /* Timer CompareValue register */ 153 uint64_t ctl; /* Timer Control register */ 154 } ARMGenericTimer; 155 156 #define GTIMER_PHYS 0 157 #define GTIMER_VIRT 1 158 #define GTIMER_HYP 2 159 #define GTIMER_SEC 3 160 #define NUM_GTIMERS 4 161 162 typedef struct { 163 uint64_t raw_tcr; 164 uint32_t mask; 165 uint32_t base_mask; 166 } TCR; 167 168 /* Define a maximum sized vector register. 169 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 170 * For 64-bit, this is a 2048-bit SVE register. 171 * 172 * Note that the mapping between S, D, and Q views of the register bank 173 * differs between AArch64 and AArch32. 174 * In AArch32: 175 * Qn = regs[n].d[1]:regs[n].d[0] 176 * Dn = regs[n / 2].d[n & 1] 177 * Sn = regs[n / 4].d[n % 4 / 2], 178 * bits 31..0 for even n, and bits 63..32 for odd n 179 * (and regs[16] to regs[31] are inaccessible) 180 * In AArch64: 181 * Zn = regs[n].d[*] 182 * Qn = regs[n].d[1]:regs[n].d[0] 183 * Dn = regs[n].d[0] 184 * Sn = regs[n].d[0] bits 31..0 185 * Hn = regs[n].d[0] bits 15..0 186 * 187 * This corresponds to the architecturally defined mapping between 188 * the two execution states, and means we do not need to explicitly 189 * map these registers when changing states. 190 * 191 * Align the data for use with TCG host vector operations. 192 */ 193 194 #ifdef TARGET_AARCH64 195 # define ARM_MAX_VQ 16 196 #else 197 # define ARM_MAX_VQ 1 198 #endif 199 200 typedef struct ARMVectorReg { 201 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 202 } ARMVectorReg; 203 204 #ifdef TARGET_AARCH64 205 /* In AArch32 mode, predicate registers do not exist at all. */ 206 typedef struct ARMPredicateReg { 207 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); 208 } ARMPredicateReg; 209 210 /* In AArch32 mode, PAC keys do not exist at all. */ 211 typedef struct ARMPACKey { 212 uint64_t lo, hi; 213 } ARMPACKey; 214 #endif 215 216 217 typedef struct CPUARMState { 218 /* Regs for current mode. */ 219 uint32_t regs[16]; 220 221 /* 32/64 switch only happens when taking and returning from 222 * exceptions so the overlap semantics are taken care of then 223 * instead of having a complicated union. 224 */ 225 /* Regs for A64 mode. */ 226 uint64_t xregs[32]; 227 uint64_t pc; 228 /* PSTATE isn't an architectural register for ARMv8. However, it is 229 * convenient for us to assemble the underlying state into a 32 bit format 230 * identical to the architectural format used for the SPSR. (This is also 231 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 232 * 'pstate' register are.) Of the PSTATE bits: 233 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 234 * semantics as for AArch32, as described in the comments on each field) 235 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 236 * DAIF (exception masks) are kept in env->daif 237 * BTYPE is kept in env->btype 238 * all other bits are stored in their correct places in env->pstate 239 */ 240 uint32_t pstate; 241 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 242 243 /* Frequently accessed CPSR bits are stored separately for efficiency. 244 This contains all the other bits. Use cpsr_{read,write} to access 245 the whole CPSR. */ 246 uint32_t uncached_cpsr; 247 uint32_t spsr; 248 249 /* Banked registers. */ 250 uint64_t banked_spsr[8]; 251 uint32_t banked_r13[8]; 252 uint32_t banked_r14[8]; 253 254 /* These hold r8-r12. */ 255 uint32_t usr_regs[5]; 256 uint32_t fiq_regs[5]; 257 258 /* cpsr flag cache for faster execution */ 259 uint32_t CF; /* 0 or 1 */ 260 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 261 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 262 uint32_t ZF; /* Z set if zero. */ 263 uint32_t QF; /* 0 or 1 */ 264 uint32_t GE; /* cpsr[19:16] */ 265 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 266 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 267 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 268 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 269 270 uint64_t elr_el[4]; /* AArch64 exception link regs */ 271 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 272 273 /* System control coprocessor (cp15) */ 274 struct { 275 uint32_t c0_cpuid; 276 union { /* Cache size selection */ 277 struct { 278 uint64_t _unused_csselr0; 279 uint64_t csselr_ns; 280 uint64_t _unused_csselr1; 281 uint64_t csselr_s; 282 }; 283 uint64_t csselr_el[4]; 284 }; 285 union { /* System control register. */ 286 struct { 287 uint64_t _unused_sctlr; 288 uint64_t sctlr_ns; 289 uint64_t hsctlr; 290 uint64_t sctlr_s; 291 }; 292 uint64_t sctlr_el[4]; 293 }; 294 uint64_t cpacr_el1; /* Architectural feature access control register */ 295 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 296 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 297 uint64_t sder; /* Secure debug enable register. */ 298 uint32_t nsacr; /* Non-secure access control register. */ 299 union { /* MMU translation table base 0. */ 300 struct { 301 uint64_t _unused_ttbr0_0; 302 uint64_t ttbr0_ns; 303 uint64_t _unused_ttbr0_1; 304 uint64_t ttbr0_s; 305 }; 306 uint64_t ttbr0_el[4]; 307 }; 308 union { /* MMU translation table base 1. */ 309 struct { 310 uint64_t _unused_ttbr1_0; 311 uint64_t ttbr1_ns; 312 uint64_t _unused_ttbr1_1; 313 uint64_t ttbr1_s; 314 }; 315 uint64_t ttbr1_el[4]; 316 }; 317 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 318 /* MMU translation table base control. */ 319 TCR tcr_el[4]; 320 TCR vtcr_el2; /* Virtualization Translation Control. */ 321 uint32_t c2_data; /* MPU data cacheable bits. */ 322 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 323 union { /* MMU domain access control register 324 * MPU write buffer control. 325 */ 326 struct { 327 uint64_t dacr_ns; 328 uint64_t dacr_s; 329 }; 330 struct { 331 uint64_t dacr32_el2; 332 }; 333 }; 334 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 335 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 336 uint64_t hcr_el2; /* Hypervisor configuration register */ 337 uint64_t scr_el3; /* Secure configuration register. */ 338 union { /* Fault status registers. */ 339 struct { 340 uint64_t ifsr_ns; 341 uint64_t ifsr_s; 342 }; 343 struct { 344 uint64_t ifsr32_el2; 345 }; 346 }; 347 union { 348 struct { 349 uint64_t _unused_dfsr; 350 uint64_t dfsr_ns; 351 uint64_t hsr; 352 uint64_t dfsr_s; 353 }; 354 uint64_t esr_el[4]; 355 }; 356 uint32_t c6_region[8]; /* MPU base/size registers. */ 357 union { /* Fault address registers. */ 358 struct { 359 uint64_t _unused_far0; 360 #ifdef HOST_WORDS_BIGENDIAN 361 uint32_t ifar_ns; 362 uint32_t dfar_ns; 363 uint32_t ifar_s; 364 uint32_t dfar_s; 365 #else 366 uint32_t dfar_ns; 367 uint32_t ifar_ns; 368 uint32_t dfar_s; 369 uint32_t ifar_s; 370 #endif 371 uint64_t _unused_far3; 372 }; 373 uint64_t far_el[4]; 374 }; 375 uint64_t hpfar_el2; 376 uint64_t hstr_el2; 377 union { /* Translation result. */ 378 struct { 379 uint64_t _unused_par_0; 380 uint64_t par_ns; 381 uint64_t _unused_par_1; 382 uint64_t par_s; 383 }; 384 uint64_t par_el[4]; 385 }; 386 387 uint32_t c9_insn; /* Cache lockdown registers. */ 388 uint32_t c9_data; 389 uint64_t c9_pmcr; /* performance monitor control register */ 390 uint64_t c9_pmcnten; /* perf monitor counter enables */ 391 uint64_t c9_pmovsr; /* perf monitor overflow status */ 392 uint64_t c9_pmuserenr; /* perf monitor user enable */ 393 uint64_t c9_pmselr; /* perf monitor counter selection register */ 394 uint64_t c9_pminten; /* perf monitor interrupt enables */ 395 union { /* Memory attribute redirection */ 396 struct { 397 #ifdef HOST_WORDS_BIGENDIAN 398 uint64_t _unused_mair_0; 399 uint32_t mair1_ns; 400 uint32_t mair0_ns; 401 uint64_t _unused_mair_1; 402 uint32_t mair1_s; 403 uint32_t mair0_s; 404 #else 405 uint64_t _unused_mair_0; 406 uint32_t mair0_ns; 407 uint32_t mair1_ns; 408 uint64_t _unused_mair_1; 409 uint32_t mair0_s; 410 uint32_t mair1_s; 411 #endif 412 }; 413 uint64_t mair_el[4]; 414 }; 415 union { /* vector base address register */ 416 struct { 417 uint64_t _unused_vbar; 418 uint64_t vbar_ns; 419 uint64_t hvbar; 420 uint64_t vbar_s; 421 }; 422 uint64_t vbar_el[4]; 423 }; 424 uint32_t mvbar; /* (monitor) vector base address register */ 425 struct { /* FCSE PID. */ 426 uint32_t fcseidr_ns; 427 uint32_t fcseidr_s; 428 }; 429 union { /* Context ID. */ 430 struct { 431 uint64_t _unused_contextidr_0; 432 uint64_t contextidr_ns; 433 uint64_t _unused_contextidr_1; 434 uint64_t contextidr_s; 435 }; 436 uint64_t contextidr_el[4]; 437 }; 438 union { /* User RW Thread register. */ 439 struct { 440 uint64_t tpidrurw_ns; 441 uint64_t tpidrprw_ns; 442 uint64_t htpidr; 443 uint64_t _tpidr_el3; 444 }; 445 uint64_t tpidr_el[4]; 446 }; 447 /* The secure banks of these registers don't map anywhere */ 448 uint64_t tpidrurw_s; 449 uint64_t tpidrprw_s; 450 uint64_t tpidruro_s; 451 452 union { /* User RO Thread register. */ 453 uint64_t tpidruro_ns; 454 uint64_t tpidrro_el[1]; 455 }; 456 uint64_t c14_cntfrq; /* Counter Frequency register */ 457 uint64_t c14_cntkctl; /* Timer Control register */ 458 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 459 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 460 ARMGenericTimer c14_timer[NUM_GTIMERS]; 461 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 462 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 463 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 464 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 465 uint32_t c15_threadid; /* TI debugger thread-ID. */ 466 uint32_t c15_config_base_address; /* SCU base address. */ 467 uint32_t c15_diagnostic; /* diagnostic register */ 468 uint32_t c15_power_diagnostic; 469 uint32_t c15_power_control; /* power control */ 470 uint64_t dbgbvr[16]; /* breakpoint value registers */ 471 uint64_t dbgbcr[16]; /* breakpoint control registers */ 472 uint64_t dbgwvr[16]; /* watchpoint value registers */ 473 uint64_t dbgwcr[16]; /* watchpoint control registers */ 474 uint64_t mdscr_el1; 475 uint64_t oslsr_el1; /* OS Lock Status */ 476 uint64_t mdcr_el2; 477 uint64_t mdcr_el3; 478 /* Stores the architectural value of the counter *the last time it was 479 * updated* by pmccntr_op_start. Accesses should always be surrounded 480 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 481 * architecturally-correct value is being read/set. 482 */ 483 uint64_t c15_ccnt; 484 /* Stores the delta between the architectural value and the underlying 485 * cycle count during normal operation. It is used to update c15_ccnt 486 * to be the correct architectural value before accesses. During 487 * accesses, c15_ccnt_delta contains the underlying count being used 488 * for the access, after which it reverts to the delta value in 489 * pmccntr_op_finish. 490 */ 491 uint64_t c15_ccnt_delta; 492 uint64_t c14_pmevcntr[31]; 493 uint64_t c14_pmevcntr_delta[31]; 494 uint64_t c14_pmevtyper[31]; 495 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 496 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 497 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 498 } cp15; 499 500 struct { 501 /* M profile has up to 4 stack pointers: 502 * a Main Stack Pointer and a Process Stack Pointer for each 503 * of the Secure and Non-Secure states. (If the CPU doesn't support 504 * the security extension then it has only two SPs.) 505 * In QEMU we always store the currently active SP in regs[13], 506 * and the non-active SP for the current security state in 507 * v7m.other_sp. The stack pointers for the inactive security state 508 * are stored in other_ss_msp and other_ss_psp. 509 * switch_v7m_security_state() is responsible for rearranging them 510 * when we change security state. 511 */ 512 uint32_t other_sp; 513 uint32_t other_ss_msp; 514 uint32_t other_ss_psp; 515 uint32_t vecbase[M_REG_NUM_BANKS]; 516 uint32_t basepri[M_REG_NUM_BANKS]; 517 uint32_t control[M_REG_NUM_BANKS]; 518 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 519 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 520 uint32_t hfsr; /* HardFault Status */ 521 uint32_t dfsr; /* Debug Fault Status Register */ 522 uint32_t sfsr; /* Secure Fault Status Register */ 523 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 524 uint32_t bfar; /* BusFault Address */ 525 uint32_t sfar; /* Secure Fault Address Register */ 526 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 527 int exception; 528 uint32_t primask[M_REG_NUM_BANKS]; 529 uint32_t faultmask[M_REG_NUM_BANKS]; 530 uint32_t aircr; /* only holds r/w state if security extn implemented */ 531 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 532 uint32_t csselr[M_REG_NUM_BANKS]; 533 uint32_t scr[M_REG_NUM_BANKS]; 534 uint32_t msplim[M_REG_NUM_BANKS]; 535 uint32_t psplim[M_REG_NUM_BANKS]; 536 } v7m; 537 538 /* Information associated with an exception about to be taken: 539 * code which raises an exception must set cs->exception_index and 540 * the relevant parts of this structure; the cpu_do_interrupt function 541 * will then set the guest-visible registers as part of the exception 542 * entry process. 543 */ 544 struct { 545 uint32_t syndrome; /* AArch64 format syndrome register */ 546 uint32_t fsr; /* AArch32 format fault status register info */ 547 uint64_t vaddress; /* virtual addr associated with exception, if any */ 548 uint32_t target_el; /* EL the exception should be targeted for */ 549 /* If we implement EL2 we will also need to store information 550 * about the intermediate physical address for stage 2 faults. 551 */ 552 } exception; 553 554 /* Information associated with an SError */ 555 struct { 556 uint8_t pending; 557 uint8_t has_esr; 558 uint64_t esr; 559 } serror; 560 561 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 562 uint32_t irq_line_state; 563 564 /* Thumb-2 EE state. */ 565 uint32_t teecr; 566 uint32_t teehbr; 567 568 /* VFP coprocessor state. */ 569 struct { 570 ARMVectorReg zregs[32]; 571 572 #ifdef TARGET_AARCH64 573 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 574 #define FFR_PRED_NUM 16 575 ARMPredicateReg pregs[17]; 576 /* Scratch space for aa64 sve predicate temporary. */ 577 ARMPredicateReg preg_tmp; 578 #endif 579 580 uint32_t xregs[16]; 581 /* We store these fpcsr fields separately for convenience. */ 582 int vec_len; 583 int vec_stride; 584 585 /* Scratch space for aa32 neon expansion. */ 586 uint32_t scratch[8]; 587 588 /* There are a number of distinct float control structures: 589 * 590 * fp_status: is the "normal" fp status. 591 * fp_status_fp16: used for half-precision calculations 592 * standard_fp_status : the ARM "Standard FPSCR Value" 593 * 594 * Half-precision operations are governed by a separate 595 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 596 * status structure to control this. 597 * 598 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 599 * round-to-nearest and is used by any operations (generally 600 * Neon) which the architecture defines as controlled by the 601 * standard FPSCR value rather than the FPSCR. 602 * 603 * To avoid having to transfer exception bits around, we simply 604 * say that the FPSCR cumulative exception flags are the logical 605 * OR of the flags in the three fp statuses. This relies on the 606 * only thing which needs to read the exception flags being 607 * an explicit FPSCR read. 608 */ 609 float_status fp_status; 610 float_status fp_status_f16; 611 float_status standard_fp_status; 612 613 /* ZCR_EL[1-3] */ 614 uint64_t zcr_el[4]; 615 } vfp; 616 uint64_t exclusive_addr; 617 uint64_t exclusive_val; 618 uint64_t exclusive_high; 619 620 /* iwMMXt coprocessor state. */ 621 struct { 622 uint64_t regs[16]; 623 uint64_t val; 624 625 uint32_t cregs[16]; 626 } iwmmxt; 627 628 #ifdef TARGET_AARCH64 629 ARMPACKey apia_key; 630 ARMPACKey apib_key; 631 ARMPACKey apda_key; 632 ARMPACKey apdb_key; 633 ARMPACKey apga_key; 634 #endif 635 636 #if defined(CONFIG_USER_ONLY) 637 /* For usermode syscall translation. */ 638 int eabi; 639 #endif 640 641 struct CPUBreakpoint *cpu_breakpoint[16]; 642 struct CPUWatchpoint *cpu_watchpoint[16]; 643 644 /* Fields up to this point are cleared by a CPU reset */ 645 struct {} end_reset_fields; 646 647 CPU_COMMON 648 649 /* Fields after CPU_COMMON are preserved across CPU reset. */ 650 651 /* Internal CPU feature flags. */ 652 uint64_t features; 653 654 /* PMSAv7 MPU */ 655 struct { 656 uint32_t *drbar; 657 uint32_t *drsr; 658 uint32_t *dracr; 659 uint32_t rnr[M_REG_NUM_BANKS]; 660 } pmsav7; 661 662 /* PMSAv8 MPU */ 663 struct { 664 /* The PMSAv8 implementation also shares some PMSAv7 config 665 * and state: 666 * pmsav7.rnr (region number register) 667 * pmsav7_dregion (number of configured regions) 668 */ 669 uint32_t *rbar[M_REG_NUM_BANKS]; 670 uint32_t *rlar[M_REG_NUM_BANKS]; 671 uint32_t mair0[M_REG_NUM_BANKS]; 672 uint32_t mair1[M_REG_NUM_BANKS]; 673 } pmsav8; 674 675 /* v8M SAU */ 676 struct { 677 uint32_t *rbar; 678 uint32_t *rlar; 679 uint32_t rnr; 680 uint32_t ctrl; 681 } sau; 682 683 void *nvic; 684 const struct arm_boot_info *boot_info; 685 /* Store GICv3CPUState to access from this struct */ 686 void *gicv3state; 687 } CPUARMState; 688 689 /** 690 * ARMELChangeHookFn: 691 * type of a function which can be registered via arm_register_el_change_hook() 692 * to get callbacks when the CPU changes its exception level or mode. 693 */ 694 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 695 typedef struct ARMELChangeHook ARMELChangeHook; 696 struct ARMELChangeHook { 697 ARMELChangeHookFn *hook; 698 void *opaque; 699 QLIST_ENTRY(ARMELChangeHook) node; 700 }; 701 702 /* These values map onto the return values for 703 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 704 typedef enum ARMPSCIState { 705 PSCI_ON = 0, 706 PSCI_OFF = 1, 707 PSCI_ON_PENDING = 2 708 } ARMPSCIState; 709 710 typedef struct ARMISARegisters ARMISARegisters; 711 712 /** 713 * ARMCPU: 714 * @env: #CPUARMState 715 * 716 * An ARM CPU core. 717 */ 718 struct ARMCPU { 719 /*< private >*/ 720 CPUState parent_obj; 721 /*< public >*/ 722 723 CPUARMState env; 724 725 /* Coprocessor information */ 726 GHashTable *cp_regs; 727 /* For marshalling (mostly coprocessor) register state between the 728 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 729 * we use these arrays. 730 */ 731 /* List of register indexes managed via these arrays; (full KVM style 732 * 64 bit indexes, not CPRegInfo 32 bit indexes) 733 */ 734 uint64_t *cpreg_indexes; 735 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 736 uint64_t *cpreg_values; 737 /* Length of the indexes, values, reset_values arrays */ 738 int32_t cpreg_array_len; 739 /* These are used only for migration: incoming data arrives in 740 * these fields and is sanity checked in post_load before copying 741 * to the working data structures above. 742 */ 743 uint64_t *cpreg_vmstate_indexes; 744 uint64_t *cpreg_vmstate_values; 745 int32_t cpreg_vmstate_array_len; 746 747 DynamicGDBXMLInfo dyn_xml; 748 749 /* Timers used by the generic (architected) timer */ 750 QEMUTimer *gt_timer[NUM_GTIMERS]; 751 /* 752 * Timer used by the PMU. Its state is restored after migration by 753 * pmu_op_finish() - it does not need other handling during migration 754 */ 755 QEMUTimer *pmu_timer; 756 /* GPIO outputs for generic timer */ 757 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 758 /* GPIO output for GICv3 maintenance interrupt signal */ 759 qemu_irq gicv3_maintenance_interrupt; 760 /* GPIO output for the PMU interrupt */ 761 qemu_irq pmu_interrupt; 762 763 /* MemoryRegion to use for secure physical accesses */ 764 MemoryRegion *secure_memory; 765 766 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 767 Object *idau; 768 769 /* 'compatible' string for this CPU for Linux device trees */ 770 const char *dtb_compatible; 771 772 /* PSCI version for this CPU 773 * Bits[31:16] = Major Version 774 * Bits[15:0] = Minor Version 775 */ 776 uint32_t psci_version; 777 778 /* Should CPU start in PSCI powered-off state? */ 779 bool start_powered_off; 780 781 /* Current power state, access guarded by BQL */ 782 ARMPSCIState power_state; 783 784 /* CPU has virtualization extension */ 785 bool has_el2; 786 /* CPU has security extension */ 787 bool has_el3; 788 /* CPU has PMU (Performance Monitor Unit) */ 789 bool has_pmu; 790 791 /* CPU has memory protection unit */ 792 bool has_mpu; 793 /* PMSAv7 MPU number of supported regions */ 794 uint32_t pmsav7_dregion; 795 /* v8M SAU number of supported regions */ 796 uint32_t sau_sregion; 797 798 /* PSCI conduit used to invoke PSCI methods 799 * 0 - disabled, 1 - smc, 2 - hvc 800 */ 801 uint32_t psci_conduit; 802 803 /* For v8M, initial value of the Secure VTOR */ 804 uint32_t init_svtor; 805 806 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 807 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 808 */ 809 uint32_t kvm_target; 810 811 /* KVM init features for this CPU */ 812 uint32_t kvm_init_features[7]; 813 814 /* Uniprocessor system with MP extensions */ 815 bool mp_is_up; 816 817 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 818 * and the probe failed (so we need to report the error in realize) 819 */ 820 bool host_cpu_probe_failed; 821 822 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 823 * register. 824 */ 825 int32_t core_count; 826 827 /* The instance init functions for implementation-specific subclasses 828 * set these fields to specify the implementation-dependent values of 829 * various constant registers and reset values of non-constant 830 * registers. 831 * Some of these might become QOM properties eventually. 832 * Field names match the official register names as defined in the 833 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 834 * is used for reset values of non-constant registers; no reset_ 835 * prefix means a constant register. 836 * Some of these registers are split out into a substructure that 837 * is shared with the translators to control the ISA. 838 */ 839 struct ARMISARegisters { 840 uint32_t id_isar0; 841 uint32_t id_isar1; 842 uint32_t id_isar2; 843 uint32_t id_isar3; 844 uint32_t id_isar4; 845 uint32_t id_isar5; 846 uint32_t id_isar6; 847 uint32_t mvfr0; 848 uint32_t mvfr1; 849 uint32_t mvfr2; 850 uint64_t id_aa64isar0; 851 uint64_t id_aa64isar1; 852 uint64_t id_aa64pfr0; 853 uint64_t id_aa64pfr1; 854 uint64_t id_aa64mmfr0; 855 uint64_t id_aa64mmfr1; 856 } isar; 857 uint32_t midr; 858 uint32_t revidr; 859 uint32_t reset_fpsid; 860 uint32_t ctr; 861 uint32_t reset_sctlr; 862 uint32_t id_pfr0; 863 uint32_t id_pfr1; 864 uint32_t id_dfr0; 865 uint64_t pmceid0; 866 uint64_t pmceid1; 867 uint32_t id_afr0; 868 uint32_t id_mmfr0; 869 uint32_t id_mmfr1; 870 uint32_t id_mmfr2; 871 uint32_t id_mmfr3; 872 uint32_t id_mmfr4; 873 uint64_t id_aa64dfr0; 874 uint64_t id_aa64dfr1; 875 uint64_t id_aa64afr0; 876 uint64_t id_aa64afr1; 877 uint32_t dbgdidr; 878 uint32_t clidr; 879 uint64_t mp_affinity; /* MP ID without feature bits */ 880 /* The elements of this array are the CCSIDR values for each cache, 881 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 882 */ 883 uint32_t ccsidr[16]; 884 uint64_t reset_cbar; 885 uint32_t reset_auxcr; 886 bool reset_hivecs; 887 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 888 uint32_t dcz_blocksize; 889 uint64_t rvbar; 890 891 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 892 int gic_num_lrs; /* number of list registers */ 893 int gic_vpribits; /* number of virtual priority bits */ 894 int gic_vprebits; /* number of virtual preemption bits */ 895 896 /* Whether the cfgend input is high (i.e. this CPU should reset into 897 * big-endian mode). This setting isn't used directly: instead it modifies 898 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 899 * architecture version. 900 */ 901 bool cfgend; 902 903 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 904 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 905 906 int32_t node_id; /* NUMA node this CPU belongs to */ 907 908 /* Used to synchronize KVM and QEMU in-kernel device levels */ 909 uint8_t device_irq_level; 910 911 /* Used to set the maximum vector length the cpu will support. */ 912 uint32_t sve_max_vq; 913 }; 914 915 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 916 { 917 return container_of(env, ARMCPU, env); 918 } 919 920 void arm_cpu_post_init(Object *obj); 921 922 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 923 924 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 925 926 #define ENV_OFFSET offsetof(ARMCPU, env) 927 928 #ifndef CONFIG_USER_ONLY 929 extern const struct VMStateDescription vmstate_arm_cpu; 930 #endif 931 932 void arm_cpu_do_interrupt(CPUState *cpu); 933 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 934 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 935 936 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 937 int flags); 938 939 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 940 MemTxAttrs *attrs); 941 942 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 943 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 944 945 /* Dynamically generates for gdb stub an XML description of the sysregs from 946 * the cp_regs hashtable. Returns the registered sysregs number. 947 */ 948 int arm_gen_dynamic_xml(CPUState *cpu); 949 950 /* Returns the dynamically generated XML for the gdb stub. 951 * Returns a pointer to the XML contents for the specified XML file or NULL 952 * if the XML name doesn't match the predefined one. 953 */ 954 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 955 956 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 957 int cpuid, void *opaque); 958 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 959 int cpuid, void *opaque); 960 961 #ifdef TARGET_AARCH64 962 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 963 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 964 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 965 void aarch64_sve_change_el(CPUARMState *env, int old_el, 966 int new_el, bool el0_a64); 967 #else 968 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 969 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 970 int n, bool a) 971 { } 972 #endif 973 974 target_ulong do_arm_semihosting(CPUARMState *env); 975 void aarch64_sync_32_to_64(CPUARMState *env); 976 void aarch64_sync_64_to_32(CPUARMState *env); 977 978 int fp_exception_el(CPUARMState *env, int cur_el); 979 int sve_exception_el(CPUARMState *env, int cur_el); 980 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 981 982 static inline bool is_a64(CPUARMState *env) 983 { 984 return env->aarch64; 985 } 986 987 /* you can call this signal handler from your SIGBUS and SIGSEGV 988 signal handlers to inform the virtual CPU of exceptions. non zero 989 is returned if the signal was handled by the virtual CPU. */ 990 int cpu_arm_signal_handler(int host_signum, void *pinfo, 991 void *puc); 992 993 /** 994 * pmccntr_op_start/finish 995 * @env: CPUARMState 996 * 997 * Convert the counter in the PMCCNTR between its delta form (the typical mode 998 * when it's enabled) and the guest-visible value. These two calls must always 999 * surround any action which might affect the counter. 1000 */ 1001 void pmccntr_op_start(CPUARMState *env); 1002 void pmccntr_op_finish(CPUARMState *env); 1003 1004 /** 1005 * pmu_op_start/finish 1006 * @env: CPUARMState 1007 * 1008 * Convert all PMU counters between their delta form (the typical mode when 1009 * they are enabled) and the guest-visible values. These two calls must 1010 * surround any action which might affect the counters. 1011 */ 1012 void pmu_op_start(CPUARMState *env); 1013 void pmu_op_finish(CPUARMState *env); 1014 1015 /* 1016 * Called when a PMU counter is due to overflow 1017 */ 1018 void arm_pmu_timer_cb(void *opaque); 1019 1020 /** 1021 * Functions to register as EL change hooks for PMU mode filtering 1022 */ 1023 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1024 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1025 1026 /* 1027 * pmu_init 1028 * @cpu: ARMCPU 1029 * 1030 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1031 * for the current configuration 1032 */ 1033 void pmu_init(ARMCPU *cpu); 1034 1035 /* SCTLR bit meanings. Several bits have been reused in newer 1036 * versions of the architecture; in that case we define constants 1037 * for both old and new bit meanings. Code which tests against those 1038 * bits should probably check or otherwise arrange that the CPU 1039 * is the architectural version it expects. 1040 */ 1041 #define SCTLR_M (1U << 0) 1042 #define SCTLR_A (1U << 1) 1043 #define SCTLR_C (1U << 2) 1044 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1045 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1046 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1047 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1048 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1049 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1050 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1051 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1052 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1053 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1054 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1055 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1056 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1057 #define SCTLR_SED (1U << 8) /* v8 onward */ 1058 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1059 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1060 #define SCTLR_F (1U << 10) /* up to v6 */ 1061 #define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ 1062 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1063 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1064 #define SCTLR_I (1U << 12) 1065 #define SCTLR_V (1U << 13) /* AArch32 only */ 1066 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1067 #define SCTLR_RR (1U << 14) /* up to v7 */ 1068 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1069 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1070 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1071 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1072 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1073 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1074 #define SCTLR_BR (1U << 17) /* PMSA only */ 1075 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1076 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1077 #define SCTLR_WXN (1U << 19) 1078 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1079 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1080 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1081 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1082 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1083 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1084 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1085 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1086 #define SCTLR_VE (1U << 24) /* up to v7 */ 1087 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1088 #define SCTLR_EE (1U << 25) 1089 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1090 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1091 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1092 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1093 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1094 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1095 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1096 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1097 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1098 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1099 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1100 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1101 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1102 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1103 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1104 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1105 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1106 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1107 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1108 1109 #define CPTR_TCPAC (1U << 31) 1110 #define CPTR_TTA (1U << 20) 1111 #define CPTR_TFP (1U << 10) 1112 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1113 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1114 1115 #define MDCR_EPMAD (1U << 21) 1116 #define MDCR_EDAD (1U << 20) 1117 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1118 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1119 #define MDCR_SDD (1U << 16) 1120 #define MDCR_SPD (3U << 14) 1121 #define MDCR_TDRA (1U << 11) 1122 #define MDCR_TDOSA (1U << 10) 1123 #define MDCR_TDA (1U << 9) 1124 #define MDCR_TDE (1U << 8) 1125 #define MDCR_HPME (1U << 7) 1126 #define MDCR_TPM (1U << 6) 1127 #define MDCR_TPMCR (1U << 5) 1128 #define MDCR_HPMN (0x1fU) 1129 1130 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1131 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1132 1133 #define CPSR_M (0x1fU) 1134 #define CPSR_T (1U << 5) 1135 #define CPSR_F (1U << 6) 1136 #define CPSR_I (1U << 7) 1137 #define CPSR_A (1U << 8) 1138 #define CPSR_E (1U << 9) 1139 #define CPSR_IT_2_7 (0xfc00U) 1140 #define CPSR_GE (0xfU << 16) 1141 #define CPSR_IL (1U << 20) 1142 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 1143 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 1144 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 1145 * where it is live state but not accessible to the AArch32 code. 1146 */ 1147 #define CPSR_RESERVED (0x7U << 21) 1148 #define CPSR_J (1U << 24) 1149 #define CPSR_IT_0_1 (3U << 25) 1150 #define CPSR_Q (1U << 27) 1151 #define CPSR_V (1U << 28) 1152 #define CPSR_C (1U << 29) 1153 #define CPSR_Z (1U << 30) 1154 #define CPSR_N (1U << 31) 1155 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1156 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1157 1158 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1159 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1160 | CPSR_NZCV) 1161 /* Bits writable in user mode. */ 1162 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1163 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1164 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1165 /* Mask of bits which may be set by exception return copying them from SPSR */ 1166 #define CPSR_ERET_MASK (~CPSR_RESERVED) 1167 1168 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1169 #define XPSR_EXCP 0x1ffU 1170 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1171 #define XPSR_IT_2_7 CPSR_IT_2_7 1172 #define XPSR_GE CPSR_GE 1173 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1174 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1175 #define XPSR_IT_0_1 CPSR_IT_0_1 1176 #define XPSR_Q CPSR_Q 1177 #define XPSR_V CPSR_V 1178 #define XPSR_C CPSR_C 1179 #define XPSR_Z CPSR_Z 1180 #define XPSR_N CPSR_N 1181 #define XPSR_NZCV CPSR_NZCV 1182 #define XPSR_IT CPSR_IT 1183 1184 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1185 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1186 #define TTBCR_PD0 (1U << 4) 1187 #define TTBCR_PD1 (1U << 5) 1188 #define TTBCR_EPD0 (1U << 7) 1189 #define TTBCR_IRGN0 (3U << 8) 1190 #define TTBCR_ORGN0 (3U << 10) 1191 #define TTBCR_SH0 (3U << 12) 1192 #define TTBCR_T1SZ (3U << 16) 1193 #define TTBCR_A1 (1U << 22) 1194 #define TTBCR_EPD1 (1U << 23) 1195 #define TTBCR_IRGN1 (3U << 24) 1196 #define TTBCR_ORGN1 (3U << 26) 1197 #define TTBCR_SH1 (1U << 28) 1198 #define TTBCR_EAE (1U << 31) 1199 1200 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1201 * Only these are valid when in AArch64 mode; in 1202 * AArch32 mode SPSRs are basically CPSR-format. 1203 */ 1204 #define PSTATE_SP (1U) 1205 #define PSTATE_M (0xFU) 1206 #define PSTATE_nRW (1U << 4) 1207 #define PSTATE_F (1U << 6) 1208 #define PSTATE_I (1U << 7) 1209 #define PSTATE_A (1U << 8) 1210 #define PSTATE_D (1U << 9) 1211 #define PSTATE_BTYPE (3U << 10) 1212 #define PSTATE_IL (1U << 20) 1213 #define PSTATE_SS (1U << 21) 1214 #define PSTATE_V (1U << 28) 1215 #define PSTATE_C (1U << 29) 1216 #define PSTATE_Z (1U << 30) 1217 #define PSTATE_N (1U << 31) 1218 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1219 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1220 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1221 /* Mode values for AArch64 */ 1222 #define PSTATE_MODE_EL3h 13 1223 #define PSTATE_MODE_EL3t 12 1224 #define PSTATE_MODE_EL2h 9 1225 #define PSTATE_MODE_EL2t 8 1226 #define PSTATE_MODE_EL1h 5 1227 #define PSTATE_MODE_EL1t 4 1228 #define PSTATE_MODE_EL0t 0 1229 1230 /* Write a new value to v7m.exception, thus transitioning into or out 1231 * of Handler mode; this may result in a change of active stack pointer. 1232 */ 1233 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1234 1235 /* Map EL and handler into a PSTATE_MODE. */ 1236 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1237 { 1238 return (el << 2) | handler; 1239 } 1240 1241 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1242 * interprocessing, so we don't attempt to sync with the cpsr state used by 1243 * the 32 bit decoder. 1244 */ 1245 static inline uint32_t pstate_read(CPUARMState *env) 1246 { 1247 int ZF; 1248 1249 ZF = (env->ZF == 0); 1250 return (env->NF & 0x80000000) | (ZF << 30) 1251 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1252 | env->pstate | env->daif | (env->btype << 10); 1253 } 1254 1255 static inline void pstate_write(CPUARMState *env, uint32_t val) 1256 { 1257 env->ZF = (~val) & PSTATE_Z; 1258 env->NF = val; 1259 env->CF = (val >> 29) & 1; 1260 env->VF = (val << 3) & 0x80000000; 1261 env->daif = val & PSTATE_DAIF; 1262 env->btype = (val >> 10) & 3; 1263 env->pstate = val & ~CACHED_PSTATE_BITS; 1264 } 1265 1266 /* Return the current CPSR value. */ 1267 uint32_t cpsr_read(CPUARMState *env); 1268 1269 typedef enum CPSRWriteType { 1270 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1271 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1272 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1273 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1274 } CPSRWriteType; 1275 1276 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1277 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1278 CPSRWriteType write_type); 1279 1280 /* Return the current xPSR value. */ 1281 static inline uint32_t xpsr_read(CPUARMState *env) 1282 { 1283 int ZF; 1284 ZF = (env->ZF == 0); 1285 return (env->NF & 0x80000000) | (ZF << 30) 1286 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1287 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1288 | ((env->condexec_bits & 0xfc) << 8) 1289 | env->v7m.exception; 1290 } 1291 1292 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1293 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1294 { 1295 if (mask & XPSR_NZCV) { 1296 env->ZF = (~val) & XPSR_Z; 1297 env->NF = val; 1298 env->CF = (val >> 29) & 1; 1299 env->VF = (val << 3) & 0x80000000; 1300 } 1301 if (mask & XPSR_Q) { 1302 env->QF = ((val & XPSR_Q) != 0); 1303 } 1304 if (mask & XPSR_T) { 1305 env->thumb = ((val & XPSR_T) != 0); 1306 } 1307 if (mask & XPSR_IT_0_1) { 1308 env->condexec_bits &= ~3; 1309 env->condexec_bits |= (val >> 25) & 3; 1310 } 1311 if (mask & XPSR_IT_2_7) { 1312 env->condexec_bits &= 3; 1313 env->condexec_bits |= (val >> 8) & 0xfc; 1314 } 1315 if (mask & XPSR_EXCP) { 1316 /* Note that this only happens on exception exit */ 1317 write_v7m_exception(env, val & XPSR_EXCP); 1318 } 1319 } 1320 1321 #define HCR_VM (1ULL << 0) 1322 #define HCR_SWIO (1ULL << 1) 1323 #define HCR_PTW (1ULL << 2) 1324 #define HCR_FMO (1ULL << 3) 1325 #define HCR_IMO (1ULL << 4) 1326 #define HCR_AMO (1ULL << 5) 1327 #define HCR_VF (1ULL << 6) 1328 #define HCR_VI (1ULL << 7) 1329 #define HCR_VSE (1ULL << 8) 1330 #define HCR_FB (1ULL << 9) 1331 #define HCR_BSU_MASK (3ULL << 10) 1332 #define HCR_DC (1ULL << 12) 1333 #define HCR_TWI (1ULL << 13) 1334 #define HCR_TWE (1ULL << 14) 1335 #define HCR_TID0 (1ULL << 15) 1336 #define HCR_TID1 (1ULL << 16) 1337 #define HCR_TID2 (1ULL << 17) 1338 #define HCR_TID3 (1ULL << 18) 1339 #define HCR_TSC (1ULL << 19) 1340 #define HCR_TIDCP (1ULL << 20) 1341 #define HCR_TACR (1ULL << 21) 1342 #define HCR_TSW (1ULL << 22) 1343 #define HCR_TPCP (1ULL << 23) 1344 #define HCR_TPU (1ULL << 24) 1345 #define HCR_TTLB (1ULL << 25) 1346 #define HCR_TVM (1ULL << 26) 1347 #define HCR_TGE (1ULL << 27) 1348 #define HCR_TDZ (1ULL << 28) 1349 #define HCR_HCD (1ULL << 29) 1350 #define HCR_TRVM (1ULL << 30) 1351 #define HCR_RW (1ULL << 31) 1352 #define HCR_CD (1ULL << 32) 1353 #define HCR_ID (1ULL << 33) 1354 #define HCR_E2H (1ULL << 34) 1355 #define HCR_TLOR (1ULL << 35) 1356 #define HCR_TERR (1ULL << 36) 1357 #define HCR_TEA (1ULL << 37) 1358 #define HCR_MIOCNCE (1ULL << 38) 1359 #define HCR_APK (1ULL << 40) 1360 #define HCR_API (1ULL << 41) 1361 #define HCR_NV (1ULL << 42) 1362 #define HCR_NV1 (1ULL << 43) 1363 #define HCR_AT (1ULL << 44) 1364 #define HCR_NV2 (1ULL << 45) 1365 #define HCR_FWB (1ULL << 46) 1366 #define HCR_FIEN (1ULL << 47) 1367 #define HCR_TID4 (1ULL << 49) 1368 #define HCR_TICAB (1ULL << 50) 1369 #define HCR_TOCU (1ULL << 52) 1370 #define HCR_TTLBIS (1ULL << 54) 1371 #define HCR_TTLBOS (1ULL << 55) 1372 #define HCR_ATA (1ULL << 56) 1373 #define HCR_DCT (1ULL << 57) 1374 1375 /* 1376 * When we actually implement ARMv8.1-VHE we should add HCR_E2H to 1377 * HCR_MASK and then clear it again if the feature bit is not set in 1378 * hcr_write(). 1379 */ 1380 #define HCR_MASK ((1ULL << 34) - 1) 1381 1382 #define SCR_NS (1U << 0) 1383 #define SCR_IRQ (1U << 1) 1384 #define SCR_FIQ (1U << 2) 1385 #define SCR_EA (1U << 3) 1386 #define SCR_FW (1U << 4) 1387 #define SCR_AW (1U << 5) 1388 #define SCR_NET (1U << 6) 1389 #define SCR_SMD (1U << 7) 1390 #define SCR_HCE (1U << 8) 1391 #define SCR_SIF (1U << 9) 1392 #define SCR_RW (1U << 10) 1393 #define SCR_ST (1U << 11) 1394 #define SCR_TWI (1U << 12) 1395 #define SCR_TWE (1U << 13) 1396 #define SCR_TLOR (1U << 14) 1397 #define SCR_TERR (1U << 15) 1398 #define SCR_APK (1U << 16) 1399 #define SCR_API (1U << 17) 1400 #define SCR_EEL2 (1U << 18) 1401 #define SCR_EASE (1U << 19) 1402 #define SCR_NMEA (1U << 20) 1403 #define SCR_FIEN (1U << 21) 1404 #define SCR_ENSCXT (1U << 25) 1405 #define SCR_ATA (1U << 26) 1406 1407 /* Return the current FPSCR value. */ 1408 uint32_t vfp_get_fpscr(CPUARMState *env); 1409 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1410 1411 /* FPCR, Floating Point Control Register 1412 * FPSR, Floating Poiht Status Register 1413 * 1414 * For A64 the FPSCR is split into two logically distinct registers, 1415 * FPCR and FPSR. However since they still use non-overlapping bits 1416 * we store the underlying state in fpscr and just mask on read/write. 1417 */ 1418 #define FPSR_MASK 0xf800009f 1419 #define FPCR_MASK 0x07ff9f00 1420 1421 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1422 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1423 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1424 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1425 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1426 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1427 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1428 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1429 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1430 1431 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1432 { 1433 return vfp_get_fpscr(env) & FPSR_MASK; 1434 } 1435 1436 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1437 { 1438 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1439 vfp_set_fpscr(env, new_fpscr); 1440 } 1441 1442 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1443 { 1444 return vfp_get_fpscr(env) & FPCR_MASK; 1445 } 1446 1447 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1448 { 1449 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1450 vfp_set_fpscr(env, new_fpscr); 1451 } 1452 1453 enum arm_cpu_mode { 1454 ARM_CPU_MODE_USR = 0x10, 1455 ARM_CPU_MODE_FIQ = 0x11, 1456 ARM_CPU_MODE_IRQ = 0x12, 1457 ARM_CPU_MODE_SVC = 0x13, 1458 ARM_CPU_MODE_MON = 0x16, 1459 ARM_CPU_MODE_ABT = 0x17, 1460 ARM_CPU_MODE_HYP = 0x1a, 1461 ARM_CPU_MODE_UND = 0x1b, 1462 ARM_CPU_MODE_SYS = 0x1f 1463 }; 1464 1465 /* VFP system registers. */ 1466 #define ARM_VFP_FPSID 0 1467 #define ARM_VFP_FPSCR 1 1468 #define ARM_VFP_MVFR2 5 1469 #define ARM_VFP_MVFR1 6 1470 #define ARM_VFP_MVFR0 7 1471 #define ARM_VFP_FPEXC 8 1472 #define ARM_VFP_FPINST 9 1473 #define ARM_VFP_FPINST2 10 1474 1475 /* iwMMXt coprocessor control registers. */ 1476 #define ARM_IWMMXT_wCID 0 1477 #define ARM_IWMMXT_wCon 1 1478 #define ARM_IWMMXT_wCSSF 2 1479 #define ARM_IWMMXT_wCASF 3 1480 #define ARM_IWMMXT_wCGR0 8 1481 #define ARM_IWMMXT_wCGR1 9 1482 #define ARM_IWMMXT_wCGR2 10 1483 #define ARM_IWMMXT_wCGR3 11 1484 1485 /* V7M CCR bits */ 1486 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1487 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1488 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1489 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1490 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1491 FIELD(V7M_CCR, STKALIGN, 9, 1) 1492 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1493 FIELD(V7M_CCR, DC, 16, 1) 1494 FIELD(V7M_CCR, IC, 17, 1) 1495 FIELD(V7M_CCR, BP, 18, 1) 1496 1497 /* V7M SCR bits */ 1498 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1499 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1500 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1501 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1502 1503 /* V7M AIRCR bits */ 1504 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1505 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1506 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1507 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1508 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1509 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1510 FIELD(V7M_AIRCR, PRIS, 14, 1) 1511 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1512 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1513 1514 /* V7M CFSR bits for MMFSR */ 1515 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1516 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1517 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1518 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1519 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1520 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1521 1522 /* V7M CFSR bits for BFSR */ 1523 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1524 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1525 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1526 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1527 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1528 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1529 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1530 1531 /* V7M CFSR bits for UFSR */ 1532 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1533 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1534 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1535 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1536 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1537 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1538 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1539 1540 /* V7M CFSR bit masks covering all of the subregister bits */ 1541 FIELD(V7M_CFSR, MMFSR, 0, 8) 1542 FIELD(V7M_CFSR, BFSR, 8, 8) 1543 FIELD(V7M_CFSR, UFSR, 16, 16) 1544 1545 /* V7M HFSR bits */ 1546 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1547 FIELD(V7M_HFSR, FORCED, 30, 1) 1548 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1549 1550 /* V7M DFSR bits */ 1551 FIELD(V7M_DFSR, HALTED, 0, 1) 1552 FIELD(V7M_DFSR, BKPT, 1, 1) 1553 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1554 FIELD(V7M_DFSR, VCATCH, 3, 1) 1555 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1556 1557 /* V7M SFSR bits */ 1558 FIELD(V7M_SFSR, INVEP, 0, 1) 1559 FIELD(V7M_SFSR, INVIS, 1, 1) 1560 FIELD(V7M_SFSR, INVER, 2, 1) 1561 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1562 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1563 FIELD(V7M_SFSR, LSPERR, 5, 1) 1564 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1565 FIELD(V7M_SFSR, LSERR, 7, 1) 1566 1567 /* v7M MPU_CTRL bits */ 1568 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1569 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1570 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1571 1572 /* v7M CLIDR bits */ 1573 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1574 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1575 FIELD(V7M_CLIDR, LOC, 24, 3) 1576 FIELD(V7M_CLIDR, LOUU, 27, 3) 1577 FIELD(V7M_CLIDR, ICB, 30, 2) 1578 1579 FIELD(V7M_CSSELR, IND, 0, 1) 1580 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1581 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1582 * define a mask for this and check that it doesn't permit running off 1583 * the end of the array. 1584 */ 1585 FIELD(V7M_CSSELR, INDEX, 0, 4) 1586 1587 /* 1588 * System register ID fields. 1589 */ 1590 FIELD(ID_ISAR0, SWAP, 0, 4) 1591 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1592 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1593 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1594 FIELD(ID_ISAR0, COPROC, 16, 4) 1595 FIELD(ID_ISAR0, DEBUG, 20, 4) 1596 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1597 1598 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1599 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1600 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1601 FIELD(ID_ISAR1, EXTEND, 12, 4) 1602 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1603 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1604 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1605 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1606 1607 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1608 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1609 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1610 FIELD(ID_ISAR2, MULT, 12, 4) 1611 FIELD(ID_ISAR2, MULTS, 16, 4) 1612 FIELD(ID_ISAR2, MULTU, 20, 4) 1613 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1614 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1615 1616 FIELD(ID_ISAR3, SATURATE, 0, 4) 1617 FIELD(ID_ISAR3, SIMD, 4, 4) 1618 FIELD(ID_ISAR3, SVC, 8, 4) 1619 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1620 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1621 FIELD(ID_ISAR3, T32COPY, 20, 4) 1622 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1623 FIELD(ID_ISAR3, T32EE, 28, 4) 1624 1625 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1626 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1627 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1628 FIELD(ID_ISAR4, SMC, 12, 4) 1629 FIELD(ID_ISAR4, BARRIER, 16, 4) 1630 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1631 FIELD(ID_ISAR4, PSR_M, 24, 4) 1632 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1633 1634 FIELD(ID_ISAR5, SEVL, 0, 4) 1635 FIELD(ID_ISAR5, AES, 4, 4) 1636 FIELD(ID_ISAR5, SHA1, 8, 4) 1637 FIELD(ID_ISAR5, SHA2, 12, 4) 1638 FIELD(ID_ISAR5, CRC32, 16, 4) 1639 FIELD(ID_ISAR5, RDM, 24, 4) 1640 FIELD(ID_ISAR5, VCMA, 28, 4) 1641 1642 FIELD(ID_ISAR6, JSCVT, 0, 4) 1643 FIELD(ID_ISAR6, DP, 4, 4) 1644 FIELD(ID_ISAR6, FHM, 8, 4) 1645 FIELD(ID_ISAR6, SB, 12, 4) 1646 FIELD(ID_ISAR6, SPECRES, 16, 4) 1647 1648 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1649 FIELD(ID_MMFR4, AC2, 4, 4) 1650 FIELD(ID_MMFR4, XNX, 8, 4) 1651 FIELD(ID_MMFR4, CNP, 12, 4) 1652 FIELD(ID_MMFR4, HPDS, 16, 4) 1653 FIELD(ID_MMFR4, LSM, 20, 4) 1654 FIELD(ID_MMFR4, CCIDX, 24, 4) 1655 FIELD(ID_MMFR4, EVT, 28, 4) 1656 1657 FIELD(ID_AA64ISAR0, AES, 4, 4) 1658 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1659 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1660 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1661 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1662 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1663 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1664 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1665 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1666 FIELD(ID_AA64ISAR0, DP, 44, 4) 1667 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1668 FIELD(ID_AA64ISAR0, TS, 52, 4) 1669 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1670 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1671 1672 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1673 FIELD(ID_AA64ISAR1, APA, 4, 4) 1674 FIELD(ID_AA64ISAR1, API, 8, 4) 1675 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1676 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1677 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1678 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1679 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1680 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1681 FIELD(ID_AA64ISAR1, SB, 36, 4) 1682 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1683 1684 FIELD(ID_AA64PFR0, EL0, 0, 4) 1685 FIELD(ID_AA64PFR0, EL1, 4, 4) 1686 FIELD(ID_AA64PFR0, EL2, 8, 4) 1687 FIELD(ID_AA64PFR0, EL3, 12, 4) 1688 FIELD(ID_AA64PFR0, FP, 16, 4) 1689 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1690 FIELD(ID_AA64PFR0, GIC, 24, 4) 1691 FIELD(ID_AA64PFR0, RAS, 28, 4) 1692 FIELD(ID_AA64PFR0, SVE, 32, 4) 1693 1694 FIELD(ID_AA64PFR1, BT, 0, 4) 1695 FIELD(ID_AA64PFR1, SBSS, 4, 4) 1696 FIELD(ID_AA64PFR1, MTE, 8, 4) 1697 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1698 1699 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1700 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1701 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1702 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1703 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1704 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1705 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1706 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1707 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1708 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1709 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1710 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1711 1712 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1713 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1714 FIELD(ID_AA64MMFR1, VH, 8, 4) 1715 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1716 FIELD(ID_AA64MMFR1, LO, 16, 4) 1717 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1718 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1719 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1720 1721 FIELD(ID_DFR0, COPDBG, 0, 4) 1722 FIELD(ID_DFR0, COPSDBG, 4, 4) 1723 FIELD(ID_DFR0, MMAPDBG, 8, 4) 1724 FIELD(ID_DFR0, COPTRC, 12, 4) 1725 FIELD(ID_DFR0, MMAPTRC, 16, 4) 1726 FIELD(ID_DFR0, MPROFDBG, 20, 4) 1727 FIELD(ID_DFR0, PERFMON, 24, 4) 1728 FIELD(ID_DFR0, TRACEFILT, 28, 4) 1729 1730 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1731 1732 /* If adding a feature bit which corresponds to a Linux ELF 1733 * HWCAP bit, remember to update the feature-bit-to-hwcap 1734 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1735 */ 1736 enum arm_features { 1737 ARM_FEATURE_VFP, 1738 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1739 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1740 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1741 ARM_FEATURE_V6, 1742 ARM_FEATURE_V6K, 1743 ARM_FEATURE_V7, 1744 ARM_FEATURE_THUMB2, 1745 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1746 ARM_FEATURE_VFP3, 1747 ARM_FEATURE_VFP_FP16, 1748 ARM_FEATURE_NEON, 1749 ARM_FEATURE_M, /* Microcontroller profile. */ 1750 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1751 ARM_FEATURE_THUMB2EE, 1752 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1753 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1754 ARM_FEATURE_V4T, 1755 ARM_FEATURE_V5, 1756 ARM_FEATURE_STRONGARM, 1757 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1758 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1759 ARM_FEATURE_GENERIC_TIMER, 1760 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1761 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1762 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1763 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1764 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1765 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1766 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1767 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1768 ARM_FEATURE_V8, 1769 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1770 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1771 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1772 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1773 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1774 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1775 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1776 ARM_FEATURE_PMU, /* has PMU support */ 1777 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1778 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1779 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1780 }; 1781 1782 static inline int arm_feature(CPUARMState *env, int feature) 1783 { 1784 return (env->features & (1ULL << feature)) != 0; 1785 } 1786 1787 #if !defined(CONFIG_USER_ONLY) 1788 /* Return true if exception levels below EL3 are in secure state, 1789 * or would be following an exception return to that level. 1790 * Unlike arm_is_secure() (which is always a question about the 1791 * _current_ state of the CPU) this doesn't care about the current 1792 * EL or mode. 1793 */ 1794 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1795 { 1796 if (arm_feature(env, ARM_FEATURE_EL3)) { 1797 return !(env->cp15.scr_el3 & SCR_NS); 1798 } else { 1799 /* If EL3 is not supported then the secure state is implementation 1800 * defined, in which case QEMU defaults to non-secure. 1801 */ 1802 return false; 1803 } 1804 } 1805 1806 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1807 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1808 { 1809 if (arm_feature(env, ARM_FEATURE_EL3)) { 1810 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1811 /* CPU currently in AArch64 state and EL3 */ 1812 return true; 1813 } else if (!is_a64(env) && 1814 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1815 /* CPU currently in AArch32 state and monitor mode */ 1816 return true; 1817 } 1818 } 1819 return false; 1820 } 1821 1822 /* Return true if the processor is in secure state */ 1823 static inline bool arm_is_secure(CPUARMState *env) 1824 { 1825 if (arm_is_el3_or_mon(env)) { 1826 return true; 1827 } 1828 return arm_is_secure_below_el3(env); 1829 } 1830 1831 #else 1832 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1833 { 1834 return false; 1835 } 1836 1837 static inline bool arm_is_secure(CPUARMState *env) 1838 { 1839 return false; 1840 } 1841 #endif 1842 1843 /** 1844 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 1845 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 1846 * "for all purposes other than a direct read or write access of HCR_EL2." 1847 * Not included here is HCR_RW. 1848 */ 1849 uint64_t arm_hcr_el2_eff(CPUARMState *env); 1850 1851 /* Return true if the specified exception level is running in AArch64 state. */ 1852 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1853 { 1854 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1855 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1856 */ 1857 assert(el >= 1 && el <= 3); 1858 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1859 1860 /* The highest exception level is always at the maximum supported 1861 * register width, and then lower levels have a register width controlled 1862 * by bits in the SCR or HCR registers. 1863 */ 1864 if (el == 3) { 1865 return aa64; 1866 } 1867 1868 if (arm_feature(env, ARM_FEATURE_EL3)) { 1869 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1870 } 1871 1872 if (el == 2) { 1873 return aa64; 1874 } 1875 1876 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1877 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1878 } 1879 1880 return aa64; 1881 } 1882 1883 /* Function for determing whether guest cp register reads and writes should 1884 * access the secure or non-secure bank of a cp register. When EL3 is 1885 * operating in AArch32 state, the NS-bit determines whether the secure 1886 * instance of a cp register should be used. When EL3 is AArch64 (or if 1887 * it doesn't exist at all) then there is no register banking, and all 1888 * accesses are to the non-secure version. 1889 */ 1890 static inline bool access_secure_reg(CPUARMState *env) 1891 { 1892 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1893 !arm_el_is_aa64(env, 3) && 1894 !(env->cp15.scr_el3 & SCR_NS)); 1895 1896 return ret; 1897 } 1898 1899 /* Macros for accessing a specified CP register bank */ 1900 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1901 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1902 1903 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1904 do { \ 1905 if (_secure) { \ 1906 (_env)->cp15._regname##_s = (_val); \ 1907 } else { \ 1908 (_env)->cp15._regname##_ns = (_val); \ 1909 } \ 1910 } while (0) 1911 1912 /* Macros for automatically accessing a specific CP register bank depending on 1913 * the current secure state of the system. These macros are not intended for 1914 * supporting instruction translation reads/writes as these are dependent 1915 * solely on the SCR.NS bit and not the mode. 1916 */ 1917 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1918 A32_BANKED_REG_GET((_env), _regname, \ 1919 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1920 1921 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1922 A32_BANKED_REG_SET((_env), _regname, \ 1923 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1924 (_val)) 1925 1926 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1927 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1928 uint32_t cur_el, bool secure); 1929 1930 /* Interface between CPU and Interrupt controller. */ 1931 #ifndef CONFIG_USER_ONLY 1932 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1933 #else 1934 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1935 { 1936 return true; 1937 } 1938 #endif 1939 /** 1940 * armv7m_nvic_set_pending: mark the specified exception as pending 1941 * @opaque: the NVIC 1942 * @irq: the exception number to mark pending 1943 * @secure: false for non-banked exceptions or for the nonsecure 1944 * version of a banked exception, true for the secure version of a banked 1945 * exception. 1946 * 1947 * Marks the specified exception as pending. Note that we will assert() 1948 * if @secure is true and @irq does not specify one of the fixed set 1949 * of architecturally banked exceptions. 1950 */ 1951 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1952 /** 1953 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 1954 * @opaque: the NVIC 1955 * @irq: the exception number to mark pending 1956 * @secure: false for non-banked exceptions or for the nonsecure 1957 * version of a banked exception, true for the secure version of a banked 1958 * exception. 1959 * 1960 * Similar to armv7m_nvic_set_pending(), but specifically for derived 1961 * exceptions (exceptions generated in the course of trying to take 1962 * a different exception). 1963 */ 1964 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 1965 /** 1966 * armv7m_nvic_get_pending_irq_info: return highest priority pending 1967 * exception, and whether it targets Secure state 1968 * @opaque: the NVIC 1969 * @pirq: set to pending exception number 1970 * @ptargets_secure: set to whether pending exception targets Secure 1971 * 1972 * This function writes the number of the highest priority pending 1973 * exception (the one which would be made active by 1974 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 1975 * to true if the current highest priority pending exception should 1976 * be taken to Secure state, false for NS. 1977 */ 1978 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 1979 bool *ptargets_secure); 1980 /** 1981 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 1982 * @opaque: the NVIC 1983 * 1984 * Move the current highest priority pending exception from the pending 1985 * state to the active state, and update v7m.exception to indicate that 1986 * it is the exception currently being handled. 1987 */ 1988 void armv7m_nvic_acknowledge_irq(void *opaque); 1989 /** 1990 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1991 * @opaque: the NVIC 1992 * @irq: the exception number to complete 1993 * @secure: true if this exception was secure 1994 * 1995 * Returns: -1 if the irq was not active 1996 * 1 if completing this irq brought us back to base (no active irqs) 1997 * 0 if there is still an irq active after this one was completed 1998 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1999 */ 2000 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2001 /** 2002 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2003 * @opaque: the NVIC 2004 * 2005 * Returns: the raw execution priority as defined by the v8M architecture. 2006 * This is the execution priority minus the effects of AIRCR.PRIS, 2007 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2008 * (v8M ARM ARM I_PKLD.) 2009 */ 2010 int armv7m_nvic_raw_execution_priority(void *opaque); 2011 /** 2012 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2013 * priority is negative for the specified security state. 2014 * @opaque: the NVIC 2015 * @secure: the security state to test 2016 * This corresponds to the pseudocode IsReqExecPriNeg(). 2017 */ 2018 #ifndef CONFIG_USER_ONLY 2019 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2020 #else 2021 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2022 { 2023 return false; 2024 } 2025 #endif 2026 2027 /* Interface for defining coprocessor registers. 2028 * Registers are defined in tables of arm_cp_reginfo structs 2029 * which are passed to define_arm_cp_regs(). 2030 */ 2031 2032 /* When looking up a coprocessor register we look for it 2033 * via an integer which encodes all of: 2034 * coprocessor number 2035 * Crn, Crm, opc1, opc2 fields 2036 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2037 * or via MRRC/MCRR?) 2038 * non-secure/secure bank (AArch32 only) 2039 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2040 * (In this case crn and opc2 should be zero.) 2041 * For AArch64, there is no 32/64 bit size distinction; 2042 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2043 * and 4 bit CRn and CRm. The encoding patterns are chosen 2044 * to be easy to convert to and from the KVM encodings, and also 2045 * so that the hashtable can contain both AArch32 and AArch64 2046 * registers (to allow for interprocessing where we might run 2047 * 32 bit code on a 64 bit core). 2048 */ 2049 /* This bit is private to our hashtable cpreg; in KVM register 2050 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2051 * in the upper bits of the 64 bit ID. 2052 */ 2053 #define CP_REG_AA64_SHIFT 28 2054 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2055 2056 /* To enable banking of coprocessor registers depending on ns-bit we 2057 * add a bit to distinguish between secure and non-secure cpregs in the 2058 * hashtable. 2059 */ 2060 #define CP_REG_NS_SHIFT 29 2061 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2062 2063 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2064 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2065 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2066 2067 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2068 (CP_REG_AA64_MASK | \ 2069 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2070 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2071 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2072 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2073 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2074 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2075 2076 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2077 * version used as a key for the coprocessor register hashtable 2078 */ 2079 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2080 { 2081 uint32_t cpregid = kvmid; 2082 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2083 cpregid |= CP_REG_AA64_MASK; 2084 } else { 2085 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2086 cpregid |= (1 << 15); 2087 } 2088 2089 /* KVM is always non-secure so add the NS flag on AArch32 register 2090 * entries. 2091 */ 2092 cpregid |= 1 << CP_REG_NS_SHIFT; 2093 } 2094 return cpregid; 2095 } 2096 2097 /* Convert a truncated 32 bit hashtable key into the full 2098 * 64 bit KVM register ID. 2099 */ 2100 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2101 { 2102 uint64_t kvmid; 2103 2104 if (cpregid & CP_REG_AA64_MASK) { 2105 kvmid = cpregid & ~CP_REG_AA64_MASK; 2106 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2107 } else { 2108 kvmid = cpregid & ~(1 << 15); 2109 if (cpregid & (1 << 15)) { 2110 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2111 } else { 2112 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2113 } 2114 } 2115 return kvmid; 2116 } 2117 2118 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2119 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2120 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2121 * TCG can assume the value to be constant (ie load at translate time) 2122 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2123 * indicates that the TB should not be ended after a write to this register 2124 * (the default is that the TB ends after cp writes). OVERRIDE permits 2125 * a register definition to override a previous definition for the 2126 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2127 * old must have the OVERRIDE bit set. 2128 * ALIAS indicates that this register is an alias view of some underlying 2129 * state which is also visible via another register, and that the other 2130 * register is handling migration and reset; registers marked ALIAS will not be 2131 * migrated but may have their state set by syncing of register state from KVM. 2132 * NO_RAW indicates that this register has no underlying state and does not 2133 * support raw access for state saving/loading; it will not be used for either 2134 * migration or KVM state synchronization. (Typically this is for "registers" 2135 * which are actually used as instructions for cache maintenance and so on.) 2136 * IO indicates that this register does I/O and therefore its accesses 2137 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2138 * registers which implement clocks or timers require this. 2139 */ 2140 #define ARM_CP_SPECIAL 0x0001 2141 #define ARM_CP_CONST 0x0002 2142 #define ARM_CP_64BIT 0x0004 2143 #define ARM_CP_SUPPRESS_TB_END 0x0008 2144 #define ARM_CP_OVERRIDE 0x0010 2145 #define ARM_CP_ALIAS 0x0020 2146 #define ARM_CP_IO 0x0040 2147 #define ARM_CP_NO_RAW 0x0080 2148 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2149 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2150 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2151 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2152 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2153 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2154 #define ARM_CP_FPU 0x1000 2155 #define ARM_CP_SVE 0x2000 2156 #define ARM_CP_NO_GDB 0x4000 2157 /* Used only as a terminator for ARMCPRegInfo lists */ 2158 #define ARM_CP_SENTINEL 0xffff 2159 /* Mask of only the flag bits in a type field */ 2160 #define ARM_CP_FLAG_MASK 0x70ff 2161 2162 /* Valid values for ARMCPRegInfo state field, indicating which of 2163 * the AArch32 and AArch64 execution states this register is visible in. 2164 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2165 * If the reginfo is declared to be visible in both states then a second 2166 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2167 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2168 * Note that we rely on the values of these enums as we iterate through 2169 * the various states in some places. 2170 */ 2171 enum { 2172 ARM_CP_STATE_AA32 = 0, 2173 ARM_CP_STATE_AA64 = 1, 2174 ARM_CP_STATE_BOTH = 2, 2175 }; 2176 2177 /* ARM CP register secure state flags. These flags identify security state 2178 * attributes for a given CP register entry. 2179 * The existence of both or neither secure and non-secure flags indicates that 2180 * the register has both a secure and non-secure hash entry. A single one of 2181 * these flags causes the register to only be hashed for the specified 2182 * security state. 2183 * Although definitions may have any combination of the S/NS bits, each 2184 * registered entry will only have one to identify whether the entry is secure 2185 * or non-secure. 2186 */ 2187 enum { 2188 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2189 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2190 }; 2191 2192 /* Return true if cptype is a valid type field. This is used to try to 2193 * catch errors where the sentinel has been accidentally left off the end 2194 * of a list of registers. 2195 */ 2196 static inline bool cptype_valid(int cptype) 2197 { 2198 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2199 || ((cptype & ARM_CP_SPECIAL) && 2200 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2201 } 2202 2203 /* Access rights: 2204 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2205 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2206 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2207 * (ie any of the privileged modes in Secure state, or Monitor mode). 2208 * If a register is accessible in one privilege level it's always accessible 2209 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2210 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2211 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2212 * terminology a little and call this PL3. 2213 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2214 * with the ELx exception levels. 2215 * 2216 * If access permissions for a register are more complex than can be 2217 * described with these bits, then use a laxer set of restrictions, and 2218 * do the more restrictive/complex check inside a helper function. 2219 */ 2220 #define PL3_R 0x80 2221 #define PL3_W 0x40 2222 #define PL2_R (0x20 | PL3_R) 2223 #define PL2_W (0x10 | PL3_W) 2224 #define PL1_R (0x08 | PL2_R) 2225 #define PL1_W (0x04 | PL2_W) 2226 #define PL0_R (0x02 | PL1_R) 2227 #define PL0_W (0x01 | PL1_W) 2228 2229 #define PL3_RW (PL3_R | PL3_W) 2230 #define PL2_RW (PL2_R | PL2_W) 2231 #define PL1_RW (PL1_R | PL1_W) 2232 #define PL0_RW (PL0_R | PL0_W) 2233 2234 /* Return the highest implemented Exception Level */ 2235 static inline int arm_highest_el(CPUARMState *env) 2236 { 2237 if (arm_feature(env, ARM_FEATURE_EL3)) { 2238 return 3; 2239 } 2240 if (arm_feature(env, ARM_FEATURE_EL2)) { 2241 return 2; 2242 } 2243 return 1; 2244 } 2245 2246 /* Return true if a v7M CPU is in Handler mode */ 2247 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2248 { 2249 return env->v7m.exception != 0; 2250 } 2251 2252 /* Return the current Exception Level (as per ARMv8; note that this differs 2253 * from the ARMv7 Privilege Level). 2254 */ 2255 static inline int arm_current_el(CPUARMState *env) 2256 { 2257 if (arm_feature(env, ARM_FEATURE_M)) { 2258 return arm_v7m_is_handler_mode(env) || 2259 !(env->v7m.control[env->v7m.secure] & 1); 2260 } 2261 2262 if (is_a64(env)) { 2263 return extract32(env->pstate, 2, 2); 2264 } 2265 2266 switch (env->uncached_cpsr & 0x1f) { 2267 case ARM_CPU_MODE_USR: 2268 return 0; 2269 case ARM_CPU_MODE_HYP: 2270 return 2; 2271 case ARM_CPU_MODE_MON: 2272 return 3; 2273 default: 2274 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2275 /* If EL3 is 32-bit then all secure privileged modes run in 2276 * EL3 2277 */ 2278 return 3; 2279 } 2280 2281 return 1; 2282 } 2283 } 2284 2285 typedef struct ARMCPRegInfo ARMCPRegInfo; 2286 2287 typedef enum CPAccessResult { 2288 /* Access is permitted */ 2289 CP_ACCESS_OK = 0, 2290 /* Access fails due to a configurable trap or enable which would 2291 * result in a categorized exception syndrome giving information about 2292 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2293 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2294 * PL1 if in EL0, otherwise to the current EL). 2295 */ 2296 CP_ACCESS_TRAP = 1, 2297 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2298 * Note that this is not a catch-all case -- the set of cases which may 2299 * result in this failure is specifically defined by the architecture. 2300 */ 2301 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2302 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2303 CP_ACCESS_TRAP_EL2 = 3, 2304 CP_ACCESS_TRAP_EL3 = 4, 2305 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2306 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2307 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2308 /* Access fails and results in an exception syndrome for an FP access, 2309 * trapped directly to EL2 or EL3 2310 */ 2311 CP_ACCESS_TRAP_FP_EL2 = 7, 2312 CP_ACCESS_TRAP_FP_EL3 = 8, 2313 } CPAccessResult; 2314 2315 /* Access functions for coprocessor registers. These cannot fail and 2316 * may not raise exceptions. 2317 */ 2318 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2319 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2320 uint64_t value); 2321 /* Access permission check functions for coprocessor registers. */ 2322 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2323 const ARMCPRegInfo *opaque, 2324 bool isread); 2325 /* Hook function for register reset */ 2326 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2327 2328 #define CP_ANY 0xff 2329 2330 /* Definition of an ARM coprocessor register */ 2331 struct ARMCPRegInfo { 2332 /* Name of register (useful mainly for debugging, need not be unique) */ 2333 const char *name; 2334 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2335 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2336 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2337 * will be decoded to this register. The register read and write 2338 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2339 * used by the program, so it is possible to register a wildcard and 2340 * then behave differently on read/write if necessary. 2341 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2342 * must both be zero. 2343 * For AArch64-visible registers, opc0 is also used. 2344 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2345 * way to distinguish (for KVM's benefit) guest-visible system registers 2346 * from demuxed ones provided to preserve the "no side effects on 2347 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2348 * visible (to match KVM's encoding); cp==0 will be converted to 2349 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2350 */ 2351 uint8_t cp; 2352 uint8_t crn; 2353 uint8_t crm; 2354 uint8_t opc0; 2355 uint8_t opc1; 2356 uint8_t opc2; 2357 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2358 int state; 2359 /* Register type: ARM_CP_* bits/values */ 2360 int type; 2361 /* Access rights: PL*_[RW] */ 2362 int access; 2363 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2364 int secure; 2365 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2366 * this register was defined: can be used to hand data through to the 2367 * register read/write functions, since they are passed the ARMCPRegInfo*. 2368 */ 2369 void *opaque; 2370 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2371 * fieldoffset is non-zero, the reset value of the register. 2372 */ 2373 uint64_t resetvalue; 2374 /* Offset of the field in CPUARMState for this register. 2375 * 2376 * This is not needed if either: 2377 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2378 * 2. both readfn and writefn are specified 2379 */ 2380 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2381 2382 /* Offsets of the secure and non-secure fields in CPUARMState for the 2383 * register if it is banked. These fields are only used during the static 2384 * registration of a register. During hashing the bank associated 2385 * with a given security state is copied to fieldoffset which is used from 2386 * there on out. 2387 * 2388 * It is expected that register definitions use either fieldoffset or 2389 * bank_fieldoffsets in the definition but not both. It is also expected 2390 * that both bank offsets are set when defining a banked register. This 2391 * use indicates that a register is banked. 2392 */ 2393 ptrdiff_t bank_fieldoffsets[2]; 2394 2395 /* Function for making any access checks for this register in addition to 2396 * those specified by the 'access' permissions bits. If NULL, no extra 2397 * checks required. The access check is performed at runtime, not at 2398 * translate time. 2399 */ 2400 CPAccessFn *accessfn; 2401 /* Function for handling reads of this register. If NULL, then reads 2402 * will be done by loading from the offset into CPUARMState specified 2403 * by fieldoffset. 2404 */ 2405 CPReadFn *readfn; 2406 /* Function for handling writes of this register. If NULL, then writes 2407 * will be done by writing to the offset into CPUARMState specified 2408 * by fieldoffset. 2409 */ 2410 CPWriteFn *writefn; 2411 /* Function for doing a "raw" read; used when we need to copy 2412 * coprocessor state to the kernel for KVM or out for 2413 * migration. This only needs to be provided if there is also a 2414 * readfn and it has side effects (for instance clear-on-read bits). 2415 */ 2416 CPReadFn *raw_readfn; 2417 /* Function for doing a "raw" write; used when we need to copy KVM 2418 * kernel coprocessor state into userspace, or for inbound 2419 * migration. This only needs to be provided if there is also a 2420 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2421 * or similar behaviour. 2422 */ 2423 CPWriteFn *raw_writefn; 2424 /* Function for resetting the register. If NULL, then reset will be done 2425 * by writing resetvalue to the field specified in fieldoffset. If 2426 * fieldoffset is 0 then no reset will be done. 2427 */ 2428 CPResetFn *resetfn; 2429 }; 2430 2431 /* Macros which are lvalues for the field in CPUARMState for the 2432 * ARMCPRegInfo *ri. 2433 */ 2434 #define CPREG_FIELD32(env, ri) \ 2435 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2436 #define CPREG_FIELD64(env, ri) \ 2437 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2438 2439 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2440 2441 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2442 const ARMCPRegInfo *regs, void *opaque); 2443 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2444 const ARMCPRegInfo *regs, void *opaque); 2445 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2446 { 2447 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2448 } 2449 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2450 { 2451 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2452 } 2453 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2454 2455 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2456 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2457 uint64_t value); 2458 /* CPReadFn that can be used for read-as-zero behaviour */ 2459 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2460 2461 /* CPResetFn that does nothing, for use if no reset is required even 2462 * if fieldoffset is non zero. 2463 */ 2464 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2465 2466 /* Return true if this reginfo struct's field in the cpu state struct 2467 * is 64 bits wide. 2468 */ 2469 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2470 { 2471 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2472 } 2473 2474 static inline bool cp_access_ok(int current_el, 2475 const ARMCPRegInfo *ri, int isread) 2476 { 2477 return (ri->access >> ((current_el * 2) + isread)) & 1; 2478 } 2479 2480 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2481 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2482 2483 /** 2484 * write_list_to_cpustate 2485 * @cpu: ARMCPU 2486 * 2487 * For each register listed in the ARMCPU cpreg_indexes list, write 2488 * its value from the cpreg_values list into the ARMCPUState structure. 2489 * This updates TCG's working data structures from KVM data or 2490 * from incoming migration state. 2491 * 2492 * Returns: true if all register values were updated correctly, 2493 * false if some register was unknown or could not be written. 2494 * Note that we do not stop early on failure -- we will attempt 2495 * writing all registers in the list. 2496 */ 2497 bool write_list_to_cpustate(ARMCPU *cpu); 2498 2499 /** 2500 * write_cpustate_to_list: 2501 * @cpu: ARMCPU 2502 * 2503 * For each register listed in the ARMCPU cpreg_indexes list, write 2504 * its value from the ARMCPUState structure into the cpreg_values list. 2505 * This is used to copy info from TCG's working data structures into 2506 * KVM or for outbound migration. 2507 * 2508 * Returns: true if all register values were read correctly, 2509 * false if some register was unknown or could not be read. 2510 * Note that we do not stop early on failure -- we will attempt 2511 * reading all registers in the list. 2512 */ 2513 bool write_cpustate_to_list(ARMCPU *cpu); 2514 2515 #define ARM_CPUID_TI915T 0x54029152 2516 #define ARM_CPUID_TI925T 0x54029252 2517 2518 #if defined(CONFIG_USER_ONLY) 2519 #define TARGET_PAGE_BITS 12 2520 #else 2521 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2522 * have to support 1K tiny pages. 2523 */ 2524 #define TARGET_PAGE_BITS_VARY 2525 #define TARGET_PAGE_BITS_MIN 10 2526 #endif 2527 2528 #if defined(TARGET_AARCH64) 2529 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2530 # define TARGET_VIRT_ADDR_SPACE_BITS 48 2531 #else 2532 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2533 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2534 #endif 2535 2536 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2537 unsigned int target_el) 2538 { 2539 CPUARMState *env = cs->env_ptr; 2540 unsigned int cur_el = arm_current_el(env); 2541 bool secure = arm_is_secure(env); 2542 bool pstate_unmasked; 2543 int8_t unmasked = 0; 2544 uint64_t hcr_el2; 2545 2546 /* Don't take exceptions if they target a lower EL. 2547 * This check should catch any exceptions that would not be taken but left 2548 * pending. 2549 */ 2550 if (cur_el > target_el) { 2551 return false; 2552 } 2553 2554 hcr_el2 = arm_hcr_el2_eff(env); 2555 2556 switch (excp_idx) { 2557 case EXCP_FIQ: 2558 pstate_unmasked = !(env->daif & PSTATE_F); 2559 break; 2560 2561 case EXCP_IRQ: 2562 pstate_unmasked = !(env->daif & PSTATE_I); 2563 break; 2564 2565 case EXCP_VFIQ: 2566 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 2567 /* VFIQs are only taken when hypervized and non-secure. */ 2568 return false; 2569 } 2570 return !(env->daif & PSTATE_F); 2571 case EXCP_VIRQ: 2572 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 2573 /* VIRQs are only taken when hypervized and non-secure. */ 2574 return false; 2575 } 2576 return !(env->daif & PSTATE_I); 2577 default: 2578 g_assert_not_reached(); 2579 } 2580 2581 /* Use the target EL, current execution state and SCR/HCR settings to 2582 * determine whether the corresponding CPSR bit is used to mask the 2583 * interrupt. 2584 */ 2585 if ((target_el > cur_el) && (target_el != 1)) { 2586 /* Exceptions targeting a higher EL may not be maskable */ 2587 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2588 /* 64-bit masking rules are simple: exceptions to EL3 2589 * can't be masked, and exceptions to EL2 can only be 2590 * masked from Secure state. The HCR and SCR settings 2591 * don't affect the masking logic, only the interrupt routing. 2592 */ 2593 if (target_el == 3 || !secure) { 2594 unmasked = 1; 2595 } 2596 } else { 2597 /* The old 32-bit-only environment has a more complicated 2598 * masking setup. HCR and SCR bits not only affect interrupt 2599 * routing but also change the behaviour of masking. 2600 */ 2601 bool hcr, scr; 2602 2603 switch (excp_idx) { 2604 case EXCP_FIQ: 2605 /* If FIQs are routed to EL3 or EL2 then there are cases where 2606 * we override the CPSR.F in determining if the exception is 2607 * masked or not. If neither of these are set then we fall back 2608 * to the CPSR.F setting otherwise we further assess the state 2609 * below. 2610 */ 2611 hcr = hcr_el2 & HCR_FMO; 2612 scr = (env->cp15.scr_el3 & SCR_FIQ); 2613 2614 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2615 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2616 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2617 * when non-secure but only when FIQs are only routed to EL3. 2618 */ 2619 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2620 break; 2621 case EXCP_IRQ: 2622 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2623 * we may override the CPSR.I masking when in non-secure state. 2624 * The SCR.IRQ setting has already been taken into consideration 2625 * when setting the target EL, so it does not have a further 2626 * affect here. 2627 */ 2628 hcr = hcr_el2 & HCR_IMO; 2629 scr = false; 2630 break; 2631 default: 2632 g_assert_not_reached(); 2633 } 2634 2635 if ((scr || hcr) && !secure) { 2636 unmasked = 1; 2637 } 2638 } 2639 } 2640 2641 /* The PSTATE bits only mask the interrupt if we have not overriden the 2642 * ability above. 2643 */ 2644 return unmasked || pstate_unmasked; 2645 } 2646 2647 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2648 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2649 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2650 2651 #define cpu_signal_handler cpu_arm_signal_handler 2652 #define cpu_list arm_cpu_list 2653 2654 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2655 * 2656 * If EL3 is 64-bit: 2657 * + NonSecure EL1 & 0 stage 1 2658 * + NonSecure EL1 & 0 stage 2 2659 * + NonSecure EL2 2660 * + Secure EL1 & EL0 2661 * + Secure EL3 2662 * If EL3 is 32-bit: 2663 * + NonSecure PL1 & 0 stage 1 2664 * + NonSecure PL1 & 0 stage 2 2665 * + NonSecure PL2 2666 * + Secure PL0 & PL1 2667 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2668 * 2669 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2670 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2671 * may differ in access permissions even if the VA->PA map is the same 2672 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2673 * translation, which means that we have one mmu_idx that deals with two 2674 * concatenated translation regimes [this sort of combined s1+2 TLB is 2675 * architecturally permitted] 2676 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2677 * handling via the TLB. The only way to do a stage 1 translation without 2678 * the immediate stage 2 translation is via the ATS or AT system insns, 2679 * which can be slow-pathed and always do a page table walk. 2680 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2681 * translation regimes, because they map reasonably well to each other 2682 * and they can't both be active at the same time. 2683 * This gives us the following list of mmu_idx values: 2684 * 2685 * NS EL0 (aka NS PL0) stage 1+2 2686 * NS EL1 (aka NS PL1) stage 1+2 2687 * NS EL2 (aka NS PL2) 2688 * S EL3 (aka S PL1) 2689 * S EL0 (aka S PL0) 2690 * S EL1 (not used if EL3 is 32 bit) 2691 * NS EL0+1 stage 2 2692 * 2693 * (The last of these is an mmu_idx because we want to be able to use the TLB 2694 * for the accesses done as part of a stage 1 page table walk, rather than 2695 * having to walk the stage 2 page table over and over.) 2696 * 2697 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2698 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2699 * NS EL2 if we ever model a Cortex-R52). 2700 * 2701 * M profile CPUs are rather different as they do not have a true MMU. 2702 * They have the following different MMU indexes: 2703 * User 2704 * Privileged 2705 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2706 * Privileged, execution priority negative (ditto) 2707 * If the CPU supports the v8M Security Extension then there are also: 2708 * Secure User 2709 * Secure Privileged 2710 * Secure User, execution priority negative 2711 * Secure Privileged, execution priority negative 2712 * 2713 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2714 * are not quite the same -- different CPU types (most notably M profile 2715 * vs A/R profile) would like to use MMU indexes with different semantics, 2716 * but since we don't ever need to use all of those in a single CPU we 2717 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2718 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2719 * the same for any particular CPU. 2720 * Variables of type ARMMUIdx are always full values, and the core 2721 * index values are in variables of type 'int'. 2722 * 2723 * Our enumeration includes at the end some entries which are not "true" 2724 * mmu_idx values in that they don't have corresponding TLBs and are only 2725 * valid for doing slow path page table walks. 2726 * 2727 * The constant names here are patterned after the general style of the names 2728 * of the AT/ATS operations. 2729 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2730 * For M profile we arrange them to have a bit for priv, a bit for negpri 2731 * and a bit for secure. 2732 */ 2733 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2734 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2735 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2736 2737 /* meanings of the bits for M profile mmu idx values */ 2738 #define ARM_MMU_IDX_M_PRIV 0x1 2739 #define ARM_MMU_IDX_M_NEGPRI 0x2 2740 #define ARM_MMU_IDX_M_S 0x4 2741 2742 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2743 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2744 2745 typedef enum ARMMMUIdx { 2746 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2747 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2748 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2749 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2750 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2751 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2752 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2753 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2754 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2755 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2756 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2757 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2758 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2759 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2760 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2761 /* Indexes below here don't have TLBs and are used only for AT system 2762 * instructions or for the first stage of an S12 page table walk. 2763 */ 2764 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2765 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2766 } ARMMMUIdx; 2767 2768 /* Bit macros for the core-mmu-index values for each index, 2769 * for use when calling tlb_flush_by_mmuidx() and friends. 2770 */ 2771 typedef enum ARMMMUIdxBit { 2772 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2773 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2774 ARMMMUIdxBit_S1E2 = 1 << 2, 2775 ARMMMUIdxBit_S1E3 = 1 << 3, 2776 ARMMMUIdxBit_S1SE0 = 1 << 4, 2777 ARMMMUIdxBit_S1SE1 = 1 << 5, 2778 ARMMMUIdxBit_S2NS = 1 << 6, 2779 ARMMMUIdxBit_MUser = 1 << 0, 2780 ARMMMUIdxBit_MPriv = 1 << 1, 2781 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2782 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2783 ARMMMUIdxBit_MSUser = 1 << 4, 2784 ARMMMUIdxBit_MSPriv = 1 << 5, 2785 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2786 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2787 } ARMMMUIdxBit; 2788 2789 #define MMU_USER_IDX 0 2790 2791 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2792 { 2793 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2794 } 2795 2796 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2797 { 2798 if (arm_feature(env, ARM_FEATURE_M)) { 2799 return mmu_idx | ARM_MMU_IDX_M; 2800 } else { 2801 return mmu_idx | ARM_MMU_IDX_A; 2802 } 2803 } 2804 2805 /* Return the exception level we're running at if this is our mmu_idx */ 2806 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2807 { 2808 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2809 case ARM_MMU_IDX_A: 2810 return mmu_idx & 3; 2811 case ARM_MMU_IDX_M: 2812 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2813 default: 2814 g_assert_not_reached(); 2815 } 2816 } 2817 2818 /* Return the MMU index for a v7M CPU in the specified security and 2819 * privilege state. 2820 */ 2821 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2822 bool secstate, bool priv); 2823 2824 /* Return the MMU index for a v7M CPU in the specified security state */ 2825 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); 2826 2827 /** 2828 * cpu_mmu_index: 2829 * @env: The cpu environment 2830 * @ifetch: True for code access, false for data access. 2831 * 2832 * Return the core mmu index for the current translation regime. 2833 * This function is used by generic TCG code paths. 2834 */ 2835 int cpu_mmu_index(CPUARMState *env, bool ifetch); 2836 2837 /* Indexes used when registering address spaces with cpu_address_space_init */ 2838 typedef enum ARMASIdx { 2839 ARMASIdx_NS = 0, 2840 ARMASIdx_S = 1, 2841 } ARMASIdx; 2842 2843 /* Return the Exception Level targeted by debug exceptions. */ 2844 static inline int arm_debug_target_el(CPUARMState *env) 2845 { 2846 bool secure = arm_is_secure(env); 2847 bool route_to_el2 = false; 2848 2849 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2850 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2851 env->cp15.mdcr_el2 & MDCR_TDE; 2852 } 2853 2854 if (route_to_el2) { 2855 return 2; 2856 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2857 !arm_el_is_aa64(env, 3) && secure) { 2858 return 3; 2859 } else { 2860 return 1; 2861 } 2862 } 2863 2864 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2865 { 2866 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2867 * CSSELR is RAZ/WI. 2868 */ 2869 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2870 } 2871 2872 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 2873 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2874 { 2875 int cur_el = arm_current_el(env); 2876 int debug_el; 2877 2878 if (cur_el == 3) { 2879 return false; 2880 } 2881 2882 /* MDCR_EL3.SDD disables debug events from Secure state */ 2883 if (arm_is_secure_below_el3(env) 2884 && extract32(env->cp15.mdcr_el3, 16, 1)) { 2885 return false; 2886 } 2887 2888 /* 2889 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 2890 * while not masking the (D)ebug bit in DAIF. 2891 */ 2892 debug_el = arm_debug_target_el(env); 2893 2894 if (cur_el == debug_el) { 2895 return extract32(env->cp15.mdscr_el1, 13, 1) 2896 && !(env->daif & PSTATE_D); 2897 } 2898 2899 /* Otherwise the debug target needs to be a higher EL */ 2900 return debug_el > cur_el; 2901 } 2902 2903 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2904 { 2905 int el = arm_current_el(env); 2906 2907 if (el == 0 && arm_el_is_aa64(env, 1)) { 2908 return aa64_generate_debug_exceptions(env); 2909 } 2910 2911 if (arm_is_secure(env)) { 2912 int spd; 2913 2914 if (el == 0 && (env->cp15.sder & 1)) { 2915 /* SDER.SUIDEN means debug exceptions from Secure EL0 2916 * are always enabled. Otherwise they are controlled by 2917 * SDCR.SPD like those from other Secure ELs. 2918 */ 2919 return true; 2920 } 2921 2922 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2923 switch (spd) { 2924 case 1: 2925 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2926 case 0: 2927 /* For 0b00 we return true if external secure invasive debug 2928 * is enabled. On real hardware this is controlled by external 2929 * signals to the core. QEMU always permits debug, and behaves 2930 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2931 */ 2932 return true; 2933 case 2: 2934 return false; 2935 case 3: 2936 return true; 2937 } 2938 } 2939 2940 return el != 2; 2941 } 2942 2943 /* Return true if debugging exceptions are currently enabled. 2944 * This corresponds to what in ARM ARM pseudocode would be 2945 * if UsingAArch32() then 2946 * return AArch32.GenerateDebugExceptions() 2947 * else 2948 * return AArch64.GenerateDebugExceptions() 2949 * We choose to push the if() down into this function for clarity, 2950 * since the pseudocode has it at all callsites except for the one in 2951 * CheckSoftwareStep(), where it is elided because both branches would 2952 * always return the same value. 2953 */ 2954 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2955 { 2956 if (env->aarch64) { 2957 return aa64_generate_debug_exceptions(env); 2958 } else { 2959 return aa32_generate_debug_exceptions(env); 2960 } 2961 } 2962 2963 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2964 * implicitly means this always returns false in pre-v8 CPUs.) 2965 */ 2966 static inline bool arm_singlestep_active(CPUARMState *env) 2967 { 2968 return extract32(env->cp15.mdscr_el1, 0, 1) 2969 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2970 && arm_generate_debug_exceptions(env); 2971 } 2972 2973 static inline bool arm_sctlr_b(CPUARMState *env) 2974 { 2975 return 2976 /* We need not implement SCTLR.ITD in user-mode emulation, so 2977 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2978 * This lets people run BE32 binaries with "-cpu any". 2979 */ 2980 #ifndef CONFIG_USER_ONLY 2981 !arm_feature(env, ARM_FEATURE_V7) && 2982 #endif 2983 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2984 } 2985 2986 /* Return true if the processor is in big-endian mode. */ 2987 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2988 { 2989 int cur_el; 2990 2991 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2992 if (!is_a64(env)) { 2993 return 2994 #ifdef CONFIG_USER_ONLY 2995 /* In system mode, BE32 is modelled in line with the 2996 * architecture (as word-invariant big-endianness), where loads 2997 * and stores are done little endian but from addresses which 2998 * are adjusted by XORing with the appropriate constant. So the 2999 * endianness to use for the raw data access is not affected by 3000 * SCTLR.B. 3001 * In user mode, however, we model BE32 as byte-invariant 3002 * big-endianness (because user-only code cannot tell the 3003 * difference), and so we need to use a data access endianness 3004 * that depends on SCTLR.B. 3005 */ 3006 arm_sctlr_b(env) || 3007 #endif 3008 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 3009 } 3010 3011 cur_el = arm_current_el(env); 3012 3013 if (cur_el == 0) { 3014 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 3015 } 3016 3017 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 3018 } 3019 3020 #include "exec/cpu-all.h" 3021 3022 /* Bit usage in the TB flags field: bit 31 indicates whether we are 3023 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 3024 * We put flags which are shared between 32 and 64 bit mode at the top 3025 * of the word, and flags which apply to only one mode at the bottom. 3026 */ 3027 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3028 FIELD(TBFLAG_ANY, MMUIDX, 28, 3) 3029 FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) 3030 FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) 3031 /* Target EL if we take a floating-point-disabled exception */ 3032 FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) 3033 FIELD(TBFLAG_ANY, BE_DATA, 23, 1) 3034 3035 /* Bit usage when in AArch32 state: */ 3036 FIELD(TBFLAG_A32, THUMB, 0, 1) 3037 FIELD(TBFLAG_A32, VECLEN, 1, 3) 3038 FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) 3039 FIELD(TBFLAG_A32, VFPEN, 7, 1) 3040 FIELD(TBFLAG_A32, CONDEXEC, 8, 8) 3041 FIELD(TBFLAG_A32, SCTLR_B, 16, 1) 3042 /* We store the bottom two bits of the CPAR as TB flags and handle 3043 * checks on the other bits at runtime 3044 */ 3045 FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) 3046 /* Indicates whether cp register reads and writes by guest code should access 3047 * the secure or nonsecure bank of banked registers; note that this is not 3048 * the same thing as the current security state of the processor! 3049 */ 3050 FIELD(TBFLAG_A32, NS, 19, 1) 3051 /* For M profile only, Handler (ie not Thread) mode */ 3052 FIELD(TBFLAG_A32, HANDLER, 21, 1) 3053 /* For M profile only, whether we should generate stack-limit checks */ 3054 FIELD(TBFLAG_A32, STACKCHECK, 22, 1) 3055 3056 /* Bit usage when in AArch64 state */ 3057 FIELD(TBFLAG_A64, TBII, 0, 2) 3058 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3059 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3060 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3061 FIELD(TBFLAG_A64, BT, 9, 1) 3062 FIELD(TBFLAG_A64, BTYPE, 10, 2) 3063 FIELD(TBFLAG_A64, TBID, 12, 2) 3064 3065 static inline bool bswap_code(bool sctlr_b) 3066 { 3067 #ifdef CONFIG_USER_ONLY 3068 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3069 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3070 * would also end up as a mixed-endian mode with BE code, LE data. 3071 */ 3072 return 3073 #ifdef TARGET_WORDS_BIGENDIAN 3074 1 ^ 3075 #endif 3076 sctlr_b; 3077 #else 3078 /* All code access in ARM is little endian, and there are no loaders 3079 * doing swaps that need to be reversed 3080 */ 3081 return 0; 3082 #endif 3083 } 3084 3085 #ifdef CONFIG_USER_ONLY 3086 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3087 { 3088 return 3089 #ifdef TARGET_WORDS_BIGENDIAN 3090 1 ^ 3091 #endif 3092 arm_cpu_data_is_big_endian(env); 3093 } 3094 #endif 3095 3096 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3097 target_ulong *cs_base, uint32_t *flags); 3098 3099 enum { 3100 QEMU_PSCI_CONDUIT_DISABLED = 0, 3101 QEMU_PSCI_CONDUIT_SMC = 1, 3102 QEMU_PSCI_CONDUIT_HVC = 2, 3103 }; 3104 3105 #ifndef CONFIG_USER_ONLY 3106 /* Return the address space index to use for a memory access */ 3107 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3108 { 3109 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3110 } 3111 3112 /* Return the AddressSpace to use for a memory access 3113 * (which depends on whether the access is S or NS, and whether 3114 * the board gave us a separate AddressSpace for S accesses). 3115 */ 3116 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3117 { 3118 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3119 } 3120 #endif 3121 3122 /** 3123 * arm_register_pre_el_change_hook: 3124 * Register a hook function which will be called immediately before this 3125 * CPU changes exception level or mode. The hook function will be 3126 * passed a pointer to the ARMCPU and the opaque data pointer passed 3127 * to this function when the hook was registered. 3128 * 3129 * Note that if a pre-change hook is called, any registered post-change hooks 3130 * are guaranteed to subsequently be called. 3131 */ 3132 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3133 void *opaque); 3134 /** 3135 * arm_register_el_change_hook: 3136 * Register a hook function which will be called immediately after this 3137 * CPU changes exception level or mode. The hook function will be 3138 * passed a pointer to the ARMCPU and the opaque data pointer passed 3139 * to this function when the hook was registered. 3140 * 3141 * Note that any registered hooks registered here are guaranteed to be called 3142 * if pre-change hooks have been. 3143 */ 3144 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3145 *opaque); 3146 3147 /** 3148 * aa32_vfp_dreg: 3149 * Return a pointer to the Dn register within env in 32-bit mode. 3150 */ 3151 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3152 { 3153 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3154 } 3155 3156 /** 3157 * aa32_vfp_qreg: 3158 * Return a pointer to the Qn register within env in 32-bit mode. 3159 */ 3160 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3161 { 3162 return &env->vfp.zregs[regno].d[0]; 3163 } 3164 3165 /** 3166 * aa64_vfp_qreg: 3167 * Return a pointer to the Qn register within env in 64-bit mode. 3168 */ 3169 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3170 { 3171 return &env->vfp.zregs[regno].d[0]; 3172 } 3173 3174 /* Shared between translate-sve.c and sve_helper.c. */ 3175 extern const uint64_t pred_esz_masks[4]; 3176 3177 /* 3178 * 32-bit feature tests via id registers. 3179 */ 3180 static inline bool isar_feature_thumb_div(const ARMISARegisters *id) 3181 { 3182 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3183 } 3184 3185 static inline bool isar_feature_arm_div(const ARMISARegisters *id) 3186 { 3187 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3188 } 3189 3190 static inline bool isar_feature_jazelle(const ARMISARegisters *id) 3191 { 3192 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3193 } 3194 3195 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3196 { 3197 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3198 } 3199 3200 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3201 { 3202 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3203 } 3204 3205 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3206 { 3207 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3208 } 3209 3210 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3211 { 3212 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3213 } 3214 3215 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3216 { 3217 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3218 } 3219 3220 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3221 { 3222 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3223 } 3224 3225 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3226 { 3227 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3228 } 3229 3230 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3231 { 3232 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3233 } 3234 3235 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3236 { 3237 /* 3238 * This is a placeholder for use by VCMA until the rest of 3239 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3240 * At which point we can properly set and check MVFR1.FPHP. 3241 */ 3242 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3243 } 3244 3245 /* 3246 * 64-bit feature tests via id registers. 3247 */ 3248 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3249 { 3250 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3251 } 3252 3253 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3254 { 3255 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3256 } 3257 3258 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3259 { 3260 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3261 } 3262 3263 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3264 { 3265 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3266 } 3267 3268 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3269 { 3270 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3271 } 3272 3273 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3274 { 3275 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3276 } 3277 3278 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3279 { 3280 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3281 } 3282 3283 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3284 { 3285 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3286 } 3287 3288 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3289 { 3290 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3291 } 3292 3293 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3294 { 3295 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3296 } 3297 3298 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3299 { 3300 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3301 } 3302 3303 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3304 { 3305 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3306 } 3307 3308 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3309 { 3310 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3311 } 3312 3313 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3314 { 3315 /* 3316 * Note that while QEMU will only implement the architected algorithm 3317 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation 3318 * defined algorithms, and thus API+GPI, and this predicate controls 3319 * migration of the 128-bit keys. 3320 */ 3321 return (id->id_aa64isar1 & 3322 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3323 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3324 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3325 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3326 } 3327 3328 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3329 { 3330 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3331 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3332 } 3333 3334 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3335 { 3336 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3337 } 3338 3339 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3340 { 3341 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3342 } 3343 3344 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3345 { 3346 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3347 } 3348 3349 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3350 { 3351 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3352 } 3353 3354 /* 3355 * Forward to the above feature tests given an ARMCPU pointer. 3356 */ 3357 #define cpu_isar_feature(name, cpu) \ 3358 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3359 3360 #endif 3361