1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 #include "cpu-qom.h" 26 #include "exec/cpu-defs.h" 27 28 /* ARM processors have a weak memory model */ 29 #define TCG_GUEST_DEFAULT_MO (0) 30 31 #define EXCP_UDEF 1 /* undefined instruction */ 32 #define EXCP_SWI 2 /* software interrupt */ 33 #define EXCP_PREFETCH_ABORT 3 34 #define EXCP_DATA_ABORT 4 35 #define EXCP_IRQ 5 36 #define EXCP_FIQ 6 37 #define EXCP_BKPT 7 38 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 39 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 40 #define EXCP_HVC 11 /* HyperVisor Call */ 41 #define EXCP_HYP_TRAP 12 42 #define EXCP_SMC 13 /* Secure Monitor Call */ 43 #define EXCP_VIRQ 14 44 #define EXCP_VFIQ 15 45 #define EXCP_SEMIHOST 16 /* semihosting call */ 46 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 47 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 48 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 49 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 50 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 51 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 52 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 53 54 #define ARMV7M_EXCP_RESET 1 55 #define ARMV7M_EXCP_NMI 2 56 #define ARMV7M_EXCP_HARD 3 57 #define ARMV7M_EXCP_MEM 4 58 #define ARMV7M_EXCP_BUS 5 59 #define ARMV7M_EXCP_USAGE 6 60 #define ARMV7M_EXCP_SECURE 7 61 #define ARMV7M_EXCP_SVC 11 62 #define ARMV7M_EXCP_DEBUG 12 63 #define ARMV7M_EXCP_PENDSV 14 64 #define ARMV7M_EXCP_SYSTICK 15 65 66 /* For M profile, some registers are banked secure vs non-secure; 67 * these are represented as a 2-element array where the first element 68 * is the non-secure copy and the second is the secure copy. 69 * When the CPU does not have implement the security extension then 70 * only the first element is used. 71 * This means that the copy for the current security state can be 72 * accessed via env->registerfield[env->v7m.secure] (whether the security 73 * extension is implemented or not). 74 */ 75 enum { 76 M_REG_NS = 0, 77 M_REG_S = 1, 78 M_REG_NUM_BANKS = 2, 79 }; 80 81 /* ARM-specific interrupt pending bits. */ 82 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 83 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 84 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 85 86 /* The usual mapping for an AArch64 system register to its AArch32 87 * counterpart is for the 32 bit world to have access to the lower 88 * half only (with writes leaving the upper half untouched). It's 89 * therefore useful to be able to pass TCG the offset of the least 90 * significant half of a uint64_t struct member. 91 */ 92 #ifdef HOST_WORDS_BIGENDIAN 93 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 94 #define offsetofhigh32(S, M) offsetof(S, M) 95 #else 96 #define offsetoflow32(S, M) offsetof(S, M) 97 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 98 #endif 99 100 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 101 #define ARM_CPU_IRQ 0 102 #define ARM_CPU_FIQ 1 103 #define ARM_CPU_VIRQ 2 104 #define ARM_CPU_VFIQ 3 105 106 /* ARM-specific extra insn start words: 107 * 1: Conditional execution bits 108 * 2: Partial exception syndrome for data aborts 109 */ 110 #define TARGET_INSN_START_EXTRA_WORDS 2 111 112 /* The 2nd extra word holding syndrome info for data aborts does not use 113 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 114 * help the sleb128 encoder do a better job. 115 * When restoring the CPU state, we shift it back up. 116 */ 117 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 118 #define ARM_INSN_START_WORD2_SHIFT 14 119 120 /* We currently assume float and double are IEEE single and double 121 precision respectively. 122 Doing runtime conversions is tricky because VFP registers may contain 123 integer values (eg. as the result of a FTOSI instruction). 124 s<2n> maps to the least significant half of d<n> 125 s<2n+1> maps to the most significant half of d<n> 126 */ 127 128 /** 129 * DynamicGDBXMLInfo: 130 * @desc: Contains the XML descriptions. 131 * @num: Number of the registers in this XML seen by GDB. 132 * @data: A union with data specific to the set of registers 133 * @cpregs_keys: Array that contains the corresponding Key of 134 * a given cpreg with the same order of the cpreg 135 * in the XML description. 136 */ 137 typedef struct DynamicGDBXMLInfo { 138 char *desc; 139 int num; 140 union { 141 struct { 142 uint32_t *keys; 143 } cpregs; 144 } data; 145 } DynamicGDBXMLInfo; 146 147 /* CPU state for each instance of a generic timer (in cp15 c14) */ 148 typedef struct ARMGenericTimer { 149 uint64_t cval; /* Timer CompareValue register */ 150 uint64_t ctl; /* Timer Control register */ 151 } ARMGenericTimer; 152 153 #define GTIMER_PHYS 0 154 #define GTIMER_VIRT 1 155 #define GTIMER_HYP 2 156 #define GTIMER_SEC 3 157 #define GTIMER_HYPVIRT 4 158 #define NUM_GTIMERS 5 159 160 typedef struct { 161 uint64_t raw_tcr; 162 uint32_t mask; 163 uint32_t base_mask; 164 } TCR; 165 166 /* Define a maximum sized vector register. 167 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 168 * For 64-bit, this is a 2048-bit SVE register. 169 * 170 * Note that the mapping between S, D, and Q views of the register bank 171 * differs between AArch64 and AArch32. 172 * In AArch32: 173 * Qn = regs[n].d[1]:regs[n].d[0] 174 * Dn = regs[n / 2].d[n & 1] 175 * Sn = regs[n / 4].d[n % 4 / 2], 176 * bits 31..0 for even n, and bits 63..32 for odd n 177 * (and regs[16] to regs[31] are inaccessible) 178 * In AArch64: 179 * Zn = regs[n].d[*] 180 * Qn = regs[n].d[1]:regs[n].d[0] 181 * Dn = regs[n].d[0] 182 * Sn = regs[n].d[0] bits 31..0 183 * Hn = regs[n].d[0] bits 15..0 184 * 185 * This corresponds to the architecturally defined mapping between 186 * the two execution states, and means we do not need to explicitly 187 * map these registers when changing states. 188 * 189 * Align the data for use with TCG host vector operations. 190 */ 191 192 #ifdef TARGET_AARCH64 193 # define ARM_MAX_VQ 16 194 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 195 #else 196 # define ARM_MAX_VQ 1 197 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 198 #endif 199 200 typedef struct ARMVectorReg { 201 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 202 } ARMVectorReg; 203 204 #ifdef TARGET_AARCH64 205 /* In AArch32 mode, predicate registers do not exist at all. */ 206 typedef struct ARMPredicateReg { 207 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 208 } ARMPredicateReg; 209 210 /* In AArch32 mode, PAC keys do not exist at all. */ 211 typedef struct ARMPACKey { 212 uint64_t lo, hi; 213 } ARMPACKey; 214 #endif 215 216 217 typedef struct CPUARMState { 218 /* Regs for current mode. */ 219 uint32_t regs[16]; 220 221 /* 32/64 switch only happens when taking and returning from 222 * exceptions so the overlap semantics are taken care of then 223 * instead of having a complicated union. 224 */ 225 /* Regs for A64 mode. */ 226 uint64_t xregs[32]; 227 uint64_t pc; 228 /* PSTATE isn't an architectural register for ARMv8. However, it is 229 * convenient for us to assemble the underlying state into a 32 bit format 230 * identical to the architectural format used for the SPSR. (This is also 231 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 232 * 'pstate' register are.) Of the PSTATE bits: 233 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 234 * semantics as for AArch32, as described in the comments on each field) 235 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 236 * DAIF (exception masks) are kept in env->daif 237 * BTYPE is kept in env->btype 238 * all other bits are stored in their correct places in env->pstate 239 */ 240 uint32_t pstate; 241 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 242 243 /* Cached TBFLAGS state. See below for which bits are included. */ 244 uint32_t hflags; 245 246 /* Frequently accessed CPSR bits are stored separately for efficiency. 247 This contains all the other bits. Use cpsr_{read,write} to access 248 the whole CPSR. */ 249 uint32_t uncached_cpsr; 250 uint32_t spsr; 251 252 /* Banked registers. */ 253 uint64_t banked_spsr[8]; 254 uint32_t banked_r13[8]; 255 uint32_t banked_r14[8]; 256 257 /* These hold r8-r12. */ 258 uint32_t usr_regs[5]; 259 uint32_t fiq_regs[5]; 260 261 /* cpsr flag cache for faster execution */ 262 uint32_t CF; /* 0 or 1 */ 263 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 264 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 265 uint32_t ZF; /* Z set if zero. */ 266 uint32_t QF; /* 0 or 1 */ 267 uint32_t GE; /* cpsr[19:16] */ 268 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 269 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 270 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 271 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 272 273 uint64_t elr_el[4]; /* AArch64 exception link regs */ 274 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 275 276 /* System control coprocessor (cp15) */ 277 struct { 278 uint32_t c0_cpuid; 279 union { /* Cache size selection */ 280 struct { 281 uint64_t _unused_csselr0; 282 uint64_t csselr_ns; 283 uint64_t _unused_csselr1; 284 uint64_t csselr_s; 285 }; 286 uint64_t csselr_el[4]; 287 }; 288 union { /* System control register. */ 289 struct { 290 uint64_t _unused_sctlr; 291 uint64_t sctlr_ns; 292 uint64_t hsctlr; 293 uint64_t sctlr_s; 294 }; 295 uint64_t sctlr_el[4]; 296 }; 297 uint64_t cpacr_el1; /* Architectural feature access control register */ 298 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 299 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 300 uint64_t sder; /* Secure debug enable register. */ 301 uint32_t nsacr; /* Non-secure access control register. */ 302 union { /* MMU translation table base 0. */ 303 struct { 304 uint64_t _unused_ttbr0_0; 305 uint64_t ttbr0_ns; 306 uint64_t _unused_ttbr0_1; 307 uint64_t ttbr0_s; 308 }; 309 uint64_t ttbr0_el[4]; 310 }; 311 union { /* MMU translation table base 1. */ 312 struct { 313 uint64_t _unused_ttbr1_0; 314 uint64_t ttbr1_ns; 315 uint64_t _unused_ttbr1_1; 316 uint64_t ttbr1_s; 317 }; 318 uint64_t ttbr1_el[4]; 319 }; 320 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 321 /* MMU translation table base control. */ 322 TCR tcr_el[4]; 323 TCR vtcr_el2; /* Virtualization Translation Control. */ 324 uint32_t c2_data; /* MPU data cacheable bits. */ 325 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 326 union { /* MMU domain access control register 327 * MPU write buffer control. 328 */ 329 struct { 330 uint64_t dacr_ns; 331 uint64_t dacr_s; 332 }; 333 struct { 334 uint64_t dacr32_el2; 335 }; 336 }; 337 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 338 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 339 uint64_t hcr_el2; /* Hypervisor configuration register */ 340 uint64_t scr_el3; /* Secure configuration register. */ 341 union { /* Fault status registers. */ 342 struct { 343 uint64_t ifsr_ns; 344 uint64_t ifsr_s; 345 }; 346 struct { 347 uint64_t ifsr32_el2; 348 }; 349 }; 350 union { 351 struct { 352 uint64_t _unused_dfsr; 353 uint64_t dfsr_ns; 354 uint64_t hsr; 355 uint64_t dfsr_s; 356 }; 357 uint64_t esr_el[4]; 358 }; 359 uint32_t c6_region[8]; /* MPU base/size registers. */ 360 union { /* Fault address registers. */ 361 struct { 362 uint64_t _unused_far0; 363 #ifdef HOST_WORDS_BIGENDIAN 364 uint32_t ifar_ns; 365 uint32_t dfar_ns; 366 uint32_t ifar_s; 367 uint32_t dfar_s; 368 #else 369 uint32_t dfar_ns; 370 uint32_t ifar_ns; 371 uint32_t dfar_s; 372 uint32_t ifar_s; 373 #endif 374 uint64_t _unused_far3; 375 }; 376 uint64_t far_el[4]; 377 }; 378 uint64_t hpfar_el2; 379 uint64_t hstr_el2; 380 union { /* Translation result. */ 381 struct { 382 uint64_t _unused_par_0; 383 uint64_t par_ns; 384 uint64_t _unused_par_1; 385 uint64_t par_s; 386 }; 387 uint64_t par_el[4]; 388 }; 389 390 uint32_t c9_insn; /* Cache lockdown registers. */ 391 uint32_t c9_data; 392 uint64_t c9_pmcr; /* performance monitor control register */ 393 uint64_t c9_pmcnten; /* perf monitor counter enables */ 394 uint64_t c9_pmovsr; /* perf monitor overflow status */ 395 uint64_t c9_pmuserenr; /* perf monitor user enable */ 396 uint64_t c9_pmselr; /* perf monitor counter selection register */ 397 uint64_t c9_pminten; /* perf monitor interrupt enables */ 398 union { /* Memory attribute redirection */ 399 struct { 400 #ifdef HOST_WORDS_BIGENDIAN 401 uint64_t _unused_mair_0; 402 uint32_t mair1_ns; 403 uint32_t mair0_ns; 404 uint64_t _unused_mair_1; 405 uint32_t mair1_s; 406 uint32_t mair0_s; 407 #else 408 uint64_t _unused_mair_0; 409 uint32_t mair0_ns; 410 uint32_t mair1_ns; 411 uint64_t _unused_mair_1; 412 uint32_t mair0_s; 413 uint32_t mair1_s; 414 #endif 415 }; 416 uint64_t mair_el[4]; 417 }; 418 union { /* vector base address register */ 419 struct { 420 uint64_t _unused_vbar; 421 uint64_t vbar_ns; 422 uint64_t hvbar; 423 uint64_t vbar_s; 424 }; 425 uint64_t vbar_el[4]; 426 }; 427 uint32_t mvbar; /* (monitor) vector base address register */ 428 struct { /* FCSE PID. */ 429 uint32_t fcseidr_ns; 430 uint32_t fcseidr_s; 431 }; 432 union { /* Context ID. */ 433 struct { 434 uint64_t _unused_contextidr_0; 435 uint64_t contextidr_ns; 436 uint64_t _unused_contextidr_1; 437 uint64_t contextidr_s; 438 }; 439 uint64_t contextidr_el[4]; 440 }; 441 union { /* User RW Thread register. */ 442 struct { 443 uint64_t tpidrurw_ns; 444 uint64_t tpidrprw_ns; 445 uint64_t htpidr; 446 uint64_t _tpidr_el3; 447 }; 448 uint64_t tpidr_el[4]; 449 }; 450 /* The secure banks of these registers don't map anywhere */ 451 uint64_t tpidrurw_s; 452 uint64_t tpidrprw_s; 453 uint64_t tpidruro_s; 454 455 union { /* User RO Thread register. */ 456 uint64_t tpidruro_ns; 457 uint64_t tpidrro_el[1]; 458 }; 459 uint64_t c14_cntfrq; /* Counter Frequency register */ 460 uint64_t c14_cntkctl; /* Timer Control register */ 461 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 462 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 463 ARMGenericTimer c14_timer[NUM_GTIMERS]; 464 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 465 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 466 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 467 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 468 uint32_t c15_threadid; /* TI debugger thread-ID. */ 469 uint32_t c15_config_base_address; /* SCU base address. */ 470 uint32_t c15_diagnostic; /* diagnostic register */ 471 uint32_t c15_power_diagnostic; 472 uint32_t c15_power_control; /* power control */ 473 uint64_t dbgbvr[16]; /* breakpoint value registers */ 474 uint64_t dbgbcr[16]; /* breakpoint control registers */ 475 uint64_t dbgwvr[16]; /* watchpoint value registers */ 476 uint64_t dbgwcr[16]; /* watchpoint control registers */ 477 uint64_t mdscr_el1; 478 uint64_t oslsr_el1; /* OS Lock Status */ 479 uint64_t mdcr_el2; 480 uint64_t mdcr_el3; 481 /* Stores the architectural value of the counter *the last time it was 482 * updated* by pmccntr_op_start. Accesses should always be surrounded 483 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 484 * architecturally-correct value is being read/set. 485 */ 486 uint64_t c15_ccnt; 487 /* Stores the delta between the architectural value and the underlying 488 * cycle count during normal operation. It is used to update c15_ccnt 489 * to be the correct architectural value before accesses. During 490 * accesses, c15_ccnt_delta contains the underlying count being used 491 * for the access, after which it reverts to the delta value in 492 * pmccntr_op_finish. 493 */ 494 uint64_t c15_ccnt_delta; 495 uint64_t c14_pmevcntr[31]; 496 uint64_t c14_pmevcntr_delta[31]; 497 uint64_t c14_pmevtyper[31]; 498 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 499 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 500 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 501 } cp15; 502 503 struct { 504 /* M profile has up to 4 stack pointers: 505 * a Main Stack Pointer and a Process Stack Pointer for each 506 * of the Secure and Non-Secure states. (If the CPU doesn't support 507 * the security extension then it has only two SPs.) 508 * In QEMU we always store the currently active SP in regs[13], 509 * and the non-active SP for the current security state in 510 * v7m.other_sp. The stack pointers for the inactive security state 511 * are stored in other_ss_msp and other_ss_psp. 512 * switch_v7m_security_state() is responsible for rearranging them 513 * when we change security state. 514 */ 515 uint32_t other_sp; 516 uint32_t other_ss_msp; 517 uint32_t other_ss_psp; 518 uint32_t vecbase[M_REG_NUM_BANKS]; 519 uint32_t basepri[M_REG_NUM_BANKS]; 520 uint32_t control[M_REG_NUM_BANKS]; 521 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 522 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 523 uint32_t hfsr; /* HardFault Status */ 524 uint32_t dfsr; /* Debug Fault Status Register */ 525 uint32_t sfsr; /* Secure Fault Status Register */ 526 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 527 uint32_t bfar; /* BusFault Address */ 528 uint32_t sfar; /* Secure Fault Address Register */ 529 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 530 int exception; 531 uint32_t primask[M_REG_NUM_BANKS]; 532 uint32_t faultmask[M_REG_NUM_BANKS]; 533 uint32_t aircr; /* only holds r/w state if security extn implemented */ 534 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 535 uint32_t csselr[M_REG_NUM_BANKS]; 536 uint32_t scr[M_REG_NUM_BANKS]; 537 uint32_t msplim[M_REG_NUM_BANKS]; 538 uint32_t psplim[M_REG_NUM_BANKS]; 539 uint32_t fpcar[M_REG_NUM_BANKS]; 540 uint32_t fpccr[M_REG_NUM_BANKS]; 541 uint32_t fpdscr[M_REG_NUM_BANKS]; 542 uint32_t cpacr[M_REG_NUM_BANKS]; 543 uint32_t nsacr; 544 } v7m; 545 546 /* Information associated with an exception about to be taken: 547 * code which raises an exception must set cs->exception_index and 548 * the relevant parts of this structure; the cpu_do_interrupt function 549 * will then set the guest-visible registers as part of the exception 550 * entry process. 551 */ 552 struct { 553 uint32_t syndrome; /* AArch64 format syndrome register */ 554 uint32_t fsr; /* AArch32 format fault status register info */ 555 uint64_t vaddress; /* virtual addr associated with exception, if any */ 556 uint32_t target_el; /* EL the exception should be targeted for */ 557 /* If we implement EL2 we will also need to store information 558 * about the intermediate physical address for stage 2 faults. 559 */ 560 } exception; 561 562 /* Information associated with an SError */ 563 struct { 564 uint8_t pending; 565 uint8_t has_esr; 566 uint64_t esr; 567 } serror; 568 569 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 570 uint32_t irq_line_state; 571 572 /* Thumb-2 EE state. */ 573 uint32_t teecr; 574 uint32_t teehbr; 575 576 /* VFP coprocessor state. */ 577 struct { 578 ARMVectorReg zregs[32]; 579 580 #ifdef TARGET_AARCH64 581 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 582 #define FFR_PRED_NUM 16 583 ARMPredicateReg pregs[17]; 584 /* Scratch space for aa64 sve predicate temporary. */ 585 ARMPredicateReg preg_tmp; 586 #endif 587 588 /* We store these fpcsr fields separately for convenience. */ 589 uint32_t qc[4] QEMU_ALIGNED(16); 590 int vec_len; 591 int vec_stride; 592 593 uint32_t xregs[16]; 594 595 /* Scratch space for aa32 neon expansion. */ 596 uint32_t scratch[8]; 597 598 /* There are a number of distinct float control structures: 599 * 600 * fp_status: is the "normal" fp status. 601 * fp_status_fp16: used for half-precision calculations 602 * standard_fp_status : the ARM "Standard FPSCR Value" 603 * 604 * Half-precision operations are governed by a separate 605 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 606 * status structure to control this. 607 * 608 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 609 * round-to-nearest and is used by any operations (generally 610 * Neon) which the architecture defines as controlled by the 611 * standard FPSCR value rather than the FPSCR. 612 * 613 * To avoid having to transfer exception bits around, we simply 614 * say that the FPSCR cumulative exception flags are the logical 615 * OR of the flags in the three fp statuses. This relies on the 616 * only thing which needs to read the exception flags being 617 * an explicit FPSCR read. 618 */ 619 float_status fp_status; 620 float_status fp_status_f16; 621 float_status standard_fp_status; 622 623 /* ZCR_EL[1-3] */ 624 uint64_t zcr_el[4]; 625 } vfp; 626 uint64_t exclusive_addr; 627 uint64_t exclusive_val; 628 uint64_t exclusive_high; 629 630 /* iwMMXt coprocessor state. */ 631 struct { 632 uint64_t regs[16]; 633 uint64_t val; 634 635 uint32_t cregs[16]; 636 } iwmmxt; 637 638 #ifdef TARGET_AARCH64 639 struct { 640 ARMPACKey apia; 641 ARMPACKey apib; 642 ARMPACKey apda; 643 ARMPACKey apdb; 644 ARMPACKey apga; 645 } keys; 646 #endif 647 648 #if defined(CONFIG_USER_ONLY) 649 /* For usermode syscall translation. */ 650 int eabi; 651 #endif 652 653 struct CPUBreakpoint *cpu_breakpoint[16]; 654 struct CPUWatchpoint *cpu_watchpoint[16]; 655 656 /* Fields up to this point are cleared by a CPU reset */ 657 struct {} end_reset_fields; 658 659 /* Fields after this point are preserved across CPU reset. */ 660 661 /* Internal CPU feature flags. */ 662 uint64_t features; 663 664 /* PMSAv7 MPU */ 665 struct { 666 uint32_t *drbar; 667 uint32_t *drsr; 668 uint32_t *dracr; 669 uint32_t rnr[M_REG_NUM_BANKS]; 670 } pmsav7; 671 672 /* PMSAv8 MPU */ 673 struct { 674 /* The PMSAv8 implementation also shares some PMSAv7 config 675 * and state: 676 * pmsav7.rnr (region number register) 677 * pmsav7_dregion (number of configured regions) 678 */ 679 uint32_t *rbar[M_REG_NUM_BANKS]; 680 uint32_t *rlar[M_REG_NUM_BANKS]; 681 uint32_t mair0[M_REG_NUM_BANKS]; 682 uint32_t mair1[M_REG_NUM_BANKS]; 683 } pmsav8; 684 685 /* v8M SAU */ 686 struct { 687 uint32_t *rbar; 688 uint32_t *rlar; 689 uint32_t rnr; 690 uint32_t ctrl; 691 } sau; 692 693 void *nvic; 694 const struct arm_boot_info *boot_info; 695 /* Store GICv3CPUState to access from this struct */ 696 void *gicv3state; 697 } CPUARMState; 698 699 /** 700 * ARMELChangeHookFn: 701 * type of a function which can be registered via arm_register_el_change_hook() 702 * to get callbacks when the CPU changes its exception level or mode. 703 */ 704 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 705 typedef struct ARMELChangeHook ARMELChangeHook; 706 struct ARMELChangeHook { 707 ARMELChangeHookFn *hook; 708 void *opaque; 709 QLIST_ENTRY(ARMELChangeHook) node; 710 }; 711 712 /* These values map onto the return values for 713 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 714 typedef enum ARMPSCIState { 715 PSCI_ON = 0, 716 PSCI_OFF = 1, 717 PSCI_ON_PENDING = 2 718 } ARMPSCIState; 719 720 typedef struct ARMISARegisters ARMISARegisters; 721 722 /** 723 * ARMCPU: 724 * @env: #CPUARMState 725 * 726 * An ARM CPU core. 727 */ 728 struct ARMCPU { 729 /*< private >*/ 730 CPUState parent_obj; 731 /*< public >*/ 732 733 CPUNegativeOffsetState neg; 734 CPUARMState env; 735 736 /* Coprocessor information */ 737 GHashTable *cp_regs; 738 /* For marshalling (mostly coprocessor) register state between the 739 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 740 * we use these arrays. 741 */ 742 /* List of register indexes managed via these arrays; (full KVM style 743 * 64 bit indexes, not CPRegInfo 32 bit indexes) 744 */ 745 uint64_t *cpreg_indexes; 746 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 747 uint64_t *cpreg_values; 748 /* Length of the indexes, values, reset_values arrays */ 749 int32_t cpreg_array_len; 750 /* These are used only for migration: incoming data arrives in 751 * these fields and is sanity checked in post_load before copying 752 * to the working data structures above. 753 */ 754 uint64_t *cpreg_vmstate_indexes; 755 uint64_t *cpreg_vmstate_values; 756 int32_t cpreg_vmstate_array_len; 757 758 DynamicGDBXMLInfo dyn_sysreg_xml; 759 DynamicGDBXMLInfo dyn_svereg_xml; 760 761 /* Timers used by the generic (architected) timer */ 762 QEMUTimer *gt_timer[NUM_GTIMERS]; 763 /* 764 * Timer used by the PMU. Its state is restored after migration by 765 * pmu_op_finish() - it does not need other handling during migration 766 */ 767 QEMUTimer *pmu_timer; 768 /* GPIO outputs for generic timer */ 769 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 770 /* GPIO output for GICv3 maintenance interrupt signal */ 771 qemu_irq gicv3_maintenance_interrupt; 772 /* GPIO output for the PMU interrupt */ 773 qemu_irq pmu_interrupt; 774 775 /* MemoryRegion to use for secure physical accesses */ 776 MemoryRegion *secure_memory; 777 778 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 779 Object *idau; 780 781 /* 'compatible' string for this CPU for Linux device trees */ 782 const char *dtb_compatible; 783 784 /* PSCI version for this CPU 785 * Bits[31:16] = Major Version 786 * Bits[15:0] = Minor Version 787 */ 788 uint32_t psci_version; 789 790 /* Should CPU start in PSCI powered-off state? */ 791 bool start_powered_off; 792 793 /* Current power state, access guarded by BQL */ 794 ARMPSCIState power_state; 795 796 /* CPU has virtualization extension */ 797 bool has_el2; 798 /* CPU has security extension */ 799 bool has_el3; 800 /* CPU has PMU (Performance Monitor Unit) */ 801 bool has_pmu; 802 /* CPU has VFP */ 803 bool has_vfp; 804 /* CPU has Neon */ 805 bool has_neon; 806 /* CPU has M-profile DSP extension */ 807 bool has_dsp; 808 809 /* CPU has memory protection unit */ 810 bool has_mpu; 811 /* PMSAv7 MPU number of supported regions */ 812 uint32_t pmsav7_dregion; 813 /* v8M SAU number of supported regions */ 814 uint32_t sau_sregion; 815 816 /* PSCI conduit used to invoke PSCI methods 817 * 0 - disabled, 1 - smc, 2 - hvc 818 */ 819 uint32_t psci_conduit; 820 821 /* For v8M, initial value of the Secure VTOR */ 822 uint32_t init_svtor; 823 824 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 825 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 826 */ 827 uint32_t kvm_target; 828 829 /* KVM init features for this CPU */ 830 uint32_t kvm_init_features[7]; 831 832 /* KVM CPU state */ 833 834 /* KVM virtual time adjustment */ 835 bool kvm_adjvtime; 836 bool kvm_vtime_dirty; 837 uint64_t kvm_vtime; 838 839 /* Uniprocessor system with MP extensions */ 840 bool mp_is_up; 841 842 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 843 * and the probe failed (so we need to report the error in realize) 844 */ 845 bool host_cpu_probe_failed; 846 847 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 848 * register. 849 */ 850 int32_t core_count; 851 852 /* The instance init functions for implementation-specific subclasses 853 * set these fields to specify the implementation-dependent values of 854 * various constant registers and reset values of non-constant 855 * registers. 856 * Some of these might become QOM properties eventually. 857 * Field names match the official register names as defined in the 858 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 859 * is used for reset values of non-constant registers; no reset_ 860 * prefix means a constant register. 861 * Some of these registers are split out into a substructure that 862 * is shared with the translators to control the ISA. 863 * 864 * Note that if you add an ID register to the ARMISARegisters struct 865 * you need to also update the 32-bit and 64-bit versions of the 866 * kvm_arm_get_host_cpu_features() function to correctly populate the 867 * field by reading the value from the KVM vCPU. 868 */ 869 struct ARMISARegisters { 870 uint32_t id_isar0; 871 uint32_t id_isar1; 872 uint32_t id_isar2; 873 uint32_t id_isar3; 874 uint32_t id_isar4; 875 uint32_t id_isar5; 876 uint32_t id_isar6; 877 uint32_t id_mmfr0; 878 uint32_t id_mmfr1; 879 uint32_t id_mmfr2; 880 uint32_t id_mmfr3; 881 uint32_t id_mmfr4; 882 uint32_t mvfr0; 883 uint32_t mvfr1; 884 uint32_t mvfr2; 885 uint32_t id_dfr0; 886 uint32_t dbgdidr; 887 uint64_t id_aa64isar0; 888 uint64_t id_aa64isar1; 889 uint64_t id_aa64pfr0; 890 uint64_t id_aa64pfr1; 891 uint64_t id_aa64mmfr0; 892 uint64_t id_aa64mmfr1; 893 uint64_t id_aa64mmfr2; 894 uint64_t id_aa64dfr0; 895 uint64_t id_aa64dfr1; 896 } isar; 897 uint64_t midr; 898 uint32_t revidr; 899 uint32_t reset_fpsid; 900 uint32_t ctr; 901 uint32_t reset_sctlr; 902 uint32_t id_pfr0; 903 uint32_t id_pfr1; 904 uint64_t pmceid0; 905 uint64_t pmceid1; 906 uint32_t id_afr0; 907 uint64_t id_aa64afr0; 908 uint64_t id_aa64afr1; 909 uint32_t clidr; 910 uint64_t mp_affinity; /* MP ID without feature bits */ 911 /* The elements of this array are the CCSIDR values for each cache, 912 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 913 */ 914 uint64_t ccsidr[16]; 915 uint64_t reset_cbar; 916 uint32_t reset_auxcr; 917 bool reset_hivecs; 918 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 919 uint32_t dcz_blocksize; 920 uint64_t rvbar; 921 922 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 923 int gic_num_lrs; /* number of list registers */ 924 int gic_vpribits; /* number of virtual priority bits */ 925 int gic_vprebits; /* number of virtual preemption bits */ 926 927 /* Whether the cfgend input is high (i.e. this CPU should reset into 928 * big-endian mode). This setting isn't used directly: instead it modifies 929 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 930 * architecture version. 931 */ 932 bool cfgend; 933 934 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 935 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 936 937 int32_t node_id; /* NUMA node this CPU belongs to */ 938 939 /* Used to synchronize KVM and QEMU in-kernel device levels */ 940 uint8_t device_irq_level; 941 942 /* Used to set the maximum vector length the cpu will support. */ 943 uint32_t sve_max_vq; 944 945 /* 946 * In sve_vq_map each set bit is a supported vector length of 947 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 948 * length in quadwords. 949 * 950 * While processing properties during initialization, corresponding 951 * sve_vq_init bits are set for bits in sve_vq_map that have been 952 * set by properties. 953 */ 954 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 955 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 956 957 /* Generic timer counter frequency, in Hz */ 958 uint64_t gt_cntfrq_hz; 959 }; 960 961 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 962 963 void arm_cpu_post_init(Object *obj); 964 965 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 966 967 #ifndef CONFIG_USER_ONLY 968 extern const VMStateDescription vmstate_arm_cpu; 969 #endif 970 971 void arm_cpu_do_interrupt(CPUState *cpu); 972 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 973 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 974 975 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 976 MemTxAttrs *attrs); 977 978 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 979 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 980 981 /* 982 * Helpers to dynamically generates XML descriptions of the sysregs 983 * and SVE registers. Returns the number of registers in each set. 984 */ 985 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 986 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 987 988 /* Returns the dynamically generated XML for the gdb stub. 989 * Returns a pointer to the XML contents for the specified XML file or NULL 990 * if the XML name doesn't match the predefined one. 991 */ 992 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 993 994 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 995 int cpuid, void *opaque); 996 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 997 int cpuid, void *opaque); 998 999 #ifdef TARGET_AARCH64 1000 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1001 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1002 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1003 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1004 int new_el, bool el0_a64); 1005 void aarch64_add_sve_properties(Object *obj); 1006 1007 /* 1008 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1009 * The byte at offset i from the start of the in-memory representation contains 1010 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1011 * lowest offsets are stored in the lowest memory addresses, then that nearly 1012 * matches QEMU's representation, which is to use an array of host-endian 1013 * uint64_t's, where the lower offsets are at the lower indices. To complete 1014 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1015 */ 1016 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1017 { 1018 #ifdef HOST_WORDS_BIGENDIAN 1019 int i; 1020 1021 for (i = 0; i < nr; ++i) { 1022 dst[i] = bswap64(src[i]); 1023 } 1024 1025 return dst; 1026 #else 1027 return src; 1028 #endif 1029 } 1030 1031 #else 1032 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1033 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1034 int n, bool a) 1035 { } 1036 static inline void aarch64_add_sve_properties(Object *obj) { } 1037 #endif 1038 1039 #if !defined(CONFIG_TCG) 1040 static inline target_ulong do_arm_semihosting(CPUARMState *env) 1041 { 1042 g_assert_not_reached(); 1043 } 1044 #else 1045 target_ulong do_arm_semihosting(CPUARMState *env); 1046 #endif 1047 void aarch64_sync_32_to_64(CPUARMState *env); 1048 void aarch64_sync_64_to_32(CPUARMState *env); 1049 1050 int fp_exception_el(CPUARMState *env, int cur_el); 1051 int sve_exception_el(CPUARMState *env, int cur_el); 1052 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1053 1054 static inline bool is_a64(CPUARMState *env) 1055 { 1056 return env->aarch64; 1057 } 1058 1059 /* you can call this signal handler from your SIGBUS and SIGSEGV 1060 signal handlers to inform the virtual CPU of exceptions. non zero 1061 is returned if the signal was handled by the virtual CPU. */ 1062 int cpu_arm_signal_handler(int host_signum, void *pinfo, 1063 void *puc); 1064 1065 /** 1066 * pmu_op_start/finish 1067 * @env: CPUARMState 1068 * 1069 * Convert all PMU counters between their delta form (the typical mode when 1070 * they are enabled) and the guest-visible values. These two calls must 1071 * surround any action which might affect the counters. 1072 */ 1073 void pmu_op_start(CPUARMState *env); 1074 void pmu_op_finish(CPUARMState *env); 1075 1076 /* 1077 * Called when a PMU counter is due to overflow 1078 */ 1079 void arm_pmu_timer_cb(void *opaque); 1080 1081 /** 1082 * Functions to register as EL change hooks for PMU mode filtering 1083 */ 1084 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1085 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1086 1087 /* 1088 * pmu_init 1089 * @cpu: ARMCPU 1090 * 1091 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1092 * for the current configuration 1093 */ 1094 void pmu_init(ARMCPU *cpu); 1095 1096 /* SCTLR bit meanings. Several bits have been reused in newer 1097 * versions of the architecture; in that case we define constants 1098 * for both old and new bit meanings. Code which tests against those 1099 * bits should probably check or otherwise arrange that the CPU 1100 * is the architectural version it expects. 1101 */ 1102 #define SCTLR_M (1U << 0) 1103 #define SCTLR_A (1U << 1) 1104 #define SCTLR_C (1U << 2) 1105 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1106 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1107 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1108 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1109 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1110 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1111 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1112 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1113 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1114 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1115 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1116 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1117 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1118 #define SCTLR_SED (1U << 8) /* v8 onward */ 1119 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1120 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1121 #define SCTLR_F (1U << 10) /* up to v6 */ 1122 #define SCTLR_SW (1U << 10) /* v7 */ 1123 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1124 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1125 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1126 #define SCTLR_I (1U << 12) 1127 #define SCTLR_V (1U << 13) /* AArch32 only */ 1128 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1129 #define SCTLR_RR (1U << 14) /* up to v7 */ 1130 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1131 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1132 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1133 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1134 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1135 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1136 #define SCTLR_BR (1U << 17) /* PMSA only */ 1137 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1138 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1139 #define SCTLR_WXN (1U << 19) 1140 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1141 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1142 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1143 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1144 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1145 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1146 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1147 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1148 #define SCTLR_VE (1U << 24) /* up to v7 */ 1149 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1150 #define SCTLR_EE (1U << 25) 1151 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1152 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1153 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1154 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1155 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1156 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1157 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1158 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1159 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1160 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1161 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1162 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1163 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1164 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1165 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1166 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1167 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1168 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1169 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1170 1171 #define CPTR_TCPAC (1U << 31) 1172 #define CPTR_TTA (1U << 20) 1173 #define CPTR_TFP (1U << 10) 1174 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1175 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1176 1177 #define MDCR_EPMAD (1U << 21) 1178 #define MDCR_EDAD (1U << 20) 1179 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1180 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1181 #define MDCR_SDD (1U << 16) 1182 #define MDCR_SPD (3U << 14) 1183 #define MDCR_TDRA (1U << 11) 1184 #define MDCR_TDOSA (1U << 10) 1185 #define MDCR_TDA (1U << 9) 1186 #define MDCR_TDE (1U << 8) 1187 #define MDCR_HPME (1U << 7) 1188 #define MDCR_TPM (1U << 6) 1189 #define MDCR_TPMCR (1U << 5) 1190 #define MDCR_HPMN (0x1fU) 1191 1192 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1193 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1194 1195 #define CPSR_M (0x1fU) 1196 #define CPSR_T (1U << 5) 1197 #define CPSR_F (1U << 6) 1198 #define CPSR_I (1U << 7) 1199 #define CPSR_A (1U << 8) 1200 #define CPSR_E (1U << 9) 1201 #define CPSR_IT_2_7 (0xfc00U) 1202 #define CPSR_GE (0xfU << 16) 1203 #define CPSR_IL (1U << 20) 1204 #define CPSR_PAN (1U << 22) 1205 #define CPSR_J (1U << 24) 1206 #define CPSR_IT_0_1 (3U << 25) 1207 #define CPSR_Q (1U << 27) 1208 #define CPSR_V (1U << 28) 1209 #define CPSR_C (1U << 29) 1210 #define CPSR_Z (1U << 30) 1211 #define CPSR_N (1U << 31) 1212 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1213 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1214 1215 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1216 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1217 | CPSR_NZCV) 1218 /* Bits writable in user mode. */ 1219 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1220 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1221 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1222 1223 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1224 #define XPSR_EXCP 0x1ffU 1225 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1226 #define XPSR_IT_2_7 CPSR_IT_2_7 1227 #define XPSR_GE CPSR_GE 1228 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1229 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1230 #define XPSR_IT_0_1 CPSR_IT_0_1 1231 #define XPSR_Q CPSR_Q 1232 #define XPSR_V CPSR_V 1233 #define XPSR_C CPSR_C 1234 #define XPSR_Z CPSR_Z 1235 #define XPSR_N CPSR_N 1236 #define XPSR_NZCV CPSR_NZCV 1237 #define XPSR_IT CPSR_IT 1238 1239 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1240 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1241 #define TTBCR_PD0 (1U << 4) 1242 #define TTBCR_PD1 (1U << 5) 1243 #define TTBCR_EPD0 (1U << 7) 1244 #define TTBCR_IRGN0 (3U << 8) 1245 #define TTBCR_ORGN0 (3U << 10) 1246 #define TTBCR_SH0 (3U << 12) 1247 #define TTBCR_T1SZ (3U << 16) 1248 #define TTBCR_A1 (1U << 22) 1249 #define TTBCR_EPD1 (1U << 23) 1250 #define TTBCR_IRGN1 (3U << 24) 1251 #define TTBCR_ORGN1 (3U << 26) 1252 #define TTBCR_SH1 (1U << 28) 1253 #define TTBCR_EAE (1U << 31) 1254 1255 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1256 * Only these are valid when in AArch64 mode; in 1257 * AArch32 mode SPSRs are basically CPSR-format. 1258 */ 1259 #define PSTATE_SP (1U) 1260 #define PSTATE_M (0xFU) 1261 #define PSTATE_nRW (1U << 4) 1262 #define PSTATE_F (1U << 6) 1263 #define PSTATE_I (1U << 7) 1264 #define PSTATE_A (1U << 8) 1265 #define PSTATE_D (1U << 9) 1266 #define PSTATE_BTYPE (3U << 10) 1267 #define PSTATE_IL (1U << 20) 1268 #define PSTATE_SS (1U << 21) 1269 #define PSTATE_PAN (1U << 22) 1270 #define PSTATE_UAO (1U << 23) 1271 #define PSTATE_V (1U << 28) 1272 #define PSTATE_C (1U << 29) 1273 #define PSTATE_Z (1U << 30) 1274 #define PSTATE_N (1U << 31) 1275 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1276 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1277 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1278 /* Mode values for AArch64 */ 1279 #define PSTATE_MODE_EL3h 13 1280 #define PSTATE_MODE_EL3t 12 1281 #define PSTATE_MODE_EL2h 9 1282 #define PSTATE_MODE_EL2t 8 1283 #define PSTATE_MODE_EL1h 5 1284 #define PSTATE_MODE_EL1t 4 1285 #define PSTATE_MODE_EL0t 0 1286 1287 /* Write a new value to v7m.exception, thus transitioning into or out 1288 * of Handler mode; this may result in a change of active stack pointer. 1289 */ 1290 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1291 1292 /* Map EL and handler into a PSTATE_MODE. */ 1293 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1294 { 1295 return (el << 2) | handler; 1296 } 1297 1298 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1299 * interprocessing, so we don't attempt to sync with the cpsr state used by 1300 * the 32 bit decoder. 1301 */ 1302 static inline uint32_t pstate_read(CPUARMState *env) 1303 { 1304 int ZF; 1305 1306 ZF = (env->ZF == 0); 1307 return (env->NF & 0x80000000) | (ZF << 30) 1308 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1309 | env->pstate | env->daif | (env->btype << 10); 1310 } 1311 1312 static inline void pstate_write(CPUARMState *env, uint32_t val) 1313 { 1314 env->ZF = (~val) & PSTATE_Z; 1315 env->NF = val; 1316 env->CF = (val >> 29) & 1; 1317 env->VF = (val << 3) & 0x80000000; 1318 env->daif = val & PSTATE_DAIF; 1319 env->btype = (val >> 10) & 3; 1320 env->pstate = val & ~CACHED_PSTATE_BITS; 1321 } 1322 1323 /* Return the current CPSR value. */ 1324 uint32_t cpsr_read(CPUARMState *env); 1325 1326 typedef enum CPSRWriteType { 1327 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1328 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1329 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1330 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1331 } CPSRWriteType; 1332 1333 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1334 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1335 CPSRWriteType write_type); 1336 1337 /* Return the current xPSR value. */ 1338 static inline uint32_t xpsr_read(CPUARMState *env) 1339 { 1340 int ZF; 1341 ZF = (env->ZF == 0); 1342 return (env->NF & 0x80000000) | (ZF << 30) 1343 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1344 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1345 | ((env->condexec_bits & 0xfc) << 8) 1346 | (env->GE << 16) 1347 | env->v7m.exception; 1348 } 1349 1350 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1351 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1352 { 1353 if (mask & XPSR_NZCV) { 1354 env->ZF = (~val) & XPSR_Z; 1355 env->NF = val; 1356 env->CF = (val >> 29) & 1; 1357 env->VF = (val << 3) & 0x80000000; 1358 } 1359 if (mask & XPSR_Q) { 1360 env->QF = ((val & XPSR_Q) != 0); 1361 } 1362 if (mask & XPSR_GE) { 1363 env->GE = (val & XPSR_GE) >> 16; 1364 } 1365 #ifndef CONFIG_USER_ONLY 1366 if (mask & XPSR_T) { 1367 env->thumb = ((val & XPSR_T) != 0); 1368 } 1369 if (mask & XPSR_IT_0_1) { 1370 env->condexec_bits &= ~3; 1371 env->condexec_bits |= (val >> 25) & 3; 1372 } 1373 if (mask & XPSR_IT_2_7) { 1374 env->condexec_bits &= 3; 1375 env->condexec_bits |= (val >> 8) & 0xfc; 1376 } 1377 if (mask & XPSR_EXCP) { 1378 /* Note that this only happens on exception exit */ 1379 write_v7m_exception(env, val & XPSR_EXCP); 1380 } 1381 #endif 1382 } 1383 1384 #define HCR_VM (1ULL << 0) 1385 #define HCR_SWIO (1ULL << 1) 1386 #define HCR_PTW (1ULL << 2) 1387 #define HCR_FMO (1ULL << 3) 1388 #define HCR_IMO (1ULL << 4) 1389 #define HCR_AMO (1ULL << 5) 1390 #define HCR_VF (1ULL << 6) 1391 #define HCR_VI (1ULL << 7) 1392 #define HCR_VSE (1ULL << 8) 1393 #define HCR_FB (1ULL << 9) 1394 #define HCR_BSU_MASK (3ULL << 10) 1395 #define HCR_DC (1ULL << 12) 1396 #define HCR_TWI (1ULL << 13) 1397 #define HCR_TWE (1ULL << 14) 1398 #define HCR_TID0 (1ULL << 15) 1399 #define HCR_TID1 (1ULL << 16) 1400 #define HCR_TID2 (1ULL << 17) 1401 #define HCR_TID3 (1ULL << 18) 1402 #define HCR_TSC (1ULL << 19) 1403 #define HCR_TIDCP (1ULL << 20) 1404 #define HCR_TACR (1ULL << 21) 1405 #define HCR_TSW (1ULL << 22) 1406 #define HCR_TPCP (1ULL << 23) 1407 #define HCR_TPU (1ULL << 24) 1408 #define HCR_TTLB (1ULL << 25) 1409 #define HCR_TVM (1ULL << 26) 1410 #define HCR_TGE (1ULL << 27) 1411 #define HCR_TDZ (1ULL << 28) 1412 #define HCR_HCD (1ULL << 29) 1413 #define HCR_TRVM (1ULL << 30) 1414 #define HCR_RW (1ULL << 31) 1415 #define HCR_CD (1ULL << 32) 1416 #define HCR_ID (1ULL << 33) 1417 #define HCR_E2H (1ULL << 34) 1418 #define HCR_TLOR (1ULL << 35) 1419 #define HCR_TERR (1ULL << 36) 1420 #define HCR_TEA (1ULL << 37) 1421 #define HCR_MIOCNCE (1ULL << 38) 1422 /* RES0 bit 39 */ 1423 #define HCR_APK (1ULL << 40) 1424 #define HCR_API (1ULL << 41) 1425 #define HCR_NV (1ULL << 42) 1426 #define HCR_NV1 (1ULL << 43) 1427 #define HCR_AT (1ULL << 44) 1428 #define HCR_NV2 (1ULL << 45) 1429 #define HCR_FWB (1ULL << 46) 1430 #define HCR_FIEN (1ULL << 47) 1431 /* RES0 bit 48 */ 1432 #define HCR_TID4 (1ULL << 49) 1433 #define HCR_TICAB (1ULL << 50) 1434 #define HCR_AMVOFFEN (1ULL << 51) 1435 #define HCR_TOCU (1ULL << 52) 1436 #define HCR_ENSCXT (1ULL << 53) 1437 #define HCR_TTLBIS (1ULL << 54) 1438 #define HCR_TTLBOS (1ULL << 55) 1439 #define HCR_ATA (1ULL << 56) 1440 #define HCR_DCT (1ULL << 57) 1441 #define HCR_TID5 (1ULL << 58) 1442 #define HCR_TWEDEN (1ULL << 59) 1443 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1444 1445 #define SCR_NS (1U << 0) 1446 #define SCR_IRQ (1U << 1) 1447 #define SCR_FIQ (1U << 2) 1448 #define SCR_EA (1U << 3) 1449 #define SCR_FW (1U << 4) 1450 #define SCR_AW (1U << 5) 1451 #define SCR_NET (1U << 6) 1452 #define SCR_SMD (1U << 7) 1453 #define SCR_HCE (1U << 8) 1454 #define SCR_SIF (1U << 9) 1455 #define SCR_RW (1U << 10) 1456 #define SCR_ST (1U << 11) 1457 #define SCR_TWI (1U << 12) 1458 #define SCR_TWE (1U << 13) 1459 #define SCR_TLOR (1U << 14) 1460 #define SCR_TERR (1U << 15) 1461 #define SCR_APK (1U << 16) 1462 #define SCR_API (1U << 17) 1463 #define SCR_EEL2 (1U << 18) 1464 #define SCR_EASE (1U << 19) 1465 #define SCR_NMEA (1U << 20) 1466 #define SCR_FIEN (1U << 21) 1467 #define SCR_ENSCXT (1U << 25) 1468 #define SCR_ATA (1U << 26) 1469 1470 /* Return the current FPSCR value. */ 1471 uint32_t vfp_get_fpscr(CPUARMState *env); 1472 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1473 1474 /* FPCR, Floating Point Control Register 1475 * FPSR, Floating Poiht Status Register 1476 * 1477 * For A64 the FPSCR is split into two logically distinct registers, 1478 * FPCR and FPSR. However since they still use non-overlapping bits 1479 * we store the underlying state in fpscr and just mask on read/write. 1480 */ 1481 #define FPSR_MASK 0xf800009f 1482 #define FPCR_MASK 0x07ff9f00 1483 1484 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1485 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1486 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1487 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1488 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1489 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1490 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1491 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1492 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1493 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1494 1495 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1496 { 1497 return vfp_get_fpscr(env) & FPSR_MASK; 1498 } 1499 1500 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1501 { 1502 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1503 vfp_set_fpscr(env, new_fpscr); 1504 } 1505 1506 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1507 { 1508 return vfp_get_fpscr(env) & FPCR_MASK; 1509 } 1510 1511 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1512 { 1513 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1514 vfp_set_fpscr(env, new_fpscr); 1515 } 1516 1517 enum arm_cpu_mode { 1518 ARM_CPU_MODE_USR = 0x10, 1519 ARM_CPU_MODE_FIQ = 0x11, 1520 ARM_CPU_MODE_IRQ = 0x12, 1521 ARM_CPU_MODE_SVC = 0x13, 1522 ARM_CPU_MODE_MON = 0x16, 1523 ARM_CPU_MODE_ABT = 0x17, 1524 ARM_CPU_MODE_HYP = 0x1a, 1525 ARM_CPU_MODE_UND = 0x1b, 1526 ARM_CPU_MODE_SYS = 0x1f 1527 }; 1528 1529 /* VFP system registers. */ 1530 #define ARM_VFP_FPSID 0 1531 #define ARM_VFP_FPSCR 1 1532 #define ARM_VFP_MVFR2 5 1533 #define ARM_VFP_MVFR1 6 1534 #define ARM_VFP_MVFR0 7 1535 #define ARM_VFP_FPEXC 8 1536 #define ARM_VFP_FPINST 9 1537 #define ARM_VFP_FPINST2 10 1538 1539 /* iwMMXt coprocessor control registers. */ 1540 #define ARM_IWMMXT_wCID 0 1541 #define ARM_IWMMXT_wCon 1 1542 #define ARM_IWMMXT_wCSSF 2 1543 #define ARM_IWMMXT_wCASF 3 1544 #define ARM_IWMMXT_wCGR0 8 1545 #define ARM_IWMMXT_wCGR1 9 1546 #define ARM_IWMMXT_wCGR2 10 1547 #define ARM_IWMMXT_wCGR3 11 1548 1549 /* V7M CCR bits */ 1550 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1551 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1552 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1553 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1554 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1555 FIELD(V7M_CCR, STKALIGN, 9, 1) 1556 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1557 FIELD(V7M_CCR, DC, 16, 1) 1558 FIELD(V7M_CCR, IC, 17, 1) 1559 FIELD(V7M_CCR, BP, 18, 1) 1560 1561 /* V7M SCR bits */ 1562 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1563 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1564 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1565 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1566 1567 /* V7M AIRCR bits */ 1568 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1569 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1570 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1571 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1572 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1573 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1574 FIELD(V7M_AIRCR, PRIS, 14, 1) 1575 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1576 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1577 1578 /* V7M CFSR bits for MMFSR */ 1579 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1580 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1581 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1582 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1583 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1584 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1585 1586 /* V7M CFSR bits for BFSR */ 1587 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1588 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1589 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1590 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1591 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1592 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1593 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1594 1595 /* V7M CFSR bits for UFSR */ 1596 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1597 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1598 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1599 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1600 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1601 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1602 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1603 1604 /* V7M CFSR bit masks covering all of the subregister bits */ 1605 FIELD(V7M_CFSR, MMFSR, 0, 8) 1606 FIELD(V7M_CFSR, BFSR, 8, 8) 1607 FIELD(V7M_CFSR, UFSR, 16, 16) 1608 1609 /* V7M HFSR bits */ 1610 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1611 FIELD(V7M_HFSR, FORCED, 30, 1) 1612 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1613 1614 /* V7M DFSR bits */ 1615 FIELD(V7M_DFSR, HALTED, 0, 1) 1616 FIELD(V7M_DFSR, BKPT, 1, 1) 1617 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1618 FIELD(V7M_DFSR, VCATCH, 3, 1) 1619 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1620 1621 /* V7M SFSR bits */ 1622 FIELD(V7M_SFSR, INVEP, 0, 1) 1623 FIELD(V7M_SFSR, INVIS, 1, 1) 1624 FIELD(V7M_SFSR, INVER, 2, 1) 1625 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1626 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1627 FIELD(V7M_SFSR, LSPERR, 5, 1) 1628 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1629 FIELD(V7M_SFSR, LSERR, 7, 1) 1630 1631 /* v7M MPU_CTRL bits */ 1632 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1633 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1634 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1635 1636 /* v7M CLIDR bits */ 1637 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1638 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1639 FIELD(V7M_CLIDR, LOC, 24, 3) 1640 FIELD(V7M_CLIDR, LOUU, 27, 3) 1641 FIELD(V7M_CLIDR, ICB, 30, 2) 1642 1643 FIELD(V7M_CSSELR, IND, 0, 1) 1644 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1645 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1646 * define a mask for this and check that it doesn't permit running off 1647 * the end of the array. 1648 */ 1649 FIELD(V7M_CSSELR, INDEX, 0, 4) 1650 1651 /* v7M FPCCR bits */ 1652 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1653 FIELD(V7M_FPCCR, USER, 1, 1) 1654 FIELD(V7M_FPCCR, S, 2, 1) 1655 FIELD(V7M_FPCCR, THREAD, 3, 1) 1656 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1657 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1658 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1659 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1660 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1661 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1662 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1663 FIELD(V7M_FPCCR, RES0, 11, 15) 1664 FIELD(V7M_FPCCR, TS, 26, 1) 1665 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1666 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1667 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1668 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1669 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1670 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1671 #define R_V7M_FPCCR_BANKED_MASK \ 1672 (R_V7M_FPCCR_LSPACT_MASK | \ 1673 R_V7M_FPCCR_USER_MASK | \ 1674 R_V7M_FPCCR_THREAD_MASK | \ 1675 R_V7M_FPCCR_MMRDY_MASK | \ 1676 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1677 R_V7M_FPCCR_UFRDY_MASK | \ 1678 R_V7M_FPCCR_ASPEN_MASK) 1679 1680 /* 1681 * System register ID fields. 1682 */ 1683 FIELD(MIDR_EL1, REVISION, 0, 4) 1684 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1685 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1686 FIELD(MIDR_EL1, VARIANT, 20, 4) 1687 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1688 1689 FIELD(ID_ISAR0, SWAP, 0, 4) 1690 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1691 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1692 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1693 FIELD(ID_ISAR0, COPROC, 16, 4) 1694 FIELD(ID_ISAR0, DEBUG, 20, 4) 1695 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1696 1697 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1698 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1699 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1700 FIELD(ID_ISAR1, EXTEND, 12, 4) 1701 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1702 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1703 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1704 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1705 1706 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1707 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1708 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1709 FIELD(ID_ISAR2, MULT, 12, 4) 1710 FIELD(ID_ISAR2, MULTS, 16, 4) 1711 FIELD(ID_ISAR2, MULTU, 20, 4) 1712 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1713 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1714 1715 FIELD(ID_ISAR3, SATURATE, 0, 4) 1716 FIELD(ID_ISAR3, SIMD, 4, 4) 1717 FIELD(ID_ISAR3, SVC, 8, 4) 1718 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1719 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1720 FIELD(ID_ISAR3, T32COPY, 20, 4) 1721 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1722 FIELD(ID_ISAR3, T32EE, 28, 4) 1723 1724 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1725 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1726 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1727 FIELD(ID_ISAR4, SMC, 12, 4) 1728 FIELD(ID_ISAR4, BARRIER, 16, 4) 1729 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1730 FIELD(ID_ISAR4, PSR_M, 24, 4) 1731 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1732 1733 FIELD(ID_ISAR5, SEVL, 0, 4) 1734 FIELD(ID_ISAR5, AES, 4, 4) 1735 FIELD(ID_ISAR5, SHA1, 8, 4) 1736 FIELD(ID_ISAR5, SHA2, 12, 4) 1737 FIELD(ID_ISAR5, CRC32, 16, 4) 1738 FIELD(ID_ISAR5, RDM, 24, 4) 1739 FIELD(ID_ISAR5, VCMA, 28, 4) 1740 1741 FIELD(ID_ISAR6, JSCVT, 0, 4) 1742 FIELD(ID_ISAR6, DP, 4, 4) 1743 FIELD(ID_ISAR6, FHM, 8, 4) 1744 FIELD(ID_ISAR6, SB, 12, 4) 1745 FIELD(ID_ISAR6, SPECRES, 16, 4) 1746 1747 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 1748 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 1749 FIELD(ID_MMFR3, BPMAINT, 8, 4) 1750 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 1751 FIELD(ID_MMFR3, PAN, 16, 4) 1752 FIELD(ID_MMFR3, COHWALK, 20, 4) 1753 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 1754 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 1755 1756 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1757 FIELD(ID_MMFR4, AC2, 4, 4) 1758 FIELD(ID_MMFR4, XNX, 8, 4) 1759 FIELD(ID_MMFR4, CNP, 12, 4) 1760 FIELD(ID_MMFR4, HPDS, 16, 4) 1761 FIELD(ID_MMFR4, LSM, 20, 4) 1762 FIELD(ID_MMFR4, CCIDX, 24, 4) 1763 FIELD(ID_MMFR4, EVT, 28, 4) 1764 1765 FIELD(ID_AA64ISAR0, AES, 4, 4) 1766 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1767 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1768 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1769 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1770 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1771 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1772 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1773 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1774 FIELD(ID_AA64ISAR0, DP, 44, 4) 1775 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1776 FIELD(ID_AA64ISAR0, TS, 52, 4) 1777 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1778 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1779 1780 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1781 FIELD(ID_AA64ISAR1, APA, 4, 4) 1782 FIELD(ID_AA64ISAR1, API, 8, 4) 1783 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1784 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1785 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1786 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1787 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1788 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1789 FIELD(ID_AA64ISAR1, SB, 36, 4) 1790 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1791 1792 FIELD(ID_AA64PFR0, EL0, 0, 4) 1793 FIELD(ID_AA64PFR0, EL1, 4, 4) 1794 FIELD(ID_AA64PFR0, EL2, 8, 4) 1795 FIELD(ID_AA64PFR0, EL3, 12, 4) 1796 FIELD(ID_AA64PFR0, FP, 16, 4) 1797 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1798 FIELD(ID_AA64PFR0, GIC, 24, 4) 1799 FIELD(ID_AA64PFR0, RAS, 28, 4) 1800 FIELD(ID_AA64PFR0, SVE, 32, 4) 1801 1802 FIELD(ID_AA64PFR1, BT, 0, 4) 1803 FIELD(ID_AA64PFR1, SBSS, 4, 4) 1804 FIELD(ID_AA64PFR1, MTE, 8, 4) 1805 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1806 1807 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1808 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1809 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1810 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1811 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1812 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1813 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1814 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1815 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1816 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1817 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1818 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1819 1820 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1821 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1822 FIELD(ID_AA64MMFR1, VH, 8, 4) 1823 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1824 FIELD(ID_AA64MMFR1, LO, 16, 4) 1825 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1826 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1827 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1828 1829 FIELD(ID_AA64MMFR2, CNP, 0, 4) 1830 FIELD(ID_AA64MMFR2, UAO, 4, 4) 1831 FIELD(ID_AA64MMFR2, LSM, 8, 4) 1832 FIELD(ID_AA64MMFR2, IESB, 12, 4) 1833 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 1834 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 1835 FIELD(ID_AA64MMFR2, NV, 24, 4) 1836 FIELD(ID_AA64MMFR2, ST, 28, 4) 1837 FIELD(ID_AA64MMFR2, AT, 32, 4) 1838 FIELD(ID_AA64MMFR2, IDS, 36, 4) 1839 FIELD(ID_AA64MMFR2, FWB, 40, 4) 1840 FIELD(ID_AA64MMFR2, TTL, 48, 4) 1841 FIELD(ID_AA64MMFR2, BBM, 52, 4) 1842 FIELD(ID_AA64MMFR2, EVT, 56, 4) 1843 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 1844 1845 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 1846 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 1847 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 1848 FIELD(ID_AA64DFR0, BRPS, 12, 4) 1849 FIELD(ID_AA64DFR0, WRPS, 20, 4) 1850 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 1851 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 1852 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 1853 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 1854 1855 FIELD(ID_DFR0, COPDBG, 0, 4) 1856 FIELD(ID_DFR0, COPSDBG, 4, 4) 1857 FIELD(ID_DFR0, MMAPDBG, 8, 4) 1858 FIELD(ID_DFR0, COPTRC, 12, 4) 1859 FIELD(ID_DFR0, MMAPTRC, 16, 4) 1860 FIELD(ID_DFR0, MPROFDBG, 20, 4) 1861 FIELD(ID_DFR0, PERFMON, 24, 4) 1862 FIELD(ID_DFR0, TRACEFILT, 28, 4) 1863 1864 FIELD(DBGDIDR, SE_IMP, 12, 1) 1865 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 1866 FIELD(DBGDIDR, VERSION, 16, 4) 1867 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 1868 FIELD(DBGDIDR, BRPS, 24, 4) 1869 FIELD(DBGDIDR, WRPS, 28, 4) 1870 1871 FIELD(MVFR0, SIMDREG, 0, 4) 1872 FIELD(MVFR0, FPSP, 4, 4) 1873 FIELD(MVFR0, FPDP, 8, 4) 1874 FIELD(MVFR0, FPTRAP, 12, 4) 1875 FIELD(MVFR0, FPDIVIDE, 16, 4) 1876 FIELD(MVFR0, FPSQRT, 20, 4) 1877 FIELD(MVFR0, FPSHVEC, 24, 4) 1878 FIELD(MVFR0, FPROUND, 28, 4) 1879 1880 FIELD(MVFR1, FPFTZ, 0, 4) 1881 FIELD(MVFR1, FPDNAN, 4, 4) 1882 FIELD(MVFR1, SIMDLS, 8, 4) 1883 FIELD(MVFR1, SIMDINT, 12, 4) 1884 FIELD(MVFR1, SIMDSP, 16, 4) 1885 FIELD(MVFR1, SIMDHP, 20, 4) 1886 FIELD(MVFR1, FPHP, 24, 4) 1887 FIELD(MVFR1, SIMDFMAC, 28, 4) 1888 1889 FIELD(MVFR2, SIMDMISC, 0, 4) 1890 FIELD(MVFR2, FPMISC, 4, 4) 1891 1892 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1893 1894 /* If adding a feature bit which corresponds to a Linux ELF 1895 * HWCAP bit, remember to update the feature-bit-to-hwcap 1896 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1897 */ 1898 enum arm_features { 1899 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1900 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1901 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1902 ARM_FEATURE_V6, 1903 ARM_FEATURE_V6K, 1904 ARM_FEATURE_V7, 1905 ARM_FEATURE_THUMB2, 1906 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1907 ARM_FEATURE_NEON, 1908 ARM_FEATURE_M, /* Microcontroller profile. */ 1909 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1910 ARM_FEATURE_THUMB2EE, 1911 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1912 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1913 ARM_FEATURE_V4T, 1914 ARM_FEATURE_V5, 1915 ARM_FEATURE_STRONGARM, 1916 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1917 ARM_FEATURE_GENERIC_TIMER, 1918 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1919 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1920 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1921 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1922 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1923 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1924 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1925 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1926 ARM_FEATURE_V8, 1927 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1928 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1929 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1930 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1931 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1932 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1933 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1934 ARM_FEATURE_PMU, /* has PMU support */ 1935 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1936 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1937 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1938 }; 1939 1940 static inline int arm_feature(CPUARMState *env, int feature) 1941 { 1942 return (env->features & (1ULL << feature)) != 0; 1943 } 1944 1945 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 1946 1947 #if !defined(CONFIG_USER_ONLY) 1948 /* Return true if exception levels below EL3 are in secure state, 1949 * or would be following an exception return to that level. 1950 * Unlike arm_is_secure() (which is always a question about the 1951 * _current_ state of the CPU) this doesn't care about the current 1952 * EL or mode. 1953 */ 1954 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1955 { 1956 if (arm_feature(env, ARM_FEATURE_EL3)) { 1957 return !(env->cp15.scr_el3 & SCR_NS); 1958 } else { 1959 /* If EL3 is not supported then the secure state is implementation 1960 * defined, in which case QEMU defaults to non-secure. 1961 */ 1962 return false; 1963 } 1964 } 1965 1966 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1967 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1968 { 1969 if (arm_feature(env, ARM_FEATURE_EL3)) { 1970 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1971 /* CPU currently in AArch64 state and EL3 */ 1972 return true; 1973 } else if (!is_a64(env) && 1974 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1975 /* CPU currently in AArch32 state and monitor mode */ 1976 return true; 1977 } 1978 } 1979 return false; 1980 } 1981 1982 /* Return true if the processor is in secure state */ 1983 static inline bool arm_is_secure(CPUARMState *env) 1984 { 1985 if (arm_is_el3_or_mon(env)) { 1986 return true; 1987 } 1988 return arm_is_secure_below_el3(env); 1989 } 1990 1991 #else 1992 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1993 { 1994 return false; 1995 } 1996 1997 static inline bool arm_is_secure(CPUARMState *env) 1998 { 1999 return false; 2000 } 2001 #endif 2002 2003 /** 2004 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2005 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2006 * "for all purposes other than a direct read or write access of HCR_EL2." 2007 * Not included here is HCR_RW. 2008 */ 2009 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2010 2011 /* Return true if the specified exception level is running in AArch64 state. */ 2012 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2013 { 2014 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2015 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2016 */ 2017 assert(el >= 1 && el <= 3); 2018 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2019 2020 /* The highest exception level is always at the maximum supported 2021 * register width, and then lower levels have a register width controlled 2022 * by bits in the SCR or HCR registers. 2023 */ 2024 if (el == 3) { 2025 return aa64; 2026 } 2027 2028 if (arm_feature(env, ARM_FEATURE_EL3)) { 2029 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2030 } 2031 2032 if (el == 2) { 2033 return aa64; 2034 } 2035 2036 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 2037 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2038 } 2039 2040 return aa64; 2041 } 2042 2043 /* Function for determing whether guest cp register reads and writes should 2044 * access the secure or non-secure bank of a cp register. When EL3 is 2045 * operating in AArch32 state, the NS-bit determines whether the secure 2046 * instance of a cp register should be used. When EL3 is AArch64 (or if 2047 * it doesn't exist at all) then there is no register banking, and all 2048 * accesses are to the non-secure version. 2049 */ 2050 static inline bool access_secure_reg(CPUARMState *env) 2051 { 2052 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2053 !arm_el_is_aa64(env, 3) && 2054 !(env->cp15.scr_el3 & SCR_NS)); 2055 2056 return ret; 2057 } 2058 2059 /* Macros for accessing a specified CP register bank */ 2060 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2061 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2062 2063 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2064 do { \ 2065 if (_secure) { \ 2066 (_env)->cp15._regname##_s = (_val); \ 2067 } else { \ 2068 (_env)->cp15._regname##_ns = (_val); \ 2069 } \ 2070 } while (0) 2071 2072 /* Macros for automatically accessing a specific CP register bank depending on 2073 * the current secure state of the system. These macros are not intended for 2074 * supporting instruction translation reads/writes as these are dependent 2075 * solely on the SCR.NS bit and not the mode. 2076 */ 2077 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2078 A32_BANKED_REG_GET((_env), _regname, \ 2079 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2080 2081 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2082 A32_BANKED_REG_SET((_env), _regname, \ 2083 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2084 (_val)) 2085 2086 void arm_cpu_list(void); 2087 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2088 uint32_t cur_el, bool secure); 2089 2090 /* Interface between CPU and Interrupt controller. */ 2091 #ifndef CONFIG_USER_ONLY 2092 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2093 #else 2094 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2095 { 2096 return true; 2097 } 2098 #endif 2099 /** 2100 * armv7m_nvic_set_pending: mark the specified exception as pending 2101 * @opaque: the NVIC 2102 * @irq: the exception number to mark pending 2103 * @secure: false for non-banked exceptions or for the nonsecure 2104 * version of a banked exception, true for the secure version of a banked 2105 * exception. 2106 * 2107 * Marks the specified exception as pending. Note that we will assert() 2108 * if @secure is true and @irq does not specify one of the fixed set 2109 * of architecturally banked exceptions. 2110 */ 2111 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2112 /** 2113 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2114 * @opaque: the NVIC 2115 * @irq: the exception number to mark pending 2116 * @secure: false for non-banked exceptions or for the nonsecure 2117 * version of a banked exception, true for the secure version of a banked 2118 * exception. 2119 * 2120 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2121 * exceptions (exceptions generated in the course of trying to take 2122 * a different exception). 2123 */ 2124 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2125 /** 2126 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2127 * @opaque: the NVIC 2128 * @irq: the exception number to mark pending 2129 * @secure: false for non-banked exceptions or for the nonsecure 2130 * version of a banked exception, true for the secure version of a banked 2131 * exception. 2132 * 2133 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2134 * generated in the course of lazy stacking of FP registers. 2135 */ 2136 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2137 /** 2138 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2139 * exception, and whether it targets Secure state 2140 * @opaque: the NVIC 2141 * @pirq: set to pending exception number 2142 * @ptargets_secure: set to whether pending exception targets Secure 2143 * 2144 * This function writes the number of the highest priority pending 2145 * exception (the one which would be made active by 2146 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2147 * to true if the current highest priority pending exception should 2148 * be taken to Secure state, false for NS. 2149 */ 2150 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2151 bool *ptargets_secure); 2152 /** 2153 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2154 * @opaque: the NVIC 2155 * 2156 * Move the current highest priority pending exception from the pending 2157 * state to the active state, and update v7m.exception to indicate that 2158 * it is the exception currently being handled. 2159 */ 2160 void armv7m_nvic_acknowledge_irq(void *opaque); 2161 /** 2162 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2163 * @opaque: the NVIC 2164 * @irq: the exception number to complete 2165 * @secure: true if this exception was secure 2166 * 2167 * Returns: -1 if the irq was not active 2168 * 1 if completing this irq brought us back to base (no active irqs) 2169 * 0 if there is still an irq active after this one was completed 2170 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2171 */ 2172 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2173 /** 2174 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2175 * @opaque: the NVIC 2176 * @irq: the exception number to mark pending 2177 * @secure: false for non-banked exceptions or for the nonsecure 2178 * version of a banked exception, true for the secure version of a banked 2179 * exception. 2180 * 2181 * Return whether an exception is "ready", i.e. whether the exception is 2182 * enabled and is configured at a priority which would allow it to 2183 * interrupt the current execution priority. This controls whether the 2184 * RDY bit for it in the FPCCR is set. 2185 */ 2186 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2187 /** 2188 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2189 * @opaque: the NVIC 2190 * 2191 * Returns: the raw execution priority as defined by the v8M architecture. 2192 * This is the execution priority minus the effects of AIRCR.PRIS, 2193 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2194 * (v8M ARM ARM I_PKLD.) 2195 */ 2196 int armv7m_nvic_raw_execution_priority(void *opaque); 2197 /** 2198 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2199 * priority is negative for the specified security state. 2200 * @opaque: the NVIC 2201 * @secure: the security state to test 2202 * This corresponds to the pseudocode IsReqExecPriNeg(). 2203 */ 2204 #ifndef CONFIG_USER_ONLY 2205 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2206 #else 2207 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2208 { 2209 return false; 2210 } 2211 #endif 2212 2213 /* Interface for defining coprocessor registers. 2214 * Registers are defined in tables of arm_cp_reginfo structs 2215 * which are passed to define_arm_cp_regs(). 2216 */ 2217 2218 /* When looking up a coprocessor register we look for it 2219 * via an integer which encodes all of: 2220 * coprocessor number 2221 * Crn, Crm, opc1, opc2 fields 2222 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2223 * or via MRRC/MCRR?) 2224 * non-secure/secure bank (AArch32 only) 2225 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2226 * (In this case crn and opc2 should be zero.) 2227 * For AArch64, there is no 32/64 bit size distinction; 2228 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2229 * and 4 bit CRn and CRm. The encoding patterns are chosen 2230 * to be easy to convert to and from the KVM encodings, and also 2231 * so that the hashtable can contain both AArch32 and AArch64 2232 * registers (to allow for interprocessing where we might run 2233 * 32 bit code on a 64 bit core). 2234 */ 2235 /* This bit is private to our hashtable cpreg; in KVM register 2236 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2237 * in the upper bits of the 64 bit ID. 2238 */ 2239 #define CP_REG_AA64_SHIFT 28 2240 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2241 2242 /* To enable banking of coprocessor registers depending on ns-bit we 2243 * add a bit to distinguish between secure and non-secure cpregs in the 2244 * hashtable. 2245 */ 2246 #define CP_REG_NS_SHIFT 29 2247 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2248 2249 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2250 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2251 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2252 2253 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2254 (CP_REG_AA64_MASK | \ 2255 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2256 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2257 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2258 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2259 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2260 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2261 2262 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2263 * version used as a key for the coprocessor register hashtable 2264 */ 2265 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2266 { 2267 uint32_t cpregid = kvmid; 2268 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2269 cpregid |= CP_REG_AA64_MASK; 2270 } else { 2271 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2272 cpregid |= (1 << 15); 2273 } 2274 2275 /* KVM is always non-secure so add the NS flag on AArch32 register 2276 * entries. 2277 */ 2278 cpregid |= 1 << CP_REG_NS_SHIFT; 2279 } 2280 return cpregid; 2281 } 2282 2283 /* Convert a truncated 32 bit hashtable key into the full 2284 * 64 bit KVM register ID. 2285 */ 2286 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2287 { 2288 uint64_t kvmid; 2289 2290 if (cpregid & CP_REG_AA64_MASK) { 2291 kvmid = cpregid & ~CP_REG_AA64_MASK; 2292 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2293 } else { 2294 kvmid = cpregid & ~(1 << 15); 2295 if (cpregid & (1 << 15)) { 2296 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2297 } else { 2298 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2299 } 2300 } 2301 return kvmid; 2302 } 2303 2304 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2305 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2306 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2307 * TCG can assume the value to be constant (ie load at translate time) 2308 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2309 * indicates that the TB should not be ended after a write to this register 2310 * (the default is that the TB ends after cp writes). OVERRIDE permits 2311 * a register definition to override a previous definition for the 2312 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2313 * old must have the OVERRIDE bit set. 2314 * ALIAS indicates that this register is an alias view of some underlying 2315 * state which is also visible via another register, and that the other 2316 * register is handling migration and reset; registers marked ALIAS will not be 2317 * migrated but may have their state set by syncing of register state from KVM. 2318 * NO_RAW indicates that this register has no underlying state and does not 2319 * support raw access for state saving/loading; it will not be used for either 2320 * migration or KVM state synchronization. (Typically this is for "registers" 2321 * which are actually used as instructions for cache maintenance and so on.) 2322 * IO indicates that this register does I/O and therefore its accesses 2323 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2324 * registers which implement clocks or timers require this. 2325 * RAISES_EXC is for when the read or write hook might raise an exception; 2326 * the generated code will synchronize the CPU state before calling the hook 2327 * so that it is safe for the hook to call raise_exception(). 2328 * NEWEL is for writes to registers that might change the exception 2329 * level - typically on older ARM chips. For those cases we need to 2330 * re-read the new el when recomputing the translation flags. 2331 */ 2332 #define ARM_CP_SPECIAL 0x0001 2333 #define ARM_CP_CONST 0x0002 2334 #define ARM_CP_64BIT 0x0004 2335 #define ARM_CP_SUPPRESS_TB_END 0x0008 2336 #define ARM_CP_OVERRIDE 0x0010 2337 #define ARM_CP_ALIAS 0x0020 2338 #define ARM_CP_IO 0x0040 2339 #define ARM_CP_NO_RAW 0x0080 2340 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2341 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2342 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2343 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2344 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2345 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2346 #define ARM_CP_FPU 0x1000 2347 #define ARM_CP_SVE 0x2000 2348 #define ARM_CP_NO_GDB 0x4000 2349 #define ARM_CP_RAISES_EXC 0x8000 2350 #define ARM_CP_NEWEL 0x10000 2351 /* Used only as a terminator for ARMCPRegInfo lists */ 2352 #define ARM_CP_SENTINEL 0xfffff 2353 /* Mask of only the flag bits in a type field */ 2354 #define ARM_CP_FLAG_MASK 0x1f0ff 2355 2356 /* Valid values for ARMCPRegInfo state field, indicating which of 2357 * the AArch32 and AArch64 execution states this register is visible in. 2358 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2359 * If the reginfo is declared to be visible in both states then a second 2360 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2361 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2362 * Note that we rely on the values of these enums as we iterate through 2363 * the various states in some places. 2364 */ 2365 enum { 2366 ARM_CP_STATE_AA32 = 0, 2367 ARM_CP_STATE_AA64 = 1, 2368 ARM_CP_STATE_BOTH = 2, 2369 }; 2370 2371 /* ARM CP register secure state flags. These flags identify security state 2372 * attributes for a given CP register entry. 2373 * The existence of both or neither secure and non-secure flags indicates that 2374 * the register has both a secure and non-secure hash entry. A single one of 2375 * these flags causes the register to only be hashed for the specified 2376 * security state. 2377 * Although definitions may have any combination of the S/NS bits, each 2378 * registered entry will only have one to identify whether the entry is secure 2379 * or non-secure. 2380 */ 2381 enum { 2382 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2383 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2384 }; 2385 2386 /* Return true if cptype is a valid type field. This is used to try to 2387 * catch errors where the sentinel has been accidentally left off the end 2388 * of a list of registers. 2389 */ 2390 static inline bool cptype_valid(int cptype) 2391 { 2392 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2393 || ((cptype & ARM_CP_SPECIAL) && 2394 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2395 } 2396 2397 /* Access rights: 2398 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2399 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2400 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2401 * (ie any of the privileged modes in Secure state, or Monitor mode). 2402 * If a register is accessible in one privilege level it's always accessible 2403 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2404 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2405 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2406 * terminology a little and call this PL3. 2407 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2408 * with the ELx exception levels. 2409 * 2410 * If access permissions for a register are more complex than can be 2411 * described with these bits, then use a laxer set of restrictions, and 2412 * do the more restrictive/complex check inside a helper function. 2413 */ 2414 #define PL3_R 0x80 2415 #define PL3_W 0x40 2416 #define PL2_R (0x20 | PL3_R) 2417 #define PL2_W (0x10 | PL3_W) 2418 #define PL1_R (0x08 | PL2_R) 2419 #define PL1_W (0x04 | PL2_W) 2420 #define PL0_R (0x02 | PL1_R) 2421 #define PL0_W (0x01 | PL1_W) 2422 2423 /* 2424 * For user-mode some registers are accessible to EL0 via a kernel 2425 * trap-and-emulate ABI. In this case we define the read permissions 2426 * as actually being PL0_R. However some bits of any given register 2427 * may still be masked. 2428 */ 2429 #ifdef CONFIG_USER_ONLY 2430 #define PL0U_R PL0_R 2431 #else 2432 #define PL0U_R PL1_R 2433 #endif 2434 2435 #define PL3_RW (PL3_R | PL3_W) 2436 #define PL2_RW (PL2_R | PL2_W) 2437 #define PL1_RW (PL1_R | PL1_W) 2438 #define PL0_RW (PL0_R | PL0_W) 2439 2440 /* Return the highest implemented Exception Level */ 2441 static inline int arm_highest_el(CPUARMState *env) 2442 { 2443 if (arm_feature(env, ARM_FEATURE_EL3)) { 2444 return 3; 2445 } 2446 if (arm_feature(env, ARM_FEATURE_EL2)) { 2447 return 2; 2448 } 2449 return 1; 2450 } 2451 2452 /* Return true if a v7M CPU is in Handler mode */ 2453 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2454 { 2455 return env->v7m.exception != 0; 2456 } 2457 2458 /* Return the current Exception Level (as per ARMv8; note that this differs 2459 * from the ARMv7 Privilege Level). 2460 */ 2461 static inline int arm_current_el(CPUARMState *env) 2462 { 2463 if (arm_feature(env, ARM_FEATURE_M)) { 2464 return arm_v7m_is_handler_mode(env) || 2465 !(env->v7m.control[env->v7m.secure] & 1); 2466 } 2467 2468 if (is_a64(env)) { 2469 return extract32(env->pstate, 2, 2); 2470 } 2471 2472 switch (env->uncached_cpsr & 0x1f) { 2473 case ARM_CPU_MODE_USR: 2474 return 0; 2475 case ARM_CPU_MODE_HYP: 2476 return 2; 2477 case ARM_CPU_MODE_MON: 2478 return 3; 2479 default: 2480 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2481 /* If EL3 is 32-bit then all secure privileged modes run in 2482 * EL3 2483 */ 2484 return 3; 2485 } 2486 2487 return 1; 2488 } 2489 } 2490 2491 typedef struct ARMCPRegInfo ARMCPRegInfo; 2492 2493 typedef enum CPAccessResult { 2494 /* Access is permitted */ 2495 CP_ACCESS_OK = 0, 2496 /* Access fails due to a configurable trap or enable which would 2497 * result in a categorized exception syndrome giving information about 2498 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2499 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2500 * PL1 if in EL0, otherwise to the current EL). 2501 */ 2502 CP_ACCESS_TRAP = 1, 2503 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2504 * Note that this is not a catch-all case -- the set of cases which may 2505 * result in this failure is specifically defined by the architecture. 2506 */ 2507 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2508 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2509 CP_ACCESS_TRAP_EL2 = 3, 2510 CP_ACCESS_TRAP_EL3 = 4, 2511 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2512 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2513 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2514 /* Access fails and results in an exception syndrome for an FP access, 2515 * trapped directly to EL2 or EL3 2516 */ 2517 CP_ACCESS_TRAP_FP_EL2 = 7, 2518 CP_ACCESS_TRAP_FP_EL3 = 8, 2519 } CPAccessResult; 2520 2521 /* Access functions for coprocessor registers. These cannot fail and 2522 * may not raise exceptions. 2523 */ 2524 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2525 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2526 uint64_t value); 2527 /* Access permission check functions for coprocessor registers. */ 2528 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2529 const ARMCPRegInfo *opaque, 2530 bool isread); 2531 /* Hook function for register reset */ 2532 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2533 2534 #define CP_ANY 0xff 2535 2536 /* Definition of an ARM coprocessor register */ 2537 struct ARMCPRegInfo { 2538 /* Name of register (useful mainly for debugging, need not be unique) */ 2539 const char *name; 2540 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2541 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2542 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2543 * will be decoded to this register. The register read and write 2544 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2545 * used by the program, so it is possible to register a wildcard and 2546 * then behave differently on read/write if necessary. 2547 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2548 * must both be zero. 2549 * For AArch64-visible registers, opc0 is also used. 2550 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2551 * way to distinguish (for KVM's benefit) guest-visible system registers 2552 * from demuxed ones provided to preserve the "no side effects on 2553 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2554 * visible (to match KVM's encoding); cp==0 will be converted to 2555 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2556 */ 2557 uint8_t cp; 2558 uint8_t crn; 2559 uint8_t crm; 2560 uint8_t opc0; 2561 uint8_t opc1; 2562 uint8_t opc2; 2563 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2564 int state; 2565 /* Register type: ARM_CP_* bits/values */ 2566 int type; 2567 /* Access rights: PL*_[RW] */ 2568 int access; 2569 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2570 int secure; 2571 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2572 * this register was defined: can be used to hand data through to the 2573 * register read/write functions, since they are passed the ARMCPRegInfo*. 2574 */ 2575 void *opaque; 2576 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2577 * fieldoffset is non-zero, the reset value of the register. 2578 */ 2579 uint64_t resetvalue; 2580 /* Offset of the field in CPUARMState for this register. 2581 * 2582 * This is not needed if either: 2583 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2584 * 2. both readfn and writefn are specified 2585 */ 2586 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2587 2588 /* Offsets of the secure and non-secure fields in CPUARMState for the 2589 * register if it is banked. These fields are only used during the static 2590 * registration of a register. During hashing the bank associated 2591 * with a given security state is copied to fieldoffset which is used from 2592 * there on out. 2593 * 2594 * It is expected that register definitions use either fieldoffset or 2595 * bank_fieldoffsets in the definition but not both. It is also expected 2596 * that both bank offsets are set when defining a banked register. This 2597 * use indicates that a register is banked. 2598 */ 2599 ptrdiff_t bank_fieldoffsets[2]; 2600 2601 /* Function for making any access checks for this register in addition to 2602 * those specified by the 'access' permissions bits. If NULL, no extra 2603 * checks required. The access check is performed at runtime, not at 2604 * translate time. 2605 */ 2606 CPAccessFn *accessfn; 2607 /* Function for handling reads of this register. If NULL, then reads 2608 * will be done by loading from the offset into CPUARMState specified 2609 * by fieldoffset. 2610 */ 2611 CPReadFn *readfn; 2612 /* Function for handling writes of this register. If NULL, then writes 2613 * will be done by writing to the offset into CPUARMState specified 2614 * by fieldoffset. 2615 */ 2616 CPWriteFn *writefn; 2617 /* Function for doing a "raw" read; used when we need to copy 2618 * coprocessor state to the kernel for KVM or out for 2619 * migration. This only needs to be provided if there is also a 2620 * readfn and it has side effects (for instance clear-on-read bits). 2621 */ 2622 CPReadFn *raw_readfn; 2623 /* Function for doing a "raw" write; used when we need to copy KVM 2624 * kernel coprocessor state into userspace, or for inbound 2625 * migration. This only needs to be provided if there is also a 2626 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2627 * or similar behaviour. 2628 */ 2629 CPWriteFn *raw_writefn; 2630 /* Function for resetting the register. If NULL, then reset will be done 2631 * by writing resetvalue to the field specified in fieldoffset. If 2632 * fieldoffset is 0 then no reset will be done. 2633 */ 2634 CPResetFn *resetfn; 2635 2636 /* 2637 * "Original" writefn and readfn. 2638 * For ARMv8.1-VHE register aliases, we overwrite the read/write 2639 * accessor functions of various EL1/EL0 to perform the runtime 2640 * check for which sysreg should actually be modified, and then 2641 * forwards the operation. Before overwriting the accessors, 2642 * the original function is copied here, so that accesses that 2643 * really do go to the EL1/EL0 version proceed normally. 2644 * (The corresponding EL2 register is linked via opaque.) 2645 */ 2646 CPReadFn *orig_readfn; 2647 CPWriteFn *orig_writefn; 2648 }; 2649 2650 /* Macros which are lvalues for the field in CPUARMState for the 2651 * ARMCPRegInfo *ri. 2652 */ 2653 #define CPREG_FIELD32(env, ri) \ 2654 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2655 #define CPREG_FIELD64(env, ri) \ 2656 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2657 2658 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2659 2660 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2661 const ARMCPRegInfo *regs, void *opaque); 2662 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2663 const ARMCPRegInfo *regs, void *opaque); 2664 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2665 { 2666 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2667 } 2668 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2669 { 2670 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2671 } 2672 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2673 2674 /* 2675 * Definition of an ARM co-processor register as viewed from 2676 * userspace. This is used for presenting sanitised versions of 2677 * registers to userspace when emulating the Linux AArch64 CPU 2678 * ID/feature ABI (advertised as HWCAP_CPUID). 2679 */ 2680 typedef struct ARMCPRegUserSpaceInfo { 2681 /* Name of register */ 2682 const char *name; 2683 2684 /* Is the name actually a glob pattern */ 2685 bool is_glob; 2686 2687 /* Only some bits are exported to user space */ 2688 uint64_t exported_bits; 2689 2690 /* Fixed bits are applied after the mask */ 2691 uint64_t fixed_bits; 2692 } ARMCPRegUserSpaceInfo; 2693 2694 #define REGUSERINFO_SENTINEL { .name = NULL } 2695 2696 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2697 2698 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2699 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2700 uint64_t value); 2701 /* CPReadFn that can be used for read-as-zero behaviour */ 2702 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2703 2704 /* CPResetFn that does nothing, for use if no reset is required even 2705 * if fieldoffset is non zero. 2706 */ 2707 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2708 2709 /* Return true if this reginfo struct's field in the cpu state struct 2710 * is 64 bits wide. 2711 */ 2712 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2713 { 2714 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2715 } 2716 2717 static inline bool cp_access_ok(int current_el, 2718 const ARMCPRegInfo *ri, int isread) 2719 { 2720 return (ri->access >> ((current_el * 2) + isread)) & 1; 2721 } 2722 2723 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2724 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2725 2726 /** 2727 * write_list_to_cpustate 2728 * @cpu: ARMCPU 2729 * 2730 * For each register listed in the ARMCPU cpreg_indexes list, write 2731 * its value from the cpreg_values list into the ARMCPUState structure. 2732 * This updates TCG's working data structures from KVM data or 2733 * from incoming migration state. 2734 * 2735 * Returns: true if all register values were updated correctly, 2736 * false if some register was unknown or could not be written. 2737 * Note that we do not stop early on failure -- we will attempt 2738 * writing all registers in the list. 2739 */ 2740 bool write_list_to_cpustate(ARMCPU *cpu); 2741 2742 /** 2743 * write_cpustate_to_list: 2744 * @cpu: ARMCPU 2745 * @kvm_sync: true if this is for syncing back to KVM 2746 * 2747 * For each register listed in the ARMCPU cpreg_indexes list, write 2748 * its value from the ARMCPUState structure into the cpreg_values list. 2749 * This is used to copy info from TCG's working data structures into 2750 * KVM or for outbound migration. 2751 * 2752 * @kvm_sync is true if we are doing this in order to sync the 2753 * register state back to KVM. In this case we will only update 2754 * values in the list if the previous list->cpustate sync actually 2755 * successfully wrote the CPU state. Otherwise we will keep the value 2756 * that is in the list. 2757 * 2758 * Returns: true if all register values were read correctly, 2759 * false if some register was unknown or could not be read. 2760 * Note that we do not stop early on failure -- we will attempt 2761 * reading all registers in the list. 2762 */ 2763 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2764 2765 #define ARM_CPUID_TI915T 0x54029152 2766 #define ARM_CPUID_TI925T 0x54029252 2767 2768 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2769 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2770 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2771 2772 #define cpu_signal_handler cpu_arm_signal_handler 2773 #define cpu_list arm_cpu_list 2774 2775 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2776 * 2777 * If EL3 is 64-bit: 2778 * + NonSecure EL1 & 0 stage 1 2779 * + NonSecure EL1 & 0 stage 2 2780 * + NonSecure EL2 2781 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2782 * + Secure EL1 & 0 2783 * + Secure EL3 2784 * If EL3 is 32-bit: 2785 * + NonSecure PL1 & 0 stage 1 2786 * + NonSecure PL1 & 0 stage 2 2787 * + NonSecure PL2 2788 * + Secure PL0 2789 * + Secure PL1 2790 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2791 * 2792 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2793 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2794 * because they may differ in access permissions even if the VA->PA map is 2795 * the same 2796 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2797 * translation, which means that we have one mmu_idx that deals with two 2798 * concatenated translation regimes [this sort of combined s1+2 TLB is 2799 * architecturally permitted] 2800 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2801 * handling via the TLB. The only way to do a stage 1 translation without 2802 * the immediate stage 2 translation is via the ATS or AT system insns, 2803 * which can be slow-pathed and always do a page table walk. 2804 * The only use of stage 2 translations is either as part of an s1+2 2805 * lookup or when loading the descriptors during a stage 1 page table walk, 2806 * and in both those cases we don't use the TLB. 2807 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2808 * translation regimes, because they map reasonably well to each other 2809 * and they can't both be active at the same time. 2810 * 5. we want to be able to use the TLB for accesses done as part of a 2811 * stage1 page table walk, rather than having to walk the stage2 page 2812 * table over and over. 2813 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2814 * Never (PAN) bit within PSTATE. 2815 * 2816 * This gives us the following list of cases: 2817 * 2818 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 2819 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 2820 * NS EL1 EL1&0 stage 1+2 +PAN 2821 * NS EL0 EL2&0 2822 * NS EL2 EL2&0 2823 * NS EL2 EL2&0 +PAN 2824 * NS EL2 (aka NS PL2) 2825 * S EL0 EL1&0 (aka S PL0) 2826 * S EL1 EL1&0 (not used if EL3 is 32 bit) 2827 * S EL1 EL1&0 +PAN 2828 * S EL3 (aka S PL1) 2829 * 2830 * for a total of 11 different mmu_idx. 2831 * 2832 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2833 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2834 * NS EL2 if we ever model a Cortex-R52). 2835 * 2836 * M profile CPUs are rather different as they do not have a true MMU. 2837 * They have the following different MMU indexes: 2838 * User 2839 * Privileged 2840 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2841 * Privileged, execution priority negative (ditto) 2842 * If the CPU supports the v8M Security Extension then there are also: 2843 * Secure User 2844 * Secure Privileged 2845 * Secure User, execution priority negative 2846 * Secure Privileged, execution priority negative 2847 * 2848 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2849 * are not quite the same -- different CPU types (most notably M profile 2850 * vs A/R profile) would like to use MMU indexes with different semantics, 2851 * but since we don't ever need to use all of those in a single CPU we 2852 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2853 * modes + total number of M profile MMU modes". The lower bits of 2854 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2855 * the same for any particular CPU. 2856 * Variables of type ARMMUIdx are always full values, and the core 2857 * index values are in variables of type 'int'. 2858 * 2859 * Our enumeration includes at the end some entries which are not "true" 2860 * mmu_idx values in that they don't have corresponding TLBs and are only 2861 * valid for doing slow path page table walks. 2862 * 2863 * The constant names here are patterned after the general style of the names 2864 * of the AT/ATS operations. 2865 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2866 * For M profile we arrange them to have a bit for priv, a bit for negpri 2867 * and a bit for secure. 2868 */ 2869 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2870 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2871 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2872 2873 /* Meanings of the bits for M profile mmu idx values */ 2874 #define ARM_MMU_IDX_M_PRIV 0x1 2875 #define ARM_MMU_IDX_M_NEGPRI 0x2 2876 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2877 2878 #define ARM_MMU_IDX_TYPE_MASK \ 2879 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2880 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2881 2882 typedef enum ARMMMUIdx { 2883 /* 2884 * A-profile. 2885 */ 2886 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2887 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2888 2889 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2890 ARMMMUIdx_E10_1_PAN = 3 | ARM_MMU_IDX_A, 2891 2892 ARMMMUIdx_E2 = 4 | ARM_MMU_IDX_A, 2893 ARMMMUIdx_E20_2 = 5 | ARM_MMU_IDX_A, 2894 ARMMMUIdx_E20_2_PAN = 6 | ARM_MMU_IDX_A, 2895 2896 ARMMMUIdx_SE10_0 = 7 | ARM_MMU_IDX_A, 2897 ARMMMUIdx_SE10_1 = 8 | ARM_MMU_IDX_A, 2898 ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A, 2899 ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A, 2900 2901 /* 2902 * These are not allocated TLBs and are used only for AT system 2903 * instructions or for the first stage of an S12 page table walk. 2904 */ 2905 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2906 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2907 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2908 /* 2909 * Not allocated a TLB: used only for second stage of an S12 page 2910 * table walk, or for descriptor loads during first stage of an S1 2911 * page table walk. Note that if we ever want to have a TLB for this 2912 * then various TLB flush insns which currently are no-ops or flush 2913 * only stage 1 MMU indexes will need to change to flush stage 2. 2914 */ 2915 ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB, 2916 2917 /* 2918 * M-profile. 2919 */ 2920 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2921 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2922 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2923 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2924 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2925 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2926 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2927 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2928 } ARMMMUIdx; 2929 2930 /* 2931 * Bit macros for the core-mmu-index values for each index, 2932 * for use when calling tlb_flush_by_mmuidx() and friends. 2933 */ 2934 #define TO_CORE_BIT(NAME) \ 2935 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2936 2937 typedef enum ARMMMUIdxBit { 2938 TO_CORE_BIT(E10_0), 2939 TO_CORE_BIT(E20_0), 2940 TO_CORE_BIT(E10_1), 2941 TO_CORE_BIT(E10_1_PAN), 2942 TO_CORE_BIT(E2), 2943 TO_CORE_BIT(E20_2), 2944 TO_CORE_BIT(E20_2_PAN), 2945 TO_CORE_BIT(SE10_0), 2946 TO_CORE_BIT(SE10_1), 2947 TO_CORE_BIT(SE10_1_PAN), 2948 TO_CORE_BIT(SE3), 2949 2950 TO_CORE_BIT(MUser), 2951 TO_CORE_BIT(MPriv), 2952 TO_CORE_BIT(MUserNegPri), 2953 TO_CORE_BIT(MPrivNegPri), 2954 TO_CORE_BIT(MSUser), 2955 TO_CORE_BIT(MSPriv), 2956 TO_CORE_BIT(MSUserNegPri), 2957 TO_CORE_BIT(MSPrivNegPri), 2958 } ARMMMUIdxBit; 2959 2960 #undef TO_CORE_BIT 2961 2962 #define MMU_USER_IDX 0 2963 2964 /* Indexes used when registering address spaces with cpu_address_space_init */ 2965 typedef enum ARMASIdx { 2966 ARMASIdx_NS = 0, 2967 ARMASIdx_S = 1, 2968 } ARMASIdx; 2969 2970 /* Return the Exception Level targeted by debug exceptions. */ 2971 static inline int arm_debug_target_el(CPUARMState *env) 2972 { 2973 bool secure = arm_is_secure(env); 2974 bool route_to_el2 = false; 2975 2976 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2977 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2978 env->cp15.mdcr_el2 & MDCR_TDE; 2979 } 2980 2981 if (route_to_el2) { 2982 return 2; 2983 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2984 !arm_el_is_aa64(env, 3) && secure) { 2985 return 3; 2986 } else { 2987 return 1; 2988 } 2989 } 2990 2991 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2992 { 2993 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2994 * CSSELR is RAZ/WI. 2995 */ 2996 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2997 } 2998 2999 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 3000 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 3001 { 3002 int cur_el = arm_current_el(env); 3003 int debug_el; 3004 3005 if (cur_el == 3) { 3006 return false; 3007 } 3008 3009 /* MDCR_EL3.SDD disables debug events from Secure state */ 3010 if (arm_is_secure_below_el3(env) 3011 && extract32(env->cp15.mdcr_el3, 16, 1)) { 3012 return false; 3013 } 3014 3015 /* 3016 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 3017 * while not masking the (D)ebug bit in DAIF. 3018 */ 3019 debug_el = arm_debug_target_el(env); 3020 3021 if (cur_el == debug_el) { 3022 return extract32(env->cp15.mdscr_el1, 13, 1) 3023 && !(env->daif & PSTATE_D); 3024 } 3025 3026 /* Otherwise the debug target needs to be a higher EL */ 3027 return debug_el > cur_el; 3028 } 3029 3030 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 3031 { 3032 int el = arm_current_el(env); 3033 3034 if (el == 0 && arm_el_is_aa64(env, 1)) { 3035 return aa64_generate_debug_exceptions(env); 3036 } 3037 3038 if (arm_is_secure(env)) { 3039 int spd; 3040 3041 if (el == 0 && (env->cp15.sder & 1)) { 3042 /* SDER.SUIDEN means debug exceptions from Secure EL0 3043 * are always enabled. Otherwise they are controlled by 3044 * SDCR.SPD like those from other Secure ELs. 3045 */ 3046 return true; 3047 } 3048 3049 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3050 switch (spd) { 3051 case 1: 3052 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3053 case 0: 3054 /* For 0b00 we return true if external secure invasive debug 3055 * is enabled. On real hardware this is controlled by external 3056 * signals to the core. QEMU always permits debug, and behaves 3057 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3058 */ 3059 return true; 3060 case 2: 3061 return false; 3062 case 3: 3063 return true; 3064 } 3065 } 3066 3067 return el != 2; 3068 } 3069 3070 /* Return true if debugging exceptions are currently enabled. 3071 * This corresponds to what in ARM ARM pseudocode would be 3072 * if UsingAArch32() then 3073 * return AArch32.GenerateDebugExceptions() 3074 * else 3075 * return AArch64.GenerateDebugExceptions() 3076 * We choose to push the if() down into this function for clarity, 3077 * since the pseudocode has it at all callsites except for the one in 3078 * CheckSoftwareStep(), where it is elided because both branches would 3079 * always return the same value. 3080 */ 3081 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3082 { 3083 if (env->aarch64) { 3084 return aa64_generate_debug_exceptions(env); 3085 } else { 3086 return aa32_generate_debug_exceptions(env); 3087 } 3088 } 3089 3090 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3091 * implicitly means this always returns false in pre-v8 CPUs.) 3092 */ 3093 static inline bool arm_singlestep_active(CPUARMState *env) 3094 { 3095 return extract32(env->cp15.mdscr_el1, 0, 1) 3096 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3097 && arm_generate_debug_exceptions(env); 3098 } 3099 3100 static inline bool arm_sctlr_b(CPUARMState *env) 3101 { 3102 return 3103 /* We need not implement SCTLR.ITD in user-mode emulation, so 3104 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3105 * This lets people run BE32 binaries with "-cpu any". 3106 */ 3107 #ifndef CONFIG_USER_ONLY 3108 !arm_feature(env, ARM_FEATURE_V7) && 3109 #endif 3110 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3111 } 3112 3113 uint64_t arm_sctlr(CPUARMState *env, int el); 3114 3115 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3116 bool sctlr_b) 3117 { 3118 #ifdef CONFIG_USER_ONLY 3119 /* 3120 * In system mode, BE32 is modelled in line with the 3121 * architecture (as word-invariant big-endianness), where loads 3122 * and stores are done little endian but from addresses which 3123 * are adjusted by XORing with the appropriate constant. So the 3124 * endianness to use for the raw data access is not affected by 3125 * SCTLR.B. 3126 * In user mode, however, we model BE32 as byte-invariant 3127 * big-endianness (because user-only code cannot tell the 3128 * difference), and so we need to use a data access endianness 3129 * that depends on SCTLR.B. 3130 */ 3131 if (sctlr_b) { 3132 return true; 3133 } 3134 #endif 3135 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3136 return env->uncached_cpsr & CPSR_E; 3137 } 3138 3139 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3140 { 3141 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3142 } 3143 3144 /* Return true if the processor is in big-endian mode. */ 3145 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3146 { 3147 if (!is_a64(env)) { 3148 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3149 } else { 3150 int cur_el = arm_current_el(env); 3151 uint64_t sctlr = arm_sctlr(env, cur_el); 3152 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3153 } 3154 } 3155 3156 typedef CPUARMState CPUArchState; 3157 typedef ARMCPU ArchCPU; 3158 3159 #include "exec/cpu-all.h" 3160 3161 /* 3162 * Bit usage in the TB flags field: bit 31 indicates whether we are 3163 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 3164 * We put flags which are shared between 32 and 64 bit mode at the top 3165 * of the word, and flags which apply to only one mode at the bottom. 3166 * 3167 * 31 20 18 14 9 0 3168 * +--------------+-----+-----+----------+--------------+ 3169 * | | | TBFLAG_A32 | | 3170 * | | +-----+----------+ TBFLAG_AM32 | 3171 * | TBFLAG_ANY | |TBFLAG_M32| | 3172 * | | +-+----------+--------------| 3173 * | | | TBFLAG_A64 | 3174 * +--------------+---------+---------------------------+ 3175 * 31 20 15 0 3176 * 3177 * Unless otherwise noted, these bits are cached in env->hflags. 3178 */ 3179 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3180 FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) 3181 FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */ 3182 FIELD(TBFLAG_ANY, BE_DATA, 28, 1) 3183 FIELD(TBFLAG_ANY, MMUIDX, 24, 4) 3184 /* Target EL if we take a floating-point-disabled exception */ 3185 FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2) 3186 /* For A-profile only, target EL for debug exceptions. */ 3187 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) 3188 3189 /* 3190 * Bit usage when in AArch32 state, both A- and M-profile. 3191 */ 3192 FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */ 3193 FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */ 3194 3195 /* 3196 * Bit usage when in AArch32 state, for A-profile only. 3197 */ 3198 FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */ 3199 FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ 3200 /* 3201 * We store the bottom two bits of the CPAR as TB flags and handle 3202 * checks on the other bits at runtime. This shares the same bits as 3203 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3204 * Not cached, because VECLEN+VECSTRIDE are not cached. 3205 */ 3206 FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) 3207 FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */ 3208 FIELD(TBFLAG_A32, SCTLR_B, 15, 1) 3209 FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) 3210 /* 3211 * Indicates whether cp register reads and writes by guest code should access 3212 * the secure or nonsecure bank of banked registers; note that this is not 3213 * the same thing as the current security state of the processor! 3214 */ 3215 FIELD(TBFLAG_A32, NS, 17, 1) 3216 3217 /* 3218 * Bit usage when in AArch32 state, for M-profile only. 3219 */ 3220 /* Handler (ie not Thread) mode */ 3221 FIELD(TBFLAG_M32, HANDLER, 9, 1) 3222 /* Whether we should generate stack-limit checks */ 3223 FIELD(TBFLAG_M32, STACKCHECK, 10, 1) 3224 /* Set if FPCCR.LSPACT is set */ 3225 FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */ 3226 /* Set if we must create a new FP context */ 3227 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */ 3228 /* Set if FPCCR.S does not match current security state */ 3229 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */ 3230 3231 /* 3232 * Bit usage when in AArch64 state 3233 */ 3234 FIELD(TBFLAG_A64, TBII, 0, 2) 3235 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3236 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3237 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3238 FIELD(TBFLAG_A64, BT, 9, 1) 3239 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3240 FIELD(TBFLAG_A64, TBID, 12, 2) 3241 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3242 3243 /** 3244 * cpu_mmu_index: 3245 * @env: The cpu environment 3246 * @ifetch: True for code access, false for data access. 3247 * 3248 * Return the core mmu index for the current translation regime. 3249 * This function is used by generic TCG code paths. 3250 */ 3251 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3252 { 3253 return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX); 3254 } 3255 3256 static inline bool bswap_code(bool sctlr_b) 3257 { 3258 #ifdef CONFIG_USER_ONLY 3259 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3260 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3261 * would also end up as a mixed-endian mode with BE code, LE data. 3262 */ 3263 return 3264 #ifdef TARGET_WORDS_BIGENDIAN 3265 1 ^ 3266 #endif 3267 sctlr_b; 3268 #else 3269 /* All code access in ARM is little endian, and there are no loaders 3270 * doing swaps that need to be reversed 3271 */ 3272 return 0; 3273 #endif 3274 } 3275 3276 #ifdef CONFIG_USER_ONLY 3277 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3278 { 3279 return 3280 #ifdef TARGET_WORDS_BIGENDIAN 3281 1 ^ 3282 #endif 3283 arm_cpu_data_is_big_endian(env); 3284 } 3285 #endif 3286 3287 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3288 target_ulong *cs_base, uint32_t *flags); 3289 3290 enum { 3291 QEMU_PSCI_CONDUIT_DISABLED = 0, 3292 QEMU_PSCI_CONDUIT_SMC = 1, 3293 QEMU_PSCI_CONDUIT_HVC = 2, 3294 }; 3295 3296 #ifndef CONFIG_USER_ONLY 3297 /* Return the address space index to use for a memory access */ 3298 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3299 { 3300 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3301 } 3302 3303 /* Return the AddressSpace to use for a memory access 3304 * (which depends on whether the access is S or NS, and whether 3305 * the board gave us a separate AddressSpace for S accesses). 3306 */ 3307 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3308 { 3309 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3310 } 3311 #endif 3312 3313 /** 3314 * arm_register_pre_el_change_hook: 3315 * Register a hook function which will be called immediately before this 3316 * CPU changes exception level or mode. The hook function will be 3317 * passed a pointer to the ARMCPU and the opaque data pointer passed 3318 * to this function when the hook was registered. 3319 * 3320 * Note that if a pre-change hook is called, any registered post-change hooks 3321 * are guaranteed to subsequently be called. 3322 */ 3323 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3324 void *opaque); 3325 /** 3326 * arm_register_el_change_hook: 3327 * Register a hook function which will be called immediately after this 3328 * CPU changes exception level or mode. The hook function will be 3329 * passed a pointer to the ARMCPU and the opaque data pointer passed 3330 * to this function when the hook was registered. 3331 * 3332 * Note that any registered hooks registered here are guaranteed to be called 3333 * if pre-change hooks have been. 3334 */ 3335 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3336 *opaque); 3337 3338 /** 3339 * arm_rebuild_hflags: 3340 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3341 */ 3342 void arm_rebuild_hflags(CPUARMState *env); 3343 3344 /** 3345 * aa32_vfp_dreg: 3346 * Return a pointer to the Dn register within env in 32-bit mode. 3347 */ 3348 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3349 { 3350 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3351 } 3352 3353 /** 3354 * aa32_vfp_qreg: 3355 * Return a pointer to the Qn register within env in 32-bit mode. 3356 */ 3357 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3358 { 3359 return &env->vfp.zregs[regno].d[0]; 3360 } 3361 3362 /** 3363 * aa64_vfp_qreg: 3364 * Return a pointer to the Qn register within env in 64-bit mode. 3365 */ 3366 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3367 { 3368 return &env->vfp.zregs[regno].d[0]; 3369 } 3370 3371 /* Shared between translate-sve.c and sve_helper.c. */ 3372 extern const uint64_t pred_esz_masks[4]; 3373 3374 /* 3375 * Naming convention for isar_feature functions: 3376 * Functions which test 32-bit ID registers should have _aa32_ in 3377 * their name. Functions which test 64-bit ID registers should have 3378 * _aa64_ in their name. These must only be used in code where we 3379 * know for certain that the CPU has AArch32 or AArch64 respectively 3380 * or where the correct answer for a CPU which doesn't implement that 3381 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3382 * system registers that are specific to that CPU state, for "should 3383 * we let this system register bit be set" tests where the 32-bit 3384 * flavour of the register doesn't have the bit, and so on). 3385 * Functions which simply ask "does this feature exist at all" have 3386 * _any_ in their name, and always return the logical OR of the _aa64_ 3387 * and the _aa32_ function. 3388 */ 3389 3390 /* 3391 * 32-bit feature tests via id registers. 3392 */ 3393 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3394 { 3395 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3396 } 3397 3398 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3399 { 3400 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3401 } 3402 3403 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3404 { 3405 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3406 } 3407 3408 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3409 { 3410 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3411 } 3412 3413 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3414 { 3415 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3416 } 3417 3418 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3419 { 3420 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3421 } 3422 3423 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3424 { 3425 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3426 } 3427 3428 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3429 { 3430 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3431 } 3432 3433 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3434 { 3435 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3436 } 3437 3438 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3439 { 3440 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3441 } 3442 3443 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3444 { 3445 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3446 } 3447 3448 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3449 { 3450 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3451 } 3452 3453 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3454 { 3455 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3456 } 3457 3458 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3459 { 3460 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3461 } 3462 3463 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3464 { 3465 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3466 } 3467 3468 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3469 { 3470 /* 3471 * This is a placeholder for use by VCMA until the rest of 3472 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3473 * At which point we can properly set and check MVFR1.FPHP. 3474 */ 3475 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3476 } 3477 3478 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3479 { 3480 /* 3481 * Return true if either VFP or SIMD is implemented. 3482 * In this case, a minimum of VFP w/ D0-D15. 3483 */ 3484 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3485 } 3486 3487 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3488 { 3489 /* Return true if D16-D31 are implemented */ 3490 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3491 } 3492 3493 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3494 { 3495 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3496 } 3497 3498 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3499 { 3500 /* Return true if CPU supports single precision floating point, VFPv2 */ 3501 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3502 } 3503 3504 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3505 { 3506 /* Return true if CPU supports single precision floating point, VFPv3 */ 3507 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3508 } 3509 3510 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3511 { 3512 /* Return true if CPU supports double precision floating point, VFPv2 */ 3513 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3514 } 3515 3516 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3517 { 3518 /* Return true if CPU supports double precision floating point, VFPv3 */ 3519 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3520 } 3521 3522 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3523 { 3524 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3525 } 3526 3527 /* 3528 * We always set the FP and SIMD FP16 fields to indicate identical 3529 * levels of support (assuming SIMD is implemented at all), so 3530 * we only need one set of accessors. 3531 */ 3532 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3533 { 3534 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3535 } 3536 3537 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3538 { 3539 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3540 } 3541 3542 /* 3543 * Note that this ID register field covers both VFP and Neon FMAC, 3544 * so should usually be tested in combination with some other 3545 * check that confirms the presence of whichever of VFP or Neon is 3546 * relevant, to avoid accidentally enabling a Neon feature on 3547 * a VFP-no-Neon core or vice-versa. 3548 */ 3549 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3550 { 3551 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3552 } 3553 3554 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3555 { 3556 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3557 } 3558 3559 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3560 { 3561 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3562 } 3563 3564 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3565 { 3566 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3567 } 3568 3569 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3570 { 3571 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3572 } 3573 3574 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3575 { 3576 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3577 } 3578 3579 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3580 { 3581 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3582 } 3583 3584 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3585 { 3586 /* 0xf means "non-standard IMPDEF PMU" */ 3587 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3588 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3589 } 3590 3591 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3592 { 3593 /* 0xf means "non-standard IMPDEF PMU" */ 3594 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3595 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3596 } 3597 3598 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3599 { 3600 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3601 } 3602 3603 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3604 { 3605 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3606 } 3607 3608 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3609 { 3610 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3611 } 3612 3613 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3614 { 3615 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3616 } 3617 3618 /* 3619 * 64-bit feature tests via id registers. 3620 */ 3621 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3622 { 3623 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3624 } 3625 3626 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3627 { 3628 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3629 } 3630 3631 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3632 { 3633 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3634 } 3635 3636 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3637 { 3638 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3639 } 3640 3641 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3642 { 3643 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3644 } 3645 3646 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3647 { 3648 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3649 } 3650 3651 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3652 { 3653 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3654 } 3655 3656 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3657 { 3658 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3659 } 3660 3661 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3662 { 3663 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3664 } 3665 3666 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3667 { 3668 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3669 } 3670 3671 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3672 { 3673 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3674 } 3675 3676 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3677 { 3678 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3679 } 3680 3681 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3682 { 3683 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3684 } 3685 3686 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3687 { 3688 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3689 } 3690 3691 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3692 { 3693 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3694 } 3695 3696 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3697 { 3698 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3699 } 3700 3701 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3702 { 3703 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3704 } 3705 3706 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3707 { 3708 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3709 } 3710 3711 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3712 { 3713 /* 3714 * Note that while QEMU will only implement the architected algorithm 3715 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation 3716 * defined algorithms, and thus API+GPI, and this predicate controls 3717 * migration of the 128-bit keys. 3718 */ 3719 return (id->id_aa64isar1 & 3720 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3721 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3722 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3723 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3724 } 3725 3726 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3727 { 3728 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3729 } 3730 3731 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3732 { 3733 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3734 } 3735 3736 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3737 { 3738 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3739 } 3740 3741 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3742 { 3743 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3744 } 3745 3746 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3747 { 3748 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3749 } 3750 3751 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3752 { 3753 /* We always set the AdvSIMD and FP fields identically. */ 3754 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3755 } 3756 3757 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3758 { 3759 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3760 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3761 } 3762 3763 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3764 { 3765 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3766 } 3767 3768 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3769 { 3770 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3771 } 3772 3773 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3774 { 3775 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3776 } 3777 3778 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3779 { 3780 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3781 } 3782 3783 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3784 { 3785 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3786 } 3787 3788 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3789 { 3790 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3791 } 3792 3793 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 3794 { 3795 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 3796 } 3797 3798 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3799 { 3800 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3801 } 3802 3803 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 3804 { 3805 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 3806 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3807 } 3808 3809 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 3810 { 3811 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 3812 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3813 } 3814 3815 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 3816 { 3817 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 3818 } 3819 3820 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 3821 { 3822 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 3823 } 3824 3825 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 3826 { 3827 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 3828 } 3829 3830 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 3831 { 3832 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 3833 } 3834 3835 /* 3836 * Feature tests for "does this exist in either 32-bit or 64-bit?" 3837 */ 3838 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 3839 { 3840 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 3841 } 3842 3843 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 3844 { 3845 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 3846 } 3847 3848 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 3849 { 3850 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 3851 } 3852 3853 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 3854 { 3855 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 3856 } 3857 3858 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 3859 { 3860 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 3861 } 3862 3863 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 3864 { 3865 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 3866 } 3867 3868 /* 3869 * Forward to the above feature tests given an ARMCPU pointer. 3870 */ 3871 #define cpu_isar_feature(name, cpu) \ 3872 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3873 3874 #endif 3875