1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #include "fpu/softfloat.h" 43 44 #define EXCP_UDEF 1 /* undefined instruction */ 45 #define EXCP_SWI 2 /* software interrupt */ 46 #define EXCP_PREFETCH_ABORT 3 47 #define EXCP_DATA_ABORT 4 48 #define EXCP_IRQ 5 49 #define EXCP_FIQ 6 50 #define EXCP_BKPT 7 51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 53 #define EXCP_HVC 11 /* HyperVisor Call */ 54 #define EXCP_HYP_TRAP 12 55 #define EXCP_SMC 13 /* Secure Monitor Call */ 56 #define EXCP_VIRQ 14 57 #define EXCP_VFIQ 15 58 #define EXCP_SEMIHOST 16 /* semihosting call */ 59 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 60 61 #define ARMV7M_EXCP_RESET 1 62 #define ARMV7M_EXCP_NMI 2 63 #define ARMV7M_EXCP_HARD 3 64 #define ARMV7M_EXCP_MEM 4 65 #define ARMV7M_EXCP_BUS 5 66 #define ARMV7M_EXCP_USAGE 6 67 #define ARMV7M_EXCP_SVC 11 68 #define ARMV7M_EXCP_DEBUG 12 69 #define ARMV7M_EXCP_PENDSV 14 70 #define ARMV7M_EXCP_SYSTICK 15 71 72 /* ARM-specific interrupt pending bits. */ 73 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 74 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 75 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 76 77 /* The usual mapping for an AArch64 system register to its AArch32 78 * counterpart is for the 32 bit world to have access to the lower 79 * half only (with writes leaving the upper half untouched). It's 80 * therefore useful to be able to pass TCG the offset of the least 81 * significant half of a uint64_t struct member. 82 */ 83 #ifdef HOST_WORDS_BIGENDIAN 84 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 85 #define offsetofhigh32(S, M) offsetof(S, M) 86 #else 87 #define offsetoflow32(S, M) offsetof(S, M) 88 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 89 #endif 90 91 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 92 #define ARM_CPU_IRQ 0 93 #define ARM_CPU_FIQ 1 94 #define ARM_CPU_VIRQ 2 95 #define ARM_CPU_VFIQ 3 96 97 #define NB_MMU_MODES 7 98 /* ARM-specific extra insn start words: 99 * 1: Conditional execution bits 100 * 2: Partial exception syndrome for data aborts 101 */ 102 #define TARGET_INSN_START_EXTRA_WORDS 2 103 104 /* The 2nd extra word holding syndrome info for data aborts does not use 105 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 106 * help the sleb128 encoder do a better job. 107 * When restoring the CPU state, we shift it back up. 108 */ 109 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 110 #define ARM_INSN_START_WORD2_SHIFT 14 111 112 /* We currently assume float and double are IEEE single and double 113 precision respectively. 114 Doing runtime conversions is tricky because VFP registers may contain 115 integer values (eg. as the result of a FTOSI instruction). 116 s<2n> maps to the least significant half of d<n> 117 s<2n+1> maps to the most significant half of d<n> 118 */ 119 120 /* CPU state for each instance of a generic timer (in cp15 c14) */ 121 typedef struct ARMGenericTimer { 122 uint64_t cval; /* Timer CompareValue register */ 123 uint64_t ctl; /* Timer Control register */ 124 } ARMGenericTimer; 125 126 #define GTIMER_PHYS 0 127 #define GTIMER_VIRT 1 128 #define GTIMER_HYP 2 129 #define GTIMER_SEC 3 130 #define NUM_GTIMERS 4 131 132 typedef struct { 133 uint64_t raw_tcr; 134 uint32_t mask; 135 uint32_t base_mask; 136 } TCR; 137 138 typedef struct CPUARMState { 139 /* Regs for current mode. */ 140 uint32_t regs[16]; 141 142 /* 32/64 switch only happens when taking and returning from 143 * exceptions so the overlap semantics are taken care of then 144 * instead of having a complicated union. 145 */ 146 /* Regs for A64 mode. */ 147 uint64_t xregs[32]; 148 uint64_t pc; 149 /* PSTATE isn't an architectural register for ARMv8. However, it is 150 * convenient for us to assemble the underlying state into a 32 bit format 151 * identical to the architectural format used for the SPSR. (This is also 152 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 153 * 'pstate' register are.) Of the PSTATE bits: 154 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 155 * semantics as for AArch32, as described in the comments on each field) 156 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 157 * DAIF (exception masks) are kept in env->daif 158 * all other bits are stored in their correct places in env->pstate 159 */ 160 uint32_t pstate; 161 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 162 163 /* Frequently accessed CPSR bits are stored separately for efficiency. 164 This contains all the other bits. Use cpsr_{read,write} to access 165 the whole CPSR. */ 166 uint32_t uncached_cpsr; 167 uint32_t spsr; 168 169 /* Banked registers. */ 170 uint64_t banked_spsr[8]; 171 uint32_t banked_r13[8]; 172 uint32_t banked_r14[8]; 173 174 /* These hold r8-r12. */ 175 uint32_t usr_regs[5]; 176 uint32_t fiq_regs[5]; 177 178 /* cpsr flag cache for faster execution */ 179 uint32_t CF; /* 0 or 1 */ 180 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 181 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 182 uint32_t ZF; /* Z set if zero. */ 183 uint32_t QF; /* 0 or 1 */ 184 uint32_t GE; /* cpsr[19:16] */ 185 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 186 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 187 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 188 189 uint64_t elr_el[4]; /* AArch64 exception link regs */ 190 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 191 192 /* System control coprocessor (cp15) */ 193 struct { 194 uint32_t c0_cpuid; 195 union { /* Cache size selection */ 196 struct { 197 uint64_t _unused_csselr0; 198 uint64_t csselr_ns; 199 uint64_t _unused_csselr1; 200 uint64_t csselr_s; 201 }; 202 uint64_t csselr_el[4]; 203 }; 204 union { /* System control register. */ 205 struct { 206 uint64_t _unused_sctlr; 207 uint64_t sctlr_ns; 208 uint64_t hsctlr; 209 uint64_t sctlr_s; 210 }; 211 uint64_t sctlr_el[4]; 212 }; 213 uint64_t cpacr_el1; /* Architectural feature access control register */ 214 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 215 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 216 uint64_t sder; /* Secure debug enable register. */ 217 uint32_t nsacr; /* Non-secure access control register. */ 218 union { /* MMU translation table base 0. */ 219 struct { 220 uint64_t _unused_ttbr0_0; 221 uint64_t ttbr0_ns; 222 uint64_t _unused_ttbr0_1; 223 uint64_t ttbr0_s; 224 }; 225 uint64_t ttbr0_el[4]; 226 }; 227 union { /* MMU translation table base 1. */ 228 struct { 229 uint64_t _unused_ttbr1_0; 230 uint64_t ttbr1_ns; 231 uint64_t _unused_ttbr1_1; 232 uint64_t ttbr1_s; 233 }; 234 uint64_t ttbr1_el[4]; 235 }; 236 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 237 /* MMU translation table base control. */ 238 TCR tcr_el[4]; 239 TCR vtcr_el2; /* Virtualization Translation Control. */ 240 uint32_t c2_data; /* MPU data cacheable bits. */ 241 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 242 union { /* MMU domain access control register 243 * MPU write buffer control. 244 */ 245 struct { 246 uint64_t dacr_ns; 247 uint64_t dacr_s; 248 }; 249 struct { 250 uint64_t dacr32_el2; 251 }; 252 }; 253 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 254 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 255 uint64_t hcr_el2; /* Hypervisor configuration register */ 256 uint64_t scr_el3; /* Secure configuration register. */ 257 union { /* Fault status registers. */ 258 struct { 259 uint64_t ifsr_ns; 260 uint64_t ifsr_s; 261 }; 262 struct { 263 uint64_t ifsr32_el2; 264 }; 265 }; 266 union { 267 struct { 268 uint64_t _unused_dfsr; 269 uint64_t dfsr_ns; 270 uint64_t hsr; 271 uint64_t dfsr_s; 272 }; 273 uint64_t esr_el[4]; 274 }; 275 uint32_t c6_region[8]; /* MPU base/size registers. */ 276 union { /* Fault address registers. */ 277 struct { 278 uint64_t _unused_far0; 279 #ifdef HOST_WORDS_BIGENDIAN 280 uint32_t ifar_ns; 281 uint32_t dfar_ns; 282 uint32_t ifar_s; 283 uint32_t dfar_s; 284 #else 285 uint32_t dfar_ns; 286 uint32_t ifar_ns; 287 uint32_t dfar_s; 288 uint32_t ifar_s; 289 #endif 290 uint64_t _unused_far3; 291 }; 292 uint64_t far_el[4]; 293 }; 294 uint64_t hpfar_el2; 295 uint64_t hstr_el2; 296 union { /* Translation result. */ 297 struct { 298 uint64_t _unused_par_0; 299 uint64_t par_ns; 300 uint64_t _unused_par_1; 301 uint64_t par_s; 302 }; 303 uint64_t par_el[4]; 304 }; 305 306 uint32_t c6_rgnr; 307 308 uint32_t c9_insn; /* Cache lockdown registers. */ 309 uint32_t c9_data; 310 uint64_t c9_pmcr; /* performance monitor control register */ 311 uint64_t c9_pmcnten; /* perf monitor counter enables */ 312 uint32_t c9_pmovsr; /* perf monitor overflow status */ 313 uint32_t c9_pmuserenr; /* perf monitor user enable */ 314 uint64_t c9_pmselr; /* perf monitor counter selection register */ 315 uint64_t c9_pminten; /* perf monitor interrupt enables */ 316 union { /* Memory attribute redirection */ 317 struct { 318 #ifdef HOST_WORDS_BIGENDIAN 319 uint64_t _unused_mair_0; 320 uint32_t mair1_ns; 321 uint32_t mair0_ns; 322 uint64_t _unused_mair_1; 323 uint32_t mair1_s; 324 uint32_t mair0_s; 325 #else 326 uint64_t _unused_mair_0; 327 uint32_t mair0_ns; 328 uint32_t mair1_ns; 329 uint64_t _unused_mair_1; 330 uint32_t mair0_s; 331 uint32_t mair1_s; 332 #endif 333 }; 334 uint64_t mair_el[4]; 335 }; 336 union { /* vector base address register */ 337 struct { 338 uint64_t _unused_vbar; 339 uint64_t vbar_ns; 340 uint64_t hvbar; 341 uint64_t vbar_s; 342 }; 343 uint64_t vbar_el[4]; 344 }; 345 uint32_t mvbar; /* (monitor) vector base address register */ 346 struct { /* FCSE PID. */ 347 uint32_t fcseidr_ns; 348 uint32_t fcseidr_s; 349 }; 350 union { /* Context ID. */ 351 struct { 352 uint64_t _unused_contextidr_0; 353 uint64_t contextidr_ns; 354 uint64_t _unused_contextidr_1; 355 uint64_t contextidr_s; 356 }; 357 uint64_t contextidr_el[4]; 358 }; 359 union { /* User RW Thread register. */ 360 struct { 361 uint64_t tpidrurw_ns; 362 uint64_t tpidrprw_ns; 363 uint64_t htpidr; 364 uint64_t _tpidr_el3; 365 }; 366 uint64_t tpidr_el[4]; 367 }; 368 /* The secure banks of these registers don't map anywhere */ 369 uint64_t tpidrurw_s; 370 uint64_t tpidrprw_s; 371 uint64_t tpidruro_s; 372 373 union { /* User RO Thread register. */ 374 uint64_t tpidruro_ns; 375 uint64_t tpidrro_el[1]; 376 }; 377 uint64_t c14_cntfrq; /* Counter Frequency register */ 378 uint64_t c14_cntkctl; /* Timer Control register */ 379 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 380 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 381 ARMGenericTimer c14_timer[NUM_GTIMERS]; 382 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 383 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 384 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 385 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 386 uint32_t c15_threadid; /* TI debugger thread-ID. */ 387 uint32_t c15_config_base_address; /* SCU base address. */ 388 uint32_t c15_diagnostic; /* diagnostic register */ 389 uint32_t c15_power_diagnostic; 390 uint32_t c15_power_control; /* power control */ 391 uint64_t dbgbvr[16]; /* breakpoint value registers */ 392 uint64_t dbgbcr[16]; /* breakpoint control registers */ 393 uint64_t dbgwvr[16]; /* watchpoint value registers */ 394 uint64_t dbgwcr[16]; /* watchpoint control registers */ 395 uint64_t mdscr_el1; 396 uint64_t oslsr_el1; /* OS Lock Status */ 397 uint64_t mdcr_el2; 398 uint64_t mdcr_el3; 399 /* If the counter is enabled, this stores the last time the counter 400 * was reset. Otherwise it stores the counter value 401 */ 402 uint64_t c15_ccnt; 403 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 404 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 405 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 406 } cp15; 407 408 struct { 409 uint32_t other_sp; 410 uint32_t vecbase; 411 uint32_t basepri; 412 uint32_t control; 413 uint32_t ccr; /* Configuration and Control */ 414 uint32_t cfsr; /* Configurable Fault Status */ 415 uint32_t hfsr; /* HardFault Status */ 416 uint32_t dfsr; /* Debug Fault Status Register */ 417 uint32_t mmfar; /* MemManage Fault Address */ 418 uint32_t bfar; /* BusFault Address */ 419 int exception; 420 } v7m; 421 422 /* Information associated with an exception about to be taken: 423 * code which raises an exception must set cs->exception_index and 424 * the relevant parts of this structure; the cpu_do_interrupt function 425 * will then set the guest-visible registers as part of the exception 426 * entry process. 427 */ 428 struct { 429 uint32_t syndrome; /* AArch64 format syndrome register */ 430 uint32_t fsr; /* AArch32 format fault status register info */ 431 uint64_t vaddress; /* virtual addr associated with exception, if any */ 432 uint32_t target_el; /* EL the exception should be targeted for */ 433 /* If we implement EL2 we will also need to store information 434 * about the intermediate physical address for stage 2 faults. 435 */ 436 } exception; 437 438 /* Thumb-2 EE state. */ 439 uint32_t teecr; 440 uint32_t teehbr; 441 442 /* VFP coprocessor state. */ 443 struct { 444 /* VFP/Neon register state. Note that the mapping between S, D and Q 445 * views of the register bank differs between AArch64 and AArch32: 446 * In AArch32: 447 * Qn = regs[2n+1]:regs[2n] 448 * Dn = regs[n] 449 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n 450 * (and regs[32] to regs[63] are inaccessible) 451 * In AArch64: 452 * Qn = regs[2n+1]:regs[2n] 453 * Dn = regs[2n] 454 * Sn = regs[2n] bits 31..0 455 * This corresponds to the architecturally defined mapping between 456 * the two execution states, and means we do not need to explicitly 457 * map these registers when changing states. 458 */ 459 float64 regs[64]; 460 461 uint32_t xregs[16]; 462 /* We store these fpcsr fields separately for convenience. */ 463 int vec_len; 464 int vec_stride; 465 466 /* scratch space when Tn are not sufficient. */ 467 uint32_t scratch[8]; 468 469 /* fp_status is the "normal" fp status. standard_fp_status retains 470 * values corresponding to the ARM "Standard FPSCR Value", ie 471 * default-NaN, flush-to-zero, round-to-nearest and is used by 472 * any operations (generally Neon) which the architecture defines 473 * as controlled by the standard FPSCR value rather than the FPSCR. 474 * 475 * To avoid having to transfer exception bits around, we simply 476 * say that the FPSCR cumulative exception flags are the logical 477 * OR of the flags in the two fp statuses. This relies on the 478 * only thing which needs to read the exception flags being 479 * an explicit FPSCR read. 480 */ 481 float_status fp_status; 482 float_status standard_fp_status; 483 } vfp; 484 uint64_t exclusive_addr; 485 uint64_t exclusive_val; 486 uint64_t exclusive_high; 487 488 /* iwMMXt coprocessor state. */ 489 struct { 490 uint64_t regs[16]; 491 uint64_t val; 492 493 uint32_t cregs[16]; 494 } iwmmxt; 495 496 #if defined(CONFIG_USER_ONLY) 497 /* For usermode syscall translation. */ 498 int eabi; 499 #endif 500 501 struct CPUBreakpoint *cpu_breakpoint[16]; 502 struct CPUWatchpoint *cpu_watchpoint[16]; 503 504 /* Fields up to this point are cleared by a CPU reset */ 505 struct {} end_reset_fields; 506 507 CPU_COMMON 508 509 /* Fields after CPU_COMMON are preserved across CPU reset. */ 510 511 /* Internal CPU feature flags. */ 512 uint64_t features; 513 514 /* PMSAv7 MPU */ 515 struct { 516 uint32_t *drbar; 517 uint32_t *drsr; 518 uint32_t *dracr; 519 } pmsav7; 520 521 void *nvic; 522 const struct arm_boot_info *boot_info; 523 } CPUARMState; 524 525 /** 526 * ARMELChangeHook: 527 * type of a function which can be registered via arm_register_el_change_hook() 528 * to get callbacks when the CPU changes its exception level or mode. 529 */ 530 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); 531 532 533 /* These values map onto the return values for 534 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 535 typedef enum ARMPSCIState { 536 PSCI_OFF = 0, 537 PSCI_ON = 1, 538 PSCI_ON_PENDING = 2 539 } ARMPSCIState; 540 541 /** 542 * ARMCPU: 543 * @env: #CPUARMState 544 * 545 * An ARM CPU core. 546 */ 547 struct ARMCPU { 548 /*< private >*/ 549 CPUState parent_obj; 550 /*< public >*/ 551 552 CPUARMState env; 553 554 /* Coprocessor information */ 555 GHashTable *cp_regs; 556 /* For marshalling (mostly coprocessor) register state between the 557 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 558 * we use these arrays. 559 */ 560 /* List of register indexes managed via these arrays; (full KVM style 561 * 64 bit indexes, not CPRegInfo 32 bit indexes) 562 */ 563 uint64_t *cpreg_indexes; 564 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 565 uint64_t *cpreg_values; 566 /* Length of the indexes, values, reset_values arrays */ 567 int32_t cpreg_array_len; 568 /* These are used only for migration: incoming data arrives in 569 * these fields and is sanity checked in post_load before copying 570 * to the working data structures above. 571 */ 572 uint64_t *cpreg_vmstate_indexes; 573 uint64_t *cpreg_vmstate_values; 574 int32_t cpreg_vmstate_array_len; 575 576 /* Timers used by the generic (architected) timer */ 577 QEMUTimer *gt_timer[NUM_GTIMERS]; 578 /* GPIO outputs for generic timer */ 579 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 580 /* GPIO output for GICv3 maintenance interrupt signal */ 581 qemu_irq gicv3_maintenance_interrupt; 582 583 /* MemoryRegion to use for secure physical accesses */ 584 MemoryRegion *secure_memory; 585 586 /* 'compatible' string for this CPU for Linux device trees */ 587 const char *dtb_compatible; 588 589 /* PSCI version for this CPU 590 * Bits[31:16] = Major Version 591 * Bits[15:0] = Minor Version 592 */ 593 uint32_t psci_version; 594 595 /* Should CPU start in PSCI powered-off state? */ 596 bool start_powered_off; 597 598 /* Current power state, access guarded by BQL */ 599 ARMPSCIState power_state; 600 601 /* CPU has virtualization extension */ 602 bool has_el2; 603 /* CPU has security extension */ 604 bool has_el3; 605 /* CPU has PMU (Performance Monitor Unit) */ 606 bool has_pmu; 607 608 /* CPU has memory protection unit */ 609 bool has_mpu; 610 /* PMSAv7 MPU number of supported regions */ 611 uint32_t pmsav7_dregion; 612 613 /* PSCI conduit used to invoke PSCI methods 614 * 0 - disabled, 1 - smc, 2 - hvc 615 */ 616 uint32_t psci_conduit; 617 618 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 619 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 620 */ 621 uint32_t kvm_target; 622 623 /* KVM init features for this CPU */ 624 uint32_t kvm_init_features[7]; 625 626 /* Uniprocessor system with MP extensions */ 627 bool mp_is_up; 628 629 /* The instance init functions for implementation-specific subclasses 630 * set these fields to specify the implementation-dependent values of 631 * various constant registers and reset values of non-constant 632 * registers. 633 * Some of these might become QOM properties eventually. 634 * Field names match the official register names as defined in the 635 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 636 * is used for reset values of non-constant registers; no reset_ 637 * prefix means a constant register. 638 */ 639 uint32_t midr; 640 uint32_t revidr; 641 uint32_t reset_fpsid; 642 uint32_t mvfr0; 643 uint32_t mvfr1; 644 uint32_t mvfr2; 645 uint32_t ctr; 646 uint32_t reset_sctlr; 647 uint32_t id_pfr0; 648 uint32_t id_pfr1; 649 uint32_t id_dfr0; 650 uint32_t pmceid0; 651 uint32_t pmceid1; 652 uint32_t id_afr0; 653 uint32_t id_mmfr0; 654 uint32_t id_mmfr1; 655 uint32_t id_mmfr2; 656 uint32_t id_mmfr3; 657 uint32_t id_mmfr4; 658 uint32_t id_isar0; 659 uint32_t id_isar1; 660 uint32_t id_isar2; 661 uint32_t id_isar3; 662 uint32_t id_isar4; 663 uint32_t id_isar5; 664 uint64_t id_aa64pfr0; 665 uint64_t id_aa64pfr1; 666 uint64_t id_aa64dfr0; 667 uint64_t id_aa64dfr1; 668 uint64_t id_aa64afr0; 669 uint64_t id_aa64afr1; 670 uint64_t id_aa64isar0; 671 uint64_t id_aa64isar1; 672 uint64_t id_aa64mmfr0; 673 uint64_t id_aa64mmfr1; 674 uint32_t dbgdidr; 675 uint32_t clidr; 676 uint64_t mp_affinity; /* MP ID without feature bits */ 677 /* The elements of this array are the CCSIDR values for each cache, 678 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 679 */ 680 uint32_t ccsidr[16]; 681 uint64_t reset_cbar; 682 uint32_t reset_auxcr; 683 bool reset_hivecs; 684 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 685 uint32_t dcz_blocksize; 686 uint64_t rvbar; 687 688 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 689 int gic_num_lrs; /* number of list registers */ 690 int gic_vpribits; /* number of virtual priority bits */ 691 int gic_vprebits; /* number of virtual preemption bits */ 692 693 /* Whether the cfgend input is high (i.e. this CPU should reset into 694 * big-endian mode). This setting isn't used directly: instead it modifies 695 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 696 * architecture version. 697 */ 698 bool cfgend; 699 700 ARMELChangeHook *el_change_hook; 701 void *el_change_hook_opaque; 702 }; 703 704 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 705 { 706 return container_of(env, ARMCPU, env); 707 } 708 709 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 710 711 #define ENV_OFFSET offsetof(ARMCPU, env) 712 713 #ifndef CONFIG_USER_ONLY 714 extern const struct VMStateDescription vmstate_arm_cpu; 715 #endif 716 717 void arm_cpu_do_interrupt(CPUState *cpu); 718 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 719 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 720 721 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 722 int flags); 723 724 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 725 MemTxAttrs *attrs); 726 727 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 728 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 729 730 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 731 int cpuid, void *opaque); 732 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 733 int cpuid, void *opaque); 734 735 #ifdef TARGET_AARCH64 736 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 737 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 738 #endif 739 740 ARMCPU *cpu_arm_init(const char *cpu_model); 741 target_ulong do_arm_semihosting(CPUARMState *env); 742 void aarch64_sync_32_to_64(CPUARMState *env); 743 void aarch64_sync_64_to_32(CPUARMState *env); 744 745 static inline bool is_a64(CPUARMState *env) 746 { 747 return env->aarch64; 748 } 749 750 /* you can call this signal handler from your SIGBUS and SIGSEGV 751 signal handlers to inform the virtual CPU of exceptions. non zero 752 is returned if the signal was handled by the virtual CPU. */ 753 int cpu_arm_signal_handler(int host_signum, void *pinfo, 754 void *puc); 755 756 /** 757 * pmccntr_sync 758 * @env: CPUARMState 759 * 760 * Synchronises the counter in the PMCCNTR. This must always be called twice, 761 * once before any action that might affect the timer and again afterwards. 762 * The function is used to swap the state of the register if required. 763 * This only happens when not in user mode (!CONFIG_USER_ONLY) 764 */ 765 void pmccntr_sync(CPUARMState *env); 766 767 /* SCTLR bit meanings. Several bits have been reused in newer 768 * versions of the architecture; in that case we define constants 769 * for both old and new bit meanings. Code which tests against those 770 * bits should probably check or otherwise arrange that the CPU 771 * is the architectural version it expects. 772 */ 773 #define SCTLR_M (1U << 0) 774 #define SCTLR_A (1U << 1) 775 #define SCTLR_C (1U << 2) 776 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 777 #define SCTLR_SA (1U << 3) 778 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 779 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 780 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 781 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 782 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 783 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 784 #define SCTLR_ITD (1U << 7) /* v8 onward */ 785 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 786 #define SCTLR_SED (1U << 8) /* v8 onward */ 787 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 788 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 789 #define SCTLR_F (1U << 10) /* up to v6 */ 790 #define SCTLR_SW (1U << 10) /* v7 onward */ 791 #define SCTLR_Z (1U << 11) 792 #define SCTLR_I (1U << 12) 793 #define SCTLR_V (1U << 13) 794 #define SCTLR_RR (1U << 14) /* up to v7 */ 795 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 796 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 797 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 798 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 799 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 800 #define SCTLR_HA (1U << 17) 801 #define SCTLR_BR (1U << 17) /* PMSA only */ 802 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 803 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 804 #define SCTLR_WXN (1U << 19) 805 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 806 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 807 #define SCTLR_FI (1U << 21) 808 #define SCTLR_U (1U << 22) 809 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 810 #define SCTLR_VE (1U << 24) /* up to v7 */ 811 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 812 #define SCTLR_EE (1U << 25) 813 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 814 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 815 #define SCTLR_NMFI (1U << 27) 816 #define SCTLR_TRE (1U << 28) 817 #define SCTLR_AFE (1U << 29) 818 #define SCTLR_TE (1U << 30) 819 820 #define CPTR_TCPAC (1U << 31) 821 #define CPTR_TTA (1U << 20) 822 #define CPTR_TFP (1U << 10) 823 824 #define MDCR_EPMAD (1U << 21) 825 #define MDCR_EDAD (1U << 20) 826 #define MDCR_SPME (1U << 17) 827 #define MDCR_SDD (1U << 16) 828 #define MDCR_SPD (3U << 14) 829 #define MDCR_TDRA (1U << 11) 830 #define MDCR_TDOSA (1U << 10) 831 #define MDCR_TDA (1U << 9) 832 #define MDCR_TDE (1U << 8) 833 #define MDCR_HPME (1U << 7) 834 #define MDCR_TPM (1U << 6) 835 #define MDCR_TPMCR (1U << 5) 836 837 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 838 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 839 840 #define CPSR_M (0x1fU) 841 #define CPSR_T (1U << 5) 842 #define CPSR_F (1U << 6) 843 #define CPSR_I (1U << 7) 844 #define CPSR_A (1U << 8) 845 #define CPSR_E (1U << 9) 846 #define CPSR_IT_2_7 (0xfc00U) 847 #define CPSR_GE (0xfU << 16) 848 #define CPSR_IL (1U << 20) 849 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 850 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 851 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 852 * where it is live state but not accessible to the AArch32 code. 853 */ 854 #define CPSR_RESERVED (0x7U << 21) 855 #define CPSR_J (1U << 24) 856 #define CPSR_IT_0_1 (3U << 25) 857 #define CPSR_Q (1U << 27) 858 #define CPSR_V (1U << 28) 859 #define CPSR_C (1U << 29) 860 #define CPSR_Z (1U << 30) 861 #define CPSR_N (1U << 31) 862 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 863 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 864 865 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 866 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 867 | CPSR_NZCV) 868 /* Bits writable in user mode. */ 869 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 870 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 871 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 872 /* Mask of bits which may be set by exception return copying them from SPSR */ 873 #define CPSR_ERET_MASK (~CPSR_RESERVED) 874 875 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 876 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 877 #define TTBCR_PD0 (1U << 4) 878 #define TTBCR_PD1 (1U << 5) 879 #define TTBCR_EPD0 (1U << 7) 880 #define TTBCR_IRGN0 (3U << 8) 881 #define TTBCR_ORGN0 (3U << 10) 882 #define TTBCR_SH0 (3U << 12) 883 #define TTBCR_T1SZ (3U << 16) 884 #define TTBCR_A1 (1U << 22) 885 #define TTBCR_EPD1 (1U << 23) 886 #define TTBCR_IRGN1 (3U << 24) 887 #define TTBCR_ORGN1 (3U << 26) 888 #define TTBCR_SH1 (1U << 28) 889 #define TTBCR_EAE (1U << 31) 890 891 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 892 * Only these are valid when in AArch64 mode; in 893 * AArch32 mode SPSRs are basically CPSR-format. 894 */ 895 #define PSTATE_SP (1U) 896 #define PSTATE_M (0xFU) 897 #define PSTATE_nRW (1U << 4) 898 #define PSTATE_F (1U << 6) 899 #define PSTATE_I (1U << 7) 900 #define PSTATE_A (1U << 8) 901 #define PSTATE_D (1U << 9) 902 #define PSTATE_IL (1U << 20) 903 #define PSTATE_SS (1U << 21) 904 #define PSTATE_V (1U << 28) 905 #define PSTATE_C (1U << 29) 906 #define PSTATE_Z (1U << 30) 907 #define PSTATE_N (1U << 31) 908 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 909 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 910 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 911 /* Mode values for AArch64 */ 912 #define PSTATE_MODE_EL3h 13 913 #define PSTATE_MODE_EL3t 12 914 #define PSTATE_MODE_EL2h 9 915 #define PSTATE_MODE_EL2t 8 916 #define PSTATE_MODE_EL1h 5 917 #define PSTATE_MODE_EL1t 4 918 #define PSTATE_MODE_EL0t 0 919 920 /* Map EL and handler into a PSTATE_MODE. */ 921 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 922 { 923 return (el << 2) | handler; 924 } 925 926 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 927 * interprocessing, so we don't attempt to sync with the cpsr state used by 928 * the 32 bit decoder. 929 */ 930 static inline uint32_t pstate_read(CPUARMState *env) 931 { 932 int ZF; 933 934 ZF = (env->ZF == 0); 935 return (env->NF & 0x80000000) | (ZF << 30) 936 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 937 | env->pstate | env->daif; 938 } 939 940 static inline void pstate_write(CPUARMState *env, uint32_t val) 941 { 942 env->ZF = (~val) & PSTATE_Z; 943 env->NF = val; 944 env->CF = (val >> 29) & 1; 945 env->VF = (val << 3) & 0x80000000; 946 env->daif = val & PSTATE_DAIF; 947 env->pstate = val & ~CACHED_PSTATE_BITS; 948 } 949 950 /* Return the current CPSR value. */ 951 uint32_t cpsr_read(CPUARMState *env); 952 953 typedef enum CPSRWriteType { 954 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 955 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 956 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 957 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 958 } CPSRWriteType; 959 960 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 961 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 962 CPSRWriteType write_type); 963 964 /* Return the current xPSR value. */ 965 static inline uint32_t xpsr_read(CPUARMState *env) 966 { 967 int ZF; 968 ZF = (env->ZF == 0); 969 return (env->NF & 0x80000000) | (ZF << 30) 970 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 971 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 972 | ((env->condexec_bits & 0xfc) << 8) 973 | env->v7m.exception; 974 } 975 976 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 977 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 978 { 979 if (mask & CPSR_NZCV) { 980 env->ZF = (~val) & CPSR_Z; 981 env->NF = val; 982 env->CF = (val >> 29) & 1; 983 env->VF = (val << 3) & 0x80000000; 984 } 985 if (mask & CPSR_Q) 986 env->QF = ((val & CPSR_Q) != 0); 987 if (mask & (1 << 24)) 988 env->thumb = ((val & (1 << 24)) != 0); 989 if (mask & CPSR_IT_0_1) { 990 env->condexec_bits &= ~3; 991 env->condexec_bits |= (val >> 25) & 3; 992 } 993 if (mask & CPSR_IT_2_7) { 994 env->condexec_bits &= 3; 995 env->condexec_bits |= (val >> 8) & 0xfc; 996 } 997 if (mask & 0x1ff) { 998 env->v7m.exception = val & 0x1ff; 999 } 1000 } 1001 1002 #define HCR_VM (1ULL << 0) 1003 #define HCR_SWIO (1ULL << 1) 1004 #define HCR_PTW (1ULL << 2) 1005 #define HCR_FMO (1ULL << 3) 1006 #define HCR_IMO (1ULL << 4) 1007 #define HCR_AMO (1ULL << 5) 1008 #define HCR_VF (1ULL << 6) 1009 #define HCR_VI (1ULL << 7) 1010 #define HCR_VSE (1ULL << 8) 1011 #define HCR_FB (1ULL << 9) 1012 #define HCR_BSU_MASK (3ULL << 10) 1013 #define HCR_DC (1ULL << 12) 1014 #define HCR_TWI (1ULL << 13) 1015 #define HCR_TWE (1ULL << 14) 1016 #define HCR_TID0 (1ULL << 15) 1017 #define HCR_TID1 (1ULL << 16) 1018 #define HCR_TID2 (1ULL << 17) 1019 #define HCR_TID3 (1ULL << 18) 1020 #define HCR_TSC (1ULL << 19) 1021 #define HCR_TIDCP (1ULL << 20) 1022 #define HCR_TACR (1ULL << 21) 1023 #define HCR_TSW (1ULL << 22) 1024 #define HCR_TPC (1ULL << 23) 1025 #define HCR_TPU (1ULL << 24) 1026 #define HCR_TTLB (1ULL << 25) 1027 #define HCR_TVM (1ULL << 26) 1028 #define HCR_TGE (1ULL << 27) 1029 #define HCR_TDZ (1ULL << 28) 1030 #define HCR_HCD (1ULL << 29) 1031 #define HCR_TRVM (1ULL << 30) 1032 #define HCR_RW (1ULL << 31) 1033 #define HCR_CD (1ULL << 32) 1034 #define HCR_ID (1ULL << 33) 1035 #define HCR_MASK ((1ULL << 34) - 1) 1036 1037 #define SCR_NS (1U << 0) 1038 #define SCR_IRQ (1U << 1) 1039 #define SCR_FIQ (1U << 2) 1040 #define SCR_EA (1U << 3) 1041 #define SCR_FW (1U << 4) 1042 #define SCR_AW (1U << 5) 1043 #define SCR_NET (1U << 6) 1044 #define SCR_SMD (1U << 7) 1045 #define SCR_HCE (1U << 8) 1046 #define SCR_SIF (1U << 9) 1047 #define SCR_RW (1U << 10) 1048 #define SCR_ST (1U << 11) 1049 #define SCR_TWI (1U << 12) 1050 #define SCR_TWE (1U << 13) 1051 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1052 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1053 1054 /* Return the current FPSCR value. */ 1055 uint32_t vfp_get_fpscr(CPUARMState *env); 1056 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1057 1058 /* For A64 the FPSCR is split into two logically distinct registers, 1059 * FPCR and FPSR. However since they still use non-overlapping bits 1060 * we store the underlying state in fpscr and just mask on read/write. 1061 */ 1062 #define FPSR_MASK 0xf800009f 1063 #define FPCR_MASK 0x07f79f00 1064 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1065 { 1066 return vfp_get_fpscr(env) & FPSR_MASK; 1067 } 1068 1069 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1070 { 1071 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1072 vfp_set_fpscr(env, new_fpscr); 1073 } 1074 1075 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1076 { 1077 return vfp_get_fpscr(env) & FPCR_MASK; 1078 } 1079 1080 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1081 { 1082 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1083 vfp_set_fpscr(env, new_fpscr); 1084 } 1085 1086 enum arm_cpu_mode { 1087 ARM_CPU_MODE_USR = 0x10, 1088 ARM_CPU_MODE_FIQ = 0x11, 1089 ARM_CPU_MODE_IRQ = 0x12, 1090 ARM_CPU_MODE_SVC = 0x13, 1091 ARM_CPU_MODE_MON = 0x16, 1092 ARM_CPU_MODE_ABT = 0x17, 1093 ARM_CPU_MODE_HYP = 0x1a, 1094 ARM_CPU_MODE_UND = 0x1b, 1095 ARM_CPU_MODE_SYS = 0x1f 1096 }; 1097 1098 /* VFP system registers. */ 1099 #define ARM_VFP_FPSID 0 1100 #define ARM_VFP_FPSCR 1 1101 #define ARM_VFP_MVFR2 5 1102 #define ARM_VFP_MVFR1 6 1103 #define ARM_VFP_MVFR0 7 1104 #define ARM_VFP_FPEXC 8 1105 #define ARM_VFP_FPINST 9 1106 #define ARM_VFP_FPINST2 10 1107 1108 /* iwMMXt coprocessor control registers. */ 1109 #define ARM_IWMMXT_wCID 0 1110 #define ARM_IWMMXT_wCon 1 1111 #define ARM_IWMMXT_wCSSF 2 1112 #define ARM_IWMMXT_wCASF 3 1113 #define ARM_IWMMXT_wCGR0 8 1114 #define ARM_IWMMXT_wCGR1 9 1115 #define ARM_IWMMXT_wCGR2 10 1116 #define ARM_IWMMXT_wCGR3 11 1117 1118 /* V7M CCR bits */ 1119 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1120 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1121 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1122 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1123 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1124 FIELD(V7M_CCR, STKALIGN, 9, 1) 1125 FIELD(V7M_CCR, DC, 16, 1) 1126 FIELD(V7M_CCR, IC, 17, 1) 1127 1128 /* V7M CFSR bits for MMFSR */ 1129 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1130 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1131 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1132 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1133 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1134 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1135 1136 /* V7M CFSR bits for BFSR */ 1137 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1138 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1139 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1140 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1141 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1142 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1143 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1144 1145 /* V7M CFSR bits for UFSR */ 1146 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1147 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1148 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1149 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1150 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1151 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1152 1153 /* V7M HFSR bits */ 1154 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1155 FIELD(V7M_HFSR, FORCED, 30, 1) 1156 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1157 1158 /* V7M DFSR bits */ 1159 FIELD(V7M_DFSR, HALTED, 0, 1) 1160 FIELD(V7M_DFSR, BKPT, 1, 1) 1161 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1162 FIELD(V7M_DFSR, VCATCH, 3, 1) 1163 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1164 1165 /* If adding a feature bit which corresponds to a Linux ELF 1166 * HWCAP bit, remember to update the feature-bit-to-hwcap 1167 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1168 */ 1169 enum arm_features { 1170 ARM_FEATURE_VFP, 1171 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1172 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1173 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1174 ARM_FEATURE_V6, 1175 ARM_FEATURE_V6K, 1176 ARM_FEATURE_V7, 1177 ARM_FEATURE_THUMB2, 1178 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ 1179 ARM_FEATURE_VFP3, 1180 ARM_FEATURE_VFP_FP16, 1181 ARM_FEATURE_NEON, 1182 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1183 ARM_FEATURE_M, /* Microcontroller profile. */ 1184 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1185 ARM_FEATURE_THUMB2EE, 1186 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1187 ARM_FEATURE_V4T, 1188 ARM_FEATURE_V5, 1189 ARM_FEATURE_STRONGARM, 1190 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1191 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1192 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1193 ARM_FEATURE_GENERIC_TIMER, 1194 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1195 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1196 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1197 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1198 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1199 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1200 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1201 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1202 ARM_FEATURE_V8, 1203 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1204 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1205 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1206 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1207 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1208 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1209 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1210 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1211 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1212 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1213 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1214 ARM_FEATURE_PMU, /* has PMU support */ 1215 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1216 }; 1217 1218 static inline int arm_feature(CPUARMState *env, int feature) 1219 { 1220 return (env->features & (1ULL << feature)) != 0; 1221 } 1222 1223 #if !defined(CONFIG_USER_ONLY) 1224 /* Return true if exception levels below EL3 are in secure state, 1225 * or would be following an exception return to that level. 1226 * Unlike arm_is_secure() (which is always a question about the 1227 * _current_ state of the CPU) this doesn't care about the current 1228 * EL or mode. 1229 */ 1230 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1231 { 1232 if (arm_feature(env, ARM_FEATURE_EL3)) { 1233 return !(env->cp15.scr_el3 & SCR_NS); 1234 } else { 1235 /* If EL3 is not supported then the secure state is implementation 1236 * defined, in which case QEMU defaults to non-secure. 1237 */ 1238 return false; 1239 } 1240 } 1241 1242 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1243 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1244 { 1245 if (arm_feature(env, ARM_FEATURE_EL3)) { 1246 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1247 /* CPU currently in AArch64 state and EL3 */ 1248 return true; 1249 } else if (!is_a64(env) && 1250 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1251 /* CPU currently in AArch32 state and monitor mode */ 1252 return true; 1253 } 1254 } 1255 return false; 1256 } 1257 1258 /* Return true if the processor is in secure state */ 1259 static inline bool arm_is_secure(CPUARMState *env) 1260 { 1261 if (arm_is_el3_or_mon(env)) { 1262 return true; 1263 } 1264 return arm_is_secure_below_el3(env); 1265 } 1266 1267 #else 1268 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1269 { 1270 return false; 1271 } 1272 1273 static inline bool arm_is_secure(CPUARMState *env) 1274 { 1275 return false; 1276 } 1277 #endif 1278 1279 /* Return true if the specified exception level is running in AArch64 state. */ 1280 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1281 { 1282 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1283 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1284 */ 1285 assert(el >= 1 && el <= 3); 1286 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1287 1288 /* The highest exception level is always at the maximum supported 1289 * register width, and then lower levels have a register width controlled 1290 * by bits in the SCR or HCR registers. 1291 */ 1292 if (el == 3) { 1293 return aa64; 1294 } 1295 1296 if (arm_feature(env, ARM_FEATURE_EL3)) { 1297 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1298 } 1299 1300 if (el == 2) { 1301 return aa64; 1302 } 1303 1304 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1305 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1306 } 1307 1308 return aa64; 1309 } 1310 1311 /* Function for determing whether guest cp register reads and writes should 1312 * access the secure or non-secure bank of a cp register. When EL3 is 1313 * operating in AArch32 state, the NS-bit determines whether the secure 1314 * instance of a cp register should be used. When EL3 is AArch64 (or if 1315 * it doesn't exist at all) then there is no register banking, and all 1316 * accesses are to the non-secure version. 1317 */ 1318 static inline bool access_secure_reg(CPUARMState *env) 1319 { 1320 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1321 !arm_el_is_aa64(env, 3) && 1322 !(env->cp15.scr_el3 & SCR_NS)); 1323 1324 return ret; 1325 } 1326 1327 /* Macros for accessing a specified CP register bank */ 1328 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1329 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1330 1331 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1332 do { \ 1333 if (_secure) { \ 1334 (_env)->cp15._regname##_s = (_val); \ 1335 } else { \ 1336 (_env)->cp15._regname##_ns = (_val); \ 1337 } \ 1338 } while (0) 1339 1340 /* Macros for automatically accessing a specific CP register bank depending on 1341 * the current secure state of the system. These macros are not intended for 1342 * supporting instruction translation reads/writes as these are dependent 1343 * solely on the SCR.NS bit and not the mode. 1344 */ 1345 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1346 A32_BANKED_REG_GET((_env), _regname, \ 1347 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1348 1349 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1350 A32_BANKED_REG_SET((_env), _regname, \ 1351 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1352 (_val)) 1353 1354 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1355 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1356 uint32_t cur_el, bool secure); 1357 1358 /* Interface between CPU and Interrupt controller. */ 1359 void armv7m_nvic_set_pending(void *opaque, int irq); 1360 int armv7m_nvic_acknowledge_irq(void *opaque); 1361 void armv7m_nvic_complete_irq(void *opaque, int irq); 1362 1363 /* Interface for defining coprocessor registers. 1364 * Registers are defined in tables of arm_cp_reginfo structs 1365 * which are passed to define_arm_cp_regs(). 1366 */ 1367 1368 /* When looking up a coprocessor register we look for it 1369 * via an integer which encodes all of: 1370 * coprocessor number 1371 * Crn, Crm, opc1, opc2 fields 1372 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1373 * or via MRRC/MCRR?) 1374 * non-secure/secure bank (AArch32 only) 1375 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1376 * (In this case crn and opc2 should be zero.) 1377 * For AArch64, there is no 32/64 bit size distinction; 1378 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1379 * and 4 bit CRn and CRm. The encoding patterns are chosen 1380 * to be easy to convert to and from the KVM encodings, and also 1381 * so that the hashtable can contain both AArch32 and AArch64 1382 * registers (to allow for interprocessing where we might run 1383 * 32 bit code on a 64 bit core). 1384 */ 1385 /* This bit is private to our hashtable cpreg; in KVM register 1386 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1387 * in the upper bits of the 64 bit ID. 1388 */ 1389 #define CP_REG_AA64_SHIFT 28 1390 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1391 1392 /* To enable banking of coprocessor registers depending on ns-bit we 1393 * add a bit to distinguish between secure and non-secure cpregs in the 1394 * hashtable. 1395 */ 1396 #define CP_REG_NS_SHIFT 29 1397 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1398 1399 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1400 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1401 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1402 1403 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1404 (CP_REG_AA64_MASK | \ 1405 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1406 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1407 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1408 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1409 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1410 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1411 1412 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1413 * version used as a key for the coprocessor register hashtable 1414 */ 1415 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1416 { 1417 uint32_t cpregid = kvmid; 1418 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1419 cpregid |= CP_REG_AA64_MASK; 1420 } else { 1421 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1422 cpregid |= (1 << 15); 1423 } 1424 1425 /* KVM is always non-secure so add the NS flag on AArch32 register 1426 * entries. 1427 */ 1428 cpregid |= 1 << CP_REG_NS_SHIFT; 1429 } 1430 return cpregid; 1431 } 1432 1433 /* Convert a truncated 32 bit hashtable key into the full 1434 * 64 bit KVM register ID. 1435 */ 1436 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1437 { 1438 uint64_t kvmid; 1439 1440 if (cpregid & CP_REG_AA64_MASK) { 1441 kvmid = cpregid & ~CP_REG_AA64_MASK; 1442 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1443 } else { 1444 kvmid = cpregid & ~(1 << 15); 1445 if (cpregid & (1 << 15)) { 1446 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1447 } else { 1448 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1449 } 1450 } 1451 return kvmid; 1452 } 1453 1454 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1455 * special-behaviour cp reg and bits [15..8] indicate what behaviour 1456 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1457 * TCG can assume the value to be constant (ie load at translate time) 1458 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1459 * indicates that the TB should not be ended after a write to this register 1460 * (the default is that the TB ends after cp writes). OVERRIDE permits 1461 * a register definition to override a previous definition for the 1462 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1463 * old must have the OVERRIDE bit set. 1464 * ALIAS indicates that this register is an alias view of some underlying 1465 * state which is also visible via another register, and that the other 1466 * register is handling migration and reset; registers marked ALIAS will not be 1467 * migrated but may have their state set by syncing of register state from KVM. 1468 * NO_RAW indicates that this register has no underlying state and does not 1469 * support raw access for state saving/loading; it will not be used for either 1470 * migration or KVM state synchronization. (Typically this is for "registers" 1471 * which are actually used as instructions for cache maintenance and so on.) 1472 * IO indicates that this register does I/O and therefore its accesses 1473 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1474 * registers which implement clocks or timers require this. 1475 */ 1476 #define ARM_CP_SPECIAL 1 1477 #define ARM_CP_CONST 2 1478 #define ARM_CP_64BIT 4 1479 #define ARM_CP_SUPPRESS_TB_END 8 1480 #define ARM_CP_OVERRIDE 16 1481 #define ARM_CP_ALIAS 32 1482 #define ARM_CP_IO 64 1483 #define ARM_CP_NO_RAW 128 1484 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) 1485 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) 1486 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) 1487 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) 1488 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) 1489 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1490 /* Used only as a terminator for ARMCPRegInfo lists */ 1491 #define ARM_CP_SENTINEL 0xffff 1492 /* Mask of only the flag bits in a type field */ 1493 #define ARM_CP_FLAG_MASK 0xff 1494 1495 /* Valid values for ARMCPRegInfo state field, indicating which of 1496 * the AArch32 and AArch64 execution states this register is visible in. 1497 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1498 * If the reginfo is declared to be visible in both states then a second 1499 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1500 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1501 * Note that we rely on the values of these enums as we iterate through 1502 * the various states in some places. 1503 */ 1504 enum { 1505 ARM_CP_STATE_AA32 = 0, 1506 ARM_CP_STATE_AA64 = 1, 1507 ARM_CP_STATE_BOTH = 2, 1508 }; 1509 1510 /* ARM CP register secure state flags. These flags identify security state 1511 * attributes for a given CP register entry. 1512 * The existence of both or neither secure and non-secure flags indicates that 1513 * the register has both a secure and non-secure hash entry. A single one of 1514 * these flags causes the register to only be hashed for the specified 1515 * security state. 1516 * Although definitions may have any combination of the S/NS bits, each 1517 * registered entry will only have one to identify whether the entry is secure 1518 * or non-secure. 1519 */ 1520 enum { 1521 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1522 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1523 }; 1524 1525 /* Return true if cptype is a valid type field. This is used to try to 1526 * catch errors where the sentinel has been accidentally left off the end 1527 * of a list of registers. 1528 */ 1529 static inline bool cptype_valid(int cptype) 1530 { 1531 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1532 || ((cptype & ARM_CP_SPECIAL) && 1533 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1534 } 1535 1536 /* Access rights: 1537 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1538 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1539 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1540 * (ie any of the privileged modes in Secure state, or Monitor mode). 1541 * If a register is accessible in one privilege level it's always accessible 1542 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1543 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1544 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1545 * terminology a little and call this PL3. 1546 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1547 * with the ELx exception levels. 1548 * 1549 * If access permissions for a register are more complex than can be 1550 * described with these bits, then use a laxer set of restrictions, and 1551 * do the more restrictive/complex check inside a helper function. 1552 */ 1553 #define PL3_R 0x80 1554 #define PL3_W 0x40 1555 #define PL2_R (0x20 | PL3_R) 1556 #define PL2_W (0x10 | PL3_W) 1557 #define PL1_R (0x08 | PL2_R) 1558 #define PL1_W (0x04 | PL2_W) 1559 #define PL0_R (0x02 | PL1_R) 1560 #define PL0_W (0x01 | PL1_W) 1561 1562 #define PL3_RW (PL3_R | PL3_W) 1563 #define PL2_RW (PL2_R | PL2_W) 1564 #define PL1_RW (PL1_R | PL1_W) 1565 #define PL0_RW (PL0_R | PL0_W) 1566 1567 /* Return the highest implemented Exception Level */ 1568 static inline int arm_highest_el(CPUARMState *env) 1569 { 1570 if (arm_feature(env, ARM_FEATURE_EL3)) { 1571 return 3; 1572 } 1573 if (arm_feature(env, ARM_FEATURE_EL2)) { 1574 return 2; 1575 } 1576 return 1; 1577 } 1578 1579 /* Return the current Exception Level (as per ARMv8; note that this differs 1580 * from the ARMv7 Privilege Level). 1581 */ 1582 static inline int arm_current_el(CPUARMState *env) 1583 { 1584 if (arm_feature(env, ARM_FEATURE_M)) { 1585 return !((env->v7m.exception == 0) && (env->v7m.control & 1)); 1586 } 1587 1588 if (is_a64(env)) { 1589 return extract32(env->pstate, 2, 2); 1590 } 1591 1592 switch (env->uncached_cpsr & 0x1f) { 1593 case ARM_CPU_MODE_USR: 1594 return 0; 1595 case ARM_CPU_MODE_HYP: 1596 return 2; 1597 case ARM_CPU_MODE_MON: 1598 return 3; 1599 default: 1600 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1601 /* If EL3 is 32-bit then all secure privileged modes run in 1602 * EL3 1603 */ 1604 return 3; 1605 } 1606 1607 return 1; 1608 } 1609 } 1610 1611 typedef struct ARMCPRegInfo ARMCPRegInfo; 1612 1613 typedef enum CPAccessResult { 1614 /* Access is permitted */ 1615 CP_ACCESS_OK = 0, 1616 /* Access fails due to a configurable trap or enable which would 1617 * result in a categorized exception syndrome giving information about 1618 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1619 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1620 * PL1 if in EL0, otherwise to the current EL). 1621 */ 1622 CP_ACCESS_TRAP = 1, 1623 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1624 * Note that this is not a catch-all case -- the set of cases which may 1625 * result in this failure is specifically defined by the architecture. 1626 */ 1627 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 1628 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 1629 CP_ACCESS_TRAP_EL2 = 3, 1630 CP_ACCESS_TRAP_EL3 = 4, 1631 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 1632 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 1633 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 1634 /* Access fails and results in an exception syndrome for an FP access, 1635 * trapped directly to EL2 or EL3 1636 */ 1637 CP_ACCESS_TRAP_FP_EL2 = 7, 1638 CP_ACCESS_TRAP_FP_EL3 = 8, 1639 } CPAccessResult; 1640 1641 /* Access functions for coprocessor registers. These cannot fail and 1642 * may not raise exceptions. 1643 */ 1644 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1645 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 1646 uint64_t value); 1647 /* Access permission check functions for coprocessor registers. */ 1648 typedef CPAccessResult CPAccessFn(CPUARMState *env, 1649 const ARMCPRegInfo *opaque, 1650 bool isread); 1651 /* Hook function for register reset */ 1652 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1653 1654 #define CP_ANY 0xff 1655 1656 /* Definition of an ARM coprocessor register */ 1657 struct ARMCPRegInfo { 1658 /* Name of register (useful mainly for debugging, need not be unique) */ 1659 const char *name; 1660 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 1661 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 1662 * 'wildcard' field -- any value of that field in the MRC/MCR insn 1663 * will be decoded to this register. The register read and write 1664 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 1665 * used by the program, so it is possible to register a wildcard and 1666 * then behave differently on read/write if necessary. 1667 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 1668 * must both be zero. 1669 * For AArch64-visible registers, opc0 is also used. 1670 * Since there are no "coprocessors" in AArch64, cp is purely used as a 1671 * way to distinguish (for KVM's benefit) guest-visible system registers 1672 * from demuxed ones provided to preserve the "no side effects on 1673 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 1674 * visible (to match KVM's encoding); cp==0 will be converted to 1675 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 1676 */ 1677 uint8_t cp; 1678 uint8_t crn; 1679 uint8_t crm; 1680 uint8_t opc0; 1681 uint8_t opc1; 1682 uint8_t opc2; 1683 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 1684 int state; 1685 /* Register type: ARM_CP_* bits/values */ 1686 int type; 1687 /* Access rights: PL*_[RW] */ 1688 int access; 1689 /* Security state: ARM_CP_SECSTATE_* bits/values */ 1690 int secure; 1691 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 1692 * this register was defined: can be used to hand data through to the 1693 * register read/write functions, since they are passed the ARMCPRegInfo*. 1694 */ 1695 void *opaque; 1696 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 1697 * fieldoffset is non-zero, the reset value of the register. 1698 */ 1699 uint64_t resetvalue; 1700 /* Offset of the field in CPUARMState for this register. 1701 * 1702 * This is not needed if either: 1703 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 1704 * 2. both readfn and writefn are specified 1705 */ 1706 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 1707 1708 /* Offsets of the secure and non-secure fields in CPUARMState for the 1709 * register if it is banked. These fields are only used during the static 1710 * registration of a register. During hashing the bank associated 1711 * with a given security state is copied to fieldoffset which is used from 1712 * there on out. 1713 * 1714 * It is expected that register definitions use either fieldoffset or 1715 * bank_fieldoffsets in the definition but not both. It is also expected 1716 * that both bank offsets are set when defining a banked register. This 1717 * use indicates that a register is banked. 1718 */ 1719 ptrdiff_t bank_fieldoffsets[2]; 1720 1721 /* Function for making any access checks for this register in addition to 1722 * those specified by the 'access' permissions bits. If NULL, no extra 1723 * checks required. The access check is performed at runtime, not at 1724 * translate time. 1725 */ 1726 CPAccessFn *accessfn; 1727 /* Function for handling reads of this register. If NULL, then reads 1728 * will be done by loading from the offset into CPUARMState specified 1729 * by fieldoffset. 1730 */ 1731 CPReadFn *readfn; 1732 /* Function for handling writes of this register. If NULL, then writes 1733 * will be done by writing to the offset into CPUARMState specified 1734 * by fieldoffset. 1735 */ 1736 CPWriteFn *writefn; 1737 /* Function for doing a "raw" read; used when we need to copy 1738 * coprocessor state to the kernel for KVM or out for 1739 * migration. This only needs to be provided if there is also a 1740 * readfn and it has side effects (for instance clear-on-read bits). 1741 */ 1742 CPReadFn *raw_readfn; 1743 /* Function for doing a "raw" write; used when we need to copy KVM 1744 * kernel coprocessor state into userspace, or for inbound 1745 * migration. This only needs to be provided if there is also a 1746 * writefn and it masks out "unwritable" bits or has write-one-to-clear 1747 * or similar behaviour. 1748 */ 1749 CPWriteFn *raw_writefn; 1750 /* Function for resetting the register. If NULL, then reset will be done 1751 * by writing resetvalue to the field specified in fieldoffset. If 1752 * fieldoffset is 0 then no reset will be done. 1753 */ 1754 CPResetFn *resetfn; 1755 }; 1756 1757 /* Macros which are lvalues for the field in CPUARMState for the 1758 * ARMCPRegInfo *ri. 1759 */ 1760 #define CPREG_FIELD32(env, ri) \ 1761 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 1762 #define CPREG_FIELD64(env, ri) \ 1763 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 1764 1765 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 1766 1767 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 1768 const ARMCPRegInfo *regs, void *opaque); 1769 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 1770 const ARMCPRegInfo *regs, void *opaque); 1771 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 1772 { 1773 define_arm_cp_regs_with_opaque(cpu, regs, 0); 1774 } 1775 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 1776 { 1777 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 1778 } 1779 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 1780 1781 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 1782 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 1783 uint64_t value); 1784 /* CPReadFn that can be used for read-as-zero behaviour */ 1785 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 1786 1787 /* CPResetFn that does nothing, for use if no reset is required even 1788 * if fieldoffset is non zero. 1789 */ 1790 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 1791 1792 /* Return true if this reginfo struct's field in the cpu state struct 1793 * is 64 bits wide. 1794 */ 1795 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 1796 { 1797 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 1798 } 1799 1800 static inline bool cp_access_ok(int current_el, 1801 const ARMCPRegInfo *ri, int isread) 1802 { 1803 return (ri->access >> ((current_el * 2) + isread)) & 1; 1804 } 1805 1806 /* Raw read of a coprocessor register (as needed for migration, etc) */ 1807 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 1808 1809 /** 1810 * write_list_to_cpustate 1811 * @cpu: ARMCPU 1812 * 1813 * For each register listed in the ARMCPU cpreg_indexes list, write 1814 * its value from the cpreg_values list into the ARMCPUState structure. 1815 * This updates TCG's working data structures from KVM data or 1816 * from incoming migration state. 1817 * 1818 * Returns: true if all register values were updated correctly, 1819 * false if some register was unknown or could not be written. 1820 * Note that we do not stop early on failure -- we will attempt 1821 * writing all registers in the list. 1822 */ 1823 bool write_list_to_cpustate(ARMCPU *cpu); 1824 1825 /** 1826 * write_cpustate_to_list: 1827 * @cpu: ARMCPU 1828 * 1829 * For each register listed in the ARMCPU cpreg_indexes list, write 1830 * its value from the ARMCPUState structure into the cpreg_values list. 1831 * This is used to copy info from TCG's working data structures into 1832 * KVM or for outbound migration. 1833 * 1834 * Returns: true if all register values were read correctly, 1835 * false if some register was unknown or could not be read. 1836 * Note that we do not stop early on failure -- we will attempt 1837 * reading all registers in the list. 1838 */ 1839 bool write_cpustate_to_list(ARMCPU *cpu); 1840 1841 #define ARM_CPUID_TI915T 0x54029152 1842 #define ARM_CPUID_TI925T 0x54029252 1843 1844 #if defined(CONFIG_USER_ONLY) 1845 #define TARGET_PAGE_BITS 12 1846 #else 1847 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 1848 * have to support 1K tiny pages. 1849 */ 1850 #define TARGET_PAGE_BITS_VARY 1851 #define TARGET_PAGE_BITS_MIN 10 1852 #endif 1853 1854 #if defined(TARGET_AARCH64) 1855 # define TARGET_PHYS_ADDR_SPACE_BITS 48 1856 # define TARGET_VIRT_ADDR_SPACE_BITS 64 1857 #else 1858 # define TARGET_PHYS_ADDR_SPACE_BITS 40 1859 # define TARGET_VIRT_ADDR_SPACE_BITS 32 1860 #endif 1861 1862 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 1863 unsigned int target_el) 1864 { 1865 CPUARMState *env = cs->env_ptr; 1866 unsigned int cur_el = arm_current_el(env); 1867 bool secure = arm_is_secure(env); 1868 bool pstate_unmasked; 1869 int8_t unmasked = 0; 1870 1871 /* Don't take exceptions if they target a lower EL. 1872 * This check should catch any exceptions that would not be taken but left 1873 * pending. 1874 */ 1875 if (cur_el > target_el) { 1876 return false; 1877 } 1878 1879 switch (excp_idx) { 1880 case EXCP_FIQ: 1881 pstate_unmasked = !(env->daif & PSTATE_F); 1882 break; 1883 1884 case EXCP_IRQ: 1885 pstate_unmasked = !(env->daif & PSTATE_I); 1886 break; 1887 1888 case EXCP_VFIQ: 1889 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 1890 /* VFIQs are only taken when hypervized and non-secure. */ 1891 return false; 1892 } 1893 return !(env->daif & PSTATE_F); 1894 case EXCP_VIRQ: 1895 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 1896 /* VIRQs are only taken when hypervized and non-secure. */ 1897 return false; 1898 } 1899 return !(env->daif & PSTATE_I); 1900 default: 1901 g_assert_not_reached(); 1902 } 1903 1904 /* Use the target EL, current execution state and SCR/HCR settings to 1905 * determine whether the corresponding CPSR bit is used to mask the 1906 * interrupt. 1907 */ 1908 if ((target_el > cur_el) && (target_el != 1)) { 1909 /* Exceptions targeting a higher EL may not be maskable */ 1910 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 1911 /* 64-bit masking rules are simple: exceptions to EL3 1912 * can't be masked, and exceptions to EL2 can only be 1913 * masked from Secure state. The HCR and SCR settings 1914 * don't affect the masking logic, only the interrupt routing. 1915 */ 1916 if (target_el == 3 || !secure) { 1917 unmasked = 1; 1918 } 1919 } else { 1920 /* The old 32-bit-only environment has a more complicated 1921 * masking setup. HCR and SCR bits not only affect interrupt 1922 * routing but also change the behaviour of masking. 1923 */ 1924 bool hcr, scr; 1925 1926 switch (excp_idx) { 1927 case EXCP_FIQ: 1928 /* If FIQs are routed to EL3 or EL2 then there are cases where 1929 * we override the CPSR.F in determining if the exception is 1930 * masked or not. If neither of these are set then we fall back 1931 * to the CPSR.F setting otherwise we further assess the state 1932 * below. 1933 */ 1934 hcr = (env->cp15.hcr_el2 & HCR_FMO); 1935 scr = (env->cp15.scr_el3 & SCR_FIQ); 1936 1937 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 1938 * CPSR.F bit masks FIQ interrupts when taken in non-secure 1939 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 1940 * when non-secure but only when FIQs are only routed to EL3. 1941 */ 1942 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 1943 break; 1944 case EXCP_IRQ: 1945 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 1946 * we may override the CPSR.I masking when in non-secure state. 1947 * The SCR.IRQ setting has already been taken into consideration 1948 * when setting the target EL, so it does not have a further 1949 * affect here. 1950 */ 1951 hcr = (env->cp15.hcr_el2 & HCR_IMO); 1952 scr = false; 1953 break; 1954 default: 1955 g_assert_not_reached(); 1956 } 1957 1958 if ((scr || hcr) && !secure) { 1959 unmasked = 1; 1960 } 1961 } 1962 } 1963 1964 /* The PSTATE bits only mask the interrupt if we have not overriden the 1965 * ability above. 1966 */ 1967 return unmasked || pstate_unmasked; 1968 } 1969 1970 #define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model)) 1971 1972 #define cpu_signal_handler cpu_arm_signal_handler 1973 #define cpu_list arm_cpu_list 1974 1975 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 1976 * 1977 * If EL3 is 64-bit: 1978 * + NonSecure EL1 & 0 stage 1 1979 * + NonSecure EL1 & 0 stage 2 1980 * + NonSecure EL2 1981 * + Secure EL1 & EL0 1982 * + Secure EL3 1983 * If EL3 is 32-bit: 1984 * + NonSecure PL1 & 0 stage 1 1985 * + NonSecure PL1 & 0 stage 2 1986 * + NonSecure PL2 1987 * + Secure PL0 & PL1 1988 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 1989 * 1990 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 1991 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 1992 * may differ in access permissions even if the VA->PA map is the same 1993 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 1994 * translation, which means that we have one mmu_idx that deals with two 1995 * concatenated translation regimes [this sort of combined s1+2 TLB is 1996 * architecturally permitted] 1997 * 3. we don't need to allocate an mmu_idx to translations that we won't be 1998 * handling via the TLB. The only way to do a stage 1 translation without 1999 * the immediate stage 2 translation is via the ATS or AT system insns, 2000 * which can be slow-pathed and always do a page table walk. 2001 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2002 * translation regimes, because they map reasonably well to each other 2003 * and they can't both be active at the same time. 2004 * This gives us the following list of mmu_idx values: 2005 * 2006 * NS EL0 (aka NS PL0) stage 1+2 2007 * NS EL1 (aka NS PL1) stage 1+2 2008 * NS EL2 (aka NS PL2) 2009 * S EL3 (aka S PL1) 2010 * S EL0 (aka S PL0) 2011 * S EL1 (not used if EL3 is 32 bit) 2012 * NS EL0+1 stage 2 2013 * 2014 * (The last of these is an mmu_idx because we want to be able to use the TLB 2015 * for the accesses done as part of a stage 1 page table walk, rather than 2016 * having to walk the stage 2 page table over and over.) 2017 * 2018 * Our enumeration includes at the end some entries which are not "true" 2019 * mmu_idx values in that they don't have corresponding TLBs and are only 2020 * valid for doing slow path page table walks. 2021 * 2022 * The constant names here are patterned after the general style of the names 2023 * of the AT/ATS operations. 2024 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2025 */ 2026 typedef enum ARMMMUIdx { 2027 ARMMMUIdx_S12NSE0 = 0, 2028 ARMMMUIdx_S12NSE1 = 1, 2029 ARMMMUIdx_S1E2 = 2, 2030 ARMMMUIdx_S1E3 = 3, 2031 ARMMMUIdx_S1SE0 = 4, 2032 ARMMMUIdx_S1SE1 = 5, 2033 ARMMMUIdx_S2NS = 6, 2034 /* Indexes below here don't have TLBs and are used only for AT system 2035 * instructions or for the first stage of an S12 page table walk. 2036 */ 2037 ARMMMUIdx_S1NSE0 = 7, 2038 ARMMMUIdx_S1NSE1 = 8, 2039 } ARMMMUIdx; 2040 2041 #define MMU_USER_IDX 0 2042 2043 /* Return the exception level we're running at if this is our mmu_idx */ 2044 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2045 { 2046 assert(mmu_idx < ARMMMUIdx_S2NS); 2047 return mmu_idx & 3; 2048 } 2049 2050 /* Determine the current mmu_idx to use for normal loads/stores */ 2051 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2052 { 2053 int el = arm_current_el(env); 2054 2055 if (el < 2 && arm_is_secure_below_el3(env)) { 2056 return ARMMMUIdx_S1SE0 + el; 2057 } 2058 return el; 2059 } 2060 2061 /* Indexes used when registering address spaces with cpu_address_space_init */ 2062 typedef enum ARMASIdx { 2063 ARMASIdx_NS = 0, 2064 ARMASIdx_S = 1, 2065 } ARMASIdx; 2066 2067 /* Return the Exception Level targeted by debug exceptions. */ 2068 static inline int arm_debug_target_el(CPUARMState *env) 2069 { 2070 bool secure = arm_is_secure(env); 2071 bool route_to_el2 = false; 2072 2073 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2074 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2075 env->cp15.mdcr_el2 & (1 << 8); 2076 } 2077 2078 if (route_to_el2) { 2079 return 2; 2080 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2081 !arm_el_is_aa64(env, 3) && secure) { 2082 return 3; 2083 } else { 2084 return 1; 2085 } 2086 } 2087 2088 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2089 { 2090 if (arm_is_secure(env)) { 2091 /* MDCR_EL3.SDD disables debug events from Secure state */ 2092 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2093 || arm_current_el(env) == 3) { 2094 return false; 2095 } 2096 } 2097 2098 if (arm_current_el(env) == arm_debug_target_el(env)) { 2099 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2100 || (env->daif & PSTATE_D)) { 2101 return false; 2102 } 2103 } 2104 return true; 2105 } 2106 2107 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2108 { 2109 int el = arm_current_el(env); 2110 2111 if (el == 0 && arm_el_is_aa64(env, 1)) { 2112 return aa64_generate_debug_exceptions(env); 2113 } 2114 2115 if (arm_is_secure(env)) { 2116 int spd; 2117 2118 if (el == 0 && (env->cp15.sder & 1)) { 2119 /* SDER.SUIDEN means debug exceptions from Secure EL0 2120 * are always enabled. Otherwise they are controlled by 2121 * SDCR.SPD like those from other Secure ELs. 2122 */ 2123 return true; 2124 } 2125 2126 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2127 switch (spd) { 2128 case 1: 2129 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2130 case 0: 2131 /* For 0b00 we return true if external secure invasive debug 2132 * is enabled. On real hardware this is controlled by external 2133 * signals to the core. QEMU always permits debug, and behaves 2134 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2135 */ 2136 return true; 2137 case 2: 2138 return false; 2139 case 3: 2140 return true; 2141 } 2142 } 2143 2144 return el != 2; 2145 } 2146 2147 /* Return true if debugging exceptions are currently enabled. 2148 * This corresponds to what in ARM ARM pseudocode would be 2149 * if UsingAArch32() then 2150 * return AArch32.GenerateDebugExceptions() 2151 * else 2152 * return AArch64.GenerateDebugExceptions() 2153 * We choose to push the if() down into this function for clarity, 2154 * since the pseudocode has it at all callsites except for the one in 2155 * CheckSoftwareStep(), where it is elided because both branches would 2156 * always return the same value. 2157 * 2158 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2159 * don't yet implement those exception levels or their associated trap bits. 2160 */ 2161 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2162 { 2163 if (env->aarch64) { 2164 return aa64_generate_debug_exceptions(env); 2165 } else { 2166 return aa32_generate_debug_exceptions(env); 2167 } 2168 } 2169 2170 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2171 * implicitly means this always returns false in pre-v8 CPUs.) 2172 */ 2173 static inline bool arm_singlestep_active(CPUARMState *env) 2174 { 2175 return extract32(env->cp15.mdscr_el1, 0, 1) 2176 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2177 && arm_generate_debug_exceptions(env); 2178 } 2179 2180 static inline bool arm_sctlr_b(CPUARMState *env) 2181 { 2182 return 2183 /* We need not implement SCTLR.ITD in user-mode emulation, so 2184 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2185 * This lets people run BE32 binaries with "-cpu any". 2186 */ 2187 #ifndef CONFIG_USER_ONLY 2188 !arm_feature(env, ARM_FEATURE_V7) && 2189 #endif 2190 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2191 } 2192 2193 /* Return true if the processor is in big-endian mode. */ 2194 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2195 { 2196 int cur_el; 2197 2198 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2199 if (!is_a64(env)) { 2200 return 2201 #ifdef CONFIG_USER_ONLY 2202 /* In system mode, BE32 is modelled in line with the 2203 * architecture (as word-invariant big-endianness), where loads 2204 * and stores are done little endian but from addresses which 2205 * are adjusted by XORing with the appropriate constant. So the 2206 * endianness to use for the raw data access is not affected by 2207 * SCTLR.B. 2208 * In user mode, however, we model BE32 as byte-invariant 2209 * big-endianness (because user-only code cannot tell the 2210 * difference), and so we need to use a data access endianness 2211 * that depends on SCTLR.B. 2212 */ 2213 arm_sctlr_b(env) || 2214 #endif 2215 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2216 } 2217 2218 cur_el = arm_current_el(env); 2219 2220 if (cur_el == 0) { 2221 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2222 } 2223 2224 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2225 } 2226 2227 #include "exec/cpu-all.h" 2228 2229 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2230 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2231 * We put flags which are shared between 32 and 64 bit mode at the top 2232 * of the word, and flags which apply to only one mode at the bottom. 2233 */ 2234 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2235 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2236 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2237 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2238 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2239 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2240 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2241 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2242 /* Target EL if we take a floating-point-disabled exception */ 2243 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2244 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2245 2246 /* Bit usage when in AArch32 state: */ 2247 #define ARM_TBFLAG_THUMB_SHIFT 0 2248 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2249 #define ARM_TBFLAG_VECLEN_SHIFT 1 2250 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2251 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2252 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2253 #define ARM_TBFLAG_VFPEN_SHIFT 7 2254 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2255 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2256 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2257 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2258 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2259 /* We store the bottom two bits of the CPAR as TB flags and handle 2260 * checks on the other bits at runtime 2261 */ 2262 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2263 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2264 /* Indicates whether cp register reads and writes by guest code should access 2265 * the secure or nonsecure bank of banked registers; note that this is not 2266 * the same thing as the current security state of the processor! 2267 */ 2268 #define ARM_TBFLAG_NS_SHIFT 19 2269 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2270 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2271 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2272 2273 /* Bit usage when in AArch64 state */ 2274 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2275 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2276 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2277 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2278 2279 /* some convenience accessor macros */ 2280 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2281 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2282 #define ARM_TBFLAG_MMUIDX(F) \ 2283 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2284 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2285 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2286 #define ARM_TBFLAG_PSTATE_SS(F) \ 2287 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2288 #define ARM_TBFLAG_FPEXC_EL(F) \ 2289 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2290 #define ARM_TBFLAG_THUMB(F) \ 2291 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2292 #define ARM_TBFLAG_VECLEN(F) \ 2293 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2294 #define ARM_TBFLAG_VECSTRIDE(F) \ 2295 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2296 #define ARM_TBFLAG_VFPEN(F) \ 2297 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2298 #define ARM_TBFLAG_CONDEXEC(F) \ 2299 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2300 #define ARM_TBFLAG_SCTLR_B(F) \ 2301 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2302 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2303 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2304 #define ARM_TBFLAG_NS(F) \ 2305 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2306 #define ARM_TBFLAG_BE_DATA(F) \ 2307 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2308 #define ARM_TBFLAG_TBI0(F) \ 2309 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2310 #define ARM_TBFLAG_TBI1(F) \ 2311 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2312 2313 static inline bool bswap_code(bool sctlr_b) 2314 { 2315 #ifdef CONFIG_USER_ONLY 2316 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2317 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2318 * would also end up as a mixed-endian mode with BE code, LE data. 2319 */ 2320 return 2321 #ifdef TARGET_WORDS_BIGENDIAN 2322 1 ^ 2323 #endif 2324 sctlr_b; 2325 #else 2326 /* All code access in ARM is little endian, and there are no loaders 2327 * doing swaps that need to be reversed 2328 */ 2329 return 0; 2330 #endif 2331 } 2332 2333 /* Return the exception level to which FP-disabled exceptions should 2334 * be taken, or 0 if FP is enabled. 2335 */ 2336 static inline int fp_exception_el(CPUARMState *env) 2337 { 2338 int fpen; 2339 int cur_el = arm_current_el(env); 2340 2341 /* CPACR and the CPTR registers don't exist before v6, so FP is 2342 * always accessible 2343 */ 2344 if (!arm_feature(env, ARM_FEATURE_V6)) { 2345 return 0; 2346 } 2347 2348 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: 2349 * 0, 2 : trap EL0 and EL1/PL1 accesses 2350 * 1 : trap only EL0 accesses 2351 * 3 : trap no accesses 2352 */ 2353 fpen = extract32(env->cp15.cpacr_el1, 20, 2); 2354 switch (fpen) { 2355 case 0: 2356 case 2: 2357 if (cur_el == 0 || cur_el == 1) { 2358 /* Trap to PL1, which might be EL1 or EL3 */ 2359 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2360 return 3; 2361 } 2362 return 1; 2363 } 2364 if (cur_el == 3 && !is_a64(env)) { 2365 /* Secure PL1 running at EL3 */ 2366 return 3; 2367 } 2368 break; 2369 case 1: 2370 if (cur_el == 0) { 2371 return 1; 2372 } 2373 break; 2374 case 3: 2375 break; 2376 } 2377 2378 /* For the CPTR registers we don't need to guard with an ARM_FEATURE 2379 * check because zero bits in the registers mean "don't trap". 2380 */ 2381 2382 /* CPTR_EL2 : present in v7VE or v8 */ 2383 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) 2384 && !arm_is_secure_below_el3(env)) { 2385 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ 2386 return 2; 2387 } 2388 2389 /* CPTR_EL3 : present in v8 */ 2390 if (extract32(env->cp15.cptr_el[3], 10, 1)) { 2391 /* Trap all FP ops to EL3 */ 2392 return 3; 2393 } 2394 2395 return 0; 2396 } 2397 2398 #ifdef CONFIG_USER_ONLY 2399 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2400 { 2401 return 2402 #ifdef TARGET_WORDS_BIGENDIAN 2403 1 ^ 2404 #endif 2405 arm_cpu_data_is_big_endian(env); 2406 } 2407 #endif 2408 2409 #ifndef CONFIG_USER_ONLY 2410 /** 2411 * arm_regime_tbi0: 2412 * @env: CPUARMState 2413 * @mmu_idx: MMU index indicating required translation regime 2414 * 2415 * Extracts the TBI0 value from the appropriate TCR for the current EL 2416 * 2417 * Returns: the TBI0 value. 2418 */ 2419 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2420 2421 /** 2422 * arm_regime_tbi1: 2423 * @env: CPUARMState 2424 * @mmu_idx: MMU index indicating required translation regime 2425 * 2426 * Extracts the TBI1 value from the appropriate TCR for the current EL 2427 * 2428 * Returns: the TBI1 value. 2429 */ 2430 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2431 #else 2432 /* We can't handle tagged addresses properly in user-only mode */ 2433 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2434 { 2435 return 0; 2436 } 2437 2438 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2439 { 2440 return 0; 2441 } 2442 #endif 2443 2444 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2445 target_ulong *cs_base, uint32_t *flags) 2446 { 2447 ARMMMUIdx mmu_idx = cpu_mmu_index(env, false); 2448 if (is_a64(env)) { 2449 *pc = env->pc; 2450 *flags = ARM_TBFLAG_AARCH64_STATE_MASK; 2451 /* Get control bits for tagged addresses */ 2452 *flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); 2453 *flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); 2454 } else { 2455 *pc = env->regs[15]; 2456 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) 2457 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) 2458 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) 2459 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) 2460 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); 2461 if (!(access_secure_reg(env))) { 2462 *flags |= ARM_TBFLAG_NS_MASK; 2463 } 2464 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) 2465 || arm_el_is_aa64(env, 1)) { 2466 *flags |= ARM_TBFLAG_VFPEN_MASK; 2467 } 2468 *flags |= (extract32(env->cp15.c15_cpar, 0, 2) 2469 << ARM_TBFLAG_XSCALE_CPAR_SHIFT); 2470 } 2471 2472 *flags |= (mmu_idx << ARM_TBFLAG_MMUIDX_SHIFT); 2473 2474 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine 2475 * states defined in the ARM ARM for software singlestep: 2476 * SS_ACTIVE PSTATE.SS State 2477 * 0 x Inactive (the TB flag for SS is always 0) 2478 * 1 0 Active-pending 2479 * 1 1 Active-not-pending 2480 */ 2481 if (arm_singlestep_active(env)) { 2482 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; 2483 if (is_a64(env)) { 2484 if (env->pstate & PSTATE_SS) { 2485 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2486 } 2487 } else { 2488 if (env->uncached_cpsr & PSTATE_SS) { 2489 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2490 } 2491 } 2492 } 2493 if (arm_cpu_data_is_big_endian(env)) { 2494 *flags |= ARM_TBFLAG_BE_DATA_MASK; 2495 } 2496 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; 2497 2498 *cs_base = 0; 2499 } 2500 2501 enum { 2502 QEMU_PSCI_CONDUIT_DISABLED = 0, 2503 QEMU_PSCI_CONDUIT_SMC = 1, 2504 QEMU_PSCI_CONDUIT_HVC = 2, 2505 }; 2506 2507 #ifndef CONFIG_USER_ONLY 2508 /* Return the address space index to use for a memory access */ 2509 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2510 { 2511 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2512 } 2513 2514 /* Return the AddressSpace to use for a memory access 2515 * (which depends on whether the access is S or NS, and whether 2516 * the board gave us a separate AddressSpace for S accesses). 2517 */ 2518 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2519 { 2520 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2521 } 2522 #endif 2523 2524 /** 2525 * arm_register_el_change_hook: 2526 * Register a hook function which will be called back whenever this 2527 * CPU changes exception level or mode. The hook function will be 2528 * passed a pointer to the ARMCPU and the opaque data pointer passed 2529 * to this function when the hook was registered. 2530 * 2531 * Note that we currently only support registering a single hook function, 2532 * and will assert if this function is called twice. 2533 * This facility is intended for the use of the GICv3 emulation. 2534 */ 2535 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 2536 void *opaque); 2537 2538 /** 2539 * arm_get_el_change_hook_opaque: 2540 * Return the opaque data that will be used by the el_change_hook 2541 * for this CPU. 2542 */ 2543 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) 2544 { 2545 return cpu->el_change_hook_opaque; 2546 } 2547 2548 #endif 2549