1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 #define VTCR_NSW (1u << 29) 170 #define VTCR_NSA (1u << 30) 171 #define VSTCR_SW VTCR_NSW 172 #define VSTCR_SA VTCR_NSA 173 174 /* Define a maximum sized vector register. 175 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 176 * For 64-bit, this is a 2048-bit SVE register. 177 * 178 * Note that the mapping between S, D, and Q views of the register bank 179 * differs between AArch64 and AArch32. 180 * In AArch32: 181 * Qn = regs[n].d[1]:regs[n].d[0] 182 * Dn = regs[n / 2].d[n & 1] 183 * Sn = regs[n / 4].d[n % 4 / 2], 184 * bits 31..0 for even n, and bits 63..32 for odd n 185 * (and regs[16] to regs[31] are inaccessible) 186 * In AArch64: 187 * Zn = regs[n].d[*] 188 * Qn = regs[n].d[1]:regs[n].d[0] 189 * Dn = regs[n].d[0] 190 * Sn = regs[n].d[0] bits 31..0 191 * Hn = regs[n].d[0] bits 15..0 192 * 193 * This corresponds to the architecturally defined mapping between 194 * the two execution states, and means we do not need to explicitly 195 * map these registers when changing states. 196 * 197 * Align the data for use with TCG host vector operations. 198 */ 199 200 #ifdef TARGET_AARCH64 201 # define ARM_MAX_VQ 16 202 #else 203 # define ARM_MAX_VQ 1 204 #endif 205 206 typedef struct ARMVectorReg { 207 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 208 } ARMVectorReg; 209 210 #ifdef TARGET_AARCH64 211 /* In AArch32 mode, predicate registers do not exist at all. */ 212 typedef struct ARMPredicateReg { 213 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 214 } ARMPredicateReg; 215 216 /* In AArch32 mode, PAC keys do not exist at all. */ 217 typedef struct ARMPACKey { 218 uint64_t lo, hi; 219 } ARMPACKey; 220 #endif 221 222 /* See the commentary above the TBFLAG field definitions. */ 223 typedef struct CPUARMTBFlags { 224 uint32_t flags; 225 target_ulong flags2; 226 } CPUARMTBFlags; 227 228 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 229 230 typedef struct CPUArchState { 231 /* Regs for current mode. */ 232 uint32_t regs[16]; 233 234 /* 32/64 switch only happens when taking and returning from 235 * exceptions so the overlap semantics are taken care of then 236 * instead of having a complicated union. 237 */ 238 /* Regs for A64 mode. */ 239 uint64_t xregs[32]; 240 uint64_t pc; 241 /* PSTATE isn't an architectural register for ARMv8. However, it is 242 * convenient for us to assemble the underlying state into a 32 bit format 243 * identical to the architectural format used for the SPSR. (This is also 244 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 245 * 'pstate' register are.) Of the PSTATE bits: 246 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 247 * semantics as for AArch32, as described in the comments on each field) 248 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 249 * DAIF (exception masks) are kept in env->daif 250 * BTYPE is kept in env->btype 251 * SM and ZA are kept in env->svcr 252 * all other bits are stored in their correct places in env->pstate 253 */ 254 uint32_t pstate; 255 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 256 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 257 258 /* Cached TBFLAGS state. See below for which bits are included. */ 259 CPUARMTBFlags hflags; 260 261 /* Frequently accessed CPSR bits are stored separately for efficiency. 262 This contains all the other bits. Use cpsr_{read,write} to access 263 the whole CPSR. */ 264 uint32_t uncached_cpsr; 265 uint32_t spsr; 266 267 /* Banked registers. */ 268 uint64_t banked_spsr[8]; 269 uint32_t banked_r13[8]; 270 uint32_t banked_r14[8]; 271 272 /* These hold r8-r12. */ 273 uint32_t usr_regs[5]; 274 uint32_t fiq_regs[5]; 275 276 /* cpsr flag cache for faster execution */ 277 uint32_t CF; /* 0 or 1 */ 278 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 279 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 280 uint32_t ZF; /* Z set if zero. */ 281 uint32_t QF; /* 0 or 1 */ 282 uint32_t GE; /* cpsr[19:16] */ 283 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 284 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 285 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 286 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 287 288 uint64_t elr_el[4]; /* AArch64 exception link regs */ 289 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 290 291 /* System control coprocessor (cp15) */ 292 struct { 293 uint32_t c0_cpuid; 294 union { /* Cache size selection */ 295 struct { 296 uint64_t _unused_csselr0; 297 uint64_t csselr_ns; 298 uint64_t _unused_csselr1; 299 uint64_t csselr_s; 300 }; 301 uint64_t csselr_el[4]; 302 }; 303 union { /* System control register. */ 304 struct { 305 uint64_t _unused_sctlr; 306 uint64_t sctlr_ns; 307 uint64_t hsctlr; 308 uint64_t sctlr_s; 309 }; 310 uint64_t sctlr_el[4]; 311 }; 312 uint64_t vsctlr; /* Virtualization System control register. */ 313 uint64_t cpacr_el1; /* Architectural feature access control register */ 314 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 315 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 316 uint64_t sder; /* Secure debug enable register. */ 317 uint32_t nsacr; /* Non-secure access control register. */ 318 union { /* MMU translation table base 0. */ 319 struct { 320 uint64_t _unused_ttbr0_0; 321 uint64_t ttbr0_ns; 322 uint64_t _unused_ttbr0_1; 323 uint64_t ttbr0_s; 324 }; 325 uint64_t ttbr0_el[4]; 326 }; 327 union { /* MMU translation table base 1. */ 328 struct { 329 uint64_t _unused_ttbr1_0; 330 uint64_t ttbr1_ns; 331 uint64_t _unused_ttbr1_1; 332 uint64_t ttbr1_s; 333 }; 334 uint64_t ttbr1_el[4]; 335 }; 336 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 337 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 338 /* MMU translation table base control. */ 339 uint64_t tcr_el[4]; 340 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 341 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 342 uint32_t c2_data; /* MPU data cacheable bits. */ 343 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 344 union { /* MMU domain access control register 345 * MPU write buffer control. 346 */ 347 struct { 348 uint64_t dacr_ns; 349 uint64_t dacr_s; 350 }; 351 struct { 352 uint64_t dacr32_el2; 353 }; 354 }; 355 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 356 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 357 uint64_t hcr_el2; /* Hypervisor configuration register */ 358 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 359 uint64_t scr_el3; /* Secure configuration register. */ 360 union { /* Fault status registers. */ 361 struct { 362 uint64_t ifsr_ns; 363 uint64_t ifsr_s; 364 }; 365 struct { 366 uint64_t ifsr32_el2; 367 }; 368 }; 369 union { 370 struct { 371 uint64_t _unused_dfsr; 372 uint64_t dfsr_ns; 373 uint64_t hsr; 374 uint64_t dfsr_s; 375 }; 376 uint64_t esr_el[4]; 377 }; 378 uint32_t c6_region[8]; /* MPU base/size registers. */ 379 union { /* Fault address registers. */ 380 struct { 381 uint64_t _unused_far0; 382 #if HOST_BIG_ENDIAN 383 uint32_t ifar_ns; 384 uint32_t dfar_ns; 385 uint32_t ifar_s; 386 uint32_t dfar_s; 387 #else 388 uint32_t dfar_ns; 389 uint32_t ifar_ns; 390 uint32_t dfar_s; 391 uint32_t ifar_s; 392 #endif 393 uint64_t _unused_far3; 394 }; 395 uint64_t far_el[4]; 396 }; 397 uint64_t hpfar_el2; 398 uint64_t hstr_el2; 399 union { /* Translation result. */ 400 struct { 401 uint64_t _unused_par_0; 402 uint64_t par_ns; 403 uint64_t _unused_par_1; 404 uint64_t par_s; 405 }; 406 uint64_t par_el[4]; 407 }; 408 409 uint32_t c9_insn; /* Cache lockdown registers. */ 410 uint32_t c9_data; 411 uint64_t c9_pmcr; /* performance monitor control register */ 412 uint64_t c9_pmcnten; /* perf monitor counter enables */ 413 uint64_t c9_pmovsr; /* perf monitor overflow status */ 414 uint64_t c9_pmuserenr; /* perf monitor user enable */ 415 uint64_t c9_pmselr; /* perf monitor counter selection register */ 416 uint64_t c9_pminten; /* perf monitor interrupt enables */ 417 union { /* Memory attribute redirection */ 418 struct { 419 #if HOST_BIG_ENDIAN 420 uint64_t _unused_mair_0; 421 uint32_t mair1_ns; 422 uint32_t mair0_ns; 423 uint64_t _unused_mair_1; 424 uint32_t mair1_s; 425 uint32_t mair0_s; 426 #else 427 uint64_t _unused_mair_0; 428 uint32_t mair0_ns; 429 uint32_t mair1_ns; 430 uint64_t _unused_mair_1; 431 uint32_t mair0_s; 432 uint32_t mair1_s; 433 #endif 434 }; 435 uint64_t mair_el[4]; 436 }; 437 union { /* vector base address register */ 438 struct { 439 uint64_t _unused_vbar; 440 uint64_t vbar_ns; 441 uint64_t hvbar; 442 uint64_t vbar_s; 443 }; 444 uint64_t vbar_el[4]; 445 }; 446 uint32_t mvbar; /* (monitor) vector base address register */ 447 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 448 struct { /* FCSE PID. */ 449 uint32_t fcseidr_ns; 450 uint32_t fcseidr_s; 451 }; 452 union { /* Context ID. */ 453 struct { 454 uint64_t _unused_contextidr_0; 455 uint64_t contextidr_ns; 456 uint64_t _unused_contextidr_1; 457 uint64_t contextidr_s; 458 }; 459 uint64_t contextidr_el[4]; 460 }; 461 union { /* User RW Thread register. */ 462 struct { 463 uint64_t tpidrurw_ns; 464 uint64_t tpidrprw_ns; 465 uint64_t htpidr; 466 uint64_t _tpidr_el3; 467 }; 468 uint64_t tpidr_el[4]; 469 }; 470 uint64_t tpidr2_el0; 471 /* The secure banks of these registers don't map anywhere */ 472 uint64_t tpidrurw_s; 473 uint64_t tpidrprw_s; 474 uint64_t tpidruro_s; 475 476 union { /* User RO Thread register. */ 477 uint64_t tpidruro_ns; 478 uint64_t tpidrro_el[1]; 479 }; 480 uint64_t c14_cntfrq; /* Counter Frequency register */ 481 uint64_t c14_cntkctl; /* Timer Control register */ 482 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 483 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 484 ARMGenericTimer c14_timer[NUM_GTIMERS]; 485 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 486 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 487 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 488 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 489 uint32_t c15_threadid; /* TI debugger thread-ID. */ 490 uint32_t c15_config_base_address; /* SCU base address. */ 491 uint32_t c15_diagnostic; /* diagnostic register */ 492 uint32_t c15_power_diagnostic; 493 uint32_t c15_power_control; /* power control */ 494 uint64_t dbgbvr[16]; /* breakpoint value registers */ 495 uint64_t dbgbcr[16]; /* breakpoint control registers */ 496 uint64_t dbgwvr[16]; /* watchpoint value registers */ 497 uint64_t dbgwcr[16]; /* watchpoint control registers */ 498 uint64_t mdscr_el1; 499 uint64_t oslsr_el1; /* OS Lock Status */ 500 uint64_t osdlr_el1; /* OS DoubleLock status */ 501 uint64_t mdcr_el2; 502 uint64_t mdcr_el3; 503 /* Stores the architectural value of the counter *the last time it was 504 * updated* by pmccntr_op_start. Accesses should always be surrounded 505 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 506 * architecturally-correct value is being read/set. 507 */ 508 uint64_t c15_ccnt; 509 /* Stores the delta between the architectural value and the underlying 510 * cycle count during normal operation. It is used to update c15_ccnt 511 * to be the correct architectural value before accesses. During 512 * accesses, c15_ccnt_delta contains the underlying count being used 513 * for the access, after which it reverts to the delta value in 514 * pmccntr_op_finish. 515 */ 516 uint64_t c15_ccnt_delta; 517 uint64_t c14_pmevcntr[31]; 518 uint64_t c14_pmevcntr_delta[31]; 519 uint64_t c14_pmevtyper[31]; 520 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 521 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 522 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 523 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 524 uint64_t gcr_el1; 525 uint64_t rgsr_el1; 526 527 /* Minimal RAS registers */ 528 uint64_t disr_el1; 529 uint64_t vdisr_el2; 530 uint64_t vsesr_el2; 531 } cp15; 532 533 struct { 534 /* M profile has up to 4 stack pointers: 535 * a Main Stack Pointer and a Process Stack Pointer for each 536 * of the Secure and Non-Secure states. (If the CPU doesn't support 537 * the security extension then it has only two SPs.) 538 * In QEMU we always store the currently active SP in regs[13], 539 * and the non-active SP for the current security state in 540 * v7m.other_sp. The stack pointers for the inactive security state 541 * are stored in other_ss_msp and other_ss_psp. 542 * switch_v7m_security_state() is responsible for rearranging them 543 * when we change security state. 544 */ 545 uint32_t other_sp; 546 uint32_t other_ss_msp; 547 uint32_t other_ss_psp; 548 uint32_t vecbase[M_REG_NUM_BANKS]; 549 uint32_t basepri[M_REG_NUM_BANKS]; 550 uint32_t control[M_REG_NUM_BANKS]; 551 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 552 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 553 uint32_t hfsr; /* HardFault Status */ 554 uint32_t dfsr; /* Debug Fault Status Register */ 555 uint32_t sfsr; /* Secure Fault Status Register */ 556 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 557 uint32_t bfar; /* BusFault Address */ 558 uint32_t sfar; /* Secure Fault Address Register */ 559 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 560 int exception; 561 uint32_t primask[M_REG_NUM_BANKS]; 562 uint32_t faultmask[M_REG_NUM_BANKS]; 563 uint32_t aircr; /* only holds r/w state if security extn implemented */ 564 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 565 uint32_t csselr[M_REG_NUM_BANKS]; 566 uint32_t scr[M_REG_NUM_BANKS]; 567 uint32_t msplim[M_REG_NUM_BANKS]; 568 uint32_t psplim[M_REG_NUM_BANKS]; 569 uint32_t fpcar[M_REG_NUM_BANKS]; 570 uint32_t fpccr[M_REG_NUM_BANKS]; 571 uint32_t fpdscr[M_REG_NUM_BANKS]; 572 uint32_t cpacr[M_REG_NUM_BANKS]; 573 uint32_t nsacr; 574 uint32_t ltpsize; 575 uint32_t vpr; 576 } v7m; 577 578 /* Information associated with an exception about to be taken: 579 * code which raises an exception must set cs->exception_index and 580 * the relevant parts of this structure; the cpu_do_interrupt function 581 * will then set the guest-visible registers as part of the exception 582 * entry process. 583 */ 584 struct { 585 uint32_t syndrome; /* AArch64 format syndrome register */ 586 uint32_t fsr; /* AArch32 format fault status register info */ 587 uint64_t vaddress; /* virtual addr associated with exception, if any */ 588 uint32_t target_el; /* EL the exception should be targeted for */ 589 /* If we implement EL2 we will also need to store information 590 * about the intermediate physical address for stage 2 faults. 591 */ 592 } exception; 593 594 /* Information associated with an SError */ 595 struct { 596 uint8_t pending; 597 uint8_t has_esr; 598 uint64_t esr; 599 } serror; 600 601 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 602 603 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 604 uint32_t irq_line_state; 605 606 /* Thumb-2 EE state. */ 607 uint32_t teecr; 608 uint32_t teehbr; 609 610 /* VFP coprocessor state. */ 611 struct { 612 ARMVectorReg zregs[32]; 613 614 #ifdef TARGET_AARCH64 615 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 616 #define FFR_PRED_NUM 16 617 ARMPredicateReg pregs[17]; 618 /* Scratch space for aa64 sve predicate temporary. */ 619 ARMPredicateReg preg_tmp; 620 #endif 621 622 /* We store these fpcsr fields separately for convenience. */ 623 uint32_t qc[4] QEMU_ALIGNED(16); 624 int vec_len; 625 int vec_stride; 626 627 uint32_t xregs[16]; 628 629 /* Scratch space for aa32 neon expansion. */ 630 uint32_t scratch[8]; 631 632 /* There are a number of distinct float control structures: 633 * 634 * fp_status: is the "normal" fp status. 635 * fp_status_fp16: used for half-precision calculations 636 * standard_fp_status : the ARM "Standard FPSCR Value" 637 * standard_fp_status_fp16 : used for half-precision 638 * calculations with the ARM "Standard FPSCR Value" 639 * 640 * Half-precision operations are governed by a separate 641 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 642 * status structure to control this. 643 * 644 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 645 * round-to-nearest and is used by any operations (generally 646 * Neon) which the architecture defines as controlled by the 647 * standard FPSCR value rather than the FPSCR. 648 * 649 * The "standard FPSCR but for fp16 ops" is needed because 650 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 651 * using a fixed value for it. 652 * 653 * To avoid having to transfer exception bits around, we simply 654 * say that the FPSCR cumulative exception flags are the logical 655 * OR of the flags in the four fp statuses. This relies on the 656 * only thing which needs to read the exception flags being 657 * an explicit FPSCR read. 658 */ 659 float_status fp_status; 660 float_status fp_status_f16; 661 float_status standard_fp_status; 662 float_status standard_fp_status_f16; 663 664 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 665 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 666 } vfp; 667 uint64_t exclusive_addr; 668 uint64_t exclusive_val; 669 uint64_t exclusive_high; 670 671 /* iwMMXt coprocessor state. */ 672 struct { 673 uint64_t regs[16]; 674 uint64_t val; 675 676 uint32_t cregs[16]; 677 } iwmmxt; 678 679 #ifdef TARGET_AARCH64 680 struct { 681 ARMPACKey apia; 682 ARMPACKey apib; 683 ARMPACKey apda; 684 ARMPACKey apdb; 685 ARMPACKey apga; 686 } keys; 687 688 uint64_t scxtnum_el[4]; 689 690 /* 691 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 692 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 693 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 694 * When SVL is less than the architectural maximum, the accessible 695 * storage is restricted, such that if the SVL is X bytes the guest can 696 * see only the bottom X elements of zarray[], and only the least 697 * significant X bytes of each element of the array. (In other words, 698 * the observable part is always square.) 699 * 700 * The ZA storage can also be considered as a set of square tiles of 701 * elements of different sizes. The mapping from tiles to the ZA array 702 * is architecturally defined, such that for tiles of elements of esz 703 * bytes, the Nth row (or "horizontal slice") of tile T is in 704 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 705 * in the ZA storage, because its rows are striped through the ZA array. 706 * 707 * Because this is so large, keep this toward the end of the reset area, 708 * to keep the offsets into the rest of the structure smaller. 709 */ 710 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 711 #endif 712 713 #if defined(CONFIG_USER_ONLY) 714 /* For usermode syscall translation. */ 715 int eabi; 716 #endif 717 718 struct CPUBreakpoint *cpu_breakpoint[16]; 719 struct CPUWatchpoint *cpu_watchpoint[16]; 720 721 /* Optional fault info across tlb lookup. */ 722 ARMMMUFaultInfo *tlb_fi; 723 724 /* Fields up to this point are cleared by a CPU reset */ 725 struct {} end_reset_fields; 726 727 /* Fields after this point are preserved across CPU reset. */ 728 729 /* Internal CPU feature flags. */ 730 uint64_t features; 731 732 /* PMSAv7 MPU */ 733 struct { 734 uint32_t *drbar; 735 uint32_t *drsr; 736 uint32_t *dracr; 737 uint32_t rnr[M_REG_NUM_BANKS]; 738 } pmsav7; 739 740 /* PMSAv8 MPU */ 741 struct { 742 /* The PMSAv8 implementation also shares some PMSAv7 config 743 * and state: 744 * pmsav7.rnr (region number register) 745 * pmsav7_dregion (number of configured regions) 746 */ 747 uint32_t *rbar[M_REG_NUM_BANKS]; 748 uint32_t *rlar[M_REG_NUM_BANKS]; 749 uint32_t *hprbar; 750 uint32_t *hprlar; 751 uint32_t mair0[M_REG_NUM_BANKS]; 752 uint32_t mair1[M_REG_NUM_BANKS]; 753 uint32_t hprselr; 754 } pmsav8; 755 756 /* v8M SAU */ 757 struct { 758 uint32_t *rbar; 759 uint32_t *rlar; 760 uint32_t rnr; 761 uint32_t ctrl; 762 } sau; 763 764 void *nvic; 765 const struct arm_boot_info *boot_info; 766 /* Store GICv3CPUState to access from this struct */ 767 void *gicv3state; 768 769 #ifdef TARGET_TAGGED_ADDRESSES 770 /* Linux syscall tagged address support */ 771 bool tagged_addr_enable; 772 #endif 773 } CPUARMState; 774 775 static inline void set_feature(CPUARMState *env, int feature) 776 { 777 env->features |= 1ULL << feature; 778 } 779 780 static inline void unset_feature(CPUARMState *env, int feature) 781 { 782 env->features &= ~(1ULL << feature); 783 } 784 785 /** 786 * ARMELChangeHookFn: 787 * type of a function which can be registered via arm_register_el_change_hook() 788 * to get callbacks when the CPU changes its exception level or mode. 789 */ 790 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 791 typedef struct ARMELChangeHook ARMELChangeHook; 792 struct ARMELChangeHook { 793 ARMELChangeHookFn *hook; 794 void *opaque; 795 QLIST_ENTRY(ARMELChangeHook) node; 796 }; 797 798 /* These values map onto the return values for 799 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 800 typedef enum ARMPSCIState { 801 PSCI_ON = 0, 802 PSCI_OFF = 1, 803 PSCI_ON_PENDING = 2 804 } ARMPSCIState; 805 806 typedef struct ARMISARegisters ARMISARegisters; 807 808 /* 809 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 810 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 811 * 812 * While processing properties during initialization, corresponding init bits 813 * are set for bits in sve_vq_map that have been set by properties. 814 * 815 * Bits set in supported represent valid vector lengths for the CPU type. 816 */ 817 typedef struct { 818 uint32_t map, init, supported; 819 } ARMVQMap; 820 821 /** 822 * ARMCPU: 823 * @env: #CPUARMState 824 * 825 * An ARM CPU core. 826 */ 827 struct ArchCPU { 828 /*< private >*/ 829 CPUState parent_obj; 830 /*< public >*/ 831 832 CPUNegativeOffsetState neg; 833 CPUARMState env; 834 835 /* Coprocessor information */ 836 GHashTable *cp_regs; 837 /* For marshalling (mostly coprocessor) register state between the 838 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 839 * we use these arrays. 840 */ 841 /* List of register indexes managed via these arrays; (full KVM style 842 * 64 bit indexes, not CPRegInfo 32 bit indexes) 843 */ 844 uint64_t *cpreg_indexes; 845 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 846 uint64_t *cpreg_values; 847 /* Length of the indexes, values, reset_values arrays */ 848 int32_t cpreg_array_len; 849 /* These are used only for migration: incoming data arrives in 850 * these fields and is sanity checked in post_load before copying 851 * to the working data structures above. 852 */ 853 uint64_t *cpreg_vmstate_indexes; 854 uint64_t *cpreg_vmstate_values; 855 int32_t cpreg_vmstate_array_len; 856 857 DynamicGDBXMLInfo dyn_sysreg_xml; 858 DynamicGDBXMLInfo dyn_svereg_xml; 859 860 /* Timers used by the generic (architected) timer */ 861 QEMUTimer *gt_timer[NUM_GTIMERS]; 862 /* 863 * Timer used by the PMU. Its state is restored after migration by 864 * pmu_op_finish() - it does not need other handling during migration 865 */ 866 QEMUTimer *pmu_timer; 867 /* GPIO outputs for generic timer */ 868 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 869 /* GPIO output for GICv3 maintenance interrupt signal */ 870 qemu_irq gicv3_maintenance_interrupt; 871 /* GPIO output for the PMU interrupt */ 872 qemu_irq pmu_interrupt; 873 874 /* MemoryRegion to use for secure physical accesses */ 875 MemoryRegion *secure_memory; 876 877 /* MemoryRegion to use for allocation tag accesses */ 878 MemoryRegion *tag_memory; 879 MemoryRegion *secure_tag_memory; 880 881 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 882 Object *idau; 883 884 /* 'compatible' string for this CPU for Linux device trees */ 885 const char *dtb_compatible; 886 887 /* PSCI version for this CPU 888 * Bits[31:16] = Major Version 889 * Bits[15:0] = Minor Version 890 */ 891 uint32_t psci_version; 892 893 /* Current power state, access guarded by BQL */ 894 ARMPSCIState power_state; 895 896 /* CPU has virtualization extension */ 897 bool has_el2; 898 /* CPU has security extension */ 899 bool has_el3; 900 /* CPU has PMU (Performance Monitor Unit) */ 901 bool has_pmu; 902 /* CPU has VFP */ 903 bool has_vfp; 904 /* CPU has Neon */ 905 bool has_neon; 906 /* CPU has M-profile DSP extension */ 907 bool has_dsp; 908 909 /* CPU has memory protection unit */ 910 bool has_mpu; 911 /* PMSAv7 MPU number of supported regions */ 912 uint32_t pmsav7_dregion; 913 /* PMSAv8 MPU number of supported hyp regions */ 914 uint32_t pmsav8r_hdregion; 915 /* v8M SAU number of supported regions */ 916 uint32_t sau_sregion; 917 918 /* PSCI conduit used to invoke PSCI methods 919 * 0 - disabled, 1 - smc, 2 - hvc 920 */ 921 uint32_t psci_conduit; 922 923 /* For v8M, initial value of the Secure VTOR */ 924 uint32_t init_svtor; 925 /* For v8M, initial value of the Non-secure VTOR */ 926 uint32_t init_nsvtor; 927 928 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 929 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 930 */ 931 uint32_t kvm_target; 932 933 /* KVM init features for this CPU */ 934 uint32_t kvm_init_features[7]; 935 936 /* KVM CPU state */ 937 938 /* KVM virtual time adjustment */ 939 bool kvm_adjvtime; 940 bool kvm_vtime_dirty; 941 uint64_t kvm_vtime; 942 943 /* KVM steal time */ 944 OnOffAuto kvm_steal_time; 945 946 /* Uniprocessor system with MP extensions */ 947 bool mp_is_up; 948 949 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 950 * and the probe failed (so we need to report the error in realize) 951 */ 952 bool host_cpu_probe_failed; 953 954 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 955 * register. 956 */ 957 int32_t core_count; 958 959 /* The instance init functions for implementation-specific subclasses 960 * set these fields to specify the implementation-dependent values of 961 * various constant registers and reset values of non-constant 962 * registers. 963 * Some of these might become QOM properties eventually. 964 * Field names match the official register names as defined in the 965 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 966 * is used for reset values of non-constant registers; no reset_ 967 * prefix means a constant register. 968 * Some of these registers are split out into a substructure that 969 * is shared with the translators to control the ISA. 970 * 971 * Note that if you add an ID register to the ARMISARegisters struct 972 * you need to also update the 32-bit and 64-bit versions of the 973 * kvm_arm_get_host_cpu_features() function to correctly populate the 974 * field by reading the value from the KVM vCPU. 975 */ 976 struct ARMISARegisters { 977 uint32_t id_isar0; 978 uint32_t id_isar1; 979 uint32_t id_isar2; 980 uint32_t id_isar3; 981 uint32_t id_isar4; 982 uint32_t id_isar5; 983 uint32_t id_isar6; 984 uint32_t id_mmfr0; 985 uint32_t id_mmfr1; 986 uint32_t id_mmfr2; 987 uint32_t id_mmfr3; 988 uint32_t id_mmfr4; 989 uint32_t id_mmfr5; 990 uint32_t id_pfr0; 991 uint32_t id_pfr1; 992 uint32_t id_pfr2; 993 uint32_t mvfr0; 994 uint32_t mvfr1; 995 uint32_t mvfr2; 996 uint32_t id_dfr0; 997 uint32_t id_dfr1; 998 uint32_t dbgdidr; 999 uint32_t dbgdevid; 1000 uint32_t dbgdevid1; 1001 uint64_t id_aa64isar0; 1002 uint64_t id_aa64isar1; 1003 uint64_t id_aa64pfr0; 1004 uint64_t id_aa64pfr1; 1005 uint64_t id_aa64mmfr0; 1006 uint64_t id_aa64mmfr1; 1007 uint64_t id_aa64mmfr2; 1008 uint64_t id_aa64dfr0; 1009 uint64_t id_aa64dfr1; 1010 uint64_t id_aa64zfr0; 1011 uint64_t id_aa64smfr0; 1012 uint64_t reset_pmcr_el0; 1013 } isar; 1014 uint64_t midr; 1015 uint32_t revidr; 1016 uint32_t reset_fpsid; 1017 uint64_t ctr; 1018 uint32_t reset_sctlr; 1019 uint64_t pmceid0; 1020 uint64_t pmceid1; 1021 uint32_t id_afr0; 1022 uint64_t id_aa64afr0; 1023 uint64_t id_aa64afr1; 1024 uint64_t clidr; 1025 uint64_t mp_affinity; /* MP ID without feature bits */ 1026 /* The elements of this array are the CCSIDR values for each cache, 1027 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1028 */ 1029 uint64_t ccsidr[16]; 1030 uint64_t reset_cbar; 1031 uint32_t reset_auxcr; 1032 bool reset_hivecs; 1033 1034 /* 1035 * Intermediate values used during property parsing. 1036 * Once finalized, the values should be read from ID_AA64*. 1037 */ 1038 bool prop_pauth; 1039 bool prop_pauth_impdef; 1040 bool prop_lpa2; 1041 1042 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1043 uint32_t dcz_blocksize; 1044 uint64_t rvbar_prop; /* Property/input signals. */ 1045 1046 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1047 int gic_num_lrs; /* number of list registers */ 1048 int gic_vpribits; /* number of virtual priority bits */ 1049 int gic_vprebits; /* number of virtual preemption bits */ 1050 int gic_pribits; /* number of physical priority bits */ 1051 1052 /* Whether the cfgend input is high (i.e. this CPU should reset into 1053 * big-endian mode). This setting isn't used directly: instead it modifies 1054 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1055 * architecture version. 1056 */ 1057 bool cfgend; 1058 1059 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1060 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1061 1062 int32_t node_id; /* NUMA node this CPU belongs to */ 1063 1064 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1065 uint8_t device_irq_level; 1066 1067 /* Used to set the maximum vector length the cpu will support. */ 1068 uint32_t sve_max_vq; 1069 1070 #ifdef CONFIG_USER_ONLY 1071 /* Used to set the default vector length at process start. */ 1072 uint32_t sve_default_vq; 1073 uint32_t sme_default_vq; 1074 #endif 1075 1076 ARMVQMap sve_vq; 1077 ARMVQMap sme_vq; 1078 1079 /* Generic timer counter frequency, in Hz */ 1080 uint64_t gt_cntfrq_hz; 1081 }; 1082 1083 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1084 1085 void arm_cpu_post_init(Object *obj); 1086 1087 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1088 1089 #ifndef CONFIG_USER_ONLY 1090 extern const VMStateDescription vmstate_arm_cpu; 1091 1092 void arm_cpu_do_interrupt(CPUState *cpu); 1093 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1094 #endif /* !CONFIG_USER_ONLY */ 1095 1096 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1097 MemTxAttrs *attrs); 1098 1099 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1100 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1101 1102 /* 1103 * Helpers to dynamically generates XML descriptions of the sysregs 1104 * and SVE registers. Returns the number of registers in each set. 1105 */ 1106 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1107 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1108 1109 /* Returns the dynamically generated XML for the gdb stub. 1110 * Returns a pointer to the XML contents for the specified XML file or NULL 1111 * if the XML name doesn't match the predefined one. 1112 */ 1113 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1114 1115 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1116 int cpuid, DumpState *s); 1117 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1118 int cpuid, DumpState *s); 1119 1120 #ifdef TARGET_AARCH64 1121 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1122 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1123 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1124 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1125 int new_el, bool el0_a64); 1126 void arm_reset_sve_state(CPUARMState *env); 1127 1128 /* 1129 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1130 * The byte at offset i from the start of the in-memory representation contains 1131 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1132 * lowest offsets are stored in the lowest memory addresses, then that nearly 1133 * matches QEMU's representation, which is to use an array of host-endian 1134 * uint64_t's, where the lower offsets are at the lower indices. To complete 1135 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1136 */ 1137 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1138 { 1139 #if HOST_BIG_ENDIAN 1140 int i; 1141 1142 for (i = 0; i < nr; ++i) { 1143 dst[i] = bswap64(src[i]); 1144 } 1145 1146 return dst; 1147 #else 1148 return src; 1149 #endif 1150 } 1151 1152 #else 1153 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1154 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1155 int n, bool a) 1156 { } 1157 #endif 1158 1159 void aarch64_sync_32_to_64(CPUARMState *env); 1160 void aarch64_sync_64_to_32(CPUARMState *env); 1161 1162 int fp_exception_el(CPUARMState *env, int cur_el); 1163 int sve_exception_el(CPUARMState *env, int cur_el); 1164 int sme_exception_el(CPUARMState *env, int cur_el); 1165 1166 /** 1167 * sve_vqm1_for_el_sm: 1168 * @env: CPUARMState 1169 * @el: exception level 1170 * @sm: streaming mode 1171 * 1172 * Compute the current vector length for @el & @sm, in units of 1173 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1174 * If @sm, compute for SVL, otherwise NVL. 1175 */ 1176 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1177 1178 /* Likewise, but using @sm = PSTATE.SM. */ 1179 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1180 1181 static inline bool is_a64(CPUARMState *env) 1182 { 1183 return env->aarch64; 1184 } 1185 1186 /** 1187 * pmu_op_start/finish 1188 * @env: CPUARMState 1189 * 1190 * Convert all PMU counters between their delta form (the typical mode when 1191 * they are enabled) and the guest-visible values. These two calls must 1192 * surround any action which might affect the counters. 1193 */ 1194 void pmu_op_start(CPUARMState *env); 1195 void pmu_op_finish(CPUARMState *env); 1196 1197 /* 1198 * Called when a PMU counter is due to overflow 1199 */ 1200 void arm_pmu_timer_cb(void *opaque); 1201 1202 /** 1203 * Functions to register as EL change hooks for PMU mode filtering 1204 */ 1205 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1206 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1207 1208 /* 1209 * pmu_init 1210 * @cpu: ARMCPU 1211 * 1212 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1213 * for the current configuration 1214 */ 1215 void pmu_init(ARMCPU *cpu); 1216 1217 /* SCTLR bit meanings. Several bits have been reused in newer 1218 * versions of the architecture; in that case we define constants 1219 * for both old and new bit meanings. Code which tests against those 1220 * bits should probably check or otherwise arrange that the CPU 1221 * is the architectural version it expects. 1222 */ 1223 #define SCTLR_M (1U << 0) 1224 #define SCTLR_A (1U << 1) 1225 #define SCTLR_C (1U << 2) 1226 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1227 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1228 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1229 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1230 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1231 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1232 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1233 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1234 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1235 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1236 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1237 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1238 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1239 #define SCTLR_SED (1U << 8) /* v8 onward */ 1240 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1241 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1242 #define SCTLR_F (1U << 10) /* up to v6 */ 1243 #define SCTLR_SW (1U << 10) /* v7 */ 1244 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1245 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1246 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1247 #define SCTLR_I (1U << 12) 1248 #define SCTLR_V (1U << 13) /* AArch32 only */ 1249 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1250 #define SCTLR_RR (1U << 14) /* up to v7 */ 1251 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1252 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1253 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1254 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1255 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1256 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1257 #define SCTLR_BR (1U << 17) /* PMSA only */ 1258 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1259 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1260 #define SCTLR_WXN (1U << 19) 1261 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1262 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1263 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1264 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1265 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1266 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1267 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1268 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1269 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1270 #define SCTLR_VE (1U << 24) /* up to v7 */ 1271 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1272 #define SCTLR_EE (1U << 25) 1273 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1274 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1275 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1276 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1277 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1278 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1279 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1280 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1281 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1282 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1283 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1284 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1285 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1286 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1287 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1288 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1289 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1290 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1291 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1292 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1293 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1294 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1295 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1296 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1297 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1298 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1299 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1300 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1301 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1302 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1303 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1304 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1305 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1306 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1307 1308 /* Bit definitions for CPACR (AArch32 only) */ 1309 FIELD(CPACR, CP10, 20, 2) 1310 FIELD(CPACR, CP11, 22, 2) 1311 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1312 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1313 FIELD(CPACR, ASEDIS, 31, 1) 1314 1315 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1316 FIELD(CPACR_EL1, ZEN, 16, 2) 1317 FIELD(CPACR_EL1, FPEN, 20, 2) 1318 FIELD(CPACR_EL1, SMEN, 24, 2) 1319 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1320 1321 /* Bit definitions for HCPTR (AArch32 only) */ 1322 FIELD(HCPTR, TCP10, 10, 1) 1323 FIELD(HCPTR, TCP11, 11, 1) 1324 FIELD(HCPTR, TASE, 15, 1) 1325 FIELD(HCPTR, TTA, 20, 1) 1326 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1327 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1328 1329 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1330 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1331 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1332 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1333 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1334 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1335 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1336 FIELD(CPTR_EL2, TTA, 28, 1) 1337 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1338 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1339 1340 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1341 FIELD(CPTR_EL3, EZ, 8, 1) 1342 FIELD(CPTR_EL3, TFP, 10, 1) 1343 FIELD(CPTR_EL3, ESM, 12, 1) 1344 FIELD(CPTR_EL3, TTA, 20, 1) 1345 FIELD(CPTR_EL3, TAM, 30, 1) 1346 FIELD(CPTR_EL3, TCPAC, 31, 1) 1347 1348 #define MDCR_MTPME (1U << 28) 1349 #define MDCR_TDCC (1U << 27) 1350 #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ 1351 #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ 1352 #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ 1353 #define MDCR_EPMAD (1U << 21) 1354 #define MDCR_EDAD (1U << 20) 1355 #define MDCR_TTRF (1U << 19) 1356 #define MDCR_STE (1U << 18) /* MDCR_EL3 */ 1357 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1358 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1359 #define MDCR_SDD (1U << 16) 1360 #define MDCR_SPD (3U << 14) 1361 #define MDCR_TDRA (1U << 11) 1362 #define MDCR_TDOSA (1U << 10) 1363 #define MDCR_TDA (1U << 9) 1364 #define MDCR_TDE (1U << 8) 1365 #define MDCR_HPME (1U << 7) 1366 #define MDCR_TPM (1U << 6) 1367 #define MDCR_TPMCR (1U << 5) 1368 #define MDCR_HPMN (0x1fU) 1369 1370 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1371 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ 1372 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ 1373 MDCR_STE | MDCR_SPME | MDCR_SPD) 1374 1375 #define CPSR_M (0x1fU) 1376 #define CPSR_T (1U << 5) 1377 #define CPSR_F (1U << 6) 1378 #define CPSR_I (1U << 7) 1379 #define CPSR_A (1U << 8) 1380 #define CPSR_E (1U << 9) 1381 #define CPSR_IT_2_7 (0xfc00U) 1382 #define CPSR_GE (0xfU << 16) 1383 #define CPSR_IL (1U << 20) 1384 #define CPSR_DIT (1U << 21) 1385 #define CPSR_PAN (1U << 22) 1386 #define CPSR_SSBS (1U << 23) 1387 #define CPSR_J (1U << 24) 1388 #define CPSR_IT_0_1 (3U << 25) 1389 #define CPSR_Q (1U << 27) 1390 #define CPSR_V (1U << 28) 1391 #define CPSR_C (1U << 29) 1392 #define CPSR_Z (1U << 30) 1393 #define CPSR_N (1U << 31) 1394 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1395 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1396 1397 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1398 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1399 | CPSR_NZCV) 1400 /* Bits writable in user mode. */ 1401 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1402 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1403 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1404 1405 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1406 #define XPSR_EXCP 0x1ffU 1407 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1408 #define XPSR_IT_2_7 CPSR_IT_2_7 1409 #define XPSR_GE CPSR_GE 1410 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1411 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1412 #define XPSR_IT_0_1 CPSR_IT_0_1 1413 #define XPSR_Q CPSR_Q 1414 #define XPSR_V CPSR_V 1415 #define XPSR_C CPSR_C 1416 #define XPSR_Z CPSR_Z 1417 #define XPSR_N CPSR_N 1418 #define XPSR_NZCV CPSR_NZCV 1419 #define XPSR_IT CPSR_IT 1420 1421 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1422 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1423 #define TTBCR_PD0 (1U << 4) 1424 #define TTBCR_PD1 (1U << 5) 1425 #define TTBCR_EPD0 (1U << 7) 1426 #define TTBCR_IRGN0 (3U << 8) 1427 #define TTBCR_ORGN0 (3U << 10) 1428 #define TTBCR_SH0 (3U << 12) 1429 #define TTBCR_T1SZ (3U << 16) 1430 #define TTBCR_A1 (1U << 22) 1431 #define TTBCR_EPD1 (1U << 23) 1432 #define TTBCR_IRGN1 (3U << 24) 1433 #define TTBCR_ORGN1 (3U << 26) 1434 #define TTBCR_SH1 (1U << 28) 1435 #define TTBCR_EAE (1U << 31) 1436 1437 FIELD(VTCR, T0SZ, 0, 6) 1438 FIELD(VTCR, SL0, 6, 2) 1439 FIELD(VTCR, IRGN0, 8, 2) 1440 FIELD(VTCR, ORGN0, 10, 2) 1441 FIELD(VTCR, SH0, 12, 2) 1442 FIELD(VTCR, TG0, 14, 2) 1443 FIELD(VTCR, PS, 16, 3) 1444 FIELD(VTCR, VS, 19, 1) 1445 FIELD(VTCR, HA, 21, 1) 1446 FIELD(VTCR, HD, 22, 1) 1447 FIELD(VTCR, HWU59, 25, 1) 1448 FIELD(VTCR, HWU60, 26, 1) 1449 FIELD(VTCR, HWU61, 27, 1) 1450 FIELD(VTCR, HWU62, 28, 1) 1451 FIELD(VTCR, NSW, 29, 1) 1452 FIELD(VTCR, NSA, 30, 1) 1453 FIELD(VTCR, DS, 32, 1) 1454 FIELD(VTCR, SL2, 33, 1) 1455 1456 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1457 * Only these are valid when in AArch64 mode; in 1458 * AArch32 mode SPSRs are basically CPSR-format. 1459 */ 1460 #define PSTATE_SP (1U) 1461 #define PSTATE_M (0xFU) 1462 #define PSTATE_nRW (1U << 4) 1463 #define PSTATE_F (1U << 6) 1464 #define PSTATE_I (1U << 7) 1465 #define PSTATE_A (1U << 8) 1466 #define PSTATE_D (1U << 9) 1467 #define PSTATE_BTYPE (3U << 10) 1468 #define PSTATE_SSBS (1U << 12) 1469 #define PSTATE_IL (1U << 20) 1470 #define PSTATE_SS (1U << 21) 1471 #define PSTATE_PAN (1U << 22) 1472 #define PSTATE_UAO (1U << 23) 1473 #define PSTATE_DIT (1U << 24) 1474 #define PSTATE_TCO (1U << 25) 1475 #define PSTATE_V (1U << 28) 1476 #define PSTATE_C (1U << 29) 1477 #define PSTATE_Z (1U << 30) 1478 #define PSTATE_N (1U << 31) 1479 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1480 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1481 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1482 /* Mode values for AArch64 */ 1483 #define PSTATE_MODE_EL3h 13 1484 #define PSTATE_MODE_EL3t 12 1485 #define PSTATE_MODE_EL2h 9 1486 #define PSTATE_MODE_EL2t 8 1487 #define PSTATE_MODE_EL1h 5 1488 #define PSTATE_MODE_EL1t 4 1489 #define PSTATE_MODE_EL0t 0 1490 1491 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1492 FIELD(SVCR, SM, 0, 1) 1493 FIELD(SVCR, ZA, 1, 1) 1494 1495 /* Fields for SMCR_ELx. */ 1496 FIELD(SMCR, LEN, 0, 4) 1497 FIELD(SMCR, FA64, 31, 1) 1498 1499 /* Write a new value to v7m.exception, thus transitioning into or out 1500 * of Handler mode; this may result in a change of active stack pointer. 1501 */ 1502 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1503 1504 /* Map EL and handler into a PSTATE_MODE. */ 1505 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1506 { 1507 return (el << 2) | handler; 1508 } 1509 1510 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1511 * interprocessing, so we don't attempt to sync with the cpsr state used by 1512 * the 32 bit decoder. 1513 */ 1514 static inline uint32_t pstate_read(CPUARMState *env) 1515 { 1516 int ZF; 1517 1518 ZF = (env->ZF == 0); 1519 return (env->NF & 0x80000000) | (ZF << 30) 1520 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1521 | env->pstate | env->daif | (env->btype << 10); 1522 } 1523 1524 static inline void pstate_write(CPUARMState *env, uint32_t val) 1525 { 1526 env->ZF = (~val) & PSTATE_Z; 1527 env->NF = val; 1528 env->CF = (val >> 29) & 1; 1529 env->VF = (val << 3) & 0x80000000; 1530 env->daif = val & PSTATE_DAIF; 1531 env->btype = (val >> 10) & 3; 1532 env->pstate = val & ~CACHED_PSTATE_BITS; 1533 } 1534 1535 /* Return the current CPSR value. */ 1536 uint32_t cpsr_read(CPUARMState *env); 1537 1538 typedef enum CPSRWriteType { 1539 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1540 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1541 CPSRWriteRaw = 2, 1542 /* trust values, no reg bank switch, no hflags rebuild */ 1543 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1544 } CPSRWriteType; 1545 1546 /* 1547 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1548 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1549 * correspond to TB flags bits cached in the hflags, unless @write_type 1550 * is CPSRWriteRaw. 1551 */ 1552 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1553 CPSRWriteType write_type); 1554 1555 /* Return the current xPSR value. */ 1556 static inline uint32_t xpsr_read(CPUARMState *env) 1557 { 1558 int ZF; 1559 ZF = (env->ZF == 0); 1560 return (env->NF & 0x80000000) | (ZF << 30) 1561 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1562 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1563 | ((env->condexec_bits & 0xfc) << 8) 1564 | (env->GE << 16) 1565 | env->v7m.exception; 1566 } 1567 1568 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1569 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1570 { 1571 if (mask & XPSR_NZCV) { 1572 env->ZF = (~val) & XPSR_Z; 1573 env->NF = val; 1574 env->CF = (val >> 29) & 1; 1575 env->VF = (val << 3) & 0x80000000; 1576 } 1577 if (mask & XPSR_Q) { 1578 env->QF = ((val & XPSR_Q) != 0); 1579 } 1580 if (mask & XPSR_GE) { 1581 env->GE = (val & XPSR_GE) >> 16; 1582 } 1583 #ifndef CONFIG_USER_ONLY 1584 if (mask & XPSR_T) { 1585 env->thumb = ((val & XPSR_T) != 0); 1586 } 1587 if (mask & XPSR_IT_0_1) { 1588 env->condexec_bits &= ~3; 1589 env->condexec_bits |= (val >> 25) & 3; 1590 } 1591 if (mask & XPSR_IT_2_7) { 1592 env->condexec_bits &= 3; 1593 env->condexec_bits |= (val >> 8) & 0xfc; 1594 } 1595 if (mask & XPSR_EXCP) { 1596 /* Note that this only happens on exception exit */ 1597 write_v7m_exception(env, val & XPSR_EXCP); 1598 } 1599 #endif 1600 } 1601 1602 #define HCR_VM (1ULL << 0) 1603 #define HCR_SWIO (1ULL << 1) 1604 #define HCR_PTW (1ULL << 2) 1605 #define HCR_FMO (1ULL << 3) 1606 #define HCR_IMO (1ULL << 4) 1607 #define HCR_AMO (1ULL << 5) 1608 #define HCR_VF (1ULL << 6) 1609 #define HCR_VI (1ULL << 7) 1610 #define HCR_VSE (1ULL << 8) 1611 #define HCR_FB (1ULL << 9) 1612 #define HCR_BSU_MASK (3ULL << 10) 1613 #define HCR_DC (1ULL << 12) 1614 #define HCR_TWI (1ULL << 13) 1615 #define HCR_TWE (1ULL << 14) 1616 #define HCR_TID0 (1ULL << 15) 1617 #define HCR_TID1 (1ULL << 16) 1618 #define HCR_TID2 (1ULL << 17) 1619 #define HCR_TID3 (1ULL << 18) 1620 #define HCR_TSC (1ULL << 19) 1621 #define HCR_TIDCP (1ULL << 20) 1622 #define HCR_TACR (1ULL << 21) 1623 #define HCR_TSW (1ULL << 22) 1624 #define HCR_TPCP (1ULL << 23) 1625 #define HCR_TPU (1ULL << 24) 1626 #define HCR_TTLB (1ULL << 25) 1627 #define HCR_TVM (1ULL << 26) 1628 #define HCR_TGE (1ULL << 27) 1629 #define HCR_TDZ (1ULL << 28) 1630 #define HCR_HCD (1ULL << 29) 1631 #define HCR_TRVM (1ULL << 30) 1632 #define HCR_RW (1ULL << 31) 1633 #define HCR_CD (1ULL << 32) 1634 #define HCR_ID (1ULL << 33) 1635 #define HCR_E2H (1ULL << 34) 1636 #define HCR_TLOR (1ULL << 35) 1637 #define HCR_TERR (1ULL << 36) 1638 #define HCR_TEA (1ULL << 37) 1639 #define HCR_MIOCNCE (1ULL << 38) 1640 /* RES0 bit 39 */ 1641 #define HCR_APK (1ULL << 40) 1642 #define HCR_API (1ULL << 41) 1643 #define HCR_NV (1ULL << 42) 1644 #define HCR_NV1 (1ULL << 43) 1645 #define HCR_AT (1ULL << 44) 1646 #define HCR_NV2 (1ULL << 45) 1647 #define HCR_FWB (1ULL << 46) 1648 #define HCR_FIEN (1ULL << 47) 1649 /* RES0 bit 48 */ 1650 #define HCR_TID4 (1ULL << 49) 1651 #define HCR_TICAB (1ULL << 50) 1652 #define HCR_AMVOFFEN (1ULL << 51) 1653 #define HCR_TOCU (1ULL << 52) 1654 #define HCR_ENSCXT (1ULL << 53) 1655 #define HCR_TTLBIS (1ULL << 54) 1656 #define HCR_TTLBOS (1ULL << 55) 1657 #define HCR_ATA (1ULL << 56) 1658 #define HCR_DCT (1ULL << 57) 1659 #define HCR_TID5 (1ULL << 58) 1660 #define HCR_TWEDEN (1ULL << 59) 1661 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1662 1663 #define HCRX_ENAS0 (1ULL << 0) 1664 #define HCRX_ENALS (1ULL << 1) 1665 #define HCRX_ENASR (1ULL << 2) 1666 #define HCRX_FNXS (1ULL << 3) 1667 #define HCRX_FGTNXS (1ULL << 4) 1668 #define HCRX_SMPME (1ULL << 5) 1669 #define HCRX_TALLINT (1ULL << 6) 1670 #define HCRX_VINMI (1ULL << 7) 1671 #define HCRX_VFNMI (1ULL << 8) 1672 #define HCRX_CMOW (1ULL << 9) 1673 #define HCRX_MCE2 (1ULL << 10) 1674 #define HCRX_MSCEN (1ULL << 11) 1675 1676 #define HPFAR_NS (1ULL << 63) 1677 1678 #define SCR_NS (1ULL << 0) 1679 #define SCR_IRQ (1ULL << 1) 1680 #define SCR_FIQ (1ULL << 2) 1681 #define SCR_EA (1ULL << 3) 1682 #define SCR_FW (1ULL << 4) 1683 #define SCR_AW (1ULL << 5) 1684 #define SCR_NET (1ULL << 6) 1685 #define SCR_SMD (1ULL << 7) 1686 #define SCR_HCE (1ULL << 8) 1687 #define SCR_SIF (1ULL << 9) 1688 #define SCR_RW (1ULL << 10) 1689 #define SCR_ST (1ULL << 11) 1690 #define SCR_TWI (1ULL << 12) 1691 #define SCR_TWE (1ULL << 13) 1692 #define SCR_TLOR (1ULL << 14) 1693 #define SCR_TERR (1ULL << 15) 1694 #define SCR_APK (1ULL << 16) 1695 #define SCR_API (1ULL << 17) 1696 #define SCR_EEL2 (1ULL << 18) 1697 #define SCR_EASE (1ULL << 19) 1698 #define SCR_NMEA (1ULL << 20) 1699 #define SCR_FIEN (1ULL << 21) 1700 #define SCR_ENSCXT (1ULL << 25) 1701 #define SCR_ATA (1ULL << 26) 1702 #define SCR_FGTEN (1ULL << 27) 1703 #define SCR_ECVEN (1ULL << 28) 1704 #define SCR_TWEDEN (1ULL << 29) 1705 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1706 #define SCR_TME (1ULL << 34) 1707 #define SCR_AMVOFFEN (1ULL << 35) 1708 #define SCR_ENAS0 (1ULL << 36) 1709 #define SCR_ADEN (1ULL << 37) 1710 #define SCR_HXEN (1ULL << 38) 1711 #define SCR_TRNDR (1ULL << 40) 1712 #define SCR_ENTP2 (1ULL << 41) 1713 #define SCR_GPF (1ULL << 48) 1714 1715 #define HSTR_TTEE (1 << 16) 1716 #define HSTR_TJDBX (1 << 17) 1717 1718 /* Return the current FPSCR value. */ 1719 uint32_t vfp_get_fpscr(CPUARMState *env); 1720 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1721 1722 /* FPCR, Floating Point Control Register 1723 * FPSR, Floating Poiht Status Register 1724 * 1725 * For A64 the FPSCR is split into two logically distinct registers, 1726 * FPCR and FPSR. However since they still use non-overlapping bits 1727 * we store the underlying state in fpscr and just mask on read/write. 1728 */ 1729 #define FPSR_MASK 0xf800009f 1730 #define FPCR_MASK 0x07ff9f00 1731 1732 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1733 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1734 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1735 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1736 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1737 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1738 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1739 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1740 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1741 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1742 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1743 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1744 #define FPCR_V (1 << 28) /* FP overflow flag */ 1745 #define FPCR_C (1 << 29) /* FP carry flag */ 1746 #define FPCR_Z (1 << 30) /* FP zero flag */ 1747 #define FPCR_N (1 << 31) /* FP negative flag */ 1748 1749 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1750 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1751 #define FPCR_LTPSIZE_LENGTH 3 1752 1753 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1754 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1755 1756 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1757 { 1758 return vfp_get_fpscr(env) & FPSR_MASK; 1759 } 1760 1761 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1762 { 1763 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1764 vfp_set_fpscr(env, new_fpscr); 1765 } 1766 1767 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1768 { 1769 return vfp_get_fpscr(env) & FPCR_MASK; 1770 } 1771 1772 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1773 { 1774 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1775 vfp_set_fpscr(env, new_fpscr); 1776 } 1777 1778 enum arm_cpu_mode { 1779 ARM_CPU_MODE_USR = 0x10, 1780 ARM_CPU_MODE_FIQ = 0x11, 1781 ARM_CPU_MODE_IRQ = 0x12, 1782 ARM_CPU_MODE_SVC = 0x13, 1783 ARM_CPU_MODE_MON = 0x16, 1784 ARM_CPU_MODE_ABT = 0x17, 1785 ARM_CPU_MODE_HYP = 0x1a, 1786 ARM_CPU_MODE_UND = 0x1b, 1787 ARM_CPU_MODE_SYS = 0x1f 1788 }; 1789 1790 /* VFP system registers. */ 1791 #define ARM_VFP_FPSID 0 1792 #define ARM_VFP_FPSCR 1 1793 #define ARM_VFP_MVFR2 5 1794 #define ARM_VFP_MVFR1 6 1795 #define ARM_VFP_MVFR0 7 1796 #define ARM_VFP_FPEXC 8 1797 #define ARM_VFP_FPINST 9 1798 #define ARM_VFP_FPINST2 10 1799 /* These ones are M-profile only */ 1800 #define ARM_VFP_FPSCR_NZCVQC 2 1801 #define ARM_VFP_VPR 12 1802 #define ARM_VFP_P0 13 1803 #define ARM_VFP_FPCXT_NS 14 1804 #define ARM_VFP_FPCXT_S 15 1805 1806 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1807 #define QEMU_VFP_FPSCR_NZCV 0xffff 1808 1809 /* iwMMXt coprocessor control registers. */ 1810 #define ARM_IWMMXT_wCID 0 1811 #define ARM_IWMMXT_wCon 1 1812 #define ARM_IWMMXT_wCSSF 2 1813 #define ARM_IWMMXT_wCASF 3 1814 #define ARM_IWMMXT_wCGR0 8 1815 #define ARM_IWMMXT_wCGR1 9 1816 #define ARM_IWMMXT_wCGR2 10 1817 #define ARM_IWMMXT_wCGR3 11 1818 1819 /* V7M CCR bits */ 1820 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1821 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1822 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1823 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1824 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1825 FIELD(V7M_CCR, STKALIGN, 9, 1) 1826 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1827 FIELD(V7M_CCR, DC, 16, 1) 1828 FIELD(V7M_CCR, IC, 17, 1) 1829 FIELD(V7M_CCR, BP, 18, 1) 1830 FIELD(V7M_CCR, LOB, 19, 1) 1831 FIELD(V7M_CCR, TRD, 20, 1) 1832 1833 /* V7M SCR bits */ 1834 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1835 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1836 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1837 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1838 1839 /* V7M AIRCR bits */ 1840 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1841 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1842 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1843 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1844 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1845 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1846 FIELD(V7M_AIRCR, PRIS, 14, 1) 1847 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1848 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1849 1850 /* V7M CFSR bits for MMFSR */ 1851 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1852 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1853 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1854 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1855 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1856 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1857 1858 /* V7M CFSR bits for BFSR */ 1859 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1860 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1861 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1862 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1863 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1864 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1865 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1866 1867 /* V7M CFSR bits for UFSR */ 1868 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1869 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1870 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1871 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1872 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1873 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1874 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1875 1876 /* V7M CFSR bit masks covering all of the subregister bits */ 1877 FIELD(V7M_CFSR, MMFSR, 0, 8) 1878 FIELD(V7M_CFSR, BFSR, 8, 8) 1879 FIELD(V7M_CFSR, UFSR, 16, 16) 1880 1881 /* V7M HFSR bits */ 1882 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1883 FIELD(V7M_HFSR, FORCED, 30, 1) 1884 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1885 1886 /* V7M DFSR bits */ 1887 FIELD(V7M_DFSR, HALTED, 0, 1) 1888 FIELD(V7M_DFSR, BKPT, 1, 1) 1889 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1890 FIELD(V7M_DFSR, VCATCH, 3, 1) 1891 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1892 1893 /* V7M SFSR bits */ 1894 FIELD(V7M_SFSR, INVEP, 0, 1) 1895 FIELD(V7M_SFSR, INVIS, 1, 1) 1896 FIELD(V7M_SFSR, INVER, 2, 1) 1897 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1898 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1899 FIELD(V7M_SFSR, LSPERR, 5, 1) 1900 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1901 FIELD(V7M_SFSR, LSERR, 7, 1) 1902 1903 /* v7M MPU_CTRL bits */ 1904 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1905 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1906 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1907 1908 /* v7M CLIDR bits */ 1909 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1910 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1911 FIELD(V7M_CLIDR, LOC, 24, 3) 1912 FIELD(V7M_CLIDR, LOUU, 27, 3) 1913 FIELD(V7M_CLIDR, ICB, 30, 2) 1914 1915 FIELD(V7M_CSSELR, IND, 0, 1) 1916 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1917 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1918 * define a mask for this and check that it doesn't permit running off 1919 * the end of the array. 1920 */ 1921 FIELD(V7M_CSSELR, INDEX, 0, 4) 1922 1923 /* v7M FPCCR bits */ 1924 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1925 FIELD(V7M_FPCCR, USER, 1, 1) 1926 FIELD(V7M_FPCCR, S, 2, 1) 1927 FIELD(V7M_FPCCR, THREAD, 3, 1) 1928 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1929 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1930 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1931 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1932 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1933 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1934 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1935 FIELD(V7M_FPCCR, RES0, 11, 15) 1936 FIELD(V7M_FPCCR, TS, 26, 1) 1937 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1938 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1939 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1940 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1941 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1942 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1943 #define R_V7M_FPCCR_BANKED_MASK \ 1944 (R_V7M_FPCCR_LSPACT_MASK | \ 1945 R_V7M_FPCCR_USER_MASK | \ 1946 R_V7M_FPCCR_THREAD_MASK | \ 1947 R_V7M_FPCCR_MMRDY_MASK | \ 1948 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1949 R_V7M_FPCCR_UFRDY_MASK | \ 1950 R_V7M_FPCCR_ASPEN_MASK) 1951 1952 /* v7M VPR bits */ 1953 FIELD(V7M_VPR, P0, 0, 16) 1954 FIELD(V7M_VPR, MASK01, 16, 4) 1955 FIELD(V7M_VPR, MASK23, 20, 4) 1956 1957 /* 1958 * System register ID fields. 1959 */ 1960 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1961 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1962 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1963 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1964 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1965 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1966 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1967 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1968 FIELD(CLIDR_EL1, LOC, 24, 3) 1969 FIELD(CLIDR_EL1, LOUU, 27, 3) 1970 FIELD(CLIDR_EL1, ICB, 30, 3) 1971 1972 /* When FEAT_CCIDX is implemented */ 1973 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1974 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1975 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1976 1977 /* When FEAT_CCIDX is not implemented */ 1978 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1979 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1980 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1981 1982 FIELD(CTR_EL0, IMINLINE, 0, 4) 1983 FIELD(CTR_EL0, L1IP, 14, 2) 1984 FIELD(CTR_EL0, DMINLINE, 16, 4) 1985 FIELD(CTR_EL0, ERG, 20, 4) 1986 FIELD(CTR_EL0, CWG, 24, 4) 1987 FIELD(CTR_EL0, IDC, 28, 1) 1988 FIELD(CTR_EL0, DIC, 29, 1) 1989 FIELD(CTR_EL0, TMINLINE, 32, 6) 1990 1991 FIELD(MIDR_EL1, REVISION, 0, 4) 1992 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1993 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1994 FIELD(MIDR_EL1, VARIANT, 20, 4) 1995 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1996 1997 FIELD(ID_ISAR0, SWAP, 0, 4) 1998 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1999 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2000 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2001 FIELD(ID_ISAR0, COPROC, 16, 4) 2002 FIELD(ID_ISAR0, DEBUG, 20, 4) 2003 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2004 2005 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2006 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2007 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2008 FIELD(ID_ISAR1, EXTEND, 12, 4) 2009 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2010 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2011 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2012 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2013 2014 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2015 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2016 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2017 FIELD(ID_ISAR2, MULT, 12, 4) 2018 FIELD(ID_ISAR2, MULTS, 16, 4) 2019 FIELD(ID_ISAR2, MULTU, 20, 4) 2020 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2021 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2022 2023 FIELD(ID_ISAR3, SATURATE, 0, 4) 2024 FIELD(ID_ISAR3, SIMD, 4, 4) 2025 FIELD(ID_ISAR3, SVC, 8, 4) 2026 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2027 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2028 FIELD(ID_ISAR3, T32COPY, 20, 4) 2029 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2030 FIELD(ID_ISAR3, T32EE, 28, 4) 2031 2032 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2033 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2034 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2035 FIELD(ID_ISAR4, SMC, 12, 4) 2036 FIELD(ID_ISAR4, BARRIER, 16, 4) 2037 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2038 FIELD(ID_ISAR4, PSR_M, 24, 4) 2039 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2040 2041 FIELD(ID_ISAR5, SEVL, 0, 4) 2042 FIELD(ID_ISAR5, AES, 4, 4) 2043 FIELD(ID_ISAR5, SHA1, 8, 4) 2044 FIELD(ID_ISAR5, SHA2, 12, 4) 2045 FIELD(ID_ISAR5, CRC32, 16, 4) 2046 FIELD(ID_ISAR5, RDM, 24, 4) 2047 FIELD(ID_ISAR5, VCMA, 28, 4) 2048 2049 FIELD(ID_ISAR6, JSCVT, 0, 4) 2050 FIELD(ID_ISAR6, DP, 4, 4) 2051 FIELD(ID_ISAR6, FHM, 8, 4) 2052 FIELD(ID_ISAR6, SB, 12, 4) 2053 FIELD(ID_ISAR6, SPECRES, 16, 4) 2054 FIELD(ID_ISAR6, BF16, 20, 4) 2055 FIELD(ID_ISAR6, I8MM, 24, 4) 2056 2057 FIELD(ID_MMFR0, VMSA, 0, 4) 2058 FIELD(ID_MMFR0, PMSA, 4, 4) 2059 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2060 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2061 FIELD(ID_MMFR0, TCM, 16, 4) 2062 FIELD(ID_MMFR0, AUXREG, 20, 4) 2063 FIELD(ID_MMFR0, FCSE, 24, 4) 2064 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2065 2066 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2067 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2068 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2069 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2070 FIELD(ID_MMFR1, L1HVD, 16, 4) 2071 FIELD(ID_MMFR1, L1UNI, 20, 4) 2072 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2073 FIELD(ID_MMFR1, BPRED, 28, 4) 2074 2075 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2076 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2077 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2078 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2079 FIELD(ID_MMFR2, UNITLB, 16, 4) 2080 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2081 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2082 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2083 2084 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2085 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2086 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2087 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2088 FIELD(ID_MMFR3, PAN, 16, 4) 2089 FIELD(ID_MMFR3, COHWALK, 20, 4) 2090 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2091 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2092 2093 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2094 FIELD(ID_MMFR4, AC2, 4, 4) 2095 FIELD(ID_MMFR4, XNX, 8, 4) 2096 FIELD(ID_MMFR4, CNP, 12, 4) 2097 FIELD(ID_MMFR4, HPDS, 16, 4) 2098 FIELD(ID_MMFR4, LSM, 20, 4) 2099 FIELD(ID_MMFR4, CCIDX, 24, 4) 2100 FIELD(ID_MMFR4, EVT, 28, 4) 2101 2102 FIELD(ID_MMFR5, ETS, 0, 4) 2103 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2104 2105 FIELD(ID_PFR0, STATE0, 0, 4) 2106 FIELD(ID_PFR0, STATE1, 4, 4) 2107 FIELD(ID_PFR0, STATE2, 8, 4) 2108 FIELD(ID_PFR0, STATE3, 12, 4) 2109 FIELD(ID_PFR0, CSV2, 16, 4) 2110 FIELD(ID_PFR0, AMU, 20, 4) 2111 FIELD(ID_PFR0, DIT, 24, 4) 2112 FIELD(ID_PFR0, RAS, 28, 4) 2113 2114 FIELD(ID_PFR1, PROGMOD, 0, 4) 2115 FIELD(ID_PFR1, SECURITY, 4, 4) 2116 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2117 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2118 FIELD(ID_PFR1, GENTIMER, 16, 4) 2119 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2120 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2121 FIELD(ID_PFR1, GIC, 28, 4) 2122 2123 FIELD(ID_PFR2, CSV3, 0, 4) 2124 FIELD(ID_PFR2, SSBS, 4, 4) 2125 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2126 2127 FIELD(ID_AA64ISAR0, AES, 4, 4) 2128 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2129 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2130 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2131 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2132 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2133 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2134 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2135 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2136 FIELD(ID_AA64ISAR0, DP, 44, 4) 2137 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2138 FIELD(ID_AA64ISAR0, TS, 52, 4) 2139 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2140 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2141 2142 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2143 FIELD(ID_AA64ISAR1, APA, 4, 4) 2144 FIELD(ID_AA64ISAR1, API, 8, 4) 2145 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2146 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2147 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2148 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2149 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2150 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2151 FIELD(ID_AA64ISAR1, SB, 36, 4) 2152 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2153 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2154 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2155 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2156 FIELD(ID_AA64ISAR1, XS, 56, 4) 2157 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2158 2159 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2160 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2161 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2162 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2163 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2164 FIELD(ID_AA64ISAR2, BC, 20, 4) 2165 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2166 2167 FIELD(ID_AA64PFR0, EL0, 0, 4) 2168 FIELD(ID_AA64PFR0, EL1, 4, 4) 2169 FIELD(ID_AA64PFR0, EL2, 8, 4) 2170 FIELD(ID_AA64PFR0, EL3, 12, 4) 2171 FIELD(ID_AA64PFR0, FP, 16, 4) 2172 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2173 FIELD(ID_AA64PFR0, GIC, 24, 4) 2174 FIELD(ID_AA64PFR0, RAS, 28, 4) 2175 FIELD(ID_AA64PFR0, SVE, 32, 4) 2176 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2177 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2178 FIELD(ID_AA64PFR0, AMU, 44, 4) 2179 FIELD(ID_AA64PFR0, DIT, 48, 4) 2180 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2181 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2182 2183 FIELD(ID_AA64PFR1, BT, 0, 4) 2184 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2185 FIELD(ID_AA64PFR1, MTE, 8, 4) 2186 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2187 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2188 FIELD(ID_AA64PFR1, SME, 24, 4) 2189 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2190 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2191 FIELD(ID_AA64PFR1, NMI, 36, 4) 2192 2193 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2194 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2195 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2196 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2197 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2198 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2199 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2200 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2201 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2202 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2203 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2204 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2205 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2206 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2207 2208 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2209 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2210 FIELD(ID_AA64MMFR1, VH, 8, 4) 2211 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2212 FIELD(ID_AA64MMFR1, LO, 16, 4) 2213 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2214 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2215 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2216 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2217 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2218 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2219 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2220 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2221 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2222 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2223 2224 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2225 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2226 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2227 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2228 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2229 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2230 FIELD(ID_AA64MMFR2, NV, 24, 4) 2231 FIELD(ID_AA64MMFR2, ST, 28, 4) 2232 FIELD(ID_AA64MMFR2, AT, 32, 4) 2233 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2234 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2235 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2236 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2237 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2238 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2239 2240 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2241 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2242 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2243 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2244 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2245 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2246 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2247 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2248 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2249 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2250 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2251 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2252 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2253 2254 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2255 FIELD(ID_AA64ZFR0, AES, 4, 4) 2256 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2257 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2258 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2259 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2260 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2261 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2262 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2263 2264 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2265 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2266 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2267 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2268 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2269 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2270 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2271 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2272 2273 FIELD(ID_DFR0, COPDBG, 0, 4) 2274 FIELD(ID_DFR0, COPSDBG, 4, 4) 2275 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2276 FIELD(ID_DFR0, COPTRC, 12, 4) 2277 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2278 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2279 FIELD(ID_DFR0, PERFMON, 24, 4) 2280 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2281 2282 FIELD(ID_DFR1, MTPMU, 0, 4) 2283 FIELD(ID_DFR1, HPMN0, 4, 4) 2284 2285 FIELD(DBGDIDR, SE_IMP, 12, 1) 2286 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2287 FIELD(DBGDIDR, VERSION, 16, 4) 2288 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2289 FIELD(DBGDIDR, BRPS, 24, 4) 2290 FIELD(DBGDIDR, WRPS, 28, 4) 2291 2292 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2293 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2294 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2295 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2296 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2297 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2298 FIELD(DBGDEVID, AUXREGS, 24, 4) 2299 FIELD(DBGDEVID, CIDMASK, 28, 4) 2300 2301 FIELD(MVFR0, SIMDREG, 0, 4) 2302 FIELD(MVFR0, FPSP, 4, 4) 2303 FIELD(MVFR0, FPDP, 8, 4) 2304 FIELD(MVFR0, FPTRAP, 12, 4) 2305 FIELD(MVFR0, FPDIVIDE, 16, 4) 2306 FIELD(MVFR0, FPSQRT, 20, 4) 2307 FIELD(MVFR0, FPSHVEC, 24, 4) 2308 FIELD(MVFR0, FPROUND, 28, 4) 2309 2310 FIELD(MVFR1, FPFTZ, 0, 4) 2311 FIELD(MVFR1, FPDNAN, 4, 4) 2312 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2313 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2314 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2315 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2316 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2317 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2318 FIELD(MVFR1, FPHP, 24, 4) 2319 FIELD(MVFR1, SIMDFMAC, 28, 4) 2320 2321 FIELD(MVFR2, SIMDMISC, 0, 4) 2322 FIELD(MVFR2, FPMISC, 4, 4) 2323 2324 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2325 2326 /* If adding a feature bit which corresponds to a Linux ELF 2327 * HWCAP bit, remember to update the feature-bit-to-hwcap 2328 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2329 */ 2330 enum arm_features { 2331 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2332 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2333 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2334 ARM_FEATURE_V6, 2335 ARM_FEATURE_V6K, 2336 ARM_FEATURE_V7, 2337 ARM_FEATURE_THUMB2, 2338 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2339 ARM_FEATURE_NEON, 2340 ARM_FEATURE_M, /* Microcontroller profile. */ 2341 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2342 ARM_FEATURE_THUMB2EE, 2343 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2344 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2345 ARM_FEATURE_V4T, 2346 ARM_FEATURE_V5, 2347 ARM_FEATURE_STRONGARM, 2348 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2349 ARM_FEATURE_GENERIC_TIMER, 2350 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2351 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2352 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2353 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2354 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2355 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2356 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2357 ARM_FEATURE_V8, 2358 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2359 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2360 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2361 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2362 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2363 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2364 ARM_FEATURE_PMU, /* has PMU support */ 2365 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2366 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2367 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2368 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2369 }; 2370 2371 static inline int arm_feature(CPUARMState *env, int feature) 2372 { 2373 return (env->features & (1ULL << feature)) != 0; 2374 } 2375 2376 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2377 2378 #if !defined(CONFIG_USER_ONLY) 2379 /* Return true if exception levels below EL3 are in secure state, 2380 * or would be following an exception return to that level. 2381 * Unlike arm_is_secure() (which is always a question about the 2382 * _current_ state of the CPU) this doesn't care about the current 2383 * EL or mode. 2384 */ 2385 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2386 { 2387 if (arm_feature(env, ARM_FEATURE_EL3)) { 2388 return !(env->cp15.scr_el3 & SCR_NS); 2389 } else { 2390 /* If EL3 is not supported then the secure state is implementation 2391 * defined, in which case QEMU defaults to non-secure. 2392 */ 2393 return false; 2394 } 2395 } 2396 2397 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2398 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2399 { 2400 if (arm_feature(env, ARM_FEATURE_EL3)) { 2401 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2402 /* CPU currently in AArch64 state and EL3 */ 2403 return true; 2404 } else if (!is_a64(env) && 2405 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2406 /* CPU currently in AArch32 state and monitor mode */ 2407 return true; 2408 } 2409 } 2410 return false; 2411 } 2412 2413 /* Return true if the processor is in secure state */ 2414 static inline bool arm_is_secure(CPUARMState *env) 2415 { 2416 if (arm_is_el3_or_mon(env)) { 2417 return true; 2418 } 2419 return arm_is_secure_below_el3(env); 2420 } 2421 2422 /* 2423 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2424 * This corresponds to the pseudocode EL2Enabled() 2425 */ 2426 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2427 { 2428 return arm_feature(env, ARM_FEATURE_EL2) 2429 && (!secure || (env->cp15.scr_el3 & SCR_EEL2)); 2430 } 2431 2432 static inline bool arm_is_el2_enabled(CPUARMState *env) 2433 { 2434 return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env)); 2435 } 2436 2437 #else 2438 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2439 { 2440 return false; 2441 } 2442 2443 static inline bool arm_is_secure(CPUARMState *env) 2444 { 2445 return false; 2446 } 2447 2448 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2449 { 2450 return false; 2451 } 2452 2453 static inline bool arm_is_el2_enabled(CPUARMState *env) 2454 { 2455 return false; 2456 } 2457 #endif 2458 2459 /** 2460 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2461 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2462 * "for all purposes other than a direct read or write access of HCR_EL2." 2463 * Not included here is HCR_RW. 2464 */ 2465 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); 2466 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2467 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2468 2469 /* Return true if the specified exception level is running in AArch64 state. */ 2470 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2471 { 2472 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2473 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2474 */ 2475 assert(el >= 1 && el <= 3); 2476 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2477 2478 /* The highest exception level is always at the maximum supported 2479 * register width, and then lower levels have a register width controlled 2480 * by bits in the SCR or HCR registers. 2481 */ 2482 if (el == 3) { 2483 return aa64; 2484 } 2485 2486 if (arm_feature(env, ARM_FEATURE_EL3) && 2487 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2488 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2489 } 2490 2491 if (el == 2) { 2492 return aa64; 2493 } 2494 2495 if (arm_is_el2_enabled(env)) { 2496 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2497 } 2498 2499 return aa64; 2500 } 2501 2502 /* Function for determing whether guest cp register reads and writes should 2503 * access the secure or non-secure bank of a cp register. When EL3 is 2504 * operating in AArch32 state, the NS-bit determines whether the secure 2505 * instance of a cp register should be used. When EL3 is AArch64 (or if 2506 * it doesn't exist at all) then there is no register banking, and all 2507 * accesses are to the non-secure version. 2508 */ 2509 static inline bool access_secure_reg(CPUARMState *env) 2510 { 2511 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2512 !arm_el_is_aa64(env, 3) && 2513 !(env->cp15.scr_el3 & SCR_NS)); 2514 2515 return ret; 2516 } 2517 2518 /* Macros for accessing a specified CP register bank */ 2519 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2520 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2521 2522 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2523 do { \ 2524 if (_secure) { \ 2525 (_env)->cp15._regname##_s = (_val); \ 2526 } else { \ 2527 (_env)->cp15._regname##_ns = (_val); \ 2528 } \ 2529 } while (0) 2530 2531 /* Macros for automatically accessing a specific CP register bank depending on 2532 * the current secure state of the system. These macros are not intended for 2533 * supporting instruction translation reads/writes as these are dependent 2534 * solely on the SCR.NS bit and not the mode. 2535 */ 2536 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2537 A32_BANKED_REG_GET((_env), _regname, \ 2538 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2539 2540 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2541 A32_BANKED_REG_SET((_env), _regname, \ 2542 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2543 (_val)) 2544 2545 void arm_cpu_list(void); 2546 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2547 uint32_t cur_el, bool secure); 2548 2549 /* Interface between CPU and Interrupt controller. */ 2550 #ifndef CONFIG_USER_ONLY 2551 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2552 #else 2553 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2554 { 2555 return true; 2556 } 2557 #endif 2558 /** 2559 * armv7m_nvic_set_pending: mark the specified exception as pending 2560 * @opaque: the NVIC 2561 * @irq: the exception number to mark pending 2562 * @secure: false for non-banked exceptions or for the nonsecure 2563 * version of a banked exception, true for the secure version of a banked 2564 * exception. 2565 * 2566 * Marks the specified exception as pending. Note that we will assert() 2567 * if @secure is true and @irq does not specify one of the fixed set 2568 * of architecturally banked exceptions. 2569 */ 2570 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2571 /** 2572 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2573 * @opaque: the NVIC 2574 * @irq: the exception number to mark pending 2575 * @secure: false for non-banked exceptions or for the nonsecure 2576 * version of a banked exception, true for the secure version of a banked 2577 * exception. 2578 * 2579 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2580 * exceptions (exceptions generated in the course of trying to take 2581 * a different exception). 2582 */ 2583 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2584 /** 2585 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2586 * @opaque: the NVIC 2587 * @irq: the exception number to mark pending 2588 * @secure: false for non-banked exceptions or for the nonsecure 2589 * version of a banked exception, true for the secure version of a banked 2590 * exception. 2591 * 2592 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2593 * generated in the course of lazy stacking of FP registers. 2594 */ 2595 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2596 /** 2597 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2598 * exception, and whether it targets Secure state 2599 * @opaque: the NVIC 2600 * @pirq: set to pending exception number 2601 * @ptargets_secure: set to whether pending exception targets Secure 2602 * 2603 * This function writes the number of the highest priority pending 2604 * exception (the one which would be made active by 2605 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2606 * to true if the current highest priority pending exception should 2607 * be taken to Secure state, false for NS. 2608 */ 2609 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2610 bool *ptargets_secure); 2611 /** 2612 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2613 * @opaque: the NVIC 2614 * 2615 * Move the current highest priority pending exception from the pending 2616 * state to the active state, and update v7m.exception to indicate that 2617 * it is the exception currently being handled. 2618 */ 2619 void armv7m_nvic_acknowledge_irq(void *opaque); 2620 /** 2621 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2622 * @opaque: the NVIC 2623 * @irq: the exception number to complete 2624 * @secure: true if this exception was secure 2625 * 2626 * Returns: -1 if the irq was not active 2627 * 1 if completing this irq brought us back to base (no active irqs) 2628 * 0 if there is still an irq active after this one was completed 2629 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2630 */ 2631 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2632 /** 2633 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2634 * @opaque: the NVIC 2635 * @irq: the exception number to mark pending 2636 * @secure: false for non-banked exceptions or for the nonsecure 2637 * version of a banked exception, true for the secure version of a banked 2638 * exception. 2639 * 2640 * Return whether an exception is "ready", i.e. whether the exception is 2641 * enabled and is configured at a priority which would allow it to 2642 * interrupt the current execution priority. This controls whether the 2643 * RDY bit for it in the FPCCR is set. 2644 */ 2645 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2646 /** 2647 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2648 * @opaque: the NVIC 2649 * 2650 * Returns: the raw execution priority as defined by the v8M architecture. 2651 * This is the execution priority minus the effects of AIRCR.PRIS, 2652 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2653 * (v8M ARM ARM I_PKLD.) 2654 */ 2655 int armv7m_nvic_raw_execution_priority(void *opaque); 2656 /** 2657 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2658 * priority is negative for the specified security state. 2659 * @opaque: the NVIC 2660 * @secure: the security state to test 2661 * This corresponds to the pseudocode IsReqExecPriNeg(). 2662 */ 2663 #ifndef CONFIG_USER_ONLY 2664 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2665 #else 2666 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2667 { 2668 return false; 2669 } 2670 #endif 2671 2672 /* Interface for defining coprocessor registers. 2673 * Registers are defined in tables of arm_cp_reginfo structs 2674 * which are passed to define_arm_cp_regs(). 2675 */ 2676 2677 /* When looking up a coprocessor register we look for it 2678 * via an integer which encodes all of: 2679 * coprocessor number 2680 * Crn, Crm, opc1, opc2 fields 2681 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2682 * or via MRRC/MCRR?) 2683 * non-secure/secure bank (AArch32 only) 2684 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2685 * (In this case crn and opc2 should be zero.) 2686 * For AArch64, there is no 32/64 bit size distinction; 2687 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2688 * and 4 bit CRn and CRm. The encoding patterns are chosen 2689 * to be easy to convert to and from the KVM encodings, and also 2690 * so that the hashtable can contain both AArch32 and AArch64 2691 * registers (to allow for interprocessing where we might run 2692 * 32 bit code on a 64 bit core). 2693 */ 2694 /* This bit is private to our hashtable cpreg; in KVM register 2695 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2696 * in the upper bits of the 64 bit ID. 2697 */ 2698 #define CP_REG_AA64_SHIFT 28 2699 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2700 2701 /* To enable banking of coprocessor registers depending on ns-bit we 2702 * add a bit to distinguish between secure and non-secure cpregs in the 2703 * hashtable. 2704 */ 2705 #define CP_REG_NS_SHIFT 29 2706 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2707 2708 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2709 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2710 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2711 2712 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2713 (CP_REG_AA64_MASK | \ 2714 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2715 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2716 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2717 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2718 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2719 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2720 2721 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2722 * version used as a key for the coprocessor register hashtable 2723 */ 2724 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2725 { 2726 uint32_t cpregid = kvmid; 2727 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2728 cpregid |= CP_REG_AA64_MASK; 2729 } else { 2730 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2731 cpregid |= (1 << 15); 2732 } 2733 2734 /* KVM is always non-secure so add the NS flag on AArch32 register 2735 * entries. 2736 */ 2737 cpregid |= 1 << CP_REG_NS_SHIFT; 2738 } 2739 return cpregid; 2740 } 2741 2742 /* Convert a truncated 32 bit hashtable key into the full 2743 * 64 bit KVM register ID. 2744 */ 2745 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2746 { 2747 uint64_t kvmid; 2748 2749 if (cpregid & CP_REG_AA64_MASK) { 2750 kvmid = cpregid & ~CP_REG_AA64_MASK; 2751 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2752 } else { 2753 kvmid = cpregid & ~(1 << 15); 2754 if (cpregid & (1 << 15)) { 2755 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2756 } else { 2757 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2758 } 2759 } 2760 return kvmid; 2761 } 2762 2763 /* Return the highest implemented Exception Level */ 2764 static inline int arm_highest_el(CPUARMState *env) 2765 { 2766 if (arm_feature(env, ARM_FEATURE_EL3)) { 2767 return 3; 2768 } 2769 if (arm_feature(env, ARM_FEATURE_EL2)) { 2770 return 2; 2771 } 2772 return 1; 2773 } 2774 2775 /* Return true if a v7M CPU is in Handler mode */ 2776 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2777 { 2778 return env->v7m.exception != 0; 2779 } 2780 2781 /* Return the current Exception Level (as per ARMv8; note that this differs 2782 * from the ARMv7 Privilege Level). 2783 */ 2784 static inline int arm_current_el(CPUARMState *env) 2785 { 2786 if (arm_feature(env, ARM_FEATURE_M)) { 2787 return arm_v7m_is_handler_mode(env) || 2788 !(env->v7m.control[env->v7m.secure] & 1); 2789 } 2790 2791 if (is_a64(env)) { 2792 return extract32(env->pstate, 2, 2); 2793 } 2794 2795 switch (env->uncached_cpsr & 0x1f) { 2796 case ARM_CPU_MODE_USR: 2797 return 0; 2798 case ARM_CPU_MODE_HYP: 2799 return 2; 2800 case ARM_CPU_MODE_MON: 2801 return 3; 2802 default: 2803 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2804 /* If EL3 is 32-bit then all secure privileged modes run in 2805 * EL3 2806 */ 2807 return 3; 2808 } 2809 2810 return 1; 2811 } 2812 } 2813 2814 /** 2815 * write_list_to_cpustate 2816 * @cpu: ARMCPU 2817 * 2818 * For each register listed in the ARMCPU cpreg_indexes list, write 2819 * its value from the cpreg_values list into the ARMCPUState structure. 2820 * This updates TCG's working data structures from KVM data or 2821 * from incoming migration state. 2822 * 2823 * Returns: true if all register values were updated correctly, 2824 * false if some register was unknown or could not be written. 2825 * Note that we do not stop early on failure -- we will attempt 2826 * writing all registers in the list. 2827 */ 2828 bool write_list_to_cpustate(ARMCPU *cpu); 2829 2830 /** 2831 * write_cpustate_to_list: 2832 * @cpu: ARMCPU 2833 * @kvm_sync: true if this is for syncing back to KVM 2834 * 2835 * For each register listed in the ARMCPU cpreg_indexes list, write 2836 * its value from the ARMCPUState structure into the cpreg_values list. 2837 * This is used to copy info from TCG's working data structures into 2838 * KVM or for outbound migration. 2839 * 2840 * @kvm_sync is true if we are doing this in order to sync the 2841 * register state back to KVM. In this case we will only update 2842 * values in the list if the previous list->cpustate sync actually 2843 * successfully wrote the CPU state. Otherwise we will keep the value 2844 * that is in the list. 2845 * 2846 * Returns: true if all register values were read correctly, 2847 * false if some register was unknown or could not be read. 2848 * Note that we do not stop early on failure -- we will attempt 2849 * reading all registers in the list. 2850 */ 2851 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2852 2853 #define ARM_CPUID_TI915T 0x54029152 2854 #define ARM_CPUID_TI925T 0x54029252 2855 2856 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2857 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2858 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2859 2860 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2861 2862 #define cpu_list arm_cpu_list 2863 2864 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2865 * 2866 * If EL3 is 64-bit: 2867 * + NonSecure EL1 & 0 stage 1 2868 * + NonSecure EL1 & 0 stage 2 2869 * + NonSecure EL2 2870 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2871 * + Secure EL1 & 0 2872 * + Secure EL3 2873 * If EL3 is 32-bit: 2874 * + NonSecure PL1 & 0 stage 1 2875 * + NonSecure PL1 & 0 stage 2 2876 * + NonSecure PL2 2877 * + Secure PL0 2878 * + Secure PL1 2879 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2880 * 2881 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2882 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2883 * because they may differ in access permissions even if the VA->PA map is 2884 * the same 2885 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2886 * translation, which means that we have one mmu_idx that deals with two 2887 * concatenated translation regimes [this sort of combined s1+2 TLB is 2888 * architecturally permitted] 2889 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2890 * handling via the TLB. The only way to do a stage 1 translation without 2891 * the immediate stage 2 translation is via the ATS or AT system insns, 2892 * which can be slow-pathed and always do a page table walk. 2893 * The only use of stage 2 translations is either as part of an s1+2 2894 * lookup or when loading the descriptors during a stage 1 page table walk, 2895 * and in both those cases we don't use the TLB. 2896 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2897 * translation regimes, because they map reasonably well to each other 2898 * and they can't both be active at the same time. 2899 * 5. we want to be able to use the TLB for accesses done as part of a 2900 * stage1 page table walk, rather than having to walk the stage2 page 2901 * table over and over. 2902 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2903 * Never (PAN) bit within PSTATE. 2904 * 7. we fold together the secure and non-secure regimes for A-profile, 2905 * because there are no banked system registers for aarch64, so the 2906 * process of switching between secure and non-secure is 2907 * already heavyweight. 2908 * 2909 * This gives us the following list of cases: 2910 * 2911 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2912 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2913 * EL1 EL1&0 stage 1+2 +PAN 2914 * EL0 EL2&0 2915 * EL2 EL2&0 2916 * EL2 EL2&0 +PAN 2917 * EL2 (aka NS PL2) 2918 * EL3 (aka S PL1) 2919 * Physical (NS & S) 2920 * Stage2 (NS & S) 2921 * 2922 * for a total of 12 different mmu_idx. 2923 * 2924 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2925 * as A profile. They only need to distinguish EL0 and EL1 (and 2926 * EL2 if we ever model a Cortex-R52). 2927 * 2928 * M profile CPUs are rather different as they do not have a true MMU. 2929 * They have the following different MMU indexes: 2930 * User 2931 * Privileged 2932 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2933 * Privileged, execution priority negative (ditto) 2934 * If the CPU supports the v8M Security Extension then there are also: 2935 * Secure User 2936 * Secure Privileged 2937 * Secure User, execution priority negative 2938 * Secure Privileged, execution priority negative 2939 * 2940 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2941 * are not quite the same -- different CPU types (most notably M profile 2942 * vs A/R profile) would like to use MMU indexes with different semantics, 2943 * but since we don't ever need to use all of those in a single CPU we 2944 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2945 * modes + total number of M profile MMU modes". The lower bits of 2946 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2947 * the same for any particular CPU. 2948 * Variables of type ARMMUIdx are always full values, and the core 2949 * index values are in variables of type 'int'. 2950 * 2951 * Our enumeration includes at the end some entries which are not "true" 2952 * mmu_idx values in that they don't have corresponding TLBs and are only 2953 * valid for doing slow path page table walks. 2954 * 2955 * The constant names here are patterned after the general style of the names 2956 * of the AT/ATS operations. 2957 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2958 * For M profile we arrange them to have a bit for priv, a bit for negpri 2959 * and a bit for secure. 2960 */ 2961 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2962 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2963 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2964 2965 /* Meanings of the bits for M profile mmu idx values */ 2966 #define ARM_MMU_IDX_M_PRIV 0x1 2967 #define ARM_MMU_IDX_M_NEGPRI 0x2 2968 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2969 2970 #define ARM_MMU_IDX_TYPE_MASK \ 2971 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2972 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2973 2974 typedef enum ARMMMUIdx { 2975 /* 2976 * A-profile. 2977 */ 2978 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2979 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2980 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2981 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2982 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2983 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2984 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2985 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2986 2987 /* TLBs with 1-1 mapping to the physical address spaces. */ 2988 ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A, 2989 ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A, 2990 2991 /* 2992 * Used for second stage of an S12 page table walk, or for descriptor 2993 * loads during first stage of an S1 page table walk. Note that both 2994 * are in use simultaneously for SecureEL2: the security state for 2995 * the S2 ptw is selected by the NS bit from the S1 ptw. 2996 */ 2997 ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A, 2998 ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A, 2999 3000 /* 3001 * These are not allocated TLBs and are used only for AT system 3002 * instructions or for the first stage of an S12 page table walk. 3003 */ 3004 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 3005 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 3006 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 3007 3008 /* 3009 * M-profile. 3010 */ 3011 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 3012 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 3013 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 3014 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 3015 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 3016 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 3017 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 3018 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 3019 } ARMMMUIdx; 3020 3021 /* 3022 * Bit macros for the core-mmu-index values for each index, 3023 * for use when calling tlb_flush_by_mmuidx() and friends. 3024 */ 3025 #define TO_CORE_BIT(NAME) \ 3026 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 3027 3028 typedef enum ARMMMUIdxBit { 3029 TO_CORE_BIT(E10_0), 3030 TO_CORE_BIT(E20_0), 3031 TO_CORE_BIT(E10_1), 3032 TO_CORE_BIT(E10_1_PAN), 3033 TO_CORE_BIT(E2), 3034 TO_CORE_BIT(E20_2), 3035 TO_CORE_BIT(E20_2_PAN), 3036 TO_CORE_BIT(E3), 3037 TO_CORE_BIT(Stage2), 3038 TO_CORE_BIT(Stage2_S), 3039 3040 TO_CORE_BIT(MUser), 3041 TO_CORE_BIT(MPriv), 3042 TO_CORE_BIT(MUserNegPri), 3043 TO_CORE_BIT(MPrivNegPri), 3044 TO_CORE_BIT(MSUser), 3045 TO_CORE_BIT(MSPriv), 3046 TO_CORE_BIT(MSUserNegPri), 3047 TO_CORE_BIT(MSPrivNegPri), 3048 } ARMMMUIdxBit; 3049 3050 #undef TO_CORE_BIT 3051 3052 #define MMU_USER_IDX 0 3053 3054 /* Indexes used when registering address spaces with cpu_address_space_init */ 3055 typedef enum ARMASIdx { 3056 ARMASIdx_NS = 0, 3057 ARMASIdx_S = 1, 3058 ARMASIdx_TagNS = 2, 3059 ARMASIdx_TagS = 3, 3060 } ARMASIdx; 3061 3062 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3063 { 3064 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3065 * CSSELR is RAZ/WI. 3066 */ 3067 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3068 } 3069 3070 static inline bool arm_sctlr_b(CPUARMState *env) 3071 { 3072 return 3073 /* We need not implement SCTLR.ITD in user-mode emulation, so 3074 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3075 * This lets people run BE32 binaries with "-cpu any". 3076 */ 3077 #ifndef CONFIG_USER_ONLY 3078 !arm_feature(env, ARM_FEATURE_V7) && 3079 #endif 3080 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3081 } 3082 3083 uint64_t arm_sctlr(CPUARMState *env, int el); 3084 3085 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3086 bool sctlr_b) 3087 { 3088 #ifdef CONFIG_USER_ONLY 3089 /* 3090 * In system mode, BE32 is modelled in line with the 3091 * architecture (as word-invariant big-endianness), where loads 3092 * and stores are done little endian but from addresses which 3093 * are adjusted by XORing with the appropriate constant. So the 3094 * endianness to use for the raw data access is not affected by 3095 * SCTLR.B. 3096 * In user mode, however, we model BE32 as byte-invariant 3097 * big-endianness (because user-only code cannot tell the 3098 * difference), and so we need to use a data access endianness 3099 * that depends on SCTLR.B. 3100 */ 3101 if (sctlr_b) { 3102 return true; 3103 } 3104 #endif 3105 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3106 return env->uncached_cpsr & CPSR_E; 3107 } 3108 3109 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3110 { 3111 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3112 } 3113 3114 /* Return true if the processor is in big-endian mode. */ 3115 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3116 { 3117 if (!is_a64(env)) { 3118 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3119 } else { 3120 int cur_el = arm_current_el(env); 3121 uint64_t sctlr = arm_sctlr(env, cur_el); 3122 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3123 } 3124 } 3125 3126 #include "exec/cpu-all.h" 3127 3128 /* 3129 * We have more than 32-bits worth of state per TB, so we split the data 3130 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3131 * We collect these two parts in CPUARMTBFlags where they are named 3132 * flags and flags2 respectively. 3133 * 3134 * The flags that are shared between all execution modes, TBFLAG_ANY, 3135 * are stored in flags. The flags that are specific to a given mode 3136 * are stores in flags2. Since cs_base is sized on the configured 3137 * address size, flags2 always has 64-bits for A64, and a minimum of 3138 * 32-bits for A32 and M32. 3139 * 3140 * The bits for 32-bit A-profile and M-profile partially overlap: 3141 * 3142 * 31 23 11 10 0 3143 * +-------------+----------+----------------+ 3144 * | | | TBFLAG_A32 | 3145 * | TBFLAG_AM32 | +-----+----------+ 3146 * | | |TBFLAG_M32| 3147 * +-------------+----------------+----------+ 3148 * 31 23 6 5 0 3149 * 3150 * Unless otherwise noted, these bits are cached in env->hflags. 3151 */ 3152 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3153 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3154 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3155 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3156 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3157 /* Target EL if we take a floating-point-disabled exception */ 3158 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3159 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3160 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3161 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3162 3163 /* 3164 * Bit usage when in AArch32 state, both A- and M-profile. 3165 */ 3166 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3167 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3168 3169 /* 3170 * Bit usage when in AArch32 state, for A-profile only. 3171 */ 3172 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3173 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3174 /* 3175 * We store the bottom two bits of the CPAR as TB flags and handle 3176 * checks on the other bits at runtime. This shares the same bits as 3177 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3178 * Not cached, because VECLEN+VECSTRIDE are not cached. 3179 */ 3180 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3181 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3182 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3183 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3184 /* 3185 * Indicates whether cp register reads and writes by guest code should access 3186 * the secure or nonsecure bank of banked registers; note that this is not 3187 * the same thing as the current security state of the processor! 3188 */ 3189 FIELD(TBFLAG_A32, NS, 10, 1) 3190 /* 3191 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3192 * This requires an SME trap from AArch32 mode when using NEON. 3193 */ 3194 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3195 3196 /* 3197 * Bit usage when in AArch32 state, for M-profile only. 3198 */ 3199 /* Handler (ie not Thread) mode */ 3200 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3201 /* Whether we should generate stack-limit checks */ 3202 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3203 /* Set if FPCCR.LSPACT is set */ 3204 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3205 /* Set if we must create a new FP context */ 3206 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3207 /* Set if FPCCR.S does not match current security state */ 3208 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3209 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3210 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3211 /* Set if in secure mode */ 3212 FIELD(TBFLAG_M32, SECURE, 6, 1) 3213 3214 /* 3215 * Bit usage when in AArch64 state 3216 */ 3217 FIELD(TBFLAG_A64, TBII, 0, 2) 3218 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3219 /* The current vector length, either NVL or SVL. */ 3220 FIELD(TBFLAG_A64, VL, 4, 4) 3221 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3222 FIELD(TBFLAG_A64, BT, 9, 1) 3223 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3224 FIELD(TBFLAG_A64, TBID, 12, 2) 3225 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3226 FIELD(TBFLAG_A64, ATA, 15, 1) 3227 FIELD(TBFLAG_A64, TCMA, 16, 2) 3228 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3229 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3230 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3231 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3232 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3233 FIELD(TBFLAG_A64, SVL, 24, 4) 3234 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3235 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3236 3237 /* 3238 * Helpers for using the above. 3239 */ 3240 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3241 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3242 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3243 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3244 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3245 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3246 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3247 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3248 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3249 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3250 3251 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3252 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3253 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3254 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3255 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3256 3257 /** 3258 * cpu_mmu_index: 3259 * @env: The cpu environment 3260 * @ifetch: True for code access, false for data access. 3261 * 3262 * Return the core mmu index for the current translation regime. 3263 * This function is used by generic TCG code paths. 3264 */ 3265 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3266 { 3267 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3268 } 3269 3270 /** 3271 * sve_vq 3272 * @env: the cpu context 3273 * 3274 * Return the VL cached within env->hflags, in units of quadwords. 3275 */ 3276 static inline int sve_vq(CPUARMState *env) 3277 { 3278 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3279 } 3280 3281 /** 3282 * sme_vq 3283 * @env: the cpu context 3284 * 3285 * Return the SVL cached within env->hflags, in units of quadwords. 3286 */ 3287 static inline int sme_vq(CPUARMState *env) 3288 { 3289 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3290 } 3291 3292 static inline bool bswap_code(bool sctlr_b) 3293 { 3294 #ifdef CONFIG_USER_ONLY 3295 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3296 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3297 * would also end up as a mixed-endian mode with BE code, LE data. 3298 */ 3299 return 3300 #if TARGET_BIG_ENDIAN 3301 1 ^ 3302 #endif 3303 sctlr_b; 3304 #else 3305 /* All code access in ARM is little endian, and there are no loaders 3306 * doing swaps that need to be reversed 3307 */ 3308 return 0; 3309 #endif 3310 } 3311 3312 #ifdef CONFIG_USER_ONLY 3313 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3314 { 3315 return 3316 #if TARGET_BIG_ENDIAN 3317 1 ^ 3318 #endif 3319 arm_cpu_data_is_big_endian(env); 3320 } 3321 #endif 3322 3323 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3324 target_ulong *cs_base, uint32_t *flags); 3325 3326 enum { 3327 QEMU_PSCI_CONDUIT_DISABLED = 0, 3328 QEMU_PSCI_CONDUIT_SMC = 1, 3329 QEMU_PSCI_CONDUIT_HVC = 2, 3330 }; 3331 3332 #ifndef CONFIG_USER_ONLY 3333 /* Return the address space index to use for a memory access */ 3334 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3335 { 3336 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3337 } 3338 3339 /* Return the AddressSpace to use for a memory access 3340 * (which depends on whether the access is S or NS, and whether 3341 * the board gave us a separate AddressSpace for S accesses). 3342 */ 3343 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3344 { 3345 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3346 } 3347 #endif 3348 3349 /** 3350 * arm_register_pre_el_change_hook: 3351 * Register a hook function which will be called immediately before this 3352 * CPU changes exception level or mode. The hook function will be 3353 * passed a pointer to the ARMCPU and the opaque data pointer passed 3354 * to this function when the hook was registered. 3355 * 3356 * Note that if a pre-change hook is called, any registered post-change hooks 3357 * are guaranteed to subsequently be called. 3358 */ 3359 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3360 void *opaque); 3361 /** 3362 * arm_register_el_change_hook: 3363 * Register a hook function which will be called immediately after this 3364 * CPU changes exception level or mode. The hook function will be 3365 * passed a pointer to the ARMCPU and the opaque data pointer passed 3366 * to this function when the hook was registered. 3367 * 3368 * Note that any registered hooks registered here are guaranteed to be called 3369 * if pre-change hooks have been. 3370 */ 3371 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3372 *opaque); 3373 3374 /** 3375 * arm_rebuild_hflags: 3376 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3377 */ 3378 void arm_rebuild_hflags(CPUARMState *env); 3379 3380 /** 3381 * aa32_vfp_dreg: 3382 * Return a pointer to the Dn register within env in 32-bit mode. 3383 */ 3384 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3385 { 3386 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3387 } 3388 3389 /** 3390 * aa32_vfp_qreg: 3391 * Return a pointer to the Qn register within env in 32-bit mode. 3392 */ 3393 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3394 { 3395 return &env->vfp.zregs[regno].d[0]; 3396 } 3397 3398 /** 3399 * aa64_vfp_qreg: 3400 * Return a pointer to the Qn register within env in 64-bit mode. 3401 */ 3402 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3403 { 3404 return &env->vfp.zregs[regno].d[0]; 3405 } 3406 3407 /* Shared between translate-sve.c and sve_helper.c. */ 3408 extern const uint64_t pred_esz_masks[5]; 3409 3410 /* 3411 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3412 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3413 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3414 */ 3415 #define PAGE_BTI PAGE_TARGET_1 3416 #define PAGE_MTE PAGE_TARGET_2 3417 #define PAGE_TARGET_STICKY PAGE_MTE 3418 3419 /* We associate one allocation tag per 16 bytes, the minimum. */ 3420 #define LOG2_TAG_GRANULE 4 3421 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3422 3423 #ifdef CONFIG_USER_ONLY 3424 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3425 #endif 3426 3427 #ifdef TARGET_TAGGED_ADDRESSES 3428 /** 3429 * cpu_untagged_addr: 3430 * @cs: CPU context 3431 * @x: tagged address 3432 * 3433 * Remove any address tag from @x. This is explicitly related to the 3434 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3435 * 3436 * There should be a better place to put this, but we need this in 3437 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3438 */ 3439 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3440 { 3441 ARMCPU *cpu = ARM_CPU(cs); 3442 if (cpu->env.tagged_addr_enable) { 3443 /* 3444 * TBI is enabled for userspace but not kernelspace addresses. 3445 * Only clear the tag if bit 55 is clear. 3446 */ 3447 x &= sextract64(x, 0, 56); 3448 } 3449 return x; 3450 } 3451 #endif 3452 3453 /* 3454 * Naming convention for isar_feature functions: 3455 * Functions which test 32-bit ID registers should have _aa32_ in 3456 * their name. Functions which test 64-bit ID registers should have 3457 * _aa64_ in their name. These must only be used in code where we 3458 * know for certain that the CPU has AArch32 or AArch64 respectively 3459 * or where the correct answer for a CPU which doesn't implement that 3460 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3461 * system registers that are specific to that CPU state, for "should 3462 * we let this system register bit be set" tests where the 32-bit 3463 * flavour of the register doesn't have the bit, and so on). 3464 * Functions which simply ask "does this feature exist at all" have 3465 * _any_ in their name, and always return the logical OR of the _aa64_ 3466 * and the _aa32_ function. 3467 */ 3468 3469 /* 3470 * 32-bit feature tests via id registers. 3471 */ 3472 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3473 { 3474 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3475 } 3476 3477 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3478 { 3479 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3480 } 3481 3482 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3483 { 3484 /* (M-profile) low-overhead loops and branch future */ 3485 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3486 } 3487 3488 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3489 { 3490 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3491 } 3492 3493 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3494 { 3495 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3496 } 3497 3498 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3499 { 3500 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3501 } 3502 3503 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3504 { 3505 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3506 } 3507 3508 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3509 { 3510 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3511 } 3512 3513 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3514 { 3515 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3516 } 3517 3518 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3519 { 3520 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3521 } 3522 3523 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3524 { 3525 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3526 } 3527 3528 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3529 { 3530 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3531 } 3532 3533 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3534 { 3535 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3536 } 3537 3538 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3539 { 3540 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3541 } 3542 3543 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3544 { 3545 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3546 } 3547 3548 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3549 { 3550 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3551 } 3552 3553 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3554 { 3555 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3556 } 3557 3558 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3559 { 3560 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3561 } 3562 3563 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3564 { 3565 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3566 } 3567 3568 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3569 { 3570 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3571 } 3572 3573 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3574 { 3575 /* 3576 * Return true if M-profile state handling insns 3577 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3578 */ 3579 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3580 } 3581 3582 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3583 { 3584 /* Sadly this is encoded differently for A-profile and M-profile */ 3585 if (isar_feature_aa32_mprofile(id)) { 3586 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3587 } else { 3588 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3589 } 3590 } 3591 3592 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3593 { 3594 /* 3595 * Return true if MVE is supported (either integer or floating point). 3596 * We must check for M-profile as the MVFR1 field means something 3597 * else for A-profile. 3598 */ 3599 return isar_feature_aa32_mprofile(id) && 3600 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3601 } 3602 3603 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3604 { 3605 /* 3606 * Return true if MVE is supported (either integer or floating point). 3607 * We must check for M-profile as the MVFR1 field means something 3608 * else for A-profile. 3609 */ 3610 return isar_feature_aa32_mprofile(id) && 3611 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3612 } 3613 3614 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3615 { 3616 /* 3617 * Return true if either VFP or SIMD is implemented. 3618 * In this case, a minimum of VFP w/ D0-D15. 3619 */ 3620 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3621 } 3622 3623 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3624 { 3625 /* Return true if D16-D31 are implemented */ 3626 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3627 } 3628 3629 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3630 { 3631 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3632 } 3633 3634 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3635 { 3636 /* Return true if CPU supports single precision floating point, VFPv2 */ 3637 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3638 } 3639 3640 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3641 { 3642 /* Return true if CPU supports single precision floating point, VFPv3 */ 3643 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3644 } 3645 3646 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3647 { 3648 /* Return true if CPU supports double precision floating point, VFPv2 */ 3649 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3650 } 3651 3652 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3653 { 3654 /* Return true if CPU supports double precision floating point, VFPv3 */ 3655 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3656 } 3657 3658 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3659 { 3660 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3661 } 3662 3663 /* 3664 * We always set the FP and SIMD FP16 fields to indicate identical 3665 * levels of support (assuming SIMD is implemented at all), so 3666 * we only need one set of accessors. 3667 */ 3668 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3669 { 3670 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3671 } 3672 3673 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3674 { 3675 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3676 } 3677 3678 /* 3679 * Note that this ID register field covers both VFP and Neon FMAC, 3680 * so should usually be tested in combination with some other 3681 * check that confirms the presence of whichever of VFP or Neon is 3682 * relevant, to avoid accidentally enabling a Neon feature on 3683 * a VFP-no-Neon core or vice-versa. 3684 */ 3685 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3686 { 3687 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3688 } 3689 3690 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3691 { 3692 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3693 } 3694 3695 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3696 { 3697 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3698 } 3699 3700 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3701 { 3702 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3703 } 3704 3705 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3706 { 3707 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3708 } 3709 3710 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3711 { 3712 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3713 } 3714 3715 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3716 { 3717 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3718 } 3719 3720 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3721 { 3722 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3723 } 3724 3725 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) 3726 { 3727 /* 0xf means "non-standard IMPDEF PMU" */ 3728 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3729 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3730 } 3731 3732 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) 3733 { 3734 /* 0xf means "non-standard IMPDEF PMU" */ 3735 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3736 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3737 } 3738 3739 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) 3740 { 3741 /* 0xf means "non-standard IMPDEF PMU" */ 3742 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 && 3743 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3744 } 3745 3746 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3747 { 3748 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3749 } 3750 3751 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3752 { 3753 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3754 } 3755 3756 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3757 { 3758 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3759 } 3760 3761 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3762 { 3763 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3764 } 3765 3766 static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) 3767 { 3768 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1; 3769 } 3770 3771 static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) 3772 { 3773 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2; 3774 } 3775 3776 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3777 { 3778 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3779 } 3780 3781 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3782 { 3783 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3784 } 3785 3786 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) 3787 { 3788 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5; 3789 } 3790 3791 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3792 { 3793 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3794 } 3795 3796 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) 3797 { 3798 return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0; 3799 } 3800 3801 /* 3802 * 64-bit feature tests via id registers. 3803 */ 3804 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3805 { 3806 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3807 } 3808 3809 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3810 { 3811 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3812 } 3813 3814 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3815 { 3816 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3817 } 3818 3819 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3820 { 3821 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3822 } 3823 3824 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3825 { 3826 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3827 } 3828 3829 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3830 { 3831 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3832 } 3833 3834 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3835 { 3836 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3837 } 3838 3839 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3840 { 3841 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3842 } 3843 3844 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3845 { 3846 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3847 } 3848 3849 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3850 { 3851 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3852 } 3853 3854 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3855 { 3856 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3857 } 3858 3859 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3860 { 3861 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3862 } 3863 3864 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3865 { 3866 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3867 } 3868 3869 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3870 { 3871 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3872 } 3873 3874 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3875 { 3876 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3877 } 3878 3879 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3880 { 3881 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3882 } 3883 3884 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3885 { 3886 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3887 } 3888 3889 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3890 { 3891 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3892 } 3893 3894 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3895 { 3896 /* 3897 * Return true if any form of pauth is enabled, as this 3898 * predicate controls migration of the 128-bit keys. 3899 */ 3900 return (id->id_aa64isar1 & 3901 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3902 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3903 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3904 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3905 } 3906 3907 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3908 { 3909 /* 3910 * Return true if pauth is enabled with the architected QARMA algorithm. 3911 * QEMU will always set APA+GPA to the same value. 3912 */ 3913 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3914 } 3915 3916 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3917 { 3918 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3919 } 3920 3921 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3922 { 3923 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3924 } 3925 3926 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3927 { 3928 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3929 } 3930 3931 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3932 { 3933 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3934 } 3935 3936 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3937 { 3938 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3939 } 3940 3941 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3942 { 3943 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3944 } 3945 3946 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3947 { 3948 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3949 } 3950 3951 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3952 { 3953 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3954 } 3955 3956 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3957 { 3958 /* We always set the AdvSIMD and FP fields identically. */ 3959 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3960 } 3961 3962 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3963 { 3964 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3965 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3966 } 3967 3968 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3969 { 3970 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3971 } 3972 3973 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3974 { 3975 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3976 } 3977 3978 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) 3979 { 3980 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; 3981 } 3982 3983 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3984 { 3985 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 3986 } 3987 3988 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) 3989 { 3990 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2; 3991 } 3992 3993 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3994 { 3995 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3996 } 3997 3998 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 3999 { 4000 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 4001 } 4002 4003 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 4004 { 4005 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 4006 } 4007 4008 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 4009 { 4010 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 4011 } 4012 4013 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 4014 { 4015 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 4016 } 4017 4018 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 4019 { 4020 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 4021 } 4022 4023 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) 4024 { 4025 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; 4026 } 4027 4028 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 4029 { 4030 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 4031 } 4032 4033 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 4034 { 4035 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 4036 } 4037 4038 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) 4039 { 4040 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; 4041 } 4042 4043 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) 4044 { 4045 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; 4046 } 4047 4048 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) 4049 { 4050 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1; 4051 } 4052 4053 static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) 4054 { 4055 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2; 4056 } 4057 4058 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 4059 { 4060 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 4061 } 4062 4063 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 4064 { 4065 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 4066 } 4067 4068 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 4069 { 4070 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 4071 } 4072 4073 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) 4074 { 4075 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; 4076 } 4077 4078 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) 4079 { 4080 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 4081 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4082 } 4083 4084 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) 4085 { 4086 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 4087 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4088 } 4089 4090 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) 4091 { 4092 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 && 4093 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4094 } 4095 4096 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 4097 { 4098 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 4099 } 4100 4101 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 4102 { 4103 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 4104 } 4105 4106 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 4107 { 4108 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 4109 } 4110 4111 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 4112 { 4113 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 4114 } 4115 4116 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 4117 { 4118 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4119 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 4120 } 4121 4122 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 4123 { 4124 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 4125 } 4126 4127 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 4128 { 4129 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4130 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 4131 } 4132 4133 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) 4134 { 4135 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0; 4136 } 4137 4138 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) 4139 { 4140 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1; 4141 } 4142 4143 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) 4144 { 4145 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0; 4146 } 4147 4148 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) 4149 { 4150 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4151 return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id)); 4152 } 4153 4154 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) 4155 { 4156 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4157 return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id)); 4158 } 4159 4160 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) 4161 { 4162 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); 4163 return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); 4164 } 4165 4166 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4167 { 4168 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4169 } 4170 4171 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4172 { 4173 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4174 } 4175 4176 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) 4177 { 4178 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; 4179 } 4180 4181 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) 4182 { 4183 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0; 4184 } 4185 4186 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) 4187 { 4188 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2; 4189 } 4190 4191 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4192 { 4193 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4194 } 4195 4196 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4197 { 4198 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4199 } 4200 4201 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 4202 { 4203 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); 4204 if (key >= 2) { 4205 return true; /* FEAT_CSV2_2 */ 4206 } 4207 if (key == 1) { 4208 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); 4209 return key >= 2; /* FEAT_CSV2_1p2 */ 4210 } 4211 return false; 4212 } 4213 4214 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4215 { 4216 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4217 } 4218 4219 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4220 { 4221 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4222 } 4223 4224 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4225 { 4226 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4227 } 4228 4229 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4230 { 4231 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4232 } 4233 4234 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4235 { 4236 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4237 } 4238 4239 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4240 { 4241 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4242 } 4243 4244 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4245 { 4246 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4247 } 4248 4249 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4250 { 4251 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4252 } 4253 4254 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4255 { 4256 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4257 } 4258 4259 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4260 { 4261 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4262 } 4263 4264 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4265 { 4266 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4267 } 4268 4269 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4270 { 4271 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4272 } 4273 4274 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) 4275 { 4276 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); 4277 } 4278 4279 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) 4280 { 4281 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; 4282 } 4283 4284 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) 4285 { 4286 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); 4287 } 4288 4289 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) 4290 { 4291 return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; 4292 } 4293 4294 /* 4295 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4296 */ 4297 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4298 { 4299 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4300 } 4301 4302 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4303 { 4304 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4305 } 4306 4307 static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id) 4308 { 4309 return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id); 4310 } 4311 4312 static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) 4313 { 4314 return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); 4315 } 4316 4317 static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) 4318 { 4319 return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); 4320 } 4321 4322 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4323 { 4324 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4325 } 4326 4327 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4328 { 4329 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4330 } 4331 4332 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4333 { 4334 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4335 } 4336 4337 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4338 { 4339 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4340 } 4341 4342 static inline bool isar_feature_any_half_evt(const ARMISARegisters *id) 4343 { 4344 return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id); 4345 } 4346 4347 static inline bool isar_feature_any_evt(const ARMISARegisters *id) 4348 { 4349 return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); 4350 } 4351 4352 /* 4353 * Forward to the above feature tests given an ARMCPU pointer. 4354 */ 4355 #define cpu_isar_feature(name, cpu) \ 4356 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4357 4358 #endif 4359