1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "exec/gdbstub.h" 29 #include "qapi/qapi-types-common.h" 30 #include "target/arm/multiprocessing.h" 31 #include "target/arm/gtimer.h" 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 61 #define EXCP_NMI 26 62 #define EXCP_VINMI 27 63 #define EXCP_VFNMI 28 64 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 65 66 #define ARMV7M_EXCP_RESET 1 67 #define ARMV7M_EXCP_NMI 2 68 #define ARMV7M_EXCP_HARD 3 69 #define ARMV7M_EXCP_MEM 4 70 #define ARMV7M_EXCP_BUS 5 71 #define ARMV7M_EXCP_USAGE 6 72 #define ARMV7M_EXCP_SECURE 7 73 #define ARMV7M_EXCP_SVC 11 74 #define ARMV7M_EXCP_DEBUG 12 75 #define ARMV7M_EXCP_PENDSV 14 76 #define ARMV7M_EXCP_SYSTICK 15 77 78 /* ARM-specific interrupt pending bits. */ 79 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 80 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 81 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 82 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 83 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4 84 #define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0 85 #define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1 86 87 /* The usual mapping for an AArch64 system register to its AArch32 88 * counterpart is for the 32 bit world to have access to the lower 89 * half only (with writes leaving the upper half untouched). It's 90 * therefore useful to be able to pass TCG the offset of the least 91 * significant half of a uint64_t struct member. 92 */ 93 #if HOST_BIG_ENDIAN 94 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 95 #define offsetofhigh32(S, M) offsetof(S, M) 96 #else 97 #define offsetoflow32(S, M) offsetof(S, M) 98 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 99 #endif 100 101 /* ARM-specific extra insn start words: 102 * 1: Conditional execution bits 103 * 2: Partial exception syndrome for data aborts 104 */ 105 #define TARGET_INSN_START_EXTRA_WORDS 2 106 107 /* The 2nd extra word holding syndrome info for data aborts does not use 108 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 109 * help the sleb128 encoder do a better job. 110 * When restoring the CPU state, we shift it back up. 111 */ 112 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 113 #define ARM_INSN_START_WORD2_SHIFT 13 114 115 /* We currently assume float and double are IEEE single and double 116 precision respectively. 117 Doing runtime conversions is tricky because VFP registers may contain 118 integer values (eg. as the result of a FTOSI instruction). 119 s<2n> maps to the least significant half of d<n> 120 s<2n+1> maps to the most significant half of d<n> 121 */ 122 123 /** 124 * DynamicGDBFeatureInfo: 125 * @desc: Contains the feature descriptions. 126 * @data: A union with data specific to the set of registers 127 * @cpregs_keys: Array that contains the corresponding Key of 128 * a given cpreg with the same order of the cpreg 129 * in the XML description. 130 */ 131 typedef struct DynamicGDBFeatureInfo { 132 GDBFeature desc; 133 union { 134 struct { 135 uint32_t *keys; 136 } cpregs; 137 } data; 138 } DynamicGDBFeatureInfo; 139 140 /* CPU state for each instance of a generic timer (in cp15 c14) */ 141 typedef struct ARMGenericTimer { 142 uint64_t cval; /* Timer CompareValue register */ 143 uint64_t ctl; /* Timer Control register */ 144 } ARMGenericTimer; 145 146 /* Define a maximum sized vector register. 147 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 148 * For 64-bit, this is a 2048-bit SVE register. 149 * 150 * Note that the mapping between S, D, and Q views of the register bank 151 * differs between AArch64 and AArch32. 152 * In AArch32: 153 * Qn = regs[n].d[1]:regs[n].d[0] 154 * Dn = regs[n / 2].d[n & 1] 155 * Sn = regs[n / 4].d[n % 4 / 2], 156 * bits 31..0 for even n, and bits 63..32 for odd n 157 * (and regs[16] to regs[31] are inaccessible) 158 * In AArch64: 159 * Zn = regs[n].d[*] 160 * Qn = regs[n].d[1]:regs[n].d[0] 161 * Dn = regs[n].d[0] 162 * Sn = regs[n].d[0] bits 31..0 163 * Hn = regs[n].d[0] bits 15..0 164 * 165 * This corresponds to the architecturally defined mapping between 166 * the two execution states, and means we do not need to explicitly 167 * map these registers when changing states. 168 * 169 * Align the data for use with TCG host vector operations. 170 */ 171 172 #ifdef TARGET_AARCH64 173 # define ARM_MAX_VQ 16 174 #else 175 # define ARM_MAX_VQ 1 176 #endif 177 178 typedef struct ARMVectorReg { 179 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 180 } ARMVectorReg; 181 182 #ifdef TARGET_AARCH64 183 /* In AArch32 mode, predicate registers do not exist at all. */ 184 typedef struct ARMPredicateReg { 185 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 186 } ARMPredicateReg; 187 188 /* In AArch32 mode, PAC keys do not exist at all. */ 189 typedef struct ARMPACKey { 190 uint64_t lo, hi; 191 } ARMPACKey; 192 #endif 193 194 /* See the commentary above the TBFLAG field definitions. */ 195 typedef struct CPUARMTBFlags { 196 uint32_t flags; 197 target_ulong flags2; 198 } CPUARMTBFlags; 199 200 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 201 202 typedef struct NVICState NVICState; 203 204 typedef struct CPUArchState { 205 /* Regs for current mode. */ 206 uint32_t regs[16]; 207 208 /* 32/64 switch only happens when taking and returning from 209 * exceptions so the overlap semantics are taken care of then 210 * instead of having a complicated union. 211 */ 212 /* Regs for A64 mode. */ 213 uint64_t xregs[32]; 214 uint64_t pc; 215 /* PSTATE isn't an architectural register for ARMv8. However, it is 216 * convenient for us to assemble the underlying state into a 32 bit format 217 * identical to the architectural format used for the SPSR. (This is also 218 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 219 * 'pstate' register are.) Of the PSTATE bits: 220 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 221 * semantics as for AArch32, as described in the comments on each field) 222 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 223 * DAIF (exception masks) are kept in env->daif 224 * BTYPE is kept in env->btype 225 * SM and ZA are kept in env->svcr 226 * all other bits are stored in their correct places in env->pstate 227 */ 228 uint32_t pstate; 229 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 230 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 231 232 /* Cached TBFLAGS state. See below for which bits are included. */ 233 CPUARMTBFlags hflags; 234 235 /* Frequently accessed CPSR bits are stored separately for efficiency. 236 This contains all the other bits. Use cpsr_{read,write} to access 237 the whole CPSR. */ 238 uint32_t uncached_cpsr; 239 uint32_t spsr; 240 241 /* Banked registers. */ 242 uint64_t banked_spsr[8]; 243 uint32_t banked_r13[8]; 244 uint32_t banked_r14[8]; 245 246 /* These hold r8-r12. */ 247 uint32_t usr_regs[5]; 248 uint32_t fiq_regs[5]; 249 250 /* cpsr flag cache for faster execution */ 251 uint32_t CF; /* 0 or 1 */ 252 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 253 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 254 uint32_t ZF; /* Z set if zero. */ 255 uint32_t QF; /* 0 or 1 */ 256 uint32_t GE; /* cpsr[19:16] */ 257 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 258 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 259 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 260 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 261 262 uint64_t elr_el[4]; /* AArch64 exception link regs */ 263 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 264 265 /* System control coprocessor (cp15) */ 266 struct { 267 uint32_t c0_cpuid; 268 union { /* Cache size selection */ 269 struct { 270 uint64_t _unused_csselr0; 271 uint64_t csselr_ns; 272 uint64_t _unused_csselr1; 273 uint64_t csselr_s; 274 }; 275 uint64_t csselr_el[4]; 276 }; 277 union { /* System control register. */ 278 struct { 279 uint64_t _unused_sctlr; 280 uint64_t sctlr_ns; 281 uint64_t hsctlr; 282 uint64_t sctlr_s; 283 }; 284 uint64_t sctlr_el[4]; 285 }; 286 uint64_t vsctlr; /* Virtualization System control register. */ 287 uint64_t cpacr_el1; /* Architectural feature access control register */ 288 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 289 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 290 uint64_t sder; /* Secure debug enable register. */ 291 uint32_t nsacr; /* Non-secure access control register. */ 292 union { /* MMU translation table base 0. */ 293 struct { 294 uint64_t _unused_ttbr0_0; 295 uint64_t ttbr0_ns; 296 uint64_t _unused_ttbr0_1; 297 uint64_t ttbr0_s; 298 }; 299 uint64_t ttbr0_el[4]; 300 }; 301 union { /* MMU translation table base 1. */ 302 struct { 303 uint64_t _unused_ttbr1_0; 304 uint64_t ttbr1_ns; 305 uint64_t _unused_ttbr1_1; 306 uint64_t ttbr1_s; 307 }; 308 uint64_t ttbr1_el[4]; 309 }; 310 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 311 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 312 /* MMU translation table base control. */ 313 uint64_t tcr_el[4]; 314 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 315 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 316 uint32_t c2_data; /* MPU data cacheable bits. */ 317 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 318 union { /* MMU domain access control register 319 * MPU write buffer control. 320 */ 321 struct { 322 uint64_t dacr_ns; 323 uint64_t dacr_s; 324 }; 325 struct { 326 uint64_t dacr32_el2; 327 }; 328 }; 329 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 330 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 331 uint64_t hcr_el2; /* Hypervisor configuration register */ 332 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 333 uint64_t scr_el3; /* Secure configuration register. */ 334 union { /* Fault status registers. */ 335 struct { 336 uint64_t ifsr_ns; 337 uint64_t ifsr_s; 338 }; 339 struct { 340 uint64_t ifsr32_el2; 341 }; 342 }; 343 union { 344 struct { 345 uint64_t _unused_dfsr; 346 uint64_t dfsr_ns; 347 uint64_t hsr; 348 uint64_t dfsr_s; 349 }; 350 uint64_t esr_el[4]; 351 }; 352 uint32_t c6_region[8]; /* MPU base/size registers. */ 353 union { /* Fault address registers. */ 354 struct { 355 uint64_t _unused_far0; 356 #if HOST_BIG_ENDIAN 357 uint32_t ifar_ns; 358 uint32_t dfar_ns; 359 uint32_t ifar_s; 360 uint32_t dfar_s; 361 #else 362 uint32_t dfar_ns; 363 uint32_t ifar_ns; 364 uint32_t dfar_s; 365 uint32_t ifar_s; 366 #endif 367 uint64_t _unused_far3; 368 }; 369 uint64_t far_el[4]; 370 }; 371 uint64_t hpfar_el2; 372 uint64_t hstr_el2; 373 union { /* Translation result. */ 374 struct { 375 uint64_t _unused_par_0; 376 uint64_t par_ns; 377 uint64_t _unused_par_1; 378 uint64_t par_s; 379 }; 380 uint64_t par_el[4]; 381 }; 382 383 uint32_t c9_insn; /* Cache lockdown registers. */ 384 uint32_t c9_data; 385 uint64_t c9_pmcr; /* performance monitor control register */ 386 uint64_t c9_pmcnten; /* perf monitor counter enables */ 387 uint64_t c9_pmovsr; /* perf monitor overflow status */ 388 uint64_t c9_pmuserenr; /* perf monitor user enable */ 389 uint64_t c9_pmselr; /* perf monitor counter selection register */ 390 uint64_t c9_pminten; /* perf monitor interrupt enables */ 391 union { /* Memory attribute redirection */ 392 struct { 393 #if HOST_BIG_ENDIAN 394 uint64_t _unused_mair_0; 395 uint32_t mair1_ns; 396 uint32_t mair0_ns; 397 uint64_t _unused_mair_1; 398 uint32_t mair1_s; 399 uint32_t mair0_s; 400 #else 401 uint64_t _unused_mair_0; 402 uint32_t mair0_ns; 403 uint32_t mair1_ns; 404 uint64_t _unused_mair_1; 405 uint32_t mair0_s; 406 uint32_t mair1_s; 407 #endif 408 }; 409 uint64_t mair_el[4]; 410 }; 411 union { /* vector base address register */ 412 struct { 413 uint64_t _unused_vbar; 414 uint64_t vbar_ns; 415 uint64_t hvbar; 416 uint64_t vbar_s; 417 }; 418 uint64_t vbar_el[4]; 419 }; 420 uint32_t mvbar; /* (monitor) vector base address register */ 421 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 422 struct { /* FCSE PID. */ 423 uint32_t fcseidr_ns; 424 uint32_t fcseidr_s; 425 }; 426 union { /* Context ID. */ 427 struct { 428 uint64_t _unused_contextidr_0; 429 uint64_t contextidr_ns; 430 uint64_t _unused_contextidr_1; 431 uint64_t contextidr_s; 432 }; 433 uint64_t contextidr_el[4]; 434 }; 435 union { /* User RW Thread register. */ 436 struct { 437 uint64_t tpidrurw_ns; 438 uint64_t tpidrprw_ns; 439 uint64_t htpidr; 440 uint64_t _tpidr_el3; 441 }; 442 uint64_t tpidr_el[4]; 443 }; 444 uint64_t tpidr2_el0; 445 /* The secure banks of these registers don't map anywhere */ 446 uint64_t tpidrurw_s; 447 uint64_t tpidrprw_s; 448 uint64_t tpidruro_s; 449 450 union { /* User RO Thread register. */ 451 uint64_t tpidruro_ns; 452 uint64_t tpidrro_el[1]; 453 }; 454 uint64_t c14_cntfrq; /* Counter Frequency register */ 455 uint64_t c14_cntkctl; /* Timer Control register */ 456 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 457 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 458 uint64_t cntpoff_el2; /* Counter Physical Offset register */ 459 ARMGenericTimer c14_timer[NUM_GTIMERS]; 460 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 461 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 462 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 463 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 464 uint32_t c15_threadid; /* TI debugger thread-ID. */ 465 uint32_t c15_config_base_address; /* SCU base address. */ 466 uint32_t c15_diagnostic; /* diagnostic register */ 467 uint32_t c15_power_diagnostic; 468 uint32_t c15_power_control; /* power control */ 469 uint64_t dbgbvr[16]; /* breakpoint value registers */ 470 uint64_t dbgbcr[16]; /* breakpoint control registers */ 471 uint64_t dbgwvr[16]; /* watchpoint value registers */ 472 uint64_t dbgwcr[16]; /* watchpoint control registers */ 473 uint64_t dbgclaim; /* DBGCLAIM bits */ 474 uint64_t mdscr_el1; 475 uint64_t oslsr_el1; /* OS Lock Status */ 476 uint64_t osdlr_el1; /* OS DoubleLock status */ 477 uint64_t mdcr_el2; 478 uint64_t mdcr_el3; 479 /* Stores the architectural value of the counter *the last time it was 480 * updated* by pmccntr_op_start. Accesses should always be surrounded 481 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 482 * architecturally-correct value is being read/set. 483 */ 484 uint64_t c15_ccnt; 485 /* Stores the delta between the architectural value and the underlying 486 * cycle count during normal operation. It is used to update c15_ccnt 487 * to be the correct architectural value before accesses. During 488 * accesses, c15_ccnt_delta contains the underlying count being used 489 * for the access, after which it reverts to the delta value in 490 * pmccntr_op_finish. 491 */ 492 uint64_t c15_ccnt_delta; 493 uint64_t c14_pmevcntr[31]; 494 uint64_t c14_pmevcntr_delta[31]; 495 uint64_t c14_pmevtyper[31]; 496 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 497 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 498 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 499 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 500 uint64_t gcr_el1; 501 uint64_t rgsr_el1; 502 503 /* Minimal RAS registers */ 504 uint64_t disr_el1; 505 uint64_t vdisr_el2; 506 uint64_t vsesr_el2; 507 508 /* 509 * Fine-Grained Trap registers. We store these as arrays so the 510 * access checking code doesn't have to manually select 511 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 512 * FEAT_FGT2 will add more elements to these arrays. 513 */ 514 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 515 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 516 uint64_t fgt_exec[1]; /* HFGITR */ 517 518 /* RME registers */ 519 uint64_t gpccr_el3; 520 uint64_t gptbr_el3; 521 uint64_t mfar_el3; 522 523 /* NV2 register */ 524 uint64_t vncr_el2; 525 } cp15; 526 527 struct { 528 /* M profile has up to 4 stack pointers: 529 * a Main Stack Pointer and a Process Stack Pointer for each 530 * of the Secure and Non-Secure states. (If the CPU doesn't support 531 * the security extension then it has only two SPs.) 532 * In QEMU we always store the currently active SP in regs[13], 533 * and the non-active SP for the current security state in 534 * v7m.other_sp. The stack pointers for the inactive security state 535 * are stored in other_ss_msp and other_ss_psp. 536 * switch_v7m_security_state() is responsible for rearranging them 537 * when we change security state. 538 */ 539 uint32_t other_sp; 540 uint32_t other_ss_msp; 541 uint32_t other_ss_psp; 542 uint32_t vecbase[M_REG_NUM_BANKS]; 543 uint32_t basepri[M_REG_NUM_BANKS]; 544 uint32_t control[M_REG_NUM_BANKS]; 545 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 546 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 547 uint32_t hfsr; /* HardFault Status */ 548 uint32_t dfsr; /* Debug Fault Status Register */ 549 uint32_t sfsr; /* Secure Fault Status Register */ 550 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 551 uint32_t bfar; /* BusFault Address */ 552 uint32_t sfar; /* Secure Fault Address Register */ 553 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 554 int exception; 555 uint32_t primask[M_REG_NUM_BANKS]; 556 uint32_t faultmask[M_REG_NUM_BANKS]; 557 uint32_t aircr; /* only holds r/w state if security extn implemented */ 558 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 559 uint32_t csselr[M_REG_NUM_BANKS]; 560 uint32_t scr[M_REG_NUM_BANKS]; 561 uint32_t msplim[M_REG_NUM_BANKS]; 562 uint32_t psplim[M_REG_NUM_BANKS]; 563 uint32_t fpcar[M_REG_NUM_BANKS]; 564 uint32_t fpccr[M_REG_NUM_BANKS]; 565 uint32_t fpdscr[M_REG_NUM_BANKS]; 566 uint32_t cpacr[M_REG_NUM_BANKS]; 567 uint32_t nsacr; 568 uint32_t ltpsize; 569 uint32_t vpr; 570 } v7m; 571 572 /* Information associated with an exception about to be taken: 573 * code which raises an exception must set cs->exception_index and 574 * the relevant parts of this structure; the cpu_do_interrupt function 575 * will then set the guest-visible registers as part of the exception 576 * entry process. 577 */ 578 struct { 579 uint32_t syndrome; /* AArch64 format syndrome register */ 580 uint32_t fsr; /* AArch32 format fault status register info */ 581 uint64_t vaddress; /* virtual addr associated with exception, if any */ 582 uint32_t target_el; /* EL the exception should be targeted for */ 583 /* If we implement EL2 we will also need to store information 584 * about the intermediate physical address for stage 2 faults. 585 */ 586 } exception; 587 588 /* Information associated with an SError */ 589 struct { 590 uint8_t pending; 591 uint8_t has_esr; 592 uint64_t esr; 593 } serror; 594 595 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 596 597 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 598 uint32_t irq_line_state; 599 600 /* Thumb-2 EE state. */ 601 uint32_t teecr; 602 uint32_t teehbr; 603 604 /* VFP coprocessor state. */ 605 struct { 606 ARMVectorReg zregs[32]; 607 608 #ifdef TARGET_AARCH64 609 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 610 #define FFR_PRED_NUM 16 611 ARMPredicateReg pregs[17]; 612 /* Scratch space for aa64 sve predicate temporary. */ 613 ARMPredicateReg preg_tmp; 614 #endif 615 616 /* We store these fpcsr fields separately for convenience. */ 617 uint32_t qc[4] QEMU_ALIGNED(16); 618 int vec_len; 619 int vec_stride; 620 621 uint32_t xregs[16]; 622 623 /* Scratch space for aa32 neon expansion. */ 624 uint32_t scratch[8]; 625 626 /* There are a number of distinct float control structures: 627 * 628 * fp_status: is the "normal" fp status. 629 * fp_status_fp16: used for half-precision calculations 630 * standard_fp_status : the ARM "Standard FPSCR Value" 631 * standard_fp_status_fp16 : used for half-precision 632 * calculations with the ARM "Standard FPSCR Value" 633 * 634 * Half-precision operations are governed by a separate 635 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 636 * status structure to control this. 637 * 638 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 639 * round-to-nearest and is used by any operations (generally 640 * Neon) which the architecture defines as controlled by the 641 * standard FPSCR value rather than the FPSCR. 642 * 643 * The "standard FPSCR but for fp16 ops" is needed because 644 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 645 * using a fixed value for it. 646 * 647 * To avoid having to transfer exception bits around, we simply 648 * say that the FPSCR cumulative exception flags are the logical 649 * OR of the flags in the four fp statuses. This relies on the 650 * only thing which needs to read the exception flags being 651 * an explicit FPSCR read. 652 */ 653 float_status fp_status; 654 float_status fp_status_f16; 655 float_status standard_fp_status; 656 float_status standard_fp_status_f16; 657 658 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 659 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 660 } vfp; 661 662 uint64_t exclusive_addr; 663 uint64_t exclusive_val; 664 /* 665 * Contains the 'val' for the second 64-bit register of LDXP, which comes 666 * from the higher address, not the high part of a complete 128-bit value. 667 * In some ways it might be more convenient to record the exclusive value 668 * as the low and high halves of a 128 bit data value, but the current 669 * semantics of these fields are baked into the migration format. 670 */ 671 uint64_t exclusive_high; 672 673 /* iwMMXt coprocessor state. */ 674 struct { 675 uint64_t regs[16]; 676 uint64_t val; 677 678 uint32_t cregs[16]; 679 } iwmmxt; 680 681 #ifdef TARGET_AARCH64 682 struct { 683 ARMPACKey apia; 684 ARMPACKey apib; 685 ARMPACKey apda; 686 ARMPACKey apdb; 687 ARMPACKey apga; 688 } keys; 689 690 uint64_t scxtnum_el[4]; 691 692 /* 693 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 694 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 695 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 696 * When SVL is less than the architectural maximum, the accessible 697 * storage is restricted, such that if the SVL is X bytes the guest can 698 * see only the bottom X elements of zarray[], and only the least 699 * significant X bytes of each element of the array. (In other words, 700 * the observable part is always square.) 701 * 702 * The ZA storage can also be considered as a set of square tiles of 703 * elements of different sizes. The mapping from tiles to the ZA array 704 * is architecturally defined, such that for tiles of elements of esz 705 * bytes, the Nth row (or "horizontal slice") of tile T is in 706 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 707 * in the ZA storage, because its rows are striped through the ZA array. 708 * 709 * Because this is so large, keep this toward the end of the reset area, 710 * to keep the offsets into the rest of the structure smaller. 711 */ 712 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 713 #endif 714 715 struct CPUBreakpoint *cpu_breakpoint[16]; 716 struct CPUWatchpoint *cpu_watchpoint[16]; 717 718 /* Optional fault info across tlb lookup. */ 719 ARMMMUFaultInfo *tlb_fi; 720 721 /* Fields up to this point are cleared by a CPU reset */ 722 struct {} end_reset_fields; 723 724 /* Fields after this point are preserved across CPU reset. */ 725 726 /* Internal CPU feature flags. */ 727 uint64_t features; 728 729 /* PMSAv7 MPU */ 730 struct { 731 uint32_t *drbar; 732 uint32_t *drsr; 733 uint32_t *dracr; 734 uint32_t rnr[M_REG_NUM_BANKS]; 735 } pmsav7; 736 737 /* PMSAv8 MPU */ 738 struct { 739 /* The PMSAv8 implementation also shares some PMSAv7 config 740 * and state: 741 * pmsav7.rnr (region number register) 742 * pmsav7_dregion (number of configured regions) 743 */ 744 uint32_t *rbar[M_REG_NUM_BANKS]; 745 uint32_t *rlar[M_REG_NUM_BANKS]; 746 uint32_t *hprbar; 747 uint32_t *hprlar; 748 uint32_t mair0[M_REG_NUM_BANKS]; 749 uint32_t mair1[M_REG_NUM_BANKS]; 750 uint32_t hprselr; 751 } pmsav8; 752 753 /* v8M SAU */ 754 struct { 755 uint32_t *rbar; 756 uint32_t *rlar; 757 uint32_t rnr; 758 uint32_t ctrl; 759 } sau; 760 761 #if !defined(CONFIG_USER_ONLY) 762 NVICState *nvic; 763 const struct arm_boot_info *boot_info; 764 /* Store GICv3CPUState to access from this struct */ 765 void *gicv3state; 766 #else /* CONFIG_USER_ONLY */ 767 /* For usermode syscall translation. */ 768 bool eabi; 769 #endif /* CONFIG_USER_ONLY */ 770 771 #ifdef TARGET_TAGGED_ADDRESSES 772 /* Linux syscall tagged address support */ 773 bool tagged_addr_enable; 774 #endif 775 } CPUARMState; 776 777 static inline void set_feature(CPUARMState *env, int feature) 778 { 779 env->features |= 1ULL << feature; 780 } 781 782 static inline void unset_feature(CPUARMState *env, int feature) 783 { 784 env->features &= ~(1ULL << feature); 785 } 786 787 /** 788 * ARMELChangeHookFn: 789 * type of a function which can be registered via arm_register_el_change_hook() 790 * to get callbacks when the CPU changes its exception level or mode. 791 */ 792 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 793 typedef struct ARMELChangeHook ARMELChangeHook; 794 struct ARMELChangeHook { 795 ARMELChangeHookFn *hook; 796 void *opaque; 797 QLIST_ENTRY(ARMELChangeHook) node; 798 }; 799 800 /* These values map onto the return values for 801 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 802 typedef enum ARMPSCIState { 803 PSCI_ON = 0, 804 PSCI_OFF = 1, 805 PSCI_ON_PENDING = 2 806 } ARMPSCIState; 807 808 typedef struct ARMISARegisters ARMISARegisters; 809 810 /* 811 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 812 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 813 * 814 * While processing properties during initialization, corresponding init bits 815 * are set for bits in sve_vq_map that have been set by properties. 816 * 817 * Bits set in supported represent valid vector lengths for the CPU type. 818 */ 819 typedef struct { 820 uint32_t map, init, supported; 821 } ARMVQMap; 822 823 /** 824 * ARMCPU: 825 * @env: #CPUARMState 826 * 827 * An ARM CPU core. 828 */ 829 struct ArchCPU { 830 CPUState parent_obj; 831 832 CPUARMState env; 833 834 /* Coprocessor information */ 835 GHashTable *cp_regs; 836 /* For marshalling (mostly coprocessor) register state between the 837 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 838 * we use these arrays. 839 */ 840 /* List of register indexes managed via these arrays; (full KVM style 841 * 64 bit indexes, not CPRegInfo 32 bit indexes) 842 */ 843 uint64_t *cpreg_indexes; 844 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 845 uint64_t *cpreg_values; 846 /* Length of the indexes, values, reset_values arrays */ 847 int32_t cpreg_array_len; 848 /* These are used only for migration: incoming data arrives in 849 * these fields and is sanity checked in post_load before copying 850 * to the working data structures above. 851 */ 852 uint64_t *cpreg_vmstate_indexes; 853 uint64_t *cpreg_vmstate_values; 854 int32_t cpreg_vmstate_array_len; 855 856 DynamicGDBFeatureInfo dyn_sysreg_feature; 857 DynamicGDBFeatureInfo dyn_svereg_feature; 858 DynamicGDBFeatureInfo dyn_m_systemreg_feature; 859 DynamicGDBFeatureInfo dyn_m_secextreg_feature; 860 861 /* Timers used by the generic (architected) timer */ 862 QEMUTimer *gt_timer[NUM_GTIMERS]; 863 /* 864 * Timer used by the PMU. Its state is restored after migration by 865 * pmu_op_finish() - it does not need other handling during migration 866 */ 867 QEMUTimer *pmu_timer; 868 /* GPIO outputs for generic timer */ 869 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 870 /* GPIO output for GICv3 maintenance interrupt signal */ 871 qemu_irq gicv3_maintenance_interrupt; 872 /* GPIO output for the PMU interrupt */ 873 qemu_irq pmu_interrupt; 874 875 /* MemoryRegion to use for secure physical accesses */ 876 MemoryRegion *secure_memory; 877 878 /* MemoryRegion to use for allocation tag accesses */ 879 MemoryRegion *tag_memory; 880 MemoryRegion *secure_tag_memory; 881 882 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 883 Object *idau; 884 885 /* 'compatible' string for this CPU for Linux device trees */ 886 const char *dtb_compatible; 887 888 /* PSCI version for this CPU 889 * Bits[31:16] = Major Version 890 * Bits[15:0] = Minor Version 891 */ 892 uint32_t psci_version; 893 894 /* Current power state, access guarded by BQL */ 895 ARMPSCIState power_state; 896 897 /* CPU has virtualization extension */ 898 bool has_el2; 899 /* CPU has security extension */ 900 bool has_el3; 901 /* CPU has PMU (Performance Monitor Unit) */ 902 bool has_pmu; 903 /* CPU has VFP */ 904 bool has_vfp; 905 /* CPU has 32 VFP registers */ 906 bool has_vfp_d32; 907 /* CPU has Neon */ 908 bool has_neon; 909 /* CPU has M-profile DSP extension */ 910 bool has_dsp; 911 912 /* CPU has memory protection unit */ 913 bool has_mpu; 914 /* PMSAv7 MPU number of supported regions */ 915 uint32_t pmsav7_dregion; 916 /* PMSAv8 MPU number of supported hyp regions */ 917 uint32_t pmsav8r_hdregion; 918 /* v8M SAU number of supported regions */ 919 uint32_t sau_sregion; 920 921 /* PSCI conduit used to invoke PSCI methods 922 * 0 - disabled, 1 - smc, 2 - hvc 923 */ 924 uint32_t psci_conduit; 925 926 /* For v8M, initial value of the Secure VTOR */ 927 uint32_t init_svtor; 928 /* For v8M, initial value of the Non-secure VTOR */ 929 uint32_t init_nsvtor; 930 931 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 932 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 933 */ 934 uint32_t kvm_target; 935 936 #ifdef CONFIG_KVM 937 /* KVM init features for this CPU */ 938 uint32_t kvm_init_features[7]; 939 940 /* KVM CPU state */ 941 942 /* KVM virtual time adjustment */ 943 bool kvm_adjvtime; 944 bool kvm_vtime_dirty; 945 uint64_t kvm_vtime; 946 947 /* KVM steal time */ 948 OnOffAuto kvm_steal_time; 949 #endif /* CONFIG_KVM */ 950 951 /* Uniprocessor system with MP extensions */ 952 bool mp_is_up; 953 954 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 955 * and the probe failed (so we need to report the error in realize) 956 */ 957 bool host_cpu_probe_failed; 958 959 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 960 * register. 961 */ 962 int32_t core_count; 963 964 /* The instance init functions for implementation-specific subclasses 965 * set these fields to specify the implementation-dependent values of 966 * various constant registers and reset values of non-constant 967 * registers. 968 * Some of these might become QOM properties eventually. 969 * Field names match the official register names as defined in the 970 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 971 * is used for reset values of non-constant registers; no reset_ 972 * prefix means a constant register. 973 * Some of these registers are split out into a substructure that 974 * is shared with the translators to control the ISA. 975 * 976 * Note that if you add an ID register to the ARMISARegisters struct 977 * you need to also update the 32-bit and 64-bit versions of the 978 * kvm_arm_get_host_cpu_features() function to correctly populate the 979 * field by reading the value from the KVM vCPU. 980 */ 981 struct ARMISARegisters { 982 uint32_t id_isar0; 983 uint32_t id_isar1; 984 uint32_t id_isar2; 985 uint32_t id_isar3; 986 uint32_t id_isar4; 987 uint32_t id_isar5; 988 uint32_t id_isar6; 989 uint32_t id_mmfr0; 990 uint32_t id_mmfr1; 991 uint32_t id_mmfr2; 992 uint32_t id_mmfr3; 993 uint32_t id_mmfr4; 994 uint32_t id_mmfr5; 995 uint32_t id_pfr0; 996 uint32_t id_pfr1; 997 uint32_t id_pfr2; 998 uint32_t mvfr0; 999 uint32_t mvfr1; 1000 uint32_t mvfr2; 1001 uint32_t id_dfr0; 1002 uint32_t id_dfr1; 1003 uint32_t dbgdidr; 1004 uint32_t dbgdevid; 1005 uint32_t dbgdevid1; 1006 uint64_t id_aa64isar0; 1007 uint64_t id_aa64isar1; 1008 uint64_t id_aa64isar2; 1009 uint64_t id_aa64pfr0; 1010 uint64_t id_aa64pfr1; 1011 uint64_t id_aa64mmfr0; 1012 uint64_t id_aa64mmfr1; 1013 uint64_t id_aa64mmfr2; 1014 uint64_t id_aa64mmfr3; 1015 uint64_t id_aa64dfr0; 1016 uint64_t id_aa64dfr1; 1017 uint64_t id_aa64zfr0; 1018 uint64_t id_aa64smfr0; 1019 uint64_t reset_pmcr_el0; 1020 } isar; 1021 uint64_t midr; 1022 uint32_t revidr; 1023 uint32_t reset_fpsid; 1024 uint64_t ctr; 1025 uint32_t reset_sctlr; 1026 uint64_t pmceid0; 1027 uint64_t pmceid1; 1028 uint32_t id_afr0; 1029 uint64_t id_aa64afr0; 1030 uint64_t id_aa64afr1; 1031 uint64_t clidr; 1032 uint64_t mp_affinity; /* MP ID without feature bits */ 1033 /* The elements of this array are the CCSIDR values for each cache, 1034 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1035 */ 1036 uint64_t ccsidr[16]; 1037 uint64_t reset_cbar; 1038 uint32_t reset_auxcr; 1039 bool reset_hivecs; 1040 uint8_t reset_l0gptsz; 1041 1042 /* 1043 * Intermediate values used during property parsing. 1044 * Once finalized, the values should be read from ID_AA64*. 1045 */ 1046 bool prop_pauth; 1047 bool prop_pauth_impdef; 1048 bool prop_pauth_qarma3; 1049 bool prop_lpa2; 1050 1051 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1052 uint8_t dcz_blocksize; 1053 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1054 uint8_t gm_blocksize; 1055 1056 uint64_t rvbar_prop; /* Property/input signals. */ 1057 1058 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1059 int gic_num_lrs; /* number of list registers */ 1060 int gic_vpribits; /* number of virtual priority bits */ 1061 int gic_vprebits; /* number of virtual preemption bits */ 1062 int gic_pribits; /* number of physical priority bits */ 1063 1064 /* Whether the cfgend input is high (i.e. this CPU should reset into 1065 * big-endian mode). This setting isn't used directly: instead it modifies 1066 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1067 * architecture version. 1068 */ 1069 bool cfgend; 1070 1071 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1072 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1073 1074 int32_t node_id; /* NUMA node this CPU belongs to */ 1075 1076 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1077 uint8_t device_irq_level; 1078 1079 /* Used to set the maximum vector length the cpu will support. */ 1080 uint32_t sve_max_vq; 1081 1082 #ifdef CONFIG_USER_ONLY 1083 /* Used to set the default vector length at process start. */ 1084 uint32_t sve_default_vq; 1085 uint32_t sme_default_vq; 1086 #endif 1087 1088 ARMVQMap sve_vq; 1089 ARMVQMap sme_vq; 1090 1091 /* Generic timer counter frequency, in Hz */ 1092 uint64_t gt_cntfrq_hz; 1093 }; 1094 1095 typedef struct ARMCPUInfo { 1096 const char *name; 1097 void (*initfn)(Object *obj); 1098 void (*class_init)(ObjectClass *oc, void *data); 1099 } ARMCPUInfo; 1100 1101 /** 1102 * ARMCPUClass: 1103 * @parent_realize: The parent class' realize handler. 1104 * @parent_phases: The parent class' reset phase handlers. 1105 * 1106 * An ARM CPU model. 1107 */ 1108 struct ARMCPUClass { 1109 CPUClass parent_class; 1110 1111 const ARMCPUInfo *info; 1112 DeviceRealize parent_realize; 1113 ResettablePhases parent_phases; 1114 }; 1115 1116 struct AArch64CPUClass { 1117 ARMCPUClass parent_class; 1118 }; 1119 1120 /* Callback functions for the generic timer's timers. */ 1121 void arm_gt_ptimer_cb(void *opaque); 1122 void arm_gt_vtimer_cb(void *opaque); 1123 void arm_gt_htimer_cb(void *opaque); 1124 void arm_gt_stimer_cb(void *opaque); 1125 void arm_gt_hvtimer_cb(void *opaque); 1126 1127 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1128 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1129 1130 void arm_cpu_post_init(Object *obj); 1131 1132 #define ARM_AFF0_SHIFT 0 1133 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1134 #define ARM_AFF1_SHIFT 8 1135 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1136 #define ARM_AFF2_SHIFT 16 1137 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1138 #define ARM_AFF3_SHIFT 32 1139 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1140 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1141 1142 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1143 #define ARM64_AFFINITY_MASK \ 1144 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1145 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1146 1147 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1148 1149 #ifndef CONFIG_USER_ONLY 1150 extern const VMStateDescription vmstate_arm_cpu; 1151 1152 void arm_cpu_do_interrupt(CPUState *cpu); 1153 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1154 1155 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1156 MemTxAttrs *attrs); 1157 #endif /* !CONFIG_USER_ONLY */ 1158 1159 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1160 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1161 1162 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1163 int cpuid, DumpState *s); 1164 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1165 int cpuid, DumpState *s); 1166 1167 /** 1168 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1169 * @cpu: CPU (which must have been freshly reset) 1170 * @target_el: exception level to put the CPU into 1171 * @secure: whether to put the CPU in secure state 1172 * 1173 * When QEMU is directly running a guest kernel at a lower level than 1174 * EL3 it implicitly emulates some aspects of the guest firmware. 1175 * This includes that on reset we need to configure the parts of the 1176 * CPU corresponding to EL3 so that the real guest code can run at its 1177 * lower exception level. This function does that post-reset CPU setup, 1178 * for when we do direct boot of a guest kernel, and for when we 1179 * emulate PSCI and similar firmware interfaces starting a CPU at a 1180 * lower exception level. 1181 * 1182 * @target_el must be an EL implemented by the CPU between 1 and 3. 1183 * We do not support dropping into a Secure EL other than 3. 1184 * 1185 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1186 */ 1187 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1188 1189 #ifdef TARGET_AARCH64 1190 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1191 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1192 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1193 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1194 int new_el, bool el0_a64); 1195 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1196 1197 /* 1198 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1199 * The byte at offset i from the start of the in-memory representation contains 1200 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1201 * lowest offsets are stored in the lowest memory addresses, then that nearly 1202 * matches QEMU's representation, which is to use an array of host-endian 1203 * uint64_t's, where the lower offsets are at the lower indices. To complete 1204 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1205 */ 1206 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1207 { 1208 #if HOST_BIG_ENDIAN 1209 int i; 1210 1211 for (i = 0; i < nr; ++i) { 1212 dst[i] = bswap64(src[i]); 1213 } 1214 1215 return dst; 1216 #else 1217 return src; 1218 #endif 1219 } 1220 1221 #else 1222 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1223 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1224 int n, bool a) 1225 { } 1226 #endif 1227 1228 void aarch64_sync_32_to_64(CPUARMState *env); 1229 void aarch64_sync_64_to_32(CPUARMState *env); 1230 1231 int fp_exception_el(CPUARMState *env, int cur_el); 1232 int sve_exception_el(CPUARMState *env, int cur_el); 1233 int sme_exception_el(CPUARMState *env, int cur_el); 1234 1235 /** 1236 * sve_vqm1_for_el_sm: 1237 * @env: CPUARMState 1238 * @el: exception level 1239 * @sm: streaming mode 1240 * 1241 * Compute the current vector length for @el & @sm, in units of 1242 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1243 * If @sm, compute for SVL, otherwise NVL. 1244 */ 1245 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1246 1247 /* Likewise, but using @sm = PSTATE.SM. */ 1248 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1249 1250 static inline bool is_a64(CPUARMState *env) 1251 { 1252 return env->aarch64; 1253 } 1254 1255 /** 1256 * pmu_op_start/finish 1257 * @env: CPUARMState 1258 * 1259 * Convert all PMU counters between their delta form (the typical mode when 1260 * they are enabled) and the guest-visible values. These two calls must 1261 * surround any action which might affect the counters. 1262 */ 1263 void pmu_op_start(CPUARMState *env); 1264 void pmu_op_finish(CPUARMState *env); 1265 1266 /* 1267 * Called when a PMU counter is due to overflow 1268 */ 1269 void arm_pmu_timer_cb(void *opaque); 1270 1271 /** 1272 * Functions to register as EL change hooks for PMU mode filtering 1273 */ 1274 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1275 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1276 1277 /* 1278 * pmu_init 1279 * @cpu: ARMCPU 1280 * 1281 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1282 * for the current configuration 1283 */ 1284 void pmu_init(ARMCPU *cpu); 1285 1286 /* SCTLR bit meanings. Several bits have been reused in newer 1287 * versions of the architecture; in that case we define constants 1288 * for both old and new bit meanings. Code which tests against those 1289 * bits should probably check or otherwise arrange that the CPU 1290 * is the architectural version it expects. 1291 */ 1292 #define SCTLR_M (1U << 0) 1293 #define SCTLR_A (1U << 1) 1294 #define SCTLR_C (1U << 2) 1295 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1296 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1297 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1298 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1299 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1300 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1301 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1302 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1303 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1304 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1305 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1306 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1307 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1308 #define SCTLR_SED (1U << 8) /* v8 onward */ 1309 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1310 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1311 #define SCTLR_F (1U << 10) /* up to v6 */ 1312 #define SCTLR_SW (1U << 10) /* v7 */ 1313 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1314 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1315 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1316 #define SCTLR_I (1U << 12) 1317 #define SCTLR_V (1U << 13) /* AArch32 only */ 1318 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1319 #define SCTLR_RR (1U << 14) /* up to v7 */ 1320 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1321 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1322 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1323 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1324 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1325 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1326 #define SCTLR_BR (1U << 17) /* PMSA only */ 1327 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1328 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1329 #define SCTLR_WXN (1U << 19) 1330 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1331 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1332 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1333 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1334 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1335 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1336 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1337 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1338 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1339 #define SCTLR_VE (1U << 24) /* up to v7 */ 1340 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1341 #define SCTLR_EE (1U << 25) 1342 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1343 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1344 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1345 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1346 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1347 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1348 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1349 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1350 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1351 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1352 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1353 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1354 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1355 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1356 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1357 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1358 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1359 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1360 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1361 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1362 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1363 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1364 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1365 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1366 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1367 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1368 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1369 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1370 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1371 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1372 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1373 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1374 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1375 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1376 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1377 1378 #define CPSR_M (0x1fU) 1379 #define CPSR_T (1U << 5) 1380 #define CPSR_F (1U << 6) 1381 #define CPSR_I (1U << 7) 1382 #define CPSR_A (1U << 8) 1383 #define CPSR_E (1U << 9) 1384 #define CPSR_IT_2_7 (0xfc00U) 1385 #define CPSR_GE (0xfU << 16) 1386 #define CPSR_IL (1U << 20) 1387 #define CPSR_DIT (1U << 21) 1388 #define CPSR_PAN (1U << 22) 1389 #define CPSR_SSBS (1U << 23) 1390 #define CPSR_J (1U << 24) 1391 #define CPSR_IT_0_1 (3U << 25) 1392 #define CPSR_Q (1U << 27) 1393 #define CPSR_V (1U << 28) 1394 #define CPSR_C (1U << 29) 1395 #define CPSR_Z (1U << 30) 1396 #define CPSR_N (1U << 31) 1397 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1398 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1399 #define ISR_FS (1U << 9) 1400 #define ISR_IS (1U << 10) 1401 1402 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1403 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1404 | CPSR_NZCV) 1405 /* Bits writable in user mode. */ 1406 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1407 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1408 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1409 1410 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1411 #define XPSR_EXCP 0x1ffU 1412 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1413 #define XPSR_IT_2_7 CPSR_IT_2_7 1414 #define XPSR_GE CPSR_GE 1415 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1416 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1417 #define XPSR_IT_0_1 CPSR_IT_0_1 1418 #define XPSR_Q CPSR_Q 1419 #define XPSR_V CPSR_V 1420 #define XPSR_C CPSR_C 1421 #define XPSR_Z CPSR_Z 1422 #define XPSR_N CPSR_N 1423 #define XPSR_NZCV CPSR_NZCV 1424 #define XPSR_IT CPSR_IT 1425 1426 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1427 * Only these are valid when in AArch64 mode; in 1428 * AArch32 mode SPSRs are basically CPSR-format. 1429 */ 1430 #define PSTATE_SP (1U) 1431 #define PSTATE_M (0xFU) 1432 #define PSTATE_nRW (1U << 4) 1433 #define PSTATE_F (1U << 6) 1434 #define PSTATE_I (1U << 7) 1435 #define PSTATE_A (1U << 8) 1436 #define PSTATE_D (1U << 9) 1437 #define PSTATE_BTYPE (3U << 10) 1438 #define PSTATE_SSBS (1U << 12) 1439 #define PSTATE_ALLINT (1U << 13) 1440 #define PSTATE_IL (1U << 20) 1441 #define PSTATE_SS (1U << 21) 1442 #define PSTATE_PAN (1U << 22) 1443 #define PSTATE_UAO (1U << 23) 1444 #define PSTATE_DIT (1U << 24) 1445 #define PSTATE_TCO (1U << 25) 1446 #define PSTATE_V (1U << 28) 1447 #define PSTATE_C (1U << 29) 1448 #define PSTATE_Z (1U << 30) 1449 #define PSTATE_N (1U << 31) 1450 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1451 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1452 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1453 /* Mode values for AArch64 */ 1454 #define PSTATE_MODE_EL3h 13 1455 #define PSTATE_MODE_EL3t 12 1456 #define PSTATE_MODE_EL2h 9 1457 #define PSTATE_MODE_EL2t 8 1458 #define PSTATE_MODE_EL1h 5 1459 #define PSTATE_MODE_EL1t 4 1460 #define PSTATE_MODE_EL0t 0 1461 1462 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1463 FIELD(SVCR, SM, 0, 1) 1464 FIELD(SVCR, ZA, 1, 1) 1465 1466 /* Fields for SMCR_ELx. */ 1467 FIELD(SMCR, LEN, 0, 4) 1468 FIELD(SMCR, FA64, 31, 1) 1469 1470 /* Write a new value to v7m.exception, thus transitioning into or out 1471 * of Handler mode; this may result in a change of active stack pointer. 1472 */ 1473 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1474 1475 /* Map EL and handler into a PSTATE_MODE. */ 1476 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1477 { 1478 return (el << 2) | handler; 1479 } 1480 1481 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1482 * interprocessing, so we don't attempt to sync with the cpsr state used by 1483 * the 32 bit decoder. 1484 */ 1485 static inline uint32_t pstate_read(CPUARMState *env) 1486 { 1487 int ZF; 1488 1489 ZF = (env->ZF == 0); 1490 return (env->NF & 0x80000000) | (ZF << 30) 1491 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1492 | env->pstate | env->daif | (env->btype << 10); 1493 } 1494 1495 static inline void pstate_write(CPUARMState *env, uint32_t val) 1496 { 1497 env->ZF = (~val) & PSTATE_Z; 1498 env->NF = val; 1499 env->CF = (val >> 29) & 1; 1500 env->VF = (val << 3) & 0x80000000; 1501 env->daif = val & PSTATE_DAIF; 1502 env->btype = (val >> 10) & 3; 1503 env->pstate = val & ~CACHED_PSTATE_BITS; 1504 } 1505 1506 /* Return the current CPSR value. */ 1507 uint32_t cpsr_read(CPUARMState *env); 1508 1509 typedef enum CPSRWriteType { 1510 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1511 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1512 CPSRWriteRaw = 2, 1513 /* trust values, no reg bank switch, no hflags rebuild */ 1514 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1515 } CPSRWriteType; 1516 1517 /* 1518 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1519 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1520 * correspond to TB flags bits cached in the hflags, unless @write_type 1521 * is CPSRWriteRaw. 1522 */ 1523 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1524 CPSRWriteType write_type); 1525 1526 /* Return the current xPSR value. */ 1527 static inline uint32_t xpsr_read(CPUARMState *env) 1528 { 1529 int ZF; 1530 ZF = (env->ZF == 0); 1531 return (env->NF & 0x80000000) | (ZF << 30) 1532 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1533 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1534 | ((env->condexec_bits & 0xfc) << 8) 1535 | (env->GE << 16) 1536 | env->v7m.exception; 1537 } 1538 1539 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1540 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1541 { 1542 if (mask & XPSR_NZCV) { 1543 env->ZF = (~val) & XPSR_Z; 1544 env->NF = val; 1545 env->CF = (val >> 29) & 1; 1546 env->VF = (val << 3) & 0x80000000; 1547 } 1548 if (mask & XPSR_Q) { 1549 env->QF = ((val & XPSR_Q) != 0); 1550 } 1551 if (mask & XPSR_GE) { 1552 env->GE = (val & XPSR_GE) >> 16; 1553 } 1554 #ifndef CONFIG_USER_ONLY 1555 if (mask & XPSR_T) { 1556 env->thumb = ((val & XPSR_T) != 0); 1557 } 1558 if (mask & XPSR_IT_0_1) { 1559 env->condexec_bits &= ~3; 1560 env->condexec_bits |= (val >> 25) & 3; 1561 } 1562 if (mask & XPSR_IT_2_7) { 1563 env->condexec_bits &= 3; 1564 env->condexec_bits |= (val >> 8) & 0xfc; 1565 } 1566 if (mask & XPSR_EXCP) { 1567 /* Note that this only happens on exception exit */ 1568 write_v7m_exception(env, val & XPSR_EXCP); 1569 } 1570 #endif 1571 } 1572 1573 #define HCR_VM (1ULL << 0) 1574 #define HCR_SWIO (1ULL << 1) 1575 #define HCR_PTW (1ULL << 2) 1576 #define HCR_FMO (1ULL << 3) 1577 #define HCR_IMO (1ULL << 4) 1578 #define HCR_AMO (1ULL << 5) 1579 #define HCR_VF (1ULL << 6) 1580 #define HCR_VI (1ULL << 7) 1581 #define HCR_VSE (1ULL << 8) 1582 #define HCR_FB (1ULL << 9) 1583 #define HCR_BSU_MASK (3ULL << 10) 1584 #define HCR_DC (1ULL << 12) 1585 #define HCR_TWI (1ULL << 13) 1586 #define HCR_TWE (1ULL << 14) 1587 #define HCR_TID0 (1ULL << 15) 1588 #define HCR_TID1 (1ULL << 16) 1589 #define HCR_TID2 (1ULL << 17) 1590 #define HCR_TID3 (1ULL << 18) 1591 #define HCR_TSC (1ULL << 19) 1592 #define HCR_TIDCP (1ULL << 20) 1593 #define HCR_TACR (1ULL << 21) 1594 #define HCR_TSW (1ULL << 22) 1595 #define HCR_TPCP (1ULL << 23) 1596 #define HCR_TPU (1ULL << 24) 1597 #define HCR_TTLB (1ULL << 25) 1598 #define HCR_TVM (1ULL << 26) 1599 #define HCR_TGE (1ULL << 27) 1600 #define HCR_TDZ (1ULL << 28) 1601 #define HCR_HCD (1ULL << 29) 1602 #define HCR_TRVM (1ULL << 30) 1603 #define HCR_RW (1ULL << 31) 1604 #define HCR_CD (1ULL << 32) 1605 #define HCR_ID (1ULL << 33) 1606 #define HCR_E2H (1ULL << 34) 1607 #define HCR_TLOR (1ULL << 35) 1608 #define HCR_TERR (1ULL << 36) 1609 #define HCR_TEA (1ULL << 37) 1610 #define HCR_MIOCNCE (1ULL << 38) 1611 #define HCR_TME (1ULL << 39) 1612 #define HCR_APK (1ULL << 40) 1613 #define HCR_API (1ULL << 41) 1614 #define HCR_NV (1ULL << 42) 1615 #define HCR_NV1 (1ULL << 43) 1616 #define HCR_AT (1ULL << 44) 1617 #define HCR_NV2 (1ULL << 45) 1618 #define HCR_FWB (1ULL << 46) 1619 #define HCR_FIEN (1ULL << 47) 1620 #define HCR_GPF (1ULL << 48) 1621 #define HCR_TID4 (1ULL << 49) 1622 #define HCR_TICAB (1ULL << 50) 1623 #define HCR_AMVOFFEN (1ULL << 51) 1624 #define HCR_TOCU (1ULL << 52) 1625 #define HCR_ENSCXT (1ULL << 53) 1626 #define HCR_TTLBIS (1ULL << 54) 1627 #define HCR_TTLBOS (1ULL << 55) 1628 #define HCR_ATA (1ULL << 56) 1629 #define HCR_DCT (1ULL << 57) 1630 #define HCR_TID5 (1ULL << 58) 1631 #define HCR_TWEDEN (1ULL << 59) 1632 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1633 1634 #define SCR_NS (1ULL << 0) 1635 #define SCR_IRQ (1ULL << 1) 1636 #define SCR_FIQ (1ULL << 2) 1637 #define SCR_EA (1ULL << 3) 1638 #define SCR_FW (1ULL << 4) 1639 #define SCR_AW (1ULL << 5) 1640 #define SCR_NET (1ULL << 6) 1641 #define SCR_SMD (1ULL << 7) 1642 #define SCR_HCE (1ULL << 8) 1643 #define SCR_SIF (1ULL << 9) 1644 #define SCR_RW (1ULL << 10) 1645 #define SCR_ST (1ULL << 11) 1646 #define SCR_TWI (1ULL << 12) 1647 #define SCR_TWE (1ULL << 13) 1648 #define SCR_TLOR (1ULL << 14) 1649 #define SCR_TERR (1ULL << 15) 1650 #define SCR_APK (1ULL << 16) 1651 #define SCR_API (1ULL << 17) 1652 #define SCR_EEL2 (1ULL << 18) 1653 #define SCR_EASE (1ULL << 19) 1654 #define SCR_NMEA (1ULL << 20) 1655 #define SCR_FIEN (1ULL << 21) 1656 #define SCR_ENSCXT (1ULL << 25) 1657 #define SCR_ATA (1ULL << 26) 1658 #define SCR_FGTEN (1ULL << 27) 1659 #define SCR_ECVEN (1ULL << 28) 1660 #define SCR_TWEDEN (1ULL << 29) 1661 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1662 #define SCR_TME (1ULL << 34) 1663 #define SCR_AMVOFFEN (1ULL << 35) 1664 #define SCR_ENAS0 (1ULL << 36) 1665 #define SCR_ADEN (1ULL << 37) 1666 #define SCR_HXEN (1ULL << 38) 1667 #define SCR_TRNDR (1ULL << 40) 1668 #define SCR_ENTP2 (1ULL << 41) 1669 #define SCR_GPF (1ULL << 48) 1670 #define SCR_NSE (1ULL << 62) 1671 1672 /* Return the current FPSCR value. */ 1673 uint32_t vfp_get_fpscr(CPUARMState *env); 1674 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1675 1676 /* FPCR, Floating Point Control Register 1677 * FPSR, Floating Poiht Status Register 1678 * 1679 * For A64 the FPSCR is split into two logically distinct registers, 1680 * FPCR and FPSR. However since they still use non-overlapping bits 1681 * we store the underlying state in fpscr and just mask on read/write. 1682 */ 1683 #define FPSR_MASK 0xf800009f 1684 #define FPCR_MASK 0x07ff9f00 1685 1686 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1687 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1688 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1689 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1690 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1691 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1692 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1693 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1694 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1695 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1696 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1697 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1698 #define FPCR_V (1 << 28) /* FP overflow flag */ 1699 #define FPCR_C (1 << 29) /* FP carry flag */ 1700 #define FPCR_Z (1 << 30) /* FP zero flag */ 1701 #define FPCR_N (1 << 31) /* FP negative flag */ 1702 1703 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1704 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1705 #define FPCR_LTPSIZE_LENGTH 3 1706 1707 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1708 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1709 1710 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1711 { 1712 return vfp_get_fpscr(env) & FPSR_MASK; 1713 } 1714 1715 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1716 { 1717 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1718 vfp_set_fpscr(env, new_fpscr); 1719 } 1720 1721 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1722 { 1723 return vfp_get_fpscr(env) & FPCR_MASK; 1724 } 1725 1726 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1727 { 1728 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1729 vfp_set_fpscr(env, new_fpscr); 1730 } 1731 1732 enum arm_cpu_mode { 1733 ARM_CPU_MODE_USR = 0x10, 1734 ARM_CPU_MODE_FIQ = 0x11, 1735 ARM_CPU_MODE_IRQ = 0x12, 1736 ARM_CPU_MODE_SVC = 0x13, 1737 ARM_CPU_MODE_MON = 0x16, 1738 ARM_CPU_MODE_ABT = 0x17, 1739 ARM_CPU_MODE_HYP = 0x1a, 1740 ARM_CPU_MODE_UND = 0x1b, 1741 ARM_CPU_MODE_SYS = 0x1f 1742 }; 1743 1744 /* VFP system registers. */ 1745 #define ARM_VFP_FPSID 0 1746 #define ARM_VFP_FPSCR 1 1747 #define ARM_VFP_MVFR2 5 1748 #define ARM_VFP_MVFR1 6 1749 #define ARM_VFP_MVFR0 7 1750 #define ARM_VFP_FPEXC 8 1751 #define ARM_VFP_FPINST 9 1752 #define ARM_VFP_FPINST2 10 1753 /* These ones are M-profile only */ 1754 #define ARM_VFP_FPSCR_NZCVQC 2 1755 #define ARM_VFP_VPR 12 1756 #define ARM_VFP_P0 13 1757 #define ARM_VFP_FPCXT_NS 14 1758 #define ARM_VFP_FPCXT_S 15 1759 1760 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1761 #define QEMU_VFP_FPSCR_NZCV 0xffff 1762 1763 /* iwMMXt coprocessor control registers. */ 1764 #define ARM_IWMMXT_wCID 0 1765 #define ARM_IWMMXT_wCon 1 1766 #define ARM_IWMMXT_wCSSF 2 1767 #define ARM_IWMMXT_wCASF 3 1768 #define ARM_IWMMXT_wCGR0 8 1769 #define ARM_IWMMXT_wCGR1 9 1770 #define ARM_IWMMXT_wCGR2 10 1771 #define ARM_IWMMXT_wCGR3 11 1772 1773 /* V7M CCR bits */ 1774 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1775 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1776 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1777 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1778 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1779 FIELD(V7M_CCR, STKALIGN, 9, 1) 1780 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1781 FIELD(V7M_CCR, DC, 16, 1) 1782 FIELD(V7M_CCR, IC, 17, 1) 1783 FIELD(V7M_CCR, BP, 18, 1) 1784 FIELD(V7M_CCR, LOB, 19, 1) 1785 FIELD(V7M_CCR, TRD, 20, 1) 1786 1787 /* V7M SCR bits */ 1788 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1789 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1790 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1791 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1792 1793 /* V7M AIRCR bits */ 1794 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1795 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1796 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1797 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1798 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1799 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1800 FIELD(V7M_AIRCR, PRIS, 14, 1) 1801 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1802 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1803 1804 /* V7M CFSR bits for MMFSR */ 1805 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1806 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1807 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1808 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1809 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1810 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1811 1812 /* V7M CFSR bits for BFSR */ 1813 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1814 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1815 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1816 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1817 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1818 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1819 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1820 1821 /* V7M CFSR bits for UFSR */ 1822 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1823 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1824 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1825 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1826 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1827 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1828 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1829 1830 /* V7M CFSR bit masks covering all of the subregister bits */ 1831 FIELD(V7M_CFSR, MMFSR, 0, 8) 1832 FIELD(V7M_CFSR, BFSR, 8, 8) 1833 FIELD(V7M_CFSR, UFSR, 16, 16) 1834 1835 /* V7M HFSR bits */ 1836 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1837 FIELD(V7M_HFSR, FORCED, 30, 1) 1838 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1839 1840 /* V7M DFSR bits */ 1841 FIELD(V7M_DFSR, HALTED, 0, 1) 1842 FIELD(V7M_DFSR, BKPT, 1, 1) 1843 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1844 FIELD(V7M_DFSR, VCATCH, 3, 1) 1845 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1846 1847 /* V7M SFSR bits */ 1848 FIELD(V7M_SFSR, INVEP, 0, 1) 1849 FIELD(V7M_SFSR, INVIS, 1, 1) 1850 FIELD(V7M_SFSR, INVER, 2, 1) 1851 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1852 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1853 FIELD(V7M_SFSR, LSPERR, 5, 1) 1854 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1855 FIELD(V7M_SFSR, LSERR, 7, 1) 1856 1857 /* v7M MPU_CTRL bits */ 1858 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1859 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1860 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1861 1862 /* v7M CLIDR bits */ 1863 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1864 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1865 FIELD(V7M_CLIDR, LOC, 24, 3) 1866 FIELD(V7M_CLIDR, LOUU, 27, 3) 1867 FIELD(V7M_CLIDR, ICB, 30, 2) 1868 1869 FIELD(V7M_CSSELR, IND, 0, 1) 1870 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1871 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1872 * define a mask for this and check that it doesn't permit running off 1873 * the end of the array. 1874 */ 1875 FIELD(V7M_CSSELR, INDEX, 0, 4) 1876 1877 /* v7M FPCCR bits */ 1878 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1879 FIELD(V7M_FPCCR, USER, 1, 1) 1880 FIELD(V7M_FPCCR, S, 2, 1) 1881 FIELD(V7M_FPCCR, THREAD, 3, 1) 1882 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1883 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1884 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1885 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1886 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1887 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1888 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1889 FIELD(V7M_FPCCR, RES0, 11, 15) 1890 FIELD(V7M_FPCCR, TS, 26, 1) 1891 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1892 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1893 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1894 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1895 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1896 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1897 #define R_V7M_FPCCR_BANKED_MASK \ 1898 (R_V7M_FPCCR_LSPACT_MASK | \ 1899 R_V7M_FPCCR_USER_MASK | \ 1900 R_V7M_FPCCR_THREAD_MASK | \ 1901 R_V7M_FPCCR_MMRDY_MASK | \ 1902 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1903 R_V7M_FPCCR_UFRDY_MASK | \ 1904 R_V7M_FPCCR_ASPEN_MASK) 1905 1906 /* v7M VPR bits */ 1907 FIELD(V7M_VPR, P0, 0, 16) 1908 FIELD(V7M_VPR, MASK01, 16, 4) 1909 FIELD(V7M_VPR, MASK23, 20, 4) 1910 1911 /* 1912 * System register ID fields. 1913 */ 1914 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1915 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1916 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1917 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1918 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1919 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1920 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1921 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1922 FIELD(CLIDR_EL1, LOC, 24, 3) 1923 FIELD(CLIDR_EL1, LOUU, 27, 3) 1924 FIELD(CLIDR_EL1, ICB, 30, 3) 1925 1926 /* When FEAT_CCIDX is implemented */ 1927 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1928 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1929 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1930 1931 /* When FEAT_CCIDX is not implemented */ 1932 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1933 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1934 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1935 1936 FIELD(CTR_EL0, IMINLINE, 0, 4) 1937 FIELD(CTR_EL0, L1IP, 14, 2) 1938 FIELD(CTR_EL0, DMINLINE, 16, 4) 1939 FIELD(CTR_EL0, ERG, 20, 4) 1940 FIELD(CTR_EL0, CWG, 24, 4) 1941 FIELD(CTR_EL0, IDC, 28, 1) 1942 FIELD(CTR_EL0, DIC, 29, 1) 1943 FIELD(CTR_EL0, TMINLINE, 32, 6) 1944 1945 FIELD(MIDR_EL1, REVISION, 0, 4) 1946 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1947 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1948 FIELD(MIDR_EL1, VARIANT, 20, 4) 1949 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1950 1951 FIELD(ID_ISAR0, SWAP, 0, 4) 1952 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1953 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1954 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1955 FIELD(ID_ISAR0, COPROC, 16, 4) 1956 FIELD(ID_ISAR0, DEBUG, 20, 4) 1957 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1958 1959 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1960 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1961 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1962 FIELD(ID_ISAR1, EXTEND, 12, 4) 1963 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1964 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1965 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1966 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1967 1968 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1969 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1970 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1971 FIELD(ID_ISAR2, MULT, 12, 4) 1972 FIELD(ID_ISAR2, MULTS, 16, 4) 1973 FIELD(ID_ISAR2, MULTU, 20, 4) 1974 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1975 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1976 1977 FIELD(ID_ISAR3, SATURATE, 0, 4) 1978 FIELD(ID_ISAR3, SIMD, 4, 4) 1979 FIELD(ID_ISAR3, SVC, 8, 4) 1980 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1981 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1982 FIELD(ID_ISAR3, T32COPY, 20, 4) 1983 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1984 FIELD(ID_ISAR3, T32EE, 28, 4) 1985 1986 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1987 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1988 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1989 FIELD(ID_ISAR4, SMC, 12, 4) 1990 FIELD(ID_ISAR4, BARRIER, 16, 4) 1991 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1992 FIELD(ID_ISAR4, PSR_M, 24, 4) 1993 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1994 1995 FIELD(ID_ISAR5, SEVL, 0, 4) 1996 FIELD(ID_ISAR5, AES, 4, 4) 1997 FIELD(ID_ISAR5, SHA1, 8, 4) 1998 FIELD(ID_ISAR5, SHA2, 12, 4) 1999 FIELD(ID_ISAR5, CRC32, 16, 4) 2000 FIELD(ID_ISAR5, RDM, 24, 4) 2001 FIELD(ID_ISAR5, VCMA, 28, 4) 2002 2003 FIELD(ID_ISAR6, JSCVT, 0, 4) 2004 FIELD(ID_ISAR6, DP, 4, 4) 2005 FIELD(ID_ISAR6, FHM, 8, 4) 2006 FIELD(ID_ISAR6, SB, 12, 4) 2007 FIELD(ID_ISAR6, SPECRES, 16, 4) 2008 FIELD(ID_ISAR6, BF16, 20, 4) 2009 FIELD(ID_ISAR6, I8MM, 24, 4) 2010 2011 FIELD(ID_MMFR0, VMSA, 0, 4) 2012 FIELD(ID_MMFR0, PMSA, 4, 4) 2013 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2014 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2015 FIELD(ID_MMFR0, TCM, 16, 4) 2016 FIELD(ID_MMFR0, AUXREG, 20, 4) 2017 FIELD(ID_MMFR0, FCSE, 24, 4) 2018 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2019 2020 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2021 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2022 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2023 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2024 FIELD(ID_MMFR1, L1HVD, 16, 4) 2025 FIELD(ID_MMFR1, L1UNI, 20, 4) 2026 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2027 FIELD(ID_MMFR1, BPRED, 28, 4) 2028 2029 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2030 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2031 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2032 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2033 FIELD(ID_MMFR2, UNITLB, 16, 4) 2034 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2035 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2036 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2037 2038 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2039 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2040 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2041 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2042 FIELD(ID_MMFR3, PAN, 16, 4) 2043 FIELD(ID_MMFR3, COHWALK, 20, 4) 2044 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2045 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2046 2047 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2048 FIELD(ID_MMFR4, AC2, 4, 4) 2049 FIELD(ID_MMFR4, XNX, 8, 4) 2050 FIELD(ID_MMFR4, CNP, 12, 4) 2051 FIELD(ID_MMFR4, HPDS, 16, 4) 2052 FIELD(ID_MMFR4, LSM, 20, 4) 2053 FIELD(ID_MMFR4, CCIDX, 24, 4) 2054 FIELD(ID_MMFR4, EVT, 28, 4) 2055 2056 FIELD(ID_MMFR5, ETS, 0, 4) 2057 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2058 2059 FIELD(ID_PFR0, STATE0, 0, 4) 2060 FIELD(ID_PFR0, STATE1, 4, 4) 2061 FIELD(ID_PFR0, STATE2, 8, 4) 2062 FIELD(ID_PFR0, STATE3, 12, 4) 2063 FIELD(ID_PFR0, CSV2, 16, 4) 2064 FIELD(ID_PFR0, AMU, 20, 4) 2065 FIELD(ID_PFR0, DIT, 24, 4) 2066 FIELD(ID_PFR0, RAS, 28, 4) 2067 2068 FIELD(ID_PFR1, PROGMOD, 0, 4) 2069 FIELD(ID_PFR1, SECURITY, 4, 4) 2070 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2071 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2072 FIELD(ID_PFR1, GENTIMER, 16, 4) 2073 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2074 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2075 FIELD(ID_PFR1, GIC, 28, 4) 2076 2077 FIELD(ID_PFR2, CSV3, 0, 4) 2078 FIELD(ID_PFR2, SSBS, 4, 4) 2079 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2080 2081 FIELD(ID_AA64ISAR0, AES, 4, 4) 2082 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2083 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2084 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2085 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2086 FIELD(ID_AA64ISAR0, TME, 24, 4) 2087 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2088 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2089 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2090 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2091 FIELD(ID_AA64ISAR0, DP, 44, 4) 2092 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2093 FIELD(ID_AA64ISAR0, TS, 52, 4) 2094 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2095 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2096 2097 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2098 FIELD(ID_AA64ISAR1, APA, 4, 4) 2099 FIELD(ID_AA64ISAR1, API, 8, 4) 2100 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2101 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2102 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2103 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2104 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2105 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2106 FIELD(ID_AA64ISAR1, SB, 36, 4) 2107 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2108 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2109 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2110 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2111 FIELD(ID_AA64ISAR1, XS, 56, 4) 2112 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2113 2114 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2115 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2116 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2117 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2118 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2119 FIELD(ID_AA64ISAR2, BC, 20, 4) 2120 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2121 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2122 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2123 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2124 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2125 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2126 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2127 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2128 2129 FIELD(ID_AA64PFR0, EL0, 0, 4) 2130 FIELD(ID_AA64PFR0, EL1, 4, 4) 2131 FIELD(ID_AA64PFR0, EL2, 8, 4) 2132 FIELD(ID_AA64PFR0, EL3, 12, 4) 2133 FIELD(ID_AA64PFR0, FP, 16, 4) 2134 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2135 FIELD(ID_AA64PFR0, GIC, 24, 4) 2136 FIELD(ID_AA64PFR0, RAS, 28, 4) 2137 FIELD(ID_AA64PFR0, SVE, 32, 4) 2138 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2139 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2140 FIELD(ID_AA64PFR0, AMU, 44, 4) 2141 FIELD(ID_AA64PFR0, DIT, 48, 4) 2142 FIELD(ID_AA64PFR0, RME, 52, 4) 2143 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2144 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2145 2146 FIELD(ID_AA64PFR1, BT, 0, 4) 2147 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2148 FIELD(ID_AA64PFR1, MTE, 8, 4) 2149 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2150 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2151 FIELD(ID_AA64PFR1, SME, 24, 4) 2152 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2153 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2154 FIELD(ID_AA64PFR1, NMI, 36, 4) 2155 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2156 FIELD(ID_AA64PFR1, GCS, 44, 4) 2157 FIELD(ID_AA64PFR1, THE, 48, 4) 2158 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2159 FIELD(ID_AA64PFR1, DF2, 56, 4) 2160 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2161 2162 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2163 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2164 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2165 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2166 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2167 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2168 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2169 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2170 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2171 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2172 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2173 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2174 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2175 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2176 2177 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2178 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2179 FIELD(ID_AA64MMFR1, VH, 8, 4) 2180 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2181 FIELD(ID_AA64MMFR1, LO, 16, 4) 2182 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2183 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2184 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2185 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2186 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2187 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2188 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2189 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2190 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2191 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2192 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2193 2194 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2195 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2196 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2197 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2198 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2199 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2200 FIELD(ID_AA64MMFR2, NV, 24, 4) 2201 FIELD(ID_AA64MMFR2, ST, 28, 4) 2202 FIELD(ID_AA64MMFR2, AT, 32, 4) 2203 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2204 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2205 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2206 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2207 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2208 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2209 2210 FIELD(ID_AA64MMFR3, TCRX, 0, 4) 2211 FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) 2212 FIELD(ID_AA64MMFR3, S1PIE, 8, 4) 2213 FIELD(ID_AA64MMFR3, S2PIE, 12, 4) 2214 FIELD(ID_AA64MMFR3, S1POE, 16, 4) 2215 FIELD(ID_AA64MMFR3, S2POE, 20, 4) 2216 FIELD(ID_AA64MMFR3, AIE, 24, 4) 2217 FIELD(ID_AA64MMFR3, MEC, 28, 4) 2218 FIELD(ID_AA64MMFR3, D128, 32, 4) 2219 FIELD(ID_AA64MMFR3, D128_2, 36, 4) 2220 FIELD(ID_AA64MMFR3, SNERR, 40, 4) 2221 FIELD(ID_AA64MMFR3, ANERR, 44, 4) 2222 FIELD(ID_AA64MMFR3, SDERR, 52, 4) 2223 FIELD(ID_AA64MMFR3, ADERR, 56, 4) 2224 FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) 2225 2226 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2227 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2228 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2229 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2230 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2231 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2232 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2233 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2234 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2235 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2236 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2237 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2238 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2239 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2240 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2241 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2242 2243 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2244 FIELD(ID_AA64ZFR0, AES, 4, 4) 2245 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2246 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2247 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2248 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2249 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2250 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2251 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2252 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2253 2254 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2255 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2256 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2257 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2258 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2259 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2260 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2261 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2262 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2263 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2264 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2265 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2266 2267 FIELD(ID_DFR0, COPDBG, 0, 4) 2268 FIELD(ID_DFR0, COPSDBG, 4, 4) 2269 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2270 FIELD(ID_DFR0, COPTRC, 12, 4) 2271 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2272 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2273 FIELD(ID_DFR0, PERFMON, 24, 4) 2274 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2275 2276 FIELD(ID_DFR1, MTPMU, 0, 4) 2277 FIELD(ID_DFR1, HPMN0, 4, 4) 2278 2279 FIELD(DBGDIDR, SE_IMP, 12, 1) 2280 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2281 FIELD(DBGDIDR, VERSION, 16, 4) 2282 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2283 FIELD(DBGDIDR, BRPS, 24, 4) 2284 FIELD(DBGDIDR, WRPS, 28, 4) 2285 2286 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2287 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2288 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2289 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2290 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2291 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2292 FIELD(DBGDEVID, AUXREGS, 24, 4) 2293 FIELD(DBGDEVID, CIDMASK, 28, 4) 2294 2295 FIELD(MVFR0, SIMDREG, 0, 4) 2296 FIELD(MVFR0, FPSP, 4, 4) 2297 FIELD(MVFR0, FPDP, 8, 4) 2298 FIELD(MVFR0, FPTRAP, 12, 4) 2299 FIELD(MVFR0, FPDIVIDE, 16, 4) 2300 FIELD(MVFR0, FPSQRT, 20, 4) 2301 FIELD(MVFR0, FPSHVEC, 24, 4) 2302 FIELD(MVFR0, FPROUND, 28, 4) 2303 2304 FIELD(MVFR1, FPFTZ, 0, 4) 2305 FIELD(MVFR1, FPDNAN, 4, 4) 2306 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2307 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2308 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2309 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2310 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2311 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2312 FIELD(MVFR1, FPHP, 24, 4) 2313 FIELD(MVFR1, SIMDFMAC, 28, 4) 2314 2315 FIELD(MVFR2, SIMDMISC, 0, 4) 2316 FIELD(MVFR2, FPMISC, 4, 4) 2317 2318 FIELD(GPCCR, PPS, 0, 3) 2319 FIELD(GPCCR, IRGN, 8, 2) 2320 FIELD(GPCCR, ORGN, 10, 2) 2321 FIELD(GPCCR, SH, 12, 2) 2322 FIELD(GPCCR, PGS, 14, 2) 2323 FIELD(GPCCR, GPC, 16, 1) 2324 FIELD(GPCCR, GPCP, 17, 1) 2325 FIELD(GPCCR, L0GPTSZ, 20, 4) 2326 2327 FIELD(MFAR, FPA, 12, 40) 2328 FIELD(MFAR, NSE, 62, 1) 2329 FIELD(MFAR, NS, 63, 1) 2330 2331 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2332 2333 /* If adding a feature bit which corresponds to a Linux ELF 2334 * HWCAP bit, remember to update the feature-bit-to-hwcap 2335 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2336 */ 2337 enum arm_features { 2338 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2339 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2340 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2341 ARM_FEATURE_V6, 2342 ARM_FEATURE_V6K, 2343 ARM_FEATURE_V7, 2344 ARM_FEATURE_THUMB2, 2345 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2346 ARM_FEATURE_NEON, 2347 ARM_FEATURE_M, /* Microcontroller profile. */ 2348 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2349 ARM_FEATURE_THUMB2EE, 2350 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2351 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2352 ARM_FEATURE_V4T, 2353 ARM_FEATURE_V5, 2354 ARM_FEATURE_STRONGARM, 2355 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2356 ARM_FEATURE_GENERIC_TIMER, 2357 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2358 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2359 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2360 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2361 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2362 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2363 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2364 ARM_FEATURE_V8, 2365 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2366 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2367 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2368 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2369 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2370 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2371 ARM_FEATURE_PMU, /* has PMU support */ 2372 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2373 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2374 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2375 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2376 }; 2377 2378 static inline int arm_feature(CPUARMState *env, int feature) 2379 { 2380 return (env->features & (1ULL << feature)) != 0; 2381 } 2382 2383 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2384 2385 /* 2386 * ARM v9 security states. 2387 * The ordering of the enumeration corresponds to the low 2 bits 2388 * of the GPI value, and (except for Root) the concat of NSE:NS. 2389 */ 2390 2391 typedef enum ARMSecuritySpace { 2392 ARMSS_Secure = 0, 2393 ARMSS_NonSecure = 1, 2394 ARMSS_Root = 2, 2395 ARMSS_Realm = 3, 2396 } ARMSecuritySpace; 2397 2398 /* Return true if @space is secure, in the pre-v9 sense. */ 2399 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2400 { 2401 return space == ARMSS_Secure || space == ARMSS_Root; 2402 } 2403 2404 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2405 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2406 { 2407 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2408 } 2409 2410 #if !defined(CONFIG_USER_ONLY) 2411 /** 2412 * arm_security_space_below_el3: 2413 * @env: cpu context 2414 * 2415 * Return the security space of exception levels below EL3, following 2416 * an exception return to those levels. Unlike arm_security_space, 2417 * this doesn't care about the current EL. 2418 */ 2419 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2420 2421 /** 2422 * arm_is_secure_below_el3: 2423 * @env: cpu context 2424 * 2425 * Return true if exception levels below EL3 are in secure state, 2426 * or would be following an exception return to those levels. 2427 */ 2428 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2429 { 2430 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2431 return ss == ARMSS_Secure; 2432 } 2433 2434 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2435 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2436 { 2437 assert(!arm_feature(env, ARM_FEATURE_M)); 2438 if (arm_feature(env, ARM_FEATURE_EL3)) { 2439 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2440 /* CPU currently in AArch64 state and EL3 */ 2441 return true; 2442 } else if (!is_a64(env) && 2443 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2444 /* CPU currently in AArch32 state and monitor mode */ 2445 return true; 2446 } 2447 } 2448 return false; 2449 } 2450 2451 /** 2452 * arm_security_space: 2453 * @env: cpu context 2454 * 2455 * Return the current security space of the cpu. 2456 */ 2457 ARMSecuritySpace arm_security_space(CPUARMState *env); 2458 2459 /** 2460 * arm_is_secure: 2461 * @env: cpu context 2462 * 2463 * Return true if the processor is in secure state. 2464 */ 2465 static inline bool arm_is_secure(CPUARMState *env) 2466 { 2467 return arm_space_is_secure(arm_security_space(env)); 2468 } 2469 2470 /* 2471 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2472 * This corresponds to the pseudocode EL2Enabled(). 2473 */ 2474 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2475 ARMSecuritySpace space) 2476 { 2477 assert(space != ARMSS_Root); 2478 return arm_feature(env, ARM_FEATURE_EL2) 2479 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2480 } 2481 2482 static inline bool arm_is_el2_enabled(CPUARMState *env) 2483 { 2484 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2485 } 2486 2487 #else 2488 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2489 { 2490 return ARMSS_NonSecure; 2491 } 2492 2493 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2494 { 2495 return false; 2496 } 2497 2498 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2499 { 2500 return ARMSS_NonSecure; 2501 } 2502 2503 static inline bool arm_is_secure(CPUARMState *env) 2504 { 2505 return false; 2506 } 2507 2508 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2509 ARMSecuritySpace space) 2510 { 2511 return false; 2512 } 2513 2514 static inline bool arm_is_el2_enabled(CPUARMState *env) 2515 { 2516 return false; 2517 } 2518 #endif 2519 2520 /** 2521 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2522 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2523 * "for all purposes other than a direct read or write access of HCR_EL2." 2524 * Not included here is HCR_RW. 2525 */ 2526 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2527 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2528 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2529 2530 /* Return true if the specified exception level is running in AArch64 state. */ 2531 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2532 { 2533 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2534 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2535 */ 2536 assert(el >= 1 && el <= 3); 2537 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2538 2539 /* The highest exception level is always at the maximum supported 2540 * register width, and then lower levels have a register width controlled 2541 * by bits in the SCR or HCR registers. 2542 */ 2543 if (el == 3) { 2544 return aa64; 2545 } 2546 2547 if (arm_feature(env, ARM_FEATURE_EL3) && 2548 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2549 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2550 } 2551 2552 if (el == 2) { 2553 return aa64; 2554 } 2555 2556 if (arm_is_el2_enabled(env)) { 2557 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2558 } 2559 2560 return aa64; 2561 } 2562 2563 /* Function for determining whether guest cp register reads and writes should 2564 * access the secure or non-secure bank of a cp register. When EL3 is 2565 * operating in AArch32 state, the NS-bit determines whether the secure 2566 * instance of a cp register should be used. When EL3 is AArch64 (or if 2567 * it doesn't exist at all) then there is no register banking, and all 2568 * accesses are to the non-secure version. 2569 */ 2570 static inline bool access_secure_reg(CPUARMState *env) 2571 { 2572 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2573 !arm_el_is_aa64(env, 3) && 2574 !(env->cp15.scr_el3 & SCR_NS)); 2575 2576 return ret; 2577 } 2578 2579 /* Macros for accessing a specified CP register bank */ 2580 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2581 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2582 2583 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2584 do { \ 2585 if (_secure) { \ 2586 (_env)->cp15._regname##_s = (_val); \ 2587 } else { \ 2588 (_env)->cp15._regname##_ns = (_val); \ 2589 } \ 2590 } while (0) 2591 2592 /* Macros for automatically accessing a specific CP register bank depending on 2593 * the current secure state of the system. These macros are not intended for 2594 * supporting instruction translation reads/writes as these are dependent 2595 * solely on the SCR.NS bit and not the mode. 2596 */ 2597 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2598 A32_BANKED_REG_GET((_env), _regname, \ 2599 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2600 2601 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2602 A32_BANKED_REG_SET((_env), _regname, \ 2603 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2604 (_val)) 2605 2606 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2607 uint32_t cur_el, bool secure); 2608 2609 /* Return the highest implemented Exception Level */ 2610 static inline int arm_highest_el(CPUARMState *env) 2611 { 2612 if (arm_feature(env, ARM_FEATURE_EL3)) { 2613 return 3; 2614 } 2615 if (arm_feature(env, ARM_FEATURE_EL2)) { 2616 return 2; 2617 } 2618 return 1; 2619 } 2620 2621 /* Return true if a v7M CPU is in Handler mode */ 2622 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2623 { 2624 return env->v7m.exception != 0; 2625 } 2626 2627 /* Return the current Exception Level (as per ARMv8; note that this differs 2628 * from the ARMv7 Privilege Level). 2629 */ 2630 static inline int arm_current_el(CPUARMState *env) 2631 { 2632 if (arm_feature(env, ARM_FEATURE_M)) { 2633 return arm_v7m_is_handler_mode(env) || 2634 !(env->v7m.control[env->v7m.secure] & 1); 2635 } 2636 2637 if (is_a64(env)) { 2638 return extract32(env->pstate, 2, 2); 2639 } 2640 2641 switch (env->uncached_cpsr & 0x1f) { 2642 case ARM_CPU_MODE_USR: 2643 return 0; 2644 case ARM_CPU_MODE_HYP: 2645 return 2; 2646 case ARM_CPU_MODE_MON: 2647 return 3; 2648 default: 2649 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2650 /* If EL3 is 32-bit then all secure privileged modes run in 2651 * EL3 2652 */ 2653 return 3; 2654 } 2655 2656 return 1; 2657 } 2658 } 2659 2660 /** 2661 * write_list_to_cpustate 2662 * @cpu: ARMCPU 2663 * 2664 * For each register listed in the ARMCPU cpreg_indexes list, write 2665 * its value from the cpreg_values list into the ARMCPUState structure. 2666 * This updates TCG's working data structures from KVM data or 2667 * from incoming migration state. 2668 * 2669 * Returns: true if all register values were updated correctly, 2670 * false if some register was unknown or could not be written. 2671 * Note that we do not stop early on failure -- we will attempt 2672 * writing all registers in the list. 2673 */ 2674 bool write_list_to_cpustate(ARMCPU *cpu); 2675 2676 /** 2677 * write_cpustate_to_list: 2678 * @cpu: ARMCPU 2679 * @kvm_sync: true if this is for syncing back to KVM 2680 * 2681 * For each register listed in the ARMCPU cpreg_indexes list, write 2682 * its value from the ARMCPUState structure into the cpreg_values list. 2683 * This is used to copy info from TCG's working data structures into 2684 * KVM or for outbound migration. 2685 * 2686 * @kvm_sync is true if we are doing this in order to sync the 2687 * register state back to KVM. In this case we will only update 2688 * values in the list if the previous list->cpustate sync actually 2689 * successfully wrote the CPU state. Otherwise we will keep the value 2690 * that is in the list. 2691 * 2692 * Returns: true if all register values were read correctly, 2693 * false if some register was unknown or could not be read. 2694 * Note that we do not stop early on failure -- we will attempt 2695 * reading all registers in the list. 2696 */ 2697 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2698 2699 #define ARM_CPUID_TI915T 0x54029152 2700 #define ARM_CPUID_TI925T 0x54029252 2701 2702 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2703 2704 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2705 2706 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2707 * 2708 * If EL3 is 64-bit: 2709 * + NonSecure EL1 & 0 stage 1 2710 * + NonSecure EL1 & 0 stage 2 2711 * + NonSecure EL2 2712 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2713 * + Secure EL1 & 0 2714 * + Secure EL3 2715 * If EL3 is 32-bit: 2716 * + NonSecure PL1 & 0 stage 1 2717 * + NonSecure PL1 & 0 stage 2 2718 * + NonSecure PL2 2719 * + Secure PL0 2720 * + Secure PL1 2721 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2722 * 2723 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2724 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2725 * because they may differ in access permissions even if the VA->PA map is 2726 * the same 2727 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2728 * translation, which means that we have one mmu_idx that deals with two 2729 * concatenated translation regimes [this sort of combined s1+2 TLB is 2730 * architecturally permitted] 2731 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2732 * handling via the TLB. The only way to do a stage 1 translation without 2733 * the immediate stage 2 translation is via the ATS or AT system insns, 2734 * which can be slow-pathed and always do a page table walk. 2735 * The only use of stage 2 translations is either as part of an s1+2 2736 * lookup or when loading the descriptors during a stage 1 page table walk, 2737 * and in both those cases we don't use the TLB. 2738 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2739 * translation regimes, because they map reasonably well to each other 2740 * and they can't both be active at the same time. 2741 * 5. we want to be able to use the TLB for accesses done as part of a 2742 * stage1 page table walk, rather than having to walk the stage2 page 2743 * table over and over. 2744 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2745 * Never (PAN) bit within PSTATE. 2746 * 7. we fold together the secure and non-secure regimes for A-profile, 2747 * because there are no banked system registers for aarch64, so the 2748 * process of switching between secure and non-secure is 2749 * already heavyweight. 2750 * 2751 * This gives us the following list of cases: 2752 * 2753 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2754 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2755 * EL1 EL1&0 stage 1+2 +PAN 2756 * EL0 EL2&0 2757 * EL2 EL2&0 2758 * EL2 EL2&0 +PAN 2759 * EL2 (aka NS PL2) 2760 * EL3 (aka S PL1) 2761 * Physical (NS & S) 2762 * Stage2 (NS & S) 2763 * 2764 * for a total of 12 different mmu_idx. 2765 * 2766 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2767 * as A profile. They only need to distinguish EL0 and EL1 (and 2768 * EL2 if we ever model a Cortex-R52). 2769 * 2770 * M profile CPUs are rather different as they do not have a true MMU. 2771 * They have the following different MMU indexes: 2772 * User 2773 * Privileged 2774 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2775 * Privileged, execution priority negative (ditto) 2776 * If the CPU supports the v8M Security Extension then there are also: 2777 * Secure User 2778 * Secure Privileged 2779 * Secure User, execution priority negative 2780 * Secure Privileged, execution priority negative 2781 * 2782 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2783 * are not quite the same -- different CPU types (most notably M profile 2784 * vs A/R profile) would like to use MMU indexes with different semantics, 2785 * but since we don't ever need to use all of those in a single CPU we 2786 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2787 * modes + total number of M profile MMU modes". The lower bits of 2788 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2789 * the same for any particular CPU. 2790 * Variables of type ARMMUIdx are always full values, and the core 2791 * index values are in variables of type 'int'. 2792 * 2793 * Our enumeration includes at the end some entries which are not "true" 2794 * mmu_idx values in that they don't have corresponding TLBs and are only 2795 * valid for doing slow path page table walks. 2796 * 2797 * The constant names here are patterned after the general style of the names 2798 * of the AT/ATS operations. 2799 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2800 * For M profile we arrange them to have a bit for priv, a bit for negpri 2801 * and a bit for secure. 2802 */ 2803 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2804 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2805 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2806 2807 /* Meanings of the bits for M profile mmu idx values */ 2808 #define ARM_MMU_IDX_M_PRIV 0x1 2809 #define ARM_MMU_IDX_M_NEGPRI 0x2 2810 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2811 2812 #define ARM_MMU_IDX_TYPE_MASK \ 2813 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2814 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2815 2816 typedef enum ARMMMUIdx { 2817 /* 2818 * A-profile. 2819 */ 2820 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2821 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2822 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2823 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2824 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2825 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2826 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2827 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2828 2829 /* 2830 * Used for second stage of an S12 page table walk, or for descriptor 2831 * loads during first stage of an S1 page table walk. Note that both 2832 * are in use simultaneously for SecureEL2: the security state for 2833 * the S2 ptw is selected by the NS bit from the S1 ptw. 2834 */ 2835 ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A, 2836 ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, 2837 2838 /* TLBs with 1-1 mapping to the physical address spaces. */ 2839 ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, 2840 ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, 2841 ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, 2842 ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, 2843 2844 /* 2845 * These are not allocated TLBs and are used only for AT system 2846 * instructions or for the first stage of an S12 page table walk. 2847 */ 2848 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2849 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2850 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2851 2852 /* 2853 * M-profile. 2854 */ 2855 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2856 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2857 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2858 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2859 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2860 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2861 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2862 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2863 } ARMMMUIdx; 2864 2865 /* 2866 * Bit macros for the core-mmu-index values for each index, 2867 * for use when calling tlb_flush_by_mmuidx() and friends. 2868 */ 2869 #define TO_CORE_BIT(NAME) \ 2870 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2871 2872 typedef enum ARMMMUIdxBit { 2873 TO_CORE_BIT(E10_0), 2874 TO_CORE_BIT(E20_0), 2875 TO_CORE_BIT(E10_1), 2876 TO_CORE_BIT(E10_1_PAN), 2877 TO_CORE_BIT(E2), 2878 TO_CORE_BIT(E20_2), 2879 TO_CORE_BIT(E20_2_PAN), 2880 TO_CORE_BIT(E3), 2881 TO_CORE_BIT(Stage2), 2882 TO_CORE_BIT(Stage2_S), 2883 2884 TO_CORE_BIT(MUser), 2885 TO_CORE_BIT(MPriv), 2886 TO_CORE_BIT(MUserNegPri), 2887 TO_CORE_BIT(MPrivNegPri), 2888 TO_CORE_BIT(MSUser), 2889 TO_CORE_BIT(MSPriv), 2890 TO_CORE_BIT(MSUserNegPri), 2891 TO_CORE_BIT(MSPrivNegPri), 2892 } ARMMMUIdxBit; 2893 2894 #undef TO_CORE_BIT 2895 2896 #define MMU_USER_IDX 0 2897 2898 /* Indexes used when registering address spaces with cpu_address_space_init */ 2899 typedef enum ARMASIdx { 2900 ARMASIdx_NS = 0, 2901 ARMASIdx_S = 1, 2902 ARMASIdx_TagNS = 2, 2903 ARMASIdx_TagS = 3, 2904 } ARMASIdx; 2905 2906 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 2907 { 2908 /* Assert the relative order of the physical mmu indexes. */ 2909 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 2910 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 2911 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 2912 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 2913 2914 return ARMMMUIdx_Phys_S + space; 2915 } 2916 2917 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 2918 { 2919 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 2920 return idx - ARMMMUIdx_Phys_S; 2921 } 2922 2923 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2924 { 2925 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2926 * CSSELR is RAZ/WI. 2927 */ 2928 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2929 } 2930 2931 static inline bool arm_sctlr_b(CPUARMState *env) 2932 { 2933 return 2934 /* We need not implement SCTLR.ITD in user-mode emulation, so 2935 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2936 * This lets people run BE32 binaries with "-cpu any". 2937 */ 2938 #ifndef CONFIG_USER_ONLY 2939 !arm_feature(env, ARM_FEATURE_V7) && 2940 #endif 2941 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2942 } 2943 2944 uint64_t arm_sctlr(CPUARMState *env, int el); 2945 2946 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 2947 bool sctlr_b) 2948 { 2949 #ifdef CONFIG_USER_ONLY 2950 /* 2951 * In system mode, BE32 is modelled in line with the 2952 * architecture (as word-invariant big-endianness), where loads 2953 * and stores are done little endian but from addresses which 2954 * are adjusted by XORing with the appropriate constant. So the 2955 * endianness to use for the raw data access is not affected by 2956 * SCTLR.B. 2957 * In user mode, however, we model BE32 as byte-invariant 2958 * big-endianness (because user-only code cannot tell the 2959 * difference), and so we need to use a data access endianness 2960 * that depends on SCTLR.B. 2961 */ 2962 if (sctlr_b) { 2963 return true; 2964 } 2965 #endif 2966 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2967 return env->uncached_cpsr & CPSR_E; 2968 } 2969 2970 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 2971 { 2972 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 2973 } 2974 2975 /* Return true if the processor is in big-endian mode. */ 2976 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2977 { 2978 if (!is_a64(env)) { 2979 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 2980 } else { 2981 int cur_el = arm_current_el(env); 2982 uint64_t sctlr = arm_sctlr(env, cur_el); 2983 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 2984 } 2985 } 2986 2987 #include "exec/cpu-all.h" 2988 2989 /* 2990 * We have more than 32-bits worth of state per TB, so we split the data 2991 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 2992 * We collect these two parts in CPUARMTBFlags where they are named 2993 * flags and flags2 respectively. 2994 * 2995 * The flags that are shared between all execution modes, TBFLAG_ANY, 2996 * are stored in flags. The flags that are specific to a given mode 2997 * are stores in flags2. Since cs_base is sized on the configured 2998 * address size, flags2 always has 64-bits for A64, and a minimum of 2999 * 32-bits for A32 and M32. 3000 * 3001 * The bits for 32-bit A-profile and M-profile partially overlap: 3002 * 3003 * 31 23 11 10 0 3004 * +-------------+----------+----------------+ 3005 * | | | TBFLAG_A32 | 3006 * | TBFLAG_AM32 | +-----+----------+ 3007 * | | |TBFLAG_M32| 3008 * +-------------+----------------+----------+ 3009 * 31 23 6 5 0 3010 * 3011 * Unless otherwise noted, these bits are cached in env->hflags. 3012 */ 3013 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3014 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3015 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3016 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3017 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3018 /* Target EL if we take a floating-point-disabled exception */ 3019 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3020 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3021 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3022 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3023 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3024 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3025 3026 /* 3027 * Bit usage when in AArch32 state, both A- and M-profile. 3028 */ 3029 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3030 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3031 3032 /* 3033 * Bit usage when in AArch32 state, for A-profile only. 3034 */ 3035 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3036 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3037 /* 3038 * We store the bottom two bits of the CPAR as TB flags and handle 3039 * checks on the other bits at runtime. This shares the same bits as 3040 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3041 * Not cached, because VECLEN+VECSTRIDE are not cached. 3042 */ 3043 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3044 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3045 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3046 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3047 /* 3048 * Indicates whether cp register reads and writes by guest code should access 3049 * the secure or nonsecure bank of banked registers; note that this is not 3050 * the same thing as the current security state of the processor! 3051 */ 3052 FIELD(TBFLAG_A32, NS, 10, 1) 3053 /* 3054 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3055 * This requires an SME trap from AArch32 mode when using NEON. 3056 */ 3057 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3058 3059 /* 3060 * Bit usage when in AArch32 state, for M-profile only. 3061 */ 3062 /* Handler (ie not Thread) mode */ 3063 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3064 /* Whether we should generate stack-limit checks */ 3065 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3066 /* Set if FPCCR.LSPACT is set */ 3067 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3068 /* Set if we must create a new FP context */ 3069 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3070 /* Set if FPCCR.S does not match current security state */ 3071 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3072 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3073 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3074 /* Set if in secure mode */ 3075 FIELD(TBFLAG_M32, SECURE, 6, 1) 3076 3077 /* 3078 * Bit usage when in AArch64 state 3079 */ 3080 FIELD(TBFLAG_A64, TBII, 0, 2) 3081 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3082 /* The current vector length, either NVL or SVL. */ 3083 FIELD(TBFLAG_A64, VL, 4, 4) 3084 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3085 FIELD(TBFLAG_A64, BT, 9, 1) 3086 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3087 FIELD(TBFLAG_A64, TBID, 12, 2) 3088 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3089 FIELD(TBFLAG_A64, ATA, 15, 1) 3090 FIELD(TBFLAG_A64, TCMA, 16, 2) 3091 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3092 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3093 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3094 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3095 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3096 FIELD(TBFLAG_A64, SVL, 24, 4) 3097 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3098 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3099 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 3100 FIELD(TBFLAG_A64, NAA, 30, 1) 3101 FIELD(TBFLAG_A64, ATA0, 31, 1) 3102 FIELD(TBFLAG_A64, NV, 32, 1) 3103 FIELD(TBFLAG_A64, NV1, 33, 1) 3104 FIELD(TBFLAG_A64, NV2, 34, 1) 3105 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ 3106 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) 3107 /* Set if FEAT_NV2 RAM accesses are big-endian */ 3108 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 3109 3110 /* 3111 * Helpers for using the above. Note that only the A64 accessors use 3112 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 3113 * word either is or might be 32 bits only. 3114 */ 3115 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3116 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3117 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3118 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3119 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3120 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3121 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3122 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3123 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3124 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3125 3126 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3127 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 3128 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3129 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3130 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3131 3132 /** 3133 * sve_vq 3134 * @env: the cpu context 3135 * 3136 * Return the VL cached within env->hflags, in units of quadwords. 3137 */ 3138 static inline int sve_vq(CPUARMState *env) 3139 { 3140 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3141 } 3142 3143 /** 3144 * sme_vq 3145 * @env: the cpu context 3146 * 3147 * Return the SVL cached within env->hflags, in units of quadwords. 3148 */ 3149 static inline int sme_vq(CPUARMState *env) 3150 { 3151 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3152 } 3153 3154 static inline bool bswap_code(bool sctlr_b) 3155 { 3156 #ifdef CONFIG_USER_ONLY 3157 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3158 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3159 * would also end up as a mixed-endian mode with BE code, LE data. 3160 */ 3161 return TARGET_BIG_ENDIAN ^ sctlr_b; 3162 #else 3163 /* All code access in ARM is little endian, and there are no loaders 3164 * doing swaps that need to be reversed 3165 */ 3166 return 0; 3167 #endif 3168 } 3169 3170 #ifdef CONFIG_USER_ONLY 3171 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3172 { 3173 return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); 3174 } 3175 #endif 3176 3177 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, 3178 uint64_t *cs_base, uint32_t *flags); 3179 3180 enum { 3181 QEMU_PSCI_CONDUIT_DISABLED = 0, 3182 QEMU_PSCI_CONDUIT_SMC = 1, 3183 QEMU_PSCI_CONDUIT_HVC = 2, 3184 }; 3185 3186 #ifndef CONFIG_USER_ONLY 3187 /* Return the address space index to use for a memory access */ 3188 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3189 { 3190 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3191 } 3192 3193 /* Return the AddressSpace to use for a memory access 3194 * (which depends on whether the access is S or NS, and whether 3195 * the board gave us a separate AddressSpace for S accesses). 3196 */ 3197 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3198 { 3199 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3200 } 3201 #endif 3202 3203 /** 3204 * arm_register_pre_el_change_hook: 3205 * Register a hook function which will be called immediately before this 3206 * CPU changes exception level or mode. The hook function will be 3207 * passed a pointer to the ARMCPU and the opaque data pointer passed 3208 * to this function when the hook was registered. 3209 * 3210 * Note that if a pre-change hook is called, any registered post-change hooks 3211 * are guaranteed to subsequently be called. 3212 */ 3213 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3214 void *opaque); 3215 /** 3216 * arm_register_el_change_hook: 3217 * Register a hook function which will be called immediately after this 3218 * CPU changes exception level or mode. The hook function will be 3219 * passed a pointer to the ARMCPU and the opaque data pointer passed 3220 * to this function when the hook was registered. 3221 * 3222 * Note that any registered hooks registered here are guaranteed to be called 3223 * if pre-change hooks have been. 3224 */ 3225 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3226 *opaque); 3227 3228 /** 3229 * arm_rebuild_hflags: 3230 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3231 */ 3232 void arm_rebuild_hflags(CPUARMState *env); 3233 3234 /** 3235 * aa32_vfp_dreg: 3236 * Return a pointer to the Dn register within env in 32-bit mode. 3237 */ 3238 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3239 { 3240 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3241 } 3242 3243 /** 3244 * aa32_vfp_qreg: 3245 * Return a pointer to the Qn register within env in 32-bit mode. 3246 */ 3247 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3248 { 3249 return &env->vfp.zregs[regno].d[0]; 3250 } 3251 3252 /** 3253 * aa64_vfp_qreg: 3254 * Return a pointer to the Qn register within env in 64-bit mode. 3255 */ 3256 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3257 { 3258 return &env->vfp.zregs[regno].d[0]; 3259 } 3260 3261 /* Shared between translate-sve.c and sve_helper.c. */ 3262 extern const uint64_t pred_esz_masks[5]; 3263 3264 /* 3265 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3266 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3267 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3268 */ 3269 #define PAGE_BTI PAGE_TARGET_1 3270 #define PAGE_MTE PAGE_TARGET_2 3271 #define PAGE_TARGET_STICKY PAGE_MTE 3272 3273 /* We associate one allocation tag per 16 bytes, the minimum. */ 3274 #define LOG2_TAG_GRANULE 4 3275 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3276 3277 #ifdef CONFIG_USER_ONLY 3278 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3279 #endif 3280 3281 #ifdef TARGET_TAGGED_ADDRESSES 3282 /** 3283 * cpu_untagged_addr: 3284 * @cs: CPU context 3285 * @x: tagged address 3286 * 3287 * Remove any address tag from @x. This is explicitly related to the 3288 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3289 * 3290 * There should be a better place to put this, but we need this in 3291 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3292 */ 3293 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3294 { 3295 ARMCPU *cpu = ARM_CPU(cs); 3296 if (cpu->env.tagged_addr_enable) { 3297 /* 3298 * TBI is enabled for userspace but not kernelspace addresses. 3299 * Only clear the tag if bit 55 is clear. 3300 */ 3301 x &= sextract64(x, 0, 56); 3302 } 3303 return x; 3304 } 3305 #endif 3306 3307 #endif 3308