1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #include "fpu/softfloat.h" 43 44 #define EXCP_UDEF 1 /* undefined instruction */ 45 #define EXCP_SWI 2 /* software interrupt */ 46 #define EXCP_PREFETCH_ABORT 3 47 #define EXCP_DATA_ABORT 4 48 #define EXCP_IRQ 5 49 #define EXCP_FIQ 6 50 #define EXCP_BKPT 7 51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 53 #define EXCP_HVC 11 /* HyperVisor Call */ 54 #define EXCP_HYP_TRAP 12 55 #define EXCP_SMC 13 /* Secure Monitor Call */ 56 #define EXCP_VIRQ 14 57 #define EXCP_VFIQ 15 58 #define EXCP_SEMIHOST 16 /* semihosting call */ 59 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 60 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SVC 11 69 #define ARMV7M_EXCP_DEBUG 12 70 #define ARMV7M_EXCP_PENDSV 14 71 #define ARMV7M_EXCP_SYSTICK 15 72 73 /* ARM-specific interrupt pending bits. */ 74 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 75 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 76 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 77 78 /* The usual mapping for an AArch64 system register to its AArch32 79 * counterpart is for the 32 bit world to have access to the lower 80 * half only (with writes leaving the upper half untouched). It's 81 * therefore useful to be able to pass TCG the offset of the least 82 * significant half of a uint64_t struct member. 83 */ 84 #ifdef HOST_WORDS_BIGENDIAN 85 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 86 #define offsetofhigh32(S, M) offsetof(S, M) 87 #else 88 #define offsetoflow32(S, M) offsetof(S, M) 89 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 90 #endif 91 92 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 93 #define ARM_CPU_IRQ 0 94 #define ARM_CPU_FIQ 1 95 #define ARM_CPU_VIRQ 2 96 #define ARM_CPU_VFIQ 3 97 98 #define NB_MMU_MODES 7 99 /* ARM-specific extra insn start words: 100 * 1: Conditional execution bits 101 * 2: Partial exception syndrome for data aborts 102 */ 103 #define TARGET_INSN_START_EXTRA_WORDS 2 104 105 /* The 2nd extra word holding syndrome info for data aborts does not use 106 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 107 * help the sleb128 encoder do a better job. 108 * When restoring the CPU state, we shift it back up. 109 */ 110 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 111 #define ARM_INSN_START_WORD2_SHIFT 14 112 113 /* We currently assume float and double are IEEE single and double 114 precision respectively. 115 Doing runtime conversions is tricky because VFP registers may contain 116 integer values (eg. as the result of a FTOSI instruction). 117 s<2n> maps to the least significant half of d<n> 118 s<2n+1> maps to the most significant half of d<n> 119 */ 120 121 /* CPU state for each instance of a generic timer (in cp15 c14) */ 122 typedef struct ARMGenericTimer { 123 uint64_t cval; /* Timer CompareValue register */ 124 uint64_t ctl; /* Timer Control register */ 125 } ARMGenericTimer; 126 127 #define GTIMER_PHYS 0 128 #define GTIMER_VIRT 1 129 #define GTIMER_HYP 2 130 #define GTIMER_SEC 3 131 #define NUM_GTIMERS 4 132 133 typedef struct { 134 uint64_t raw_tcr; 135 uint32_t mask; 136 uint32_t base_mask; 137 } TCR; 138 139 typedef struct CPUARMState { 140 /* Regs for current mode. */ 141 uint32_t regs[16]; 142 143 /* 32/64 switch only happens when taking and returning from 144 * exceptions so the overlap semantics are taken care of then 145 * instead of having a complicated union. 146 */ 147 /* Regs for A64 mode. */ 148 uint64_t xregs[32]; 149 uint64_t pc; 150 /* PSTATE isn't an architectural register for ARMv8. However, it is 151 * convenient for us to assemble the underlying state into a 32 bit format 152 * identical to the architectural format used for the SPSR. (This is also 153 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 154 * 'pstate' register are.) Of the PSTATE bits: 155 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 156 * semantics as for AArch32, as described in the comments on each field) 157 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 158 * DAIF (exception masks) are kept in env->daif 159 * all other bits are stored in their correct places in env->pstate 160 */ 161 uint32_t pstate; 162 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 163 164 /* Frequently accessed CPSR bits are stored separately for efficiency. 165 This contains all the other bits. Use cpsr_{read,write} to access 166 the whole CPSR. */ 167 uint32_t uncached_cpsr; 168 uint32_t spsr; 169 170 /* Banked registers. */ 171 uint64_t banked_spsr[8]; 172 uint32_t banked_r13[8]; 173 uint32_t banked_r14[8]; 174 175 /* These hold r8-r12. */ 176 uint32_t usr_regs[5]; 177 uint32_t fiq_regs[5]; 178 179 /* cpsr flag cache for faster execution */ 180 uint32_t CF; /* 0 or 1 */ 181 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 182 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 183 uint32_t ZF; /* Z set if zero. */ 184 uint32_t QF; /* 0 or 1 */ 185 uint32_t GE; /* cpsr[19:16] */ 186 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 187 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 188 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 189 190 uint64_t elr_el[4]; /* AArch64 exception link regs */ 191 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 192 193 /* System control coprocessor (cp15) */ 194 struct { 195 uint32_t c0_cpuid; 196 union { /* Cache size selection */ 197 struct { 198 uint64_t _unused_csselr0; 199 uint64_t csselr_ns; 200 uint64_t _unused_csselr1; 201 uint64_t csselr_s; 202 }; 203 uint64_t csselr_el[4]; 204 }; 205 union { /* System control register. */ 206 struct { 207 uint64_t _unused_sctlr; 208 uint64_t sctlr_ns; 209 uint64_t hsctlr; 210 uint64_t sctlr_s; 211 }; 212 uint64_t sctlr_el[4]; 213 }; 214 uint64_t cpacr_el1; /* Architectural feature access control register */ 215 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 216 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 217 uint64_t sder; /* Secure debug enable register. */ 218 uint32_t nsacr; /* Non-secure access control register. */ 219 union { /* MMU translation table base 0. */ 220 struct { 221 uint64_t _unused_ttbr0_0; 222 uint64_t ttbr0_ns; 223 uint64_t _unused_ttbr0_1; 224 uint64_t ttbr0_s; 225 }; 226 uint64_t ttbr0_el[4]; 227 }; 228 union { /* MMU translation table base 1. */ 229 struct { 230 uint64_t _unused_ttbr1_0; 231 uint64_t ttbr1_ns; 232 uint64_t _unused_ttbr1_1; 233 uint64_t ttbr1_s; 234 }; 235 uint64_t ttbr1_el[4]; 236 }; 237 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 238 /* MMU translation table base control. */ 239 TCR tcr_el[4]; 240 TCR vtcr_el2; /* Virtualization Translation Control. */ 241 uint32_t c2_data; /* MPU data cacheable bits. */ 242 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 243 union { /* MMU domain access control register 244 * MPU write buffer control. 245 */ 246 struct { 247 uint64_t dacr_ns; 248 uint64_t dacr_s; 249 }; 250 struct { 251 uint64_t dacr32_el2; 252 }; 253 }; 254 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 255 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 256 uint64_t hcr_el2; /* Hypervisor configuration register */ 257 uint64_t scr_el3; /* Secure configuration register. */ 258 union { /* Fault status registers. */ 259 struct { 260 uint64_t ifsr_ns; 261 uint64_t ifsr_s; 262 }; 263 struct { 264 uint64_t ifsr32_el2; 265 }; 266 }; 267 union { 268 struct { 269 uint64_t _unused_dfsr; 270 uint64_t dfsr_ns; 271 uint64_t hsr; 272 uint64_t dfsr_s; 273 }; 274 uint64_t esr_el[4]; 275 }; 276 uint32_t c6_region[8]; /* MPU base/size registers. */ 277 union { /* Fault address registers. */ 278 struct { 279 uint64_t _unused_far0; 280 #ifdef HOST_WORDS_BIGENDIAN 281 uint32_t ifar_ns; 282 uint32_t dfar_ns; 283 uint32_t ifar_s; 284 uint32_t dfar_s; 285 #else 286 uint32_t dfar_ns; 287 uint32_t ifar_ns; 288 uint32_t dfar_s; 289 uint32_t ifar_s; 290 #endif 291 uint64_t _unused_far3; 292 }; 293 uint64_t far_el[4]; 294 }; 295 uint64_t hpfar_el2; 296 uint64_t hstr_el2; 297 union { /* Translation result. */ 298 struct { 299 uint64_t _unused_par_0; 300 uint64_t par_ns; 301 uint64_t _unused_par_1; 302 uint64_t par_s; 303 }; 304 uint64_t par_el[4]; 305 }; 306 307 uint32_t c6_rgnr; 308 309 uint32_t c9_insn; /* Cache lockdown registers. */ 310 uint32_t c9_data; 311 uint64_t c9_pmcr; /* performance monitor control register */ 312 uint64_t c9_pmcnten; /* perf monitor counter enables */ 313 uint32_t c9_pmovsr; /* perf monitor overflow status */ 314 uint32_t c9_pmuserenr; /* perf monitor user enable */ 315 uint64_t c9_pmselr; /* perf monitor counter selection register */ 316 uint64_t c9_pminten; /* perf monitor interrupt enables */ 317 union { /* Memory attribute redirection */ 318 struct { 319 #ifdef HOST_WORDS_BIGENDIAN 320 uint64_t _unused_mair_0; 321 uint32_t mair1_ns; 322 uint32_t mair0_ns; 323 uint64_t _unused_mair_1; 324 uint32_t mair1_s; 325 uint32_t mair0_s; 326 #else 327 uint64_t _unused_mair_0; 328 uint32_t mair0_ns; 329 uint32_t mair1_ns; 330 uint64_t _unused_mair_1; 331 uint32_t mair0_s; 332 uint32_t mair1_s; 333 #endif 334 }; 335 uint64_t mair_el[4]; 336 }; 337 union { /* vector base address register */ 338 struct { 339 uint64_t _unused_vbar; 340 uint64_t vbar_ns; 341 uint64_t hvbar; 342 uint64_t vbar_s; 343 }; 344 uint64_t vbar_el[4]; 345 }; 346 uint32_t mvbar; /* (monitor) vector base address register */ 347 struct { /* FCSE PID. */ 348 uint32_t fcseidr_ns; 349 uint32_t fcseidr_s; 350 }; 351 union { /* Context ID. */ 352 struct { 353 uint64_t _unused_contextidr_0; 354 uint64_t contextidr_ns; 355 uint64_t _unused_contextidr_1; 356 uint64_t contextidr_s; 357 }; 358 uint64_t contextidr_el[4]; 359 }; 360 union { /* User RW Thread register. */ 361 struct { 362 uint64_t tpidrurw_ns; 363 uint64_t tpidrprw_ns; 364 uint64_t htpidr; 365 uint64_t _tpidr_el3; 366 }; 367 uint64_t tpidr_el[4]; 368 }; 369 /* The secure banks of these registers don't map anywhere */ 370 uint64_t tpidrurw_s; 371 uint64_t tpidrprw_s; 372 uint64_t tpidruro_s; 373 374 union { /* User RO Thread register. */ 375 uint64_t tpidruro_ns; 376 uint64_t tpidrro_el[1]; 377 }; 378 uint64_t c14_cntfrq; /* Counter Frequency register */ 379 uint64_t c14_cntkctl; /* Timer Control register */ 380 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 381 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 382 ARMGenericTimer c14_timer[NUM_GTIMERS]; 383 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 384 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 385 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 386 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 387 uint32_t c15_threadid; /* TI debugger thread-ID. */ 388 uint32_t c15_config_base_address; /* SCU base address. */ 389 uint32_t c15_diagnostic; /* diagnostic register */ 390 uint32_t c15_power_diagnostic; 391 uint32_t c15_power_control; /* power control */ 392 uint64_t dbgbvr[16]; /* breakpoint value registers */ 393 uint64_t dbgbcr[16]; /* breakpoint control registers */ 394 uint64_t dbgwvr[16]; /* watchpoint value registers */ 395 uint64_t dbgwcr[16]; /* watchpoint control registers */ 396 uint64_t mdscr_el1; 397 uint64_t oslsr_el1; /* OS Lock Status */ 398 uint64_t mdcr_el2; 399 uint64_t mdcr_el3; 400 /* If the counter is enabled, this stores the last time the counter 401 * was reset. Otherwise it stores the counter value 402 */ 403 uint64_t c15_ccnt; 404 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 405 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 406 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 407 } cp15; 408 409 struct { 410 uint32_t other_sp; 411 uint32_t vecbase; 412 uint32_t basepri; 413 uint32_t control; 414 uint32_t ccr; /* Configuration and Control */ 415 uint32_t cfsr; /* Configurable Fault Status */ 416 uint32_t hfsr; /* HardFault Status */ 417 uint32_t dfsr; /* Debug Fault Status Register */ 418 uint32_t mmfar; /* MemManage Fault Address */ 419 uint32_t bfar; /* BusFault Address */ 420 int exception; 421 } v7m; 422 423 /* Information associated with an exception about to be taken: 424 * code which raises an exception must set cs->exception_index and 425 * the relevant parts of this structure; the cpu_do_interrupt function 426 * will then set the guest-visible registers as part of the exception 427 * entry process. 428 */ 429 struct { 430 uint32_t syndrome; /* AArch64 format syndrome register */ 431 uint32_t fsr; /* AArch32 format fault status register info */ 432 uint64_t vaddress; /* virtual addr associated with exception, if any */ 433 uint32_t target_el; /* EL the exception should be targeted for */ 434 /* If we implement EL2 we will also need to store information 435 * about the intermediate physical address for stage 2 faults. 436 */ 437 } exception; 438 439 /* Thumb-2 EE state. */ 440 uint32_t teecr; 441 uint32_t teehbr; 442 443 /* VFP coprocessor state. */ 444 struct { 445 /* VFP/Neon register state. Note that the mapping between S, D and Q 446 * views of the register bank differs between AArch64 and AArch32: 447 * In AArch32: 448 * Qn = regs[2n+1]:regs[2n] 449 * Dn = regs[n] 450 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n 451 * (and regs[32] to regs[63] are inaccessible) 452 * In AArch64: 453 * Qn = regs[2n+1]:regs[2n] 454 * Dn = regs[2n] 455 * Sn = regs[2n] bits 31..0 456 * This corresponds to the architecturally defined mapping between 457 * the two execution states, and means we do not need to explicitly 458 * map these registers when changing states. 459 */ 460 float64 regs[64]; 461 462 uint32_t xregs[16]; 463 /* We store these fpcsr fields separately for convenience. */ 464 int vec_len; 465 int vec_stride; 466 467 /* scratch space when Tn are not sufficient. */ 468 uint32_t scratch[8]; 469 470 /* fp_status is the "normal" fp status. standard_fp_status retains 471 * values corresponding to the ARM "Standard FPSCR Value", ie 472 * default-NaN, flush-to-zero, round-to-nearest and is used by 473 * any operations (generally Neon) which the architecture defines 474 * as controlled by the standard FPSCR value rather than the FPSCR. 475 * 476 * To avoid having to transfer exception bits around, we simply 477 * say that the FPSCR cumulative exception flags are the logical 478 * OR of the flags in the two fp statuses. This relies on the 479 * only thing which needs to read the exception flags being 480 * an explicit FPSCR read. 481 */ 482 float_status fp_status; 483 float_status standard_fp_status; 484 } vfp; 485 uint64_t exclusive_addr; 486 uint64_t exclusive_val; 487 uint64_t exclusive_high; 488 489 /* iwMMXt coprocessor state. */ 490 struct { 491 uint64_t regs[16]; 492 uint64_t val; 493 494 uint32_t cregs[16]; 495 } iwmmxt; 496 497 #if defined(CONFIG_USER_ONLY) 498 /* For usermode syscall translation. */ 499 int eabi; 500 #endif 501 502 struct CPUBreakpoint *cpu_breakpoint[16]; 503 struct CPUWatchpoint *cpu_watchpoint[16]; 504 505 /* Fields up to this point are cleared by a CPU reset */ 506 struct {} end_reset_fields; 507 508 CPU_COMMON 509 510 /* Fields after CPU_COMMON are preserved across CPU reset. */ 511 512 /* Internal CPU feature flags. */ 513 uint64_t features; 514 515 /* PMSAv7 MPU */ 516 struct { 517 uint32_t *drbar; 518 uint32_t *drsr; 519 uint32_t *dracr; 520 } pmsav7; 521 522 void *nvic; 523 const struct arm_boot_info *boot_info; 524 /* Store GICv3CPUState to access from this struct */ 525 void *gicv3state; 526 } CPUARMState; 527 528 /** 529 * ARMELChangeHook: 530 * type of a function which can be registered via arm_register_el_change_hook() 531 * to get callbacks when the CPU changes its exception level or mode. 532 */ 533 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); 534 535 536 /* These values map onto the return values for 537 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 538 typedef enum ARMPSCIState { 539 PSCI_ON = 0, 540 PSCI_OFF = 1, 541 PSCI_ON_PENDING = 2 542 } ARMPSCIState; 543 544 /** 545 * ARMCPU: 546 * @env: #CPUARMState 547 * 548 * An ARM CPU core. 549 */ 550 struct ARMCPU { 551 /*< private >*/ 552 CPUState parent_obj; 553 /*< public >*/ 554 555 CPUARMState env; 556 557 /* Coprocessor information */ 558 GHashTable *cp_regs; 559 /* For marshalling (mostly coprocessor) register state between the 560 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 561 * we use these arrays. 562 */ 563 /* List of register indexes managed via these arrays; (full KVM style 564 * 64 bit indexes, not CPRegInfo 32 bit indexes) 565 */ 566 uint64_t *cpreg_indexes; 567 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 568 uint64_t *cpreg_values; 569 /* Length of the indexes, values, reset_values arrays */ 570 int32_t cpreg_array_len; 571 /* These are used only for migration: incoming data arrives in 572 * these fields and is sanity checked in post_load before copying 573 * to the working data structures above. 574 */ 575 uint64_t *cpreg_vmstate_indexes; 576 uint64_t *cpreg_vmstate_values; 577 int32_t cpreg_vmstate_array_len; 578 579 /* Timers used by the generic (architected) timer */ 580 QEMUTimer *gt_timer[NUM_GTIMERS]; 581 /* GPIO outputs for generic timer */ 582 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 583 /* GPIO output for GICv3 maintenance interrupt signal */ 584 qemu_irq gicv3_maintenance_interrupt; 585 586 /* MemoryRegion to use for secure physical accesses */ 587 MemoryRegion *secure_memory; 588 589 /* 'compatible' string for this CPU for Linux device trees */ 590 const char *dtb_compatible; 591 592 /* PSCI version for this CPU 593 * Bits[31:16] = Major Version 594 * Bits[15:0] = Minor Version 595 */ 596 uint32_t psci_version; 597 598 /* Should CPU start in PSCI powered-off state? */ 599 bool start_powered_off; 600 601 /* Current power state, access guarded by BQL */ 602 ARMPSCIState power_state; 603 604 /* CPU has virtualization extension */ 605 bool has_el2; 606 /* CPU has security extension */ 607 bool has_el3; 608 /* CPU has PMU (Performance Monitor Unit) */ 609 bool has_pmu; 610 611 /* CPU has memory protection unit */ 612 bool has_mpu; 613 /* PMSAv7 MPU number of supported regions */ 614 uint32_t pmsav7_dregion; 615 616 /* PSCI conduit used to invoke PSCI methods 617 * 0 - disabled, 1 - smc, 2 - hvc 618 */ 619 uint32_t psci_conduit; 620 621 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 622 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 623 */ 624 uint32_t kvm_target; 625 626 /* KVM init features for this CPU */ 627 uint32_t kvm_init_features[7]; 628 629 /* Uniprocessor system with MP extensions */ 630 bool mp_is_up; 631 632 /* The instance init functions for implementation-specific subclasses 633 * set these fields to specify the implementation-dependent values of 634 * various constant registers and reset values of non-constant 635 * registers. 636 * Some of these might become QOM properties eventually. 637 * Field names match the official register names as defined in the 638 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 639 * is used for reset values of non-constant registers; no reset_ 640 * prefix means a constant register. 641 */ 642 uint32_t midr; 643 uint32_t revidr; 644 uint32_t reset_fpsid; 645 uint32_t mvfr0; 646 uint32_t mvfr1; 647 uint32_t mvfr2; 648 uint32_t ctr; 649 uint32_t reset_sctlr; 650 uint32_t id_pfr0; 651 uint32_t id_pfr1; 652 uint32_t id_dfr0; 653 uint32_t pmceid0; 654 uint32_t pmceid1; 655 uint32_t id_afr0; 656 uint32_t id_mmfr0; 657 uint32_t id_mmfr1; 658 uint32_t id_mmfr2; 659 uint32_t id_mmfr3; 660 uint32_t id_mmfr4; 661 uint32_t id_isar0; 662 uint32_t id_isar1; 663 uint32_t id_isar2; 664 uint32_t id_isar3; 665 uint32_t id_isar4; 666 uint32_t id_isar5; 667 uint64_t id_aa64pfr0; 668 uint64_t id_aa64pfr1; 669 uint64_t id_aa64dfr0; 670 uint64_t id_aa64dfr1; 671 uint64_t id_aa64afr0; 672 uint64_t id_aa64afr1; 673 uint64_t id_aa64isar0; 674 uint64_t id_aa64isar1; 675 uint64_t id_aa64mmfr0; 676 uint64_t id_aa64mmfr1; 677 uint32_t dbgdidr; 678 uint32_t clidr; 679 uint64_t mp_affinity; /* MP ID without feature bits */ 680 /* The elements of this array are the CCSIDR values for each cache, 681 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 682 */ 683 uint32_t ccsidr[16]; 684 uint64_t reset_cbar; 685 uint32_t reset_auxcr; 686 bool reset_hivecs; 687 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 688 uint32_t dcz_blocksize; 689 uint64_t rvbar; 690 691 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 692 int gic_num_lrs; /* number of list registers */ 693 int gic_vpribits; /* number of virtual priority bits */ 694 int gic_vprebits; /* number of virtual preemption bits */ 695 696 /* Whether the cfgend input is high (i.e. this CPU should reset into 697 * big-endian mode). This setting isn't used directly: instead it modifies 698 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 699 * architecture version. 700 */ 701 bool cfgend; 702 703 ARMELChangeHook *el_change_hook; 704 void *el_change_hook_opaque; 705 }; 706 707 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 708 { 709 return container_of(env, ARMCPU, env); 710 } 711 712 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 713 714 #define ENV_OFFSET offsetof(ARMCPU, env) 715 716 #ifndef CONFIG_USER_ONLY 717 extern const struct VMStateDescription vmstate_arm_cpu; 718 #endif 719 720 void arm_cpu_do_interrupt(CPUState *cpu); 721 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 722 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 723 724 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 725 int flags); 726 727 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 728 MemTxAttrs *attrs); 729 730 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 731 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 732 733 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 734 int cpuid, void *opaque); 735 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 736 int cpuid, void *opaque); 737 738 #ifdef TARGET_AARCH64 739 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 740 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 741 #endif 742 743 ARMCPU *cpu_arm_init(const char *cpu_model); 744 target_ulong do_arm_semihosting(CPUARMState *env); 745 void aarch64_sync_32_to_64(CPUARMState *env); 746 void aarch64_sync_64_to_32(CPUARMState *env); 747 748 static inline bool is_a64(CPUARMState *env) 749 { 750 return env->aarch64; 751 } 752 753 /* you can call this signal handler from your SIGBUS and SIGSEGV 754 signal handlers to inform the virtual CPU of exceptions. non zero 755 is returned if the signal was handled by the virtual CPU. */ 756 int cpu_arm_signal_handler(int host_signum, void *pinfo, 757 void *puc); 758 759 /** 760 * pmccntr_sync 761 * @env: CPUARMState 762 * 763 * Synchronises the counter in the PMCCNTR. This must always be called twice, 764 * once before any action that might affect the timer and again afterwards. 765 * The function is used to swap the state of the register if required. 766 * This only happens when not in user mode (!CONFIG_USER_ONLY) 767 */ 768 void pmccntr_sync(CPUARMState *env); 769 770 /* SCTLR bit meanings. Several bits have been reused in newer 771 * versions of the architecture; in that case we define constants 772 * for both old and new bit meanings. Code which tests against those 773 * bits should probably check or otherwise arrange that the CPU 774 * is the architectural version it expects. 775 */ 776 #define SCTLR_M (1U << 0) 777 #define SCTLR_A (1U << 1) 778 #define SCTLR_C (1U << 2) 779 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 780 #define SCTLR_SA (1U << 3) 781 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 782 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 783 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 784 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 785 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 786 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 787 #define SCTLR_ITD (1U << 7) /* v8 onward */ 788 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 789 #define SCTLR_SED (1U << 8) /* v8 onward */ 790 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 791 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 792 #define SCTLR_F (1U << 10) /* up to v6 */ 793 #define SCTLR_SW (1U << 10) /* v7 onward */ 794 #define SCTLR_Z (1U << 11) 795 #define SCTLR_I (1U << 12) 796 #define SCTLR_V (1U << 13) 797 #define SCTLR_RR (1U << 14) /* up to v7 */ 798 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 799 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 800 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 801 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 802 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 803 #define SCTLR_HA (1U << 17) 804 #define SCTLR_BR (1U << 17) /* PMSA only */ 805 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 806 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 807 #define SCTLR_WXN (1U << 19) 808 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 809 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 810 #define SCTLR_FI (1U << 21) 811 #define SCTLR_U (1U << 22) 812 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 813 #define SCTLR_VE (1U << 24) /* up to v7 */ 814 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 815 #define SCTLR_EE (1U << 25) 816 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 817 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 818 #define SCTLR_NMFI (1U << 27) 819 #define SCTLR_TRE (1U << 28) 820 #define SCTLR_AFE (1U << 29) 821 #define SCTLR_TE (1U << 30) 822 823 #define CPTR_TCPAC (1U << 31) 824 #define CPTR_TTA (1U << 20) 825 #define CPTR_TFP (1U << 10) 826 827 #define MDCR_EPMAD (1U << 21) 828 #define MDCR_EDAD (1U << 20) 829 #define MDCR_SPME (1U << 17) 830 #define MDCR_SDD (1U << 16) 831 #define MDCR_SPD (3U << 14) 832 #define MDCR_TDRA (1U << 11) 833 #define MDCR_TDOSA (1U << 10) 834 #define MDCR_TDA (1U << 9) 835 #define MDCR_TDE (1U << 8) 836 #define MDCR_HPME (1U << 7) 837 #define MDCR_TPM (1U << 6) 838 #define MDCR_TPMCR (1U << 5) 839 840 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 841 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 842 843 #define CPSR_M (0x1fU) 844 #define CPSR_T (1U << 5) 845 #define CPSR_F (1U << 6) 846 #define CPSR_I (1U << 7) 847 #define CPSR_A (1U << 8) 848 #define CPSR_E (1U << 9) 849 #define CPSR_IT_2_7 (0xfc00U) 850 #define CPSR_GE (0xfU << 16) 851 #define CPSR_IL (1U << 20) 852 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 853 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 854 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 855 * where it is live state but not accessible to the AArch32 code. 856 */ 857 #define CPSR_RESERVED (0x7U << 21) 858 #define CPSR_J (1U << 24) 859 #define CPSR_IT_0_1 (3U << 25) 860 #define CPSR_Q (1U << 27) 861 #define CPSR_V (1U << 28) 862 #define CPSR_C (1U << 29) 863 #define CPSR_Z (1U << 30) 864 #define CPSR_N (1U << 31) 865 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 866 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 867 868 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 869 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 870 | CPSR_NZCV) 871 /* Bits writable in user mode. */ 872 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 873 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 874 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 875 /* Mask of bits which may be set by exception return copying them from SPSR */ 876 #define CPSR_ERET_MASK (~CPSR_RESERVED) 877 878 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 879 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 880 #define TTBCR_PD0 (1U << 4) 881 #define TTBCR_PD1 (1U << 5) 882 #define TTBCR_EPD0 (1U << 7) 883 #define TTBCR_IRGN0 (3U << 8) 884 #define TTBCR_ORGN0 (3U << 10) 885 #define TTBCR_SH0 (3U << 12) 886 #define TTBCR_T1SZ (3U << 16) 887 #define TTBCR_A1 (1U << 22) 888 #define TTBCR_EPD1 (1U << 23) 889 #define TTBCR_IRGN1 (3U << 24) 890 #define TTBCR_ORGN1 (3U << 26) 891 #define TTBCR_SH1 (1U << 28) 892 #define TTBCR_EAE (1U << 31) 893 894 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 895 * Only these are valid when in AArch64 mode; in 896 * AArch32 mode SPSRs are basically CPSR-format. 897 */ 898 #define PSTATE_SP (1U) 899 #define PSTATE_M (0xFU) 900 #define PSTATE_nRW (1U << 4) 901 #define PSTATE_F (1U << 6) 902 #define PSTATE_I (1U << 7) 903 #define PSTATE_A (1U << 8) 904 #define PSTATE_D (1U << 9) 905 #define PSTATE_IL (1U << 20) 906 #define PSTATE_SS (1U << 21) 907 #define PSTATE_V (1U << 28) 908 #define PSTATE_C (1U << 29) 909 #define PSTATE_Z (1U << 30) 910 #define PSTATE_N (1U << 31) 911 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 912 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 913 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 914 /* Mode values for AArch64 */ 915 #define PSTATE_MODE_EL3h 13 916 #define PSTATE_MODE_EL3t 12 917 #define PSTATE_MODE_EL2h 9 918 #define PSTATE_MODE_EL2t 8 919 #define PSTATE_MODE_EL1h 5 920 #define PSTATE_MODE_EL1t 4 921 #define PSTATE_MODE_EL0t 0 922 923 /* Map EL and handler into a PSTATE_MODE. */ 924 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 925 { 926 return (el << 2) | handler; 927 } 928 929 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 930 * interprocessing, so we don't attempt to sync with the cpsr state used by 931 * the 32 bit decoder. 932 */ 933 static inline uint32_t pstate_read(CPUARMState *env) 934 { 935 int ZF; 936 937 ZF = (env->ZF == 0); 938 return (env->NF & 0x80000000) | (ZF << 30) 939 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 940 | env->pstate | env->daif; 941 } 942 943 static inline void pstate_write(CPUARMState *env, uint32_t val) 944 { 945 env->ZF = (~val) & PSTATE_Z; 946 env->NF = val; 947 env->CF = (val >> 29) & 1; 948 env->VF = (val << 3) & 0x80000000; 949 env->daif = val & PSTATE_DAIF; 950 env->pstate = val & ~CACHED_PSTATE_BITS; 951 } 952 953 /* Return the current CPSR value. */ 954 uint32_t cpsr_read(CPUARMState *env); 955 956 typedef enum CPSRWriteType { 957 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 958 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 959 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 960 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 961 } CPSRWriteType; 962 963 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 964 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 965 CPSRWriteType write_type); 966 967 /* Return the current xPSR value. */ 968 static inline uint32_t xpsr_read(CPUARMState *env) 969 { 970 int ZF; 971 ZF = (env->ZF == 0); 972 return (env->NF & 0x80000000) | (ZF << 30) 973 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 974 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 975 | ((env->condexec_bits & 0xfc) << 8) 976 | env->v7m.exception; 977 } 978 979 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 980 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 981 { 982 if (mask & CPSR_NZCV) { 983 env->ZF = (~val) & CPSR_Z; 984 env->NF = val; 985 env->CF = (val >> 29) & 1; 986 env->VF = (val << 3) & 0x80000000; 987 } 988 if (mask & CPSR_Q) 989 env->QF = ((val & CPSR_Q) != 0); 990 if (mask & (1 << 24)) 991 env->thumb = ((val & (1 << 24)) != 0); 992 if (mask & CPSR_IT_0_1) { 993 env->condexec_bits &= ~3; 994 env->condexec_bits |= (val >> 25) & 3; 995 } 996 if (mask & CPSR_IT_2_7) { 997 env->condexec_bits &= 3; 998 env->condexec_bits |= (val >> 8) & 0xfc; 999 } 1000 if (mask & 0x1ff) { 1001 env->v7m.exception = val & 0x1ff; 1002 } 1003 } 1004 1005 #define HCR_VM (1ULL << 0) 1006 #define HCR_SWIO (1ULL << 1) 1007 #define HCR_PTW (1ULL << 2) 1008 #define HCR_FMO (1ULL << 3) 1009 #define HCR_IMO (1ULL << 4) 1010 #define HCR_AMO (1ULL << 5) 1011 #define HCR_VF (1ULL << 6) 1012 #define HCR_VI (1ULL << 7) 1013 #define HCR_VSE (1ULL << 8) 1014 #define HCR_FB (1ULL << 9) 1015 #define HCR_BSU_MASK (3ULL << 10) 1016 #define HCR_DC (1ULL << 12) 1017 #define HCR_TWI (1ULL << 13) 1018 #define HCR_TWE (1ULL << 14) 1019 #define HCR_TID0 (1ULL << 15) 1020 #define HCR_TID1 (1ULL << 16) 1021 #define HCR_TID2 (1ULL << 17) 1022 #define HCR_TID3 (1ULL << 18) 1023 #define HCR_TSC (1ULL << 19) 1024 #define HCR_TIDCP (1ULL << 20) 1025 #define HCR_TACR (1ULL << 21) 1026 #define HCR_TSW (1ULL << 22) 1027 #define HCR_TPC (1ULL << 23) 1028 #define HCR_TPU (1ULL << 24) 1029 #define HCR_TTLB (1ULL << 25) 1030 #define HCR_TVM (1ULL << 26) 1031 #define HCR_TGE (1ULL << 27) 1032 #define HCR_TDZ (1ULL << 28) 1033 #define HCR_HCD (1ULL << 29) 1034 #define HCR_TRVM (1ULL << 30) 1035 #define HCR_RW (1ULL << 31) 1036 #define HCR_CD (1ULL << 32) 1037 #define HCR_ID (1ULL << 33) 1038 #define HCR_MASK ((1ULL << 34) - 1) 1039 1040 #define SCR_NS (1U << 0) 1041 #define SCR_IRQ (1U << 1) 1042 #define SCR_FIQ (1U << 2) 1043 #define SCR_EA (1U << 3) 1044 #define SCR_FW (1U << 4) 1045 #define SCR_AW (1U << 5) 1046 #define SCR_NET (1U << 6) 1047 #define SCR_SMD (1U << 7) 1048 #define SCR_HCE (1U << 8) 1049 #define SCR_SIF (1U << 9) 1050 #define SCR_RW (1U << 10) 1051 #define SCR_ST (1U << 11) 1052 #define SCR_TWI (1U << 12) 1053 #define SCR_TWE (1U << 13) 1054 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1055 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1056 1057 /* Return the current FPSCR value. */ 1058 uint32_t vfp_get_fpscr(CPUARMState *env); 1059 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1060 1061 /* For A64 the FPSCR is split into two logically distinct registers, 1062 * FPCR and FPSR. However since they still use non-overlapping bits 1063 * we store the underlying state in fpscr and just mask on read/write. 1064 */ 1065 #define FPSR_MASK 0xf800009f 1066 #define FPCR_MASK 0x07f79f00 1067 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1068 { 1069 return vfp_get_fpscr(env) & FPSR_MASK; 1070 } 1071 1072 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1073 { 1074 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1075 vfp_set_fpscr(env, new_fpscr); 1076 } 1077 1078 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1079 { 1080 return vfp_get_fpscr(env) & FPCR_MASK; 1081 } 1082 1083 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1084 { 1085 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1086 vfp_set_fpscr(env, new_fpscr); 1087 } 1088 1089 enum arm_cpu_mode { 1090 ARM_CPU_MODE_USR = 0x10, 1091 ARM_CPU_MODE_FIQ = 0x11, 1092 ARM_CPU_MODE_IRQ = 0x12, 1093 ARM_CPU_MODE_SVC = 0x13, 1094 ARM_CPU_MODE_MON = 0x16, 1095 ARM_CPU_MODE_ABT = 0x17, 1096 ARM_CPU_MODE_HYP = 0x1a, 1097 ARM_CPU_MODE_UND = 0x1b, 1098 ARM_CPU_MODE_SYS = 0x1f 1099 }; 1100 1101 /* VFP system registers. */ 1102 #define ARM_VFP_FPSID 0 1103 #define ARM_VFP_FPSCR 1 1104 #define ARM_VFP_MVFR2 5 1105 #define ARM_VFP_MVFR1 6 1106 #define ARM_VFP_MVFR0 7 1107 #define ARM_VFP_FPEXC 8 1108 #define ARM_VFP_FPINST 9 1109 #define ARM_VFP_FPINST2 10 1110 1111 /* iwMMXt coprocessor control registers. */ 1112 #define ARM_IWMMXT_wCID 0 1113 #define ARM_IWMMXT_wCon 1 1114 #define ARM_IWMMXT_wCSSF 2 1115 #define ARM_IWMMXT_wCASF 3 1116 #define ARM_IWMMXT_wCGR0 8 1117 #define ARM_IWMMXT_wCGR1 9 1118 #define ARM_IWMMXT_wCGR2 10 1119 #define ARM_IWMMXT_wCGR3 11 1120 1121 /* V7M CCR bits */ 1122 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1123 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1124 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1125 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1126 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1127 FIELD(V7M_CCR, STKALIGN, 9, 1) 1128 FIELD(V7M_CCR, DC, 16, 1) 1129 FIELD(V7M_CCR, IC, 17, 1) 1130 1131 /* V7M CFSR bits for MMFSR */ 1132 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1133 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1134 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1135 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1136 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1137 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1138 1139 /* V7M CFSR bits for BFSR */ 1140 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1141 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1142 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1143 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1144 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1145 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1146 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1147 1148 /* V7M CFSR bits for UFSR */ 1149 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1150 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1151 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1152 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1153 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1154 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1155 1156 /* V7M HFSR bits */ 1157 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1158 FIELD(V7M_HFSR, FORCED, 30, 1) 1159 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1160 1161 /* V7M DFSR bits */ 1162 FIELD(V7M_DFSR, HALTED, 0, 1) 1163 FIELD(V7M_DFSR, BKPT, 1, 1) 1164 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1165 FIELD(V7M_DFSR, VCATCH, 3, 1) 1166 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1167 1168 /* If adding a feature bit which corresponds to a Linux ELF 1169 * HWCAP bit, remember to update the feature-bit-to-hwcap 1170 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1171 */ 1172 enum arm_features { 1173 ARM_FEATURE_VFP, 1174 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1175 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1176 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1177 ARM_FEATURE_V6, 1178 ARM_FEATURE_V6K, 1179 ARM_FEATURE_V7, 1180 ARM_FEATURE_THUMB2, 1181 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ 1182 ARM_FEATURE_VFP3, 1183 ARM_FEATURE_VFP_FP16, 1184 ARM_FEATURE_NEON, 1185 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1186 ARM_FEATURE_M, /* Microcontroller profile. */ 1187 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1188 ARM_FEATURE_THUMB2EE, 1189 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1190 ARM_FEATURE_V4T, 1191 ARM_FEATURE_V5, 1192 ARM_FEATURE_STRONGARM, 1193 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1194 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1195 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1196 ARM_FEATURE_GENERIC_TIMER, 1197 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1198 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1199 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1200 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1201 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1202 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1203 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1204 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1205 ARM_FEATURE_V8, 1206 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1207 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1208 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1209 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1210 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1211 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1212 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1213 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1214 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1215 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1216 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1217 ARM_FEATURE_PMU, /* has PMU support */ 1218 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1219 }; 1220 1221 static inline int arm_feature(CPUARMState *env, int feature) 1222 { 1223 return (env->features & (1ULL << feature)) != 0; 1224 } 1225 1226 #if !defined(CONFIG_USER_ONLY) 1227 /* Return true if exception levels below EL3 are in secure state, 1228 * or would be following an exception return to that level. 1229 * Unlike arm_is_secure() (which is always a question about the 1230 * _current_ state of the CPU) this doesn't care about the current 1231 * EL or mode. 1232 */ 1233 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1234 { 1235 if (arm_feature(env, ARM_FEATURE_EL3)) { 1236 return !(env->cp15.scr_el3 & SCR_NS); 1237 } else { 1238 /* If EL3 is not supported then the secure state is implementation 1239 * defined, in which case QEMU defaults to non-secure. 1240 */ 1241 return false; 1242 } 1243 } 1244 1245 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1246 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1247 { 1248 if (arm_feature(env, ARM_FEATURE_EL3)) { 1249 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1250 /* CPU currently in AArch64 state and EL3 */ 1251 return true; 1252 } else if (!is_a64(env) && 1253 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1254 /* CPU currently in AArch32 state and monitor mode */ 1255 return true; 1256 } 1257 } 1258 return false; 1259 } 1260 1261 /* Return true if the processor is in secure state */ 1262 static inline bool arm_is_secure(CPUARMState *env) 1263 { 1264 if (arm_is_el3_or_mon(env)) { 1265 return true; 1266 } 1267 return arm_is_secure_below_el3(env); 1268 } 1269 1270 #else 1271 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1272 { 1273 return false; 1274 } 1275 1276 static inline bool arm_is_secure(CPUARMState *env) 1277 { 1278 return false; 1279 } 1280 #endif 1281 1282 /* Return true if the specified exception level is running in AArch64 state. */ 1283 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1284 { 1285 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1286 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1287 */ 1288 assert(el >= 1 && el <= 3); 1289 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1290 1291 /* The highest exception level is always at the maximum supported 1292 * register width, and then lower levels have a register width controlled 1293 * by bits in the SCR or HCR registers. 1294 */ 1295 if (el == 3) { 1296 return aa64; 1297 } 1298 1299 if (arm_feature(env, ARM_FEATURE_EL3)) { 1300 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1301 } 1302 1303 if (el == 2) { 1304 return aa64; 1305 } 1306 1307 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1308 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1309 } 1310 1311 return aa64; 1312 } 1313 1314 /* Function for determing whether guest cp register reads and writes should 1315 * access the secure or non-secure bank of a cp register. When EL3 is 1316 * operating in AArch32 state, the NS-bit determines whether the secure 1317 * instance of a cp register should be used. When EL3 is AArch64 (or if 1318 * it doesn't exist at all) then there is no register banking, and all 1319 * accesses are to the non-secure version. 1320 */ 1321 static inline bool access_secure_reg(CPUARMState *env) 1322 { 1323 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1324 !arm_el_is_aa64(env, 3) && 1325 !(env->cp15.scr_el3 & SCR_NS)); 1326 1327 return ret; 1328 } 1329 1330 /* Macros for accessing a specified CP register bank */ 1331 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1332 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1333 1334 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1335 do { \ 1336 if (_secure) { \ 1337 (_env)->cp15._regname##_s = (_val); \ 1338 } else { \ 1339 (_env)->cp15._regname##_ns = (_val); \ 1340 } \ 1341 } while (0) 1342 1343 /* Macros for automatically accessing a specific CP register bank depending on 1344 * the current secure state of the system. These macros are not intended for 1345 * supporting instruction translation reads/writes as these are dependent 1346 * solely on the SCR.NS bit and not the mode. 1347 */ 1348 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1349 A32_BANKED_REG_GET((_env), _regname, \ 1350 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1351 1352 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1353 A32_BANKED_REG_SET((_env), _regname, \ 1354 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1355 (_val)) 1356 1357 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1358 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1359 uint32_t cur_el, bool secure); 1360 1361 /* Interface between CPU and Interrupt controller. */ 1362 #ifndef CONFIG_USER_ONLY 1363 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1364 #else 1365 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1366 { 1367 return true; 1368 } 1369 #endif 1370 void armv7m_nvic_set_pending(void *opaque, int irq); 1371 void armv7m_nvic_acknowledge_irq(void *opaque); 1372 /** 1373 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1374 * @opaque: the NVIC 1375 * @irq: the exception number to complete 1376 * 1377 * Returns: -1 if the irq was not active 1378 * 1 if completing this irq brought us back to base (no active irqs) 1379 * 0 if there is still an irq active after this one was completed 1380 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1381 */ 1382 int armv7m_nvic_complete_irq(void *opaque, int irq); 1383 1384 /* Interface for defining coprocessor registers. 1385 * Registers are defined in tables of arm_cp_reginfo structs 1386 * which are passed to define_arm_cp_regs(). 1387 */ 1388 1389 /* When looking up a coprocessor register we look for it 1390 * via an integer which encodes all of: 1391 * coprocessor number 1392 * Crn, Crm, opc1, opc2 fields 1393 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1394 * or via MRRC/MCRR?) 1395 * non-secure/secure bank (AArch32 only) 1396 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1397 * (In this case crn and opc2 should be zero.) 1398 * For AArch64, there is no 32/64 bit size distinction; 1399 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1400 * and 4 bit CRn and CRm. The encoding patterns are chosen 1401 * to be easy to convert to and from the KVM encodings, and also 1402 * so that the hashtable can contain both AArch32 and AArch64 1403 * registers (to allow for interprocessing where we might run 1404 * 32 bit code on a 64 bit core). 1405 */ 1406 /* This bit is private to our hashtable cpreg; in KVM register 1407 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1408 * in the upper bits of the 64 bit ID. 1409 */ 1410 #define CP_REG_AA64_SHIFT 28 1411 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1412 1413 /* To enable banking of coprocessor registers depending on ns-bit we 1414 * add a bit to distinguish between secure and non-secure cpregs in the 1415 * hashtable. 1416 */ 1417 #define CP_REG_NS_SHIFT 29 1418 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1419 1420 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1421 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1422 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1423 1424 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1425 (CP_REG_AA64_MASK | \ 1426 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1427 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1428 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1429 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1430 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1431 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1432 1433 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1434 * version used as a key for the coprocessor register hashtable 1435 */ 1436 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1437 { 1438 uint32_t cpregid = kvmid; 1439 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1440 cpregid |= CP_REG_AA64_MASK; 1441 } else { 1442 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1443 cpregid |= (1 << 15); 1444 } 1445 1446 /* KVM is always non-secure so add the NS flag on AArch32 register 1447 * entries. 1448 */ 1449 cpregid |= 1 << CP_REG_NS_SHIFT; 1450 } 1451 return cpregid; 1452 } 1453 1454 /* Convert a truncated 32 bit hashtable key into the full 1455 * 64 bit KVM register ID. 1456 */ 1457 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1458 { 1459 uint64_t kvmid; 1460 1461 if (cpregid & CP_REG_AA64_MASK) { 1462 kvmid = cpregid & ~CP_REG_AA64_MASK; 1463 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1464 } else { 1465 kvmid = cpregid & ~(1 << 15); 1466 if (cpregid & (1 << 15)) { 1467 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1468 } else { 1469 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1470 } 1471 } 1472 return kvmid; 1473 } 1474 1475 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1476 * special-behaviour cp reg and bits [15..8] indicate what behaviour 1477 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1478 * TCG can assume the value to be constant (ie load at translate time) 1479 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1480 * indicates that the TB should not be ended after a write to this register 1481 * (the default is that the TB ends after cp writes). OVERRIDE permits 1482 * a register definition to override a previous definition for the 1483 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1484 * old must have the OVERRIDE bit set. 1485 * ALIAS indicates that this register is an alias view of some underlying 1486 * state which is also visible via another register, and that the other 1487 * register is handling migration and reset; registers marked ALIAS will not be 1488 * migrated but may have their state set by syncing of register state from KVM. 1489 * NO_RAW indicates that this register has no underlying state and does not 1490 * support raw access for state saving/loading; it will not be used for either 1491 * migration or KVM state synchronization. (Typically this is for "registers" 1492 * which are actually used as instructions for cache maintenance and so on.) 1493 * IO indicates that this register does I/O and therefore its accesses 1494 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1495 * registers which implement clocks or timers require this. 1496 */ 1497 #define ARM_CP_SPECIAL 1 1498 #define ARM_CP_CONST 2 1499 #define ARM_CP_64BIT 4 1500 #define ARM_CP_SUPPRESS_TB_END 8 1501 #define ARM_CP_OVERRIDE 16 1502 #define ARM_CP_ALIAS 32 1503 #define ARM_CP_IO 64 1504 #define ARM_CP_NO_RAW 128 1505 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) 1506 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) 1507 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) 1508 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) 1509 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) 1510 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1511 /* Used only as a terminator for ARMCPRegInfo lists */ 1512 #define ARM_CP_SENTINEL 0xffff 1513 /* Mask of only the flag bits in a type field */ 1514 #define ARM_CP_FLAG_MASK 0xff 1515 1516 /* Valid values for ARMCPRegInfo state field, indicating which of 1517 * the AArch32 and AArch64 execution states this register is visible in. 1518 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1519 * If the reginfo is declared to be visible in both states then a second 1520 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1521 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1522 * Note that we rely on the values of these enums as we iterate through 1523 * the various states in some places. 1524 */ 1525 enum { 1526 ARM_CP_STATE_AA32 = 0, 1527 ARM_CP_STATE_AA64 = 1, 1528 ARM_CP_STATE_BOTH = 2, 1529 }; 1530 1531 /* ARM CP register secure state flags. These flags identify security state 1532 * attributes for a given CP register entry. 1533 * The existence of both or neither secure and non-secure flags indicates that 1534 * the register has both a secure and non-secure hash entry. A single one of 1535 * these flags causes the register to only be hashed for the specified 1536 * security state. 1537 * Although definitions may have any combination of the S/NS bits, each 1538 * registered entry will only have one to identify whether the entry is secure 1539 * or non-secure. 1540 */ 1541 enum { 1542 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1543 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1544 }; 1545 1546 /* Return true if cptype is a valid type field. This is used to try to 1547 * catch errors where the sentinel has been accidentally left off the end 1548 * of a list of registers. 1549 */ 1550 static inline bool cptype_valid(int cptype) 1551 { 1552 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1553 || ((cptype & ARM_CP_SPECIAL) && 1554 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1555 } 1556 1557 /* Access rights: 1558 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1559 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1560 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1561 * (ie any of the privileged modes in Secure state, or Monitor mode). 1562 * If a register is accessible in one privilege level it's always accessible 1563 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1564 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1565 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1566 * terminology a little and call this PL3. 1567 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1568 * with the ELx exception levels. 1569 * 1570 * If access permissions for a register are more complex than can be 1571 * described with these bits, then use a laxer set of restrictions, and 1572 * do the more restrictive/complex check inside a helper function. 1573 */ 1574 #define PL3_R 0x80 1575 #define PL3_W 0x40 1576 #define PL2_R (0x20 | PL3_R) 1577 #define PL2_W (0x10 | PL3_W) 1578 #define PL1_R (0x08 | PL2_R) 1579 #define PL1_W (0x04 | PL2_W) 1580 #define PL0_R (0x02 | PL1_R) 1581 #define PL0_W (0x01 | PL1_W) 1582 1583 #define PL3_RW (PL3_R | PL3_W) 1584 #define PL2_RW (PL2_R | PL2_W) 1585 #define PL1_RW (PL1_R | PL1_W) 1586 #define PL0_RW (PL0_R | PL0_W) 1587 1588 /* Return the highest implemented Exception Level */ 1589 static inline int arm_highest_el(CPUARMState *env) 1590 { 1591 if (arm_feature(env, ARM_FEATURE_EL3)) { 1592 return 3; 1593 } 1594 if (arm_feature(env, ARM_FEATURE_EL2)) { 1595 return 2; 1596 } 1597 return 1; 1598 } 1599 1600 /* Return the current Exception Level (as per ARMv8; note that this differs 1601 * from the ARMv7 Privilege Level). 1602 */ 1603 static inline int arm_current_el(CPUARMState *env) 1604 { 1605 if (arm_feature(env, ARM_FEATURE_M)) { 1606 return !((env->v7m.exception == 0) && (env->v7m.control & 1)); 1607 } 1608 1609 if (is_a64(env)) { 1610 return extract32(env->pstate, 2, 2); 1611 } 1612 1613 switch (env->uncached_cpsr & 0x1f) { 1614 case ARM_CPU_MODE_USR: 1615 return 0; 1616 case ARM_CPU_MODE_HYP: 1617 return 2; 1618 case ARM_CPU_MODE_MON: 1619 return 3; 1620 default: 1621 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1622 /* If EL3 is 32-bit then all secure privileged modes run in 1623 * EL3 1624 */ 1625 return 3; 1626 } 1627 1628 return 1; 1629 } 1630 } 1631 1632 typedef struct ARMCPRegInfo ARMCPRegInfo; 1633 1634 typedef enum CPAccessResult { 1635 /* Access is permitted */ 1636 CP_ACCESS_OK = 0, 1637 /* Access fails due to a configurable trap or enable which would 1638 * result in a categorized exception syndrome giving information about 1639 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1640 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1641 * PL1 if in EL0, otherwise to the current EL). 1642 */ 1643 CP_ACCESS_TRAP = 1, 1644 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1645 * Note that this is not a catch-all case -- the set of cases which may 1646 * result in this failure is specifically defined by the architecture. 1647 */ 1648 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 1649 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 1650 CP_ACCESS_TRAP_EL2 = 3, 1651 CP_ACCESS_TRAP_EL3 = 4, 1652 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 1653 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 1654 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 1655 /* Access fails and results in an exception syndrome for an FP access, 1656 * trapped directly to EL2 or EL3 1657 */ 1658 CP_ACCESS_TRAP_FP_EL2 = 7, 1659 CP_ACCESS_TRAP_FP_EL3 = 8, 1660 } CPAccessResult; 1661 1662 /* Access functions for coprocessor registers. These cannot fail and 1663 * may not raise exceptions. 1664 */ 1665 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1666 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 1667 uint64_t value); 1668 /* Access permission check functions for coprocessor registers. */ 1669 typedef CPAccessResult CPAccessFn(CPUARMState *env, 1670 const ARMCPRegInfo *opaque, 1671 bool isread); 1672 /* Hook function for register reset */ 1673 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1674 1675 #define CP_ANY 0xff 1676 1677 /* Definition of an ARM coprocessor register */ 1678 struct ARMCPRegInfo { 1679 /* Name of register (useful mainly for debugging, need not be unique) */ 1680 const char *name; 1681 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 1682 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 1683 * 'wildcard' field -- any value of that field in the MRC/MCR insn 1684 * will be decoded to this register. The register read and write 1685 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 1686 * used by the program, so it is possible to register a wildcard and 1687 * then behave differently on read/write if necessary. 1688 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 1689 * must both be zero. 1690 * For AArch64-visible registers, opc0 is also used. 1691 * Since there are no "coprocessors" in AArch64, cp is purely used as a 1692 * way to distinguish (for KVM's benefit) guest-visible system registers 1693 * from demuxed ones provided to preserve the "no side effects on 1694 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 1695 * visible (to match KVM's encoding); cp==0 will be converted to 1696 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 1697 */ 1698 uint8_t cp; 1699 uint8_t crn; 1700 uint8_t crm; 1701 uint8_t opc0; 1702 uint8_t opc1; 1703 uint8_t opc2; 1704 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 1705 int state; 1706 /* Register type: ARM_CP_* bits/values */ 1707 int type; 1708 /* Access rights: PL*_[RW] */ 1709 int access; 1710 /* Security state: ARM_CP_SECSTATE_* bits/values */ 1711 int secure; 1712 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 1713 * this register was defined: can be used to hand data through to the 1714 * register read/write functions, since they are passed the ARMCPRegInfo*. 1715 */ 1716 void *opaque; 1717 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 1718 * fieldoffset is non-zero, the reset value of the register. 1719 */ 1720 uint64_t resetvalue; 1721 /* Offset of the field in CPUARMState for this register. 1722 * 1723 * This is not needed if either: 1724 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 1725 * 2. both readfn and writefn are specified 1726 */ 1727 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 1728 1729 /* Offsets of the secure and non-secure fields in CPUARMState for the 1730 * register if it is banked. These fields are only used during the static 1731 * registration of a register. During hashing the bank associated 1732 * with a given security state is copied to fieldoffset which is used from 1733 * there on out. 1734 * 1735 * It is expected that register definitions use either fieldoffset or 1736 * bank_fieldoffsets in the definition but not both. It is also expected 1737 * that both bank offsets are set when defining a banked register. This 1738 * use indicates that a register is banked. 1739 */ 1740 ptrdiff_t bank_fieldoffsets[2]; 1741 1742 /* Function for making any access checks for this register in addition to 1743 * those specified by the 'access' permissions bits. If NULL, no extra 1744 * checks required. The access check is performed at runtime, not at 1745 * translate time. 1746 */ 1747 CPAccessFn *accessfn; 1748 /* Function for handling reads of this register. If NULL, then reads 1749 * will be done by loading from the offset into CPUARMState specified 1750 * by fieldoffset. 1751 */ 1752 CPReadFn *readfn; 1753 /* Function for handling writes of this register. If NULL, then writes 1754 * will be done by writing to the offset into CPUARMState specified 1755 * by fieldoffset. 1756 */ 1757 CPWriteFn *writefn; 1758 /* Function for doing a "raw" read; used when we need to copy 1759 * coprocessor state to the kernel for KVM or out for 1760 * migration. This only needs to be provided if there is also a 1761 * readfn and it has side effects (for instance clear-on-read bits). 1762 */ 1763 CPReadFn *raw_readfn; 1764 /* Function for doing a "raw" write; used when we need to copy KVM 1765 * kernel coprocessor state into userspace, or for inbound 1766 * migration. This only needs to be provided if there is also a 1767 * writefn and it masks out "unwritable" bits or has write-one-to-clear 1768 * or similar behaviour. 1769 */ 1770 CPWriteFn *raw_writefn; 1771 /* Function for resetting the register. If NULL, then reset will be done 1772 * by writing resetvalue to the field specified in fieldoffset. If 1773 * fieldoffset is 0 then no reset will be done. 1774 */ 1775 CPResetFn *resetfn; 1776 }; 1777 1778 /* Macros which are lvalues for the field in CPUARMState for the 1779 * ARMCPRegInfo *ri. 1780 */ 1781 #define CPREG_FIELD32(env, ri) \ 1782 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 1783 #define CPREG_FIELD64(env, ri) \ 1784 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 1785 1786 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 1787 1788 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 1789 const ARMCPRegInfo *regs, void *opaque); 1790 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 1791 const ARMCPRegInfo *regs, void *opaque); 1792 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 1793 { 1794 define_arm_cp_regs_with_opaque(cpu, regs, 0); 1795 } 1796 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 1797 { 1798 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 1799 } 1800 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 1801 1802 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 1803 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 1804 uint64_t value); 1805 /* CPReadFn that can be used for read-as-zero behaviour */ 1806 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 1807 1808 /* CPResetFn that does nothing, for use if no reset is required even 1809 * if fieldoffset is non zero. 1810 */ 1811 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 1812 1813 /* Return true if this reginfo struct's field in the cpu state struct 1814 * is 64 bits wide. 1815 */ 1816 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 1817 { 1818 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 1819 } 1820 1821 static inline bool cp_access_ok(int current_el, 1822 const ARMCPRegInfo *ri, int isread) 1823 { 1824 return (ri->access >> ((current_el * 2) + isread)) & 1; 1825 } 1826 1827 /* Raw read of a coprocessor register (as needed for migration, etc) */ 1828 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 1829 1830 /** 1831 * write_list_to_cpustate 1832 * @cpu: ARMCPU 1833 * 1834 * For each register listed in the ARMCPU cpreg_indexes list, write 1835 * its value from the cpreg_values list into the ARMCPUState structure. 1836 * This updates TCG's working data structures from KVM data or 1837 * from incoming migration state. 1838 * 1839 * Returns: true if all register values were updated correctly, 1840 * false if some register was unknown or could not be written. 1841 * Note that we do not stop early on failure -- we will attempt 1842 * writing all registers in the list. 1843 */ 1844 bool write_list_to_cpustate(ARMCPU *cpu); 1845 1846 /** 1847 * write_cpustate_to_list: 1848 * @cpu: ARMCPU 1849 * 1850 * For each register listed in the ARMCPU cpreg_indexes list, write 1851 * its value from the ARMCPUState structure into the cpreg_values list. 1852 * This is used to copy info from TCG's working data structures into 1853 * KVM or for outbound migration. 1854 * 1855 * Returns: true if all register values were read correctly, 1856 * false if some register was unknown or could not be read. 1857 * Note that we do not stop early on failure -- we will attempt 1858 * reading all registers in the list. 1859 */ 1860 bool write_cpustate_to_list(ARMCPU *cpu); 1861 1862 #define ARM_CPUID_TI915T 0x54029152 1863 #define ARM_CPUID_TI925T 0x54029252 1864 1865 #if defined(CONFIG_USER_ONLY) 1866 #define TARGET_PAGE_BITS 12 1867 #else 1868 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 1869 * have to support 1K tiny pages. 1870 */ 1871 #define TARGET_PAGE_BITS_VARY 1872 #define TARGET_PAGE_BITS_MIN 10 1873 #endif 1874 1875 #if defined(TARGET_AARCH64) 1876 # define TARGET_PHYS_ADDR_SPACE_BITS 48 1877 # define TARGET_VIRT_ADDR_SPACE_BITS 64 1878 #else 1879 # define TARGET_PHYS_ADDR_SPACE_BITS 40 1880 # define TARGET_VIRT_ADDR_SPACE_BITS 32 1881 #endif 1882 1883 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 1884 unsigned int target_el) 1885 { 1886 CPUARMState *env = cs->env_ptr; 1887 unsigned int cur_el = arm_current_el(env); 1888 bool secure = arm_is_secure(env); 1889 bool pstate_unmasked; 1890 int8_t unmasked = 0; 1891 1892 /* Don't take exceptions if they target a lower EL. 1893 * This check should catch any exceptions that would not be taken but left 1894 * pending. 1895 */ 1896 if (cur_el > target_el) { 1897 return false; 1898 } 1899 1900 switch (excp_idx) { 1901 case EXCP_FIQ: 1902 pstate_unmasked = !(env->daif & PSTATE_F); 1903 break; 1904 1905 case EXCP_IRQ: 1906 pstate_unmasked = !(env->daif & PSTATE_I); 1907 break; 1908 1909 case EXCP_VFIQ: 1910 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 1911 /* VFIQs are only taken when hypervized and non-secure. */ 1912 return false; 1913 } 1914 return !(env->daif & PSTATE_F); 1915 case EXCP_VIRQ: 1916 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 1917 /* VIRQs are only taken when hypervized and non-secure. */ 1918 return false; 1919 } 1920 return !(env->daif & PSTATE_I); 1921 default: 1922 g_assert_not_reached(); 1923 } 1924 1925 /* Use the target EL, current execution state and SCR/HCR settings to 1926 * determine whether the corresponding CPSR bit is used to mask the 1927 * interrupt. 1928 */ 1929 if ((target_el > cur_el) && (target_el != 1)) { 1930 /* Exceptions targeting a higher EL may not be maskable */ 1931 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 1932 /* 64-bit masking rules are simple: exceptions to EL3 1933 * can't be masked, and exceptions to EL2 can only be 1934 * masked from Secure state. The HCR and SCR settings 1935 * don't affect the masking logic, only the interrupt routing. 1936 */ 1937 if (target_el == 3 || !secure) { 1938 unmasked = 1; 1939 } 1940 } else { 1941 /* The old 32-bit-only environment has a more complicated 1942 * masking setup. HCR and SCR bits not only affect interrupt 1943 * routing but also change the behaviour of masking. 1944 */ 1945 bool hcr, scr; 1946 1947 switch (excp_idx) { 1948 case EXCP_FIQ: 1949 /* If FIQs are routed to EL3 or EL2 then there are cases where 1950 * we override the CPSR.F in determining if the exception is 1951 * masked or not. If neither of these are set then we fall back 1952 * to the CPSR.F setting otherwise we further assess the state 1953 * below. 1954 */ 1955 hcr = (env->cp15.hcr_el2 & HCR_FMO); 1956 scr = (env->cp15.scr_el3 & SCR_FIQ); 1957 1958 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 1959 * CPSR.F bit masks FIQ interrupts when taken in non-secure 1960 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 1961 * when non-secure but only when FIQs are only routed to EL3. 1962 */ 1963 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 1964 break; 1965 case EXCP_IRQ: 1966 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 1967 * we may override the CPSR.I masking when in non-secure state. 1968 * The SCR.IRQ setting has already been taken into consideration 1969 * when setting the target EL, so it does not have a further 1970 * affect here. 1971 */ 1972 hcr = (env->cp15.hcr_el2 & HCR_IMO); 1973 scr = false; 1974 break; 1975 default: 1976 g_assert_not_reached(); 1977 } 1978 1979 if ((scr || hcr) && !secure) { 1980 unmasked = 1; 1981 } 1982 } 1983 } 1984 1985 /* The PSTATE bits only mask the interrupt if we have not overriden the 1986 * ability above. 1987 */ 1988 return unmasked || pstate_unmasked; 1989 } 1990 1991 #define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model)) 1992 1993 #define cpu_signal_handler cpu_arm_signal_handler 1994 #define cpu_list arm_cpu_list 1995 1996 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 1997 * 1998 * If EL3 is 64-bit: 1999 * + NonSecure EL1 & 0 stage 1 2000 * + NonSecure EL1 & 0 stage 2 2001 * + NonSecure EL2 2002 * + Secure EL1 & EL0 2003 * + Secure EL3 2004 * If EL3 is 32-bit: 2005 * + NonSecure PL1 & 0 stage 1 2006 * + NonSecure PL1 & 0 stage 2 2007 * + NonSecure PL2 2008 * + Secure PL0 & PL1 2009 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2010 * 2011 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2012 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2013 * may differ in access permissions even if the VA->PA map is the same 2014 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2015 * translation, which means that we have one mmu_idx that deals with two 2016 * concatenated translation regimes [this sort of combined s1+2 TLB is 2017 * architecturally permitted] 2018 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2019 * handling via the TLB. The only way to do a stage 1 translation without 2020 * the immediate stage 2 translation is via the ATS or AT system insns, 2021 * which can be slow-pathed and always do a page table walk. 2022 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2023 * translation regimes, because they map reasonably well to each other 2024 * and they can't both be active at the same time. 2025 * This gives us the following list of mmu_idx values: 2026 * 2027 * NS EL0 (aka NS PL0) stage 1+2 2028 * NS EL1 (aka NS PL1) stage 1+2 2029 * NS EL2 (aka NS PL2) 2030 * S EL3 (aka S PL1) 2031 * S EL0 (aka S PL0) 2032 * S EL1 (not used if EL3 is 32 bit) 2033 * NS EL0+1 stage 2 2034 * 2035 * (The last of these is an mmu_idx because we want to be able to use the TLB 2036 * for the accesses done as part of a stage 1 page table walk, rather than 2037 * having to walk the stage 2 page table over and over.) 2038 * 2039 * Our enumeration includes at the end some entries which are not "true" 2040 * mmu_idx values in that they don't have corresponding TLBs and are only 2041 * valid for doing slow path page table walks. 2042 * 2043 * The constant names here are patterned after the general style of the names 2044 * of the AT/ATS operations. 2045 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2046 */ 2047 typedef enum ARMMMUIdx { 2048 ARMMMUIdx_S12NSE0 = 0, 2049 ARMMMUIdx_S12NSE1 = 1, 2050 ARMMMUIdx_S1E2 = 2, 2051 ARMMMUIdx_S1E3 = 3, 2052 ARMMMUIdx_S1SE0 = 4, 2053 ARMMMUIdx_S1SE1 = 5, 2054 ARMMMUIdx_S2NS = 6, 2055 /* Indexes below here don't have TLBs and are used only for AT system 2056 * instructions or for the first stage of an S12 page table walk. 2057 */ 2058 ARMMMUIdx_S1NSE0 = 7, 2059 ARMMMUIdx_S1NSE1 = 8, 2060 } ARMMMUIdx; 2061 2062 #define MMU_USER_IDX 0 2063 2064 /* Return the exception level we're running at if this is our mmu_idx */ 2065 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2066 { 2067 assert(mmu_idx < ARMMMUIdx_S2NS); 2068 return mmu_idx & 3; 2069 } 2070 2071 /* Determine the current mmu_idx to use for normal loads/stores */ 2072 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2073 { 2074 int el = arm_current_el(env); 2075 2076 if (el < 2 && arm_is_secure_below_el3(env)) { 2077 return ARMMMUIdx_S1SE0 + el; 2078 } 2079 return el; 2080 } 2081 2082 /* Indexes used when registering address spaces with cpu_address_space_init */ 2083 typedef enum ARMASIdx { 2084 ARMASIdx_NS = 0, 2085 ARMASIdx_S = 1, 2086 } ARMASIdx; 2087 2088 /* Return the Exception Level targeted by debug exceptions. */ 2089 static inline int arm_debug_target_el(CPUARMState *env) 2090 { 2091 bool secure = arm_is_secure(env); 2092 bool route_to_el2 = false; 2093 2094 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2095 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2096 env->cp15.mdcr_el2 & (1 << 8); 2097 } 2098 2099 if (route_to_el2) { 2100 return 2; 2101 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2102 !arm_el_is_aa64(env, 3) && secure) { 2103 return 3; 2104 } else { 2105 return 1; 2106 } 2107 } 2108 2109 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2110 { 2111 if (arm_is_secure(env)) { 2112 /* MDCR_EL3.SDD disables debug events from Secure state */ 2113 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2114 || arm_current_el(env) == 3) { 2115 return false; 2116 } 2117 } 2118 2119 if (arm_current_el(env) == arm_debug_target_el(env)) { 2120 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2121 || (env->daif & PSTATE_D)) { 2122 return false; 2123 } 2124 } 2125 return true; 2126 } 2127 2128 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2129 { 2130 int el = arm_current_el(env); 2131 2132 if (el == 0 && arm_el_is_aa64(env, 1)) { 2133 return aa64_generate_debug_exceptions(env); 2134 } 2135 2136 if (arm_is_secure(env)) { 2137 int spd; 2138 2139 if (el == 0 && (env->cp15.sder & 1)) { 2140 /* SDER.SUIDEN means debug exceptions from Secure EL0 2141 * are always enabled. Otherwise they are controlled by 2142 * SDCR.SPD like those from other Secure ELs. 2143 */ 2144 return true; 2145 } 2146 2147 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2148 switch (spd) { 2149 case 1: 2150 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2151 case 0: 2152 /* For 0b00 we return true if external secure invasive debug 2153 * is enabled. On real hardware this is controlled by external 2154 * signals to the core. QEMU always permits debug, and behaves 2155 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2156 */ 2157 return true; 2158 case 2: 2159 return false; 2160 case 3: 2161 return true; 2162 } 2163 } 2164 2165 return el != 2; 2166 } 2167 2168 /* Return true if debugging exceptions are currently enabled. 2169 * This corresponds to what in ARM ARM pseudocode would be 2170 * if UsingAArch32() then 2171 * return AArch32.GenerateDebugExceptions() 2172 * else 2173 * return AArch64.GenerateDebugExceptions() 2174 * We choose to push the if() down into this function for clarity, 2175 * since the pseudocode has it at all callsites except for the one in 2176 * CheckSoftwareStep(), where it is elided because both branches would 2177 * always return the same value. 2178 * 2179 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2180 * don't yet implement those exception levels or their associated trap bits. 2181 */ 2182 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2183 { 2184 if (env->aarch64) { 2185 return aa64_generate_debug_exceptions(env); 2186 } else { 2187 return aa32_generate_debug_exceptions(env); 2188 } 2189 } 2190 2191 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2192 * implicitly means this always returns false in pre-v8 CPUs.) 2193 */ 2194 static inline bool arm_singlestep_active(CPUARMState *env) 2195 { 2196 return extract32(env->cp15.mdscr_el1, 0, 1) 2197 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2198 && arm_generate_debug_exceptions(env); 2199 } 2200 2201 static inline bool arm_sctlr_b(CPUARMState *env) 2202 { 2203 return 2204 /* We need not implement SCTLR.ITD in user-mode emulation, so 2205 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2206 * This lets people run BE32 binaries with "-cpu any". 2207 */ 2208 #ifndef CONFIG_USER_ONLY 2209 !arm_feature(env, ARM_FEATURE_V7) && 2210 #endif 2211 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2212 } 2213 2214 /* Return true if the processor is in big-endian mode. */ 2215 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2216 { 2217 int cur_el; 2218 2219 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2220 if (!is_a64(env)) { 2221 return 2222 #ifdef CONFIG_USER_ONLY 2223 /* In system mode, BE32 is modelled in line with the 2224 * architecture (as word-invariant big-endianness), where loads 2225 * and stores are done little endian but from addresses which 2226 * are adjusted by XORing with the appropriate constant. So the 2227 * endianness to use for the raw data access is not affected by 2228 * SCTLR.B. 2229 * In user mode, however, we model BE32 as byte-invariant 2230 * big-endianness (because user-only code cannot tell the 2231 * difference), and so we need to use a data access endianness 2232 * that depends on SCTLR.B. 2233 */ 2234 arm_sctlr_b(env) || 2235 #endif 2236 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2237 } 2238 2239 cur_el = arm_current_el(env); 2240 2241 if (cur_el == 0) { 2242 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2243 } 2244 2245 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2246 } 2247 2248 #include "exec/cpu-all.h" 2249 2250 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2251 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2252 * We put flags which are shared between 32 and 64 bit mode at the top 2253 * of the word, and flags which apply to only one mode at the bottom. 2254 */ 2255 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2256 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2257 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2258 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2259 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2260 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2261 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2262 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2263 /* Target EL if we take a floating-point-disabled exception */ 2264 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2265 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2266 2267 /* Bit usage when in AArch32 state: */ 2268 #define ARM_TBFLAG_THUMB_SHIFT 0 2269 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2270 #define ARM_TBFLAG_VECLEN_SHIFT 1 2271 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2272 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2273 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2274 #define ARM_TBFLAG_VFPEN_SHIFT 7 2275 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2276 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2277 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2278 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2279 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2280 /* We store the bottom two bits of the CPAR as TB flags and handle 2281 * checks on the other bits at runtime 2282 */ 2283 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2284 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2285 /* Indicates whether cp register reads and writes by guest code should access 2286 * the secure or nonsecure bank of banked registers; note that this is not 2287 * the same thing as the current security state of the processor! 2288 */ 2289 #define ARM_TBFLAG_NS_SHIFT 19 2290 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2291 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2292 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2293 2294 /* Bit usage when in AArch64 state */ 2295 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2296 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2297 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2298 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2299 2300 /* some convenience accessor macros */ 2301 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2302 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2303 #define ARM_TBFLAG_MMUIDX(F) \ 2304 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2305 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2306 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2307 #define ARM_TBFLAG_PSTATE_SS(F) \ 2308 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2309 #define ARM_TBFLAG_FPEXC_EL(F) \ 2310 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2311 #define ARM_TBFLAG_THUMB(F) \ 2312 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2313 #define ARM_TBFLAG_VECLEN(F) \ 2314 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2315 #define ARM_TBFLAG_VECSTRIDE(F) \ 2316 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2317 #define ARM_TBFLAG_VFPEN(F) \ 2318 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2319 #define ARM_TBFLAG_CONDEXEC(F) \ 2320 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2321 #define ARM_TBFLAG_SCTLR_B(F) \ 2322 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2323 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2324 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2325 #define ARM_TBFLAG_NS(F) \ 2326 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2327 #define ARM_TBFLAG_BE_DATA(F) \ 2328 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2329 #define ARM_TBFLAG_TBI0(F) \ 2330 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2331 #define ARM_TBFLAG_TBI1(F) \ 2332 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2333 2334 static inline bool bswap_code(bool sctlr_b) 2335 { 2336 #ifdef CONFIG_USER_ONLY 2337 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2338 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2339 * would also end up as a mixed-endian mode with BE code, LE data. 2340 */ 2341 return 2342 #ifdef TARGET_WORDS_BIGENDIAN 2343 1 ^ 2344 #endif 2345 sctlr_b; 2346 #else 2347 /* All code access in ARM is little endian, and there are no loaders 2348 * doing swaps that need to be reversed 2349 */ 2350 return 0; 2351 #endif 2352 } 2353 2354 /* Return the exception level to which FP-disabled exceptions should 2355 * be taken, or 0 if FP is enabled. 2356 */ 2357 static inline int fp_exception_el(CPUARMState *env) 2358 { 2359 int fpen; 2360 int cur_el = arm_current_el(env); 2361 2362 /* CPACR and the CPTR registers don't exist before v6, so FP is 2363 * always accessible 2364 */ 2365 if (!arm_feature(env, ARM_FEATURE_V6)) { 2366 return 0; 2367 } 2368 2369 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: 2370 * 0, 2 : trap EL0 and EL1/PL1 accesses 2371 * 1 : trap only EL0 accesses 2372 * 3 : trap no accesses 2373 */ 2374 fpen = extract32(env->cp15.cpacr_el1, 20, 2); 2375 switch (fpen) { 2376 case 0: 2377 case 2: 2378 if (cur_el == 0 || cur_el == 1) { 2379 /* Trap to PL1, which might be EL1 or EL3 */ 2380 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2381 return 3; 2382 } 2383 return 1; 2384 } 2385 if (cur_el == 3 && !is_a64(env)) { 2386 /* Secure PL1 running at EL3 */ 2387 return 3; 2388 } 2389 break; 2390 case 1: 2391 if (cur_el == 0) { 2392 return 1; 2393 } 2394 break; 2395 case 3: 2396 break; 2397 } 2398 2399 /* For the CPTR registers we don't need to guard with an ARM_FEATURE 2400 * check because zero bits in the registers mean "don't trap". 2401 */ 2402 2403 /* CPTR_EL2 : present in v7VE or v8 */ 2404 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) 2405 && !arm_is_secure_below_el3(env)) { 2406 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ 2407 return 2; 2408 } 2409 2410 /* CPTR_EL3 : present in v8 */ 2411 if (extract32(env->cp15.cptr_el[3], 10, 1)) { 2412 /* Trap all FP ops to EL3 */ 2413 return 3; 2414 } 2415 2416 return 0; 2417 } 2418 2419 #ifdef CONFIG_USER_ONLY 2420 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2421 { 2422 return 2423 #ifdef TARGET_WORDS_BIGENDIAN 2424 1 ^ 2425 #endif 2426 arm_cpu_data_is_big_endian(env); 2427 } 2428 #endif 2429 2430 #ifndef CONFIG_USER_ONLY 2431 /** 2432 * arm_regime_tbi0: 2433 * @env: CPUARMState 2434 * @mmu_idx: MMU index indicating required translation regime 2435 * 2436 * Extracts the TBI0 value from the appropriate TCR for the current EL 2437 * 2438 * Returns: the TBI0 value. 2439 */ 2440 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2441 2442 /** 2443 * arm_regime_tbi1: 2444 * @env: CPUARMState 2445 * @mmu_idx: MMU index indicating required translation regime 2446 * 2447 * Extracts the TBI1 value from the appropriate TCR for the current EL 2448 * 2449 * Returns: the TBI1 value. 2450 */ 2451 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2452 #else 2453 /* We can't handle tagged addresses properly in user-only mode */ 2454 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2455 { 2456 return 0; 2457 } 2458 2459 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2460 { 2461 return 0; 2462 } 2463 #endif 2464 2465 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2466 target_ulong *cs_base, uint32_t *flags) 2467 { 2468 ARMMMUIdx mmu_idx = cpu_mmu_index(env, false); 2469 if (is_a64(env)) { 2470 *pc = env->pc; 2471 *flags = ARM_TBFLAG_AARCH64_STATE_MASK; 2472 /* Get control bits for tagged addresses */ 2473 *flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); 2474 *flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); 2475 } else { 2476 *pc = env->regs[15]; 2477 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) 2478 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) 2479 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) 2480 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) 2481 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); 2482 if (!(access_secure_reg(env))) { 2483 *flags |= ARM_TBFLAG_NS_MASK; 2484 } 2485 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) 2486 || arm_el_is_aa64(env, 1)) { 2487 *flags |= ARM_TBFLAG_VFPEN_MASK; 2488 } 2489 *flags |= (extract32(env->cp15.c15_cpar, 0, 2) 2490 << ARM_TBFLAG_XSCALE_CPAR_SHIFT); 2491 } 2492 2493 *flags |= (mmu_idx << ARM_TBFLAG_MMUIDX_SHIFT); 2494 2495 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine 2496 * states defined in the ARM ARM for software singlestep: 2497 * SS_ACTIVE PSTATE.SS State 2498 * 0 x Inactive (the TB flag for SS is always 0) 2499 * 1 0 Active-pending 2500 * 1 1 Active-not-pending 2501 */ 2502 if (arm_singlestep_active(env)) { 2503 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; 2504 if (is_a64(env)) { 2505 if (env->pstate & PSTATE_SS) { 2506 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2507 } 2508 } else { 2509 if (env->uncached_cpsr & PSTATE_SS) { 2510 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2511 } 2512 } 2513 } 2514 if (arm_cpu_data_is_big_endian(env)) { 2515 *flags |= ARM_TBFLAG_BE_DATA_MASK; 2516 } 2517 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; 2518 2519 *cs_base = 0; 2520 } 2521 2522 enum { 2523 QEMU_PSCI_CONDUIT_DISABLED = 0, 2524 QEMU_PSCI_CONDUIT_SMC = 1, 2525 QEMU_PSCI_CONDUIT_HVC = 2, 2526 }; 2527 2528 #ifndef CONFIG_USER_ONLY 2529 /* Return the address space index to use for a memory access */ 2530 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2531 { 2532 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2533 } 2534 2535 /* Return the AddressSpace to use for a memory access 2536 * (which depends on whether the access is S or NS, and whether 2537 * the board gave us a separate AddressSpace for S accesses). 2538 */ 2539 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2540 { 2541 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2542 } 2543 #endif 2544 2545 /** 2546 * arm_register_el_change_hook: 2547 * Register a hook function which will be called back whenever this 2548 * CPU changes exception level or mode. The hook function will be 2549 * passed a pointer to the ARMCPU and the opaque data pointer passed 2550 * to this function when the hook was registered. 2551 * 2552 * Note that we currently only support registering a single hook function, 2553 * and will assert if this function is called twice. 2554 * This facility is intended for the use of the GICv3 emulation. 2555 */ 2556 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 2557 void *opaque); 2558 2559 /** 2560 * arm_get_el_change_hook_opaque: 2561 * Return the opaque data that will be used by the el_change_hook 2562 * for this CPU. 2563 */ 2564 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) 2565 { 2566 return cpu->el_change_hook_opaque; 2567 } 2568 2569 #endif 2570